drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/pm_runtime.h>
  19
  20 #include <video/exynos5433_decon.h>
  21
  22 #include "exynos_drm_drv.h"
  23 #include "exynos_drm_crtc.h"
  24 #include "exynos_drm_fb.h"
  25 #include "exynos_drm_plane.h"
  26 #include "exynos_drm_iommu.h"
  27
  28 #define WINDOWS_NR      3
  29 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  30
  31 #define IFTYPE_I80      (1 << 0)
  32 #define I80_HW_TRG      (1 << 1)
  33 #define IFTYPE_HDMI     (1 << 2)
  34
  35 static const char * const decon_clks_name[] = {
  36         "pclk",
  37         "aclk_decon",
  38         "aclk_smmu_decon0x",
  39         "aclk_xiu_decon0x",
  40         "pclk_smmu_decon0x",
  41         "sclk_decon_vclk",
  42         "sclk_decon_eclk",
  43 };
  44
  45 enum decon_flag_bits {
  46         BIT_CLKS_ENABLED,
  47         BIT_IRQS_ENABLED,
  48         BIT_WIN_UPDATED,
  49         BIT_SUSPENDED
  50 };
  51
  52 struct decon_context {
  53         struct device                   *dev;
  54         struct drm_device               *drm_dev;
  55         struct exynos_drm_crtc          *crtc;
  56         struct exynos_drm_plane         planes[WINDOWS_NR];
  57         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  58         void __iomem                    *addr;
  59         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  60         int                             pipe;
  61         unsigned long                   flags;
  62         unsigned long                   out_type;
  63         int                             first_win;
  64 };
  65
  66 static const uint32_t decon_formats[] = {
  67         DRM_FORMAT_XRGB1555,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_ARGB8888,
  71 };
  72
  73 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  74         DRM_PLANE_TYPE_PRIMARY,
  75         DRM_PLANE_TYPE_OVERLAY,
  76         DRM_PLANE_TYPE_CURSOR,
  77 };
  78
  79 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  80                                   u32 val)
  81 {
  82         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  83         writel(val, ctx->addr + reg);
  84 }
  85
  86 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  87 {
  88         struct decon_context *ctx = crtc->ctx;
  89         u32 val;
  90
  91         if (test_bit(BIT_SUSPENDED, &ctx->flags))
  92                 return -EPERM;
  93
  94         if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
  95                 val = VIDINTCON0_INTEN;
  96                 if (ctx->out_type & IFTYPE_I80)
  97                         val |= VIDINTCON0_FRAMEDONE;
  98                 else
  99                         val |= VIDINTCON0_INTFRMEN;
 100
 101                 writel(val, ctx->addr + DECON_VIDINTCON0);
 102         }
 103
 104         return 0;
 105 }
 106
 107 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 108 {
 109         struct decon_context *ctx = crtc->ctx;
 110
 111         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 112                 return;
 113
 114         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 115                 writel(0, ctx->addr + DECON_VIDINTCON0);
 116 }
 117
 118 static void decon_setup_trigger(struct decon_context *ctx)
 119 {
 120         u32 val = !(ctx->out_type & I80_HW_TRG)
 121                 ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 122                   TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
 123                 : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 124                   TRIGCON_HWTRIGMASK | TRIGCON_HWTRIGEN;
 125         writel(val, ctx->addr + DECON_TRIGCON);
 126 }
 127
 128 static void decon_commit(struct exynos_drm_crtc *crtc)
 129 {
 130         struct decon_context *ctx = crtc->ctx;
 131         struct drm_display_mode *m = &crtc->base.mode;
 132         u32 val;
 133
 134         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 135                 return;
 136
 137         if (ctx->out_type & IFTYPE_HDMI) {
 138                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 139                 m->crtc_hsync_end = m->crtc_htotal - 92;
 140                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 141                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 142         }
 143
 144         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
 145
 146         /* enable clock gate */
 147         val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
 148         writel(val, ctx->addr + DECON_CMU);
 149
 150         if (ctx->out_type & (IFTYPE_I80 | I80_HW_TRG))
 151                 decon_setup_trigger(ctx);
 152
 153         /* lcd on and use command if */
 154         val = VIDOUT_LCD_ON;
 155         if (ctx->out_type & IFTYPE_I80) {
 156                 val |= VIDOUT_COMMAND_IF;
 157         } else {
 158                 val |= VIDOUT_RGB_IF;
 159         }
 160
 161         writel(val, ctx->addr + DECON_VIDOUTCON0);
 162
 163         val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 164                 VIDTCON2_HOZVAL(m->hdisplay - 1);
 165         writel(val, ctx->addr + DECON_VIDTCON2);
 166
 167         if (!(ctx->out_type & IFTYPE_I80)) {
 168                 val = VIDTCON00_VBPD_F(
 169                                 m->crtc_vtotal - m->crtc_vsync_end - 1) |
 170                         VIDTCON00_VFPD_F(
 171                                 m->crtc_vsync_start - m->crtc_vdisplay - 1);
 172                 writel(val, ctx->addr + DECON_VIDTCON00);
 173
 174                 val = VIDTCON01_VSPW_F(
 175                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 176                 writel(val, ctx->addr + DECON_VIDTCON01);
 177
 178                 val = VIDTCON10_HBPD_F(
 179                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 180                         VIDTCON10_HFPD_F(
 181                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 182                 writel(val, ctx->addr + DECON_VIDTCON10);
 183
 184                 val = VIDTCON11_HSPW_F(
 185                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 186                 writel(val, ctx->addr + DECON_VIDTCON11);
 187         }
 188
 189         /* enable output and display signal */
 190         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 191
 192         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 193 }
 194
 195 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 196                                  struct drm_framebuffer *fb)
 197 {
 198         unsigned long val;
 199
 200         val = readl(ctx->addr + DECON_WINCONx(win));
 201         val &= ~WINCONx_BPPMODE_MASK;
 202
 203         switch (fb->pixel_format) {
 204         case DRM_FORMAT_XRGB1555:
 205                 val |= WINCONx_BPPMODE_16BPP_I1555;
 206                 val |= WINCONx_HAWSWP_F;
 207                 val |= WINCONx_BURSTLEN_16WORD;
 208                 break;
 209         case DRM_FORMAT_RGB565:
 210                 val |= WINCONx_BPPMODE_16BPP_565;
 211                 val |= WINCONx_HAWSWP_F;
 212                 val |= WINCONx_BURSTLEN_16WORD;
 213                 break;
 214         case DRM_FORMAT_XRGB8888:
 215                 val |= WINCONx_BPPMODE_24BPP_888;
 216                 val |= WINCONx_WSWP_F;
 217                 val |= WINCONx_BURSTLEN_16WORD;
 218                 break;
 219         case DRM_FORMAT_ARGB8888:
 220                 val |= WINCONx_BPPMODE_32BPP_A8888;
 221                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 222                 val |= WINCONx_BURSTLEN_16WORD;
 223                 break;
 224         default:
 225                 DRM_ERROR("Proper pixel format is not set\n");
 226                 return;
 227         }
 228
 229         DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel);
 230
 231         /*
 232          * In case of exynos, setting dma-burst to 16Word causes permanent
 233          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 234          * switching which is based on plane size is not recommended as
 235          * plane size varies a lot towards the end of the screen and rapid
 236          * movement causes unstable DMA which results into iommu crash/tear.
 237          */
 238
 239         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 240                 val &= ~WINCONx_BURSTLEN_MASK;
 241                 val |= WINCONx_BURSTLEN_8WORD;
 242         }
 243
 244         writel(val, ctx->addr + DECON_WINCONx(win));
 245 }
 246
 247 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 248                                         bool protect)
 249 {
 250         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
 251                        protect ? ~0 : 0);
 252 }
 253
 254 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 255 {
 256         struct decon_context *ctx = crtc->ctx;
 257         int i;
 258
 259         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 260                 return;
 261
 262         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 263                 decon_shadow_protect_win(ctx, i, true);
 264 }
 265
 266 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 267 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 268 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 269
 270 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 271                                struct exynos_drm_plane *plane)
 272 {
 273         struct exynos_drm_plane_state *state =
 274                                 to_exynos_plane_state(plane->base.state);
 275         struct decon_context *ctx = crtc->ctx;
 276         struct drm_framebuffer *fb = state->base.fb;
 277         unsigned int win = plane->index;
 278         unsigned int bpp = fb->bits_per_pixel >> 3;
 279         unsigned int pitch = fb->pitches[0];
 280         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 281         u32 val;
 282
 283         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 284                 return;
 285
 286         val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 287         writel(val, ctx->addr + DECON_VIDOSDxA(win));
 288
 289         val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 290                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 291         writel(val, ctx->addr + DECON_VIDOSDxB(win));
 292
 293         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 294                 VIDOSD_Wx_ALPHA_B_F(0x0);
 295         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 296
 297         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 298                 VIDOSD_Wx_ALPHA_B_F(0x0);
 299         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 300
 301         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 302
 303         val = dma_addr + pitch * state->src.h;
 304         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 305
 306         if (!(ctx->out_type & IFTYPE_HDMI))
 307                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 308                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 309         else
 310                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 311                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 312         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 313
 314         decon_win_set_pixfmt(ctx, win, fb);
 315
 316         /* window enable */
 317         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 318 }
 319
 320 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 321                                 struct exynos_drm_plane *plane)
 322 {
 323         struct decon_context *ctx = crtc->ctx;
 324         unsigned int win = plane->index;
 325
 326         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 327                 return;
 328
 329         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 330 }
 331
 332 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 333 {
 334         struct decon_context *ctx = crtc->ctx;
 335         int i;
 336
 337         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 338                 return;
 339
 340         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 341                 decon_shadow_protect_win(ctx, i, false);
 342
 343         /* standalone update */
 344         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 345
 346         if (ctx->out_type & IFTYPE_I80)
 347                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 348 }
 349
 350 static void decon_swreset(struct decon_context *ctx)
 351 {
 352         unsigned int tries;
 353
 354         writel(0, ctx->addr + DECON_VIDCON0);
 355         for (tries = 2000; tries; --tries) {
 356                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 357                         break;
 358                 udelay(10);
 359         }
 360
 361         WARN(tries == 0, "failed to disable DECON\n");
 362
 363         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 364         for (tries = 2000; tries; --tries) {
 365                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 366                         break;
 367                 udelay(10);
 368         }
 369
 370         WARN(tries == 0, "failed to software reset DECON\n");
 371
 372         if (!(ctx->out_type & IFTYPE_HDMI))
 373                 return;
 374
 375         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 376         decon_set_bits(ctx, DECON_CMU,
 377                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 378         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 379         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 380                ctx->addr + DECON_CRCCTRL);
 381 }
 382
 383 static void decon_enable(struct exynos_drm_crtc *crtc)
 384 {
 385         struct decon_context *ctx = crtc->ctx;
 386
 387         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 388                 return;
 389
 390         pm_runtime_get_sync(ctx->dev);
 391
 392         exynos_drm_pipe_clk_enable(crtc, true);
 393
 394         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 395
 396         decon_swreset(ctx);
 397
 398         /* if vblank was enabled status, enable it again. */
 399         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 400                 decon_enable_vblank(ctx->crtc);
 401
 402         decon_commit(ctx->crtc);
 403 }
 404
 405 static void decon_disable(struct exynos_drm_crtc *crtc)
 406 {
 407         struct decon_context *ctx = crtc->ctx;
 408         int i;
 409
 410         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 411                 return;
 412
 413         /*
 414          * We need to make sure that all windows are disabled before we
 415          * suspend that connector. Otherwise we might try to scan from
 416          * a destroyed buffer later.
 417          */
 418         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 419                 decon_disable_plane(crtc, &ctx->planes[i]);
 420
 421         decon_swreset(ctx);
 422
 423         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 424
 425         exynos_drm_pipe_clk_enable(crtc, false);
 426
 427         pm_runtime_put_sync(ctx->dev);
 428
 429         set_bit(BIT_SUSPENDED, &ctx->flags);
 430 }
 431
 432 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 433 {
 434         struct decon_context *ctx = crtc->ctx;
 435
 436         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) ||
 437             (ctx->out_type & I80_HW_TRG))
 438                 return;
 439
 440         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
 441                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 442 }
 443
 444 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 445 {
 446         struct decon_context *ctx = crtc->ctx;
 447         int win, i, ret;
 448
 449         DRM_DEBUG_KMS("%s\n", __FILE__);
 450
 451         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 452                 ret = clk_prepare_enable(ctx->clks[i]);
 453                 if (ret < 0)
 454                         goto err;
 455         }
 456
 457         for (win = 0; win < WINDOWS_NR; win++) {
 458                 decon_shadow_protect_win(ctx, win, true);
 459                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 460                 decon_shadow_protect_win(ctx, win, false);
 461         }
 462
 463         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 464
 465         /* TODO: wait for possible vsync */
 466         msleep(50);
 467
 468 err:
 469         while (--i >= 0)
 470                 clk_disable_unprepare(ctx->clks[i]);
 471 }
 472
 473 static struct exynos_drm_crtc_ops decon_crtc_ops = {
 474         .enable                 = decon_enable,
 475         .disable                = decon_disable,
 476         .enable_vblank          = decon_enable_vblank,
 477         .disable_vblank         = decon_disable_vblank,
 478         .atomic_begin           = decon_atomic_begin,
 479         .update_plane           = decon_update_plane,
 480         .disable_plane          = decon_disable_plane,
 481         .atomic_flush           = decon_atomic_flush,
 482         .te_handler             = decon_te_irq_handler,
 483 };
 484
 485 static int decon_bind(struct device *dev, struct device *master, void *data)
 486 {
 487         struct decon_context *ctx = dev_get_drvdata(dev);
 488         struct drm_device *drm_dev = data;
 489         struct exynos_drm_private *priv = drm_dev->dev_private;
 490         struct exynos_drm_plane *exynos_plane;
 491         enum exynos_drm_output_type out_type;
 492         unsigned int win;
 493         int ret;
 494
 495         ctx->drm_dev = drm_dev;
 496         ctx->pipe = priv->pipe++;
 497
 498         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 499                 int tmp = (win == ctx->first_win) ? 0 : win;
 500
 501                 ctx->configs[win].pixel_formats = decon_formats;
 502                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 503                 ctx->configs[win].zpos = win;
 504                 ctx->configs[win].type = decon_win_types[tmp];
 505
 506                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 507                                         1 << ctx->pipe, &ctx->configs[win]);
 508                 if (ret)
 509                         return ret;
 510         }
 511
 512         exynos_plane = &ctx->planes[ctx->first_win];
 513         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 514                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 515         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 516                                         ctx->pipe, out_type,
 517                                         &decon_crtc_ops, ctx);
 518         if (IS_ERR(ctx->crtc)) {
 519                 ret = PTR_ERR(ctx->crtc);
 520                 goto err;
 521         }
 522
 523         decon_clear_channels(ctx->crtc);
 524
 525         ret = drm_iommu_attach_device(drm_dev, dev);
 526         if (ret)
 527                 goto err;
 528
 529         return ret;
 530 err:
 531         priv->pipe--;
 532         return ret;
 533 }
 534
 535 static void decon_unbind(struct device *dev, struct device *master, void *data)
 536 {
 537         struct decon_context *ctx = dev_get_drvdata(dev);
 538
 539         decon_disable(ctx->crtc);
 540
 541         /* detach this sub driver from iommu mapping if supported. */
 542         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 543 }
 544
 545 static const struct component_ops decon_component_ops = {
 546         .bind   = decon_bind,
 547         .unbind = decon_unbind,
 548 };
 549
 550 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 551 {
 552         struct decon_context *ctx = dev_id;
 553         u32 val;
 554
 555         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 556                 goto out;
 557
 558         val = readl(ctx->addr + DECON_VIDINTCON1);
 559         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 560
 561         if (val) {
 562                 writel(val, ctx->addr + DECON_VIDINTCON1);
 563                 drm_crtc_handle_vblank(&ctx->crtc->base);
 564         }
 565
 566 out:
 567         return IRQ_HANDLED;
 568 }
 569
 570 #ifdef CONFIG_PM
 571 static int exynos5433_decon_suspend(struct device *dev)
 572 {
 573         struct decon_context *ctx = dev_get_drvdata(dev);
 574         int i = ARRAY_SIZE(decon_clks_name);
 575
 576         while (--i >= 0)
 577                 clk_disable_unprepare(ctx->clks[i]);
 578
 579         return 0;
 580 }
 581
 582 static int exynos5433_decon_resume(struct device *dev)
 583 {
 584         struct decon_context *ctx = dev_get_drvdata(dev);
 585         int i, ret;
 586
 587         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 588                 ret = clk_prepare_enable(ctx->clks[i]);
 589                 if (ret < 0)
 590                         goto err;
 591         }
 592
 593         return 0;
 594
 595 err:
 596         while (--i >= 0)
 597                 clk_disable_unprepare(ctx->clks[i]);
 598
 599         return ret;
 600 }
 601 #endif
 602
 603 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 604         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 605                            NULL)
 606 };
 607
 608 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 609         {
 610                 .compatible = "samsung,exynos5433-decon",
 611                 .data = (void *)I80_HW_TRG
 612         },
 613         {
 614                 .compatible = "samsung,exynos5433-decon-tv",
 615                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 616         },
 617         {},
 618 };
 619 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 620
 621 static int exynos5433_decon_probe(struct platform_device *pdev)
 622 {
 623         struct device *dev = &pdev->dev;
 624         struct decon_context *ctx;
 625         struct resource *res;
 626         int ret;
 627         int i;
 628
 629         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 630         if (!ctx)
 631                 return -ENOMEM;
 632
 633         __set_bit(BIT_SUSPENDED, &ctx->flags);
 634         ctx->dev = dev;
 635         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 636
 637         if (ctx->out_type & IFTYPE_HDMI) {
 638                 ctx->first_win = 1;
 639         } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
 640                 ctx->out_type |= IFTYPE_I80;
 641         }
 642
 643         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 644                 struct clk *clk;
 645
 646                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 647                 if (IS_ERR(clk))
 648                         return PTR_ERR(clk);
 649
 650                 ctx->clks[i] = clk;
 651         }
 652
 653         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 654         if (!res) {
 655                 dev_err(dev, "cannot find IO resource\n");
 656                 return -ENXIO;
 657         }
 658
 659         ctx->addr = devm_ioremap_resource(dev, res);
 660         if (IS_ERR(ctx->addr)) {
 661                 dev_err(dev, "ioremap failed\n");
 662                 return PTR_ERR(ctx->addr);
 663         }
 664
 665         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 666                         (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync");
 667         if (!res) {
 668                 dev_err(dev, "cannot find IRQ resource\n");
 669                 return -ENXIO;
 670         }
 671
 672         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 673                                "drm_decon", ctx);
 674         if (ret < 0) {
 675                 dev_err(dev, "lcd_sys irq request failed\n");
 676                 return ret;
 677         }
 678
 679         platform_set_drvdata(pdev, ctx);
 680
 681         pm_runtime_enable(dev);
 682
 683         ret = component_add(dev, &decon_component_ops);
 684         if (ret)
 685                 goto err_disable_pm_runtime;
 686
 687         return 0;
 688
 689 err_disable_pm_runtime:
 690         pm_runtime_disable(dev);
 691
 692         return ret;
 693 }
 694
 695 static int exynos5433_decon_remove(struct platform_device *pdev)
 696 {
 697         pm_runtime_disable(&pdev->dev);
 698
 699         component_del(&pdev->dev, &decon_component_ops);
 700
 701         return 0;
 702 }
 703
 704 struct platform_driver exynos5433_decon_driver = {
 705         .probe          = exynos5433_decon_probe,
 706         .remove         = exynos5433_decon_remove,
 707         .driver         = {
 708                 .name   = "exynos5433-decon",
 709                 .pm     = &exynos5433_decon_pm_ops,
 710                 .of_match_table = exynos5433_decon_driver_dt_match,
 711         },
 712 };