drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (i915_gem_obj_is_pinned(obj))
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct i915_vma *vma;
 124         int pin_count = 0;
 125
 126         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
 127                    &obj->base,
 128                    get_pin_flag(obj),
 129                    get_tiling_flag(obj),
 130                    get_global_flag(obj),
 131                    obj->base.size / 1024,
 132                    obj->base.read_domains,
 133                    obj->base.write_domain,
 134                    i915_gem_request_get_seqno(obj->last_read_req),
 135                    i915_gem_request_get_seqno(obj->last_write_req),
 136                    i915_gem_request_get_seqno(obj->last_fenced_req),
 137                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 138                    obj->dirty ? " dirty" : "",
 139                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 140         if (obj->base.name)
 141                 seq_printf(m, " (name: %d)", obj->base.name);
 142         list_for_each_entry(vma, &obj->vma_list, vma_link)
 143                 if (vma->pin_count > 0)
 144                         pin_count++;
 145                 seq_printf(m, " (pinned x %d)", pin_count);
 146         if (obj->pin_display)
 147                 seq_printf(m, " (display)");
 148         if (obj->fence_reg != I915_FENCE_REG_NONE)
 149                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 150         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 151                 if (!i915_is_ggtt(vma->vm))
 152                         seq_puts(m, " (pp");
 153                 else
 154                         seq_puts(m, " (g");
 155                 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
 156                            vma->node.start, vma->node.size,
 157                            vma->ggtt_view.type);
 158         }
 159         if (obj->stolen)
 160                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 161         if (obj->pin_mappable || obj->fault_mappable) {
 162                 char s[3], *t = s;
 163                 if (obj->pin_mappable)
 164                         *t++ = 'p';
 165                 if (obj->fault_mappable)
 166                         *t++ = 'f';
 167                 *t = '\0';
 168                 seq_printf(m, " (%s mappable)", s);
 169         }
 170         if (obj->last_read_req != NULL)
 171                 seq_printf(m, " (%s)",
 172                            i915_gem_request_get_ring(obj->last_read_req)->name);
 173         if (obj->frontbuffer_bits)
 174                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 175 }
 176
 177 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 178 {
 179         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 180         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 181         seq_putc(m, ' ');
 182 }
 183
 184 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 185 {
 186         struct drm_info_node *node = m->private;
 187         uintptr_t list = (uintptr_t) node->info_ent->data;
 188         struct list_head *head;
 189         struct drm_device *dev = node->minor->dev;
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         struct i915_address_space *vm = &dev_priv->gtt.base;
 192         struct i915_vma *vma;
 193         size_t total_obj_size, total_gtt_size;
 194         int count, ret;
 195
 196         ret = mutex_lock_interruptible(&dev->struct_mutex);
 197         if (ret)
 198                 return ret;
 199
 200         /* FIXME: the user of this interface might want more than just GGTT */
 201         switch (list) {
 202         case ACTIVE_LIST:
 203                 seq_puts(m, "Active:\n");
 204                 head = &vm->active_list;
 205                 break;
 206         case INACTIVE_LIST:
 207                 seq_puts(m, "Inactive:\n");
 208                 head = &vm->inactive_list;
 209                 break;
 210         default:
 211                 mutex_unlock(&dev->struct_mutex);
 212                 return -EINVAL;
 213         }
 214
 215         total_obj_size = total_gtt_size = count = 0;
 216         list_for_each_entry(vma, head, mm_list) {
 217                 seq_printf(m, "   ");
 218                 describe_obj(m, vma->obj);
 219                 seq_printf(m, "\n");
 220                 total_obj_size += vma->obj->base.size;
 221                 total_gtt_size += vma->node.size;
 222                 count++;
 223         }
 224         mutex_unlock(&dev->struct_mutex);
 225
 226         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 227                    count, total_obj_size, total_gtt_size);
 228         return 0;
 229 }
 230
 231 static int obj_rank_by_stolen(void *priv,
 232                               struct list_head *A, struct list_head *B)
 233 {
 234         struct drm_i915_gem_object *a =
 235                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 236         struct drm_i915_gem_object *b =
 237                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 238
 239         return a->stolen->start - b->stolen->start;
 240 }
 241
 242 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 243 {
 244         struct drm_info_node *node = m->private;
 245         struct drm_device *dev = node->minor->dev;
 246         struct drm_i915_private *dev_priv = dev->dev_private;
 247         struct drm_i915_gem_object *obj;
 248         size_t total_obj_size, total_gtt_size;
 249         LIST_HEAD(stolen);
 250         int count, ret;
 251
 252         ret = mutex_lock_interruptible(&dev->struct_mutex);
 253         if (ret)
 254                 return ret;
 255
 256         total_obj_size = total_gtt_size = count = 0;
 257         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 258                 if (obj->stolen == NULL)
 259                         continue;
 260
 261                 list_add(&obj->obj_exec_link, &stolen);
 262
 263                 total_obj_size += obj->base.size;
 264                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 265                 count++;
 266         }
 267         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 268                 if (obj->stolen == NULL)
 269                         continue;
 270
 271                 list_add(&obj->obj_exec_link, &stolen);
 272
 273                 total_obj_size += obj->base.size;
 274                 count++;
 275         }
 276         list_sort(NULL, &stolen, obj_rank_by_stolen);
 277         seq_puts(m, "Stolen:\n");
 278         while (!list_empty(&stolen)) {
 279                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 280                 seq_puts(m, "   ");
 281                 describe_obj(m, obj);
 282                 seq_putc(m, '\n');
 283                 list_del_init(&obj->obj_exec_link);
 284         }
 285         mutex_unlock(&dev->struct_mutex);
 286
 287         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 288                    count, total_obj_size, total_gtt_size);
 289         return 0;
 290 }
 291
 292 #define count_objects(list, member) do { \
 293         list_for_each_entry(obj, list, member) { \
 294                 size += i915_gem_obj_ggtt_size(obj); \
 295                 ++count; \
 296                 if (obj->map_and_fenceable) { \
 297                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 298                         ++mappable_count; \
 299                 } \
 300         } \
 301 } while (0)
 302
 303 struct file_stats {
 304         struct drm_i915_file_private *file_priv;
 305         int count;
 306         size_t total, unbound;
 307         size_t global, shared;
 308         size_t active, inactive;
 309 };
 310
 311 static int per_file_stats(int id, void *ptr, void *data)
 312 {
 313         struct drm_i915_gem_object *obj = ptr;
 314         struct file_stats *stats = data;
 315         struct i915_vma *vma;
 316
 317         stats->count++;
 318         stats->total += obj->base.size;
 319
 320         if (obj->base.name || obj->base.dma_buf)
 321                 stats->shared += obj->base.size;
 322
 323         if (USES_FULL_PPGTT(obj->base.dev)) {
 324                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 325                         struct i915_hw_ppgtt *ppgtt;
 326
 327                         if (!drm_mm_node_allocated(&vma->node))
 328                                 continue;
 329
 330                         if (i915_is_ggtt(vma->vm)) {
 331                                 stats->global += obj->base.size;
 332                                 continue;
 333                         }
 334
 335                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 336                         if (ppgtt->file_priv != stats->file_priv)
 337                                 continue;
 338
 339                         if (obj->active) /* XXX per-vma statistic */
 340                                 stats->active += obj->base.size;
 341                         else
 342                                 stats->inactive += obj->base.size;
 343
 344                         return 0;
 345                 }
 346         } else {
 347                 if (i915_gem_obj_ggtt_bound(obj)) {
 348                         stats->global += obj->base.size;
 349                         if (obj->active)
 350                                 stats->active += obj->base.size;
 351                         else
 352                                 stats->inactive += obj->base.size;
 353                         return 0;
 354                 }
 355         }
 356
 357         if (!list_empty(&obj->global_list))
 358                 stats->unbound += obj->base.size;
 359
 360         return 0;
 361 }
 362
 363 #define print_file_stats(m, name, stats) \
 364         seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
 365                    name, \
 366                    stats.count, \
 367                    stats.total, \
 368                    stats.active, \
 369                    stats.inactive, \
 370                    stats.global, \
 371                    stats.shared, \
 372                    stats.unbound)
 373
 374 static void print_batch_pool_stats(struct seq_file *m,
 375                                    struct drm_i915_private *dev_priv)
 376 {
 377         struct drm_i915_gem_object *obj;
 378         struct file_stats stats;
 379
 380         memset(&stats, 0, sizeof(stats));
 381
 382         list_for_each_entry(obj,
 383                             &dev_priv->mm.batch_pool.cache_list,
 384                             batch_pool_list)
 385                 per_file_stats(0, obj, &stats);
 386
 387         print_file_stats(m, "batch pool", stats);
 388 }
 389
 390 #define count_vmas(list, member) do { \
 391         list_for_each_entry(vma, list, member) { \
 392                 size += i915_gem_obj_ggtt_size(vma->obj); \
 393                 ++count; \
 394                 if (vma->obj->map_and_fenceable) { \
 395                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 396                         ++mappable_count; \
 397                 } \
 398         } \
 399 } while (0)
 400
 401 static int i915_gem_object_info(struct seq_file *m, void* data)
 402 {
 403         struct drm_info_node *node = m->private;
 404         struct drm_device *dev = node->minor->dev;
 405         struct drm_i915_private *dev_priv = dev->dev_private;
 406         u32 count, mappable_count, purgeable_count;
 407         size_t size, mappable_size, purgeable_size;
 408         struct drm_i915_gem_object *obj;
 409         struct i915_address_space *vm = &dev_priv->gtt.base;
 410         struct drm_file *file;
 411         struct i915_vma *vma;
 412         int ret;
 413
 414         ret = mutex_lock_interruptible(&dev->struct_mutex);
 415         if (ret)
 416                 return ret;
 417
 418         seq_printf(m, "%u objects, %zu bytes\n",
 419                    dev_priv->mm.object_count,
 420                    dev_priv->mm.object_memory);
 421
 422         size = count = mappable_size = mappable_count = 0;
 423         count_objects(&dev_priv->mm.bound_list, global_list);
 424         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 425                    count, mappable_count, size, mappable_size);
 426
 427         size = count = mappable_size = mappable_count = 0;
 428         count_vmas(&vm->active_list, mm_list);
 429         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 430                    count, mappable_count, size, mappable_size);
 431
 432         size = count = mappable_size = mappable_count = 0;
 433         count_vmas(&vm->inactive_list, mm_list);
 434         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 435                    count, mappable_count, size, mappable_size);
 436
 437         size = count = purgeable_size = purgeable_count = 0;
 438         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 439                 size += obj->base.size, ++count;
 440                 if (obj->madv == I915_MADV_DONTNEED)
 441                         purgeable_size += obj->base.size, ++purgeable_count;
 442         }
 443         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 444
 445         size = count = mappable_size = mappable_count = 0;
 446         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 447                 if (obj->fault_mappable) {
 448                         size += i915_gem_obj_ggtt_size(obj);
 449                         ++count;
 450                 }
 451                 if (obj->pin_mappable) {
 452                         mappable_size += i915_gem_obj_ggtt_size(obj);
 453                         ++mappable_count;
 454                 }
 455                 if (obj->madv == I915_MADV_DONTNEED) {
 456                         purgeable_size += obj->base.size;
 457                         ++purgeable_count;
 458                 }
 459         }
 460         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 461                    purgeable_count, purgeable_size);
 462         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 463                    mappable_count, mappable_size);
 464         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 465                    count, size);
 466
 467         seq_printf(m, "%zu [%lu] gtt total\n",
 468                    dev_priv->gtt.base.total,
 469                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 470
 471         seq_putc(m, '\n');
 472         print_batch_pool_stats(m, dev_priv);
 473
 474         seq_putc(m, '\n');
 475         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 476                 struct file_stats stats;
 477                 struct task_struct *task;
 478
 479                 memset(&stats, 0, sizeof(stats));
 480                 stats.file_priv = file->driver_priv;
 481                 spin_lock(&file->table_lock);
 482                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 483                 spin_unlock(&file->table_lock);
 484                 /*
 485                  * Although we have a valid reference on file->pid, that does
 486                  * not guarantee that the task_struct who called get_pid() is
 487                  * still alive (e.g. get_pid(current) => fork() => exit()).
 488                  * Therefore, we need to protect this ->comm access using RCU.
 489                  */
 490                 rcu_read_lock();
 491                 task = pid_task(file->pid, PIDTYPE_PID);
 492                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 493                 rcu_read_unlock();
 494         }
 495
 496         mutex_unlock(&dev->struct_mutex);
 497
 498         return 0;
 499 }
 500
 501 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 502 {
 503         struct drm_info_node *node = m->private;
 504         struct drm_device *dev = node->minor->dev;
 505         uintptr_t list = (uintptr_t) node->info_ent->data;
 506         struct drm_i915_private *dev_priv = dev->dev_private;
 507         struct drm_i915_gem_object *obj;
 508         size_t total_obj_size, total_gtt_size;
 509         int count, ret;
 510
 511         ret = mutex_lock_interruptible(&dev->struct_mutex);
 512         if (ret)
 513                 return ret;
 514
 515         total_obj_size = total_gtt_size = count = 0;
 516         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 517                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 518                         continue;
 519
 520                 seq_puts(m, "   ");
 521                 describe_obj(m, obj);
 522                 seq_putc(m, '\n');
 523                 total_obj_size += obj->base.size;
 524                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 525                 count++;
 526         }
 527
 528         mutex_unlock(&dev->struct_mutex);
 529
 530         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 531                    count, total_obj_size, total_gtt_size);
 532
 533         return 0;
 534 }
 535
 536 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 537 {
 538         struct drm_info_node *node = m->private;
 539         struct drm_device *dev = node->minor->dev;
 540         struct drm_i915_private *dev_priv = dev->dev_private;
 541         struct intel_crtc *crtc;
 542         int ret;
 543
 544         ret = mutex_lock_interruptible(&dev->struct_mutex);
 545         if (ret)
 546                 return ret;
 547
 548         for_each_intel_crtc(dev, crtc) {
 549                 const char pipe = pipe_name(crtc->pipe);
 550                 const char plane = plane_name(crtc->plane);
 551                 struct intel_unpin_work *work;
 552
 553                 spin_lock_irq(&dev->event_lock);
 554                 work = crtc->unpin_work;
 555                 if (work == NULL) {
 556                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 557                                    pipe, plane);
 558                 } else {
 559                         u32 addr;
 560
 561                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 562                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 563                                            pipe, plane);
 564                         } else {
 565                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 566                                            pipe, plane);
 567                         }
 568                         if (work->flip_queued_req) {
 569                                 struct intel_engine_cs *ring =
 570                                         i915_gem_request_get_ring(work->flip_queued_req);
 571
 572                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 573                                            ring->name,
 574                                            i915_gem_request_get_seqno(work->flip_queued_req),
 575                                            dev_priv->next_seqno,
 576                                            ring->get_seqno(ring, true),
 577                                            i915_gem_request_completed(work->flip_queued_req, true));
 578                         } else
 579                                 seq_printf(m, "Flip not associated with any ring\n");
 580                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 581                                    work->flip_queued_vblank,
 582                                    work->flip_ready_vblank,
 583                                    drm_vblank_count(dev, crtc->pipe));
 584                         if (work->enable_stall_check)
 585                                 seq_puts(m, "Stall check enabled, ");
 586                         else
 587                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 588                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 589
 590                         if (INTEL_INFO(dev)->gen >= 4)
 591                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 592                         else
 593                                 addr = I915_READ(DSPADDR(crtc->plane));
 594                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 595
 596                         if (work->pending_flip_obj) {
 597                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 598                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 599                         }
 600                 }
 601                 spin_unlock_irq(&dev->event_lock);
 602         }
 603
 604         mutex_unlock(&dev->struct_mutex);
 605
 606         return 0;
 607 }
 608
 609 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 610 {
 611         struct drm_info_node *node = m->private;
 612         struct drm_device *dev = node->minor->dev;
 613         struct drm_i915_private *dev_priv = dev->dev_private;
 614         struct drm_i915_gem_object *obj;
 615         int count = 0;
 616         int ret;
 617
 618         ret = mutex_lock_interruptible(&dev->struct_mutex);
 619         if (ret)
 620                 return ret;
 621
 622         seq_puts(m, "cache:\n");
 623         list_for_each_entry(obj,
 624                             &dev_priv->mm.batch_pool.cache_list,
 625                             batch_pool_list) {
 626                 seq_puts(m, "   ");
 627                 describe_obj(m, obj);
 628                 seq_putc(m, '\n');
 629                 count++;
 630         }
 631
 632         seq_printf(m, "total: %d\n", count);
 633
 634         mutex_unlock(&dev->struct_mutex);
 635
 636         return 0;
 637 }
 638
 639 static int i915_gem_request_info(struct seq_file *m, void *data)
 640 {
 641         struct drm_info_node *node = m->private;
 642         struct drm_device *dev = node->minor->dev;
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         struct intel_engine_cs *ring;
 645         struct drm_i915_gem_request *gem_request;
 646         int ret, count, i;
 647
 648         ret = mutex_lock_interruptible(&dev->struct_mutex);
 649         if (ret)
 650                 return ret;
 651
 652         count = 0;
 653         for_each_ring(ring, dev_priv, i) {
 654                 if (list_empty(&ring->request_list))
 655                         continue;
 656
 657                 seq_printf(m, "%s requests:\n", ring->name);
 658                 list_for_each_entry(gem_request,
 659                                     &ring->request_list,
 660                                     list) {
 661                         seq_printf(m, "    %x @ %d\n",
 662                                    gem_request->seqno,
 663                                    (int) (jiffies - gem_request->emitted_jiffies));
 664                 }
 665                 count++;
 666         }
 667         mutex_unlock(&dev->struct_mutex);
 668
 669         if (count == 0)
 670                 seq_puts(m, "No requests\n");
 671
 672         return 0;
 673 }
 674
 675 static void i915_ring_seqno_info(struct seq_file *m,
 676                                  struct intel_engine_cs *ring)
 677 {
 678         if (ring->get_seqno) {
 679                 seq_printf(m, "Current sequence (%s): %x\n",
 680                            ring->name, ring->get_seqno(ring, false));
 681         }
 682 }
 683
 684 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 685 {
 686         struct drm_info_node *node = m->private;
 687         struct drm_device *dev = node->minor->dev;
 688         struct drm_i915_private *dev_priv = dev->dev_private;
 689         struct intel_engine_cs *ring;
 690         int ret, i;
 691
 692         ret = mutex_lock_interruptible(&dev->struct_mutex);
 693         if (ret)
 694                 return ret;
 695         intel_runtime_pm_get(dev_priv);
 696
 697         for_each_ring(ring, dev_priv, i)
 698                 i915_ring_seqno_info(m, ring);
 699
 700         intel_runtime_pm_put(dev_priv);
 701         mutex_unlock(&dev->struct_mutex);
 702
 703         return 0;
 704 }
 705
 706
 707 static int i915_interrupt_info(struct seq_file *m, void *data)
 708 {
 709         struct drm_info_node *node = m->private;
 710         struct drm_device *dev = node->minor->dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         struct intel_engine_cs *ring;
 713         int ret, i, pipe;
 714
 715         ret = mutex_lock_interruptible(&dev->struct_mutex);
 716         if (ret)
 717                 return ret;
 718         intel_runtime_pm_get(dev_priv);
 719
 720         if (IS_CHERRYVIEW(dev)) {
 721                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 722                            I915_READ(GEN8_MASTER_IRQ));
 723
 724                 seq_printf(m, "Display IER:\t%08x\n",
 725                            I915_READ(VLV_IER));
 726                 seq_printf(m, "Display IIR:\t%08x\n",
 727                            I915_READ(VLV_IIR));
 728                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 729                            I915_READ(VLV_IIR_RW));
 730                 seq_printf(m, "Display IMR:\t%08x\n",
 731                            I915_READ(VLV_IMR));
 732                 for_each_pipe(dev_priv, pipe)
 733                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 734                                    pipe_name(pipe),
 735                                    I915_READ(PIPESTAT(pipe)));
 736
 737                 seq_printf(m, "Port hotplug:\t%08x\n",
 738                            I915_READ(PORT_HOTPLUG_EN));
 739                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 740                            I915_READ(VLV_DPFLIPSTAT));
 741                 seq_printf(m, "DPINVGTT:\t%08x\n",
 742                            I915_READ(DPINVGTT));
 743
 744                 for (i = 0; i < 4; i++) {
 745                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 746                                    i, I915_READ(GEN8_GT_IMR(i)));
 747                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 748                                    i, I915_READ(GEN8_GT_IIR(i)));
 749                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 750                                    i, I915_READ(GEN8_GT_IER(i)));
 751                 }
 752
 753                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 754                            I915_READ(GEN8_PCU_IMR));
 755                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 756                            I915_READ(GEN8_PCU_IIR));
 757                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 758                            I915_READ(GEN8_PCU_IER));
 759         } else if (INTEL_INFO(dev)->gen >= 8) {
 760                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 761                            I915_READ(GEN8_MASTER_IRQ));
 762
 763                 for (i = 0; i < 4; i++) {
 764                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 765                                    i, I915_READ(GEN8_GT_IMR(i)));
 766                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 767                                    i, I915_READ(GEN8_GT_IIR(i)));
 768                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 769                                    i, I915_READ(GEN8_GT_IER(i)));
 770                 }
 771
 772                 for_each_pipe(dev_priv, pipe) {
 773                         if (!intel_display_power_is_enabled(dev_priv,
 774                                                 POWER_DOMAIN_PIPE(pipe))) {
 775                                 seq_printf(m, "Pipe %c power disabled\n",
 776                                            pipe_name(pipe));
 777                                 continue;
 778                         }
 779                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 780                                    pipe_name(pipe),
 781                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 782                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 783                                    pipe_name(pipe),
 784                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 785                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 786                                    pipe_name(pipe),
 787                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 788                 }
 789
 790                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 791                            I915_READ(GEN8_DE_PORT_IMR));
 792                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 793                            I915_READ(GEN8_DE_PORT_IIR));
 794                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 795                            I915_READ(GEN8_DE_PORT_IER));
 796
 797                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 798                            I915_READ(GEN8_DE_MISC_IMR));
 799                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 800                            I915_READ(GEN8_DE_MISC_IIR));
 801                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 802                            I915_READ(GEN8_DE_MISC_IER));
 803
 804                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 805                            I915_READ(GEN8_PCU_IMR));
 806                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 807                            I915_READ(GEN8_PCU_IIR));
 808                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IER));
 810         } else if (IS_VALLEYVIEW(dev)) {
 811                 seq_printf(m, "Display IER:\t%08x\n",
 812                            I915_READ(VLV_IER));
 813                 seq_printf(m, "Display IIR:\t%08x\n",
 814                            I915_READ(VLV_IIR));
 815                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 816                            I915_READ(VLV_IIR_RW));
 817                 seq_printf(m, "Display IMR:\t%08x\n",
 818                            I915_READ(VLV_IMR));
 819                 for_each_pipe(dev_priv, pipe)
 820                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 821                                    pipe_name(pipe),
 822                                    I915_READ(PIPESTAT(pipe)));
 823
 824                 seq_printf(m, "Master IER:\t%08x\n",
 825                            I915_READ(VLV_MASTER_IER));
 826
 827                 seq_printf(m, "Render IER:\t%08x\n",
 828                            I915_READ(GTIER));
 829                 seq_printf(m, "Render IIR:\t%08x\n",
 830                            I915_READ(GTIIR));
 831                 seq_printf(m, "Render IMR:\t%08x\n",
 832                            I915_READ(GTIMR));
 833
 834                 seq_printf(m, "PM IER:\t\t%08x\n",
 835                            I915_READ(GEN6_PMIER));
 836                 seq_printf(m, "PM IIR:\t\t%08x\n",
 837                            I915_READ(GEN6_PMIIR));
 838                 seq_printf(m, "PM IMR:\t\t%08x\n",
 839                            I915_READ(GEN6_PMIMR));
 840
 841                 seq_printf(m, "Port hotplug:\t%08x\n",
 842                            I915_READ(PORT_HOTPLUG_EN));
 843                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 844                            I915_READ(VLV_DPFLIPSTAT));
 845                 seq_printf(m, "DPINVGTT:\t%08x\n",
 846                            I915_READ(DPINVGTT));
 847
 848         } else if (!HAS_PCH_SPLIT(dev)) {
 849                 seq_printf(m, "Interrupt enable:    %08x\n",
 850                            I915_READ(IER));
 851                 seq_printf(m, "Interrupt identity:  %08x\n",
 852                            I915_READ(IIR));
 853                 seq_printf(m, "Interrupt mask:      %08x\n",
 854                            I915_READ(IMR));
 855                 for_each_pipe(dev_priv, pipe)
 856                         seq_printf(m, "Pipe %c stat:         %08x\n",
 857                                    pipe_name(pipe),
 858                                    I915_READ(PIPESTAT(pipe)));
 859         } else {
 860                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 861                            I915_READ(DEIER));
 862                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 863                            I915_READ(DEIIR));
 864                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 865                            I915_READ(DEIMR));
 866                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 867                            I915_READ(SDEIER));
 868                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 869                            I915_READ(SDEIIR));
 870                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 871                            I915_READ(SDEIMR));
 872                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 873                            I915_READ(GTIER));
 874                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 875                            I915_READ(GTIIR));
 876                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 877                            I915_READ(GTIMR));
 878         }
 879         for_each_ring(ring, dev_priv, i) {
 880                 if (INTEL_INFO(dev)->gen >= 6) {
 881                         seq_printf(m,
 882                                    "Graphics Interrupt mask (%s):       %08x\n",
 883                                    ring->name, I915_READ_IMR(ring));
 884                 }
 885                 i915_ring_seqno_info(m, ring);
 886         }
 887         intel_runtime_pm_put(dev_priv);
 888         mutex_unlock(&dev->struct_mutex);
 889
 890         return 0;
 891 }
 892
 893 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 894 {
 895         struct drm_info_node *node = m->private;
 896         struct drm_device *dev = node->minor->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898         int i, ret;
 899
 900         ret = mutex_lock_interruptible(&dev->struct_mutex);
 901         if (ret)
 902                 return ret;
 903
 904         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 905         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 906         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 907                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 908
 909                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 910                            i, dev_priv->fence_regs[i].pin_count);
 911                 if (obj == NULL)
 912                         seq_puts(m, "unused");
 913                 else
 914                         describe_obj(m, obj);
 915                 seq_putc(m, '\n');
 916         }
 917
 918         mutex_unlock(&dev->struct_mutex);
 919         return 0;
 920 }
 921
 922 static int i915_hws_info(struct seq_file *m, void *data)
 923 {
 924         struct drm_info_node *node = m->private;
 925         struct drm_device *dev = node->minor->dev;
 926         struct drm_i915_private *dev_priv = dev->dev_private;
 927         struct intel_engine_cs *ring;
 928         const u32 *hws;
 929         int i;
 930
 931         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 932         hws = ring->status_page.page_addr;
 933         if (hws == NULL)
 934                 return 0;
 935
 936         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 937                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 938                            i * 4,
 939                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 940         }
 941         return 0;
 942 }
 943
 944 static ssize_t
 945 i915_error_state_write(struct file *filp,
 946                        const char __user *ubuf,
 947                        size_t cnt,
 948                        loff_t *ppos)
 949 {
 950         struct i915_error_state_file_priv *error_priv = filp->private_data;
 951         struct drm_device *dev = error_priv->dev;
 952         int ret;
 953
 954         DRM_DEBUG_DRIVER("Resetting error state\n");
 955
 956         ret = mutex_lock_interruptible(&dev->struct_mutex);
 957         if (ret)
 958                 return ret;
 959
 960         i915_destroy_error_state(dev);
 961         mutex_unlock(&dev->struct_mutex);
 962
 963         return cnt;
 964 }
 965
 966 static int i915_error_state_open(struct inode *inode, struct file *file)
 967 {
 968         struct drm_device *dev = inode->i_private;
 969         struct i915_error_state_file_priv *error_priv;
 970
 971         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 972         if (!error_priv)
 973                 return -ENOMEM;
 974
 975         error_priv->dev = dev;
 976
 977         i915_error_state_get(dev, error_priv);
 978
 979         file->private_data = error_priv;
 980
 981         return 0;
 982 }
 983
 984 static int i915_error_state_release(struct inode *inode, struct file *file)
 985 {
 986         struct i915_error_state_file_priv *error_priv = file->private_data;
 987
 988         i915_error_state_put(error_priv);
 989         kfree(error_priv);
 990
 991         return 0;
 992 }
 993
 994 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 995                                      size_t count, loff_t *pos)
 996 {
 997         struct i915_error_state_file_priv *error_priv = file->private_data;
 998         struct drm_i915_error_state_buf error_str;
 999         loff_t tmp_pos = 0;
1000         ssize_t ret_count = 0;
1001         int ret;
1002
1003         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1004         if (ret)
1005                 return ret;
1006
1007         ret = i915_error_state_to_str(&error_str, error_priv);
1008         if (ret)
1009                 goto out;
1010
1011         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1012                                             error_str.buf,
1013                                             error_str.bytes);
1014
1015         if (ret_count < 0)
1016                 ret = ret_count;
1017         else
1018                 *pos = error_str.start + ret_count;
1019 out:
1020         i915_error_state_buf_release(&error_str);
1021         return ret ?: ret_count;
1022 }
1023
1024 static const struct file_operations i915_error_state_fops = {
1025         .owner = THIS_MODULE,
1026         .open = i915_error_state_open,
1027         .read = i915_error_state_read,
1028         .write = i915_error_state_write,
1029         .llseek = default_llseek,
1030         .release = i915_error_state_release,
1031 };
1032
1033 static int
1034 i915_next_seqno_get(void *data, u64 *val)
1035 {
1036         struct drm_device *dev = data;
1037         struct drm_i915_private *dev_priv = dev->dev_private;
1038         int ret;
1039
1040         ret = mutex_lock_interruptible(&dev->struct_mutex);
1041         if (ret)
1042                 return ret;
1043
1044         *val = dev_priv->next_seqno;
1045         mutex_unlock(&dev->struct_mutex);
1046
1047         return 0;
1048 }
1049
1050 static int
1051 i915_next_seqno_set(void *data, u64 val)
1052 {
1053         struct drm_device *dev = data;
1054         int ret;
1055
1056         ret = mutex_lock_interruptible(&dev->struct_mutex);
1057         if (ret)
1058                 return ret;
1059
1060         ret = i915_gem_set_seqno(dev, val);
1061         mutex_unlock(&dev->struct_mutex);
1062
1063         return ret;
1064 }
1065
1066 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1067                         i915_next_seqno_get, i915_next_seqno_set,
1068                         "0x%llx\n");
1069
1070 static int i915_frequency_info(struct seq_file *m, void *unused)
1071 {
1072         struct drm_info_node *node = m->private;
1073         struct drm_device *dev = node->minor->dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         int ret = 0;
1076
1077         intel_runtime_pm_get(dev_priv);
1078
1079         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1080
1081         if (IS_GEN5(dev)) {
1082                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1083                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1084
1085                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1086                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1087                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1088                            MEMSTAT_VID_SHIFT);
1089                 seq_printf(m, "Current P-state: %d\n",
1090                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1091         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1092                    IS_BROADWELL(dev)) {
1093                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1094                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1095                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1096                 u32 rpmodectl, rpinclimit, rpdeclimit;
1097                 u32 rpstat, cagf, reqf;
1098                 u32 rpupei, rpcurup, rpprevup;
1099                 u32 rpdownei, rpcurdown, rpprevdown;
1100                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1101                 int max_freq;
1102
1103                 /* RPSTAT1 is in the GT power well */
1104                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1105                 if (ret)
1106                         goto out;
1107
1108                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1109
1110                 reqf = I915_READ(GEN6_RPNSWREQ);
1111                 reqf &= ~GEN6_TURBO_DISABLE;
1112                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1113                         reqf >>= 24;
1114                 else
1115                         reqf >>= 25;
1116                 reqf = intel_gpu_freq(dev_priv, reqf);
1117
1118                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1119                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1120                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1121
1122                 rpstat = I915_READ(GEN6_RPSTAT1);
1123                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1124                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1125                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1126                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1127                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1128                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1129                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1130                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1131                 else
1132                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1133                 cagf = intel_gpu_freq(dev_priv, cagf);
1134
1135                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1136                 mutex_unlock(&dev->struct_mutex);
1137
1138                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1139                         pm_ier = I915_READ(GEN6_PMIER);
1140                         pm_imr = I915_READ(GEN6_PMIMR);
1141                         pm_isr = I915_READ(GEN6_PMISR);
1142                         pm_iir = I915_READ(GEN6_PMIIR);
1143                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1144                 } else {
1145                         pm_ier = I915_READ(GEN8_GT_IER(2));
1146                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1147                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1148                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1149                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1150                 }
1151                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1152                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1153                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1154                 seq_printf(m, "Render p-state ratio: %d\n",
1155                            (gt_perf_status & 0xff00) >> 8);
1156                 seq_printf(m, "Render p-state VID: %d\n",
1157                            gt_perf_status & 0xff);
1158                 seq_printf(m, "Render p-state limit: %d\n",
1159                            rp_state_limits & 0xff);
1160                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1161                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1162                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1163                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1164                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1165                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1166                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1167                            GEN6_CURICONT_MASK);
1168                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1169                            GEN6_CURBSYTAVG_MASK);
1170                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1171                            GEN6_CURBSYTAVG_MASK);
1172                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1173                            GEN6_CURIAVG_MASK);
1174                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1175                            GEN6_CURBSYTAVG_MASK);
1176                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1177                            GEN6_CURBSYTAVG_MASK);
1178
1179                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1180                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1181                            intel_gpu_freq(dev_priv, max_freq));
1182
1183                 max_freq = (rp_state_cap & 0xff00) >> 8;
1184                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1185                            intel_gpu_freq(dev_priv, max_freq));
1186
1187                 max_freq = rp_state_cap & 0xff;
1188                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1189                            intel_gpu_freq(dev_priv, max_freq));
1190
1191                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1192                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1193         } else if (IS_VALLEYVIEW(dev)) {
1194                 u32 freq_sts;
1195
1196                 mutex_lock(&dev_priv->rps.hw_lock);
1197                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1198                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1199                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1200
1201                 seq_printf(m, "max GPU freq: %d MHz\n",
1202                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1203
1204                 seq_printf(m, "min GPU freq: %d MHz\n",
1205                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1206
1207                 seq_printf(m,
1208                            "efficient (RPe) frequency: %d MHz\n",
1209                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1210
1211                 seq_printf(m, "current GPU freq: %d MHz\n",
1212                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1213                 mutex_unlock(&dev_priv->rps.hw_lock);
1214         } else {
1215                 seq_puts(m, "no P-state info available\n");
1216         }
1217
1218 out:
1219         intel_runtime_pm_put(dev_priv);
1220         return ret;
1221 }
1222
1223 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1224 {
1225         struct drm_info_node *node = m->private;
1226         struct drm_device *dev = node->minor->dev;
1227         struct drm_i915_private *dev_priv = dev->dev_private;
1228         struct intel_engine_cs *ring;
1229         u64 acthd[I915_NUM_RINGS];
1230         u32 seqno[I915_NUM_RINGS];
1231         int i;
1232
1233         if (!i915.enable_hangcheck) {
1234                 seq_printf(m, "Hangcheck disabled\n");
1235                 return 0;
1236         }
1237
1238         intel_runtime_pm_get(dev_priv);
1239
1240         for_each_ring(ring, dev_priv, i) {
1241                 seqno[i] = ring->get_seqno(ring, false);
1242                 acthd[i] = intel_ring_get_active_head(ring);
1243         }
1244
1245         intel_runtime_pm_put(dev_priv);
1246
1247         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1248                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1249                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1250                                             jiffies));
1251         } else
1252                 seq_printf(m, "Hangcheck inactive\n");
1253
1254         for_each_ring(ring, dev_priv, i) {
1255                 seq_printf(m, "%s:\n", ring->name);
1256                 seq_printf(m, "\tseqno = %x [current %x]\n",
1257                            ring->hangcheck.seqno, seqno[i]);
1258                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1259                            (long long)ring->hangcheck.acthd,
1260                            (long long)acthd[i]);
1261                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1262                            (long long)ring->hangcheck.max_acthd);
1263                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1264                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1265         }
1266
1267         return 0;
1268 }
1269
1270 static int ironlake_drpc_info(struct seq_file *m)
1271 {
1272         struct drm_info_node *node = m->private;
1273         struct drm_device *dev = node->minor->dev;
1274         struct drm_i915_private *dev_priv = dev->dev_private;
1275         u32 rgvmodectl, rstdbyctl;
1276         u16 crstandvid;
1277         int ret;
1278
1279         ret = mutex_lock_interruptible(&dev->struct_mutex);
1280         if (ret)
1281                 return ret;
1282         intel_runtime_pm_get(dev_priv);
1283
1284         rgvmodectl = I915_READ(MEMMODECTL);
1285         rstdbyctl = I915_READ(RSTDBYCTL);
1286         crstandvid = I915_READ16(CRSTANDVID);
1287
1288         intel_runtime_pm_put(dev_priv);
1289         mutex_unlock(&dev->struct_mutex);
1290
1291         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1292                    "yes" : "no");
1293         seq_printf(m, "Boost freq: %d\n",
1294                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1295                    MEMMODE_BOOST_FREQ_SHIFT);
1296         seq_printf(m, "HW control enabled: %s\n",
1297                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1298         seq_printf(m, "SW control enabled: %s\n",
1299                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1300         seq_printf(m, "Gated voltage change: %s\n",
1301                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1302         seq_printf(m, "Starting frequency: P%d\n",
1303                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1304         seq_printf(m, "Max P-state: P%d\n",
1305                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1306         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1307         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1308         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1309         seq_printf(m, "Render standby enabled: %s\n",
1310                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1311         seq_puts(m, "Current RS state: ");
1312         switch (rstdbyctl & RSX_STATUS_MASK) {
1313         case RSX_STATUS_ON:
1314                 seq_puts(m, "on\n");
1315                 break;
1316         case RSX_STATUS_RC1:
1317                 seq_puts(m, "RC1\n");
1318                 break;
1319         case RSX_STATUS_RC1E:
1320                 seq_puts(m, "RC1E\n");
1321                 break;
1322         case RSX_STATUS_RS1:
1323                 seq_puts(m, "RS1\n");
1324                 break;
1325         case RSX_STATUS_RS2:
1326                 seq_puts(m, "RS2 (RC6)\n");
1327                 break;
1328         case RSX_STATUS_RS3:
1329                 seq_puts(m, "RC3 (RC6+)\n");
1330                 break;
1331         default:
1332                 seq_puts(m, "unknown\n");
1333                 break;
1334         }
1335
1336         return 0;
1337 }
1338
1339 static int i915_forcewake_domains(struct seq_file *m, void *data)
1340 {
1341         struct drm_info_node *node = m->private;
1342         struct drm_device *dev = node->minor->dev;
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         struct intel_uncore_forcewake_domain *fw_domain;
1345         int i;
1346
1347         spin_lock_irq(&dev_priv->uncore.lock);
1348         for_each_fw_domain(fw_domain, dev_priv, i) {
1349                 seq_printf(m, "%s.wake_count = %u\n",
1350                            intel_uncore_forcewake_domain_to_str(i),
1351                            fw_domain->wake_count);
1352         }
1353         spin_unlock_irq(&dev_priv->uncore.lock);
1354
1355         return 0;
1356 }
1357
1358 static int vlv_drpc_info(struct seq_file *m)
1359 {
1360         struct drm_info_node *node = m->private;
1361         struct drm_device *dev = node->minor->dev;
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363         u32 rpmodectl1, rcctl1, pw_status;
1364
1365         intel_runtime_pm_get(dev_priv);
1366
1367         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1368         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1369         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1370
1371         intel_runtime_pm_put(dev_priv);
1372
1373         seq_printf(m, "Video Turbo Mode: %s\n",
1374                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1375         seq_printf(m, "Turbo enabled: %s\n",
1376                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1377         seq_printf(m, "HW control enabled: %s\n",
1378                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1379         seq_printf(m, "SW control enabled: %s\n",
1380                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1381                           GEN6_RP_MEDIA_SW_MODE));
1382         seq_printf(m, "RC6 Enabled: %s\n",
1383                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1384                                         GEN6_RC_CTL_EI_MODE(1))));
1385         seq_printf(m, "Render Power Well: %s\n",
1386                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1387         seq_printf(m, "Media Power Well: %s\n",
1388                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1389
1390         seq_printf(m, "Render RC6 residency since boot: %u\n",
1391                    I915_READ(VLV_GT_RENDER_RC6));
1392         seq_printf(m, "Media RC6 residency since boot: %u\n",
1393                    I915_READ(VLV_GT_MEDIA_RC6));
1394
1395         return i915_forcewake_domains(m, NULL);
1396 }
1397
1398 static int gen6_drpc_info(struct seq_file *m)
1399 {
1400         struct drm_info_node *node = m->private;
1401         struct drm_device *dev = node->minor->dev;
1402         struct drm_i915_private *dev_priv = dev->dev_private;
1403         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1404         unsigned forcewake_count;
1405         int count = 0, ret;
1406
1407         ret = mutex_lock_interruptible(&dev->struct_mutex);
1408         if (ret)
1409                 return ret;
1410         intel_runtime_pm_get(dev_priv);
1411
1412         spin_lock_irq(&dev_priv->uncore.lock);
1413         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1414         spin_unlock_irq(&dev_priv->uncore.lock);
1415
1416         if (forcewake_count) {
1417                 seq_puts(m, "RC information inaccurate because somebody "
1418                             "holds a forcewake reference \n");
1419         } else {
1420                 /* NB: we cannot use forcewake, else we read the wrong values */
1421                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1422                         udelay(10);
1423                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1424         }
1425
1426         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1427         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1428
1429         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1430         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1431         mutex_unlock(&dev->struct_mutex);
1432         mutex_lock(&dev_priv->rps.hw_lock);
1433         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1434         mutex_unlock(&dev_priv->rps.hw_lock);
1435
1436         intel_runtime_pm_put(dev_priv);
1437
1438         seq_printf(m, "Video Turbo Mode: %s\n",
1439                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1440         seq_printf(m, "HW control enabled: %s\n",
1441                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1442         seq_printf(m, "SW control enabled: %s\n",
1443                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1444                           GEN6_RP_MEDIA_SW_MODE));
1445         seq_printf(m, "RC1e Enabled: %s\n",
1446                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1447         seq_printf(m, "RC6 Enabled: %s\n",
1448                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1449         seq_printf(m, "Deep RC6 Enabled: %s\n",
1450                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1451         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1452                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1453         seq_puts(m, "Current RC state: ");
1454         switch (gt_core_status & GEN6_RCn_MASK) {
1455         case GEN6_RC0:
1456                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1457                         seq_puts(m, "Core Power Down\n");
1458                 else
1459                         seq_puts(m, "on\n");
1460                 break;
1461         case GEN6_RC3:
1462                 seq_puts(m, "RC3\n");
1463                 break;
1464         case GEN6_RC6:
1465                 seq_puts(m, "RC6\n");
1466                 break;
1467         case GEN6_RC7:
1468                 seq_puts(m, "RC7\n");
1469                 break;
1470         default:
1471                 seq_puts(m, "Unknown\n");
1472                 break;
1473         }
1474
1475         seq_printf(m, "Core Power Down: %s\n",
1476                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1477
1478         /* Not exactly sure what this is */
1479         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1480                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1481         seq_printf(m, "RC6 residency since boot: %u\n",
1482                    I915_READ(GEN6_GT_GFX_RC6));
1483         seq_printf(m, "RC6+ residency since boot: %u\n",
1484                    I915_READ(GEN6_GT_GFX_RC6p));
1485         seq_printf(m, "RC6++ residency since boot: %u\n",
1486                    I915_READ(GEN6_GT_GFX_RC6pp));
1487
1488         seq_printf(m, "RC6   voltage: %dmV\n",
1489                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1490         seq_printf(m, "RC6+  voltage: %dmV\n",
1491                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1492         seq_printf(m, "RC6++ voltage: %dmV\n",
1493                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1494         return 0;
1495 }
1496
1497 static int i915_drpc_info(struct seq_file *m, void *unused)
1498 {
1499         struct drm_info_node *node = m->private;
1500         struct drm_device *dev = node->minor->dev;
1501
1502         if (IS_VALLEYVIEW(dev))
1503                 return vlv_drpc_info(m);
1504         else if (INTEL_INFO(dev)->gen >= 6)
1505                 return gen6_drpc_info(m);
1506         else
1507                 return ironlake_drpc_info(m);
1508 }
1509
1510 static int i915_fbc_status(struct seq_file *m, void *unused)
1511 {
1512         struct drm_info_node *node = m->private;
1513         struct drm_device *dev = node->minor->dev;
1514         struct drm_i915_private *dev_priv = dev->dev_private;
1515
1516         if (!HAS_FBC(dev)) {
1517                 seq_puts(m, "FBC unsupported on this chipset\n");
1518                 return 0;
1519         }
1520
1521         intel_runtime_pm_get(dev_priv);
1522
1523         if (intel_fbc_enabled(dev)) {
1524                 seq_puts(m, "FBC enabled\n");
1525         } else {
1526                 seq_puts(m, "FBC disabled: ");
1527                 switch (dev_priv->fbc.no_fbc_reason) {
1528                 case FBC_OK:
1529                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1530                         break;
1531                 case FBC_UNSUPPORTED:
1532                         seq_puts(m, "unsupported by this chipset");
1533                         break;
1534                 case FBC_NO_OUTPUT:
1535                         seq_puts(m, "no outputs");
1536                         break;
1537                 case FBC_STOLEN_TOO_SMALL:
1538                         seq_puts(m, "not enough stolen memory");
1539                         break;
1540                 case FBC_UNSUPPORTED_MODE:
1541                         seq_puts(m, "mode not supported");
1542                         break;
1543                 case FBC_MODE_TOO_LARGE:
1544                         seq_puts(m, "mode too large");
1545                         break;
1546                 case FBC_BAD_PLANE:
1547                         seq_puts(m, "FBC unsupported on plane");
1548                         break;
1549                 case FBC_NOT_TILED:
1550                         seq_puts(m, "scanout buffer not tiled");
1551                         break;
1552                 case FBC_MULTIPLE_PIPES:
1553                         seq_puts(m, "multiple pipes are enabled");
1554                         break;
1555                 case FBC_MODULE_PARAM:
1556                         seq_puts(m, "disabled per module param (default off)");
1557                         break;
1558                 case FBC_CHIP_DEFAULT:
1559                         seq_puts(m, "disabled per chip default");
1560                         break;
1561                 default:
1562                         seq_puts(m, "unknown reason");
1563                 }
1564                 seq_putc(m, '\n');
1565         }
1566
1567         intel_runtime_pm_put(dev_priv);
1568
1569         return 0;
1570 }
1571
1572 static int i915_fbc_fc_get(void *data, u64 *val)
1573 {
1574         struct drm_device *dev = data;
1575         struct drm_i915_private *dev_priv = dev->dev_private;
1576
1577         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1578                 return -ENODEV;
1579
1580         drm_modeset_lock_all(dev);
1581         *val = dev_priv->fbc.false_color;
1582         drm_modeset_unlock_all(dev);
1583
1584         return 0;
1585 }
1586
1587 static int i915_fbc_fc_set(void *data, u64 val)
1588 {
1589         struct drm_device *dev = data;
1590         struct drm_i915_private *dev_priv = dev->dev_private;
1591         u32 reg;
1592
1593         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1594                 return -ENODEV;
1595
1596         drm_modeset_lock_all(dev);
1597
1598         reg = I915_READ(ILK_DPFC_CONTROL);
1599         dev_priv->fbc.false_color = val;
1600
1601         I915_WRITE(ILK_DPFC_CONTROL, val ?
1602                    (reg | FBC_CTL_FALSE_COLOR) :
1603                    (reg & ~FBC_CTL_FALSE_COLOR));
1604
1605         drm_modeset_unlock_all(dev);
1606         return 0;
1607 }
1608
1609 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1610                         i915_fbc_fc_get, i915_fbc_fc_set,
1611                         "%llu\n");
1612
1613 static int i915_ips_status(struct seq_file *m, void *unused)
1614 {
1615         struct drm_info_node *node = m->private;
1616         struct drm_device *dev = node->minor->dev;
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618
1619         if (!HAS_IPS(dev)) {
1620                 seq_puts(m, "not supported\n");
1621                 return 0;
1622         }
1623
1624         intel_runtime_pm_get(dev_priv);
1625
1626         seq_printf(m, "Enabled by kernel parameter: %s\n",
1627                    yesno(i915.enable_ips));
1628
1629         if (INTEL_INFO(dev)->gen >= 8) {
1630                 seq_puts(m, "Currently: unknown\n");
1631         } else {
1632                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1633                         seq_puts(m, "Currently: enabled\n");
1634                 else
1635                         seq_puts(m, "Currently: disabled\n");
1636         }
1637
1638         intel_runtime_pm_put(dev_priv);
1639
1640         return 0;
1641 }
1642
1643 static int i915_sr_status(struct seq_file *m, void *unused)
1644 {
1645         struct drm_info_node *node = m->private;
1646         struct drm_device *dev = node->minor->dev;
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         bool sr_enabled = false;
1649
1650         intel_runtime_pm_get(dev_priv);
1651
1652         if (HAS_PCH_SPLIT(dev))
1653                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1654         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1655                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1656         else if (IS_I915GM(dev))
1657                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1658         else if (IS_PINEVIEW(dev))
1659                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1660
1661         intel_runtime_pm_put(dev_priv);
1662
1663         seq_printf(m, "self-refresh: %s\n",
1664                    sr_enabled ? "enabled" : "disabled");
1665
1666         return 0;
1667 }
1668
1669 static int i915_emon_status(struct seq_file *m, void *unused)
1670 {
1671         struct drm_info_node *node = m->private;
1672         struct drm_device *dev = node->minor->dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         unsigned long temp, chipset, gfx;
1675         int ret;
1676
1677         if (!IS_GEN5(dev))
1678                 return -ENODEV;
1679
1680         ret = mutex_lock_interruptible(&dev->struct_mutex);
1681         if (ret)
1682                 return ret;
1683
1684         temp = i915_mch_val(dev_priv);
1685         chipset = i915_chipset_val(dev_priv);
1686         gfx = i915_gfx_val(dev_priv);
1687         mutex_unlock(&dev->struct_mutex);
1688
1689         seq_printf(m, "GMCH temp: %ld\n", temp);
1690         seq_printf(m, "Chipset power: %ld\n", chipset);
1691         seq_printf(m, "GFX power: %ld\n", gfx);
1692         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1693
1694         return 0;
1695 }
1696
1697 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1698 {
1699         struct drm_info_node *node = m->private;
1700         struct drm_device *dev = node->minor->dev;
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702         int ret = 0;
1703         int gpu_freq, ia_freq;
1704
1705         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1706                 seq_puts(m, "unsupported on this chipset\n");
1707                 return 0;
1708         }
1709
1710         intel_runtime_pm_get(dev_priv);
1711
1712         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1713
1714         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1715         if (ret)
1716                 goto out;
1717
1718         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1719
1720         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1721              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1722              gpu_freq++) {
1723                 ia_freq = gpu_freq;
1724                 sandybridge_pcode_read(dev_priv,
1725                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1726                                        &ia_freq);
1727                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1728                            intel_gpu_freq(dev_priv, gpu_freq),
1729                            ((ia_freq >> 0) & 0xff) * 100,
1730                            ((ia_freq >> 8) & 0xff) * 100);
1731         }
1732
1733         mutex_unlock(&dev_priv->rps.hw_lock);
1734
1735 out:
1736         intel_runtime_pm_put(dev_priv);
1737         return ret;
1738 }
1739
1740 static int i915_opregion(struct seq_file *m, void *unused)
1741 {
1742         struct drm_info_node *node = m->private;
1743         struct drm_device *dev = node->minor->dev;
1744         struct drm_i915_private *dev_priv = dev->dev_private;
1745         struct intel_opregion *opregion = &dev_priv->opregion;
1746         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1747         int ret;
1748
1749         if (data == NULL)
1750                 return -ENOMEM;
1751
1752         ret = mutex_lock_interruptible(&dev->struct_mutex);
1753         if (ret)
1754                 goto out;
1755
1756         if (opregion->header) {
1757                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1758                 seq_write(m, data, OPREGION_SIZE);
1759         }
1760
1761         mutex_unlock(&dev->struct_mutex);
1762
1763 out:
1764         kfree(data);
1765         return 0;
1766 }
1767
1768 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1769 {
1770         struct drm_info_node *node = m->private;
1771         struct drm_device *dev = node->minor->dev;
1772         struct intel_fbdev *ifbdev = NULL;
1773         struct intel_framebuffer *fb;
1774
1775 #ifdef CONFIG_DRM_I915_FBDEV
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777
1778         ifbdev = dev_priv->fbdev;
1779         fb = to_intel_framebuffer(ifbdev->helper.fb);
1780
1781         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1782                    fb->base.width,
1783                    fb->base.height,
1784                    fb->base.depth,
1785                    fb->base.bits_per_pixel,
1786                    fb->base.modifier[0],
1787                    atomic_read(&fb->base.refcount.refcount));
1788         describe_obj(m, fb->obj);
1789         seq_putc(m, '\n');
1790 #endif
1791
1792         mutex_lock(&dev->mode_config.fb_lock);
1793         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1794                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1795                         continue;
1796
1797                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1798                            fb->base.width,
1799                            fb->base.height,
1800                            fb->base.depth,
1801                            fb->base.bits_per_pixel,
1802                            fb->base.modifier[0],
1803                            atomic_read(&fb->base.refcount.refcount));
1804                 describe_obj(m, fb->obj);
1805                 seq_putc(m, '\n');
1806         }
1807         mutex_unlock(&dev->mode_config.fb_lock);
1808
1809         return 0;
1810 }
1811
1812 static void describe_ctx_ringbuf(struct seq_file *m,
1813                                  struct intel_ringbuffer *ringbuf)
1814 {
1815         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1816                    ringbuf->space, ringbuf->head, ringbuf->tail,
1817                    ringbuf->last_retired_head);
1818 }
1819
1820 static int i915_context_status(struct seq_file *m, void *unused)
1821 {
1822         struct drm_info_node *node = m->private;
1823         struct drm_device *dev = node->minor->dev;
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         struct intel_engine_cs *ring;
1826         struct intel_context *ctx;
1827         int ret, i;
1828
1829         ret = mutex_lock_interruptible(&dev->struct_mutex);
1830         if (ret)
1831                 return ret;
1832
1833         if (dev_priv->ips.pwrctx) {
1834                 seq_puts(m, "power context ");
1835                 describe_obj(m, dev_priv->ips.pwrctx);
1836                 seq_putc(m, '\n');
1837         }
1838
1839         if (dev_priv->ips.renderctx) {
1840                 seq_puts(m, "render context ");
1841                 describe_obj(m, dev_priv->ips.renderctx);
1842                 seq_putc(m, '\n');
1843         }
1844
1845         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1846                 if (!i915.enable_execlists &&
1847                     ctx->legacy_hw_ctx.rcs_state == NULL)
1848                         continue;
1849
1850                 seq_puts(m, "HW context ");
1851                 describe_ctx(m, ctx);
1852                 for_each_ring(ring, dev_priv, i) {
1853                         if (ring->default_context == ctx)
1854                                 seq_printf(m, "(default context %s) ",
1855                                            ring->name);
1856                 }
1857
1858                 if (i915.enable_execlists) {
1859                         seq_putc(m, '\n');
1860                         for_each_ring(ring, dev_priv, i) {
1861                                 struct drm_i915_gem_object *ctx_obj =
1862                                         ctx->engine[i].state;
1863                                 struct intel_ringbuffer *ringbuf =
1864                                         ctx->engine[i].ringbuf;
1865
1866                                 seq_printf(m, "%s: ", ring->name);
1867                                 if (ctx_obj)
1868                                         describe_obj(m, ctx_obj);
1869                                 if (ringbuf)
1870                                         describe_ctx_ringbuf(m, ringbuf);
1871                                 seq_putc(m, '\n');
1872                         }
1873                 } else {
1874                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1875                 }
1876
1877                 seq_putc(m, '\n');
1878         }
1879
1880         mutex_unlock(&dev->struct_mutex);
1881
1882         return 0;
1883 }
1884
1885 static void i915_dump_lrc_obj(struct seq_file *m,
1886                               struct intel_engine_cs *ring,
1887                               struct drm_i915_gem_object *ctx_obj)
1888 {
1889         struct page *page;
1890         uint32_t *reg_state;
1891         int j;
1892         unsigned long ggtt_offset = 0;
1893
1894         if (ctx_obj == NULL) {
1895                 seq_printf(m, "Context on %s with no gem object\n",
1896                            ring->name);
1897                 return;
1898         }
1899
1900         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1901                    intel_execlists_ctx_id(ctx_obj));
1902
1903         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1904                 seq_puts(m, "\tNot bound in GGTT\n");
1905         else
1906                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1907
1908         if (i915_gem_object_get_pages(ctx_obj)) {
1909                 seq_puts(m, "\tFailed to get pages for context object\n");
1910                 return;
1911         }
1912
1913         page = i915_gem_object_get_page(ctx_obj, 1);
1914         if (!WARN_ON(page == NULL)) {
1915                 reg_state = kmap_atomic(page);
1916
1917                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1918                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1919                                    ggtt_offset + 4096 + (j * 4),
1920                                    reg_state[j], reg_state[j + 1],
1921                                    reg_state[j + 2], reg_state[j + 3]);
1922                 }
1923                 kunmap_atomic(reg_state);
1924         }
1925
1926         seq_putc(m, '\n');
1927 }
1928
1929 static int i915_dump_lrc(struct seq_file *m, void *unused)
1930 {
1931         struct drm_info_node *node = (struct drm_info_node *) m->private;
1932         struct drm_device *dev = node->minor->dev;
1933         struct drm_i915_private *dev_priv = dev->dev_private;
1934         struct intel_engine_cs *ring;
1935         struct intel_context *ctx;
1936         int ret, i;
1937
1938         if (!i915.enable_execlists) {
1939                 seq_printf(m, "Logical Ring Contexts are disabled\n");
1940                 return 0;
1941         }
1942
1943         ret = mutex_lock_interruptible(&dev->struct_mutex);
1944         if (ret)
1945                 return ret;
1946
1947         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1948                 for_each_ring(ring, dev_priv, i) {
1949                         if (ring->default_context != ctx)
1950                                 i915_dump_lrc_obj(m, ring,
1951                                                   ctx->engine[i].state);
1952                 }
1953         }
1954
1955         mutex_unlock(&dev->struct_mutex);
1956
1957         return 0;
1958 }
1959
1960 static int i915_execlists(struct seq_file *m, void *data)
1961 {
1962         struct drm_info_node *node = (struct drm_info_node *)m->private;
1963         struct drm_device *dev = node->minor->dev;
1964         struct drm_i915_private *dev_priv = dev->dev_private;
1965         struct intel_engine_cs *ring;
1966         u32 status_pointer;
1967         u8 read_pointer;
1968         u8 write_pointer;
1969         u32 status;
1970         u32 ctx_id;
1971         struct list_head *cursor;
1972         int ring_id, i;
1973         int ret;
1974
1975         if (!i915.enable_execlists) {
1976                 seq_puts(m, "Logical Ring Contexts are disabled\n");
1977                 return 0;
1978         }
1979
1980         ret = mutex_lock_interruptible(&dev->struct_mutex);
1981         if (ret)
1982                 return ret;
1983
1984         intel_runtime_pm_get(dev_priv);
1985
1986         for_each_ring(ring, dev_priv, ring_id) {
1987                 struct drm_i915_gem_request *head_req = NULL;
1988                 int count = 0;
1989                 unsigned long flags;
1990
1991                 seq_printf(m, "%s\n", ring->name);
1992
1993                 status = I915_READ(RING_EXECLIST_STATUS(ring));
1994                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1995                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1996                            status, ctx_id);
1997
1998                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1999                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2000
2001                 read_pointer = ring->next_context_status_buffer;
2002                 write_pointer = status_pointer & 0x07;
2003                 if (read_pointer > write_pointer)
2004                         write_pointer += 6;
2005                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2006                            read_pointer, write_pointer);
2007
2008                 for (i = 0; i < 6; i++) {
2009                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2010                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2011
2012                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2013                                    i, status, ctx_id);
2014                 }
2015
2016                 spin_lock_irqsave(&ring->execlist_lock, flags);
2017                 list_for_each(cursor, &ring->execlist_queue)
2018                         count++;
2019                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2020                                 struct drm_i915_gem_request, execlist_link);
2021                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2022
2023                 seq_printf(m, "\t%d requests in queue\n", count);
2024                 if (head_req) {
2025                         struct drm_i915_gem_object *ctx_obj;
2026
2027                         ctx_obj = head_req->ctx->engine[ring_id].state;
2028                         seq_printf(m, "\tHead request id: %u\n",
2029                                    intel_execlists_ctx_id(ctx_obj));
2030                         seq_printf(m, "\tHead request tail: %u\n",
2031                                    head_req->tail);
2032                 }
2033
2034                 seq_putc(m, '\n');
2035         }
2036
2037         intel_runtime_pm_put(dev_priv);
2038         mutex_unlock(&dev->struct_mutex);
2039
2040         return 0;
2041 }
2042
2043 static const char *swizzle_string(unsigned swizzle)
2044 {
2045         switch (swizzle) {
2046         case I915_BIT_6_SWIZZLE_NONE:
2047                 return "none";
2048         case I915_BIT_6_SWIZZLE_9:
2049                 return "bit9";
2050         case I915_BIT_6_SWIZZLE_9_10:
2051                 return "bit9/bit10";
2052         case I915_BIT_6_SWIZZLE_9_11:
2053                 return "bit9/bit11";
2054         case I915_BIT_6_SWIZZLE_9_10_11:
2055                 return "bit9/bit10/bit11";
2056         case I915_BIT_6_SWIZZLE_9_17:
2057                 return "bit9/bit17";
2058         case I915_BIT_6_SWIZZLE_9_10_17:
2059                 return "bit9/bit10/bit17";
2060         case I915_BIT_6_SWIZZLE_UNKNOWN:
2061                 return "unknown";
2062         }
2063
2064         return "bug";
2065 }
2066
2067 static int i915_swizzle_info(struct seq_file *m, void *data)
2068 {
2069         struct drm_info_node *node = m->private;
2070         struct drm_device *dev = node->minor->dev;
2071         struct drm_i915_private *dev_priv = dev->dev_private;
2072         int ret;
2073
2074         ret = mutex_lock_interruptible(&dev->struct_mutex);
2075         if (ret)
2076                 return ret;
2077         intel_runtime_pm_get(dev_priv);
2078
2079         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2080                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2081         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2082                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2083
2084         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2085                 seq_printf(m, "DDC = 0x%08x\n",
2086                            I915_READ(DCC));
2087                 seq_printf(m, "DDC2 = 0x%08x\n",
2088                            I915_READ(DCC2));
2089                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2090                            I915_READ16(C0DRB3));
2091                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2092                            I915_READ16(C1DRB3));
2093         } else if (INTEL_INFO(dev)->gen >= 6) {
2094                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2095                            I915_READ(MAD_DIMM_C0));
2096                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2097                            I915_READ(MAD_DIMM_C1));
2098                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2099                            I915_READ(MAD_DIMM_C2));
2100                 seq_printf(m, "TILECTL = 0x%08x\n",
2101                            I915_READ(TILECTL));
2102                 if (INTEL_INFO(dev)->gen >= 8)
2103                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2104                                    I915_READ(GAMTARBMODE));
2105                 else
2106                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2107                                    I915_READ(ARB_MODE));
2108                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2109                            I915_READ(DISP_ARB_CTL));
2110         }
2111
2112         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2113                 seq_puts(m, "L-shaped memory detected\n");
2114
2115         intel_runtime_pm_put(dev_priv);
2116         mutex_unlock(&dev->struct_mutex);
2117
2118         return 0;
2119 }
2120
2121 static int per_file_ctx(int id, void *ptr, void *data)
2122 {
2123         struct intel_context *ctx = ptr;
2124         struct seq_file *m = data;
2125         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2126
2127         if (!ppgtt) {
2128                 seq_printf(m, "  no ppgtt for context %d\n",
2129                            ctx->user_handle);
2130                 return 0;
2131         }
2132
2133         if (i915_gem_context_is_default(ctx))
2134                 seq_puts(m, "  default context:\n");
2135         else
2136                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2137         ppgtt->debug_dump(ppgtt, m);
2138
2139         return 0;
2140 }
2141
2142 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2143 {
2144         struct drm_i915_private *dev_priv = dev->dev_private;
2145         struct intel_engine_cs *ring;
2146         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2147         int unused, i;
2148
2149         if (!ppgtt)
2150                 return;
2151
2152         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2153         seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2154         for_each_ring(ring, dev_priv, unused) {
2155                 seq_printf(m, "%s\n", ring->name);
2156                 for (i = 0; i < 4; i++) {
2157                         u32 offset = 0x270 + i * 8;
2158                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2159                         pdp <<= 32;
2160                         pdp |= I915_READ(ring->mmio_base + offset);
2161                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2162                 }
2163         }
2164 }
2165
2166 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2167 {
2168         struct drm_i915_private *dev_priv = dev->dev_private;
2169         struct intel_engine_cs *ring;
2170         struct drm_file *file;
2171         int i;
2172
2173         if (INTEL_INFO(dev)->gen == 6)
2174                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2175
2176         for_each_ring(ring, dev_priv, i) {
2177                 seq_printf(m, "%s\n", ring->name);
2178                 if (INTEL_INFO(dev)->gen == 7)
2179                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2180                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2181                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2182                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2183         }
2184         if (dev_priv->mm.aliasing_ppgtt) {
2185                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2186
2187                 seq_puts(m, "aliasing PPGTT:\n");
2188                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
2189
2190                 ppgtt->debug_dump(ppgtt, m);
2191         }
2192
2193         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2194                 struct drm_i915_file_private *file_priv = file->driver_priv;
2195
2196                 seq_printf(m, "proc: %s\n",
2197                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2198                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2199         }
2200         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2201 }
2202
2203 static int i915_ppgtt_info(struct seq_file *m, void *data)
2204 {
2205         struct drm_info_node *node = m->private;
2206         struct drm_device *dev = node->minor->dev;
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208
2209         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2210         if (ret)
2211                 return ret;
2212         intel_runtime_pm_get(dev_priv);
2213
2214         if (INTEL_INFO(dev)->gen >= 8)
2215                 gen8_ppgtt_info(m, dev);
2216         else if (INTEL_INFO(dev)->gen >= 6)
2217                 gen6_ppgtt_info(m, dev);
2218
2219         intel_runtime_pm_put(dev_priv);
2220         mutex_unlock(&dev->struct_mutex);
2221
2222         return 0;
2223 }
2224
2225 static int i915_llc(struct seq_file *m, void *data)
2226 {
2227         struct drm_info_node *node = m->private;
2228         struct drm_device *dev = node->minor->dev;
2229         struct drm_i915_private *dev_priv = dev->dev_private;
2230
2231         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2232         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2233         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2234
2235         return 0;
2236 }
2237
2238 static int i915_edp_psr_status(struct seq_file *m, void *data)
2239 {
2240         struct drm_info_node *node = m->private;
2241         struct drm_device *dev = node->minor->dev;
2242         struct drm_i915_private *dev_priv = dev->dev_private;
2243         u32 psrperf = 0;
2244         u32 stat[3];
2245         enum pipe pipe;
2246         bool enabled = false;
2247
2248         intel_runtime_pm_get(dev_priv);
2249
2250         mutex_lock(&dev_priv->psr.lock);
2251         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2252         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2253         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2254         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2255         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2256                    dev_priv->psr.busy_frontbuffer_bits);
2257         seq_printf(m, "Re-enable work scheduled: %s\n",
2258                    yesno(work_busy(&dev_priv->psr.work.work)));
2259
2260         if (HAS_PSR(dev)) {
2261                 if (HAS_DDI(dev))
2262                         enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2263                 else {
2264                         for_each_pipe(dev_priv, pipe) {
2265                                 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2266                                         VLV_EDP_PSR_CURR_STATE_MASK;
2267                                 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2268                                     (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2269                                         enabled = true;
2270                         }
2271                 }
2272         }
2273         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2274
2275         if (!HAS_DDI(dev))
2276                 for_each_pipe(dev_priv, pipe) {
2277                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2278                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2279                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2280                 }
2281         seq_puts(m, "\n");
2282
2283         seq_printf(m, "Link standby: %s\n",
2284                    yesno((bool)dev_priv->psr.link_standby));
2285
2286         /* CHV PSR has no kind of performance counter */
2287         if (HAS_PSR(dev) && HAS_DDI(dev)) {
2288                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2289                         EDP_PSR_PERF_CNT_MASK;
2290
2291                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2292         }
2293         mutex_unlock(&dev_priv->psr.lock);
2294
2295         intel_runtime_pm_put(dev_priv);
2296         return 0;
2297 }
2298
2299 static int i915_sink_crc(struct seq_file *m, void *data)
2300 {
2301         struct drm_info_node *node = m->private;
2302         struct drm_device *dev = node->minor->dev;
2303         struct intel_encoder *encoder;
2304         struct intel_connector *connector;
2305         struct intel_dp *intel_dp = NULL;
2306         int ret;
2307         u8 crc[6];
2308
2309         drm_modeset_lock_all(dev);
2310         list_for_each_entry(connector, &dev->mode_config.connector_list,
2311                             base.head) {
2312
2313                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2314                         continue;
2315
2316                 if (!connector->base.encoder)
2317                         continue;
2318
2319                 encoder = to_intel_encoder(connector->base.encoder);
2320                 if (encoder->type != INTEL_OUTPUT_EDP)
2321                         continue;
2322
2323                 intel_dp = enc_to_intel_dp(&encoder->base);
2324
2325                 ret = intel_dp_sink_crc(intel_dp, crc);
2326                 if (ret)
2327                         goto out;
2328
2329                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2330                            crc[0], crc[1], crc[2],
2331                            crc[3], crc[4], crc[5]);
2332                 goto out;
2333         }
2334         ret = -ENODEV;
2335 out:
2336         drm_modeset_unlock_all(dev);
2337         return ret;
2338 }
2339
2340 static int i915_energy_uJ(struct seq_file *m, void *data)
2341 {
2342         struct drm_info_node *node = m->private;
2343         struct drm_device *dev = node->minor->dev;
2344         struct drm_i915_private *dev_priv = dev->dev_private;
2345         u64 power;
2346         u32 units;
2347
2348         if (INTEL_INFO(dev)->gen < 6)
2349                 return -ENODEV;
2350
2351         intel_runtime_pm_get(dev_priv);
2352
2353         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2354         power = (power & 0x1f00) >> 8;
2355         units = 1000000 / (1 << power); /* convert to uJ */
2356         power = I915_READ(MCH_SECP_NRG_STTS);
2357         power *= units;
2358
2359         intel_runtime_pm_put(dev_priv);
2360
2361         seq_printf(m, "%llu", (long long unsigned)power);
2362
2363         return 0;
2364 }
2365
2366 static int i915_pc8_status(struct seq_file *m, void *unused)
2367 {
2368         struct drm_info_node *node = m->private;
2369         struct drm_device *dev = node->minor->dev;
2370         struct drm_i915_private *dev_priv = dev->dev_private;
2371
2372         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2373                 seq_puts(m, "not supported\n");
2374                 return 0;
2375         }
2376
2377         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2378         seq_printf(m, "IRQs disabled: %s\n",
2379                    yesno(!intel_irqs_enabled(dev_priv)));
2380
2381         return 0;
2382 }
2383
2384 static const char *power_domain_str(enum intel_display_power_domain domain)
2385 {
2386         switch (domain) {
2387         case POWER_DOMAIN_PIPE_A:
2388                 return "PIPE_A";
2389         case POWER_DOMAIN_PIPE_B:
2390                 return "PIPE_B";
2391         case POWER_DOMAIN_PIPE_C:
2392                 return "PIPE_C";
2393         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2394                 return "PIPE_A_PANEL_FITTER";
2395         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2396                 return "PIPE_B_PANEL_FITTER";
2397         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2398                 return "PIPE_C_PANEL_FITTER";
2399         case POWER_DOMAIN_TRANSCODER_A:
2400                 return "TRANSCODER_A";
2401         case POWER_DOMAIN_TRANSCODER_B:
2402                 return "TRANSCODER_B";
2403         case POWER_DOMAIN_TRANSCODER_C:
2404                 return "TRANSCODER_C";
2405         case POWER_DOMAIN_TRANSCODER_EDP:
2406                 return "TRANSCODER_EDP";
2407         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2408                 return "PORT_DDI_A_2_LANES";
2409         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2410                 return "PORT_DDI_A_4_LANES";
2411         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2412                 return "PORT_DDI_B_2_LANES";
2413         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2414                 return "PORT_DDI_B_4_LANES";
2415         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2416                 return "PORT_DDI_C_2_LANES";
2417         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2418                 return "PORT_DDI_C_4_LANES";
2419         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2420                 return "PORT_DDI_D_2_LANES";
2421         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2422                 return "PORT_DDI_D_4_LANES";
2423         case POWER_DOMAIN_PORT_DSI:
2424                 return "PORT_DSI";
2425         case POWER_DOMAIN_PORT_CRT:
2426                 return "PORT_CRT";
2427         case POWER_DOMAIN_PORT_OTHER:
2428                 return "PORT_OTHER";
2429         case POWER_DOMAIN_VGA:
2430                 return "VGA";
2431         case POWER_DOMAIN_AUDIO:
2432                 return "AUDIO";
2433         case POWER_DOMAIN_PLLS:
2434                 return "PLLS";
2435         case POWER_DOMAIN_AUX_A:
2436                 return "AUX_A";
2437         case POWER_DOMAIN_AUX_B:
2438                 return "AUX_B";
2439         case POWER_DOMAIN_AUX_C:
2440                 return "AUX_C";
2441         case POWER_DOMAIN_AUX_D:
2442                 return "AUX_D";
2443         case POWER_DOMAIN_INIT:
2444                 return "INIT";
2445         default:
2446                 MISSING_CASE(domain);
2447                 return "?";
2448         }
2449 }
2450
2451 static int i915_power_domain_info(struct seq_file *m, void *unused)
2452 {
2453         struct drm_info_node *node = m->private;
2454         struct drm_device *dev = node->minor->dev;
2455         struct drm_i915_private *dev_priv = dev->dev_private;
2456         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2457         int i;
2458
2459         mutex_lock(&power_domains->lock);
2460
2461         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2462         for (i = 0; i < power_domains->power_well_count; i++) {
2463                 struct i915_power_well *power_well;
2464                 enum intel_display_power_domain power_domain;
2465
2466                 power_well = &power_domains->power_wells[i];
2467                 seq_printf(m, "%-25s %d\n", power_well->name,
2468                            power_well->count);
2469
2470                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2471                      power_domain++) {
2472                         if (!(BIT(power_domain) & power_well->domains))
2473                                 continue;
2474
2475                         seq_printf(m, "  %-23s %d\n",
2476                                  power_domain_str(power_domain),
2477                                  power_domains->domain_use_count[power_domain]);
2478                 }
2479         }
2480
2481         mutex_unlock(&power_domains->lock);
2482
2483         return 0;
2484 }
2485
2486 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2487                                  struct drm_display_mode *mode)
2488 {
2489         int i;
2490
2491         for (i = 0; i < tabs; i++)
2492                 seq_putc(m, '\t');
2493
2494         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2495                    mode->base.id, mode->name,
2496                    mode->vrefresh, mode->clock,
2497                    mode->hdisplay, mode->hsync_start,
2498                    mode->hsync_end, mode->htotal,
2499                    mode->vdisplay, mode->vsync_start,
2500                    mode->vsync_end, mode->vtotal,
2501                    mode->type, mode->flags);
2502 }
2503
2504 static void intel_encoder_info(struct seq_file *m,
2505                                struct intel_crtc *intel_crtc,
2506                                struct intel_encoder *intel_encoder)
2507 {
2508         struct drm_info_node *node = m->private;
2509         struct drm_device *dev = node->minor->dev;
2510         struct drm_crtc *crtc = &intel_crtc->base;
2511         struct intel_connector *intel_connector;
2512         struct drm_encoder *encoder;
2513
2514         encoder = &intel_encoder->base;
2515         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2516                    encoder->base.id, encoder->name);
2517         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2518                 struct drm_connector *connector = &intel_connector->base;
2519                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2520                            connector->base.id,
2521                            connector->name,
2522                            drm_get_connector_status_name(connector->status));
2523                 if (connector->status == connector_status_connected) {
2524                         struct drm_display_mode *mode = &crtc->mode;
2525                         seq_printf(m, ", mode:\n");
2526                         intel_seq_print_mode(m, 2, mode);
2527                 } else {
2528                         seq_putc(m, '\n');
2529                 }
2530         }
2531 }
2532
2533 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2534 {
2535         struct drm_info_node *node = m->private;
2536         struct drm_device *dev = node->minor->dev;
2537         struct drm_crtc *crtc = &intel_crtc->base;
2538         struct intel_encoder *intel_encoder;
2539
2540         if (crtc->primary->fb)
2541                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2542                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2543                            crtc->primary->fb->width, crtc->primary->fb->height);
2544         else
2545                 seq_puts(m, "\tprimary plane disabled\n");
2546         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2547                 intel_encoder_info(m, intel_crtc, intel_encoder);
2548 }
2549
2550 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2551 {
2552         struct drm_display_mode *mode = panel->fixed_mode;
2553
2554         seq_printf(m, "\tfixed mode:\n");
2555         intel_seq_print_mode(m, 2, mode);
2556 }
2557
2558 static void intel_dp_info(struct seq_file *m,
2559                           struct intel_connector *intel_connector)
2560 {
2561         struct intel_encoder *intel_encoder = intel_connector->encoder;
2562         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2563
2564         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2565         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2566                    "no");
2567         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2568                 intel_panel_info(m, &intel_connector->panel);
2569 }
2570
2571 static void intel_hdmi_info(struct seq_file *m,
2572                             struct intel_connector *intel_connector)
2573 {
2574         struct intel_encoder *intel_encoder = intel_connector->encoder;
2575         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2576
2577         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2578                    "no");
2579 }
2580
2581 static void intel_lvds_info(struct seq_file *m,
2582                             struct intel_connector *intel_connector)
2583 {
2584         intel_panel_info(m, &intel_connector->panel);
2585 }
2586
2587 static void intel_connector_info(struct seq_file *m,
2588                                  struct drm_connector *connector)
2589 {
2590         struct intel_connector *intel_connector = to_intel_connector(connector);
2591         struct intel_encoder *intel_encoder = intel_connector->encoder;
2592         struct drm_display_mode *mode;
2593
2594         seq_printf(m, "connector %d: type %s, status: %s\n",
2595                    connector->base.id, connector->name,
2596                    drm_get_connector_status_name(connector->status));
2597         if (connector->status == connector_status_connected) {
2598                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2599                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2600                            connector->display_info.width_mm,
2601                            connector->display_info.height_mm);
2602                 seq_printf(m, "\tsubpixel order: %s\n",
2603                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2604                 seq_printf(m, "\tCEA rev: %d\n",
2605                            connector->display_info.cea_rev);
2606         }
2607         if (intel_encoder) {
2608                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2609                     intel_encoder->type == INTEL_OUTPUT_EDP)
2610                         intel_dp_info(m, intel_connector);
2611                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2612                         intel_hdmi_info(m, intel_connector);
2613                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2614                         intel_lvds_info(m, intel_connector);
2615         }
2616
2617         seq_printf(m, "\tmodes:\n");
2618         list_for_each_entry(mode, &connector->modes, head)
2619                 intel_seq_print_mode(m, 2, mode);
2620 }
2621
2622 static bool cursor_active(struct drm_device *dev, int pipe)
2623 {
2624         struct drm_i915_private *dev_priv = dev->dev_private;
2625         u32 state;
2626
2627         if (IS_845G(dev) || IS_I865G(dev))
2628                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2629         else
2630                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2631
2632         return state;
2633 }
2634
2635 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2636 {
2637         struct drm_i915_private *dev_priv = dev->dev_private;
2638         u32 pos;
2639
2640         pos = I915_READ(CURPOS(pipe));
2641
2642         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2643         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2644                 *x = -*x;
2645
2646         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2647         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2648                 *y = -*y;
2649
2650         return cursor_active(dev, pipe);
2651 }
2652
2653 static int i915_display_info(struct seq_file *m, void *unused)
2654 {
2655         struct drm_info_node *node = m->private;
2656         struct drm_device *dev = node->minor->dev;
2657         struct drm_i915_private *dev_priv = dev->dev_private;
2658         struct intel_crtc *crtc;
2659         struct drm_connector *connector;
2660
2661         intel_runtime_pm_get(dev_priv);
2662         drm_modeset_lock_all(dev);
2663         seq_printf(m, "CRTC info\n");
2664         seq_printf(m, "---------\n");
2665         for_each_intel_crtc(dev, crtc) {
2666                 bool active;
2667                 int x, y;
2668
2669                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2670                            crtc->base.base.id, pipe_name(crtc->pipe),
2671                            yesno(crtc->active), crtc->config->pipe_src_w,
2672                            crtc->config->pipe_src_h);
2673                 if (crtc->active) {
2674                         intel_crtc_info(m, crtc);
2675
2676                         active = cursor_position(dev, crtc->pipe, &x, &y);
2677                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2678                                    yesno(crtc->cursor_base),
2679                                    x, y, crtc->cursor_width, crtc->cursor_height,
2680                                    crtc->cursor_addr, yesno(active));
2681                 }
2682
2683                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2684                            yesno(!crtc->cpu_fifo_underrun_disabled),
2685                            yesno(!crtc->pch_fifo_underrun_disabled));
2686         }
2687
2688         seq_printf(m, "\n");
2689         seq_printf(m, "Connector info\n");
2690         seq_printf(m, "--------------\n");
2691         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2692                 intel_connector_info(m, connector);
2693         }
2694         drm_modeset_unlock_all(dev);
2695         intel_runtime_pm_put(dev_priv);
2696
2697         return 0;
2698 }
2699
2700 static int i915_semaphore_status(struct seq_file *m, void *unused)
2701 {
2702         struct drm_info_node *node = (struct drm_info_node *) m->private;
2703         struct drm_device *dev = node->minor->dev;
2704         struct drm_i915_private *dev_priv = dev->dev_private;
2705         struct intel_engine_cs *ring;
2706         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2707         int i, j, ret;
2708
2709         if (!i915_semaphore_is_enabled(dev)) {
2710                 seq_puts(m, "Semaphores are disabled\n");
2711                 return 0;
2712         }
2713
2714         ret = mutex_lock_interruptible(&dev->struct_mutex);
2715         if (ret)
2716                 return ret;
2717         intel_runtime_pm_get(dev_priv);
2718
2719         if (IS_BROADWELL(dev)) {
2720                 struct page *page;
2721                 uint64_t *seqno;
2722
2723                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2724
2725                 seqno = (uint64_t *)kmap_atomic(page);
2726                 for_each_ring(ring, dev_priv, i) {
2727                         uint64_t offset;
2728
2729                         seq_printf(m, "%s\n", ring->name);
2730
2731                         seq_puts(m, "  Last signal:");
2732                         for (j = 0; j < num_rings; j++) {
2733                                 offset = i * I915_NUM_RINGS + j;
2734                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2735                                            seqno[offset], offset * 8);
2736                         }
2737                         seq_putc(m, '\n');
2738
2739                         seq_puts(m, "  Last wait:  ");
2740                         for (j = 0; j < num_rings; j++) {
2741                                 offset = i + (j * I915_NUM_RINGS);
2742                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2743                                            seqno[offset], offset * 8);
2744                         }
2745                         seq_putc(m, '\n');
2746
2747                 }
2748                 kunmap_atomic(seqno);
2749         } else {
2750                 seq_puts(m, "  Last signal:");
2751                 for_each_ring(ring, dev_priv, i)
2752                         for (j = 0; j < num_rings; j++)
2753                                 seq_printf(m, "0x%08x\n",
2754                                            I915_READ(ring->semaphore.mbox.signal[j]));
2755                 seq_putc(m, '\n');
2756         }
2757
2758         seq_puts(m, "\nSync seqno:\n");
2759         for_each_ring(ring, dev_priv, i) {
2760                 for (j = 0; j < num_rings; j++) {
2761                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2762                 }
2763                 seq_putc(m, '\n');
2764         }
2765         seq_putc(m, '\n');
2766
2767         intel_runtime_pm_put(dev_priv);
2768         mutex_unlock(&dev->struct_mutex);
2769         return 0;
2770 }
2771
2772 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2773 {
2774         struct drm_info_node *node = (struct drm_info_node *) m->private;
2775         struct drm_device *dev = node->minor->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         int i;
2778
2779         drm_modeset_lock_all(dev);
2780         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2781                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2782
2783                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2784                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2785                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2786                 seq_printf(m, " tracked hardware state:\n");
2787                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2788                 seq_printf(m, " dpll_md: 0x%08x\n",
2789                            pll->config.hw_state.dpll_md);
2790                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2791                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2792                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2793         }
2794         drm_modeset_unlock_all(dev);
2795
2796         return 0;
2797 }
2798
2799 static int i915_wa_registers(struct seq_file *m, void *unused)
2800 {
2801         int i;
2802         int ret;
2803         struct drm_info_node *node = (struct drm_info_node *) m->private;
2804         struct drm_device *dev = node->minor->dev;
2805         struct drm_i915_private *dev_priv = dev->dev_private;
2806
2807         ret = mutex_lock_interruptible(&dev->struct_mutex);
2808         if (ret)
2809                 return ret;
2810
2811         intel_runtime_pm_get(dev_priv);
2812
2813         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2814         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2815                 u32 addr, mask, value, read;
2816                 bool ok;
2817
2818                 addr = dev_priv->workarounds.reg[i].addr;
2819                 mask = dev_priv->workarounds.reg[i].mask;
2820                 value = dev_priv->workarounds.reg[i].value;
2821                 read = I915_READ(addr);
2822                 ok = (value & mask) == (read & mask);
2823                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2824                            addr, value, mask, read, ok ? "OK" : "FAIL");
2825         }
2826
2827         intel_runtime_pm_put(dev_priv);
2828         mutex_unlock(&dev->struct_mutex);
2829
2830         return 0;
2831 }
2832
2833 static int i915_ddb_info(struct seq_file *m, void *unused)
2834 {
2835         struct drm_info_node *node = m->private;
2836         struct drm_device *dev = node->minor->dev;
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         struct skl_ddb_allocation *ddb;
2839         struct skl_ddb_entry *entry;
2840         enum pipe pipe;
2841         int plane;
2842
2843         if (INTEL_INFO(dev)->gen < 9)
2844                 return 0;
2845
2846         drm_modeset_lock_all(dev);
2847
2848         ddb = &dev_priv->wm.skl_hw.ddb;
2849
2850         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2851
2852         for_each_pipe(dev_priv, pipe) {
2853                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2854
2855                 for_each_plane(pipe, plane) {
2856                         entry = &ddb->plane[pipe][plane];
2857                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2858                                    entry->start, entry->end,
2859                                    skl_ddb_entry_size(entry));
2860                 }
2861
2862                 entry = &ddb->cursor[pipe];
2863                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
2864                            entry->end, skl_ddb_entry_size(entry));
2865         }
2866
2867         drm_modeset_unlock_all(dev);
2868
2869         return 0;
2870 }
2871
2872 struct pipe_crc_info {
2873         const char *name;
2874         struct drm_device *dev;
2875         enum pipe pipe;
2876 };
2877
2878 static int i915_dp_mst_info(struct seq_file *m, void *unused)
2879 {
2880         struct drm_info_node *node = (struct drm_info_node *) m->private;
2881         struct drm_device *dev = node->minor->dev;
2882         struct drm_encoder *encoder;
2883         struct intel_encoder *intel_encoder;
2884         struct intel_digital_port *intel_dig_port;
2885         drm_modeset_lock_all(dev);
2886         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2887                 intel_encoder = to_intel_encoder(encoder);
2888                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2889                         continue;
2890                 intel_dig_port = enc_to_dig_port(encoder);
2891                 if (!intel_dig_port->dp.can_mst)
2892                         continue;
2893
2894                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2895         }
2896         drm_modeset_unlock_all(dev);
2897         return 0;
2898 }
2899
2900 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2901 {
2902         struct pipe_crc_info *info = inode->i_private;
2903         struct drm_i915_private *dev_priv = info->dev->dev_private;
2904         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2905
2906         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2907                 return -ENODEV;
2908
2909         spin_lock_irq(&pipe_crc->lock);
2910
2911         if (pipe_crc->opened) {
2912                 spin_unlock_irq(&pipe_crc->lock);
2913                 return -EBUSY; /* already open */
2914         }
2915
2916         pipe_crc->opened = true;
2917         filep->private_data = inode->i_private;
2918
2919         spin_unlock_irq(&pipe_crc->lock);
2920
2921         return 0;
2922 }
2923
2924 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2925 {
2926         struct pipe_crc_info *info = inode->i_private;
2927         struct drm_i915_private *dev_priv = info->dev->dev_private;
2928         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2929
2930         spin_lock_irq(&pipe_crc->lock);
2931         pipe_crc->opened = false;
2932         spin_unlock_irq(&pipe_crc->lock);
2933
2934         return 0;
2935 }
2936
2937 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2938 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2939 /* account for \'0' */
2940 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2941
2942 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2943 {
2944         assert_spin_locked(&pipe_crc->lock);
2945         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2946                         INTEL_PIPE_CRC_ENTRIES_NR);
2947 }
2948
2949 static ssize_t
2950 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2951                    loff_t *pos)
2952 {
2953         struct pipe_crc_info *info = filep->private_data;
2954         struct drm_device *dev = info->dev;
2955         struct drm_i915_private *dev_priv = dev->dev_private;
2956         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2957         char buf[PIPE_CRC_BUFFER_LEN];
2958         int n_entries;
2959         ssize_t bytes_read;
2960
2961         /*
2962          * Don't allow user space to provide buffers not big enough to hold
2963          * a line of data.
2964          */
2965         if (count < PIPE_CRC_LINE_LEN)
2966                 return -EINVAL;
2967
2968         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2969                 return 0;
2970
2971         /* nothing to read */
2972         spin_lock_irq(&pipe_crc->lock);
2973         while (pipe_crc_data_count(pipe_crc) == 0) {
2974                 int ret;
2975
2976                 if (filep->f_flags & O_NONBLOCK) {
2977                         spin_unlock_irq(&pipe_crc->lock);
2978                         return -EAGAIN;
2979                 }
2980
2981                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2982                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2983                 if (ret) {
2984                         spin_unlock_irq(&pipe_crc->lock);
2985                         return ret;
2986                 }
2987         }
2988
2989         /* We now have one or more entries to read */
2990         n_entries = count / PIPE_CRC_LINE_LEN;
2991
2992         bytes_read = 0;
2993         while (n_entries > 0) {
2994                 struct intel_pipe_crc_entry *entry =
2995                         &pipe_crc->entries[pipe_crc->tail];
2996                 int ret;
2997
2998                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2999                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3000                         break;
3001
3002                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3003                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3004
3005                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3006                                        "%8u %8x %8x %8x %8x %8x\n",
3007                                        entry->frame, entry->crc[0],
3008                                        entry->crc[1], entry->crc[2],
3009                                        entry->crc[3], entry->crc[4]);
3010
3011                 spin_unlock_irq(&pipe_crc->lock);
3012
3013                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3014                 if (ret == PIPE_CRC_LINE_LEN)
3015                         return -EFAULT;
3016
3017                 user_buf += PIPE_CRC_LINE_LEN;
3018                 n_entries--;
3019
3020                 spin_lock_irq(&pipe_crc->lock);
3021         }
3022
3023         spin_unlock_irq(&pipe_crc->lock);
3024
3025         return bytes_read;
3026 }
3027
3028 static const struct file_operations i915_pipe_crc_fops = {
3029         .owner = THIS_MODULE,
3030         .open = i915_pipe_crc_open,
3031         .read = i915_pipe_crc_read,
3032         .release = i915_pipe_crc_release,
3033 };
3034
3035 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3036         {
3037                 .name = "i915_pipe_A_crc",
3038                 .pipe = PIPE_A,
3039         },
3040         {
3041                 .name = "i915_pipe_B_crc",
3042                 .pipe = PIPE_B,
3043         },
3044         {
3045                 .name = "i915_pipe_C_crc",
3046                 .pipe = PIPE_C,
3047         },
3048 };
3049
3050 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3051                                 enum pipe pipe)
3052 {
3053         struct drm_device *dev = minor->dev;
3054         struct dentry *ent;
3055         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3056
3057         info->dev = dev;
3058         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3059                                   &i915_pipe_crc_fops);
3060         if (!ent)
3061                 return -ENOMEM;
3062
3063         return drm_add_fake_info_node(minor, ent, info);
3064 }
3065
3066 static const char * const pipe_crc_sources[] = {
3067         "none",
3068         "plane1",
3069         "plane2",
3070         "pf",
3071         "pipe",
3072         "TV",
3073         "DP-B",
3074         "DP-C",
3075         "DP-D",
3076         "auto",
3077 };
3078
3079 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3080 {
3081         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3082         return pipe_crc_sources[source];
3083 }
3084
3085 static int display_crc_ctl_show(struct seq_file *m, void *data)
3086 {
3087         struct drm_device *dev = m->private;
3088         struct drm_i915_private *dev_priv = dev->dev_private;
3089         int i;
3090
3091         for (i = 0; i < I915_MAX_PIPES; i++)
3092                 seq_printf(m, "%c %s\n", pipe_name(i),
3093                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3094
3095         return 0;
3096 }
3097
3098 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3099 {
3100         struct drm_device *dev = inode->i_private;
3101
3102         return single_open(file, display_crc_ctl_show, dev);
3103 }
3104
3105 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3106                                  uint32_t *val)
3107 {
3108         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3109                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3110
3111         switch (*source) {
3112         case INTEL_PIPE_CRC_SOURCE_PIPE:
3113                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3114                 break;
3115         case INTEL_PIPE_CRC_SOURCE_NONE:
3116                 *val = 0;
3117                 break;
3118         default:
3119                 return -EINVAL;
3120         }
3121
3122         return 0;
3123 }
3124
3125 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3126                                      enum intel_pipe_crc_source *source)
3127 {
3128         struct intel_encoder *encoder;
3129         struct intel_crtc *crtc;
3130         struct intel_digital_port *dig_port;
3131         int ret = 0;
3132
3133         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3134
3135         drm_modeset_lock_all(dev);
3136         for_each_intel_encoder(dev, encoder) {
3137                 if (!encoder->base.crtc)
3138                         continue;
3139
3140                 crtc = to_intel_crtc(encoder->base.crtc);
3141
3142                 if (crtc->pipe != pipe)
3143                         continue;
3144
3145                 switch (encoder->type) {
3146                 case INTEL_OUTPUT_TVOUT:
3147                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3148                         break;
3149                 case INTEL_OUTPUT_DISPLAYPORT:
3150                 case INTEL_OUTPUT_EDP:
3151                         dig_port = enc_to_dig_port(&encoder->base);
3152                         switch (dig_port->port) {
3153                         case PORT_B:
3154                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3155                                 break;
3156                         case PORT_C:
3157                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3158                                 break;
3159                         case PORT_D:
3160                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3161                                 break;
3162                         default:
3163                                 WARN(1, "nonexisting DP port %c\n",
3164                                      port_name(dig_port->port));
3165                                 break;
3166                         }
3167                         break;
3168                 default:
3169                         break;
3170                 }
3171         }
3172         drm_modeset_unlock_all(dev);
3173
3174         return ret;
3175 }
3176
3177 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3178                                 enum pipe pipe,
3179                                 enum intel_pipe_crc_source *source,
3180                                 uint32_t *val)
3181 {
3182         struct drm_i915_private *dev_priv = dev->dev_private;
3183         bool need_stable_symbols = false;
3184
3185         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3186                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3187                 if (ret)
3188                         return ret;
3189         }
3190
3191         switch (*source) {
3192         case INTEL_PIPE_CRC_SOURCE_PIPE:
3193                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3194                 break;
3195         case INTEL_PIPE_CRC_SOURCE_DP_B:
3196                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3197                 need_stable_symbols = true;
3198                 break;
3199         case INTEL_PIPE_CRC_SOURCE_DP_C:
3200                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3201                 need_stable_symbols = true;
3202                 break;
3203         case INTEL_PIPE_CRC_SOURCE_DP_D:
3204                 if (!IS_CHERRYVIEW(dev))
3205                         return -EINVAL;
3206                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3207                 need_stable_symbols = true;
3208                 break;
3209         case INTEL_PIPE_CRC_SOURCE_NONE:
3210                 *val = 0;
3211                 break;
3212         default:
3213                 return -EINVAL;
3214         }
3215
3216         /*
3217          * When the pipe CRC tap point is after the transcoders we need
3218          * to tweak symbol-level features to produce a deterministic series of
3219          * symbols for a given frame. We need to reset those features only once
3220          * a frame (instead of every nth symbol):
3221          *   - DC-balance: used to ensure a better clock recovery from the data
3222          *     link (SDVO)
3223          *   - DisplayPort scrambling: used for EMI reduction
3224          */
3225         if (need_stable_symbols) {
3226                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3227
3228                 tmp |= DC_BALANCE_RESET_VLV;
3229                 switch (pipe) {
3230                 case PIPE_A:
3231                         tmp |= PIPE_A_SCRAMBLE_RESET;
3232                         break;
3233                 case PIPE_B:
3234                         tmp |= PIPE_B_SCRAMBLE_RESET;
3235                         break;
3236                 case PIPE_C:
3237                         tmp |= PIPE_C_SCRAMBLE_RESET;
3238                         break;
3239                 default:
3240                         return -EINVAL;
3241                 }
3242                 I915_WRITE(PORT_DFT2_G4X, tmp);
3243         }
3244
3245         return 0;
3246 }
3247
3248 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3249                                  enum pipe pipe,
3250                                  enum intel_pipe_crc_source *source,
3251                                  uint32_t *val)
3252 {
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         bool need_stable_symbols = false;
3255
3256         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3257                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3258                 if (ret)
3259                         return ret;
3260         }
3261
3262         switch (*source) {
3263         case INTEL_PIPE_CRC_SOURCE_PIPE:
3264                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3265                 break;
3266         case INTEL_PIPE_CRC_SOURCE_TV:
3267                 if (!SUPPORTS_TV(dev))
3268                         return -EINVAL;
3269                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3270                 break;
3271         case INTEL_PIPE_CRC_SOURCE_DP_B:
3272                 if (!IS_G4X(dev))
3273                         return -EINVAL;
3274                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3275                 need_stable_symbols = true;
3276                 break;
3277         case INTEL_PIPE_CRC_SOURCE_DP_C:
3278                 if (!IS_G4X(dev))
3279                         return -EINVAL;
3280                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3281                 need_stable_symbols = true;
3282                 break;
3283         case INTEL_PIPE_CRC_SOURCE_DP_D:
3284                 if (!IS_G4X(dev))
3285                         return -EINVAL;
3286                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3287                 need_stable_symbols = true;
3288                 break;
3289         case INTEL_PIPE_CRC_SOURCE_NONE:
3290                 *val = 0;
3291                 break;
3292         default:
3293                 return -EINVAL;
3294         }
3295
3296         /*
3297          * When the pipe CRC tap point is after the transcoders we need
3298          * to tweak symbol-level features to produce a deterministic series of
3299          * symbols for a given frame. We need to reset those features only once
3300          * a frame (instead of every nth symbol):
3301          *   - DC-balance: used to ensure a better clock recovery from the data
3302          *     link (SDVO)
3303          *   - DisplayPort scrambling: used for EMI reduction
3304          */
3305         if (need_stable_symbols) {
3306                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3307
3308                 WARN_ON(!IS_G4X(dev));
3309
3310                 I915_WRITE(PORT_DFT_I9XX,
3311                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3312
3313                 if (pipe == PIPE_A)
3314                         tmp |= PIPE_A_SCRAMBLE_RESET;
3315                 else
3316                         tmp |= PIPE_B_SCRAMBLE_RESET;
3317
3318                 I915_WRITE(PORT_DFT2_G4X, tmp);
3319         }
3320
3321         return 0;
3322 }
3323
3324 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3325                                          enum pipe pipe)
3326 {
3327         struct drm_i915_private *dev_priv = dev->dev_private;
3328         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3329
3330         switch (pipe) {
3331         case PIPE_A:
3332                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3333                 break;
3334         case PIPE_B:
3335                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3336                 break;
3337         case PIPE_C:
3338                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3339                 break;
3340         default:
3341                 return;
3342         }
3343         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3344                 tmp &= ~DC_BALANCE_RESET_VLV;
3345         I915_WRITE(PORT_DFT2_G4X, tmp);
3346
3347 }
3348
3349 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3350                                          enum pipe pipe)
3351 {
3352         struct drm_i915_private *dev_priv = dev->dev_private;
3353         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3354
3355         if (pipe == PIPE_A)
3356                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3357         else
3358                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3359         I915_WRITE(PORT_DFT2_G4X, tmp);
3360
3361         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3362                 I915_WRITE(PORT_DFT_I9XX,
3363                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3364         }
3365 }
3366
3367 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3368                                 uint32_t *val)
3369 {
3370         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3371                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3372
3373         switch (*source) {
3374         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3375                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3376                 break;
3377         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3378                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3379                 break;
3380         case INTEL_PIPE_CRC_SOURCE_PIPE:
3381                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3382                 break;
3383         case INTEL_PIPE_CRC_SOURCE_NONE:
3384                 *val = 0;
3385                 break;
3386         default:
3387                 return -EINVAL;
3388         }
3389
3390         return 0;
3391 }
3392
3393 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3394 {
3395         struct drm_i915_private *dev_priv = dev->dev_private;
3396         struct intel_crtc *crtc =
3397                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3398
3399         drm_modeset_lock_all(dev);
3400         /*
3401          * If we use the eDP transcoder we need to make sure that we don't
3402          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3403          * relevant on hsw with pipe A when using the always-on power well
3404          * routing.
3405          */
3406         if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3407             !crtc->config->pch_pfit.enabled) {
3408                 crtc->config->pch_pfit.force_thru = true;
3409
3410                 intel_display_power_get(dev_priv,
3411                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3412
3413                 dev_priv->display.crtc_disable(&crtc->base);
3414                 dev_priv->display.crtc_enable(&crtc->base);
3415         }
3416         drm_modeset_unlock_all(dev);
3417 }
3418
3419 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3420 {
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         struct intel_crtc *crtc =
3423                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3424
3425         drm_modeset_lock_all(dev);
3426         /*
3427          * If we use the eDP transcoder we need to make sure that we don't
3428          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3429          * relevant on hsw with pipe A when using the always-on power well
3430          * routing.
3431          */
3432         if (crtc->config->pch_pfit.force_thru) {
3433                 crtc->config->pch_pfit.force_thru = false;
3434
3435                 dev_priv->display.crtc_disable(&crtc->base);
3436                 dev_priv->display.crtc_enable(&crtc->base);
3437
3438                 intel_display_power_put(dev_priv,
3439                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3440         }
3441         drm_modeset_unlock_all(dev);
3442 }
3443
3444 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3445                                 enum pipe pipe,
3446                                 enum intel_pipe_crc_source *source,
3447                                 uint32_t *val)
3448 {
3449         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3450                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3451
3452         switch (*source) {
3453         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3454                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3455                 break;
3456         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3457                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3458                 break;
3459         case INTEL_PIPE_CRC_SOURCE_PF:
3460                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3461                         hsw_trans_edp_pipe_A_crc_wa(dev);
3462
3463                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3464                 break;
3465         case INTEL_PIPE_CRC_SOURCE_NONE:
3466                 *val = 0;
3467                 break;
3468         default:
3469                 return -EINVAL;
3470         }
3471
3472         return 0;
3473 }
3474
3475 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3476                                enum intel_pipe_crc_source source)
3477 {
3478         struct drm_i915_private *dev_priv = dev->dev_private;
3479         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3480         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3481                                                                         pipe));
3482         u32 val = 0; /* shut up gcc */
3483         int ret;
3484
3485         if (pipe_crc->source == source)
3486                 return 0;
3487
3488         /* forbid changing the source without going back to 'none' */
3489         if (pipe_crc->source && source)
3490                 return -EINVAL;
3491
3492         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3493                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3494                 return -EIO;
3495         }
3496
3497         if (IS_GEN2(dev))
3498                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3499         else if (INTEL_INFO(dev)->gen < 5)
3500                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3501         else if (IS_VALLEYVIEW(dev))
3502                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3503         else if (IS_GEN5(dev) || IS_GEN6(dev))
3504                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3505         else
3506                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3507
3508         if (ret != 0)
3509                 return ret;
3510
3511         /* none -> real source transition */
3512         if (source) {
3513                 struct intel_pipe_crc_entry *entries;
3514
3515                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3516                                  pipe_name(pipe), pipe_crc_source_name(source));
3517
3518                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3519                                   sizeof(pipe_crc->entries[0]),
3520                                   GFP_KERNEL);
3521                 if (!entries)
3522                         return -ENOMEM;
3523
3524                 /*
3525                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3526                  * enabled and disabled dynamically based on package C states,
3527                  * user space can't make reliable use of the CRCs, so let's just
3528                  * completely disable it.
3529                  */
3530                 hsw_disable_ips(crtc);
3531
3532                 spin_lock_irq(&pipe_crc->lock);
3533                 kfree(pipe_crc->entries);
3534                 pipe_crc->entries = entries;
3535                 pipe_crc->head = 0;
3536                 pipe_crc->tail = 0;
3537                 spin_unlock_irq(&pipe_crc->lock);
3538         }
3539
3540         pipe_crc->source = source;
3541
3542         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3543         POSTING_READ(PIPE_CRC_CTL(pipe));
3544
3545         /* real source -> none transition */
3546         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3547                 struct intel_pipe_crc_entry *entries;
3548                 struct intel_crtc *crtc =
3549                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3550
3551                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3552                                  pipe_name(pipe));
3553
3554                 drm_modeset_lock(&crtc->base.mutex, NULL);
3555                 if (crtc->active)
3556                         intel_wait_for_vblank(dev, pipe);
3557                 drm_modeset_unlock(&crtc->base.mutex);
3558
3559                 spin_lock_irq(&pipe_crc->lock);
3560                 entries = pipe_crc->entries;
3561                 pipe_crc->entries = NULL;
3562                 pipe_crc->head = 0;
3563                 pipe_crc->tail = 0;
3564                 spin_unlock_irq(&pipe_crc->lock);
3565
3566                 kfree(entries);
3567
3568                 if (IS_G4X(dev))
3569                         g4x_undo_pipe_scramble_reset(dev, pipe);
3570                 else if (IS_VALLEYVIEW(dev))
3571                         vlv_undo_pipe_scramble_reset(dev, pipe);
3572                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3573                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3574
3575                 hsw_enable_ips(crtc);
3576         }
3577
3578         return 0;
3579 }
3580
3581 /*
3582  * Parse pipe CRC command strings:
3583  *   command: wsp* object wsp+ name wsp+ source wsp*
3584  *   object: 'pipe'
3585  *   name: (A | B | C)
3586  *   source: (none | plane1 | plane2 | pf)
3587  *   wsp: (#0x20 | #0x9 | #0xA)+
3588  *
3589  * eg.:
3590  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3591  *  "pipe A none"    ->  Stop CRC
3592  */
3593 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3594 {
3595         int n_words = 0;
3596
3597         while (*buf) {
3598                 char *end;
3599
3600                 /* skip leading white space */
3601                 buf = skip_spaces(buf);
3602                 if (!*buf)
3603                         break;  /* end of buffer */
3604
3605                 /* find end of word */
3606                 for (end = buf; *end && !isspace(*end); end++)
3607                         ;
3608
3609                 if (n_words == max_words) {
3610                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3611                                          max_words);
3612                         return -EINVAL; /* ran out of words[] before bytes */
3613                 }
3614
3615                 if (*end)
3616                         *end++ = '\0';
3617                 words[n_words++] = buf;
3618                 buf = end;
3619         }
3620
3621         return n_words;
3622 }
3623
3624 enum intel_pipe_crc_object {
3625         PIPE_CRC_OBJECT_PIPE,
3626 };
3627
3628 static const char * const pipe_crc_objects[] = {
3629         "pipe",
3630 };
3631
3632 static int
3633 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3634 {
3635         int i;
3636
3637         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3638                 if (!strcmp(buf, pipe_crc_objects[i])) {
3639                         *o = i;
3640                         return 0;
3641                     }
3642
3643         return -EINVAL;
3644 }
3645
3646 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3647 {
3648         const char name = buf[0];
3649
3650         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3651                 return -EINVAL;
3652
3653         *pipe = name - 'A';
3654
3655         return 0;
3656 }
3657
3658 static int
3659 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3660 {
3661         int i;
3662
3663         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3664                 if (!strcmp(buf, pipe_crc_sources[i])) {
3665                         *s = i;
3666                         return 0;
3667                     }
3668
3669         return -EINVAL;
3670 }
3671
3672 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3673 {
3674 #define N_WORDS 3
3675         int n_words;
3676         char *words[N_WORDS];
3677         enum pipe pipe;
3678         enum intel_pipe_crc_object object;
3679         enum intel_pipe_crc_source source;
3680
3681         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3682         if (n_words != N_WORDS) {
3683                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3684                                  N_WORDS);
3685                 return -EINVAL;
3686         }
3687
3688         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3689                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3690                 return -EINVAL;
3691         }
3692
3693         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3694                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3695                 return -EINVAL;
3696         }
3697
3698         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3699                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3700                 return -EINVAL;
3701         }
3702
3703         return pipe_crc_set_source(dev, pipe, source);
3704 }
3705
3706 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3707                                      size_t len, loff_t *offp)
3708 {
3709         struct seq_file *m = file->private_data;
3710         struct drm_device *dev = m->private;
3711         char *tmpbuf;
3712         int ret;
3713
3714         if (len == 0)
3715                 return 0;
3716
3717         if (len > PAGE_SIZE - 1) {
3718                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3719                                  PAGE_SIZE);
3720                 return -E2BIG;
3721         }
3722
3723         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3724         if (!tmpbuf)
3725                 return -ENOMEM;
3726
3727         if (copy_from_user(tmpbuf, ubuf, len)) {
3728                 ret = -EFAULT;
3729                 goto out;
3730         }
3731         tmpbuf[len] = '\0';
3732
3733         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3734
3735 out:
3736         kfree(tmpbuf);
3737         if (ret < 0)
3738                 return ret;
3739
3740         *offp += len;
3741         return len;
3742 }
3743
3744 static const struct file_operations i915_display_crc_ctl_fops = {
3745         .owner = THIS_MODULE,
3746         .open = display_crc_ctl_open,
3747         .read = seq_read,
3748         .llseek = seq_lseek,
3749         .release = single_release,
3750         .write = display_crc_ctl_write
3751 };
3752
3753 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3754 {
3755         struct drm_device *dev = m->private;
3756         int num_levels = ilk_wm_max_level(dev) + 1;
3757         int level;
3758
3759         drm_modeset_lock_all(dev);
3760
3761         for (level = 0; level < num_levels; level++) {
3762                 unsigned int latency = wm[level];
3763
3764                 /*
3765                  * - WM1+ latency values in 0.5us units
3766                  * - latencies are in us on gen9
3767                  */
3768                 if (INTEL_INFO(dev)->gen >= 9)
3769                         latency *= 10;
3770                 else if (level > 0)
3771                         latency *= 5;
3772
3773                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3774                            level, wm[level], latency / 10, latency % 10);
3775         }
3776
3777         drm_modeset_unlock_all(dev);
3778 }
3779
3780 static int pri_wm_latency_show(struct seq_file *m, void *data)
3781 {
3782         struct drm_device *dev = m->private;
3783         struct drm_i915_private *dev_priv = dev->dev_private;
3784         const uint16_t *latencies;
3785
3786         if (INTEL_INFO(dev)->gen >= 9)
3787                 latencies = dev_priv->wm.skl_latency;
3788         else
3789                 latencies = to_i915(dev)->wm.pri_latency;
3790
3791         wm_latency_show(m, latencies);
3792
3793         return 0;
3794 }
3795
3796 static int spr_wm_latency_show(struct seq_file *m, void *data)
3797 {
3798         struct drm_device *dev = m->private;
3799         struct drm_i915_private *dev_priv = dev->dev_private;
3800         const uint16_t *latencies;
3801
3802         if (INTEL_INFO(dev)->gen >= 9)
3803                 latencies = dev_priv->wm.skl_latency;
3804         else
3805                 latencies = to_i915(dev)->wm.spr_latency;
3806
3807         wm_latency_show(m, latencies);
3808
3809         return 0;
3810 }
3811
3812 static int cur_wm_latency_show(struct seq_file *m, void *data)
3813 {
3814         struct drm_device *dev = m->private;
3815         struct drm_i915_private *dev_priv = dev->dev_private;
3816         const uint16_t *latencies;
3817
3818         if (INTEL_INFO(dev)->gen >= 9)
3819                 latencies = dev_priv->wm.skl_latency;
3820         else
3821                 latencies = to_i915(dev)->wm.cur_latency;
3822
3823         wm_latency_show(m, latencies);
3824
3825         return 0;
3826 }
3827
3828 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3829 {
3830         struct drm_device *dev = inode->i_private;
3831
3832         if (HAS_GMCH_DISPLAY(dev))
3833                 return -ENODEV;
3834
3835         return single_open(file, pri_wm_latency_show, dev);
3836 }
3837
3838 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3839 {
3840         struct drm_device *dev = inode->i_private;
3841
3842         if (HAS_GMCH_DISPLAY(dev))
3843                 return -ENODEV;
3844
3845         return single_open(file, spr_wm_latency_show, dev);
3846 }
3847
3848 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3849 {
3850         struct drm_device *dev = inode->i_private;
3851
3852         if (HAS_GMCH_DISPLAY(dev))
3853                 return -ENODEV;
3854
3855         return single_open(file, cur_wm_latency_show, dev);
3856 }
3857
3858 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3859                                 size_t len, loff_t *offp, uint16_t wm[8])
3860 {
3861         struct seq_file *m = file->private_data;
3862         struct drm_device *dev = m->private;
3863         uint16_t new[8] = { 0 };
3864         int num_levels = ilk_wm_max_level(dev) + 1;
3865         int level;
3866         int ret;
3867         char tmp[32];
3868
3869         if (len >= sizeof(tmp))
3870                 return -EINVAL;
3871
3872         if (copy_from_user(tmp, ubuf, len))
3873                 return -EFAULT;
3874
3875         tmp[len] = '\0';
3876
3877         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3878                      &new[0], &new[1], &new[2], &new[3],
3879                      &new[4], &new[5], &new[6], &new[7]);
3880         if (ret != num_levels)
3881                 return -EINVAL;
3882
3883         drm_modeset_lock_all(dev);
3884
3885         for (level = 0; level < num_levels; level++)
3886                 wm[level] = new[level];
3887
3888         drm_modeset_unlock_all(dev);
3889
3890         return len;
3891 }
3892
3893
3894 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3895                                     size_t len, loff_t *offp)
3896 {
3897         struct seq_file *m = file->private_data;
3898         struct drm_device *dev = m->private;
3899         struct drm_i915_private *dev_priv = dev->dev_private;
3900         uint16_t *latencies;
3901
3902         if (INTEL_INFO(dev)->gen >= 9)
3903                 latencies = dev_priv->wm.skl_latency;
3904         else
3905                 latencies = to_i915(dev)->wm.pri_latency;
3906
3907         return wm_latency_write(file, ubuf, len, offp, latencies);
3908 }
3909
3910 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3911                                     size_t len, loff_t *offp)
3912 {
3913         struct seq_file *m = file->private_data;
3914         struct drm_device *dev = m->private;
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916         uint16_t *latencies;
3917
3918         if (INTEL_INFO(dev)->gen >= 9)
3919                 latencies = dev_priv->wm.skl_latency;
3920         else
3921                 latencies = to_i915(dev)->wm.spr_latency;
3922
3923         return wm_latency_write(file, ubuf, len, offp, latencies);
3924 }
3925
3926 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3927                                     size_t len, loff_t *offp)
3928 {
3929         struct seq_file *m = file->private_data;
3930         struct drm_device *dev = m->private;
3931         struct drm_i915_private *dev_priv = dev->dev_private;
3932         uint16_t *latencies;
3933
3934         if (INTEL_INFO(dev)->gen >= 9)
3935                 latencies = dev_priv->wm.skl_latency;
3936         else
3937                 latencies = to_i915(dev)->wm.cur_latency;
3938
3939         return wm_latency_write(file, ubuf, len, offp, latencies);
3940 }
3941
3942 static const struct file_operations i915_pri_wm_latency_fops = {
3943         .owner = THIS_MODULE,
3944         .open = pri_wm_latency_open,
3945         .read = seq_read,
3946         .llseek = seq_lseek,
3947         .release = single_release,
3948         .write = pri_wm_latency_write
3949 };
3950
3951 static const struct file_operations i915_spr_wm_latency_fops = {
3952         .owner = THIS_MODULE,
3953         .open = spr_wm_latency_open,
3954         .read = seq_read,
3955         .llseek = seq_lseek,
3956         .release = single_release,
3957         .write = spr_wm_latency_write
3958 };
3959
3960 static const struct file_operations i915_cur_wm_latency_fops = {
3961         .owner = THIS_MODULE,
3962         .open = cur_wm_latency_open,
3963         .read = seq_read,
3964         .llseek = seq_lseek,
3965         .release = single_release,
3966         .write = cur_wm_latency_write
3967 };
3968
3969 static int
3970 i915_wedged_get(void *data, u64 *val)
3971 {
3972         struct drm_device *dev = data;
3973         struct drm_i915_private *dev_priv = dev->dev_private;
3974
3975         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3976
3977         return 0;
3978 }
3979
3980 static int
3981 i915_wedged_set(void *data, u64 val)
3982 {
3983         struct drm_device *dev = data;
3984         struct drm_i915_private *dev_priv = dev->dev_private;
3985
3986         /*
3987          * There is no safeguard against this debugfs entry colliding
3988          * with the hangcheck calling same i915_handle_error() in
3989          * parallel, causing an explosion. For now we assume that the
3990          * test harness is responsible enough not to inject gpu hangs
3991          * while it is writing to 'i915_wedged'
3992          */
3993
3994         if (i915_reset_in_progress(&dev_priv->gpu_error))
3995                 return -EAGAIN;
3996
3997         intel_runtime_pm_get(dev_priv);
3998
3999         i915_handle_error(dev, val,
4000                           "Manually setting wedged to %llu", val);
4001
4002         intel_runtime_pm_put(dev_priv);
4003
4004         return 0;
4005 }
4006
4007 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4008                         i915_wedged_get, i915_wedged_set,
4009                         "%llu\n");
4010
4011 static int
4012 i915_ring_stop_get(void *data, u64 *val)
4013 {
4014         struct drm_device *dev = data;
4015         struct drm_i915_private *dev_priv = dev->dev_private;
4016
4017         *val = dev_priv->gpu_error.stop_rings;
4018
4019         return 0;
4020 }
4021
4022 static int
4023 i915_ring_stop_set(void *data, u64 val)
4024 {
4025         struct drm_device *dev = data;
4026         struct drm_i915_private *dev_priv = dev->dev_private;
4027         int ret;
4028
4029         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4030
4031         ret = mutex_lock_interruptible(&dev->struct_mutex);
4032         if (ret)
4033                 return ret;
4034
4035         dev_priv->gpu_error.stop_rings = val;
4036         mutex_unlock(&dev->struct_mutex);
4037
4038         return 0;
4039 }
4040
4041 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4042                         i915_ring_stop_get, i915_ring_stop_set,
4043                         "0x%08llx\n");
4044
4045 static int
4046 i915_ring_missed_irq_get(void *data, u64 *val)
4047 {
4048         struct drm_device *dev = data;
4049         struct drm_i915_private *dev_priv = dev->dev_private;
4050
4051         *val = dev_priv->gpu_error.missed_irq_rings;
4052         return 0;
4053 }
4054
4055 static int
4056 i915_ring_missed_irq_set(void *data, u64 val)
4057 {
4058         struct drm_device *dev = data;
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         int ret;
4061
4062         /* Lock against concurrent debugfs callers */
4063         ret = mutex_lock_interruptible(&dev->struct_mutex);
4064         if (ret)
4065                 return ret;
4066         dev_priv->gpu_error.missed_irq_rings = val;
4067         mutex_unlock(&dev->struct_mutex);
4068
4069         return 0;
4070 }
4071
4072 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4073                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4074                         "0x%08llx\n");
4075
4076 static int
4077 i915_ring_test_irq_get(void *data, u64 *val)
4078 {
4079         struct drm_device *dev = data;
4080         struct drm_i915_private *dev_priv = dev->dev_private;
4081
4082         *val = dev_priv->gpu_error.test_irq_rings;
4083
4084         return 0;
4085 }
4086
4087 static int
4088 i915_ring_test_irq_set(void *data, u64 val)
4089 {
4090         struct drm_device *dev = data;
4091         struct drm_i915_private *dev_priv = dev->dev_private;
4092         int ret;
4093
4094         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4095
4096         /* Lock against concurrent debugfs callers */
4097         ret = mutex_lock_interruptible(&dev->struct_mutex);
4098         if (ret)
4099                 return ret;
4100
4101         dev_priv->gpu_error.test_irq_rings = val;
4102         mutex_unlock(&dev->struct_mutex);
4103
4104         return 0;
4105 }
4106
4107 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4108                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4109                         "0x%08llx\n");
4110
4111 #define DROP_UNBOUND 0x1
4112 #define DROP_BOUND 0x2
4113 #define DROP_RETIRE 0x4
4114 #define DROP_ACTIVE 0x8
4115 #define DROP_ALL (DROP_UNBOUND | \
4116                   DROP_BOUND | \
4117                   DROP_RETIRE | \
4118                   DROP_ACTIVE)
4119 static int
4120 i915_drop_caches_get(void *data, u64 *val)
4121 {
4122         *val = DROP_ALL;
4123
4124         return 0;
4125 }
4126
4127 static int
4128 i915_drop_caches_set(void *data, u64 val)
4129 {
4130         struct drm_device *dev = data;
4131         struct drm_i915_private *dev_priv = dev->dev_private;
4132         int ret;
4133
4134         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4135
4136         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4137          * on ioctls on -EAGAIN. */
4138         ret = mutex_lock_interruptible(&dev->struct_mutex);
4139         if (ret)
4140                 return ret;
4141
4142         if (val & DROP_ACTIVE) {
4143                 ret = i915_gpu_idle(dev);
4144                 if (ret)
4145                         goto unlock;
4146         }
4147
4148         if (val & (DROP_RETIRE | DROP_ACTIVE))
4149                 i915_gem_retire_requests(dev);
4150
4151         if (val & DROP_BOUND)
4152                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4153
4154         if (val & DROP_UNBOUND)
4155                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4156
4157 unlock:
4158         mutex_unlock(&dev->struct_mutex);
4159
4160         return ret;
4161 }
4162
4163 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4164                         i915_drop_caches_get, i915_drop_caches_set,
4165                         "0x%08llx\n");
4166
4167 static int
4168 i915_max_freq_get(void *data, u64 *val)
4169 {
4170         struct drm_device *dev = data;
4171         struct drm_i915_private *dev_priv = dev->dev_private;
4172         int ret;
4173
4174         if (INTEL_INFO(dev)->gen < 6)
4175                 return -ENODEV;
4176
4177         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4178
4179         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4180         if (ret)
4181                 return ret;
4182
4183         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4184         mutex_unlock(&dev_priv->rps.hw_lock);
4185
4186         return 0;
4187 }
4188
4189 static int
4190 i915_max_freq_set(void *data, u64 val)
4191 {
4192         struct drm_device *dev = data;
4193         struct drm_i915_private *dev_priv = dev->dev_private;
4194         u32 rp_state_cap, hw_max, hw_min;
4195         int ret;
4196
4197         if (INTEL_INFO(dev)->gen < 6)
4198                 return -ENODEV;
4199
4200         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4201
4202         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4203
4204         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4205         if (ret)
4206                 return ret;
4207
4208         /*
4209          * Turbo will still be enabled, but won't go above the set value.
4210          */
4211         if (IS_VALLEYVIEW(dev)) {
4212                 val = intel_freq_opcode(dev_priv, val);
4213
4214                 hw_max = dev_priv->rps.max_freq;
4215                 hw_min = dev_priv->rps.min_freq;
4216         } else {
4217                 val = intel_freq_opcode(dev_priv, val);
4218
4219                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4220                 hw_max = dev_priv->rps.max_freq;
4221                 hw_min = (rp_state_cap >> 16) & 0xff;
4222         }
4223
4224         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4225                 mutex_unlock(&dev_priv->rps.hw_lock);
4226                 return -EINVAL;
4227         }
4228
4229         dev_priv->rps.max_freq_softlimit = val;
4230
4231         intel_set_rps(dev, val);
4232
4233         mutex_unlock(&dev_priv->rps.hw_lock);
4234
4235         return 0;
4236 }
4237
4238 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4239                         i915_max_freq_get, i915_max_freq_set,
4240                         "%llu\n");
4241
4242 static int
4243 i915_min_freq_get(void *data, u64 *val)
4244 {
4245         struct drm_device *dev = data;
4246         struct drm_i915_private *dev_priv = dev->dev_private;
4247         int ret;
4248
4249         if (INTEL_INFO(dev)->gen < 6)
4250                 return -ENODEV;
4251
4252         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4253
4254         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4255         if (ret)
4256                 return ret;
4257
4258         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4259         mutex_unlock(&dev_priv->rps.hw_lock);
4260
4261         return 0;
4262 }
4263
4264 static int
4265 i915_min_freq_set(void *data, u64 val)
4266 {
4267         struct drm_device *dev = data;
4268         struct drm_i915_private *dev_priv = dev->dev_private;
4269         u32 rp_state_cap, hw_max, hw_min;
4270         int ret;
4271
4272         if (INTEL_INFO(dev)->gen < 6)
4273                 return -ENODEV;
4274
4275         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4276
4277         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4278
4279         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4280         if (ret)
4281                 return ret;
4282
4283         /*
4284          * Turbo will still be enabled, but won't go below the set value.
4285          */
4286         if (IS_VALLEYVIEW(dev)) {
4287                 val = intel_freq_opcode(dev_priv, val);
4288
4289                 hw_max = dev_priv->rps.max_freq;
4290                 hw_min = dev_priv->rps.min_freq;
4291         } else {
4292                 val = intel_freq_opcode(dev_priv, val);
4293
4294                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4295                 hw_max = dev_priv->rps.max_freq;
4296                 hw_min = (rp_state_cap >> 16) & 0xff;
4297         }
4298
4299         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4300                 mutex_unlock(&dev_priv->rps.hw_lock);
4301                 return -EINVAL;
4302         }
4303
4304         dev_priv->rps.min_freq_softlimit = val;
4305
4306         intel_set_rps(dev, val);
4307
4308         mutex_unlock(&dev_priv->rps.hw_lock);
4309
4310         return 0;
4311 }
4312
4313 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4314                         i915_min_freq_get, i915_min_freq_set,
4315                         "%llu\n");
4316
4317 static int
4318 i915_cache_sharing_get(void *data, u64 *val)
4319 {
4320         struct drm_device *dev = data;
4321         struct drm_i915_private *dev_priv = dev->dev_private;
4322         u32 snpcr;
4323         int ret;
4324
4325         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4326                 return -ENODEV;
4327
4328         ret = mutex_lock_interruptible(&dev->struct_mutex);
4329         if (ret)
4330                 return ret;
4331         intel_runtime_pm_get(dev_priv);
4332
4333         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4334
4335         intel_runtime_pm_put(dev_priv);
4336         mutex_unlock(&dev_priv->dev->struct_mutex);
4337
4338         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4339
4340         return 0;
4341 }
4342
4343 static int
4344 i915_cache_sharing_set(void *data, u64 val)
4345 {
4346         struct drm_device *dev = data;
4347         struct drm_i915_private *dev_priv = dev->dev_private;
4348         u32 snpcr;
4349
4350         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4351                 return -ENODEV;
4352
4353         if (val > 3)
4354                 return -EINVAL;
4355
4356         intel_runtime_pm_get(dev_priv);
4357         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4358
4359         /* Update the cache sharing policy here as well */
4360         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4361         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4362         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4363         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4364
4365         intel_runtime_pm_put(dev_priv);
4366         return 0;
4367 }
4368
4369 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4370                         i915_cache_sharing_get, i915_cache_sharing_set,
4371                         "%llu\n");
4372
4373 static int i915_forcewake_open(struct inode *inode, struct file *file)
4374 {
4375         struct drm_device *dev = inode->i_private;
4376         struct drm_i915_private *dev_priv = dev->dev_private;
4377
4378         if (INTEL_INFO(dev)->gen < 6)
4379                 return 0;
4380
4381         intel_runtime_pm_get(dev_priv);
4382         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4383
4384         return 0;
4385 }
4386
4387 static int i915_forcewake_release(struct inode *inode, struct file *file)
4388 {
4389         struct drm_device *dev = inode->i_private;
4390         struct drm_i915_private *dev_priv = dev->dev_private;
4391
4392         if (INTEL_INFO(dev)->gen < 6)
4393                 return 0;
4394
4395         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4396         intel_runtime_pm_put(dev_priv);
4397
4398         return 0;
4399 }
4400
4401 static const struct file_operations i915_forcewake_fops = {
4402         .owner = THIS_MODULE,
4403         .open = i915_forcewake_open,
4404         .release = i915_forcewake_release,
4405 };
4406
4407 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4408 {
4409         struct drm_device *dev = minor->dev;
4410         struct dentry *ent;
4411
4412         ent = debugfs_create_file("i915_forcewake_user",
4413                                   S_IRUSR,
4414                                   root, dev,
4415                                   &i915_forcewake_fops);
4416         if (!ent)
4417                 return -ENOMEM;
4418
4419         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4420 }
4421
4422 static int i915_debugfs_create(struct dentry *root,
4423                                struct drm_minor *minor,
4424                                const char *name,
4425                                const struct file_operations *fops)
4426 {
4427         struct drm_device *dev = minor->dev;
4428         struct dentry *ent;
4429
4430         ent = debugfs_create_file(name,
4431                                   S_IRUGO | S_IWUSR,
4432                                   root, dev,
4433                                   fops);
4434         if (!ent)
4435                 return -ENOMEM;
4436
4437         return drm_add_fake_info_node(minor, ent, fops);
4438 }
4439
4440 static const struct drm_info_list i915_debugfs_list[] = {
4441         {"i915_capabilities", i915_capabilities, 0},
4442         {"i915_gem_objects", i915_gem_object_info, 0},
4443         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4444         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4445         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4446         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4447         {"i915_gem_stolen", i915_gem_stolen_list_info },
4448         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4449         {"i915_gem_request", i915_gem_request_info, 0},
4450         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4451         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4452         {"i915_gem_interrupt", i915_interrupt_info, 0},
4453         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4454         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4455         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4456         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4457         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4458         {"i915_frequency_info", i915_frequency_info, 0},
4459         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4460         {"i915_drpc_info", i915_drpc_info, 0},
4461         {"i915_emon_status", i915_emon_status, 0},
4462         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4463         {"i915_fbc_status", i915_fbc_status, 0},
4464         {"i915_ips_status", i915_ips_status, 0},
4465         {"i915_sr_status", i915_sr_status, 0},
4466         {"i915_opregion", i915_opregion, 0},
4467         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4468         {"i915_context_status", i915_context_status, 0},
4469         {"i915_dump_lrc", i915_dump_lrc, 0},
4470         {"i915_execlists", i915_execlists, 0},
4471         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4472         {"i915_swizzle_info", i915_swizzle_info, 0},
4473         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4474         {"i915_llc", i915_llc, 0},
4475         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4476         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4477         {"i915_energy_uJ", i915_energy_uJ, 0},
4478         {"i915_pc8_status", i915_pc8_status, 0},
4479         {"i915_power_domain_info", i915_power_domain_info, 0},
4480         {"i915_display_info", i915_display_info, 0},
4481         {"i915_semaphore_status", i915_semaphore_status, 0},
4482         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4483         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4484         {"i915_wa_registers", i915_wa_registers, 0},
4485         {"i915_ddb_info", i915_ddb_info, 0},
4486 };
4487 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4488
4489 static const struct i915_debugfs_files {
4490         const char *name;
4491         const struct file_operations *fops;
4492 } i915_debugfs_files[] = {
4493         {"i915_wedged", &i915_wedged_fops},
4494         {"i915_max_freq", &i915_max_freq_fops},
4495         {"i915_min_freq", &i915_min_freq_fops},
4496         {"i915_cache_sharing", &i915_cache_sharing_fops},
4497         {"i915_ring_stop", &i915_ring_stop_fops},
4498         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4499         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4500         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4501         {"i915_error_state", &i915_error_state_fops},
4502         {"i915_next_seqno", &i915_next_seqno_fops},
4503         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4504         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4505         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4506         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4507         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4508 };
4509
4510 void intel_display_crc_init(struct drm_device *dev)
4511 {
4512         struct drm_i915_private *dev_priv = dev->dev_private;
4513         enum pipe pipe;
4514
4515         for_each_pipe(dev_priv, pipe) {
4516                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4517
4518                 pipe_crc->opened = false;
4519                 spin_lock_init(&pipe_crc->lock);
4520                 init_waitqueue_head(&pipe_crc->wq);
4521         }
4522 }
4523
4524 int i915_debugfs_init(struct drm_minor *minor)
4525 {
4526         int ret, i;
4527
4528         ret = i915_forcewake_create(minor->debugfs_root, minor);
4529         if (ret)
4530                 return ret;
4531
4532         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4533                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4534                 if (ret)
4535                         return ret;
4536         }
4537
4538         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4539                 ret = i915_debugfs_create(minor->debugfs_root, minor,
4540                                           i915_debugfs_files[i].name,
4541                                           i915_debugfs_files[i].fops);
4542                 if (ret)
4543                         return ret;
4544         }
4545
4546         return drm_debugfs_create_files(i915_debugfs_list,
4547                                         I915_DEBUGFS_ENTRIES,
4548                                         minor->debugfs_root, minor);
4549 }
4550
4551 void i915_debugfs_cleanup(struct drm_minor *minor)
4552 {
4553         int i;
4554
4555         drm_debugfs_remove_files(i915_debugfs_list,
4556                                  I915_DEBUGFS_ENTRIES, minor);
4557
4558         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4559                                  1, minor);
4560
4561         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4562                 struct drm_info_list *info_list =
4563                         (struct drm_info_list *)&i915_pipe_crc_data[i];
4564
4565                 drm_debugfs_remove_files(info_list, 1, minor);
4566         }
4567
4568         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4569                 struct drm_info_list *info_list =
4570                         (struct drm_info_list *) i915_debugfs_files[i].fops;
4571
4572                 drm_debugfs_remove_files(info_list, 1, minor);
4573         }
4574 }