drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (i915_gem_obj_is_pinned(obj))
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct i915_vma *vma;
 124         int pin_count = 0;
 125
 126         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
 127                    &obj->base,
 128                    get_pin_flag(obj),
 129                    get_tiling_flag(obj),
 130                    get_global_flag(obj),
 131                    obj->base.size / 1024,
 132                    obj->base.read_domains,
 133                    obj->base.write_domain,
 134                    i915_gem_request_get_seqno(obj->last_read_req),
 135                    i915_gem_request_get_seqno(obj->last_write_req),
 136                    i915_gem_request_get_seqno(obj->last_fenced_req),
 137                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 138                    obj->dirty ? " dirty" : "",
 139                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 140         if (obj->base.name)
 141                 seq_printf(m, " (name: %d)", obj->base.name);
 142         list_for_each_entry(vma, &obj->vma_list, vma_link)
 143                 if (vma->pin_count > 0)
 144                         pin_count++;
 145                 seq_printf(m, " (pinned x %d)", pin_count);
 146         if (obj->pin_display)
 147                 seq_printf(m, " (display)");
 148         if (obj->fence_reg != I915_FENCE_REG_NONE)
 149                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 150         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 151                 if (!i915_is_ggtt(vma->vm))
 152                         seq_puts(m, " (pp");
 153                 else
 154                         seq_puts(m, " (g");
 155                 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
 156                            vma->node.start, vma->node.size,
 157                            vma->ggtt_view.type);
 158         }
 159         if (obj->stolen)
 160                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 161         if (obj->pin_mappable || obj->fault_mappable) {
 162                 char s[3], *t = s;
 163                 if (obj->pin_mappable)
 164                         *t++ = 'p';
 165                 if (obj->fault_mappable)
 166                         *t++ = 'f';
 167                 *t = '\0';
 168                 seq_printf(m, " (%s mappable)", s);
 169         }
 170         if (obj->last_read_req != NULL)
 171                 seq_printf(m, " (%s)",
 172                            i915_gem_request_get_ring(obj->last_read_req)->name);
 173         if (obj->frontbuffer_bits)
 174                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 175 }
 176
 177 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 178 {
 179         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 180         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 181         seq_putc(m, ' ');
 182 }
 183
 184 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 185 {
 186         struct drm_info_node *node = m->private;
 187         uintptr_t list = (uintptr_t) node->info_ent->data;
 188         struct list_head *head;
 189         struct drm_device *dev = node->minor->dev;
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         struct i915_address_space *vm = &dev_priv->gtt.base;
 192         struct i915_vma *vma;
 193         size_t total_obj_size, total_gtt_size;
 194         int count, ret;
 195
 196         ret = mutex_lock_interruptible(&dev->struct_mutex);
 197         if (ret)
 198                 return ret;
 199
 200         /* FIXME: the user of this interface might want more than just GGTT */
 201         switch (list) {
 202         case ACTIVE_LIST:
 203                 seq_puts(m, "Active:\n");
 204                 head = &vm->active_list;
 205                 break;
 206         case INACTIVE_LIST:
 207                 seq_puts(m, "Inactive:\n");
 208                 head = &vm->inactive_list;
 209                 break;
 210         default:
 211                 mutex_unlock(&dev->struct_mutex);
 212                 return -EINVAL;
 213         }
 214
 215         total_obj_size = total_gtt_size = count = 0;
 216         list_for_each_entry(vma, head, mm_list) {
 217                 seq_printf(m, "   ");
 218                 describe_obj(m, vma->obj);
 219                 seq_printf(m, "\n");
 220                 total_obj_size += vma->obj->base.size;
 221                 total_gtt_size += vma->node.size;
 222                 count++;
 223         }
 224         mutex_unlock(&dev->struct_mutex);
 225
 226         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 227                    count, total_obj_size, total_gtt_size);
 228         return 0;
 229 }
 230
 231 static int obj_rank_by_stolen(void *priv,
 232                               struct list_head *A, struct list_head *B)
 233 {
 234         struct drm_i915_gem_object *a =
 235                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 236         struct drm_i915_gem_object *b =
 237                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 238
 239         return a->stolen->start - b->stolen->start;
 240 }
 241
 242 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 243 {
 244         struct drm_info_node *node = m->private;
 245         struct drm_device *dev = node->minor->dev;
 246         struct drm_i915_private *dev_priv = dev->dev_private;
 247         struct drm_i915_gem_object *obj;
 248         size_t total_obj_size, total_gtt_size;
 249         LIST_HEAD(stolen);
 250         int count, ret;
 251
 252         ret = mutex_lock_interruptible(&dev->struct_mutex);
 253         if (ret)
 254                 return ret;
 255
 256         total_obj_size = total_gtt_size = count = 0;
 257         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 258                 if (obj->stolen == NULL)
 259                         continue;
 260
 261                 list_add(&obj->obj_exec_link, &stolen);
 262
 263                 total_obj_size += obj->base.size;
 264                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 265                 count++;
 266         }
 267         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 268                 if (obj->stolen == NULL)
 269                         continue;
 270
 271                 list_add(&obj->obj_exec_link, &stolen);
 272
 273                 total_obj_size += obj->base.size;
 274                 count++;
 275         }
 276         list_sort(NULL, &stolen, obj_rank_by_stolen);
 277         seq_puts(m, "Stolen:\n");
 278         while (!list_empty(&stolen)) {
 279                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 280                 seq_puts(m, "   ");
 281                 describe_obj(m, obj);
 282                 seq_putc(m, '\n');
 283                 list_del_init(&obj->obj_exec_link);
 284         }
 285         mutex_unlock(&dev->struct_mutex);
 286
 287         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 288                    count, total_obj_size, total_gtt_size);
 289         return 0;
 290 }
 291
 292 #define count_objects(list, member) do { \
 293         list_for_each_entry(obj, list, member) { \
 294                 size += i915_gem_obj_ggtt_size(obj); \
 295                 ++count; \
 296                 if (obj->map_and_fenceable) { \
 297                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 298                         ++mappable_count; \
 299                 } \
 300         } \
 301 } while (0)
 302
 303 struct file_stats {
 304         struct drm_i915_file_private *file_priv;
 305         int count;
 306         size_t total, unbound;
 307         size_t global, shared;
 308         size_t active, inactive;
 309 };
 310
 311 static int per_file_stats(int id, void *ptr, void *data)
 312 {
 313         struct drm_i915_gem_object *obj = ptr;
 314         struct file_stats *stats = data;
 315         struct i915_vma *vma;
 316
 317         stats->count++;
 318         stats->total += obj->base.size;
 319
 320         if (obj->base.name || obj->base.dma_buf)
 321                 stats->shared += obj->base.size;
 322
 323         if (USES_FULL_PPGTT(obj->base.dev)) {
 324                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 325                         struct i915_hw_ppgtt *ppgtt;
 326
 327                         if (!drm_mm_node_allocated(&vma->node))
 328                                 continue;
 329
 330                         if (i915_is_ggtt(vma->vm)) {
 331                                 stats->global += obj->base.size;
 332                                 continue;
 333                         }
 334
 335                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 336                         if (ppgtt->file_priv != stats->file_priv)
 337                                 continue;
 338
 339                         if (obj->active) /* XXX per-vma statistic */
 340                                 stats->active += obj->base.size;
 341                         else
 342                                 stats->inactive += obj->base.size;
 343
 344                         return 0;
 345                 }
 346         } else {
 347                 if (i915_gem_obj_ggtt_bound(obj)) {
 348                         stats->global += obj->base.size;
 349                         if (obj->active)
 350                                 stats->active += obj->base.size;
 351                         else
 352                                 stats->inactive += obj->base.size;
 353                         return 0;
 354                 }
 355         }
 356
 357         if (!list_empty(&obj->global_list))
 358                 stats->unbound += obj->base.size;
 359
 360         return 0;
 361 }
 362
 363 #define print_file_stats(m, name, stats) \
 364         seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
 365                    name, \
 366                    stats.count, \
 367                    stats.total, \
 368                    stats.active, \
 369                    stats.inactive, \
 370                    stats.global, \
 371                    stats.shared, \
 372                    stats.unbound)
 373
 374 static void print_batch_pool_stats(struct seq_file *m,
 375                                    struct drm_i915_private *dev_priv)
 376 {
 377         struct drm_i915_gem_object *obj;
 378         struct file_stats stats;
 379
 380         memset(&stats, 0, sizeof(stats));
 381
 382         list_for_each_entry(obj,
 383                             &dev_priv->mm.batch_pool.cache_list,
 384                             batch_pool_list)
 385                 per_file_stats(0, obj, &stats);
 386
 387         print_file_stats(m, "batch pool", stats);
 388 }
 389
 390 #define count_vmas(list, member) do { \
 391         list_for_each_entry(vma, list, member) { \
 392                 size += i915_gem_obj_ggtt_size(vma->obj); \
 393                 ++count; \
 394                 if (vma->obj->map_and_fenceable) { \
 395                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 396                         ++mappable_count; \
 397                 } \
 398         } \
 399 } while (0)
 400
 401 static int i915_gem_object_info(struct seq_file *m, void* data)
 402 {
 403         struct drm_info_node *node = m->private;
 404         struct drm_device *dev = node->minor->dev;
 405         struct drm_i915_private *dev_priv = dev->dev_private;
 406         u32 count, mappable_count, purgeable_count;
 407         size_t size, mappable_size, purgeable_size;
 408         struct drm_i915_gem_object *obj;
 409         struct i915_address_space *vm = &dev_priv->gtt.base;
 410         struct drm_file *file;
 411         struct i915_vma *vma;
 412         int ret;
 413
 414         ret = mutex_lock_interruptible(&dev->struct_mutex);
 415         if (ret)
 416                 return ret;
 417
 418         seq_printf(m, "%u objects, %zu bytes\n",
 419                    dev_priv->mm.object_count,
 420                    dev_priv->mm.object_memory);
 421
 422         size = count = mappable_size = mappable_count = 0;
 423         count_objects(&dev_priv->mm.bound_list, global_list);
 424         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 425                    count, mappable_count, size, mappable_size);
 426
 427         size = count = mappable_size = mappable_count = 0;
 428         count_vmas(&vm->active_list, mm_list);
 429         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 430                    count, mappable_count, size, mappable_size);
 431
 432         size = count = mappable_size = mappable_count = 0;
 433         count_vmas(&vm->inactive_list, mm_list);
 434         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 435                    count, mappable_count, size, mappable_size);
 436
 437         size = count = purgeable_size = purgeable_count = 0;
 438         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 439                 size += obj->base.size, ++count;
 440                 if (obj->madv == I915_MADV_DONTNEED)
 441                         purgeable_size += obj->base.size, ++purgeable_count;
 442         }
 443         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 444
 445         size = count = mappable_size = mappable_count = 0;
 446         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 447                 if (obj->fault_mappable) {
 448                         size += i915_gem_obj_ggtt_size(obj);
 449                         ++count;
 450                 }
 451                 if (obj->pin_mappable) {
 452                         mappable_size += i915_gem_obj_ggtt_size(obj);
 453                         ++mappable_count;
 454                 }
 455                 if (obj->madv == I915_MADV_DONTNEED) {
 456                         purgeable_size += obj->base.size;
 457                         ++purgeable_count;
 458                 }
 459         }
 460         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 461                    purgeable_count, purgeable_size);
 462         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 463                    mappable_count, mappable_size);
 464         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 465                    count, size);
 466
 467         seq_printf(m, "%zu [%lu] gtt total\n",
 468                    dev_priv->gtt.base.total,
 469                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 470
 471         seq_putc(m, '\n');
 472         print_batch_pool_stats(m, dev_priv);
 473
 474         seq_putc(m, '\n');
 475         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 476                 struct file_stats stats;
 477                 struct task_struct *task;
 478
 479                 memset(&stats, 0, sizeof(stats));
 480                 stats.file_priv = file->driver_priv;
 481                 spin_lock(&file->table_lock);
 482                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 483                 spin_unlock(&file->table_lock);
 484                 /*
 485                  * Although we have a valid reference on file->pid, that does
 486                  * not guarantee that the task_struct who called get_pid() is
 487                  * still alive (e.g. get_pid(current) => fork() => exit()).
 488                  * Therefore, we need to protect this ->comm access using RCU.
 489                  */
 490                 rcu_read_lock();
 491                 task = pid_task(file->pid, PIDTYPE_PID);
 492                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 493                 rcu_read_unlock();
 494         }
 495
 496         mutex_unlock(&dev->struct_mutex);
 497
 498         return 0;
 499 }
 500
 501 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 502 {
 503         struct drm_info_node *node = m->private;
 504         struct drm_device *dev = node->minor->dev;
 505         uintptr_t list = (uintptr_t) node->info_ent->data;
 506         struct drm_i915_private *dev_priv = dev->dev_private;
 507         struct drm_i915_gem_object *obj;
 508         size_t total_obj_size, total_gtt_size;
 509         int count, ret;
 510
 511         ret = mutex_lock_interruptible(&dev->struct_mutex);
 512         if (ret)
 513                 return ret;
 514
 515         total_obj_size = total_gtt_size = count = 0;
 516         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 517                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 518                         continue;
 519
 520                 seq_puts(m, "   ");
 521                 describe_obj(m, obj);
 522                 seq_putc(m, '\n');
 523                 total_obj_size += obj->base.size;
 524                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 525                 count++;
 526         }
 527
 528         mutex_unlock(&dev->struct_mutex);
 529
 530         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 531                    count, total_obj_size, total_gtt_size);
 532
 533         return 0;
 534 }
 535
 536 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 537 {
 538         struct drm_info_node *node = m->private;
 539         struct drm_device *dev = node->minor->dev;
 540         struct drm_i915_private *dev_priv = dev->dev_private;
 541         struct intel_crtc *crtc;
 542         int ret;
 543
 544         ret = mutex_lock_interruptible(&dev->struct_mutex);
 545         if (ret)
 546                 return ret;
 547
 548         for_each_intel_crtc(dev, crtc) {
 549                 const char pipe = pipe_name(crtc->pipe);
 550                 const char plane = plane_name(crtc->plane);
 551                 struct intel_unpin_work *work;
 552
 553                 spin_lock_irq(&dev->event_lock);
 554                 work = crtc->unpin_work;
 555                 if (work == NULL) {
 556                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 557                                    pipe, plane);
 558                 } else {
 559                         u32 addr;
 560
 561                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 562                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 563                                            pipe, plane);
 564                         } else {
 565                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 566                                            pipe, plane);
 567                         }
 568                         if (work->flip_queued_req) {
 569                                 struct intel_engine_cs *ring =
 570                                         i915_gem_request_get_ring(work->flip_queued_req);
 571
 572                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 573                                            ring->name,
 574                                            i915_gem_request_get_seqno(work->flip_queued_req),
 575                                            dev_priv->next_seqno,
 576                                            ring->get_seqno(ring, true),
 577                                            i915_gem_request_completed(work->flip_queued_req, true));
 578                         } else
 579                                 seq_printf(m, "Flip not associated with any ring\n");
 580                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 581                                    work->flip_queued_vblank,
 582                                    work->flip_ready_vblank,
 583                                    drm_vblank_count(dev, crtc->pipe));
 584                         if (work->enable_stall_check)
 585                                 seq_puts(m, "Stall check enabled, ");
 586                         else
 587                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 588                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 589
 590                         if (INTEL_INFO(dev)->gen >= 4)
 591                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 592                         else
 593                                 addr = I915_READ(DSPADDR(crtc->plane));
 594                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 595
 596                         if (work->pending_flip_obj) {
 597                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 598                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 599                         }
 600                 }
 601                 spin_unlock_irq(&dev->event_lock);
 602         }
 603
 604         mutex_unlock(&dev->struct_mutex);
 605
 606         return 0;
 607 }
 608
 609 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 610 {
 611         struct drm_info_node *node = m->private;
 612         struct drm_device *dev = node->minor->dev;
 613         struct drm_i915_private *dev_priv = dev->dev_private;
 614         struct drm_i915_gem_object *obj;
 615         int count = 0;
 616         int ret;
 617
 618         ret = mutex_lock_interruptible(&dev->struct_mutex);
 619         if (ret)
 620                 return ret;
 621
 622         seq_puts(m, "cache:\n");
 623         list_for_each_entry(obj,
 624                             &dev_priv->mm.batch_pool.cache_list,
 625                             batch_pool_list) {
 626                 seq_puts(m, "   ");
 627                 describe_obj(m, obj);
 628                 seq_putc(m, '\n');
 629                 count++;
 630         }
 631
 632         seq_printf(m, "total: %d\n", count);
 633
 634         mutex_unlock(&dev->struct_mutex);
 635
 636         return 0;
 637 }
 638
 639 static int i915_gem_request_info(struct seq_file *m, void *data)
 640 {
 641         struct drm_info_node *node = m->private;
 642         struct drm_device *dev = node->minor->dev;
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         struct intel_engine_cs *ring;
 645         struct drm_i915_gem_request *gem_request;
 646         int ret, count, i;
 647
 648         ret = mutex_lock_interruptible(&dev->struct_mutex);
 649         if (ret)
 650                 return ret;
 651
 652         count = 0;
 653         for_each_ring(ring, dev_priv, i) {
 654                 if (list_empty(&ring->request_list))
 655                         continue;
 656
 657                 seq_printf(m, "%s requests:\n", ring->name);
 658                 list_for_each_entry(gem_request,
 659                                     &ring->request_list,
 660                                     list) {
 661                         seq_printf(m, "    %x @ %d\n",
 662                                    gem_request->seqno,
 663                                    (int) (jiffies - gem_request->emitted_jiffies));
 664                 }
 665                 count++;
 666         }
 667         mutex_unlock(&dev->struct_mutex);
 668
 669         if (count == 0)
 670                 seq_puts(m, "No requests\n");
 671
 672         return 0;
 673 }
 674
 675 static void i915_ring_seqno_info(struct seq_file *m,
 676                                  struct intel_engine_cs *ring)
 677 {
 678         if (ring->get_seqno) {
 679                 seq_printf(m, "Current sequence (%s): %x\n",
 680                            ring->name, ring->get_seqno(ring, false));
 681         }
 682 }
 683
 684 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 685 {
 686         struct drm_info_node *node = m->private;
 687         struct drm_device *dev = node->minor->dev;
 688         struct drm_i915_private *dev_priv = dev->dev_private;
 689         struct intel_engine_cs *ring;
 690         int ret, i;
 691
 692         ret = mutex_lock_interruptible(&dev->struct_mutex);
 693         if (ret)
 694                 return ret;
 695         intel_runtime_pm_get(dev_priv);
 696
 697         for_each_ring(ring, dev_priv, i)
 698                 i915_ring_seqno_info(m, ring);
 699
 700         intel_runtime_pm_put(dev_priv);
 701         mutex_unlock(&dev->struct_mutex);
 702
 703         return 0;
 704 }
 705
 706
 707 static int i915_interrupt_info(struct seq_file *m, void *data)
 708 {
 709         struct drm_info_node *node = m->private;
 710         struct drm_device *dev = node->minor->dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         struct intel_engine_cs *ring;
 713         int ret, i, pipe;
 714
 715         ret = mutex_lock_interruptible(&dev->struct_mutex);
 716         if (ret)
 717                 return ret;
 718         intel_runtime_pm_get(dev_priv);
 719
 720         if (IS_CHERRYVIEW(dev)) {
 721                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 722                            I915_READ(GEN8_MASTER_IRQ));
 723
 724                 seq_printf(m, "Display IER:\t%08x\n",
 725                            I915_READ(VLV_IER));
 726                 seq_printf(m, "Display IIR:\t%08x\n",
 727                            I915_READ(VLV_IIR));
 728                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 729                            I915_READ(VLV_IIR_RW));
 730                 seq_printf(m, "Display IMR:\t%08x\n",
 731                            I915_READ(VLV_IMR));
 732                 for_each_pipe(dev_priv, pipe)
 733                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 734                                    pipe_name(pipe),
 735                                    I915_READ(PIPESTAT(pipe)));
 736
 737                 seq_printf(m, "Port hotplug:\t%08x\n",
 738                            I915_READ(PORT_HOTPLUG_EN));
 739                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 740                            I915_READ(VLV_DPFLIPSTAT));
 741                 seq_printf(m, "DPINVGTT:\t%08x\n",
 742                            I915_READ(DPINVGTT));
 743
 744                 for (i = 0; i < 4; i++) {
 745                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 746                                    i, I915_READ(GEN8_GT_IMR(i)));
 747                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 748                                    i, I915_READ(GEN8_GT_IIR(i)));
 749                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 750                                    i, I915_READ(GEN8_GT_IER(i)));
 751                 }
 752
 753                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 754                            I915_READ(GEN8_PCU_IMR));
 755                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 756                            I915_READ(GEN8_PCU_IIR));
 757                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 758                            I915_READ(GEN8_PCU_IER));
 759         } else if (INTEL_INFO(dev)->gen >= 8) {
 760                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 761                            I915_READ(GEN8_MASTER_IRQ));
 762
 763                 for (i = 0; i < 4; i++) {
 764                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 765                                    i, I915_READ(GEN8_GT_IMR(i)));
 766                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 767                                    i, I915_READ(GEN8_GT_IIR(i)));
 768                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 769                                    i, I915_READ(GEN8_GT_IER(i)));
 770                 }
 771
 772                 for_each_pipe(dev_priv, pipe) {
 773                         if (!intel_display_power_is_enabled(dev_priv,
 774                                                 POWER_DOMAIN_PIPE(pipe))) {
 775                                 seq_printf(m, "Pipe %c power disabled\n",
 776                                            pipe_name(pipe));
 777                                 continue;
 778                         }
 779                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 780                                    pipe_name(pipe),
 781                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 782                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 783                                    pipe_name(pipe),
 784                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 785                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 786                                    pipe_name(pipe),
 787                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 788                 }
 789
 790                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 791                            I915_READ(GEN8_DE_PORT_IMR));
 792                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 793                            I915_READ(GEN8_DE_PORT_IIR));
 794                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 795                            I915_READ(GEN8_DE_PORT_IER));
 796
 797                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 798                            I915_READ(GEN8_DE_MISC_IMR));
 799                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 800                            I915_READ(GEN8_DE_MISC_IIR));
 801                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 802                            I915_READ(GEN8_DE_MISC_IER));
 803
 804                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 805                            I915_READ(GEN8_PCU_IMR));
 806                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 807                            I915_READ(GEN8_PCU_IIR));
 808                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IER));
 810         } else if (IS_VALLEYVIEW(dev)) {
 811                 seq_printf(m, "Display IER:\t%08x\n",
 812                            I915_READ(VLV_IER));
 813                 seq_printf(m, "Display IIR:\t%08x\n",
 814                            I915_READ(VLV_IIR));
 815                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 816                            I915_READ(VLV_IIR_RW));
 817                 seq_printf(m, "Display IMR:\t%08x\n",
 818                            I915_READ(VLV_IMR));
 819                 for_each_pipe(dev_priv, pipe)
 820                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 821                                    pipe_name(pipe),
 822                                    I915_READ(PIPESTAT(pipe)));
 823
 824                 seq_printf(m, "Master IER:\t%08x\n",
 825                            I915_READ(VLV_MASTER_IER));
 826
 827                 seq_printf(m, "Render IER:\t%08x\n",
 828                            I915_READ(GTIER));
 829                 seq_printf(m, "Render IIR:\t%08x\n",
 830                            I915_READ(GTIIR));
 831                 seq_printf(m, "Render IMR:\t%08x\n",
 832                            I915_READ(GTIMR));
 833
 834                 seq_printf(m, "PM IER:\t\t%08x\n",
 835                            I915_READ(GEN6_PMIER));
 836                 seq_printf(m, "PM IIR:\t\t%08x\n",
 837                            I915_READ(GEN6_PMIIR));
 838                 seq_printf(m, "PM IMR:\t\t%08x\n",
 839                            I915_READ(GEN6_PMIMR));
 840
 841                 seq_printf(m, "Port hotplug:\t%08x\n",
 842                            I915_READ(PORT_HOTPLUG_EN));
 843                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 844                            I915_READ(VLV_DPFLIPSTAT));
 845                 seq_printf(m, "DPINVGTT:\t%08x\n",
 846                            I915_READ(DPINVGTT));
 847
 848         } else if (!HAS_PCH_SPLIT(dev)) {
 849                 seq_printf(m, "Interrupt enable:    %08x\n",
 850                            I915_READ(IER));
 851                 seq_printf(m, "Interrupt identity:  %08x\n",
 852                            I915_READ(IIR));
 853                 seq_printf(m, "Interrupt mask:      %08x\n",
 854                            I915_READ(IMR));
 855                 for_each_pipe(dev_priv, pipe)
 856                         seq_printf(m, "Pipe %c stat:         %08x\n",
 857                                    pipe_name(pipe),
 858                                    I915_READ(PIPESTAT(pipe)));
 859         } else {
 860                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 861                            I915_READ(DEIER));
 862                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 863                            I915_READ(DEIIR));
 864                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 865                            I915_READ(DEIMR));
 866                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 867                            I915_READ(SDEIER));
 868                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 869                            I915_READ(SDEIIR));
 870                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 871                            I915_READ(SDEIMR));
 872                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 873                            I915_READ(GTIER));
 874                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 875                            I915_READ(GTIIR));
 876                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 877                            I915_READ(GTIMR));
 878         }
 879         for_each_ring(ring, dev_priv, i) {
 880                 if (INTEL_INFO(dev)->gen >= 6) {
 881                         seq_printf(m,
 882                                    "Graphics Interrupt mask (%s):       %08x\n",
 883                                    ring->name, I915_READ_IMR(ring));
 884                 }
 885                 i915_ring_seqno_info(m, ring);
 886         }
 887         intel_runtime_pm_put(dev_priv);
 888         mutex_unlock(&dev->struct_mutex);
 889
 890         return 0;
 891 }
 892
 893 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 894 {
 895         struct drm_info_node *node = m->private;
 896         struct drm_device *dev = node->minor->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898         int i, ret;
 899
 900         ret = mutex_lock_interruptible(&dev->struct_mutex);
 901         if (ret)
 902                 return ret;
 903
 904         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 905         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 906         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 907                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 908
 909                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 910                            i, dev_priv->fence_regs[i].pin_count);
 911                 if (obj == NULL)
 912                         seq_puts(m, "unused");
 913                 else
 914                         describe_obj(m, obj);
 915                 seq_putc(m, '\n');
 916         }
 917
 918         mutex_unlock(&dev->struct_mutex);
 919         return 0;
 920 }
 921
 922 static int i915_hws_info(struct seq_file *m, void *data)
 923 {
 924         struct drm_info_node *node = m->private;
 925         struct drm_device *dev = node->minor->dev;
 926         struct drm_i915_private *dev_priv = dev->dev_private;
 927         struct intel_engine_cs *ring;
 928         const u32 *hws;
 929         int i;
 930
 931         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 932         hws = ring->status_page.page_addr;
 933         if (hws == NULL)
 934                 return 0;
 935
 936         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 937                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 938                            i * 4,
 939                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 940         }
 941         return 0;
 942 }
 943
 944 static ssize_t
 945 i915_error_state_write(struct file *filp,
 946                        const char __user *ubuf,
 947                        size_t cnt,
 948                        loff_t *ppos)
 949 {
 950         struct i915_error_state_file_priv *error_priv = filp->private_data;
 951         struct drm_device *dev = error_priv->dev;
 952         int ret;
 953
 954         DRM_DEBUG_DRIVER("Resetting error state\n");
 955
 956         ret = mutex_lock_interruptible(&dev->struct_mutex);
 957         if (ret)
 958                 return ret;
 959
 960         i915_destroy_error_state(dev);
 961         mutex_unlock(&dev->struct_mutex);
 962
 963         return cnt;
 964 }
 965
 966 static int i915_error_state_open(struct inode *inode, struct file *file)
 967 {
 968         struct drm_device *dev = inode->i_private;
 969         struct i915_error_state_file_priv *error_priv;
 970
 971         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 972         if (!error_priv)
 973                 return -ENOMEM;
 974
 975         error_priv->dev = dev;
 976
 977         i915_error_state_get(dev, error_priv);
 978
 979         file->private_data = error_priv;
 980
 981         return 0;
 982 }
 983
 984 static int i915_error_state_release(struct inode *inode, struct file *file)
 985 {
 986         struct i915_error_state_file_priv *error_priv = file->private_data;
 987
 988         i915_error_state_put(error_priv);
 989         kfree(error_priv);
 990
 991         return 0;
 992 }
 993
 994 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 995                                      size_t count, loff_t *pos)
 996 {
 997         struct i915_error_state_file_priv *error_priv = file->private_data;
 998         struct drm_i915_error_state_buf error_str;
 999         loff_t tmp_pos = 0;
1000         ssize_t ret_count = 0;
1001         int ret;
1002
1003         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1004         if (ret)
1005                 return ret;
1006
1007         ret = i915_error_state_to_str(&error_str, error_priv);
1008         if (ret)
1009                 goto out;
1010
1011         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1012                                             error_str.buf,
1013                                             error_str.bytes);
1014
1015         if (ret_count < 0)
1016                 ret = ret_count;
1017         else
1018                 *pos = error_str.start + ret_count;
1019 out:
1020         i915_error_state_buf_release(&error_str);
1021         return ret ?: ret_count;
1022 }
1023
1024 static const struct file_operations i915_error_state_fops = {
1025         .owner = THIS_MODULE,
1026         .open = i915_error_state_open,
1027         .read = i915_error_state_read,
1028         .write = i915_error_state_write,
1029         .llseek = default_llseek,
1030         .release = i915_error_state_release,
1031 };
1032
1033 static int
1034 i915_next_seqno_get(void *data, u64 *val)
1035 {
1036         struct drm_device *dev = data;
1037         struct drm_i915_private *dev_priv = dev->dev_private;
1038         int ret;
1039
1040         ret = mutex_lock_interruptible(&dev->struct_mutex);
1041         if (ret)
1042                 return ret;
1043
1044         *val = dev_priv->next_seqno;
1045         mutex_unlock(&dev->struct_mutex);
1046
1047         return 0;
1048 }
1049
1050 static int
1051 i915_next_seqno_set(void *data, u64 val)
1052 {
1053         struct drm_device *dev = data;
1054         int ret;
1055
1056         ret = mutex_lock_interruptible(&dev->struct_mutex);
1057         if (ret)
1058                 return ret;
1059
1060         ret = i915_gem_set_seqno(dev, val);
1061         mutex_unlock(&dev->struct_mutex);
1062
1063         return ret;
1064 }
1065
1066 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1067                         i915_next_seqno_get, i915_next_seqno_set,
1068                         "0x%llx\n");
1069
1070 static int i915_frequency_info(struct seq_file *m, void *unused)
1071 {
1072         struct drm_info_node *node = m->private;
1073         struct drm_device *dev = node->minor->dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         int ret = 0;
1076
1077         intel_runtime_pm_get(dev_priv);
1078
1079         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1080
1081         if (IS_GEN5(dev)) {
1082                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1083                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1084
1085                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1086                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1087                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1088                            MEMSTAT_VID_SHIFT);
1089                 seq_printf(m, "Current P-state: %d\n",
1090                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1091         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1092                    IS_BROADWELL(dev)) {
1093                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1094                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1095                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1096                 u32 rpmodectl, rpinclimit, rpdeclimit;
1097                 u32 rpstat, cagf, reqf;
1098                 u32 rpupei, rpcurup, rpprevup;
1099                 u32 rpdownei, rpcurdown, rpprevdown;
1100                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1101                 int max_freq;
1102
1103                 /* RPSTAT1 is in the GT power well */
1104                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1105                 if (ret)
1106                         goto out;
1107
1108                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1109
1110                 reqf = I915_READ(GEN6_RPNSWREQ);
1111                 reqf &= ~GEN6_TURBO_DISABLE;
1112                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1113                         reqf >>= 24;
1114                 else
1115                         reqf >>= 25;
1116                 reqf = intel_gpu_freq(dev_priv, reqf);
1117
1118                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1119                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1120                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1121
1122                 rpstat = I915_READ(GEN6_RPSTAT1);
1123                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1124                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1125                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1126                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1127                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1128                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1129                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1130                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1131                 else
1132                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1133                 cagf = intel_gpu_freq(dev_priv, cagf);
1134
1135                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1136                 mutex_unlock(&dev->struct_mutex);
1137
1138                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1139                         pm_ier = I915_READ(GEN6_PMIER);
1140                         pm_imr = I915_READ(GEN6_PMIMR);
1141                         pm_isr = I915_READ(GEN6_PMISR);
1142                         pm_iir = I915_READ(GEN6_PMIIR);
1143                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1144                 } else {
1145                         pm_ier = I915_READ(GEN8_GT_IER(2));
1146                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1147                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1148                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1149                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1150                 }
1151                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1152                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1153                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1154                 seq_printf(m, "Render p-state ratio: %d\n",
1155                            (gt_perf_status & 0xff00) >> 8);
1156                 seq_printf(m, "Render p-state VID: %d\n",
1157                            gt_perf_status & 0xff);
1158                 seq_printf(m, "Render p-state limit: %d\n",
1159                            rp_state_limits & 0xff);
1160                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1161                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1162                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1163                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1164                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1165                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1166                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1167                            GEN6_CURICONT_MASK);
1168                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1169                            GEN6_CURBSYTAVG_MASK);
1170                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1171                            GEN6_CURBSYTAVG_MASK);
1172                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1173                            GEN6_CURIAVG_MASK);
1174                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1175                            GEN6_CURBSYTAVG_MASK);
1176                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1177                            GEN6_CURBSYTAVG_MASK);
1178
1179                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1180                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1181                            intel_gpu_freq(dev_priv, max_freq));
1182
1183                 max_freq = (rp_state_cap & 0xff00) >> 8;
1184                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1185                            intel_gpu_freq(dev_priv, max_freq));
1186
1187                 max_freq = rp_state_cap & 0xff;
1188                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1189                            intel_gpu_freq(dev_priv, max_freq));
1190
1191                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1192                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1193         } else if (IS_VALLEYVIEW(dev)) {
1194                 u32 freq_sts;
1195
1196                 mutex_lock(&dev_priv->rps.hw_lock);
1197                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1198                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1199                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1200
1201                 seq_printf(m, "max GPU freq: %d MHz\n",
1202                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1203
1204                 seq_printf(m, "min GPU freq: %d MHz\n",
1205                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1206
1207                 seq_printf(m,
1208                            "efficient (RPe) frequency: %d MHz\n",
1209                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1210
1211                 seq_printf(m, "current GPU freq: %d MHz\n",
1212                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1213                 mutex_unlock(&dev_priv->rps.hw_lock);
1214         } else {
1215                 seq_puts(m, "no P-state info available\n");
1216         }
1217
1218 out:
1219         intel_runtime_pm_put(dev_priv);
1220         return ret;
1221 }
1222
1223 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1224 {
1225         struct drm_info_node *node = m->private;
1226         struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
1227         struct intel_engine_cs *ring;
1228         int i;
1229
1230         if (!i915.enable_hangcheck) {
1231                 seq_printf(m, "Hangcheck disabled\n");
1232                 return 0;
1233         }
1234
1235         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1236                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1237                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1238                                             jiffies));
1239         } else
1240                 seq_printf(m, "Hangcheck inactive\n");
1241
1242         for_each_ring(ring, dev_priv, i) {
1243                 seq_printf(m, "%s:\n", ring->name);
1244                 seq_printf(m, "\tseqno = %x [current %x]\n",
1245                            ring->hangcheck.seqno, ring->get_seqno(ring, false));
1246                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1247                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1248                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1249                            (long long)ring->hangcheck.acthd,
1250                            (long long)intel_ring_get_active_head(ring));
1251                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1252                            (long long)ring->hangcheck.max_acthd);
1253         }
1254
1255         return 0;
1256 }
1257
1258 static int ironlake_drpc_info(struct seq_file *m)
1259 {
1260         struct drm_info_node *node = m->private;
1261         struct drm_device *dev = node->minor->dev;
1262         struct drm_i915_private *dev_priv = dev->dev_private;
1263         u32 rgvmodectl, rstdbyctl;
1264         u16 crstandvid;
1265         int ret;
1266
1267         ret = mutex_lock_interruptible(&dev->struct_mutex);
1268         if (ret)
1269                 return ret;
1270         intel_runtime_pm_get(dev_priv);
1271
1272         rgvmodectl = I915_READ(MEMMODECTL);
1273         rstdbyctl = I915_READ(RSTDBYCTL);
1274         crstandvid = I915_READ16(CRSTANDVID);
1275
1276         intel_runtime_pm_put(dev_priv);
1277         mutex_unlock(&dev->struct_mutex);
1278
1279         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1280                    "yes" : "no");
1281         seq_printf(m, "Boost freq: %d\n",
1282                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1283                    MEMMODE_BOOST_FREQ_SHIFT);
1284         seq_printf(m, "HW control enabled: %s\n",
1285                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1286         seq_printf(m, "SW control enabled: %s\n",
1287                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1288         seq_printf(m, "Gated voltage change: %s\n",
1289                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1290         seq_printf(m, "Starting frequency: P%d\n",
1291                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1292         seq_printf(m, "Max P-state: P%d\n",
1293                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1294         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1295         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1296         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1297         seq_printf(m, "Render standby enabled: %s\n",
1298                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1299         seq_puts(m, "Current RS state: ");
1300         switch (rstdbyctl & RSX_STATUS_MASK) {
1301         case RSX_STATUS_ON:
1302                 seq_puts(m, "on\n");
1303                 break;
1304         case RSX_STATUS_RC1:
1305                 seq_puts(m, "RC1\n");
1306                 break;
1307         case RSX_STATUS_RC1E:
1308                 seq_puts(m, "RC1E\n");
1309                 break;
1310         case RSX_STATUS_RS1:
1311                 seq_puts(m, "RS1\n");
1312                 break;
1313         case RSX_STATUS_RS2:
1314                 seq_puts(m, "RS2 (RC6)\n");
1315                 break;
1316         case RSX_STATUS_RS3:
1317                 seq_puts(m, "RC3 (RC6+)\n");
1318                 break;
1319         default:
1320                 seq_puts(m, "unknown\n");
1321                 break;
1322         }
1323
1324         return 0;
1325 }
1326
1327 static int i915_forcewake_domains(struct seq_file *m, void *data)
1328 {
1329         struct drm_info_node *node = m->private;
1330         struct drm_device *dev = node->minor->dev;
1331         struct drm_i915_private *dev_priv = dev->dev_private;
1332         struct intel_uncore_forcewake_domain *fw_domain;
1333         int i;
1334
1335         spin_lock_irq(&dev_priv->uncore.lock);
1336         for_each_fw_domain(fw_domain, dev_priv, i) {
1337                 seq_printf(m, "%s.wake_count = %u\n",
1338                            intel_uncore_forcewake_domain_to_str(i),
1339                            fw_domain->wake_count);
1340         }
1341         spin_unlock_irq(&dev_priv->uncore.lock);
1342
1343         return 0;
1344 }
1345
1346 static int vlv_drpc_info(struct seq_file *m)
1347 {
1348         struct drm_info_node *node = m->private;
1349         struct drm_device *dev = node->minor->dev;
1350         struct drm_i915_private *dev_priv = dev->dev_private;
1351         u32 rpmodectl1, rcctl1, pw_status;
1352
1353         intel_runtime_pm_get(dev_priv);
1354
1355         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1356         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1357         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1358
1359         intel_runtime_pm_put(dev_priv);
1360
1361         seq_printf(m, "Video Turbo Mode: %s\n",
1362                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1363         seq_printf(m, "Turbo enabled: %s\n",
1364                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1365         seq_printf(m, "HW control enabled: %s\n",
1366                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1367         seq_printf(m, "SW control enabled: %s\n",
1368                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1369                           GEN6_RP_MEDIA_SW_MODE));
1370         seq_printf(m, "RC6 Enabled: %s\n",
1371                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1372                                         GEN6_RC_CTL_EI_MODE(1))));
1373         seq_printf(m, "Render Power Well: %s\n",
1374                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1375         seq_printf(m, "Media Power Well: %s\n",
1376                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1377
1378         seq_printf(m, "Render RC6 residency since boot: %u\n",
1379                    I915_READ(VLV_GT_RENDER_RC6));
1380         seq_printf(m, "Media RC6 residency since boot: %u\n",
1381                    I915_READ(VLV_GT_MEDIA_RC6));
1382
1383         return i915_forcewake_domains(m, NULL);
1384 }
1385
1386 static int gen6_drpc_info(struct seq_file *m)
1387 {
1388         struct drm_info_node *node = m->private;
1389         struct drm_device *dev = node->minor->dev;
1390         struct drm_i915_private *dev_priv = dev->dev_private;
1391         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1392         unsigned forcewake_count;
1393         int count = 0, ret;
1394
1395         ret = mutex_lock_interruptible(&dev->struct_mutex);
1396         if (ret)
1397                 return ret;
1398         intel_runtime_pm_get(dev_priv);
1399
1400         spin_lock_irq(&dev_priv->uncore.lock);
1401         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1402         spin_unlock_irq(&dev_priv->uncore.lock);
1403
1404         if (forcewake_count) {
1405                 seq_puts(m, "RC information inaccurate because somebody "
1406                             "holds a forcewake reference \n");
1407         } else {
1408                 /* NB: we cannot use forcewake, else we read the wrong values */
1409                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1410                         udelay(10);
1411                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1412         }
1413
1414         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1415         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1416
1417         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1418         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1419         mutex_unlock(&dev->struct_mutex);
1420         mutex_lock(&dev_priv->rps.hw_lock);
1421         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1422         mutex_unlock(&dev_priv->rps.hw_lock);
1423
1424         intel_runtime_pm_put(dev_priv);
1425
1426         seq_printf(m, "Video Turbo Mode: %s\n",
1427                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1428         seq_printf(m, "HW control enabled: %s\n",
1429                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1430         seq_printf(m, "SW control enabled: %s\n",
1431                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1432                           GEN6_RP_MEDIA_SW_MODE));
1433         seq_printf(m, "RC1e Enabled: %s\n",
1434                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1435         seq_printf(m, "RC6 Enabled: %s\n",
1436                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1437         seq_printf(m, "Deep RC6 Enabled: %s\n",
1438                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1439         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1440                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1441         seq_puts(m, "Current RC state: ");
1442         switch (gt_core_status & GEN6_RCn_MASK) {
1443         case GEN6_RC0:
1444                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1445                         seq_puts(m, "Core Power Down\n");
1446                 else
1447                         seq_puts(m, "on\n");
1448                 break;
1449         case GEN6_RC3:
1450                 seq_puts(m, "RC3\n");
1451                 break;
1452         case GEN6_RC6:
1453                 seq_puts(m, "RC6\n");
1454                 break;
1455         case GEN6_RC7:
1456                 seq_puts(m, "RC7\n");
1457                 break;
1458         default:
1459                 seq_puts(m, "Unknown\n");
1460                 break;
1461         }
1462
1463         seq_printf(m, "Core Power Down: %s\n",
1464                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1465
1466         /* Not exactly sure what this is */
1467         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1468                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1469         seq_printf(m, "RC6 residency since boot: %u\n",
1470                    I915_READ(GEN6_GT_GFX_RC6));
1471         seq_printf(m, "RC6+ residency since boot: %u\n",
1472                    I915_READ(GEN6_GT_GFX_RC6p));
1473         seq_printf(m, "RC6++ residency since boot: %u\n",
1474                    I915_READ(GEN6_GT_GFX_RC6pp));
1475
1476         seq_printf(m, "RC6   voltage: %dmV\n",
1477                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1478         seq_printf(m, "RC6+  voltage: %dmV\n",
1479                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1480         seq_printf(m, "RC6++ voltage: %dmV\n",
1481                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1482         return 0;
1483 }
1484
1485 static int i915_drpc_info(struct seq_file *m, void *unused)
1486 {
1487         struct drm_info_node *node = m->private;
1488         struct drm_device *dev = node->minor->dev;
1489
1490         if (IS_VALLEYVIEW(dev))
1491                 return vlv_drpc_info(m);
1492         else if (INTEL_INFO(dev)->gen >= 6)
1493                 return gen6_drpc_info(m);
1494         else
1495                 return ironlake_drpc_info(m);
1496 }
1497
1498 static int i915_fbc_status(struct seq_file *m, void *unused)
1499 {
1500         struct drm_info_node *node = m->private;
1501         struct drm_device *dev = node->minor->dev;
1502         struct drm_i915_private *dev_priv = dev->dev_private;
1503
1504         if (!HAS_FBC(dev)) {
1505                 seq_puts(m, "FBC unsupported on this chipset\n");
1506                 return 0;
1507         }
1508
1509         intel_runtime_pm_get(dev_priv);
1510
1511         if (intel_fbc_enabled(dev)) {
1512                 seq_puts(m, "FBC enabled\n");
1513         } else {
1514                 seq_puts(m, "FBC disabled: ");
1515                 switch (dev_priv->fbc.no_fbc_reason) {
1516                 case FBC_OK:
1517                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1518                         break;
1519                 case FBC_UNSUPPORTED:
1520                         seq_puts(m, "unsupported by this chipset");
1521                         break;
1522                 case FBC_NO_OUTPUT:
1523                         seq_puts(m, "no outputs");
1524                         break;
1525                 case FBC_STOLEN_TOO_SMALL:
1526                         seq_puts(m, "not enough stolen memory");
1527                         break;
1528                 case FBC_UNSUPPORTED_MODE:
1529                         seq_puts(m, "mode not supported");
1530                         break;
1531                 case FBC_MODE_TOO_LARGE:
1532                         seq_puts(m, "mode too large");
1533                         break;
1534                 case FBC_BAD_PLANE:
1535                         seq_puts(m, "FBC unsupported on plane");
1536                         break;
1537                 case FBC_NOT_TILED:
1538                         seq_puts(m, "scanout buffer not tiled");
1539                         break;
1540                 case FBC_MULTIPLE_PIPES:
1541                         seq_puts(m, "multiple pipes are enabled");
1542                         break;
1543                 case FBC_MODULE_PARAM:
1544                         seq_puts(m, "disabled per module param (default off)");
1545                         break;
1546                 case FBC_CHIP_DEFAULT:
1547                         seq_puts(m, "disabled per chip default");
1548                         break;
1549                 default:
1550                         seq_puts(m, "unknown reason");
1551                 }
1552                 seq_putc(m, '\n');
1553         }
1554
1555         intel_runtime_pm_put(dev_priv);
1556
1557         return 0;
1558 }
1559
1560 static int i915_fbc_fc_get(void *data, u64 *val)
1561 {
1562         struct drm_device *dev = data;
1563         struct drm_i915_private *dev_priv = dev->dev_private;
1564
1565         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1566                 return -ENODEV;
1567
1568         drm_modeset_lock_all(dev);
1569         *val = dev_priv->fbc.false_color;
1570         drm_modeset_unlock_all(dev);
1571
1572         return 0;
1573 }
1574
1575 static int i915_fbc_fc_set(void *data, u64 val)
1576 {
1577         struct drm_device *dev = data;
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579         u32 reg;
1580
1581         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1582                 return -ENODEV;
1583
1584         drm_modeset_lock_all(dev);
1585
1586         reg = I915_READ(ILK_DPFC_CONTROL);
1587         dev_priv->fbc.false_color = val;
1588
1589         I915_WRITE(ILK_DPFC_CONTROL, val ?
1590                    (reg | FBC_CTL_FALSE_COLOR) :
1591                    (reg & ~FBC_CTL_FALSE_COLOR));
1592
1593         drm_modeset_unlock_all(dev);
1594         return 0;
1595 }
1596
1597 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1598                         i915_fbc_fc_get, i915_fbc_fc_set,
1599                         "%llu\n");
1600
1601 static int i915_ips_status(struct seq_file *m, void *unused)
1602 {
1603         struct drm_info_node *node = m->private;
1604         struct drm_device *dev = node->minor->dev;
1605         struct drm_i915_private *dev_priv = dev->dev_private;
1606
1607         if (!HAS_IPS(dev)) {
1608                 seq_puts(m, "not supported\n");
1609                 return 0;
1610         }
1611
1612         intel_runtime_pm_get(dev_priv);
1613
1614         seq_printf(m, "Enabled by kernel parameter: %s\n",
1615                    yesno(i915.enable_ips));
1616
1617         if (INTEL_INFO(dev)->gen >= 8) {
1618                 seq_puts(m, "Currently: unknown\n");
1619         } else {
1620                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1621                         seq_puts(m, "Currently: enabled\n");
1622                 else
1623                         seq_puts(m, "Currently: disabled\n");
1624         }
1625
1626         intel_runtime_pm_put(dev_priv);
1627
1628         return 0;
1629 }
1630
1631 static int i915_sr_status(struct seq_file *m, void *unused)
1632 {
1633         struct drm_info_node *node = m->private;
1634         struct drm_device *dev = node->minor->dev;
1635         struct drm_i915_private *dev_priv = dev->dev_private;
1636         bool sr_enabled = false;
1637
1638         intel_runtime_pm_get(dev_priv);
1639
1640         if (HAS_PCH_SPLIT(dev))
1641                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1642         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1643                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1644         else if (IS_I915GM(dev))
1645                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1646         else if (IS_PINEVIEW(dev))
1647                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1648
1649         intel_runtime_pm_put(dev_priv);
1650
1651         seq_printf(m, "self-refresh: %s\n",
1652                    sr_enabled ? "enabled" : "disabled");
1653
1654         return 0;
1655 }
1656
1657 static int i915_emon_status(struct seq_file *m, void *unused)
1658 {
1659         struct drm_info_node *node = m->private;
1660         struct drm_device *dev = node->minor->dev;
1661         struct drm_i915_private *dev_priv = dev->dev_private;
1662         unsigned long temp, chipset, gfx;
1663         int ret;
1664
1665         if (!IS_GEN5(dev))
1666                 return -ENODEV;
1667
1668         ret = mutex_lock_interruptible(&dev->struct_mutex);
1669         if (ret)
1670                 return ret;
1671
1672         temp = i915_mch_val(dev_priv);
1673         chipset = i915_chipset_val(dev_priv);
1674         gfx = i915_gfx_val(dev_priv);
1675         mutex_unlock(&dev->struct_mutex);
1676
1677         seq_printf(m, "GMCH temp: %ld\n", temp);
1678         seq_printf(m, "Chipset power: %ld\n", chipset);
1679         seq_printf(m, "GFX power: %ld\n", gfx);
1680         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1681
1682         return 0;
1683 }
1684
1685 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1686 {
1687         struct drm_info_node *node = m->private;
1688         struct drm_device *dev = node->minor->dev;
1689         struct drm_i915_private *dev_priv = dev->dev_private;
1690         int ret = 0;
1691         int gpu_freq, ia_freq;
1692
1693         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1694                 seq_puts(m, "unsupported on this chipset\n");
1695                 return 0;
1696         }
1697
1698         intel_runtime_pm_get(dev_priv);
1699
1700         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1701
1702         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1703         if (ret)
1704                 goto out;
1705
1706         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1707
1708         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1709              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1710              gpu_freq++) {
1711                 ia_freq = gpu_freq;
1712                 sandybridge_pcode_read(dev_priv,
1713                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1714                                        &ia_freq);
1715                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1716                            intel_gpu_freq(dev_priv, gpu_freq),
1717                            ((ia_freq >> 0) & 0xff) * 100,
1718                            ((ia_freq >> 8) & 0xff) * 100);
1719         }
1720
1721         mutex_unlock(&dev_priv->rps.hw_lock);
1722
1723 out:
1724         intel_runtime_pm_put(dev_priv);
1725         return ret;
1726 }
1727
1728 static int i915_opregion(struct seq_file *m, void *unused)
1729 {
1730         struct drm_info_node *node = m->private;
1731         struct drm_device *dev = node->minor->dev;
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         struct intel_opregion *opregion = &dev_priv->opregion;
1734         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1735         int ret;
1736
1737         if (data == NULL)
1738                 return -ENOMEM;
1739
1740         ret = mutex_lock_interruptible(&dev->struct_mutex);
1741         if (ret)
1742                 goto out;
1743
1744         if (opregion->header) {
1745                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1746                 seq_write(m, data, OPREGION_SIZE);
1747         }
1748
1749         mutex_unlock(&dev->struct_mutex);
1750
1751 out:
1752         kfree(data);
1753         return 0;
1754 }
1755
1756 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1757 {
1758         struct drm_info_node *node = m->private;
1759         struct drm_device *dev = node->minor->dev;
1760         struct intel_fbdev *ifbdev = NULL;
1761         struct intel_framebuffer *fb;
1762
1763 #ifdef CONFIG_DRM_I915_FBDEV
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765
1766         ifbdev = dev_priv->fbdev;
1767         fb = to_intel_framebuffer(ifbdev->helper.fb);
1768
1769         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1770                    fb->base.width,
1771                    fb->base.height,
1772                    fb->base.depth,
1773                    fb->base.bits_per_pixel,
1774                    fb->base.modifier[0],
1775                    atomic_read(&fb->base.refcount.refcount));
1776         describe_obj(m, fb->obj);
1777         seq_putc(m, '\n');
1778 #endif
1779
1780         mutex_lock(&dev->mode_config.fb_lock);
1781         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1782                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1783                         continue;
1784
1785                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1786                            fb->base.width,
1787                            fb->base.height,
1788                            fb->base.depth,
1789                            fb->base.bits_per_pixel,
1790                            fb->base.modifier[0],
1791                            atomic_read(&fb->base.refcount.refcount));
1792                 describe_obj(m, fb->obj);
1793                 seq_putc(m, '\n');
1794         }
1795         mutex_unlock(&dev->mode_config.fb_lock);
1796
1797         return 0;
1798 }
1799
1800 static void describe_ctx_ringbuf(struct seq_file *m,
1801                                  struct intel_ringbuffer *ringbuf)
1802 {
1803         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1804                    ringbuf->space, ringbuf->head, ringbuf->tail,
1805                    ringbuf->last_retired_head);
1806 }
1807
1808 static int i915_context_status(struct seq_file *m, void *unused)
1809 {
1810         struct drm_info_node *node = m->private;
1811         struct drm_device *dev = node->minor->dev;
1812         struct drm_i915_private *dev_priv = dev->dev_private;
1813         struct intel_engine_cs *ring;
1814         struct intel_context *ctx;
1815         int ret, i;
1816
1817         ret = mutex_lock_interruptible(&dev->struct_mutex);
1818         if (ret)
1819                 return ret;
1820
1821         if (dev_priv->ips.pwrctx) {
1822                 seq_puts(m, "power context ");
1823                 describe_obj(m, dev_priv->ips.pwrctx);
1824                 seq_putc(m, '\n');
1825         }
1826
1827         if (dev_priv->ips.renderctx) {
1828                 seq_puts(m, "render context ");
1829                 describe_obj(m, dev_priv->ips.renderctx);
1830                 seq_putc(m, '\n');
1831         }
1832
1833         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1834                 if (!i915.enable_execlists &&
1835                     ctx->legacy_hw_ctx.rcs_state == NULL)
1836                         continue;
1837
1838                 seq_puts(m, "HW context ");
1839                 describe_ctx(m, ctx);
1840                 for_each_ring(ring, dev_priv, i) {
1841                         if (ring->default_context == ctx)
1842                                 seq_printf(m, "(default context %s) ",
1843                                            ring->name);
1844                 }
1845
1846                 if (i915.enable_execlists) {
1847                         seq_putc(m, '\n');
1848                         for_each_ring(ring, dev_priv, i) {
1849                                 struct drm_i915_gem_object *ctx_obj =
1850                                         ctx->engine[i].state;
1851                                 struct intel_ringbuffer *ringbuf =
1852                                         ctx->engine[i].ringbuf;
1853
1854                                 seq_printf(m, "%s: ", ring->name);
1855                                 if (ctx_obj)
1856                                         describe_obj(m, ctx_obj);
1857                                 if (ringbuf)
1858                                         describe_ctx_ringbuf(m, ringbuf);
1859                                 seq_putc(m, '\n');
1860                         }
1861                 } else {
1862                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1863                 }
1864
1865                 seq_putc(m, '\n');
1866         }
1867
1868         mutex_unlock(&dev->struct_mutex);
1869
1870         return 0;
1871 }
1872
1873 static void i915_dump_lrc_obj(struct seq_file *m,
1874                               struct intel_engine_cs *ring,
1875                               struct drm_i915_gem_object *ctx_obj)
1876 {
1877         struct page *page;
1878         uint32_t *reg_state;
1879         int j;
1880         unsigned long ggtt_offset = 0;
1881
1882         if (ctx_obj == NULL) {
1883                 seq_printf(m, "Context on %s with no gem object\n",
1884                            ring->name);
1885                 return;
1886         }
1887
1888         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1889                    intel_execlists_ctx_id(ctx_obj));
1890
1891         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1892                 seq_puts(m, "\tNot bound in GGTT\n");
1893         else
1894                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1895
1896         if (i915_gem_object_get_pages(ctx_obj)) {
1897                 seq_puts(m, "\tFailed to get pages for context object\n");
1898                 return;
1899         }
1900
1901         page = i915_gem_object_get_page(ctx_obj, 1);
1902         if (!WARN_ON(page == NULL)) {
1903                 reg_state = kmap_atomic(page);
1904
1905                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1906                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1907                                    ggtt_offset + 4096 + (j * 4),
1908                                    reg_state[j], reg_state[j + 1],
1909                                    reg_state[j + 2], reg_state[j + 3]);
1910                 }
1911                 kunmap_atomic(reg_state);
1912         }
1913
1914         seq_putc(m, '\n');
1915 }
1916
1917 static int i915_dump_lrc(struct seq_file *m, void *unused)
1918 {
1919         struct drm_info_node *node = (struct drm_info_node *) m->private;
1920         struct drm_device *dev = node->minor->dev;
1921         struct drm_i915_private *dev_priv = dev->dev_private;
1922         struct intel_engine_cs *ring;
1923         struct intel_context *ctx;
1924         int ret, i;
1925
1926         if (!i915.enable_execlists) {
1927                 seq_printf(m, "Logical Ring Contexts are disabled\n");
1928                 return 0;
1929         }
1930
1931         ret = mutex_lock_interruptible(&dev->struct_mutex);
1932         if (ret)
1933                 return ret;
1934
1935         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1936                 for_each_ring(ring, dev_priv, i) {
1937                         if (ring->default_context != ctx)
1938                                 i915_dump_lrc_obj(m, ring,
1939                                                   ctx->engine[i].state);
1940                 }
1941         }
1942
1943         mutex_unlock(&dev->struct_mutex);
1944
1945         return 0;
1946 }
1947
1948 static int i915_execlists(struct seq_file *m, void *data)
1949 {
1950         struct drm_info_node *node = (struct drm_info_node *)m->private;
1951         struct drm_device *dev = node->minor->dev;
1952         struct drm_i915_private *dev_priv = dev->dev_private;
1953         struct intel_engine_cs *ring;
1954         u32 status_pointer;
1955         u8 read_pointer;
1956         u8 write_pointer;
1957         u32 status;
1958         u32 ctx_id;
1959         struct list_head *cursor;
1960         int ring_id, i;
1961         int ret;
1962
1963         if (!i915.enable_execlists) {
1964                 seq_puts(m, "Logical Ring Contexts are disabled\n");
1965                 return 0;
1966         }
1967
1968         ret = mutex_lock_interruptible(&dev->struct_mutex);
1969         if (ret)
1970                 return ret;
1971
1972         intel_runtime_pm_get(dev_priv);
1973
1974         for_each_ring(ring, dev_priv, ring_id) {
1975                 struct drm_i915_gem_request *head_req = NULL;
1976                 int count = 0;
1977                 unsigned long flags;
1978
1979                 seq_printf(m, "%s\n", ring->name);
1980
1981                 status = I915_READ(RING_EXECLIST_STATUS(ring));
1982                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1983                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1984                            status, ctx_id);
1985
1986                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1987                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1988
1989                 read_pointer = ring->next_context_status_buffer;
1990                 write_pointer = status_pointer & 0x07;
1991                 if (read_pointer > write_pointer)
1992                         write_pointer += 6;
1993                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1994                            read_pointer, write_pointer);
1995
1996                 for (i = 0; i < 6; i++) {
1997                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1998                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1999
2000                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2001                                    i, status, ctx_id);
2002                 }
2003
2004                 spin_lock_irqsave(&ring->execlist_lock, flags);
2005                 list_for_each(cursor, &ring->execlist_queue)
2006                         count++;
2007                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2008                                 struct drm_i915_gem_request, execlist_link);
2009                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2010
2011                 seq_printf(m, "\t%d requests in queue\n", count);
2012                 if (head_req) {
2013                         struct drm_i915_gem_object *ctx_obj;
2014
2015                         ctx_obj = head_req->ctx->engine[ring_id].state;
2016                         seq_printf(m, "\tHead request id: %u\n",
2017                                    intel_execlists_ctx_id(ctx_obj));
2018                         seq_printf(m, "\tHead request tail: %u\n",
2019                                    head_req->tail);
2020                 }
2021
2022                 seq_putc(m, '\n');
2023         }
2024
2025         intel_runtime_pm_put(dev_priv);
2026         mutex_unlock(&dev->struct_mutex);
2027
2028         return 0;
2029 }
2030
2031 static const char *swizzle_string(unsigned swizzle)
2032 {
2033         switch (swizzle) {
2034         case I915_BIT_6_SWIZZLE_NONE:
2035                 return "none";
2036         case I915_BIT_6_SWIZZLE_9:
2037                 return "bit9";
2038         case I915_BIT_6_SWIZZLE_9_10:
2039                 return "bit9/bit10";
2040         case I915_BIT_6_SWIZZLE_9_11:
2041                 return "bit9/bit11";
2042         case I915_BIT_6_SWIZZLE_9_10_11:
2043                 return "bit9/bit10/bit11";
2044         case I915_BIT_6_SWIZZLE_9_17:
2045                 return "bit9/bit17";
2046         case I915_BIT_6_SWIZZLE_9_10_17:
2047                 return "bit9/bit10/bit17";
2048         case I915_BIT_6_SWIZZLE_UNKNOWN:
2049                 return "unknown";
2050         }
2051
2052         return "bug";
2053 }
2054
2055 static int i915_swizzle_info(struct seq_file *m, void *data)
2056 {
2057         struct drm_info_node *node = m->private;
2058         struct drm_device *dev = node->minor->dev;
2059         struct drm_i915_private *dev_priv = dev->dev_private;
2060         int ret;
2061
2062         ret = mutex_lock_interruptible(&dev->struct_mutex);
2063         if (ret)
2064                 return ret;
2065         intel_runtime_pm_get(dev_priv);
2066
2067         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2068                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2069         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2070                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2071
2072         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2073                 seq_printf(m, "DDC = 0x%08x\n",
2074                            I915_READ(DCC));
2075                 seq_printf(m, "DDC2 = 0x%08x\n",
2076                            I915_READ(DCC2));
2077                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2078                            I915_READ16(C0DRB3));
2079                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2080                            I915_READ16(C1DRB3));
2081         } else if (INTEL_INFO(dev)->gen >= 6) {
2082                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2083                            I915_READ(MAD_DIMM_C0));
2084                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2085                            I915_READ(MAD_DIMM_C1));
2086                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2087                            I915_READ(MAD_DIMM_C2));
2088                 seq_printf(m, "TILECTL = 0x%08x\n",
2089                            I915_READ(TILECTL));
2090                 if (INTEL_INFO(dev)->gen >= 8)
2091                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2092                                    I915_READ(GAMTARBMODE));
2093                 else
2094                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2095                                    I915_READ(ARB_MODE));
2096                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2097                            I915_READ(DISP_ARB_CTL));
2098         }
2099
2100         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2101                 seq_puts(m, "L-shaped memory detected\n");
2102
2103         intel_runtime_pm_put(dev_priv);
2104         mutex_unlock(&dev->struct_mutex);
2105
2106         return 0;
2107 }
2108
2109 static int per_file_ctx(int id, void *ptr, void *data)
2110 {
2111         struct intel_context *ctx = ptr;
2112         struct seq_file *m = data;
2113         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2114
2115         if (!ppgtt) {
2116                 seq_printf(m, "  no ppgtt for context %d\n",
2117                            ctx->user_handle);
2118                 return 0;
2119         }
2120
2121         if (i915_gem_context_is_default(ctx))
2122                 seq_puts(m, "  default context:\n");
2123         else
2124                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2125         ppgtt->debug_dump(ppgtt, m);
2126
2127         return 0;
2128 }
2129
2130 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2131 {
2132         struct drm_i915_private *dev_priv = dev->dev_private;
2133         struct intel_engine_cs *ring;
2134         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2135         int unused, i;
2136
2137         if (!ppgtt)
2138                 return;
2139
2140         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2141         seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2142         for_each_ring(ring, dev_priv, unused) {
2143                 seq_printf(m, "%s\n", ring->name);
2144                 for (i = 0; i < 4; i++) {
2145                         u32 offset = 0x270 + i * 8;
2146                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2147                         pdp <<= 32;
2148                         pdp |= I915_READ(ring->mmio_base + offset);
2149                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2150                 }
2151         }
2152 }
2153
2154 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2155 {
2156         struct drm_i915_private *dev_priv = dev->dev_private;
2157         struct intel_engine_cs *ring;
2158         struct drm_file *file;
2159         int i;
2160
2161         if (INTEL_INFO(dev)->gen == 6)
2162                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2163
2164         for_each_ring(ring, dev_priv, i) {
2165                 seq_printf(m, "%s\n", ring->name);
2166                 if (INTEL_INFO(dev)->gen == 7)
2167                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2168                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2169                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2170                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2171         }
2172         if (dev_priv->mm.aliasing_ppgtt) {
2173                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2174
2175                 seq_puts(m, "aliasing PPGTT:\n");
2176                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
2177
2178                 ppgtt->debug_dump(ppgtt, m);
2179         }
2180
2181         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2182                 struct drm_i915_file_private *file_priv = file->driver_priv;
2183
2184                 seq_printf(m, "proc: %s\n",
2185                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2186                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2187         }
2188         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2189 }
2190
2191 static int i915_ppgtt_info(struct seq_file *m, void *data)
2192 {
2193         struct drm_info_node *node = m->private;
2194         struct drm_device *dev = node->minor->dev;
2195         struct drm_i915_private *dev_priv = dev->dev_private;
2196
2197         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2198         if (ret)
2199                 return ret;
2200         intel_runtime_pm_get(dev_priv);
2201
2202         if (INTEL_INFO(dev)->gen >= 8)
2203                 gen8_ppgtt_info(m, dev);
2204         else if (INTEL_INFO(dev)->gen >= 6)
2205                 gen6_ppgtt_info(m, dev);
2206
2207         intel_runtime_pm_put(dev_priv);
2208         mutex_unlock(&dev->struct_mutex);
2209
2210         return 0;
2211 }
2212
2213 static int i915_llc(struct seq_file *m, void *data)
2214 {
2215         struct drm_info_node *node = m->private;
2216         struct drm_device *dev = node->minor->dev;
2217         struct drm_i915_private *dev_priv = dev->dev_private;
2218
2219         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2220         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2221         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2222
2223         return 0;
2224 }
2225
2226 static int i915_edp_psr_status(struct seq_file *m, void *data)
2227 {
2228         struct drm_info_node *node = m->private;
2229         struct drm_device *dev = node->minor->dev;
2230         struct drm_i915_private *dev_priv = dev->dev_private;
2231         u32 psrperf = 0;
2232         u32 stat[3];
2233         enum pipe pipe;
2234         bool enabled = false;
2235
2236         intel_runtime_pm_get(dev_priv);
2237
2238         mutex_lock(&dev_priv->psr.lock);
2239         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2240         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2241         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2242         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2243         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2244                    dev_priv->psr.busy_frontbuffer_bits);
2245         seq_printf(m, "Re-enable work scheduled: %s\n",
2246                    yesno(work_busy(&dev_priv->psr.work.work)));
2247
2248         if (HAS_PSR(dev)) {
2249                 if (HAS_DDI(dev))
2250                         enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2251                 else {
2252                         for_each_pipe(dev_priv, pipe) {
2253                                 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2254                                         VLV_EDP_PSR_CURR_STATE_MASK;
2255                                 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2256                                     (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2257                                         enabled = true;
2258                         }
2259                 }
2260         }
2261         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2262
2263         if (!HAS_DDI(dev))
2264                 for_each_pipe(dev_priv, pipe) {
2265                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2266                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2267                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2268                 }
2269         seq_puts(m, "\n");
2270
2271         seq_printf(m, "Link standby: %s\n",
2272                    yesno((bool)dev_priv->psr.link_standby));
2273
2274         /* CHV PSR has no kind of performance counter */
2275         if (HAS_PSR(dev) && HAS_DDI(dev)) {
2276                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2277                         EDP_PSR_PERF_CNT_MASK;
2278
2279                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2280         }
2281         mutex_unlock(&dev_priv->psr.lock);
2282
2283         intel_runtime_pm_put(dev_priv);
2284         return 0;
2285 }
2286
2287 static int i915_sink_crc(struct seq_file *m, void *data)
2288 {
2289         struct drm_info_node *node = m->private;
2290         struct drm_device *dev = node->minor->dev;
2291         struct intel_encoder *encoder;
2292         struct intel_connector *connector;
2293         struct intel_dp *intel_dp = NULL;
2294         int ret;
2295         u8 crc[6];
2296
2297         drm_modeset_lock_all(dev);
2298         list_for_each_entry(connector, &dev->mode_config.connector_list,
2299                             base.head) {
2300
2301                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2302                         continue;
2303
2304                 if (!connector->base.encoder)
2305                         continue;
2306
2307                 encoder = to_intel_encoder(connector->base.encoder);
2308                 if (encoder->type != INTEL_OUTPUT_EDP)
2309                         continue;
2310
2311                 intel_dp = enc_to_intel_dp(&encoder->base);
2312
2313                 ret = intel_dp_sink_crc(intel_dp, crc);
2314                 if (ret)
2315                         goto out;
2316
2317                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2318                            crc[0], crc[1], crc[2],
2319                            crc[3], crc[4], crc[5]);
2320                 goto out;
2321         }
2322         ret = -ENODEV;
2323 out:
2324         drm_modeset_unlock_all(dev);
2325         return ret;
2326 }
2327
2328 static int i915_energy_uJ(struct seq_file *m, void *data)
2329 {
2330         struct drm_info_node *node = m->private;
2331         struct drm_device *dev = node->minor->dev;
2332         struct drm_i915_private *dev_priv = dev->dev_private;
2333         u64 power;
2334         u32 units;
2335
2336         if (INTEL_INFO(dev)->gen < 6)
2337                 return -ENODEV;
2338
2339         intel_runtime_pm_get(dev_priv);
2340
2341         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2342         power = (power & 0x1f00) >> 8;
2343         units = 1000000 / (1 << power); /* convert to uJ */
2344         power = I915_READ(MCH_SECP_NRG_STTS);
2345         power *= units;
2346
2347         intel_runtime_pm_put(dev_priv);
2348
2349         seq_printf(m, "%llu", (long long unsigned)power);
2350
2351         return 0;
2352 }
2353
2354 static int i915_pc8_status(struct seq_file *m, void *unused)
2355 {
2356         struct drm_info_node *node = m->private;
2357         struct drm_device *dev = node->minor->dev;
2358         struct drm_i915_private *dev_priv = dev->dev_private;
2359
2360         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2361                 seq_puts(m, "not supported\n");
2362                 return 0;
2363         }
2364
2365         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2366         seq_printf(m, "IRQs disabled: %s\n",
2367                    yesno(!intel_irqs_enabled(dev_priv)));
2368
2369         return 0;
2370 }
2371
2372 static const char *power_domain_str(enum intel_display_power_domain domain)
2373 {
2374         switch (domain) {
2375         case POWER_DOMAIN_PIPE_A:
2376                 return "PIPE_A";
2377         case POWER_DOMAIN_PIPE_B:
2378                 return "PIPE_B";
2379         case POWER_DOMAIN_PIPE_C:
2380                 return "PIPE_C";
2381         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2382                 return "PIPE_A_PANEL_FITTER";
2383         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2384                 return "PIPE_B_PANEL_FITTER";
2385         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2386                 return "PIPE_C_PANEL_FITTER";
2387         case POWER_DOMAIN_TRANSCODER_A:
2388                 return "TRANSCODER_A";
2389         case POWER_DOMAIN_TRANSCODER_B:
2390                 return "TRANSCODER_B";
2391         case POWER_DOMAIN_TRANSCODER_C:
2392                 return "TRANSCODER_C";
2393         case POWER_DOMAIN_TRANSCODER_EDP:
2394                 return "TRANSCODER_EDP";
2395         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2396                 return "PORT_DDI_A_2_LANES";
2397         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2398                 return "PORT_DDI_A_4_LANES";
2399         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2400                 return "PORT_DDI_B_2_LANES";
2401         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2402                 return "PORT_DDI_B_4_LANES";
2403         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2404                 return "PORT_DDI_C_2_LANES";
2405         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2406                 return "PORT_DDI_C_4_LANES";
2407         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2408                 return "PORT_DDI_D_2_LANES";
2409         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2410                 return "PORT_DDI_D_4_LANES";
2411         case POWER_DOMAIN_PORT_DSI:
2412                 return "PORT_DSI";
2413         case POWER_DOMAIN_PORT_CRT:
2414                 return "PORT_CRT";
2415         case POWER_DOMAIN_PORT_OTHER:
2416                 return "PORT_OTHER";
2417         case POWER_DOMAIN_VGA:
2418                 return "VGA";
2419         case POWER_DOMAIN_AUDIO:
2420                 return "AUDIO";
2421         case POWER_DOMAIN_PLLS:
2422                 return "PLLS";
2423         case POWER_DOMAIN_AUX_A:
2424                 return "AUX_A";
2425         case POWER_DOMAIN_AUX_B:
2426                 return "AUX_B";
2427         case POWER_DOMAIN_AUX_C:
2428                 return "AUX_C";
2429         case POWER_DOMAIN_AUX_D:
2430                 return "AUX_D";
2431         case POWER_DOMAIN_INIT:
2432                 return "INIT";
2433         default:
2434                 MISSING_CASE(domain);
2435                 return "?";
2436         }
2437 }
2438
2439 static int i915_power_domain_info(struct seq_file *m, void *unused)
2440 {
2441         struct drm_info_node *node = m->private;
2442         struct drm_device *dev = node->minor->dev;
2443         struct drm_i915_private *dev_priv = dev->dev_private;
2444         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2445         int i;
2446
2447         mutex_lock(&power_domains->lock);
2448
2449         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2450         for (i = 0; i < power_domains->power_well_count; i++) {
2451                 struct i915_power_well *power_well;
2452                 enum intel_display_power_domain power_domain;
2453
2454                 power_well = &power_domains->power_wells[i];
2455                 seq_printf(m, "%-25s %d\n", power_well->name,
2456                            power_well->count);
2457
2458                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2459                      power_domain++) {
2460                         if (!(BIT(power_domain) & power_well->domains))
2461                                 continue;
2462
2463                         seq_printf(m, "  %-23s %d\n",
2464                                  power_domain_str(power_domain),
2465                                  power_domains->domain_use_count[power_domain]);
2466                 }
2467         }
2468
2469         mutex_unlock(&power_domains->lock);
2470
2471         return 0;
2472 }
2473
2474 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2475                                  struct drm_display_mode *mode)
2476 {
2477         int i;
2478
2479         for (i = 0; i < tabs; i++)
2480                 seq_putc(m, '\t');
2481
2482         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2483                    mode->base.id, mode->name,
2484                    mode->vrefresh, mode->clock,
2485                    mode->hdisplay, mode->hsync_start,
2486                    mode->hsync_end, mode->htotal,
2487                    mode->vdisplay, mode->vsync_start,
2488                    mode->vsync_end, mode->vtotal,
2489                    mode->type, mode->flags);
2490 }
2491
2492 static void intel_encoder_info(struct seq_file *m,
2493                                struct intel_crtc *intel_crtc,
2494                                struct intel_encoder *intel_encoder)
2495 {
2496         struct drm_info_node *node = m->private;
2497         struct drm_device *dev = node->minor->dev;
2498         struct drm_crtc *crtc = &intel_crtc->base;
2499         struct intel_connector *intel_connector;
2500         struct drm_encoder *encoder;
2501
2502         encoder = &intel_encoder->base;
2503         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2504                    encoder->base.id, encoder->name);
2505         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2506                 struct drm_connector *connector = &intel_connector->base;
2507                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2508                            connector->base.id,
2509                            connector->name,
2510                            drm_get_connector_status_name(connector->status));
2511                 if (connector->status == connector_status_connected) {
2512                         struct drm_display_mode *mode = &crtc->mode;
2513                         seq_printf(m, ", mode:\n");
2514                         intel_seq_print_mode(m, 2, mode);
2515                 } else {
2516                         seq_putc(m, '\n');
2517                 }
2518         }
2519 }
2520
2521 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2522 {
2523         struct drm_info_node *node = m->private;
2524         struct drm_device *dev = node->minor->dev;
2525         struct drm_crtc *crtc = &intel_crtc->base;
2526         struct intel_encoder *intel_encoder;
2527
2528         if (crtc->primary->fb)
2529                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2530                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2531                            crtc->primary->fb->width, crtc->primary->fb->height);
2532         else
2533                 seq_puts(m, "\tprimary plane disabled\n");
2534         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2535                 intel_encoder_info(m, intel_crtc, intel_encoder);
2536 }
2537
2538 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2539 {
2540         struct drm_display_mode *mode = panel->fixed_mode;
2541
2542         seq_printf(m, "\tfixed mode:\n");
2543         intel_seq_print_mode(m, 2, mode);
2544 }
2545
2546 static void intel_dp_info(struct seq_file *m,
2547                           struct intel_connector *intel_connector)
2548 {
2549         struct intel_encoder *intel_encoder = intel_connector->encoder;
2550         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2551
2552         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2553         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2554                    "no");
2555         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2556                 intel_panel_info(m, &intel_connector->panel);
2557 }
2558
2559 static void intel_hdmi_info(struct seq_file *m,
2560                             struct intel_connector *intel_connector)
2561 {
2562         struct intel_encoder *intel_encoder = intel_connector->encoder;
2563         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2564
2565         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2566                    "no");
2567 }
2568
2569 static void intel_lvds_info(struct seq_file *m,
2570                             struct intel_connector *intel_connector)
2571 {
2572         intel_panel_info(m, &intel_connector->panel);
2573 }
2574
2575 static void intel_connector_info(struct seq_file *m,
2576                                  struct drm_connector *connector)
2577 {
2578         struct intel_connector *intel_connector = to_intel_connector(connector);
2579         struct intel_encoder *intel_encoder = intel_connector->encoder;
2580         struct drm_display_mode *mode;
2581
2582         seq_printf(m, "connector %d: type %s, status: %s\n",
2583                    connector->base.id, connector->name,
2584                    drm_get_connector_status_name(connector->status));
2585         if (connector->status == connector_status_connected) {
2586                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2587                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2588                            connector->display_info.width_mm,
2589                            connector->display_info.height_mm);
2590                 seq_printf(m, "\tsubpixel order: %s\n",
2591                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2592                 seq_printf(m, "\tCEA rev: %d\n",
2593                            connector->display_info.cea_rev);
2594         }
2595         if (intel_encoder) {
2596                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2597                     intel_encoder->type == INTEL_OUTPUT_EDP)
2598                         intel_dp_info(m, intel_connector);
2599                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2600                         intel_hdmi_info(m, intel_connector);
2601                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2602                         intel_lvds_info(m, intel_connector);
2603         }
2604
2605         seq_printf(m, "\tmodes:\n");
2606         list_for_each_entry(mode, &connector->modes, head)
2607                 intel_seq_print_mode(m, 2, mode);
2608 }
2609
2610 static bool cursor_active(struct drm_device *dev, int pipe)
2611 {
2612         struct drm_i915_private *dev_priv = dev->dev_private;
2613         u32 state;
2614
2615         if (IS_845G(dev) || IS_I865G(dev))
2616                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2617         else
2618                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2619
2620         return state;
2621 }
2622
2623 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2624 {
2625         struct drm_i915_private *dev_priv = dev->dev_private;
2626         u32 pos;
2627
2628         pos = I915_READ(CURPOS(pipe));
2629
2630         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2631         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2632                 *x = -*x;
2633
2634         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2635         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2636                 *y = -*y;
2637
2638         return cursor_active(dev, pipe);
2639 }
2640
2641 static int i915_display_info(struct seq_file *m, void *unused)
2642 {
2643         struct drm_info_node *node = m->private;
2644         struct drm_device *dev = node->minor->dev;
2645         struct drm_i915_private *dev_priv = dev->dev_private;
2646         struct intel_crtc *crtc;
2647         struct drm_connector *connector;
2648
2649         intel_runtime_pm_get(dev_priv);
2650         drm_modeset_lock_all(dev);
2651         seq_printf(m, "CRTC info\n");
2652         seq_printf(m, "---------\n");
2653         for_each_intel_crtc(dev, crtc) {
2654                 bool active;
2655                 int x, y;
2656
2657                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2658                            crtc->base.base.id, pipe_name(crtc->pipe),
2659                            yesno(crtc->active), crtc->config->pipe_src_w,
2660                            crtc->config->pipe_src_h);
2661                 if (crtc->active) {
2662                         intel_crtc_info(m, crtc);
2663
2664                         active = cursor_position(dev, crtc->pipe, &x, &y);
2665                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2666                                    yesno(crtc->cursor_base),
2667                                    x, y, crtc->cursor_width, crtc->cursor_height,
2668                                    crtc->cursor_addr, yesno(active));
2669                 }
2670
2671                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2672                            yesno(!crtc->cpu_fifo_underrun_disabled),
2673                            yesno(!crtc->pch_fifo_underrun_disabled));
2674         }
2675
2676         seq_printf(m, "\n");
2677         seq_printf(m, "Connector info\n");
2678         seq_printf(m, "--------------\n");
2679         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2680                 intel_connector_info(m, connector);
2681         }
2682         drm_modeset_unlock_all(dev);
2683         intel_runtime_pm_put(dev_priv);
2684
2685         return 0;
2686 }
2687
2688 static int i915_semaphore_status(struct seq_file *m, void *unused)
2689 {
2690         struct drm_info_node *node = (struct drm_info_node *) m->private;
2691         struct drm_device *dev = node->minor->dev;
2692         struct drm_i915_private *dev_priv = dev->dev_private;
2693         struct intel_engine_cs *ring;
2694         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2695         int i, j, ret;
2696
2697         if (!i915_semaphore_is_enabled(dev)) {
2698                 seq_puts(m, "Semaphores are disabled\n");
2699                 return 0;
2700         }
2701
2702         ret = mutex_lock_interruptible(&dev->struct_mutex);
2703         if (ret)
2704                 return ret;
2705         intel_runtime_pm_get(dev_priv);
2706
2707         if (IS_BROADWELL(dev)) {
2708                 struct page *page;
2709                 uint64_t *seqno;
2710
2711                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2712
2713                 seqno = (uint64_t *)kmap_atomic(page);
2714                 for_each_ring(ring, dev_priv, i) {
2715                         uint64_t offset;
2716
2717                         seq_printf(m, "%s\n", ring->name);
2718
2719                         seq_puts(m, "  Last signal:");
2720                         for (j = 0; j < num_rings; j++) {
2721                                 offset = i * I915_NUM_RINGS + j;
2722                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2723                                            seqno[offset], offset * 8);
2724                         }
2725                         seq_putc(m, '\n');
2726
2727                         seq_puts(m, "  Last wait:  ");
2728                         for (j = 0; j < num_rings; j++) {
2729                                 offset = i + (j * I915_NUM_RINGS);
2730                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2731                                            seqno[offset], offset * 8);
2732                         }
2733                         seq_putc(m, '\n');
2734
2735                 }
2736                 kunmap_atomic(seqno);
2737         } else {
2738                 seq_puts(m, "  Last signal:");
2739                 for_each_ring(ring, dev_priv, i)
2740                         for (j = 0; j < num_rings; j++)
2741                                 seq_printf(m, "0x%08x\n",
2742                                            I915_READ(ring->semaphore.mbox.signal[j]));
2743                 seq_putc(m, '\n');
2744         }
2745
2746         seq_puts(m, "\nSync seqno:\n");
2747         for_each_ring(ring, dev_priv, i) {
2748                 for (j = 0; j < num_rings; j++) {
2749                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2750                 }
2751                 seq_putc(m, '\n');
2752         }
2753         seq_putc(m, '\n');
2754
2755         intel_runtime_pm_put(dev_priv);
2756         mutex_unlock(&dev->struct_mutex);
2757         return 0;
2758 }
2759
2760 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2761 {
2762         struct drm_info_node *node = (struct drm_info_node *) m->private;
2763         struct drm_device *dev = node->minor->dev;
2764         struct drm_i915_private *dev_priv = dev->dev_private;
2765         int i;
2766
2767         drm_modeset_lock_all(dev);
2768         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2769                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2770
2771                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2772                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2773                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2774                 seq_printf(m, " tracked hardware state:\n");
2775                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2776                 seq_printf(m, " dpll_md: 0x%08x\n",
2777                            pll->config.hw_state.dpll_md);
2778                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2779                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2780                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2781         }
2782         drm_modeset_unlock_all(dev);
2783
2784         return 0;
2785 }
2786
2787 static int i915_wa_registers(struct seq_file *m, void *unused)
2788 {
2789         int i;
2790         int ret;
2791         struct drm_info_node *node = (struct drm_info_node *) m->private;
2792         struct drm_device *dev = node->minor->dev;
2793         struct drm_i915_private *dev_priv = dev->dev_private;
2794
2795         ret = mutex_lock_interruptible(&dev->struct_mutex);
2796         if (ret)
2797                 return ret;
2798
2799         intel_runtime_pm_get(dev_priv);
2800
2801         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2802         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2803                 u32 addr, mask, value, read;
2804                 bool ok;
2805
2806                 addr = dev_priv->workarounds.reg[i].addr;
2807                 mask = dev_priv->workarounds.reg[i].mask;
2808                 value = dev_priv->workarounds.reg[i].value;
2809                 read = I915_READ(addr);
2810                 ok = (value & mask) == (read & mask);
2811                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2812                            addr, value, mask, read, ok ? "OK" : "FAIL");
2813         }
2814
2815         intel_runtime_pm_put(dev_priv);
2816         mutex_unlock(&dev->struct_mutex);
2817
2818         return 0;
2819 }
2820
2821 static int i915_ddb_info(struct seq_file *m, void *unused)
2822 {
2823         struct drm_info_node *node = m->private;
2824         struct drm_device *dev = node->minor->dev;
2825         struct drm_i915_private *dev_priv = dev->dev_private;
2826         struct skl_ddb_allocation *ddb;
2827         struct skl_ddb_entry *entry;
2828         enum pipe pipe;
2829         int plane;
2830
2831         if (INTEL_INFO(dev)->gen < 9)
2832                 return 0;
2833
2834         drm_modeset_lock_all(dev);
2835
2836         ddb = &dev_priv->wm.skl_hw.ddb;
2837
2838         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2839
2840         for_each_pipe(dev_priv, pipe) {
2841                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2842
2843                 for_each_plane(pipe, plane) {
2844                         entry = &ddb->plane[pipe][plane];
2845                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2846                                    entry->start, entry->end,
2847                                    skl_ddb_entry_size(entry));
2848                 }
2849
2850                 entry = &ddb->cursor[pipe];
2851                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
2852                            entry->end, skl_ddb_entry_size(entry));
2853         }
2854
2855         drm_modeset_unlock_all(dev);
2856
2857         return 0;
2858 }
2859
2860 struct pipe_crc_info {
2861         const char *name;
2862         struct drm_device *dev;
2863         enum pipe pipe;
2864 };
2865
2866 static int i915_dp_mst_info(struct seq_file *m, void *unused)
2867 {
2868         struct drm_info_node *node = (struct drm_info_node *) m->private;
2869         struct drm_device *dev = node->minor->dev;
2870         struct drm_encoder *encoder;
2871         struct intel_encoder *intel_encoder;
2872         struct intel_digital_port *intel_dig_port;
2873         drm_modeset_lock_all(dev);
2874         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2875                 intel_encoder = to_intel_encoder(encoder);
2876                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2877                         continue;
2878                 intel_dig_port = enc_to_dig_port(encoder);
2879                 if (!intel_dig_port->dp.can_mst)
2880                         continue;
2881
2882                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2883         }
2884         drm_modeset_unlock_all(dev);
2885         return 0;
2886 }
2887
2888 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2889 {
2890         struct pipe_crc_info *info = inode->i_private;
2891         struct drm_i915_private *dev_priv = info->dev->dev_private;
2892         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2893
2894         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2895                 return -ENODEV;
2896
2897         spin_lock_irq(&pipe_crc->lock);
2898
2899         if (pipe_crc->opened) {
2900                 spin_unlock_irq(&pipe_crc->lock);
2901                 return -EBUSY; /* already open */
2902         }
2903
2904         pipe_crc->opened = true;
2905         filep->private_data = inode->i_private;
2906
2907         spin_unlock_irq(&pipe_crc->lock);
2908
2909         return 0;
2910 }
2911
2912 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2913 {
2914         struct pipe_crc_info *info = inode->i_private;
2915         struct drm_i915_private *dev_priv = info->dev->dev_private;
2916         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2917
2918         spin_lock_irq(&pipe_crc->lock);
2919         pipe_crc->opened = false;
2920         spin_unlock_irq(&pipe_crc->lock);
2921
2922         return 0;
2923 }
2924
2925 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2926 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2927 /* account for \'0' */
2928 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2929
2930 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2931 {
2932         assert_spin_locked(&pipe_crc->lock);
2933         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2934                         INTEL_PIPE_CRC_ENTRIES_NR);
2935 }
2936
2937 static ssize_t
2938 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2939                    loff_t *pos)
2940 {
2941         struct pipe_crc_info *info = filep->private_data;
2942         struct drm_device *dev = info->dev;
2943         struct drm_i915_private *dev_priv = dev->dev_private;
2944         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2945         char buf[PIPE_CRC_BUFFER_LEN];
2946         int n_entries;
2947         ssize_t bytes_read;
2948
2949         /*
2950          * Don't allow user space to provide buffers not big enough to hold
2951          * a line of data.
2952          */
2953         if (count < PIPE_CRC_LINE_LEN)
2954                 return -EINVAL;
2955
2956         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2957                 return 0;
2958
2959         /* nothing to read */
2960         spin_lock_irq(&pipe_crc->lock);
2961         while (pipe_crc_data_count(pipe_crc) == 0) {
2962                 int ret;
2963
2964                 if (filep->f_flags & O_NONBLOCK) {
2965                         spin_unlock_irq(&pipe_crc->lock);
2966                         return -EAGAIN;
2967                 }
2968
2969                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2970                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2971                 if (ret) {
2972                         spin_unlock_irq(&pipe_crc->lock);
2973                         return ret;
2974                 }
2975         }
2976
2977         /* We now have one or more entries to read */
2978         n_entries = count / PIPE_CRC_LINE_LEN;
2979
2980         bytes_read = 0;
2981         while (n_entries > 0) {
2982                 struct intel_pipe_crc_entry *entry =
2983                         &pipe_crc->entries[pipe_crc->tail];
2984                 int ret;
2985
2986                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2987                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2988                         break;
2989
2990                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2991                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2992
2993                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2994                                        "%8u %8x %8x %8x %8x %8x\n",
2995                                        entry->frame, entry->crc[0],
2996                                        entry->crc[1], entry->crc[2],
2997                                        entry->crc[3], entry->crc[4]);
2998
2999                 spin_unlock_irq(&pipe_crc->lock);
3000
3001                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3002                 if (ret == PIPE_CRC_LINE_LEN)
3003                         return -EFAULT;
3004
3005                 user_buf += PIPE_CRC_LINE_LEN;
3006                 n_entries--;
3007
3008                 spin_lock_irq(&pipe_crc->lock);
3009         }
3010
3011         spin_unlock_irq(&pipe_crc->lock);
3012
3013         return bytes_read;
3014 }
3015
3016 static const struct file_operations i915_pipe_crc_fops = {
3017         .owner = THIS_MODULE,
3018         .open = i915_pipe_crc_open,
3019         .read = i915_pipe_crc_read,
3020         .release = i915_pipe_crc_release,
3021 };
3022
3023 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3024         {
3025                 .name = "i915_pipe_A_crc",
3026                 .pipe = PIPE_A,
3027         },
3028         {
3029                 .name = "i915_pipe_B_crc",
3030                 .pipe = PIPE_B,
3031         },
3032         {
3033                 .name = "i915_pipe_C_crc",
3034                 .pipe = PIPE_C,
3035         },
3036 };
3037
3038 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3039                                 enum pipe pipe)
3040 {
3041         struct drm_device *dev = minor->dev;
3042         struct dentry *ent;
3043         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3044
3045         info->dev = dev;
3046         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3047                                   &i915_pipe_crc_fops);
3048         if (!ent)
3049                 return -ENOMEM;
3050
3051         return drm_add_fake_info_node(minor, ent, info);
3052 }
3053
3054 static const char * const pipe_crc_sources[] = {
3055         "none",
3056         "plane1",
3057         "plane2",
3058         "pf",
3059         "pipe",
3060         "TV",
3061         "DP-B",
3062         "DP-C",
3063         "DP-D",
3064         "auto",
3065 };
3066
3067 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3068 {
3069         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3070         return pipe_crc_sources[source];
3071 }
3072
3073 static int display_crc_ctl_show(struct seq_file *m, void *data)
3074 {
3075         struct drm_device *dev = m->private;
3076         struct drm_i915_private *dev_priv = dev->dev_private;
3077         int i;
3078
3079         for (i = 0; i < I915_MAX_PIPES; i++)
3080                 seq_printf(m, "%c %s\n", pipe_name(i),
3081                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3082
3083         return 0;
3084 }
3085
3086 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3087 {
3088         struct drm_device *dev = inode->i_private;
3089
3090         return single_open(file, display_crc_ctl_show, dev);
3091 }
3092
3093 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3094                                  uint32_t *val)
3095 {
3096         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3097                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3098
3099         switch (*source) {
3100         case INTEL_PIPE_CRC_SOURCE_PIPE:
3101                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3102                 break;
3103         case INTEL_PIPE_CRC_SOURCE_NONE:
3104                 *val = 0;
3105                 break;
3106         default:
3107                 return -EINVAL;
3108         }
3109
3110         return 0;
3111 }
3112
3113 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3114                                      enum intel_pipe_crc_source *source)
3115 {
3116         struct intel_encoder *encoder;
3117         struct intel_crtc *crtc;
3118         struct intel_digital_port *dig_port;
3119         int ret = 0;
3120
3121         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3122
3123         drm_modeset_lock_all(dev);
3124         for_each_intel_encoder(dev, encoder) {
3125                 if (!encoder->base.crtc)
3126                         continue;
3127
3128                 crtc = to_intel_crtc(encoder->base.crtc);
3129
3130                 if (crtc->pipe != pipe)
3131                         continue;
3132
3133                 switch (encoder->type) {
3134                 case INTEL_OUTPUT_TVOUT:
3135                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3136                         break;
3137                 case INTEL_OUTPUT_DISPLAYPORT:
3138                 case INTEL_OUTPUT_EDP:
3139                         dig_port = enc_to_dig_port(&encoder->base);
3140                         switch (dig_port->port) {
3141                         case PORT_B:
3142                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3143                                 break;
3144                         case PORT_C:
3145                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3146                                 break;
3147                         case PORT_D:
3148                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3149                                 break;
3150                         default:
3151                                 WARN(1, "nonexisting DP port %c\n",
3152                                      port_name(dig_port->port));
3153                                 break;
3154                         }
3155                         break;
3156                 default:
3157                         break;
3158                 }
3159         }
3160         drm_modeset_unlock_all(dev);
3161
3162         return ret;
3163 }
3164
3165 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3166                                 enum pipe pipe,
3167                                 enum intel_pipe_crc_source *source,
3168                                 uint32_t *val)
3169 {
3170         struct drm_i915_private *dev_priv = dev->dev_private;
3171         bool need_stable_symbols = false;
3172
3173         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3174                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3175                 if (ret)
3176                         return ret;
3177         }
3178
3179         switch (*source) {
3180         case INTEL_PIPE_CRC_SOURCE_PIPE:
3181                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3182                 break;
3183         case INTEL_PIPE_CRC_SOURCE_DP_B:
3184                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3185                 need_stable_symbols = true;
3186                 break;
3187         case INTEL_PIPE_CRC_SOURCE_DP_C:
3188                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3189                 need_stable_symbols = true;
3190                 break;
3191         case INTEL_PIPE_CRC_SOURCE_DP_D:
3192                 if (!IS_CHERRYVIEW(dev))
3193                         return -EINVAL;
3194                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3195                 need_stable_symbols = true;
3196                 break;
3197         case INTEL_PIPE_CRC_SOURCE_NONE:
3198                 *val = 0;
3199                 break;
3200         default:
3201                 return -EINVAL;
3202         }
3203
3204         /*
3205          * When the pipe CRC tap point is after the transcoders we need
3206          * to tweak symbol-level features to produce a deterministic series of
3207          * symbols for a given frame. We need to reset those features only once
3208          * a frame (instead of every nth symbol):
3209          *   - DC-balance: used to ensure a better clock recovery from the data
3210          *     link (SDVO)
3211          *   - DisplayPort scrambling: used for EMI reduction
3212          */
3213         if (need_stable_symbols) {
3214                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3215
3216                 tmp |= DC_BALANCE_RESET_VLV;
3217                 switch (pipe) {
3218                 case PIPE_A:
3219                         tmp |= PIPE_A_SCRAMBLE_RESET;
3220                         break;
3221                 case PIPE_B:
3222                         tmp |= PIPE_B_SCRAMBLE_RESET;
3223                         break;
3224                 case PIPE_C:
3225                         tmp |= PIPE_C_SCRAMBLE_RESET;
3226                         break;
3227                 default:
3228                         return -EINVAL;
3229                 }
3230                 I915_WRITE(PORT_DFT2_G4X, tmp);
3231         }
3232
3233         return 0;
3234 }
3235
3236 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3237                                  enum pipe pipe,
3238                                  enum intel_pipe_crc_source *source,
3239                                  uint32_t *val)
3240 {
3241         struct drm_i915_private *dev_priv = dev->dev_private;
3242         bool need_stable_symbols = false;
3243
3244         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3245                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3246                 if (ret)
3247                         return ret;
3248         }
3249
3250         switch (*source) {
3251         case INTEL_PIPE_CRC_SOURCE_PIPE:
3252                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3253                 break;
3254         case INTEL_PIPE_CRC_SOURCE_TV:
3255                 if (!SUPPORTS_TV(dev))
3256                         return -EINVAL;
3257                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3258                 break;
3259         case INTEL_PIPE_CRC_SOURCE_DP_B:
3260                 if (!IS_G4X(dev))
3261                         return -EINVAL;
3262                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3263                 need_stable_symbols = true;
3264                 break;
3265         case INTEL_PIPE_CRC_SOURCE_DP_C:
3266                 if (!IS_G4X(dev))
3267                         return -EINVAL;
3268                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3269                 need_stable_symbols = true;
3270                 break;
3271         case INTEL_PIPE_CRC_SOURCE_DP_D:
3272                 if (!IS_G4X(dev))
3273                         return -EINVAL;
3274                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3275                 need_stable_symbols = true;
3276                 break;
3277         case INTEL_PIPE_CRC_SOURCE_NONE:
3278                 *val = 0;
3279                 break;
3280         default:
3281                 return -EINVAL;
3282         }
3283
3284         /*
3285          * When the pipe CRC tap point is after the transcoders we need
3286          * to tweak symbol-level features to produce a deterministic series of
3287          * symbols for a given frame. We need to reset those features only once
3288          * a frame (instead of every nth symbol):
3289          *   - DC-balance: used to ensure a better clock recovery from the data
3290          *     link (SDVO)
3291          *   - DisplayPort scrambling: used for EMI reduction
3292          */
3293         if (need_stable_symbols) {
3294                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3295
3296                 WARN_ON(!IS_G4X(dev));
3297
3298                 I915_WRITE(PORT_DFT_I9XX,
3299                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3300
3301                 if (pipe == PIPE_A)
3302                         tmp |= PIPE_A_SCRAMBLE_RESET;
3303                 else
3304                         tmp |= PIPE_B_SCRAMBLE_RESET;
3305
3306                 I915_WRITE(PORT_DFT2_G4X, tmp);
3307         }
3308
3309         return 0;
3310 }
3311
3312 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3313                                          enum pipe pipe)
3314 {
3315         struct drm_i915_private *dev_priv = dev->dev_private;
3316         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3317
3318         switch (pipe) {
3319         case PIPE_A:
3320                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3321                 break;
3322         case PIPE_B:
3323                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3324                 break;
3325         case PIPE_C:
3326                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3327                 break;
3328         default:
3329                 return;
3330         }
3331         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3332                 tmp &= ~DC_BALANCE_RESET_VLV;
3333         I915_WRITE(PORT_DFT2_G4X, tmp);
3334
3335 }
3336
3337 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3338                                          enum pipe pipe)
3339 {
3340         struct drm_i915_private *dev_priv = dev->dev_private;
3341         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3342
3343         if (pipe == PIPE_A)
3344                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3345         else
3346                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3347         I915_WRITE(PORT_DFT2_G4X, tmp);
3348
3349         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3350                 I915_WRITE(PORT_DFT_I9XX,
3351                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3352         }
3353 }
3354
3355 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3356                                 uint32_t *val)
3357 {
3358         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3359                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3360
3361         switch (*source) {
3362         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3363                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3364                 break;
3365         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3366                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3367                 break;
3368         case INTEL_PIPE_CRC_SOURCE_PIPE:
3369                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3370                 break;
3371         case INTEL_PIPE_CRC_SOURCE_NONE:
3372                 *val = 0;
3373                 break;
3374         default:
3375                 return -EINVAL;
3376         }
3377
3378         return 0;
3379 }
3380
3381 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3382 {
3383         struct drm_i915_private *dev_priv = dev->dev_private;
3384         struct intel_crtc *crtc =
3385                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3386
3387         drm_modeset_lock_all(dev);
3388         /*
3389          * If we use the eDP transcoder we need to make sure that we don't
3390          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3391          * relevant on hsw with pipe A when using the always-on power well
3392          * routing.
3393          */
3394         if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3395             !crtc->config->pch_pfit.enabled) {
3396                 crtc->config->pch_pfit.force_thru = true;
3397
3398                 intel_display_power_get(dev_priv,
3399                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3400
3401                 dev_priv->display.crtc_disable(&crtc->base);
3402                 dev_priv->display.crtc_enable(&crtc->base);
3403         }
3404         drm_modeset_unlock_all(dev);
3405 }
3406
3407 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3408 {
3409         struct drm_i915_private *dev_priv = dev->dev_private;
3410         struct intel_crtc *crtc =
3411                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3412
3413         drm_modeset_lock_all(dev);
3414         /*
3415          * If we use the eDP transcoder we need to make sure that we don't
3416          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3417          * relevant on hsw with pipe A when using the always-on power well
3418          * routing.
3419          */
3420         if (crtc->config->pch_pfit.force_thru) {
3421                 crtc->config->pch_pfit.force_thru = false;
3422
3423                 dev_priv->display.crtc_disable(&crtc->base);
3424                 dev_priv->display.crtc_enable(&crtc->base);
3425
3426                 intel_display_power_put(dev_priv,
3427                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3428         }
3429         drm_modeset_unlock_all(dev);
3430 }
3431
3432 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3433                                 enum pipe pipe,
3434                                 enum intel_pipe_crc_source *source,
3435                                 uint32_t *val)
3436 {
3437         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3438                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3439
3440         switch (*source) {
3441         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3442                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3443                 break;
3444         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3445                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3446                 break;
3447         case INTEL_PIPE_CRC_SOURCE_PF:
3448                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3449                         hsw_trans_edp_pipe_A_crc_wa(dev);
3450
3451                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3452                 break;
3453         case INTEL_PIPE_CRC_SOURCE_NONE:
3454                 *val = 0;
3455                 break;
3456         default:
3457                 return -EINVAL;
3458         }
3459
3460         return 0;
3461 }
3462
3463 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3464                                enum intel_pipe_crc_source source)
3465 {
3466         struct drm_i915_private *dev_priv = dev->dev_private;
3467         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3468         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3469                                                                         pipe));
3470         u32 val = 0; /* shut up gcc */
3471         int ret;
3472
3473         if (pipe_crc->source == source)
3474                 return 0;
3475
3476         /* forbid changing the source without going back to 'none' */
3477         if (pipe_crc->source && source)
3478                 return -EINVAL;
3479
3480         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3481                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3482                 return -EIO;
3483         }
3484
3485         if (IS_GEN2(dev))
3486                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3487         else if (INTEL_INFO(dev)->gen < 5)
3488                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3489         else if (IS_VALLEYVIEW(dev))
3490                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3491         else if (IS_GEN5(dev) || IS_GEN6(dev))
3492                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3493         else
3494                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3495
3496         if (ret != 0)
3497                 return ret;
3498
3499         /* none -> real source transition */
3500         if (source) {
3501                 struct intel_pipe_crc_entry *entries;
3502
3503                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3504                                  pipe_name(pipe), pipe_crc_source_name(source));
3505
3506                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3507                                   sizeof(pipe_crc->entries[0]),
3508                                   GFP_KERNEL);
3509                 if (!entries)
3510                         return -ENOMEM;
3511
3512                 /*
3513                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3514                  * enabled and disabled dynamically based on package C states,
3515                  * user space can't make reliable use of the CRCs, so let's just
3516                  * completely disable it.
3517                  */
3518                 hsw_disable_ips(crtc);
3519
3520                 spin_lock_irq(&pipe_crc->lock);
3521                 kfree(pipe_crc->entries);
3522                 pipe_crc->entries = entries;
3523                 pipe_crc->head = 0;
3524                 pipe_crc->tail = 0;
3525                 spin_unlock_irq(&pipe_crc->lock);
3526         }
3527
3528         pipe_crc->source = source;
3529
3530         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3531         POSTING_READ(PIPE_CRC_CTL(pipe));
3532
3533         /* real source -> none transition */
3534         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3535                 struct intel_pipe_crc_entry *entries;
3536                 struct intel_crtc *crtc =
3537                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3538
3539                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3540                                  pipe_name(pipe));
3541
3542                 drm_modeset_lock(&crtc->base.mutex, NULL);
3543                 if (crtc->active)
3544                         intel_wait_for_vblank(dev, pipe);
3545                 drm_modeset_unlock(&crtc->base.mutex);
3546
3547                 spin_lock_irq(&pipe_crc->lock);
3548                 entries = pipe_crc->entries;
3549                 pipe_crc->entries = NULL;
3550                 pipe_crc->head = 0;
3551                 pipe_crc->tail = 0;
3552                 spin_unlock_irq(&pipe_crc->lock);
3553
3554                 kfree(entries);
3555
3556                 if (IS_G4X(dev))
3557                         g4x_undo_pipe_scramble_reset(dev, pipe);
3558                 else if (IS_VALLEYVIEW(dev))
3559                         vlv_undo_pipe_scramble_reset(dev, pipe);
3560                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3561                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3562
3563                 hsw_enable_ips(crtc);
3564         }
3565
3566         return 0;
3567 }
3568
3569 /*
3570  * Parse pipe CRC command strings:
3571  *   command: wsp* object wsp+ name wsp+ source wsp*
3572  *   object: 'pipe'
3573  *   name: (A | B | C)
3574  *   source: (none | plane1 | plane2 | pf)
3575  *   wsp: (#0x20 | #0x9 | #0xA)+
3576  *
3577  * eg.:
3578  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3579  *  "pipe A none"    ->  Stop CRC
3580  */
3581 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3582 {
3583         int n_words = 0;
3584
3585         while (*buf) {
3586                 char *end;
3587
3588                 /* skip leading white space */
3589                 buf = skip_spaces(buf);
3590                 if (!*buf)
3591                         break;  /* end of buffer */
3592
3593                 /* find end of word */
3594                 for (end = buf; *end && !isspace(*end); end++)
3595                         ;
3596
3597                 if (n_words == max_words) {
3598                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3599                                          max_words);
3600                         return -EINVAL; /* ran out of words[] before bytes */
3601                 }
3602
3603                 if (*end)
3604                         *end++ = '\0';
3605                 words[n_words++] = buf;
3606                 buf = end;
3607         }
3608
3609         return n_words;
3610 }
3611
3612 enum intel_pipe_crc_object {
3613         PIPE_CRC_OBJECT_PIPE,
3614 };
3615
3616 static const char * const pipe_crc_objects[] = {
3617         "pipe",
3618 };
3619
3620 static int
3621 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3622 {
3623         int i;
3624
3625         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3626                 if (!strcmp(buf, pipe_crc_objects[i])) {
3627                         *o = i;
3628                         return 0;
3629                     }
3630
3631         return -EINVAL;
3632 }
3633
3634 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3635 {
3636         const char name = buf[0];
3637
3638         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3639                 return -EINVAL;
3640
3641         *pipe = name - 'A';
3642
3643         return 0;
3644 }
3645
3646 static int
3647 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3648 {
3649         int i;
3650
3651         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3652                 if (!strcmp(buf, pipe_crc_sources[i])) {
3653                         *s = i;
3654                         return 0;
3655                     }
3656
3657         return -EINVAL;
3658 }
3659
3660 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3661 {
3662 #define N_WORDS 3
3663         int n_words;
3664         char *words[N_WORDS];
3665         enum pipe pipe;
3666         enum intel_pipe_crc_object object;
3667         enum intel_pipe_crc_source source;
3668
3669         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3670         if (n_words != N_WORDS) {
3671                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3672                                  N_WORDS);
3673                 return -EINVAL;
3674         }
3675
3676         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3677                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3678                 return -EINVAL;
3679         }
3680
3681         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3682                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3683                 return -EINVAL;
3684         }
3685
3686         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3687                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3688                 return -EINVAL;
3689         }
3690
3691         return pipe_crc_set_source(dev, pipe, source);
3692 }
3693
3694 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3695                                      size_t len, loff_t *offp)
3696 {
3697         struct seq_file *m = file->private_data;
3698         struct drm_device *dev = m->private;
3699         char *tmpbuf;
3700         int ret;
3701
3702         if (len == 0)
3703                 return 0;
3704
3705         if (len > PAGE_SIZE - 1) {
3706                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3707                                  PAGE_SIZE);
3708                 return -E2BIG;
3709         }
3710
3711         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3712         if (!tmpbuf)
3713                 return -ENOMEM;
3714
3715         if (copy_from_user(tmpbuf, ubuf, len)) {
3716                 ret = -EFAULT;
3717                 goto out;
3718         }
3719         tmpbuf[len] = '\0';
3720
3721         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3722
3723 out:
3724         kfree(tmpbuf);
3725         if (ret < 0)
3726                 return ret;
3727
3728         *offp += len;
3729         return len;
3730 }
3731
3732 static const struct file_operations i915_display_crc_ctl_fops = {
3733         .owner = THIS_MODULE,
3734         .open = display_crc_ctl_open,
3735         .read = seq_read,
3736         .llseek = seq_lseek,
3737         .release = single_release,
3738         .write = display_crc_ctl_write
3739 };
3740
3741 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3742 {
3743         struct drm_device *dev = m->private;
3744         int num_levels = ilk_wm_max_level(dev) + 1;
3745         int level;
3746
3747         drm_modeset_lock_all(dev);
3748
3749         for (level = 0; level < num_levels; level++) {
3750                 unsigned int latency = wm[level];
3751
3752                 /*
3753                  * - WM1+ latency values in 0.5us units
3754                  * - latencies are in us on gen9
3755                  */
3756                 if (INTEL_INFO(dev)->gen >= 9)
3757                         latency *= 10;
3758                 else if (level > 0)
3759                         latency *= 5;
3760
3761                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3762                            level, wm[level], latency / 10, latency % 10);
3763         }
3764
3765         drm_modeset_unlock_all(dev);
3766 }
3767
3768 static int pri_wm_latency_show(struct seq_file *m, void *data)
3769 {
3770         struct drm_device *dev = m->private;
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772         const uint16_t *latencies;
3773
3774         if (INTEL_INFO(dev)->gen >= 9)
3775                 latencies = dev_priv->wm.skl_latency;
3776         else
3777                 latencies = to_i915(dev)->wm.pri_latency;
3778
3779         wm_latency_show(m, latencies);
3780
3781         return 0;
3782 }
3783
3784 static int spr_wm_latency_show(struct seq_file *m, void *data)
3785 {
3786         struct drm_device *dev = m->private;
3787         struct drm_i915_private *dev_priv = dev->dev_private;
3788         const uint16_t *latencies;
3789
3790         if (INTEL_INFO(dev)->gen >= 9)
3791                 latencies = dev_priv->wm.skl_latency;
3792         else
3793                 latencies = to_i915(dev)->wm.spr_latency;
3794
3795         wm_latency_show(m, latencies);
3796
3797         return 0;
3798 }
3799
3800 static int cur_wm_latency_show(struct seq_file *m, void *data)
3801 {
3802         struct drm_device *dev = m->private;
3803         struct drm_i915_private *dev_priv = dev->dev_private;
3804         const uint16_t *latencies;
3805
3806         if (INTEL_INFO(dev)->gen >= 9)
3807                 latencies = dev_priv->wm.skl_latency;
3808         else
3809                 latencies = to_i915(dev)->wm.cur_latency;
3810
3811         wm_latency_show(m, latencies);
3812
3813         return 0;
3814 }
3815
3816 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3817 {
3818         struct drm_device *dev = inode->i_private;
3819
3820         if (HAS_GMCH_DISPLAY(dev))
3821                 return -ENODEV;
3822
3823         return single_open(file, pri_wm_latency_show, dev);
3824 }
3825
3826 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3827 {
3828         struct drm_device *dev = inode->i_private;
3829
3830         if (HAS_GMCH_DISPLAY(dev))
3831                 return -ENODEV;
3832
3833         return single_open(file, spr_wm_latency_show, dev);
3834 }
3835
3836 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3837 {
3838         struct drm_device *dev = inode->i_private;
3839
3840         if (HAS_GMCH_DISPLAY(dev))
3841                 return -ENODEV;
3842
3843         return single_open(file, cur_wm_latency_show, dev);
3844 }
3845
3846 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3847                                 size_t len, loff_t *offp, uint16_t wm[8])
3848 {
3849         struct seq_file *m = file->private_data;
3850         struct drm_device *dev = m->private;
3851         uint16_t new[8] = { 0 };
3852         int num_levels = ilk_wm_max_level(dev) + 1;
3853         int level;
3854         int ret;
3855         char tmp[32];
3856
3857         if (len >= sizeof(tmp))
3858                 return -EINVAL;
3859
3860         if (copy_from_user(tmp, ubuf, len))
3861                 return -EFAULT;
3862
3863         tmp[len] = '\0';
3864
3865         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3866                      &new[0], &new[1], &new[2], &new[3],
3867                      &new[4], &new[5], &new[6], &new[7]);
3868         if (ret != num_levels)
3869                 return -EINVAL;
3870
3871         drm_modeset_lock_all(dev);
3872
3873         for (level = 0; level < num_levels; level++)
3874                 wm[level] = new[level];
3875
3876         drm_modeset_unlock_all(dev);
3877
3878         return len;
3879 }
3880
3881
3882 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3883                                     size_t len, loff_t *offp)
3884 {
3885         struct seq_file *m = file->private_data;
3886         struct drm_device *dev = m->private;
3887         struct drm_i915_private *dev_priv = dev->dev_private;
3888         uint16_t *latencies;
3889
3890         if (INTEL_INFO(dev)->gen >= 9)
3891                 latencies = dev_priv->wm.skl_latency;
3892         else
3893                 latencies = to_i915(dev)->wm.pri_latency;
3894
3895         return wm_latency_write(file, ubuf, len, offp, latencies);
3896 }
3897
3898 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3899                                     size_t len, loff_t *offp)
3900 {
3901         struct seq_file *m = file->private_data;
3902         struct drm_device *dev = m->private;
3903         struct drm_i915_private *dev_priv = dev->dev_private;
3904         uint16_t *latencies;
3905
3906         if (INTEL_INFO(dev)->gen >= 9)
3907                 latencies = dev_priv->wm.skl_latency;
3908         else
3909                 latencies = to_i915(dev)->wm.spr_latency;
3910
3911         return wm_latency_write(file, ubuf, len, offp, latencies);
3912 }
3913
3914 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3915                                     size_t len, loff_t *offp)
3916 {
3917         struct seq_file *m = file->private_data;
3918         struct drm_device *dev = m->private;
3919         struct drm_i915_private *dev_priv = dev->dev_private;
3920         uint16_t *latencies;
3921
3922         if (INTEL_INFO(dev)->gen >= 9)
3923                 latencies = dev_priv->wm.skl_latency;
3924         else
3925                 latencies = to_i915(dev)->wm.cur_latency;
3926
3927         return wm_latency_write(file, ubuf, len, offp, latencies);
3928 }
3929
3930 static const struct file_operations i915_pri_wm_latency_fops = {
3931         .owner = THIS_MODULE,
3932         .open = pri_wm_latency_open,
3933         .read = seq_read,
3934         .llseek = seq_lseek,
3935         .release = single_release,
3936         .write = pri_wm_latency_write
3937 };
3938
3939 static const struct file_operations i915_spr_wm_latency_fops = {
3940         .owner = THIS_MODULE,
3941         .open = spr_wm_latency_open,
3942         .read = seq_read,
3943         .llseek = seq_lseek,
3944         .release = single_release,
3945         .write = spr_wm_latency_write
3946 };
3947
3948 static const struct file_operations i915_cur_wm_latency_fops = {
3949         .owner = THIS_MODULE,
3950         .open = cur_wm_latency_open,
3951         .read = seq_read,
3952         .llseek = seq_lseek,
3953         .release = single_release,
3954         .write = cur_wm_latency_write
3955 };
3956
3957 static int
3958 i915_wedged_get(void *data, u64 *val)
3959 {
3960         struct drm_device *dev = data;
3961         struct drm_i915_private *dev_priv = dev->dev_private;
3962
3963         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3964
3965         return 0;
3966 }
3967
3968 static int
3969 i915_wedged_set(void *data, u64 val)
3970 {
3971         struct drm_device *dev = data;
3972         struct drm_i915_private *dev_priv = dev->dev_private;
3973
3974         /*
3975          * There is no safeguard against this debugfs entry colliding
3976          * with the hangcheck calling same i915_handle_error() in
3977          * parallel, causing an explosion. For now we assume that the
3978          * test harness is responsible enough not to inject gpu hangs
3979          * while it is writing to 'i915_wedged'
3980          */
3981
3982         if (i915_reset_in_progress(&dev_priv->gpu_error))
3983                 return -EAGAIN;
3984
3985         intel_runtime_pm_get(dev_priv);
3986
3987         i915_handle_error(dev, val,
3988                           "Manually setting wedged to %llu", val);
3989
3990         intel_runtime_pm_put(dev_priv);
3991
3992         return 0;
3993 }
3994
3995 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3996                         i915_wedged_get, i915_wedged_set,
3997                         "%llu\n");
3998
3999 static int
4000 i915_ring_stop_get(void *data, u64 *val)
4001 {
4002         struct drm_device *dev = data;
4003         struct drm_i915_private *dev_priv = dev->dev_private;
4004
4005         *val = dev_priv->gpu_error.stop_rings;
4006
4007         return 0;
4008 }
4009
4010 static int
4011 i915_ring_stop_set(void *data, u64 val)
4012 {
4013         struct drm_device *dev = data;
4014         struct drm_i915_private *dev_priv = dev->dev_private;
4015         int ret;
4016
4017         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4018
4019         ret = mutex_lock_interruptible(&dev->struct_mutex);
4020         if (ret)
4021                 return ret;
4022
4023         dev_priv->gpu_error.stop_rings = val;
4024         mutex_unlock(&dev->struct_mutex);
4025
4026         return 0;
4027 }
4028
4029 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4030                         i915_ring_stop_get, i915_ring_stop_set,
4031                         "0x%08llx\n");
4032
4033 static int
4034 i915_ring_missed_irq_get(void *data, u64 *val)
4035 {
4036         struct drm_device *dev = data;
4037         struct drm_i915_private *dev_priv = dev->dev_private;
4038
4039         *val = dev_priv->gpu_error.missed_irq_rings;
4040         return 0;
4041 }
4042
4043 static int
4044 i915_ring_missed_irq_set(void *data, u64 val)
4045 {
4046         struct drm_device *dev = data;
4047         struct drm_i915_private *dev_priv = dev->dev_private;
4048         int ret;
4049
4050         /* Lock against concurrent debugfs callers */
4051         ret = mutex_lock_interruptible(&dev->struct_mutex);
4052         if (ret)
4053                 return ret;
4054         dev_priv->gpu_error.missed_irq_rings = val;
4055         mutex_unlock(&dev->struct_mutex);
4056
4057         return 0;
4058 }
4059
4060 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4061                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4062                         "0x%08llx\n");
4063
4064 static int
4065 i915_ring_test_irq_get(void *data, u64 *val)
4066 {
4067         struct drm_device *dev = data;
4068         struct drm_i915_private *dev_priv = dev->dev_private;
4069
4070         *val = dev_priv->gpu_error.test_irq_rings;
4071
4072         return 0;
4073 }
4074
4075 static int
4076 i915_ring_test_irq_set(void *data, u64 val)
4077 {
4078         struct drm_device *dev = data;
4079         struct drm_i915_private *dev_priv = dev->dev_private;
4080         int ret;
4081
4082         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4083
4084         /* Lock against concurrent debugfs callers */
4085         ret = mutex_lock_interruptible(&dev->struct_mutex);
4086         if (ret)
4087                 return ret;
4088
4089         dev_priv->gpu_error.test_irq_rings = val;
4090         mutex_unlock(&dev->struct_mutex);
4091
4092         return 0;
4093 }
4094
4095 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4096                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4097                         "0x%08llx\n");
4098
4099 #define DROP_UNBOUND 0x1
4100 #define DROP_BOUND 0x2
4101 #define DROP_RETIRE 0x4
4102 #define DROP_ACTIVE 0x8
4103 #define DROP_ALL (DROP_UNBOUND | \
4104                   DROP_BOUND | \
4105                   DROP_RETIRE | \
4106                   DROP_ACTIVE)
4107 static int
4108 i915_drop_caches_get(void *data, u64 *val)
4109 {
4110         *val = DROP_ALL;
4111
4112         return 0;
4113 }
4114
4115 static int
4116 i915_drop_caches_set(void *data, u64 val)
4117 {
4118         struct drm_device *dev = data;
4119         struct drm_i915_private *dev_priv = dev->dev_private;
4120         int ret;
4121
4122         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4123
4124         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4125          * on ioctls on -EAGAIN. */
4126         ret = mutex_lock_interruptible(&dev->struct_mutex);
4127         if (ret)
4128                 return ret;
4129
4130         if (val & DROP_ACTIVE) {
4131                 ret = i915_gpu_idle(dev);
4132                 if (ret)
4133                         goto unlock;
4134         }
4135
4136         if (val & (DROP_RETIRE | DROP_ACTIVE))
4137                 i915_gem_retire_requests(dev);
4138
4139         if (val & DROP_BOUND)
4140                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4141
4142         if (val & DROP_UNBOUND)
4143                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4144
4145 unlock:
4146         mutex_unlock(&dev->struct_mutex);
4147
4148         return ret;
4149 }
4150
4151 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4152                         i915_drop_caches_get, i915_drop_caches_set,
4153                         "0x%08llx\n");
4154
4155 static int
4156 i915_max_freq_get(void *data, u64 *val)
4157 {
4158         struct drm_device *dev = data;
4159         struct drm_i915_private *dev_priv = dev->dev_private;
4160         int ret;
4161
4162         if (INTEL_INFO(dev)->gen < 6)
4163                 return -ENODEV;
4164
4165         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4166
4167         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4168         if (ret)
4169                 return ret;
4170
4171         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4172         mutex_unlock(&dev_priv->rps.hw_lock);
4173
4174         return 0;
4175 }
4176
4177 static int
4178 i915_max_freq_set(void *data, u64 val)
4179 {
4180         struct drm_device *dev = data;
4181         struct drm_i915_private *dev_priv = dev->dev_private;
4182         u32 rp_state_cap, hw_max, hw_min;
4183         int ret;
4184
4185         if (INTEL_INFO(dev)->gen < 6)
4186                 return -ENODEV;
4187
4188         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4189
4190         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4191
4192         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4193         if (ret)
4194                 return ret;
4195
4196         /*
4197          * Turbo will still be enabled, but won't go above the set value.
4198          */
4199         if (IS_VALLEYVIEW(dev)) {
4200                 val = intel_freq_opcode(dev_priv, val);
4201
4202                 hw_max = dev_priv->rps.max_freq;
4203                 hw_min = dev_priv->rps.min_freq;
4204         } else {
4205                 val = intel_freq_opcode(dev_priv, val);
4206
4207                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4208                 hw_max = dev_priv->rps.max_freq;
4209                 hw_min = (rp_state_cap >> 16) & 0xff;
4210         }
4211
4212         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4213                 mutex_unlock(&dev_priv->rps.hw_lock);
4214                 return -EINVAL;
4215         }
4216
4217         dev_priv->rps.max_freq_softlimit = val;
4218
4219         intel_set_rps(dev, val);
4220
4221         mutex_unlock(&dev_priv->rps.hw_lock);
4222
4223         return 0;
4224 }
4225
4226 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4227                         i915_max_freq_get, i915_max_freq_set,
4228                         "%llu\n");
4229
4230 static int
4231 i915_min_freq_get(void *data, u64 *val)
4232 {
4233         struct drm_device *dev = data;
4234         struct drm_i915_private *dev_priv = dev->dev_private;
4235         int ret;
4236
4237         if (INTEL_INFO(dev)->gen < 6)
4238                 return -ENODEV;
4239
4240         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4241
4242         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4243         if (ret)
4244                 return ret;
4245
4246         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4247         mutex_unlock(&dev_priv->rps.hw_lock);
4248
4249         return 0;
4250 }
4251
4252 static int
4253 i915_min_freq_set(void *data, u64 val)
4254 {
4255         struct drm_device *dev = data;
4256         struct drm_i915_private *dev_priv = dev->dev_private;
4257         u32 rp_state_cap, hw_max, hw_min;
4258         int ret;
4259
4260         if (INTEL_INFO(dev)->gen < 6)
4261                 return -ENODEV;
4262
4263         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4264
4265         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4266
4267         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4268         if (ret)
4269                 return ret;
4270
4271         /*
4272          * Turbo will still be enabled, but won't go below the set value.
4273          */
4274         if (IS_VALLEYVIEW(dev)) {
4275                 val = intel_freq_opcode(dev_priv, val);
4276
4277                 hw_max = dev_priv->rps.max_freq;
4278                 hw_min = dev_priv->rps.min_freq;
4279         } else {
4280                 val = intel_freq_opcode(dev_priv, val);
4281
4282                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4283                 hw_max = dev_priv->rps.max_freq;
4284                 hw_min = (rp_state_cap >> 16) & 0xff;
4285         }
4286
4287         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4288                 mutex_unlock(&dev_priv->rps.hw_lock);
4289                 return -EINVAL;
4290         }
4291
4292         dev_priv->rps.min_freq_softlimit = val;
4293
4294         intel_set_rps(dev, val);
4295
4296         mutex_unlock(&dev_priv->rps.hw_lock);
4297
4298         return 0;
4299 }
4300
4301 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4302                         i915_min_freq_get, i915_min_freq_set,
4303                         "%llu\n");
4304
4305 static int
4306 i915_cache_sharing_get(void *data, u64 *val)
4307 {
4308         struct drm_device *dev = data;
4309         struct drm_i915_private *dev_priv = dev->dev_private;
4310         u32 snpcr;
4311         int ret;
4312
4313         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4314                 return -ENODEV;
4315
4316         ret = mutex_lock_interruptible(&dev->struct_mutex);
4317         if (ret)
4318                 return ret;
4319         intel_runtime_pm_get(dev_priv);
4320
4321         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4322
4323         intel_runtime_pm_put(dev_priv);
4324         mutex_unlock(&dev_priv->dev->struct_mutex);
4325
4326         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4327
4328         return 0;
4329 }
4330
4331 static int
4332 i915_cache_sharing_set(void *data, u64 val)
4333 {
4334         struct drm_device *dev = data;
4335         struct drm_i915_private *dev_priv = dev->dev_private;
4336         u32 snpcr;
4337
4338         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4339                 return -ENODEV;
4340
4341         if (val > 3)
4342                 return -EINVAL;
4343
4344         intel_runtime_pm_get(dev_priv);
4345         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4346
4347         /* Update the cache sharing policy here as well */
4348         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4349         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4350         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4351         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4352
4353         intel_runtime_pm_put(dev_priv);
4354         return 0;
4355 }
4356
4357 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4358                         i915_cache_sharing_get, i915_cache_sharing_set,
4359                         "%llu\n");
4360
4361 static int i915_forcewake_open(struct inode *inode, struct file *file)
4362 {
4363         struct drm_device *dev = inode->i_private;
4364         struct drm_i915_private *dev_priv = dev->dev_private;
4365
4366         if (INTEL_INFO(dev)->gen < 6)
4367                 return 0;
4368
4369         intel_runtime_pm_get(dev_priv);
4370         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4371
4372         return 0;
4373 }
4374
4375 static int i915_forcewake_release(struct inode *inode, struct file *file)
4376 {
4377         struct drm_device *dev = inode->i_private;
4378         struct drm_i915_private *dev_priv = dev->dev_private;
4379
4380         if (INTEL_INFO(dev)->gen < 6)
4381                 return 0;
4382
4383         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4384         intel_runtime_pm_put(dev_priv);
4385
4386         return 0;
4387 }
4388
4389 static const struct file_operations i915_forcewake_fops = {
4390         .owner = THIS_MODULE,
4391         .open = i915_forcewake_open,
4392         .release = i915_forcewake_release,
4393 };
4394
4395 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4396 {
4397         struct drm_device *dev = minor->dev;
4398         struct dentry *ent;
4399
4400         ent = debugfs_create_file("i915_forcewake_user",
4401                                   S_IRUSR,
4402                                   root, dev,
4403                                   &i915_forcewake_fops);
4404         if (!ent)
4405                 return -ENOMEM;
4406
4407         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4408 }
4409
4410 static int i915_debugfs_create(struct dentry *root,
4411                                struct drm_minor *minor,
4412                                const char *name,
4413                                const struct file_operations *fops)
4414 {
4415         struct drm_device *dev = minor->dev;
4416         struct dentry *ent;
4417
4418         ent = debugfs_create_file(name,
4419                                   S_IRUGO | S_IWUSR,
4420                                   root, dev,
4421                                   fops);
4422         if (!ent)
4423                 return -ENOMEM;
4424
4425         return drm_add_fake_info_node(minor, ent, fops);
4426 }
4427
4428 static const struct drm_info_list i915_debugfs_list[] = {
4429         {"i915_capabilities", i915_capabilities, 0},
4430         {"i915_gem_objects", i915_gem_object_info, 0},
4431         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4432         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4433         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4434         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4435         {"i915_gem_stolen", i915_gem_stolen_list_info },
4436         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4437         {"i915_gem_request", i915_gem_request_info, 0},
4438         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4439         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4440         {"i915_gem_interrupt", i915_interrupt_info, 0},
4441         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4442         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4443         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4444         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4445         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4446         {"i915_frequency_info", i915_frequency_info, 0},
4447         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4448         {"i915_drpc_info", i915_drpc_info, 0},
4449         {"i915_emon_status", i915_emon_status, 0},
4450         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4451         {"i915_fbc_status", i915_fbc_status, 0},
4452         {"i915_ips_status", i915_ips_status, 0},
4453         {"i915_sr_status", i915_sr_status, 0},
4454         {"i915_opregion", i915_opregion, 0},
4455         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4456         {"i915_context_status", i915_context_status, 0},
4457         {"i915_dump_lrc", i915_dump_lrc, 0},
4458         {"i915_execlists", i915_execlists, 0},
4459         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4460         {"i915_swizzle_info", i915_swizzle_info, 0},
4461         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4462         {"i915_llc", i915_llc, 0},
4463         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4464         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4465         {"i915_energy_uJ", i915_energy_uJ, 0},
4466         {"i915_pc8_status", i915_pc8_status, 0},
4467         {"i915_power_domain_info", i915_power_domain_info, 0},
4468         {"i915_display_info", i915_display_info, 0},
4469         {"i915_semaphore_status", i915_semaphore_status, 0},
4470         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4471         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4472         {"i915_wa_registers", i915_wa_registers, 0},
4473         {"i915_ddb_info", i915_ddb_info, 0},
4474 };
4475 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4476
4477 static const struct i915_debugfs_files {
4478         const char *name;
4479         const struct file_operations *fops;
4480 } i915_debugfs_files[] = {
4481         {"i915_wedged", &i915_wedged_fops},
4482         {"i915_max_freq", &i915_max_freq_fops},
4483         {"i915_min_freq", &i915_min_freq_fops},
4484         {"i915_cache_sharing", &i915_cache_sharing_fops},
4485         {"i915_ring_stop", &i915_ring_stop_fops},
4486         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4487         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4488         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4489         {"i915_error_state", &i915_error_state_fops},
4490         {"i915_next_seqno", &i915_next_seqno_fops},
4491         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4492         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4493         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4494         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4495         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4496 };
4497
4498 void intel_display_crc_init(struct drm_device *dev)
4499 {
4500         struct drm_i915_private *dev_priv = dev->dev_private;
4501         enum pipe pipe;
4502
4503         for_each_pipe(dev_priv, pipe) {
4504                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4505
4506                 pipe_crc->opened = false;
4507                 spin_lock_init(&pipe_crc->lock);
4508                 init_waitqueue_head(&pipe_crc->wq);
4509         }
4510 }
4511
4512 int i915_debugfs_init(struct drm_minor *minor)
4513 {
4514         int ret, i;
4515
4516         ret = i915_forcewake_create(minor->debugfs_root, minor);
4517         if (ret)
4518                 return ret;
4519
4520         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4521                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4522                 if (ret)
4523                         return ret;
4524         }
4525
4526         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4527                 ret = i915_debugfs_create(minor->debugfs_root, minor,
4528                                           i915_debugfs_files[i].name,
4529                                           i915_debugfs_files[i].fops);
4530                 if (ret)
4531                         return ret;
4532         }
4533
4534         return drm_debugfs_create_files(i915_debugfs_list,
4535                                         I915_DEBUGFS_ENTRIES,
4536                                         minor->debugfs_root, minor);
4537 }
4538
4539 void i915_debugfs_cleanup(struct drm_minor *minor)
4540 {
4541         int i;
4542
4543         drm_debugfs_remove_files(i915_debugfs_list,
4544                                  I915_DEBUGFS_ENTRIES, minor);
4545
4546         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4547                                  1, minor);
4548
4549         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4550                 struct drm_info_list *info_list =
4551                         (struct drm_info_list *)&i915_pipe_crc_data[i];
4552
4553                 drm_debugfs_remove_files(info_list, 1, minor);
4554         }
4555
4556         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4557                 struct drm_info_list *info_list =
4558                         (struct drm_info_list *) i915_debugfs_files[i].fops;
4559
4560                 drm_debugfs_remove_files(info_list, 1, minor);
4561         }
4562 }