drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (i915_gem_obj_is_pinned(obj))
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct i915_vma *vma;
 124         int pin_count = 0;
 125
 126         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
 127                    &obj->base,
 128                    get_pin_flag(obj),
 129                    get_tiling_flag(obj),
 130                    get_global_flag(obj),
 131                    obj->base.size / 1024,
 132                    obj->base.read_domains,
 133                    obj->base.write_domain,
 134                    i915_gem_request_get_seqno(obj->last_read_req),
 135                    i915_gem_request_get_seqno(obj->last_write_req),
 136                    i915_gem_request_get_seqno(obj->last_fenced_req),
 137                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 138                    obj->dirty ? " dirty" : "",
 139                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 140         if (obj->base.name)
 141                 seq_printf(m, " (name: %d)", obj->base.name);
 142         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 143                 if (vma->pin_count > 0)
 144                         pin_count++;
 145         }
 146         seq_printf(m, " (pinned x %d)", pin_count);
 147         if (obj->pin_display)
 148                 seq_printf(m, " (display)");
 149         if (obj->fence_reg != I915_FENCE_REG_NONE)
 150                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 151         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 152                 if (!i915_is_ggtt(vma->vm))
 153                         seq_puts(m, " (pp");
 154                 else
 155                         seq_puts(m, " (g");
 156                 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
 157                            vma->node.start, vma->node.size,
 158                            vma->ggtt_view.type);
 159         }
 160         if (obj->stolen)
 161                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 162         if (obj->pin_mappable || obj->fault_mappable) {
 163                 char s[3], *t = s;
 164                 if (obj->pin_mappable)
 165                         *t++ = 'p';
 166                 if (obj->fault_mappable)
 167                         *t++ = 'f';
 168                 *t = '\0';
 169                 seq_printf(m, " (%s mappable)", s);
 170         }
 171         if (obj->last_read_req != NULL)
 172                 seq_printf(m, " (%s)",
 173                            i915_gem_request_get_ring(obj->last_read_req)->name);
 174         if (obj->frontbuffer_bits)
 175                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 176 }
 177
 178 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 179 {
 180         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 181         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 182         seq_putc(m, ' ');
 183 }
 184
 185 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 186 {
 187         struct drm_info_node *node = m->private;
 188         uintptr_t list = (uintptr_t) node->info_ent->data;
 189         struct list_head *head;
 190         struct drm_device *dev = node->minor->dev;
 191         struct drm_i915_private *dev_priv = dev->dev_private;
 192         struct i915_address_space *vm = &dev_priv->gtt.base;
 193         struct i915_vma *vma;
 194         size_t total_obj_size, total_gtt_size;
 195         int count, ret;
 196
 197         ret = mutex_lock_interruptible(&dev->struct_mutex);
 198         if (ret)
 199                 return ret;
 200
 201         /* FIXME: the user of this interface might want more than just GGTT */
 202         switch (list) {
 203         case ACTIVE_LIST:
 204                 seq_puts(m, "Active:\n");
 205                 head = &vm->active_list;
 206                 break;
 207         case INACTIVE_LIST:
 208                 seq_puts(m, "Inactive:\n");
 209                 head = &vm->inactive_list;
 210                 break;
 211         default:
 212                 mutex_unlock(&dev->struct_mutex);
 213                 return -EINVAL;
 214         }
 215
 216         total_obj_size = total_gtt_size = count = 0;
 217         list_for_each_entry(vma, head, mm_list) {
 218                 seq_printf(m, "   ");
 219                 describe_obj(m, vma->obj);
 220                 seq_printf(m, "\n");
 221                 total_obj_size += vma->obj->base.size;
 222                 total_gtt_size += vma->node.size;
 223                 count++;
 224         }
 225         mutex_unlock(&dev->struct_mutex);
 226
 227         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 228                    count, total_obj_size, total_gtt_size);
 229         return 0;
 230 }
 231
 232 static int obj_rank_by_stolen(void *priv,
 233                               struct list_head *A, struct list_head *B)
 234 {
 235         struct drm_i915_gem_object *a =
 236                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 237         struct drm_i915_gem_object *b =
 238                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 239
 240         return a->stolen->start - b->stolen->start;
 241 }
 242
 243 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 244 {
 245         struct drm_info_node *node = m->private;
 246         struct drm_device *dev = node->minor->dev;
 247         struct drm_i915_private *dev_priv = dev->dev_private;
 248         struct drm_i915_gem_object *obj;
 249         size_t total_obj_size, total_gtt_size;
 250         LIST_HEAD(stolen);
 251         int count, ret;
 252
 253         ret = mutex_lock_interruptible(&dev->struct_mutex);
 254         if (ret)
 255                 return ret;
 256
 257         total_obj_size = total_gtt_size = count = 0;
 258         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 259                 if (obj->stolen == NULL)
 260                         continue;
 261
 262                 list_add(&obj->obj_exec_link, &stolen);
 263
 264                 total_obj_size += obj->base.size;
 265                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 266                 count++;
 267         }
 268         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 269                 if (obj->stolen == NULL)
 270                         continue;
 271
 272                 list_add(&obj->obj_exec_link, &stolen);
 273
 274                 total_obj_size += obj->base.size;
 275                 count++;
 276         }
 277         list_sort(NULL, &stolen, obj_rank_by_stolen);
 278         seq_puts(m, "Stolen:\n");
 279         while (!list_empty(&stolen)) {
 280                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 281                 seq_puts(m, "   ");
 282                 describe_obj(m, obj);
 283                 seq_putc(m, '\n');
 284                 list_del_init(&obj->obj_exec_link);
 285         }
 286         mutex_unlock(&dev->struct_mutex);
 287
 288         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 289                    count, total_obj_size, total_gtt_size);
 290         return 0;
 291 }
 292
 293 #define count_objects(list, member) do { \
 294         list_for_each_entry(obj, list, member) { \
 295                 size += i915_gem_obj_ggtt_size(obj); \
 296                 ++count; \
 297                 if (obj->map_and_fenceable) { \
 298                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 299                         ++mappable_count; \
 300                 } \
 301         } \
 302 } while (0)
 303
 304 struct file_stats {
 305         struct drm_i915_file_private *file_priv;
 306         int count;
 307         size_t total, unbound;
 308         size_t global, shared;
 309         size_t active, inactive;
 310 };
 311
 312 static int per_file_stats(int id, void *ptr, void *data)
 313 {
 314         struct drm_i915_gem_object *obj = ptr;
 315         struct file_stats *stats = data;
 316         struct i915_vma *vma;
 317
 318         stats->count++;
 319         stats->total += obj->base.size;
 320
 321         if (obj->base.name || obj->base.dma_buf)
 322                 stats->shared += obj->base.size;
 323
 324         if (USES_FULL_PPGTT(obj->base.dev)) {
 325                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 326                         struct i915_hw_ppgtt *ppgtt;
 327
 328                         if (!drm_mm_node_allocated(&vma->node))
 329                                 continue;
 330
 331                         if (i915_is_ggtt(vma->vm)) {
 332                                 stats->global += obj->base.size;
 333                                 continue;
 334                         }
 335
 336                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 337                         if (ppgtt->file_priv != stats->file_priv)
 338                                 continue;
 339
 340                         if (obj->active) /* XXX per-vma statistic */
 341                                 stats->active += obj->base.size;
 342                         else
 343                                 stats->inactive += obj->base.size;
 344
 345                         return 0;
 346                 }
 347         } else {
 348                 if (i915_gem_obj_ggtt_bound(obj)) {
 349                         stats->global += obj->base.size;
 350                         if (obj->active)
 351                                 stats->active += obj->base.size;
 352                         else
 353                                 stats->inactive += obj->base.size;
 354                         return 0;
 355                 }
 356         }
 357
 358         if (!list_empty(&obj->global_list))
 359                 stats->unbound += obj->base.size;
 360
 361         return 0;
 362 }
 363
 364 #define print_file_stats(m, name, stats) \
 365         seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
 366                    name, \
 367                    stats.count, \
 368                    stats.total, \
 369                    stats.active, \
 370                    stats.inactive, \
 371                    stats.global, \
 372                    stats.shared, \
 373                    stats.unbound)
 374
 375 static void print_batch_pool_stats(struct seq_file *m,
 376                                    struct drm_i915_private *dev_priv)
 377 {
 378         struct drm_i915_gem_object *obj;
 379         struct file_stats stats;
 380
 381         memset(&stats, 0, sizeof(stats));
 382
 383         list_for_each_entry(obj,
 384                             &dev_priv->mm.batch_pool.cache_list,
 385                             batch_pool_list)
 386                 per_file_stats(0, obj, &stats);
 387
 388         print_file_stats(m, "batch pool", stats);
 389 }
 390
 391 #define count_vmas(list, member) do { \
 392         list_for_each_entry(vma, list, member) { \
 393                 size += i915_gem_obj_ggtt_size(vma->obj); \
 394                 ++count; \
 395                 if (vma->obj->map_and_fenceable) { \
 396                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 397                         ++mappable_count; \
 398                 } \
 399         } \
 400 } while (0)
 401
 402 static int i915_gem_object_info(struct seq_file *m, void* data)
 403 {
 404         struct drm_info_node *node = m->private;
 405         struct drm_device *dev = node->minor->dev;
 406         struct drm_i915_private *dev_priv = dev->dev_private;
 407         u32 count, mappable_count, purgeable_count;
 408         size_t size, mappable_size, purgeable_size;
 409         struct drm_i915_gem_object *obj;
 410         struct i915_address_space *vm = &dev_priv->gtt.base;
 411         struct drm_file *file;
 412         struct i915_vma *vma;
 413         int ret;
 414
 415         ret = mutex_lock_interruptible(&dev->struct_mutex);
 416         if (ret)
 417                 return ret;
 418
 419         seq_printf(m, "%u objects, %zu bytes\n",
 420                    dev_priv->mm.object_count,
 421                    dev_priv->mm.object_memory);
 422
 423         size = count = mappable_size = mappable_count = 0;
 424         count_objects(&dev_priv->mm.bound_list, global_list);
 425         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 426                    count, mappable_count, size, mappable_size);
 427
 428         size = count = mappable_size = mappable_count = 0;
 429         count_vmas(&vm->active_list, mm_list);
 430         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 431                    count, mappable_count, size, mappable_size);
 432
 433         size = count = mappable_size = mappable_count = 0;
 434         count_vmas(&vm->inactive_list, mm_list);
 435         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 436                    count, mappable_count, size, mappable_size);
 437
 438         size = count = purgeable_size = purgeable_count = 0;
 439         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 440                 size += obj->base.size, ++count;
 441                 if (obj->madv == I915_MADV_DONTNEED)
 442                         purgeable_size += obj->base.size, ++purgeable_count;
 443         }
 444         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 445
 446         size = count = mappable_size = mappable_count = 0;
 447         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 448                 if (obj->fault_mappable) {
 449                         size += i915_gem_obj_ggtt_size(obj);
 450                         ++count;
 451                 }
 452                 if (obj->pin_mappable) {
 453                         mappable_size += i915_gem_obj_ggtt_size(obj);
 454                         ++mappable_count;
 455                 }
 456                 if (obj->madv == I915_MADV_DONTNEED) {
 457                         purgeable_size += obj->base.size;
 458                         ++purgeable_count;
 459                 }
 460         }
 461         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 462                    purgeable_count, purgeable_size);
 463         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 464                    mappable_count, mappable_size);
 465         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 466                    count, size);
 467
 468         seq_printf(m, "%zu [%lu] gtt total\n",
 469                    dev_priv->gtt.base.total,
 470                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 471
 472         seq_putc(m, '\n');
 473         print_batch_pool_stats(m, dev_priv);
 474
 475         seq_putc(m, '\n');
 476         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 477                 struct file_stats stats;
 478                 struct task_struct *task;
 479
 480                 memset(&stats, 0, sizeof(stats));
 481                 stats.file_priv = file->driver_priv;
 482                 spin_lock(&file->table_lock);
 483                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 484                 spin_unlock(&file->table_lock);
 485                 /*
 486                  * Although we have a valid reference on file->pid, that does
 487                  * not guarantee that the task_struct who called get_pid() is
 488                  * still alive (e.g. get_pid(current) => fork() => exit()).
 489                  * Therefore, we need to protect this ->comm access using RCU.
 490                  */
 491                 rcu_read_lock();
 492                 task = pid_task(file->pid, PIDTYPE_PID);
 493                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 494                 rcu_read_unlock();
 495         }
 496
 497         mutex_unlock(&dev->struct_mutex);
 498
 499         return 0;
 500 }
 501
 502 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 503 {
 504         struct drm_info_node *node = m->private;
 505         struct drm_device *dev = node->minor->dev;
 506         uintptr_t list = (uintptr_t) node->info_ent->data;
 507         struct drm_i915_private *dev_priv = dev->dev_private;
 508         struct drm_i915_gem_object *obj;
 509         size_t total_obj_size, total_gtt_size;
 510         int count, ret;
 511
 512         ret = mutex_lock_interruptible(&dev->struct_mutex);
 513         if (ret)
 514                 return ret;
 515
 516         total_obj_size = total_gtt_size = count = 0;
 517         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 518                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 519                         continue;
 520
 521                 seq_puts(m, "   ");
 522                 describe_obj(m, obj);
 523                 seq_putc(m, '\n');
 524                 total_obj_size += obj->base.size;
 525                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 526                 count++;
 527         }
 528
 529         mutex_unlock(&dev->struct_mutex);
 530
 531         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 532                    count, total_obj_size, total_gtt_size);
 533
 534         return 0;
 535 }
 536
 537 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 538 {
 539         struct drm_info_node *node = m->private;
 540         struct drm_device *dev = node->minor->dev;
 541         struct drm_i915_private *dev_priv = dev->dev_private;
 542         struct intel_crtc *crtc;
 543         int ret;
 544
 545         ret = mutex_lock_interruptible(&dev->struct_mutex);
 546         if (ret)
 547                 return ret;
 548
 549         for_each_intel_crtc(dev, crtc) {
 550                 const char pipe = pipe_name(crtc->pipe);
 551                 const char plane = plane_name(crtc->plane);
 552                 struct intel_unpin_work *work;
 553
 554                 spin_lock_irq(&dev->event_lock);
 555                 work = crtc->unpin_work;
 556                 if (work == NULL) {
 557                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 558                                    pipe, plane);
 559                 } else {
 560                         u32 addr;
 561
 562                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 563                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 564                                            pipe, plane);
 565                         } else {
 566                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 567                                            pipe, plane);
 568                         }
 569                         if (work->flip_queued_req) {
 570                                 struct intel_engine_cs *ring =
 571                                         i915_gem_request_get_ring(work->flip_queued_req);
 572
 573                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 574                                            ring->name,
 575                                            i915_gem_request_get_seqno(work->flip_queued_req),
 576                                            dev_priv->next_seqno,
 577                                            ring->get_seqno(ring, true),
 578                                            i915_gem_request_completed(work->flip_queued_req, true));
 579                         } else
 580                                 seq_printf(m, "Flip not associated with any ring\n");
 581                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 582                                    work->flip_queued_vblank,
 583                                    work->flip_ready_vblank,
 584                                    drm_crtc_vblank_count(&crtc->base));
 585                         if (work->enable_stall_check)
 586                                 seq_puts(m, "Stall check enabled, ");
 587                         else
 588                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 589                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 590
 591                         if (INTEL_INFO(dev)->gen >= 4)
 592                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 593                         else
 594                                 addr = I915_READ(DSPADDR(crtc->plane));
 595                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 596
 597                         if (work->pending_flip_obj) {
 598                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 599                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 600                         }
 601                 }
 602                 spin_unlock_irq(&dev->event_lock);
 603         }
 604
 605         mutex_unlock(&dev->struct_mutex);
 606
 607         return 0;
 608 }
 609
 610 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 611 {
 612         struct drm_info_node *node = m->private;
 613         struct drm_device *dev = node->minor->dev;
 614         struct drm_i915_private *dev_priv = dev->dev_private;
 615         struct drm_i915_gem_object *obj;
 616         int count = 0;
 617         int ret;
 618
 619         ret = mutex_lock_interruptible(&dev->struct_mutex);
 620         if (ret)
 621                 return ret;
 622
 623         seq_puts(m, "cache:\n");
 624         list_for_each_entry(obj,
 625                             &dev_priv->mm.batch_pool.cache_list,
 626                             batch_pool_list) {
 627                 seq_puts(m, "   ");
 628                 describe_obj(m, obj);
 629                 seq_putc(m, '\n');
 630                 count++;
 631         }
 632
 633         seq_printf(m, "total: %d\n", count);
 634
 635         mutex_unlock(&dev->struct_mutex);
 636
 637         return 0;
 638 }
 639
 640 static int i915_gem_request_info(struct seq_file *m, void *data)
 641 {
 642         struct drm_info_node *node = m->private;
 643         struct drm_device *dev = node->minor->dev;
 644         struct drm_i915_private *dev_priv = dev->dev_private;
 645         struct intel_engine_cs *ring;
 646         struct drm_i915_gem_request *gem_request;
 647         int ret, count, i;
 648
 649         ret = mutex_lock_interruptible(&dev->struct_mutex);
 650         if (ret)
 651                 return ret;
 652
 653         count = 0;
 654         for_each_ring(ring, dev_priv, i) {
 655                 if (list_empty(&ring->request_list))
 656                         continue;
 657
 658                 seq_printf(m, "%s requests:\n", ring->name);
 659                 list_for_each_entry(gem_request,
 660                                     &ring->request_list,
 661                                     list) {
 662                         seq_printf(m, "    %x @ %d\n",
 663                                    gem_request->seqno,
 664                                    (int) (jiffies - gem_request->emitted_jiffies));
 665                 }
 666                 count++;
 667         }
 668         mutex_unlock(&dev->struct_mutex);
 669
 670         if (count == 0)
 671                 seq_puts(m, "No requests\n");
 672
 673         return 0;
 674 }
 675
 676 static void i915_ring_seqno_info(struct seq_file *m,
 677                                  struct intel_engine_cs *ring)
 678 {
 679         if (ring->get_seqno) {
 680                 seq_printf(m, "Current sequence (%s): %x\n",
 681                            ring->name, ring->get_seqno(ring, false));
 682         }
 683 }
 684
 685 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 686 {
 687         struct drm_info_node *node = m->private;
 688         struct drm_device *dev = node->minor->dev;
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690         struct intel_engine_cs *ring;
 691         int ret, i;
 692
 693         ret = mutex_lock_interruptible(&dev->struct_mutex);
 694         if (ret)
 695                 return ret;
 696         intel_runtime_pm_get(dev_priv);
 697
 698         for_each_ring(ring, dev_priv, i)
 699                 i915_ring_seqno_info(m, ring);
 700
 701         intel_runtime_pm_put(dev_priv);
 702         mutex_unlock(&dev->struct_mutex);
 703
 704         return 0;
 705 }
 706
 707
 708 static int i915_interrupt_info(struct seq_file *m, void *data)
 709 {
 710         struct drm_info_node *node = m->private;
 711         struct drm_device *dev = node->minor->dev;
 712         struct drm_i915_private *dev_priv = dev->dev_private;
 713         struct intel_engine_cs *ring;
 714         int ret, i, pipe;
 715
 716         ret = mutex_lock_interruptible(&dev->struct_mutex);
 717         if (ret)
 718                 return ret;
 719         intel_runtime_pm_get(dev_priv);
 720
 721         if (IS_CHERRYVIEW(dev)) {
 722                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 723                            I915_READ(GEN8_MASTER_IRQ));
 724
 725                 seq_printf(m, "Display IER:\t%08x\n",
 726                            I915_READ(VLV_IER));
 727                 seq_printf(m, "Display IIR:\t%08x\n",
 728                            I915_READ(VLV_IIR));
 729                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 730                            I915_READ(VLV_IIR_RW));
 731                 seq_printf(m, "Display IMR:\t%08x\n",
 732                            I915_READ(VLV_IMR));
 733                 for_each_pipe(dev_priv, pipe)
 734                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 735                                    pipe_name(pipe),
 736                                    I915_READ(PIPESTAT(pipe)));
 737
 738                 seq_printf(m, "Port hotplug:\t%08x\n",
 739                            I915_READ(PORT_HOTPLUG_EN));
 740                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 741                            I915_READ(VLV_DPFLIPSTAT));
 742                 seq_printf(m, "DPINVGTT:\t%08x\n",
 743                            I915_READ(DPINVGTT));
 744
 745                 for (i = 0; i < 4; i++) {
 746                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 747                                    i, I915_READ(GEN8_GT_IMR(i)));
 748                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 749                                    i, I915_READ(GEN8_GT_IIR(i)));
 750                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 751                                    i, I915_READ(GEN8_GT_IER(i)));
 752                 }
 753
 754                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 755                            I915_READ(GEN8_PCU_IMR));
 756                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 757                            I915_READ(GEN8_PCU_IIR));
 758                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 759                            I915_READ(GEN8_PCU_IER));
 760         } else if (INTEL_INFO(dev)->gen >= 8) {
 761                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 762                            I915_READ(GEN8_MASTER_IRQ));
 763
 764                 for (i = 0; i < 4; i++) {
 765                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 766                                    i, I915_READ(GEN8_GT_IMR(i)));
 767                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 768                                    i, I915_READ(GEN8_GT_IIR(i)));
 769                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 770                                    i, I915_READ(GEN8_GT_IER(i)));
 771                 }
 772
 773                 for_each_pipe(dev_priv, pipe) {
 774                         if (!intel_display_power_is_enabled(dev_priv,
 775                                                 POWER_DOMAIN_PIPE(pipe))) {
 776                                 seq_printf(m, "Pipe %c power disabled\n",
 777                                            pipe_name(pipe));
 778                                 continue;
 779                         }
 780                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 781                                    pipe_name(pipe),
 782                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 783                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 784                                    pipe_name(pipe),
 785                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 786                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 787                                    pipe_name(pipe),
 788                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 789                 }
 790
 791                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 792                            I915_READ(GEN8_DE_PORT_IMR));
 793                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 794                            I915_READ(GEN8_DE_PORT_IIR));
 795                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 796                            I915_READ(GEN8_DE_PORT_IER));
 797
 798                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 799                            I915_READ(GEN8_DE_MISC_IMR));
 800                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 801                            I915_READ(GEN8_DE_MISC_IIR));
 802                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 803                            I915_READ(GEN8_DE_MISC_IER));
 804
 805                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 806                            I915_READ(GEN8_PCU_IMR));
 807                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 808                            I915_READ(GEN8_PCU_IIR));
 809                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 810                            I915_READ(GEN8_PCU_IER));
 811         } else if (IS_VALLEYVIEW(dev)) {
 812                 seq_printf(m, "Display IER:\t%08x\n",
 813                            I915_READ(VLV_IER));
 814                 seq_printf(m, "Display IIR:\t%08x\n",
 815                            I915_READ(VLV_IIR));
 816                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 817                            I915_READ(VLV_IIR_RW));
 818                 seq_printf(m, "Display IMR:\t%08x\n",
 819                            I915_READ(VLV_IMR));
 820                 for_each_pipe(dev_priv, pipe)
 821                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 822                                    pipe_name(pipe),
 823                                    I915_READ(PIPESTAT(pipe)));
 824
 825                 seq_printf(m, "Master IER:\t%08x\n",
 826                            I915_READ(VLV_MASTER_IER));
 827
 828                 seq_printf(m, "Render IER:\t%08x\n",
 829                            I915_READ(GTIER));
 830                 seq_printf(m, "Render IIR:\t%08x\n",
 831                            I915_READ(GTIIR));
 832                 seq_printf(m, "Render IMR:\t%08x\n",
 833                            I915_READ(GTIMR));
 834
 835                 seq_printf(m, "PM IER:\t\t%08x\n",
 836                            I915_READ(GEN6_PMIER));
 837                 seq_printf(m, "PM IIR:\t\t%08x\n",
 838                            I915_READ(GEN6_PMIIR));
 839                 seq_printf(m, "PM IMR:\t\t%08x\n",
 840                            I915_READ(GEN6_PMIMR));
 841
 842                 seq_printf(m, "Port hotplug:\t%08x\n",
 843                            I915_READ(PORT_HOTPLUG_EN));
 844                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 845                            I915_READ(VLV_DPFLIPSTAT));
 846                 seq_printf(m, "DPINVGTT:\t%08x\n",
 847                            I915_READ(DPINVGTT));
 848
 849         } else if (!HAS_PCH_SPLIT(dev)) {
 850                 seq_printf(m, "Interrupt enable:    %08x\n",
 851                            I915_READ(IER));
 852                 seq_printf(m, "Interrupt identity:  %08x\n",
 853                            I915_READ(IIR));
 854                 seq_printf(m, "Interrupt mask:      %08x\n",
 855                            I915_READ(IMR));
 856                 for_each_pipe(dev_priv, pipe)
 857                         seq_printf(m, "Pipe %c stat:         %08x\n",
 858                                    pipe_name(pipe),
 859                                    I915_READ(PIPESTAT(pipe)));
 860         } else {
 861                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 862                            I915_READ(DEIER));
 863                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 864                            I915_READ(DEIIR));
 865                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 866                            I915_READ(DEIMR));
 867                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 868                            I915_READ(SDEIER));
 869                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 870                            I915_READ(SDEIIR));
 871                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 872                            I915_READ(SDEIMR));
 873                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 874                            I915_READ(GTIER));
 875                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 876                            I915_READ(GTIIR));
 877                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 878                            I915_READ(GTIMR));
 879         }
 880         for_each_ring(ring, dev_priv, i) {
 881                 if (INTEL_INFO(dev)->gen >= 6) {
 882                         seq_printf(m,
 883                                    "Graphics Interrupt mask (%s):       %08x\n",
 884                                    ring->name, I915_READ_IMR(ring));
 885                 }
 886                 i915_ring_seqno_info(m, ring);
 887         }
 888         intel_runtime_pm_put(dev_priv);
 889         mutex_unlock(&dev->struct_mutex);
 890
 891         return 0;
 892 }
 893
 894 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 895 {
 896         struct drm_info_node *node = m->private;
 897         struct drm_device *dev = node->minor->dev;
 898         struct drm_i915_private *dev_priv = dev->dev_private;
 899         int i, ret;
 900
 901         ret = mutex_lock_interruptible(&dev->struct_mutex);
 902         if (ret)
 903                 return ret;
 904
 905         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 906         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 907         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 908                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 909
 910                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 911                            i, dev_priv->fence_regs[i].pin_count);
 912                 if (obj == NULL)
 913                         seq_puts(m, "unused");
 914                 else
 915                         describe_obj(m, obj);
 916                 seq_putc(m, '\n');
 917         }
 918
 919         mutex_unlock(&dev->struct_mutex);
 920         return 0;
 921 }
 922
 923 static int i915_hws_info(struct seq_file *m, void *data)
 924 {
 925         struct drm_info_node *node = m->private;
 926         struct drm_device *dev = node->minor->dev;
 927         struct drm_i915_private *dev_priv = dev->dev_private;
 928         struct intel_engine_cs *ring;
 929         const u32 *hws;
 930         int i;
 931
 932         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 933         hws = ring->status_page.page_addr;
 934         if (hws == NULL)
 935                 return 0;
 936
 937         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 938                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 939                            i * 4,
 940                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 941         }
 942         return 0;
 943 }
 944
 945 static ssize_t
 946 i915_error_state_write(struct file *filp,
 947                        const char __user *ubuf,
 948                        size_t cnt,
 949                        loff_t *ppos)
 950 {
 951         struct i915_error_state_file_priv *error_priv = filp->private_data;
 952         struct drm_device *dev = error_priv->dev;
 953         int ret;
 954
 955         DRM_DEBUG_DRIVER("Resetting error state\n");
 956
 957         ret = mutex_lock_interruptible(&dev->struct_mutex);
 958         if (ret)
 959                 return ret;
 960
 961         i915_destroy_error_state(dev);
 962         mutex_unlock(&dev->struct_mutex);
 963
 964         return cnt;
 965 }
 966
 967 static int i915_error_state_open(struct inode *inode, struct file *file)
 968 {
 969         struct drm_device *dev = inode->i_private;
 970         struct i915_error_state_file_priv *error_priv;
 971
 972         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 973         if (!error_priv)
 974                 return -ENOMEM;
 975
 976         error_priv->dev = dev;
 977
 978         i915_error_state_get(dev, error_priv);
 979
 980         file->private_data = error_priv;
 981
 982         return 0;
 983 }
 984
 985 static int i915_error_state_release(struct inode *inode, struct file *file)
 986 {
 987         struct i915_error_state_file_priv *error_priv = file->private_data;
 988
 989         i915_error_state_put(error_priv);
 990         kfree(error_priv);
 991
 992         return 0;
 993 }
 994
 995 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 996                                      size_t count, loff_t *pos)
 997 {
 998         struct i915_error_state_file_priv *error_priv = file->private_data;
 999         struct drm_i915_error_state_buf error_str;
1000         loff_t tmp_pos = 0;
1001         ssize_t ret_count = 0;
1002         int ret;
1003
1004         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1005         if (ret)
1006                 return ret;
1007
1008         ret = i915_error_state_to_str(&error_str, error_priv);
1009         if (ret)
1010                 goto out;
1011
1012         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1013                                             error_str.buf,
1014                                             error_str.bytes);
1015
1016         if (ret_count < 0)
1017                 ret = ret_count;
1018         else
1019                 *pos = error_str.start + ret_count;
1020 out:
1021         i915_error_state_buf_release(&error_str);
1022         return ret ?: ret_count;
1023 }
1024
1025 static const struct file_operations i915_error_state_fops = {
1026         .owner = THIS_MODULE,
1027         .open = i915_error_state_open,
1028         .read = i915_error_state_read,
1029         .write = i915_error_state_write,
1030         .llseek = default_llseek,
1031         .release = i915_error_state_release,
1032 };
1033
1034 static int
1035 i915_next_seqno_get(void *data, u64 *val)
1036 {
1037         struct drm_device *dev = data;
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039         int ret;
1040
1041         ret = mutex_lock_interruptible(&dev->struct_mutex);
1042         if (ret)
1043                 return ret;
1044
1045         *val = dev_priv->next_seqno;
1046         mutex_unlock(&dev->struct_mutex);
1047
1048         return 0;
1049 }
1050
1051 static int
1052 i915_next_seqno_set(void *data, u64 val)
1053 {
1054         struct drm_device *dev = data;
1055         int ret;
1056
1057         ret = mutex_lock_interruptible(&dev->struct_mutex);
1058         if (ret)
1059                 return ret;
1060
1061         ret = i915_gem_set_seqno(dev, val);
1062         mutex_unlock(&dev->struct_mutex);
1063
1064         return ret;
1065 }
1066
1067 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1068                         i915_next_seqno_get, i915_next_seqno_set,
1069                         "0x%llx\n");
1070
1071 static int i915_frequency_info(struct seq_file *m, void *unused)
1072 {
1073         struct drm_info_node *node = m->private;
1074         struct drm_device *dev = node->minor->dev;
1075         struct drm_i915_private *dev_priv = dev->dev_private;
1076         int ret = 0;
1077
1078         intel_runtime_pm_get(dev_priv);
1079
1080         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1081
1082         if (IS_GEN5(dev)) {
1083                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1084                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1085
1086                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1087                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1088                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1089                            MEMSTAT_VID_SHIFT);
1090                 seq_printf(m, "Current P-state: %d\n",
1091                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1092         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1093                    IS_BROADWELL(dev)) {
1094                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1095                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1096                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1097                 u32 rpmodectl, rpinclimit, rpdeclimit;
1098                 u32 rpstat, cagf, reqf;
1099                 u32 rpupei, rpcurup, rpprevup;
1100                 u32 rpdownei, rpcurdown, rpprevdown;
1101                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1102                 int max_freq;
1103
1104                 /* RPSTAT1 is in the GT power well */
1105                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1106                 if (ret)
1107                         goto out;
1108
1109                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1110
1111                 reqf = I915_READ(GEN6_RPNSWREQ);
1112                 reqf &= ~GEN6_TURBO_DISABLE;
1113                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1114                         reqf >>= 24;
1115                 else
1116                         reqf >>= 25;
1117                 reqf = intel_gpu_freq(dev_priv, reqf);
1118
1119                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1120                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1121                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1122
1123                 rpstat = I915_READ(GEN6_RPSTAT1);
1124                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1125                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1126                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1127                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1128                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1129                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1130                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1131                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1132                 else
1133                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1134                 cagf = intel_gpu_freq(dev_priv, cagf);
1135
1136                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1137                 mutex_unlock(&dev->struct_mutex);
1138
1139                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1140                         pm_ier = I915_READ(GEN6_PMIER);
1141                         pm_imr = I915_READ(GEN6_PMIMR);
1142                         pm_isr = I915_READ(GEN6_PMISR);
1143                         pm_iir = I915_READ(GEN6_PMIIR);
1144                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1145                 } else {
1146                         pm_ier = I915_READ(GEN8_GT_IER(2));
1147                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1148                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1149                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1150                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1151                 }
1152                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1153                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1154                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1155                 seq_printf(m, "Render p-state ratio: %d\n",
1156                            (gt_perf_status & 0xff00) >> 8);
1157                 seq_printf(m, "Render p-state VID: %d\n",
1158                            gt_perf_status & 0xff);
1159                 seq_printf(m, "Render p-state limit: %d\n",
1160                            rp_state_limits & 0xff);
1161                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1162                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1163                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1164                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1165                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1166                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1167                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1168                            GEN6_CURICONT_MASK);
1169                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1170                            GEN6_CURBSYTAVG_MASK);
1171                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1172                            GEN6_CURBSYTAVG_MASK);
1173                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1174                            GEN6_CURIAVG_MASK);
1175                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1176                            GEN6_CURBSYTAVG_MASK);
1177                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1178                            GEN6_CURBSYTAVG_MASK);
1179
1180                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1181                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1182                            intel_gpu_freq(dev_priv, max_freq));
1183
1184                 max_freq = (rp_state_cap & 0xff00) >> 8;
1185                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1186                            intel_gpu_freq(dev_priv, max_freq));
1187
1188                 max_freq = rp_state_cap & 0xff;
1189                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1190                            intel_gpu_freq(dev_priv, max_freq));
1191
1192                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1193                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1194         } else if (IS_VALLEYVIEW(dev)) {
1195                 u32 freq_sts;
1196
1197                 mutex_lock(&dev_priv->rps.hw_lock);
1198                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1199                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1200                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1201
1202                 seq_printf(m, "max GPU freq: %d MHz\n",
1203                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1204
1205                 seq_printf(m, "min GPU freq: %d MHz\n",
1206                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1207
1208                 seq_printf(m,
1209                            "efficient (RPe) frequency: %d MHz\n",
1210                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1211
1212                 seq_printf(m, "current GPU freq: %d MHz\n",
1213                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1214                 mutex_unlock(&dev_priv->rps.hw_lock);
1215         } else {
1216                 seq_puts(m, "no P-state info available\n");
1217         }
1218
1219 out:
1220         intel_runtime_pm_put(dev_priv);
1221         return ret;
1222 }
1223
1224 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1225 {
1226         struct drm_info_node *node = m->private;
1227         struct drm_device *dev = node->minor->dev;
1228         struct drm_i915_private *dev_priv = dev->dev_private;
1229         struct intel_engine_cs *ring;
1230         u64 acthd[I915_NUM_RINGS];
1231         u32 seqno[I915_NUM_RINGS];
1232         int i;
1233
1234         if (!i915.enable_hangcheck) {
1235                 seq_printf(m, "Hangcheck disabled\n");
1236                 return 0;
1237         }
1238
1239         intel_runtime_pm_get(dev_priv);
1240
1241         for_each_ring(ring, dev_priv, i) {
1242                 seqno[i] = ring->get_seqno(ring, false);
1243                 acthd[i] = intel_ring_get_active_head(ring);
1244         }
1245
1246         intel_runtime_pm_put(dev_priv);
1247
1248         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1249                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1250                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1251                                             jiffies));
1252         } else
1253                 seq_printf(m, "Hangcheck inactive\n");
1254
1255         for_each_ring(ring, dev_priv, i) {
1256                 seq_printf(m, "%s:\n", ring->name);
1257                 seq_printf(m, "\tseqno = %x [current %x]\n",
1258                            ring->hangcheck.seqno, seqno[i]);
1259                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1260                            (long long)ring->hangcheck.acthd,
1261                            (long long)acthd[i]);
1262                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1263                            (long long)ring->hangcheck.max_acthd);
1264                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1265                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1266         }
1267
1268         return 0;
1269 }
1270
1271 static int ironlake_drpc_info(struct seq_file *m)
1272 {
1273         struct drm_info_node *node = m->private;
1274         struct drm_device *dev = node->minor->dev;
1275         struct drm_i915_private *dev_priv = dev->dev_private;
1276         u32 rgvmodectl, rstdbyctl;
1277         u16 crstandvid;
1278         int ret;
1279
1280         ret = mutex_lock_interruptible(&dev->struct_mutex);
1281         if (ret)
1282                 return ret;
1283         intel_runtime_pm_get(dev_priv);
1284
1285         rgvmodectl = I915_READ(MEMMODECTL);
1286         rstdbyctl = I915_READ(RSTDBYCTL);
1287         crstandvid = I915_READ16(CRSTANDVID);
1288
1289         intel_runtime_pm_put(dev_priv);
1290         mutex_unlock(&dev->struct_mutex);
1291
1292         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1293                    "yes" : "no");
1294         seq_printf(m, "Boost freq: %d\n",
1295                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1296                    MEMMODE_BOOST_FREQ_SHIFT);
1297         seq_printf(m, "HW control enabled: %s\n",
1298                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1299         seq_printf(m, "SW control enabled: %s\n",
1300                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1301         seq_printf(m, "Gated voltage change: %s\n",
1302                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1303         seq_printf(m, "Starting frequency: P%d\n",
1304                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1305         seq_printf(m, "Max P-state: P%d\n",
1306                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1307         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1308         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1309         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1310         seq_printf(m, "Render standby enabled: %s\n",
1311                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1312         seq_puts(m, "Current RS state: ");
1313         switch (rstdbyctl & RSX_STATUS_MASK) {
1314         case RSX_STATUS_ON:
1315                 seq_puts(m, "on\n");
1316                 break;
1317         case RSX_STATUS_RC1:
1318                 seq_puts(m, "RC1\n");
1319                 break;
1320         case RSX_STATUS_RC1E:
1321                 seq_puts(m, "RC1E\n");
1322                 break;
1323         case RSX_STATUS_RS1:
1324                 seq_puts(m, "RS1\n");
1325                 break;
1326         case RSX_STATUS_RS2:
1327                 seq_puts(m, "RS2 (RC6)\n");
1328                 break;
1329         case RSX_STATUS_RS3:
1330                 seq_puts(m, "RC3 (RC6+)\n");
1331                 break;
1332         default:
1333                 seq_puts(m, "unknown\n");
1334                 break;
1335         }
1336
1337         return 0;
1338 }
1339
1340 static int i915_forcewake_domains(struct seq_file *m, void *data)
1341 {
1342         struct drm_info_node *node = m->private;
1343         struct drm_device *dev = node->minor->dev;
1344         struct drm_i915_private *dev_priv = dev->dev_private;
1345         struct intel_uncore_forcewake_domain *fw_domain;
1346         int i;
1347
1348         spin_lock_irq(&dev_priv->uncore.lock);
1349         for_each_fw_domain(fw_domain, dev_priv, i) {
1350                 seq_printf(m, "%s.wake_count = %u\n",
1351                            intel_uncore_forcewake_domain_to_str(i),
1352                            fw_domain->wake_count);
1353         }
1354         spin_unlock_irq(&dev_priv->uncore.lock);
1355
1356         return 0;
1357 }
1358
1359 static int vlv_drpc_info(struct seq_file *m)
1360 {
1361         struct drm_info_node *node = m->private;
1362         struct drm_device *dev = node->minor->dev;
1363         struct drm_i915_private *dev_priv = dev->dev_private;
1364         u32 rpmodectl1, rcctl1, pw_status;
1365
1366         intel_runtime_pm_get(dev_priv);
1367
1368         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1369         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1370         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1371
1372         intel_runtime_pm_put(dev_priv);
1373
1374         seq_printf(m, "Video Turbo Mode: %s\n",
1375                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1376         seq_printf(m, "Turbo enabled: %s\n",
1377                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1378         seq_printf(m, "HW control enabled: %s\n",
1379                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1380         seq_printf(m, "SW control enabled: %s\n",
1381                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1382                           GEN6_RP_MEDIA_SW_MODE));
1383         seq_printf(m, "RC6 Enabled: %s\n",
1384                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1385                                         GEN6_RC_CTL_EI_MODE(1))));
1386         seq_printf(m, "Render Power Well: %s\n",
1387                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1388         seq_printf(m, "Media Power Well: %s\n",
1389                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1390
1391         seq_printf(m, "Render RC6 residency since boot: %u\n",
1392                    I915_READ(VLV_GT_RENDER_RC6));
1393         seq_printf(m, "Media RC6 residency since boot: %u\n",
1394                    I915_READ(VLV_GT_MEDIA_RC6));
1395
1396         return i915_forcewake_domains(m, NULL);
1397 }
1398
1399 static int gen6_drpc_info(struct seq_file *m)
1400 {
1401         struct drm_info_node *node = m->private;
1402         struct drm_device *dev = node->minor->dev;
1403         struct drm_i915_private *dev_priv = dev->dev_private;
1404         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1405         unsigned forcewake_count;
1406         int count = 0, ret;
1407
1408         ret = mutex_lock_interruptible(&dev->struct_mutex);
1409         if (ret)
1410                 return ret;
1411         intel_runtime_pm_get(dev_priv);
1412
1413         spin_lock_irq(&dev_priv->uncore.lock);
1414         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1415         spin_unlock_irq(&dev_priv->uncore.lock);
1416
1417         if (forcewake_count) {
1418                 seq_puts(m, "RC information inaccurate because somebody "
1419                             "holds a forcewake reference \n");
1420         } else {
1421                 /* NB: we cannot use forcewake, else we read the wrong values */
1422                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1423                         udelay(10);
1424                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1425         }
1426
1427         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1428         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1429
1430         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1431         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1432         mutex_unlock(&dev->struct_mutex);
1433         mutex_lock(&dev_priv->rps.hw_lock);
1434         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1435         mutex_unlock(&dev_priv->rps.hw_lock);
1436
1437         intel_runtime_pm_put(dev_priv);
1438
1439         seq_printf(m, "Video Turbo Mode: %s\n",
1440                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1441         seq_printf(m, "HW control enabled: %s\n",
1442                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1443         seq_printf(m, "SW control enabled: %s\n",
1444                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1445                           GEN6_RP_MEDIA_SW_MODE));
1446         seq_printf(m, "RC1e Enabled: %s\n",
1447                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1448         seq_printf(m, "RC6 Enabled: %s\n",
1449                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1450         seq_printf(m, "Deep RC6 Enabled: %s\n",
1451                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1452         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1453                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1454         seq_puts(m, "Current RC state: ");
1455         switch (gt_core_status & GEN6_RCn_MASK) {
1456         case GEN6_RC0:
1457                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1458                         seq_puts(m, "Core Power Down\n");
1459                 else
1460                         seq_puts(m, "on\n");
1461                 break;
1462         case GEN6_RC3:
1463                 seq_puts(m, "RC3\n");
1464                 break;
1465         case GEN6_RC6:
1466                 seq_puts(m, "RC6\n");
1467                 break;
1468         case GEN6_RC7:
1469                 seq_puts(m, "RC7\n");
1470                 break;
1471         default:
1472                 seq_puts(m, "Unknown\n");
1473                 break;
1474         }
1475
1476         seq_printf(m, "Core Power Down: %s\n",
1477                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1478
1479         /* Not exactly sure what this is */
1480         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1481                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1482         seq_printf(m, "RC6 residency since boot: %u\n",
1483                    I915_READ(GEN6_GT_GFX_RC6));
1484         seq_printf(m, "RC6+ residency since boot: %u\n",
1485                    I915_READ(GEN6_GT_GFX_RC6p));
1486         seq_printf(m, "RC6++ residency since boot: %u\n",
1487                    I915_READ(GEN6_GT_GFX_RC6pp));
1488
1489         seq_printf(m, "RC6   voltage: %dmV\n",
1490                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1491         seq_printf(m, "RC6+  voltage: %dmV\n",
1492                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1493         seq_printf(m, "RC6++ voltage: %dmV\n",
1494                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1495         return 0;
1496 }
1497
1498 static int i915_drpc_info(struct seq_file *m, void *unused)
1499 {
1500         struct drm_info_node *node = m->private;
1501         struct drm_device *dev = node->minor->dev;
1502
1503         if (IS_VALLEYVIEW(dev))
1504                 return vlv_drpc_info(m);
1505         else if (INTEL_INFO(dev)->gen >= 6)
1506                 return gen6_drpc_info(m);
1507         else
1508                 return ironlake_drpc_info(m);
1509 }
1510
1511 static int i915_fbc_status(struct seq_file *m, void *unused)
1512 {
1513         struct drm_info_node *node = m->private;
1514         struct drm_device *dev = node->minor->dev;
1515         struct drm_i915_private *dev_priv = dev->dev_private;
1516
1517         if (!HAS_FBC(dev)) {
1518                 seq_puts(m, "FBC unsupported on this chipset\n");
1519                 return 0;
1520         }
1521
1522         intel_runtime_pm_get(dev_priv);
1523
1524         if (intel_fbc_enabled(dev)) {
1525                 seq_puts(m, "FBC enabled\n");
1526         } else {
1527                 seq_puts(m, "FBC disabled: ");
1528                 switch (dev_priv->fbc.no_fbc_reason) {
1529                 case FBC_OK:
1530                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1531                         break;
1532                 case FBC_UNSUPPORTED:
1533                         seq_puts(m, "unsupported by this chipset");
1534                         break;
1535                 case FBC_NO_OUTPUT:
1536                         seq_puts(m, "no outputs");
1537                         break;
1538                 case FBC_STOLEN_TOO_SMALL:
1539                         seq_puts(m, "not enough stolen memory");
1540                         break;
1541                 case FBC_UNSUPPORTED_MODE:
1542                         seq_puts(m, "mode not supported");
1543                         break;
1544                 case FBC_MODE_TOO_LARGE:
1545                         seq_puts(m, "mode too large");
1546                         break;
1547                 case FBC_BAD_PLANE:
1548                         seq_puts(m, "FBC unsupported on plane");
1549                         break;
1550                 case FBC_NOT_TILED:
1551                         seq_puts(m, "scanout buffer not tiled");
1552                         break;
1553                 case FBC_MULTIPLE_PIPES:
1554                         seq_puts(m, "multiple pipes are enabled");
1555                         break;
1556                 case FBC_MODULE_PARAM:
1557                         seq_puts(m, "disabled per module param (default off)");
1558                         break;
1559                 case FBC_CHIP_DEFAULT:
1560                         seq_puts(m, "disabled per chip default");
1561                         break;
1562                 default:
1563                         seq_puts(m, "unknown reason");
1564                 }
1565                 seq_putc(m, '\n');
1566         }
1567
1568         intel_runtime_pm_put(dev_priv);
1569
1570         return 0;
1571 }
1572
1573 static int i915_fbc_fc_get(void *data, u64 *val)
1574 {
1575         struct drm_device *dev = data;
1576         struct drm_i915_private *dev_priv = dev->dev_private;
1577
1578         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1579                 return -ENODEV;
1580
1581         drm_modeset_lock_all(dev);
1582         *val = dev_priv->fbc.false_color;
1583         drm_modeset_unlock_all(dev);
1584
1585         return 0;
1586 }
1587
1588 static int i915_fbc_fc_set(void *data, u64 val)
1589 {
1590         struct drm_device *dev = data;
1591         struct drm_i915_private *dev_priv = dev->dev_private;
1592         u32 reg;
1593
1594         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1595                 return -ENODEV;
1596
1597         drm_modeset_lock_all(dev);
1598
1599         reg = I915_READ(ILK_DPFC_CONTROL);
1600         dev_priv->fbc.false_color = val;
1601
1602         I915_WRITE(ILK_DPFC_CONTROL, val ?
1603                    (reg | FBC_CTL_FALSE_COLOR) :
1604                    (reg & ~FBC_CTL_FALSE_COLOR));
1605
1606         drm_modeset_unlock_all(dev);
1607         return 0;
1608 }
1609
1610 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1611                         i915_fbc_fc_get, i915_fbc_fc_set,
1612                         "%llu\n");
1613
1614 static int i915_ips_status(struct seq_file *m, void *unused)
1615 {
1616         struct drm_info_node *node = m->private;
1617         struct drm_device *dev = node->minor->dev;
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619
1620         if (!HAS_IPS(dev)) {
1621                 seq_puts(m, "not supported\n");
1622                 return 0;
1623         }
1624
1625         intel_runtime_pm_get(dev_priv);
1626
1627         seq_printf(m, "Enabled by kernel parameter: %s\n",
1628                    yesno(i915.enable_ips));
1629
1630         if (INTEL_INFO(dev)->gen >= 8) {
1631                 seq_puts(m, "Currently: unknown\n");
1632         } else {
1633                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1634                         seq_puts(m, "Currently: enabled\n");
1635                 else
1636                         seq_puts(m, "Currently: disabled\n");
1637         }
1638
1639         intel_runtime_pm_put(dev_priv);
1640
1641         return 0;
1642 }
1643
1644 static int i915_sr_status(struct seq_file *m, void *unused)
1645 {
1646         struct drm_info_node *node = m->private;
1647         struct drm_device *dev = node->minor->dev;
1648         struct drm_i915_private *dev_priv = dev->dev_private;
1649         bool sr_enabled = false;
1650
1651         intel_runtime_pm_get(dev_priv);
1652
1653         if (HAS_PCH_SPLIT(dev))
1654                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1655         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1656                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1657         else if (IS_I915GM(dev))
1658                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1659         else if (IS_PINEVIEW(dev))
1660                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1661
1662         intel_runtime_pm_put(dev_priv);
1663
1664         seq_printf(m, "self-refresh: %s\n",
1665                    sr_enabled ? "enabled" : "disabled");
1666
1667         return 0;
1668 }
1669
1670 static int i915_emon_status(struct seq_file *m, void *unused)
1671 {
1672         struct drm_info_node *node = m->private;
1673         struct drm_device *dev = node->minor->dev;
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675         unsigned long temp, chipset, gfx;
1676         int ret;
1677
1678         if (!IS_GEN5(dev))
1679                 return -ENODEV;
1680
1681         ret = mutex_lock_interruptible(&dev->struct_mutex);
1682         if (ret)
1683                 return ret;
1684
1685         temp = i915_mch_val(dev_priv);
1686         chipset = i915_chipset_val(dev_priv);
1687         gfx = i915_gfx_val(dev_priv);
1688         mutex_unlock(&dev->struct_mutex);
1689
1690         seq_printf(m, "GMCH temp: %ld\n", temp);
1691         seq_printf(m, "Chipset power: %ld\n", chipset);
1692         seq_printf(m, "GFX power: %ld\n", gfx);
1693         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1694
1695         return 0;
1696 }
1697
1698 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1699 {
1700         struct drm_info_node *node = m->private;
1701         struct drm_device *dev = node->minor->dev;
1702         struct drm_i915_private *dev_priv = dev->dev_private;
1703         int ret = 0;
1704         int gpu_freq, ia_freq;
1705
1706         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1707                 seq_puts(m, "unsupported on this chipset\n");
1708                 return 0;
1709         }
1710
1711         intel_runtime_pm_get(dev_priv);
1712
1713         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1714
1715         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1716         if (ret)
1717                 goto out;
1718
1719         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1720
1721         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1722              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1723              gpu_freq++) {
1724                 ia_freq = gpu_freq;
1725                 sandybridge_pcode_read(dev_priv,
1726                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1727                                        &ia_freq);
1728                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1729                            intel_gpu_freq(dev_priv, gpu_freq),
1730                            ((ia_freq >> 0) & 0xff) * 100,
1731                            ((ia_freq >> 8) & 0xff) * 100);
1732         }
1733
1734         mutex_unlock(&dev_priv->rps.hw_lock);
1735
1736 out:
1737         intel_runtime_pm_put(dev_priv);
1738         return ret;
1739 }
1740
1741 static int i915_opregion(struct seq_file *m, void *unused)
1742 {
1743         struct drm_info_node *node = m->private;
1744         struct drm_device *dev = node->minor->dev;
1745         struct drm_i915_private *dev_priv = dev->dev_private;
1746         struct intel_opregion *opregion = &dev_priv->opregion;
1747         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1748         int ret;
1749
1750         if (data == NULL)
1751                 return -ENOMEM;
1752
1753         ret = mutex_lock_interruptible(&dev->struct_mutex);
1754         if (ret)
1755                 goto out;
1756
1757         if (opregion->header) {
1758                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1759                 seq_write(m, data, OPREGION_SIZE);
1760         }
1761
1762         mutex_unlock(&dev->struct_mutex);
1763
1764 out:
1765         kfree(data);
1766         return 0;
1767 }
1768
1769 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1770 {
1771         struct drm_info_node *node = m->private;
1772         struct drm_device *dev = node->minor->dev;
1773         struct intel_fbdev *ifbdev = NULL;
1774         struct intel_framebuffer *fb;
1775
1776 #ifdef CONFIG_DRM_I915_FBDEV
1777         struct drm_i915_private *dev_priv = dev->dev_private;
1778
1779         ifbdev = dev_priv->fbdev;
1780         fb = to_intel_framebuffer(ifbdev->helper.fb);
1781
1782         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1783                    fb->base.width,
1784                    fb->base.height,
1785                    fb->base.depth,
1786                    fb->base.bits_per_pixel,
1787                    fb->base.modifier[0],
1788                    atomic_read(&fb->base.refcount.refcount));
1789         describe_obj(m, fb->obj);
1790         seq_putc(m, '\n');
1791 #endif
1792
1793         mutex_lock(&dev->mode_config.fb_lock);
1794         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1795                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1796                         continue;
1797
1798                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1799                            fb->base.width,
1800                            fb->base.height,
1801                            fb->base.depth,
1802                            fb->base.bits_per_pixel,
1803                            fb->base.modifier[0],
1804                            atomic_read(&fb->base.refcount.refcount));
1805                 describe_obj(m, fb->obj);
1806                 seq_putc(m, '\n');
1807         }
1808         mutex_unlock(&dev->mode_config.fb_lock);
1809
1810         return 0;
1811 }
1812
1813 static void describe_ctx_ringbuf(struct seq_file *m,
1814                                  struct intel_ringbuffer *ringbuf)
1815 {
1816         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1817                    ringbuf->space, ringbuf->head, ringbuf->tail,
1818                    ringbuf->last_retired_head);
1819 }
1820
1821 static int i915_context_status(struct seq_file *m, void *unused)
1822 {
1823         struct drm_info_node *node = m->private;
1824         struct drm_device *dev = node->minor->dev;
1825         struct drm_i915_private *dev_priv = dev->dev_private;
1826         struct intel_engine_cs *ring;
1827         struct intel_context *ctx;
1828         int ret, i;
1829
1830         ret = mutex_lock_interruptible(&dev->struct_mutex);
1831         if (ret)
1832                 return ret;
1833
1834         if (dev_priv->ips.pwrctx) {
1835                 seq_puts(m, "power context ");
1836                 describe_obj(m, dev_priv->ips.pwrctx);
1837                 seq_putc(m, '\n');
1838         }
1839
1840         if (dev_priv->ips.renderctx) {
1841                 seq_puts(m, "render context ");
1842                 describe_obj(m, dev_priv->ips.renderctx);
1843                 seq_putc(m, '\n');
1844         }
1845
1846         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1847                 if (!i915.enable_execlists &&
1848                     ctx->legacy_hw_ctx.rcs_state == NULL)
1849                         continue;
1850
1851                 seq_puts(m, "HW context ");
1852                 describe_ctx(m, ctx);
1853                 for_each_ring(ring, dev_priv, i) {
1854                         if (ring->default_context == ctx)
1855                                 seq_printf(m, "(default context %s) ",
1856                                            ring->name);
1857                 }
1858
1859                 if (i915.enable_execlists) {
1860                         seq_putc(m, '\n');
1861                         for_each_ring(ring, dev_priv, i) {
1862                                 struct drm_i915_gem_object *ctx_obj =
1863                                         ctx->engine[i].state;
1864                                 struct intel_ringbuffer *ringbuf =
1865                                         ctx->engine[i].ringbuf;
1866
1867                                 seq_printf(m, "%s: ", ring->name);
1868                                 if (ctx_obj)
1869                                         describe_obj(m, ctx_obj);
1870                                 if (ringbuf)
1871                                         describe_ctx_ringbuf(m, ringbuf);
1872                                 seq_putc(m, '\n');
1873                         }
1874                 } else {
1875                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1876                 }
1877
1878                 seq_putc(m, '\n');
1879         }
1880
1881         mutex_unlock(&dev->struct_mutex);
1882
1883         return 0;
1884 }
1885
1886 static void i915_dump_lrc_obj(struct seq_file *m,
1887                               struct intel_engine_cs *ring,
1888                               struct drm_i915_gem_object *ctx_obj)
1889 {
1890         struct page *page;
1891         uint32_t *reg_state;
1892         int j;
1893         unsigned long ggtt_offset = 0;
1894
1895         if (ctx_obj == NULL) {
1896                 seq_printf(m, "Context on %s with no gem object\n",
1897                            ring->name);
1898                 return;
1899         }
1900
1901         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1902                    intel_execlists_ctx_id(ctx_obj));
1903
1904         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1905                 seq_puts(m, "\tNot bound in GGTT\n");
1906         else
1907                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1908
1909         if (i915_gem_object_get_pages(ctx_obj)) {
1910                 seq_puts(m, "\tFailed to get pages for context object\n");
1911                 return;
1912         }
1913
1914         page = i915_gem_object_get_page(ctx_obj, 1);
1915         if (!WARN_ON(page == NULL)) {
1916                 reg_state = kmap_atomic(page);
1917
1918                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1919                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1920                                    ggtt_offset + 4096 + (j * 4),
1921                                    reg_state[j], reg_state[j + 1],
1922                                    reg_state[j + 2], reg_state[j + 3]);
1923                 }
1924                 kunmap_atomic(reg_state);
1925         }
1926
1927         seq_putc(m, '\n');
1928 }
1929
1930 static int i915_dump_lrc(struct seq_file *m, void *unused)
1931 {
1932         struct drm_info_node *node = (struct drm_info_node *) m->private;
1933         struct drm_device *dev = node->minor->dev;
1934         struct drm_i915_private *dev_priv = dev->dev_private;
1935         struct intel_engine_cs *ring;
1936         struct intel_context *ctx;
1937         int ret, i;
1938
1939         if (!i915.enable_execlists) {
1940                 seq_printf(m, "Logical Ring Contexts are disabled\n");
1941                 return 0;
1942         }
1943
1944         ret = mutex_lock_interruptible(&dev->struct_mutex);
1945         if (ret)
1946                 return ret;
1947
1948         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1949                 for_each_ring(ring, dev_priv, i) {
1950                         if (ring->default_context != ctx)
1951                                 i915_dump_lrc_obj(m, ring,
1952                                                   ctx->engine[i].state);
1953                 }
1954         }
1955
1956         mutex_unlock(&dev->struct_mutex);
1957
1958         return 0;
1959 }
1960
1961 static int i915_execlists(struct seq_file *m, void *data)
1962 {
1963         struct drm_info_node *node = (struct drm_info_node *)m->private;
1964         struct drm_device *dev = node->minor->dev;
1965         struct drm_i915_private *dev_priv = dev->dev_private;
1966         struct intel_engine_cs *ring;
1967         u32 status_pointer;
1968         u8 read_pointer;
1969         u8 write_pointer;
1970         u32 status;
1971         u32 ctx_id;
1972         struct list_head *cursor;
1973         int ring_id, i;
1974         int ret;
1975
1976         if (!i915.enable_execlists) {
1977                 seq_puts(m, "Logical Ring Contexts are disabled\n");
1978                 return 0;
1979         }
1980
1981         ret = mutex_lock_interruptible(&dev->struct_mutex);
1982         if (ret)
1983                 return ret;
1984
1985         intel_runtime_pm_get(dev_priv);
1986
1987         for_each_ring(ring, dev_priv, ring_id) {
1988                 struct drm_i915_gem_request *head_req = NULL;
1989                 int count = 0;
1990                 unsigned long flags;
1991
1992                 seq_printf(m, "%s\n", ring->name);
1993
1994                 status = I915_READ(RING_EXECLIST_STATUS(ring));
1995                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1996                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1997                            status, ctx_id);
1998
1999                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2000                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2001
2002                 read_pointer = ring->next_context_status_buffer;
2003                 write_pointer = status_pointer & 0x07;
2004                 if (read_pointer > write_pointer)
2005                         write_pointer += 6;
2006                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2007                            read_pointer, write_pointer);
2008
2009                 for (i = 0; i < 6; i++) {
2010                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2011                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2012
2013                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2014                                    i, status, ctx_id);
2015                 }
2016
2017                 spin_lock_irqsave(&ring->execlist_lock, flags);
2018                 list_for_each(cursor, &ring->execlist_queue)
2019                         count++;
2020                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2021                                 struct drm_i915_gem_request, execlist_link);
2022                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2023
2024                 seq_printf(m, "\t%d requests in queue\n", count);
2025                 if (head_req) {
2026                         struct drm_i915_gem_object *ctx_obj;
2027
2028                         ctx_obj = head_req->ctx->engine[ring_id].state;
2029                         seq_printf(m, "\tHead request id: %u\n",
2030                                    intel_execlists_ctx_id(ctx_obj));
2031                         seq_printf(m, "\tHead request tail: %u\n",
2032                                    head_req->tail);
2033                 }
2034
2035                 seq_putc(m, '\n');
2036         }
2037
2038         intel_runtime_pm_put(dev_priv);
2039         mutex_unlock(&dev->struct_mutex);
2040
2041         return 0;
2042 }
2043
2044 static const char *swizzle_string(unsigned swizzle)
2045 {
2046         switch (swizzle) {
2047         case I915_BIT_6_SWIZZLE_NONE:
2048                 return "none";
2049         case I915_BIT_6_SWIZZLE_9:
2050                 return "bit9";
2051         case I915_BIT_6_SWIZZLE_9_10:
2052                 return "bit9/bit10";
2053         case I915_BIT_6_SWIZZLE_9_11:
2054                 return "bit9/bit11";
2055         case I915_BIT_6_SWIZZLE_9_10_11:
2056                 return "bit9/bit10/bit11";
2057         case I915_BIT_6_SWIZZLE_9_17:
2058                 return "bit9/bit17";
2059         case I915_BIT_6_SWIZZLE_9_10_17:
2060                 return "bit9/bit10/bit17";
2061         case I915_BIT_6_SWIZZLE_UNKNOWN:
2062                 return "unknown";
2063         }
2064
2065         return "bug";
2066 }
2067
2068 static int i915_swizzle_info(struct seq_file *m, void *data)
2069 {
2070         struct drm_info_node *node = m->private;
2071         struct drm_device *dev = node->minor->dev;
2072         struct drm_i915_private *dev_priv = dev->dev_private;
2073         int ret;
2074
2075         ret = mutex_lock_interruptible(&dev->struct_mutex);
2076         if (ret)
2077                 return ret;
2078         intel_runtime_pm_get(dev_priv);
2079
2080         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2081                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2082         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2083                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2084
2085         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2086                 seq_printf(m, "DDC = 0x%08x\n",
2087                            I915_READ(DCC));
2088                 seq_printf(m, "DDC2 = 0x%08x\n",
2089                            I915_READ(DCC2));
2090                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2091                            I915_READ16(C0DRB3));
2092                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2093                            I915_READ16(C1DRB3));
2094         } else if (INTEL_INFO(dev)->gen >= 6) {
2095                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2096                            I915_READ(MAD_DIMM_C0));
2097                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2098                            I915_READ(MAD_DIMM_C1));
2099                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2100                            I915_READ(MAD_DIMM_C2));
2101                 seq_printf(m, "TILECTL = 0x%08x\n",
2102                            I915_READ(TILECTL));
2103                 if (INTEL_INFO(dev)->gen >= 8)
2104                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2105                                    I915_READ(GAMTARBMODE));
2106                 else
2107                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2108                                    I915_READ(ARB_MODE));
2109                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2110                            I915_READ(DISP_ARB_CTL));
2111         }
2112
2113         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2114                 seq_puts(m, "L-shaped memory detected\n");
2115
2116         intel_runtime_pm_put(dev_priv);
2117         mutex_unlock(&dev->struct_mutex);
2118
2119         return 0;
2120 }
2121
2122 static int per_file_ctx(int id, void *ptr, void *data)
2123 {
2124         struct intel_context *ctx = ptr;
2125         struct seq_file *m = data;
2126         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2127
2128         if (!ppgtt) {
2129                 seq_printf(m, "  no ppgtt for context %d\n",
2130                            ctx->user_handle);
2131                 return 0;
2132         }
2133
2134         if (i915_gem_context_is_default(ctx))
2135                 seq_puts(m, "  default context:\n");
2136         else
2137                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2138         ppgtt->debug_dump(ppgtt, m);
2139
2140         return 0;
2141 }
2142
2143 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2144 {
2145         struct drm_i915_private *dev_priv = dev->dev_private;
2146         struct intel_engine_cs *ring;
2147         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2148         int unused, i;
2149
2150         if (!ppgtt)
2151                 return;
2152
2153         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2154         seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2155         for_each_ring(ring, dev_priv, unused) {
2156                 seq_printf(m, "%s\n", ring->name);
2157                 for (i = 0; i < 4; i++) {
2158                         u32 offset = 0x270 + i * 8;
2159                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2160                         pdp <<= 32;
2161                         pdp |= I915_READ(ring->mmio_base + offset);
2162                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2163                 }
2164         }
2165 }
2166
2167 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2168 {
2169         struct drm_i915_private *dev_priv = dev->dev_private;
2170         struct intel_engine_cs *ring;
2171         struct drm_file *file;
2172         int i;
2173
2174         if (INTEL_INFO(dev)->gen == 6)
2175                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2176
2177         for_each_ring(ring, dev_priv, i) {
2178                 seq_printf(m, "%s\n", ring->name);
2179                 if (INTEL_INFO(dev)->gen == 7)
2180                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2181                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2182                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2183                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2184         }
2185         if (dev_priv->mm.aliasing_ppgtt) {
2186                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2187
2188                 seq_puts(m, "aliasing PPGTT:\n");
2189                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
2190
2191                 ppgtt->debug_dump(ppgtt, m);
2192         }
2193
2194         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2195                 struct drm_i915_file_private *file_priv = file->driver_priv;
2196
2197                 seq_printf(m, "proc: %s\n",
2198                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2199                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2200         }
2201         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2202 }
2203
2204 static int i915_ppgtt_info(struct seq_file *m, void *data)
2205 {
2206         struct drm_info_node *node = m->private;
2207         struct drm_device *dev = node->minor->dev;
2208         struct drm_i915_private *dev_priv = dev->dev_private;
2209
2210         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2211         if (ret)
2212                 return ret;
2213         intel_runtime_pm_get(dev_priv);
2214
2215         if (INTEL_INFO(dev)->gen >= 8)
2216                 gen8_ppgtt_info(m, dev);
2217         else if (INTEL_INFO(dev)->gen >= 6)
2218                 gen6_ppgtt_info(m, dev);
2219
2220         intel_runtime_pm_put(dev_priv);
2221         mutex_unlock(&dev->struct_mutex);
2222
2223         return 0;
2224 }
2225
2226 static int i915_llc(struct seq_file *m, void *data)
2227 {
2228         struct drm_info_node *node = m->private;
2229         struct drm_device *dev = node->minor->dev;
2230         struct drm_i915_private *dev_priv = dev->dev_private;
2231
2232         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2233         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2234         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2235
2236         return 0;
2237 }
2238
2239 static int i915_edp_psr_status(struct seq_file *m, void *data)
2240 {
2241         struct drm_info_node *node = m->private;
2242         struct drm_device *dev = node->minor->dev;
2243         struct drm_i915_private *dev_priv = dev->dev_private;
2244         u32 psrperf = 0;
2245         u32 stat[3];
2246         enum pipe pipe;
2247         bool enabled = false;
2248
2249         intel_runtime_pm_get(dev_priv);
2250
2251         mutex_lock(&dev_priv->psr.lock);
2252         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2253         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2254         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2255         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2256         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2257                    dev_priv->psr.busy_frontbuffer_bits);
2258         seq_printf(m, "Re-enable work scheduled: %s\n",
2259                    yesno(work_busy(&dev_priv->psr.work.work)));
2260
2261         if (HAS_PSR(dev)) {
2262                 if (HAS_DDI(dev))
2263                         enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2264                 else {
2265                         for_each_pipe(dev_priv, pipe) {
2266                                 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2267                                         VLV_EDP_PSR_CURR_STATE_MASK;
2268                                 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2269                                     (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2270                                         enabled = true;
2271                         }
2272                 }
2273         }
2274         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2275
2276         if (!HAS_DDI(dev))
2277                 for_each_pipe(dev_priv, pipe) {
2278                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2279                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2280                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2281                 }
2282         seq_puts(m, "\n");
2283
2284         seq_printf(m, "Link standby: %s\n",
2285                    yesno((bool)dev_priv->psr.link_standby));
2286
2287         /* CHV PSR has no kind of performance counter */
2288         if (HAS_PSR(dev) && HAS_DDI(dev)) {
2289                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2290                         EDP_PSR_PERF_CNT_MASK;
2291
2292                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2293         }
2294         mutex_unlock(&dev_priv->psr.lock);
2295
2296         intel_runtime_pm_put(dev_priv);
2297         return 0;
2298 }
2299
2300 static int i915_sink_crc(struct seq_file *m, void *data)
2301 {
2302         struct drm_info_node *node = m->private;
2303         struct drm_device *dev = node->minor->dev;
2304         struct intel_encoder *encoder;
2305         struct intel_connector *connector;
2306         struct intel_dp *intel_dp = NULL;
2307         int ret;
2308         u8 crc[6];
2309
2310         drm_modeset_lock_all(dev);
2311         list_for_each_entry(connector, &dev->mode_config.connector_list,
2312                             base.head) {
2313
2314                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2315                         continue;
2316
2317                 if (!connector->base.encoder)
2318                         continue;
2319
2320                 encoder = to_intel_encoder(connector->base.encoder);
2321                 if (encoder->type != INTEL_OUTPUT_EDP)
2322                         continue;
2323
2324                 intel_dp = enc_to_intel_dp(&encoder->base);
2325
2326                 ret = intel_dp_sink_crc(intel_dp, crc);
2327                 if (ret)
2328                         goto out;
2329
2330                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2331                            crc[0], crc[1], crc[2],
2332                            crc[3], crc[4], crc[5]);
2333                 goto out;
2334         }
2335         ret = -ENODEV;
2336 out:
2337         drm_modeset_unlock_all(dev);
2338         return ret;
2339 }
2340
2341 static int i915_energy_uJ(struct seq_file *m, void *data)
2342 {
2343         struct drm_info_node *node = m->private;
2344         struct drm_device *dev = node->minor->dev;
2345         struct drm_i915_private *dev_priv = dev->dev_private;
2346         u64 power;
2347         u32 units;
2348
2349         if (INTEL_INFO(dev)->gen < 6)
2350                 return -ENODEV;
2351
2352         intel_runtime_pm_get(dev_priv);
2353
2354         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2355         power = (power & 0x1f00) >> 8;
2356         units = 1000000 / (1 << power); /* convert to uJ */
2357         power = I915_READ(MCH_SECP_NRG_STTS);
2358         power *= units;
2359
2360         intel_runtime_pm_put(dev_priv);
2361
2362         seq_printf(m, "%llu", (long long unsigned)power);
2363
2364         return 0;
2365 }
2366
2367 static int i915_pc8_status(struct seq_file *m, void *unused)
2368 {
2369         struct drm_info_node *node = m->private;
2370         struct drm_device *dev = node->minor->dev;
2371         struct drm_i915_private *dev_priv = dev->dev_private;
2372
2373         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2374                 seq_puts(m, "not supported\n");
2375                 return 0;
2376         }
2377
2378         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2379         seq_printf(m, "IRQs disabled: %s\n",
2380                    yesno(!intel_irqs_enabled(dev_priv)));
2381
2382         return 0;
2383 }
2384
2385 static const char *power_domain_str(enum intel_display_power_domain domain)
2386 {
2387         switch (domain) {
2388         case POWER_DOMAIN_PIPE_A:
2389                 return "PIPE_A";
2390         case POWER_DOMAIN_PIPE_B:
2391                 return "PIPE_B";
2392         case POWER_DOMAIN_PIPE_C:
2393                 return "PIPE_C";
2394         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2395                 return "PIPE_A_PANEL_FITTER";
2396         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2397                 return "PIPE_B_PANEL_FITTER";
2398         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2399                 return "PIPE_C_PANEL_FITTER";
2400         case POWER_DOMAIN_TRANSCODER_A:
2401                 return "TRANSCODER_A";
2402         case POWER_DOMAIN_TRANSCODER_B:
2403                 return "TRANSCODER_B";
2404         case POWER_DOMAIN_TRANSCODER_C:
2405                 return "TRANSCODER_C";
2406         case POWER_DOMAIN_TRANSCODER_EDP:
2407                 return "TRANSCODER_EDP";
2408         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2409                 return "PORT_DDI_A_2_LANES";
2410         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2411                 return "PORT_DDI_A_4_LANES";
2412         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2413                 return "PORT_DDI_B_2_LANES";
2414         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2415                 return "PORT_DDI_B_4_LANES";
2416         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2417                 return "PORT_DDI_C_2_LANES";
2418         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2419                 return "PORT_DDI_C_4_LANES";
2420         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2421                 return "PORT_DDI_D_2_LANES";
2422         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2423                 return "PORT_DDI_D_4_LANES";
2424         case POWER_DOMAIN_PORT_DSI:
2425                 return "PORT_DSI";
2426         case POWER_DOMAIN_PORT_CRT:
2427                 return "PORT_CRT";
2428         case POWER_DOMAIN_PORT_OTHER:
2429                 return "PORT_OTHER";
2430         case POWER_DOMAIN_VGA:
2431                 return "VGA";
2432         case POWER_DOMAIN_AUDIO:
2433                 return "AUDIO";
2434         case POWER_DOMAIN_PLLS:
2435                 return "PLLS";
2436         case POWER_DOMAIN_AUX_A:
2437                 return "AUX_A";
2438         case POWER_DOMAIN_AUX_B:
2439                 return "AUX_B";
2440         case POWER_DOMAIN_AUX_C:
2441                 return "AUX_C";
2442         case POWER_DOMAIN_AUX_D:
2443                 return "AUX_D";
2444         case POWER_DOMAIN_INIT:
2445                 return "INIT";
2446         default:
2447                 MISSING_CASE(domain);
2448                 return "?";
2449         }
2450 }
2451
2452 static int i915_power_domain_info(struct seq_file *m, void *unused)
2453 {
2454         struct drm_info_node *node = m->private;
2455         struct drm_device *dev = node->minor->dev;
2456         struct drm_i915_private *dev_priv = dev->dev_private;
2457         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2458         int i;
2459
2460         mutex_lock(&power_domains->lock);
2461
2462         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2463         for (i = 0; i < power_domains->power_well_count; i++) {
2464                 struct i915_power_well *power_well;
2465                 enum intel_display_power_domain power_domain;
2466
2467                 power_well = &power_domains->power_wells[i];
2468                 seq_printf(m, "%-25s %d\n", power_well->name,
2469                            power_well->count);
2470
2471                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2472                      power_domain++) {
2473                         if (!(BIT(power_domain) & power_well->domains))
2474                                 continue;
2475
2476                         seq_printf(m, "  %-23s %d\n",
2477                                  power_domain_str(power_domain),
2478                                  power_domains->domain_use_count[power_domain]);
2479                 }
2480         }
2481
2482         mutex_unlock(&power_domains->lock);
2483
2484         return 0;
2485 }
2486
2487 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2488                                  struct drm_display_mode *mode)
2489 {
2490         int i;
2491
2492         for (i = 0; i < tabs; i++)
2493                 seq_putc(m, '\t');
2494
2495         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2496                    mode->base.id, mode->name,
2497                    mode->vrefresh, mode->clock,
2498                    mode->hdisplay, mode->hsync_start,
2499                    mode->hsync_end, mode->htotal,
2500                    mode->vdisplay, mode->vsync_start,
2501                    mode->vsync_end, mode->vtotal,
2502                    mode->type, mode->flags);
2503 }
2504
2505 static void intel_encoder_info(struct seq_file *m,
2506                                struct intel_crtc *intel_crtc,
2507                                struct intel_encoder *intel_encoder)
2508 {
2509         struct drm_info_node *node = m->private;
2510         struct drm_device *dev = node->minor->dev;
2511         struct drm_crtc *crtc = &intel_crtc->base;
2512         struct intel_connector *intel_connector;
2513         struct drm_encoder *encoder;
2514
2515         encoder = &intel_encoder->base;
2516         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2517                    encoder->base.id, encoder->name);
2518         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2519                 struct drm_connector *connector = &intel_connector->base;
2520                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2521                            connector->base.id,
2522                            connector->name,
2523                            drm_get_connector_status_name(connector->status));
2524                 if (connector->status == connector_status_connected) {
2525                         struct drm_display_mode *mode = &crtc->mode;
2526                         seq_printf(m, ", mode:\n");
2527                         intel_seq_print_mode(m, 2, mode);
2528                 } else {
2529                         seq_putc(m, '\n');
2530                 }
2531         }
2532 }
2533
2534 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2535 {
2536         struct drm_info_node *node = m->private;
2537         struct drm_device *dev = node->minor->dev;
2538         struct drm_crtc *crtc = &intel_crtc->base;
2539         struct intel_encoder *intel_encoder;
2540
2541         if (crtc->primary->fb)
2542                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2543                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2544                            crtc->primary->fb->width, crtc->primary->fb->height);
2545         else
2546                 seq_puts(m, "\tprimary plane disabled\n");
2547         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2548                 intel_encoder_info(m, intel_crtc, intel_encoder);
2549 }
2550
2551 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2552 {
2553         struct drm_display_mode *mode = panel->fixed_mode;
2554
2555         seq_printf(m, "\tfixed mode:\n");
2556         intel_seq_print_mode(m, 2, mode);
2557 }
2558
2559 static void intel_dp_info(struct seq_file *m,
2560                           struct intel_connector *intel_connector)
2561 {
2562         struct intel_encoder *intel_encoder = intel_connector->encoder;
2563         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2564
2565         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2566         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2567                    "no");
2568         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2569                 intel_panel_info(m, &intel_connector->panel);
2570 }
2571
2572 static void intel_hdmi_info(struct seq_file *m,
2573                             struct intel_connector *intel_connector)
2574 {
2575         struct intel_encoder *intel_encoder = intel_connector->encoder;
2576         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2577
2578         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2579                    "no");
2580 }
2581
2582 static void intel_lvds_info(struct seq_file *m,
2583                             struct intel_connector *intel_connector)
2584 {
2585         intel_panel_info(m, &intel_connector->panel);
2586 }
2587
2588 static void intel_connector_info(struct seq_file *m,
2589                                  struct drm_connector *connector)
2590 {
2591         struct intel_connector *intel_connector = to_intel_connector(connector);
2592         struct intel_encoder *intel_encoder = intel_connector->encoder;
2593         struct drm_display_mode *mode;
2594
2595         seq_printf(m, "connector %d: type %s, status: %s\n",
2596                    connector->base.id, connector->name,
2597                    drm_get_connector_status_name(connector->status));
2598         if (connector->status == connector_status_connected) {
2599                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2600                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2601                            connector->display_info.width_mm,
2602                            connector->display_info.height_mm);
2603                 seq_printf(m, "\tsubpixel order: %s\n",
2604                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2605                 seq_printf(m, "\tCEA rev: %d\n",
2606                            connector->display_info.cea_rev);
2607         }
2608         if (intel_encoder) {
2609                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2610                     intel_encoder->type == INTEL_OUTPUT_EDP)
2611                         intel_dp_info(m, intel_connector);
2612                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2613                         intel_hdmi_info(m, intel_connector);
2614                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2615                         intel_lvds_info(m, intel_connector);
2616         }
2617
2618         seq_printf(m, "\tmodes:\n");
2619         list_for_each_entry(mode, &connector->modes, head)
2620                 intel_seq_print_mode(m, 2, mode);
2621 }
2622
2623 static bool cursor_active(struct drm_device *dev, int pipe)
2624 {
2625         struct drm_i915_private *dev_priv = dev->dev_private;
2626         u32 state;
2627
2628         if (IS_845G(dev) || IS_I865G(dev))
2629                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2630         else
2631                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2632
2633         return state;
2634 }
2635
2636 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2637 {
2638         struct drm_i915_private *dev_priv = dev->dev_private;
2639         u32 pos;
2640
2641         pos = I915_READ(CURPOS(pipe));
2642
2643         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2644         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2645                 *x = -*x;
2646
2647         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2648         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2649                 *y = -*y;
2650
2651         return cursor_active(dev, pipe);
2652 }
2653
2654 static int i915_display_info(struct seq_file *m, void *unused)
2655 {
2656         struct drm_info_node *node = m->private;
2657         struct drm_device *dev = node->minor->dev;
2658         struct drm_i915_private *dev_priv = dev->dev_private;
2659         struct intel_crtc *crtc;
2660         struct drm_connector *connector;
2661
2662         intel_runtime_pm_get(dev_priv);
2663         drm_modeset_lock_all(dev);
2664         seq_printf(m, "CRTC info\n");
2665         seq_printf(m, "---------\n");
2666         for_each_intel_crtc(dev, crtc) {
2667                 bool active;
2668                 int x, y;
2669
2670                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2671                            crtc->base.base.id, pipe_name(crtc->pipe),
2672                            yesno(crtc->active), crtc->config->pipe_src_w,
2673                            crtc->config->pipe_src_h);
2674                 if (crtc->active) {
2675                         intel_crtc_info(m, crtc);
2676
2677                         active = cursor_position(dev, crtc->pipe, &x, &y);
2678                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2679                                    yesno(crtc->cursor_base),
2680                                    x, y, crtc->cursor_width, crtc->cursor_height,
2681                                    crtc->cursor_addr, yesno(active));
2682                 }
2683
2684                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2685                            yesno(!crtc->cpu_fifo_underrun_disabled),
2686                            yesno(!crtc->pch_fifo_underrun_disabled));
2687         }
2688
2689         seq_printf(m, "\n");
2690         seq_printf(m, "Connector info\n");
2691         seq_printf(m, "--------------\n");
2692         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2693                 intel_connector_info(m, connector);
2694         }
2695         drm_modeset_unlock_all(dev);
2696         intel_runtime_pm_put(dev_priv);
2697
2698         return 0;
2699 }
2700
2701 static int i915_semaphore_status(struct seq_file *m, void *unused)
2702 {
2703         struct drm_info_node *node = (struct drm_info_node *) m->private;
2704         struct drm_device *dev = node->minor->dev;
2705         struct drm_i915_private *dev_priv = dev->dev_private;
2706         struct intel_engine_cs *ring;
2707         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2708         int i, j, ret;
2709
2710         if (!i915_semaphore_is_enabled(dev)) {
2711                 seq_puts(m, "Semaphores are disabled\n");
2712                 return 0;
2713         }
2714
2715         ret = mutex_lock_interruptible(&dev->struct_mutex);
2716         if (ret)
2717                 return ret;
2718         intel_runtime_pm_get(dev_priv);
2719
2720         if (IS_BROADWELL(dev)) {
2721                 struct page *page;
2722                 uint64_t *seqno;
2723
2724                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2725
2726                 seqno = (uint64_t *)kmap_atomic(page);
2727                 for_each_ring(ring, dev_priv, i) {
2728                         uint64_t offset;
2729
2730                         seq_printf(m, "%s\n", ring->name);
2731
2732                         seq_puts(m, "  Last signal:");
2733                         for (j = 0; j < num_rings; j++) {
2734                                 offset = i * I915_NUM_RINGS + j;
2735                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2736                                            seqno[offset], offset * 8);
2737                         }
2738                         seq_putc(m, '\n');
2739
2740                         seq_puts(m, "  Last wait:  ");
2741                         for (j = 0; j < num_rings; j++) {
2742                                 offset = i + (j * I915_NUM_RINGS);
2743                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2744                                            seqno[offset], offset * 8);
2745                         }
2746                         seq_putc(m, '\n');
2747
2748                 }
2749                 kunmap_atomic(seqno);
2750         } else {
2751                 seq_puts(m, "  Last signal:");
2752                 for_each_ring(ring, dev_priv, i)
2753                         for (j = 0; j < num_rings; j++)
2754                                 seq_printf(m, "0x%08x\n",
2755                                            I915_READ(ring->semaphore.mbox.signal[j]));
2756                 seq_putc(m, '\n');
2757         }
2758
2759         seq_puts(m, "\nSync seqno:\n");
2760         for_each_ring(ring, dev_priv, i) {
2761                 for (j = 0; j < num_rings; j++) {
2762                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2763                 }
2764                 seq_putc(m, '\n');
2765         }
2766         seq_putc(m, '\n');
2767
2768         intel_runtime_pm_put(dev_priv);
2769         mutex_unlock(&dev->struct_mutex);
2770         return 0;
2771 }
2772
2773 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2774 {
2775         struct drm_info_node *node = (struct drm_info_node *) m->private;
2776         struct drm_device *dev = node->minor->dev;
2777         struct drm_i915_private *dev_priv = dev->dev_private;
2778         int i;
2779
2780         drm_modeset_lock_all(dev);
2781         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2782                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2783
2784                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2785                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2786                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2787                 seq_printf(m, " tracked hardware state:\n");
2788                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2789                 seq_printf(m, " dpll_md: 0x%08x\n",
2790                            pll->config.hw_state.dpll_md);
2791                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2792                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2793                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2794         }
2795         drm_modeset_unlock_all(dev);
2796
2797         return 0;
2798 }
2799
2800 static int i915_wa_registers(struct seq_file *m, void *unused)
2801 {
2802         int i;
2803         int ret;
2804         struct drm_info_node *node = (struct drm_info_node *) m->private;
2805         struct drm_device *dev = node->minor->dev;
2806         struct drm_i915_private *dev_priv = dev->dev_private;
2807
2808         ret = mutex_lock_interruptible(&dev->struct_mutex);
2809         if (ret)
2810                 return ret;
2811
2812         intel_runtime_pm_get(dev_priv);
2813
2814         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2815         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2816                 u32 addr, mask, value, read;
2817                 bool ok;
2818
2819                 addr = dev_priv->workarounds.reg[i].addr;
2820                 mask = dev_priv->workarounds.reg[i].mask;
2821                 value = dev_priv->workarounds.reg[i].value;
2822                 read = I915_READ(addr);
2823                 ok = (value & mask) == (read & mask);
2824                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2825                            addr, value, mask, read, ok ? "OK" : "FAIL");
2826         }
2827
2828         intel_runtime_pm_put(dev_priv);
2829         mutex_unlock(&dev->struct_mutex);
2830
2831         return 0;
2832 }
2833
2834 static int i915_ddb_info(struct seq_file *m, void *unused)
2835 {
2836         struct drm_info_node *node = m->private;
2837         struct drm_device *dev = node->minor->dev;
2838         struct drm_i915_private *dev_priv = dev->dev_private;
2839         struct skl_ddb_allocation *ddb;
2840         struct skl_ddb_entry *entry;
2841         enum pipe pipe;
2842         int plane;
2843
2844         if (INTEL_INFO(dev)->gen < 9)
2845                 return 0;
2846
2847         drm_modeset_lock_all(dev);
2848
2849         ddb = &dev_priv->wm.skl_hw.ddb;
2850
2851         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2852
2853         for_each_pipe(dev_priv, pipe) {
2854                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2855
2856                 for_each_plane(pipe, plane) {
2857                         entry = &ddb->plane[pipe][plane];
2858                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2859                                    entry->start, entry->end,
2860                                    skl_ddb_entry_size(entry));
2861                 }
2862
2863                 entry = &ddb->cursor[pipe];
2864                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
2865                            entry->end, skl_ddb_entry_size(entry));
2866         }
2867
2868         drm_modeset_unlock_all(dev);
2869
2870         return 0;
2871 }
2872
2873 struct pipe_crc_info {
2874         const char *name;
2875         struct drm_device *dev;
2876         enum pipe pipe;
2877 };
2878
2879 static int i915_dp_mst_info(struct seq_file *m, void *unused)
2880 {
2881         struct drm_info_node *node = (struct drm_info_node *) m->private;
2882         struct drm_device *dev = node->minor->dev;
2883         struct drm_encoder *encoder;
2884         struct intel_encoder *intel_encoder;
2885         struct intel_digital_port *intel_dig_port;
2886         drm_modeset_lock_all(dev);
2887         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2888                 intel_encoder = to_intel_encoder(encoder);
2889                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2890                         continue;
2891                 intel_dig_port = enc_to_dig_port(encoder);
2892                 if (!intel_dig_port->dp.can_mst)
2893                         continue;
2894
2895                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2896         }
2897         drm_modeset_unlock_all(dev);
2898         return 0;
2899 }
2900
2901 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2902 {
2903         struct pipe_crc_info *info = inode->i_private;
2904         struct drm_i915_private *dev_priv = info->dev->dev_private;
2905         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2906
2907         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2908                 return -ENODEV;
2909
2910         spin_lock_irq(&pipe_crc->lock);
2911
2912         if (pipe_crc->opened) {
2913                 spin_unlock_irq(&pipe_crc->lock);
2914                 return -EBUSY; /* already open */
2915         }
2916
2917         pipe_crc->opened = true;
2918         filep->private_data = inode->i_private;
2919
2920         spin_unlock_irq(&pipe_crc->lock);
2921
2922         return 0;
2923 }
2924
2925 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2926 {
2927         struct pipe_crc_info *info = inode->i_private;
2928         struct drm_i915_private *dev_priv = info->dev->dev_private;
2929         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2930
2931         spin_lock_irq(&pipe_crc->lock);
2932         pipe_crc->opened = false;
2933         spin_unlock_irq(&pipe_crc->lock);
2934
2935         return 0;
2936 }
2937
2938 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2939 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2940 /* account for \'0' */
2941 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2942
2943 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2944 {
2945         assert_spin_locked(&pipe_crc->lock);
2946         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2947                         INTEL_PIPE_CRC_ENTRIES_NR);
2948 }
2949
2950 static ssize_t
2951 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2952                    loff_t *pos)
2953 {
2954         struct pipe_crc_info *info = filep->private_data;
2955         struct drm_device *dev = info->dev;
2956         struct drm_i915_private *dev_priv = dev->dev_private;
2957         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2958         char buf[PIPE_CRC_BUFFER_LEN];
2959         int n_entries;
2960         ssize_t bytes_read;
2961
2962         /*
2963          * Don't allow user space to provide buffers not big enough to hold
2964          * a line of data.
2965          */
2966         if (count < PIPE_CRC_LINE_LEN)
2967                 return -EINVAL;
2968
2969         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2970                 return 0;
2971
2972         /* nothing to read */
2973         spin_lock_irq(&pipe_crc->lock);
2974         while (pipe_crc_data_count(pipe_crc) == 0) {
2975                 int ret;
2976
2977                 if (filep->f_flags & O_NONBLOCK) {
2978                         spin_unlock_irq(&pipe_crc->lock);
2979                         return -EAGAIN;
2980                 }
2981
2982                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2983                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2984                 if (ret) {
2985                         spin_unlock_irq(&pipe_crc->lock);
2986                         return ret;
2987                 }
2988         }
2989
2990         /* We now have one or more entries to read */
2991         n_entries = count / PIPE_CRC_LINE_LEN;
2992
2993         bytes_read = 0;
2994         while (n_entries > 0) {
2995                 struct intel_pipe_crc_entry *entry =
2996                         &pipe_crc->entries[pipe_crc->tail];
2997                 int ret;
2998
2999                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3000                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3001                         break;
3002
3003                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3004                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3005
3006                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3007                                        "%8u %8x %8x %8x %8x %8x\n",
3008                                        entry->frame, entry->crc[0],
3009                                        entry->crc[1], entry->crc[2],
3010                                        entry->crc[3], entry->crc[4]);
3011
3012                 spin_unlock_irq(&pipe_crc->lock);
3013
3014                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3015                 if (ret == PIPE_CRC_LINE_LEN)
3016                         return -EFAULT;
3017
3018                 user_buf += PIPE_CRC_LINE_LEN;
3019                 n_entries--;
3020
3021                 spin_lock_irq(&pipe_crc->lock);
3022         }
3023
3024         spin_unlock_irq(&pipe_crc->lock);
3025
3026         return bytes_read;
3027 }
3028
3029 static const struct file_operations i915_pipe_crc_fops = {
3030         .owner = THIS_MODULE,
3031         .open = i915_pipe_crc_open,
3032         .read = i915_pipe_crc_read,
3033         .release = i915_pipe_crc_release,
3034 };
3035
3036 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3037         {
3038                 .name = "i915_pipe_A_crc",
3039                 .pipe = PIPE_A,
3040         },
3041         {
3042                 .name = "i915_pipe_B_crc",
3043                 .pipe = PIPE_B,
3044         },
3045         {
3046                 .name = "i915_pipe_C_crc",
3047                 .pipe = PIPE_C,
3048         },
3049 };
3050
3051 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3052                                 enum pipe pipe)
3053 {
3054         struct drm_device *dev = minor->dev;
3055         struct dentry *ent;
3056         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3057
3058         info->dev = dev;
3059         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3060                                   &i915_pipe_crc_fops);
3061         if (!ent)
3062                 return -ENOMEM;
3063
3064         return drm_add_fake_info_node(minor, ent, info);
3065 }
3066
3067 static const char * const pipe_crc_sources[] = {
3068         "none",
3069         "plane1",
3070         "plane2",
3071         "pf",
3072         "pipe",
3073         "TV",
3074         "DP-B",
3075         "DP-C",
3076         "DP-D",
3077         "auto",
3078 };
3079
3080 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3081 {
3082         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3083         return pipe_crc_sources[source];
3084 }
3085
3086 static int display_crc_ctl_show(struct seq_file *m, void *data)
3087 {
3088         struct drm_device *dev = m->private;
3089         struct drm_i915_private *dev_priv = dev->dev_private;
3090         int i;
3091
3092         for (i = 0; i < I915_MAX_PIPES; i++)
3093                 seq_printf(m, "%c %s\n", pipe_name(i),
3094                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3095
3096         return 0;
3097 }
3098
3099 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3100 {
3101         struct drm_device *dev = inode->i_private;
3102
3103         return single_open(file, display_crc_ctl_show, dev);
3104 }
3105
3106 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3107                                  uint32_t *val)
3108 {
3109         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3110                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3111
3112         switch (*source) {
3113         case INTEL_PIPE_CRC_SOURCE_PIPE:
3114                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3115                 break;
3116         case INTEL_PIPE_CRC_SOURCE_NONE:
3117                 *val = 0;
3118                 break;
3119         default:
3120                 return -EINVAL;
3121         }
3122
3123         return 0;
3124 }
3125
3126 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3127                                      enum intel_pipe_crc_source *source)
3128 {
3129         struct intel_encoder *encoder;
3130         struct intel_crtc *crtc;
3131         struct intel_digital_port *dig_port;
3132         int ret = 0;
3133
3134         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3135
3136         drm_modeset_lock_all(dev);
3137         for_each_intel_encoder(dev, encoder) {
3138                 if (!encoder->base.crtc)
3139                         continue;
3140
3141                 crtc = to_intel_crtc(encoder->base.crtc);
3142
3143                 if (crtc->pipe != pipe)
3144                         continue;
3145
3146                 switch (encoder->type) {
3147                 case INTEL_OUTPUT_TVOUT:
3148                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3149                         break;
3150                 case INTEL_OUTPUT_DISPLAYPORT:
3151                 case INTEL_OUTPUT_EDP:
3152                         dig_port = enc_to_dig_port(&encoder->base);
3153                         switch (dig_port->port) {
3154                         case PORT_B:
3155                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3156                                 break;
3157                         case PORT_C:
3158                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3159                                 break;
3160                         case PORT_D:
3161                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3162                                 break;
3163                         default:
3164                                 WARN(1, "nonexisting DP port %c\n",
3165                                      port_name(dig_port->port));
3166                                 break;
3167                         }
3168                         break;
3169                 default:
3170                         break;
3171                 }
3172         }
3173         drm_modeset_unlock_all(dev);
3174
3175         return ret;
3176 }
3177
3178 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3179                                 enum pipe pipe,
3180                                 enum intel_pipe_crc_source *source,
3181                                 uint32_t *val)
3182 {
3183         struct drm_i915_private *dev_priv = dev->dev_private;
3184         bool need_stable_symbols = false;
3185
3186         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3187                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3188                 if (ret)
3189                         return ret;
3190         }
3191
3192         switch (*source) {
3193         case INTEL_PIPE_CRC_SOURCE_PIPE:
3194                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3195                 break;
3196         case INTEL_PIPE_CRC_SOURCE_DP_B:
3197                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3198                 need_stable_symbols = true;
3199                 break;
3200         case INTEL_PIPE_CRC_SOURCE_DP_C:
3201                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3202                 need_stable_symbols = true;
3203                 break;
3204         case INTEL_PIPE_CRC_SOURCE_DP_D:
3205                 if (!IS_CHERRYVIEW(dev))
3206                         return -EINVAL;
3207                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3208                 need_stable_symbols = true;
3209                 break;
3210         case INTEL_PIPE_CRC_SOURCE_NONE:
3211                 *val = 0;
3212                 break;
3213         default:
3214                 return -EINVAL;
3215         }
3216
3217         /*
3218          * When the pipe CRC tap point is after the transcoders we need
3219          * to tweak symbol-level features to produce a deterministic series of
3220          * symbols for a given frame. We need to reset those features only once
3221          * a frame (instead of every nth symbol):
3222          *   - DC-balance: used to ensure a better clock recovery from the data
3223          *     link (SDVO)
3224          *   - DisplayPort scrambling: used for EMI reduction
3225          */
3226         if (need_stable_symbols) {
3227                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3228
3229                 tmp |= DC_BALANCE_RESET_VLV;
3230                 switch (pipe) {
3231                 case PIPE_A:
3232                         tmp |= PIPE_A_SCRAMBLE_RESET;
3233                         break;
3234                 case PIPE_B:
3235                         tmp |= PIPE_B_SCRAMBLE_RESET;
3236                         break;
3237                 case PIPE_C:
3238                         tmp |= PIPE_C_SCRAMBLE_RESET;
3239                         break;
3240                 default:
3241                         return -EINVAL;
3242                 }
3243                 I915_WRITE(PORT_DFT2_G4X, tmp);
3244         }
3245
3246         return 0;
3247 }
3248
3249 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3250                                  enum pipe pipe,
3251                                  enum intel_pipe_crc_source *source,
3252                                  uint32_t *val)
3253 {
3254         struct drm_i915_private *dev_priv = dev->dev_private;
3255         bool need_stable_symbols = false;
3256
3257         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3258                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3259                 if (ret)
3260                         return ret;
3261         }
3262
3263         switch (*source) {
3264         case INTEL_PIPE_CRC_SOURCE_PIPE:
3265                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3266                 break;
3267         case INTEL_PIPE_CRC_SOURCE_TV:
3268                 if (!SUPPORTS_TV(dev))
3269                         return -EINVAL;
3270                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3271                 break;
3272         case INTEL_PIPE_CRC_SOURCE_DP_B:
3273                 if (!IS_G4X(dev))
3274                         return -EINVAL;
3275                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3276                 need_stable_symbols = true;
3277                 break;
3278         case INTEL_PIPE_CRC_SOURCE_DP_C:
3279                 if (!IS_G4X(dev))
3280                         return -EINVAL;
3281                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3282                 need_stable_symbols = true;
3283                 break;
3284         case INTEL_PIPE_CRC_SOURCE_DP_D:
3285                 if (!IS_G4X(dev))
3286                         return -EINVAL;
3287                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3288                 need_stable_symbols = true;
3289                 break;
3290         case INTEL_PIPE_CRC_SOURCE_NONE:
3291                 *val = 0;
3292                 break;
3293         default:
3294                 return -EINVAL;
3295         }
3296
3297         /*
3298          * When the pipe CRC tap point is after the transcoders we need
3299          * to tweak symbol-level features to produce a deterministic series of
3300          * symbols for a given frame. We need to reset those features only once
3301          * a frame (instead of every nth symbol):
3302          *   - DC-balance: used to ensure a better clock recovery from the data
3303          *     link (SDVO)
3304          *   - DisplayPort scrambling: used for EMI reduction
3305          */
3306         if (need_stable_symbols) {
3307                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3308
3309                 WARN_ON(!IS_G4X(dev));
3310
3311                 I915_WRITE(PORT_DFT_I9XX,
3312                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3313
3314                 if (pipe == PIPE_A)
3315                         tmp |= PIPE_A_SCRAMBLE_RESET;
3316                 else
3317                         tmp |= PIPE_B_SCRAMBLE_RESET;
3318
3319                 I915_WRITE(PORT_DFT2_G4X, tmp);
3320         }
3321
3322         return 0;
3323 }
3324
3325 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3326                                          enum pipe pipe)
3327 {
3328         struct drm_i915_private *dev_priv = dev->dev_private;
3329         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3330
3331         switch (pipe) {
3332         case PIPE_A:
3333                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3334                 break;
3335         case PIPE_B:
3336                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3337                 break;
3338         case PIPE_C:
3339                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3340                 break;
3341         default:
3342                 return;
3343         }
3344         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3345                 tmp &= ~DC_BALANCE_RESET_VLV;
3346         I915_WRITE(PORT_DFT2_G4X, tmp);
3347
3348 }
3349
3350 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3351                                          enum pipe pipe)
3352 {
3353         struct drm_i915_private *dev_priv = dev->dev_private;
3354         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3355
3356         if (pipe == PIPE_A)
3357                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3358         else
3359                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3360         I915_WRITE(PORT_DFT2_G4X, tmp);
3361
3362         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3363                 I915_WRITE(PORT_DFT_I9XX,
3364                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3365         }
3366 }
3367
3368 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3369                                 uint32_t *val)
3370 {
3371         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3372                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3373
3374         switch (*source) {
3375         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3376                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3377                 break;
3378         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3379                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3380                 break;
3381         case INTEL_PIPE_CRC_SOURCE_PIPE:
3382                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3383                 break;
3384         case INTEL_PIPE_CRC_SOURCE_NONE:
3385                 *val = 0;
3386                 break;
3387         default:
3388                 return -EINVAL;
3389         }
3390
3391         return 0;
3392 }
3393
3394 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3395 {
3396         struct drm_i915_private *dev_priv = dev->dev_private;
3397         struct intel_crtc *crtc =
3398                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3399
3400         drm_modeset_lock_all(dev);
3401         /*
3402          * If we use the eDP transcoder we need to make sure that we don't
3403          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3404          * relevant on hsw with pipe A when using the always-on power well
3405          * routing.
3406          */
3407         if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3408             !crtc->config->pch_pfit.enabled) {
3409                 crtc->config->pch_pfit.force_thru = true;
3410
3411                 intel_display_power_get(dev_priv,
3412                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3413
3414                 dev_priv->display.crtc_disable(&crtc->base);
3415                 dev_priv->display.crtc_enable(&crtc->base);
3416         }
3417         drm_modeset_unlock_all(dev);
3418 }
3419
3420 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3421 {
3422         struct drm_i915_private *dev_priv = dev->dev_private;
3423         struct intel_crtc *crtc =
3424                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3425
3426         drm_modeset_lock_all(dev);
3427         /*
3428          * If we use the eDP transcoder we need to make sure that we don't
3429          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3430          * relevant on hsw with pipe A when using the always-on power well
3431          * routing.
3432          */
3433         if (crtc->config->pch_pfit.force_thru) {
3434                 crtc->config->pch_pfit.force_thru = false;
3435
3436                 dev_priv->display.crtc_disable(&crtc->base);
3437                 dev_priv->display.crtc_enable(&crtc->base);
3438
3439                 intel_display_power_put(dev_priv,
3440                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3441         }
3442         drm_modeset_unlock_all(dev);
3443 }
3444
3445 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3446                                 enum pipe pipe,
3447                                 enum intel_pipe_crc_source *source,
3448                                 uint32_t *val)
3449 {
3450         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3451                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3452
3453         switch (*source) {
3454         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3455                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3456                 break;
3457         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3458                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3459                 break;
3460         case INTEL_PIPE_CRC_SOURCE_PF:
3461                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3462                         hsw_trans_edp_pipe_A_crc_wa(dev);
3463
3464                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3465                 break;
3466         case INTEL_PIPE_CRC_SOURCE_NONE:
3467                 *val = 0;
3468                 break;
3469         default:
3470                 return -EINVAL;
3471         }
3472
3473         return 0;
3474 }
3475
3476 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3477                                enum intel_pipe_crc_source source)
3478 {
3479         struct drm_i915_private *dev_priv = dev->dev_private;
3480         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3481         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3482                                                                         pipe));
3483         u32 val = 0; /* shut up gcc */
3484         int ret;
3485
3486         if (pipe_crc->source == source)
3487                 return 0;
3488
3489         /* forbid changing the source without going back to 'none' */
3490         if (pipe_crc->source && source)
3491                 return -EINVAL;
3492
3493         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3494                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3495                 return -EIO;
3496         }
3497
3498         if (IS_GEN2(dev))
3499                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3500         else if (INTEL_INFO(dev)->gen < 5)
3501                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3502         else if (IS_VALLEYVIEW(dev))
3503                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3504         else if (IS_GEN5(dev) || IS_GEN6(dev))
3505                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3506         else
3507                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3508
3509         if (ret != 0)
3510                 return ret;
3511
3512         /* none -> real source transition */
3513         if (source) {
3514                 struct intel_pipe_crc_entry *entries;
3515
3516                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3517                                  pipe_name(pipe), pipe_crc_source_name(source));
3518
3519                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3520                                   sizeof(pipe_crc->entries[0]),
3521                                   GFP_KERNEL);
3522                 if (!entries)
3523                         return -ENOMEM;
3524
3525                 /*
3526                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3527                  * enabled and disabled dynamically based on package C states,
3528                  * user space can't make reliable use of the CRCs, so let's just
3529                  * completely disable it.
3530                  */
3531                 hsw_disable_ips(crtc);
3532
3533                 spin_lock_irq(&pipe_crc->lock);
3534                 kfree(pipe_crc->entries);
3535                 pipe_crc->entries = entries;
3536                 pipe_crc->head = 0;
3537                 pipe_crc->tail = 0;
3538                 spin_unlock_irq(&pipe_crc->lock);
3539         }
3540
3541         pipe_crc->source = source;
3542
3543         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3544         POSTING_READ(PIPE_CRC_CTL(pipe));
3545
3546         /* real source -> none transition */
3547         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3548                 struct intel_pipe_crc_entry *entries;
3549                 struct intel_crtc *crtc =
3550                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3551
3552                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3553                                  pipe_name(pipe));
3554
3555                 drm_modeset_lock(&crtc->base.mutex, NULL);
3556                 if (crtc->active)
3557                         intel_wait_for_vblank(dev, pipe);
3558                 drm_modeset_unlock(&crtc->base.mutex);
3559
3560                 spin_lock_irq(&pipe_crc->lock);
3561                 entries = pipe_crc->entries;
3562                 pipe_crc->entries = NULL;
3563                 pipe_crc->head = 0;
3564                 pipe_crc->tail = 0;
3565                 spin_unlock_irq(&pipe_crc->lock);
3566
3567                 kfree(entries);
3568
3569                 if (IS_G4X(dev))
3570                         g4x_undo_pipe_scramble_reset(dev, pipe);
3571                 else if (IS_VALLEYVIEW(dev))
3572                         vlv_undo_pipe_scramble_reset(dev, pipe);
3573                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3574                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3575
3576                 hsw_enable_ips(crtc);
3577         }
3578
3579         return 0;
3580 }
3581
3582 /*
3583  * Parse pipe CRC command strings:
3584  *   command: wsp* object wsp+ name wsp+ source wsp*
3585  *   object: 'pipe'
3586  *   name: (A | B | C)
3587  *   source: (none | plane1 | plane2 | pf)
3588  *   wsp: (#0x20 | #0x9 | #0xA)+
3589  *
3590  * eg.:
3591  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3592  *  "pipe A none"    ->  Stop CRC
3593  */
3594 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3595 {
3596         int n_words = 0;
3597
3598         while (*buf) {
3599                 char *end;
3600
3601                 /* skip leading white space */
3602                 buf = skip_spaces(buf);
3603                 if (!*buf)
3604                         break;  /* end of buffer */
3605
3606                 /* find end of word */
3607                 for (end = buf; *end && !isspace(*end); end++)
3608                         ;
3609
3610                 if (n_words == max_words) {
3611                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3612                                          max_words);
3613                         return -EINVAL; /* ran out of words[] before bytes */
3614                 }
3615
3616                 if (*end)
3617                         *end++ = '\0';
3618                 words[n_words++] = buf;
3619                 buf = end;
3620         }
3621
3622         return n_words;
3623 }
3624
3625 enum intel_pipe_crc_object {
3626         PIPE_CRC_OBJECT_PIPE,
3627 };
3628
3629 static const char * const pipe_crc_objects[] = {
3630         "pipe",
3631 };
3632
3633 static int
3634 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3635 {
3636         int i;
3637
3638         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3639                 if (!strcmp(buf, pipe_crc_objects[i])) {
3640                         *o = i;
3641                         return 0;
3642                     }
3643
3644         return -EINVAL;
3645 }
3646
3647 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3648 {
3649         const char name = buf[0];
3650
3651         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3652                 return -EINVAL;
3653
3654         *pipe = name - 'A';
3655
3656         return 0;
3657 }
3658
3659 static int
3660 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3661 {
3662         int i;
3663
3664         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3665                 if (!strcmp(buf, pipe_crc_sources[i])) {
3666                         *s = i;
3667                         return 0;
3668                     }
3669
3670         return -EINVAL;
3671 }
3672
3673 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3674 {
3675 #define N_WORDS 3
3676         int n_words;
3677         char *words[N_WORDS];
3678         enum pipe pipe;
3679         enum intel_pipe_crc_object object;
3680         enum intel_pipe_crc_source source;
3681
3682         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3683         if (n_words != N_WORDS) {
3684                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3685                                  N_WORDS);
3686                 return -EINVAL;
3687         }
3688
3689         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3690                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3691                 return -EINVAL;
3692         }
3693
3694         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3695                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3696                 return -EINVAL;
3697         }
3698
3699         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3700                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3701                 return -EINVAL;
3702         }
3703
3704         return pipe_crc_set_source(dev, pipe, source);
3705 }
3706
3707 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3708                                      size_t len, loff_t *offp)
3709 {
3710         struct seq_file *m = file->private_data;
3711         struct drm_device *dev = m->private;
3712         char *tmpbuf;
3713         int ret;
3714
3715         if (len == 0)
3716                 return 0;
3717
3718         if (len > PAGE_SIZE - 1) {
3719                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3720                                  PAGE_SIZE);
3721                 return -E2BIG;
3722         }
3723
3724         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3725         if (!tmpbuf)
3726                 return -ENOMEM;
3727
3728         if (copy_from_user(tmpbuf, ubuf, len)) {
3729                 ret = -EFAULT;
3730                 goto out;
3731         }
3732         tmpbuf[len] = '\0';
3733
3734         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3735
3736 out:
3737         kfree(tmpbuf);
3738         if (ret < 0)
3739                 return ret;
3740
3741         *offp += len;
3742         return len;
3743 }
3744
3745 static const struct file_operations i915_display_crc_ctl_fops = {
3746         .owner = THIS_MODULE,
3747         .open = display_crc_ctl_open,
3748         .read = seq_read,
3749         .llseek = seq_lseek,
3750         .release = single_release,
3751         .write = display_crc_ctl_write
3752 };
3753
3754 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3755 {
3756         struct drm_device *dev = m->private;
3757         int num_levels = ilk_wm_max_level(dev) + 1;
3758         int level;
3759
3760         drm_modeset_lock_all(dev);
3761
3762         for (level = 0; level < num_levels; level++) {
3763                 unsigned int latency = wm[level];
3764
3765                 /*
3766                  * - WM1+ latency values in 0.5us units
3767                  * - latencies are in us on gen9
3768                  */
3769                 if (INTEL_INFO(dev)->gen >= 9)
3770                         latency *= 10;
3771                 else if (level > 0)
3772                         latency *= 5;
3773
3774                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3775                            level, wm[level], latency / 10, latency % 10);
3776         }
3777
3778         drm_modeset_unlock_all(dev);
3779 }
3780
3781 static int pri_wm_latency_show(struct seq_file *m, void *data)
3782 {
3783         struct drm_device *dev = m->private;
3784         struct drm_i915_private *dev_priv = dev->dev_private;
3785         const uint16_t *latencies;
3786
3787         if (INTEL_INFO(dev)->gen >= 9)
3788                 latencies = dev_priv->wm.skl_latency;
3789         else
3790                 latencies = to_i915(dev)->wm.pri_latency;
3791
3792         wm_latency_show(m, latencies);
3793
3794         return 0;
3795 }
3796
3797 static int spr_wm_latency_show(struct seq_file *m, void *data)
3798 {
3799         struct drm_device *dev = m->private;
3800         struct drm_i915_private *dev_priv = dev->dev_private;
3801         const uint16_t *latencies;
3802
3803         if (INTEL_INFO(dev)->gen >= 9)
3804                 latencies = dev_priv->wm.skl_latency;
3805         else
3806                 latencies = to_i915(dev)->wm.spr_latency;
3807
3808         wm_latency_show(m, latencies);
3809
3810         return 0;
3811 }
3812
3813 static int cur_wm_latency_show(struct seq_file *m, void *data)
3814 {
3815         struct drm_device *dev = m->private;
3816         struct drm_i915_private *dev_priv = dev->dev_private;
3817         const uint16_t *latencies;
3818
3819         if (INTEL_INFO(dev)->gen >= 9)
3820                 latencies = dev_priv->wm.skl_latency;
3821         else
3822                 latencies = to_i915(dev)->wm.cur_latency;
3823
3824         wm_latency_show(m, latencies);
3825
3826         return 0;
3827 }
3828
3829 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3830 {
3831         struct drm_device *dev = inode->i_private;
3832
3833         if (HAS_GMCH_DISPLAY(dev))
3834                 return -ENODEV;
3835
3836         return single_open(file, pri_wm_latency_show, dev);
3837 }
3838
3839 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3840 {
3841         struct drm_device *dev = inode->i_private;
3842
3843         if (HAS_GMCH_DISPLAY(dev))
3844                 return -ENODEV;
3845
3846         return single_open(file, spr_wm_latency_show, dev);
3847 }
3848
3849 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3850 {
3851         struct drm_device *dev = inode->i_private;
3852
3853         if (HAS_GMCH_DISPLAY(dev))
3854                 return -ENODEV;
3855
3856         return single_open(file, cur_wm_latency_show, dev);
3857 }
3858
3859 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3860                                 size_t len, loff_t *offp, uint16_t wm[8])
3861 {
3862         struct seq_file *m = file->private_data;
3863         struct drm_device *dev = m->private;
3864         uint16_t new[8] = { 0 };
3865         int num_levels = ilk_wm_max_level(dev) + 1;
3866         int level;
3867         int ret;
3868         char tmp[32];
3869
3870         if (len >= sizeof(tmp))
3871                 return -EINVAL;
3872
3873         if (copy_from_user(tmp, ubuf, len))
3874                 return -EFAULT;
3875
3876         tmp[len] = '\0';
3877
3878         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3879                      &new[0], &new[1], &new[2], &new[3],
3880                      &new[4], &new[5], &new[6], &new[7]);
3881         if (ret != num_levels)
3882                 return -EINVAL;
3883
3884         drm_modeset_lock_all(dev);
3885
3886         for (level = 0; level < num_levels; level++)
3887                 wm[level] = new[level];
3888
3889         drm_modeset_unlock_all(dev);
3890
3891         return len;
3892 }
3893
3894
3895 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3896                                     size_t len, loff_t *offp)
3897 {
3898         struct seq_file *m = file->private_data;
3899         struct drm_device *dev = m->private;
3900         struct drm_i915_private *dev_priv = dev->dev_private;
3901         uint16_t *latencies;
3902
3903         if (INTEL_INFO(dev)->gen >= 9)
3904                 latencies = dev_priv->wm.skl_latency;
3905         else
3906                 latencies = to_i915(dev)->wm.pri_latency;
3907
3908         return wm_latency_write(file, ubuf, len, offp, latencies);
3909 }
3910
3911 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3912                                     size_t len, loff_t *offp)
3913 {
3914         struct seq_file *m = file->private_data;
3915         struct drm_device *dev = m->private;
3916         struct drm_i915_private *dev_priv = dev->dev_private;
3917         uint16_t *latencies;
3918
3919         if (INTEL_INFO(dev)->gen >= 9)
3920                 latencies = dev_priv->wm.skl_latency;
3921         else
3922                 latencies = to_i915(dev)->wm.spr_latency;
3923
3924         return wm_latency_write(file, ubuf, len, offp, latencies);
3925 }
3926
3927 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3928                                     size_t len, loff_t *offp)
3929 {
3930         struct seq_file *m = file->private_data;
3931         struct drm_device *dev = m->private;
3932         struct drm_i915_private *dev_priv = dev->dev_private;
3933         uint16_t *latencies;
3934
3935         if (INTEL_INFO(dev)->gen >= 9)
3936                 latencies = dev_priv->wm.skl_latency;
3937         else
3938                 latencies = to_i915(dev)->wm.cur_latency;
3939
3940         return wm_latency_write(file, ubuf, len, offp, latencies);
3941 }
3942
3943 static const struct file_operations i915_pri_wm_latency_fops = {
3944         .owner = THIS_MODULE,
3945         .open = pri_wm_latency_open,
3946         .read = seq_read,
3947         .llseek = seq_lseek,
3948         .release = single_release,
3949         .write = pri_wm_latency_write
3950 };
3951
3952 static const struct file_operations i915_spr_wm_latency_fops = {
3953         .owner = THIS_MODULE,
3954         .open = spr_wm_latency_open,
3955         .read = seq_read,
3956         .llseek = seq_lseek,
3957         .release = single_release,
3958         .write = spr_wm_latency_write
3959 };
3960
3961 static const struct file_operations i915_cur_wm_latency_fops = {
3962         .owner = THIS_MODULE,
3963         .open = cur_wm_latency_open,
3964         .read = seq_read,
3965         .llseek = seq_lseek,
3966         .release = single_release,
3967         .write = cur_wm_latency_write
3968 };
3969
3970 static int
3971 i915_wedged_get(void *data, u64 *val)
3972 {
3973         struct drm_device *dev = data;
3974         struct drm_i915_private *dev_priv = dev->dev_private;
3975
3976         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3977
3978         return 0;
3979 }
3980
3981 static int
3982 i915_wedged_set(void *data, u64 val)
3983 {
3984         struct drm_device *dev = data;
3985         struct drm_i915_private *dev_priv = dev->dev_private;
3986
3987         /*
3988          * There is no safeguard against this debugfs entry colliding
3989          * with the hangcheck calling same i915_handle_error() in
3990          * parallel, causing an explosion. For now we assume that the
3991          * test harness is responsible enough not to inject gpu hangs
3992          * while it is writing to 'i915_wedged'
3993          */
3994
3995         if (i915_reset_in_progress(&dev_priv->gpu_error))
3996                 return -EAGAIN;
3997
3998         intel_runtime_pm_get(dev_priv);
3999
4000         i915_handle_error(dev, val,
4001                           "Manually setting wedged to %llu", val);
4002
4003         intel_runtime_pm_put(dev_priv);
4004
4005         return 0;
4006 }
4007
4008 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4009                         i915_wedged_get, i915_wedged_set,
4010                         "%llu\n");
4011
4012 static int
4013 i915_ring_stop_get(void *data, u64 *val)
4014 {
4015         struct drm_device *dev = data;
4016         struct drm_i915_private *dev_priv = dev->dev_private;
4017
4018         *val = dev_priv->gpu_error.stop_rings;
4019
4020         return 0;
4021 }
4022
4023 static int
4024 i915_ring_stop_set(void *data, u64 val)
4025 {
4026         struct drm_device *dev = data;
4027         struct drm_i915_private *dev_priv = dev->dev_private;
4028         int ret;
4029
4030         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4031
4032         ret = mutex_lock_interruptible(&dev->struct_mutex);
4033         if (ret)
4034                 return ret;
4035
4036         dev_priv->gpu_error.stop_rings = val;
4037         mutex_unlock(&dev->struct_mutex);
4038
4039         return 0;
4040 }
4041
4042 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4043                         i915_ring_stop_get, i915_ring_stop_set,
4044                         "0x%08llx\n");
4045
4046 static int
4047 i915_ring_missed_irq_get(void *data, u64 *val)
4048 {
4049         struct drm_device *dev = data;
4050         struct drm_i915_private *dev_priv = dev->dev_private;
4051
4052         *val = dev_priv->gpu_error.missed_irq_rings;
4053         return 0;
4054 }
4055
4056 static int
4057 i915_ring_missed_irq_set(void *data, u64 val)
4058 {
4059         struct drm_device *dev = data;
4060         struct drm_i915_private *dev_priv = dev->dev_private;
4061         int ret;
4062
4063         /* Lock against concurrent debugfs callers */
4064         ret = mutex_lock_interruptible(&dev->struct_mutex);
4065         if (ret)
4066                 return ret;
4067         dev_priv->gpu_error.missed_irq_rings = val;
4068         mutex_unlock(&dev->struct_mutex);
4069
4070         return 0;
4071 }
4072
4073 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4074                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4075                         "0x%08llx\n");
4076
4077 static int
4078 i915_ring_test_irq_get(void *data, u64 *val)
4079 {
4080         struct drm_device *dev = data;
4081         struct drm_i915_private *dev_priv = dev->dev_private;
4082
4083         *val = dev_priv->gpu_error.test_irq_rings;
4084
4085         return 0;
4086 }
4087
4088 static int
4089 i915_ring_test_irq_set(void *data, u64 val)
4090 {
4091         struct drm_device *dev = data;
4092         struct drm_i915_private *dev_priv = dev->dev_private;
4093         int ret;
4094
4095         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4096
4097         /* Lock against concurrent debugfs callers */
4098         ret = mutex_lock_interruptible(&dev->struct_mutex);
4099         if (ret)
4100                 return ret;
4101
4102         dev_priv->gpu_error.test_irq_rings = val;
4103         mutex_unlock(&dev->struct_mutex);
4104
4105         return 0;
4106 }
4107
4108 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4109                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4110                         "0x%08llx\n");
4111
4112 #define DROP_UNBOUND 0x1
4113 #define DROP_BOUND 0x2
4114 #define DROP_RETIRE 0x4
4115 #define DROP_ACTIVE 0x8
4116 #define DROP_ALL (DROP_UNBOUND | \
4117                   DROP_BOUND | \
4118                   DROP_RETIRE | \
4119                   DROP_ACTIVE)
4120 static int
4121 i915_drop_caches_get(void *data, u64 *val)
4122 {
4123         *val = DROP_ALL;
4124
4125         return 0;
4126 }
4127
4128 static int
4129 i915_drop_caches_set(void *data, u64 val)
4130 {
4131         struct drm_device *dev = data;
4132         struct drm_i915_private *dev_priv = dev->dev_private;
4133         int ret;
4134
4135         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4136
4137         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4138          * on ioctls on -EAGAIN. */
4139         ret = mutex_lock_interruptible(&dev->struct_mutex);
4140         if (ret)
4141                 return ret;
4142
4143         if (val & DROP_ACTIVE) {
4144                 ret = i915_gpu_idle(dev);
4145                 if (ret)
4146                         goto unlock;
4147         }
4148
4149         if (val & (DROP_RETIRE | DROP_ACTIVE))
4150                 i915_gem_retire_requests(dev);
4151
4152         if (val & DROP_BOUND)
4153                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4154
4155         if (val & DROP_UNBOUND)
4156                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4157
4158 unlock:
4159         mutex_unlock(&dev->struct_mutex);
4160
4161         return ret;
4162 }
4163
4164 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4165                         i915_drop_caches_get, i915_drop_caches_set,
4166                         "0x%08llx\n");
4167
4168 static int
4169 i915_max_freq_get(void *data, u64 *val)
4170 {
4171         struct drm_device *dev = data;
4172         struct drm_i915_private *dev_priv = dev->dev_private;
4173         int ret;
4174
4175         if (INTEL_INFO(dev)->gen < 6)
4176                 return -ENODEV;
4177
4178         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4179
4180         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4181         if (ret)
4182                 return ret;
4183
4184         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4185         mutex_unlock(&dev_priv->rps.hw_lock);
4186
4187         return 0;
4188 }
4189
4190 static int
4191 i915_max_freq_set(void *data, u64 val)
4192 {
4193         struct drm_device *dev = data;
4194         struct drm_i915_private *dev_priv = dev->dev_private;
4195         u32 hw_max, hw_min;
4196         int ret;
4197
4198         if (INTEL_INFO(dev)->gen < 6)
4199                 return -ENODEV;
4200
4201         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4202
4203         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4204
4205         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4206         if (ret)
4207                 return ret;
4208
4209         /*
4210          * Turbo will still be enabled, but won't go above the set value.
4211          */
4212         val = intel_freq_opcode(dev_priv, val);
4213
4214         hw_max = dev_priv->rps.max_freq;
4215         hw_min = dev_priv->rps.min_freq;
4216
4217         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4218                 mutex_unlock(&dev_priv->rps.hw_lock);
4219                 return -EINVAL;
4220         }
4221
4222         dev_priv->rps.max_freq_softlimit = val;
4223
4224         intel_set_rps(dev, val);
4225
4226         mutex_unlock(&dev_priv->rps.hw_lock);
4227
4228         return 0;
4229 }
4230
4231 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4232                         i915_max_freq_get, i915_max_freq_set,
4233                         "%llu\n");
4234
4235 static int
4236 i915_min_freq_get(void *data, u64 *val)
4237 {
4238         struct drm_device *dev = data;
4239         struct drm_i915_private *dev_priv = dev->dev_private;
4240         int ret;
4241
4242         if (INTEL_INFO(dev)->gen < 6)
4243                 return -ENODEV;
4244
4245         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4246
4247         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4248         if (ret)
4249                 return ret;
4250
4251         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4252         mutex_unlock(&dev_priv->rps.hw_lock);
4253
4254         return 0;
4255 }
4256
4257 static int
4258 i915_min_freq_set(void *data, u64 val)
4259 {
4260         struct drm_device *dev = data;
4261         struct drm_i915_private *dev_priv = dev->dev_private;
4262         u32 hw_max, hw_min;
4263         int ret;
4264
4265         if (INTEL_INFO(dev)->gen < 6)
4266                 return -ENODEV;
4267
4268         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4269
4270         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4271
4272         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4273         if (ret)
4274                 return ret;
4275
4276         /*
4277          * Turbo will still be enabled, but won't go below the set value.
4278          */
4279         val = intel_freq_opcode(dev_priv, val);
4280
4281         hw_max = dev_priv->rps.max_freq;
4282         hw_min = dev_priv->rps.min_freq;
4283
4284         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4285                 mutex_unlock(&dev_priv->rps.hw_lock);
4286                 return -EINVAL;
4287         }
4288
4289         dev_priv->rps.min_freq_softlimit = val;
4290
4291         intel_set_rps(dev, val);
4292
4293         mutex_unlock(&dev_priv->rps.hw_lock);
4294
4295         return 0;
4296 }
4297
4298 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4299                         i915_min_freq_get, i915_min_freq_set,
4300                         "%llu\n");
4301
4302 static int
4303 i915_cache_sharing_get(void *data, u64 *val)
4304 {
4305         struct drm_device *dev = data;
4306         struct drm_i915_private *dev_priv = dev->dev_private;
4307         u32 snpcr;
4308         int ret;
4309
4310         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4311                 return -ENODEV;
4312
4313         ret = mutex_lock_interruptible(&dev->struct_mutex);
4314         if (ret)
4315                 return ret;
4316         intel_runtime_pm_get(dev_priv);
4317
4318         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4319
4320         intel_runtime_pm_put(dev_priv);
4321         mutex_unlock(&dev_priv->dev->struct_mutex);
4322
4323         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4324
4325         return 0;
4326 }
4327
4328 static int
4329 i915_cache_sharing_set(void *data, u64 val)
4330 {
4331         struct drm_device *dev = data;
4332         struct drm_i915_private *dev_priv = dev->dev_private;
4333         u32 snpcr;
4334
4335         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4336                 return -ENODEV;
4337
4338         if (val > 3)
4339                 return -EINVAL;
4340
4341         intel_runtime_pm_get(dev_priv);
4342         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4343
4344         /* Update the cache sharing policy here as well */
4345         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4346         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4347         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4348         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4349
4350         intel_runtime_pm_put(dev_priv);
4351         return 0;
4352 }
4353
4354 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4355                         i915_cache_sharing_get, i915_cache_sharing_set,
4356                         "%llu\n");
4357
4358 static int i915_sseu_status(struct seq_file *m, void *unused)
4359 {
4360         struct drm_info_node *node = (struct drm_info_node *) m->private;
4361         struct drm_device *dev = node->minor->dev;
4362         struct drm_i915_private *dev_priv = dev->dev_private;
4363         unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
4364
4365         if (INTEL_INFO(dev)->gen < 9)
4366                 return -ENODEV;
4367
4368         seq_puts(m, "SSEU Device Info\n");
4369         seq_printf(m, "  Available Slice Total: %u\n",
4370                    INTEL_INFO(dev)->slice_total);
4371         seq_printf(m, "  Available Subslice Total: %u\n",
4372                    INTEL_INFO(dev)->subslice_total);
4373         seq_printf(m, "  Available Subslice Per Slice: %u\n",
4374                    INTEL_INFO(dev)->subslice_per_slice);
4375         seq_printf(m, "  Available EU Total: %u\n",
4376                    INTEL_INFO(dev)->eu_total);
4377         seq_printf(m, "  Available EU Per Subslice: %u\n",
4378                    INTEL_INFO(dev)->eu_per_subslice);
4379         seq_printf(m, "  Has Slice Power Gating: %s\n",
4380                    yesno(INTEL_INFO(dev)->has_slice_pg));
4381         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4382                    yesno(INTEL_INFO(dev)->has_subslice_pg));
4383         seq_printf(m, "  Has EU Power Gating: %s\n",
4384                    yesno(INTEL_INFO(dev)->has_eu_pg));
4385
4386         seq_puts(m, "SSEU Device Status\n");
4387         if (IS_SKYLAKE(dev)) {
4388                 const int s_max = 3, ss_max = 4;
4389                 int s, ss;
4390                 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4391
4392                 s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
4393                 s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
4394                 s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
4395                 eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
4396                 eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
4397                 eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
4398                 eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
4399                 eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
4400                 eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
4401                 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4402                              GEN9_PGCTL_SSA_EU19_ACK |
4403                              GEN9_PGCTL_SSA_EU210_ACK |
4404                              GEN9_PGCTL_SSA_EU311_ACK;
4405                 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4406                              GEN9_PGCTL_SSB_EU19_ACK |
4407                              GEN9_PGCTL_SSB_EU210_ACK |
4408                              GEN9_PGCTL_SSB_EU311_ACK;
4409
4410                 for (s = 0; s < s_max; s++) {
4411                         if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4412                                 /* skip disabled slice */
4413                                 continue;
4414
4415                         s_tot++;
4416                         ss_per = INTEL_INFO(dev)->subslice_per_slice;
4417                         ss_tot += ss_per;
4418                         for (ss = 0; ss < ss_max; ss++) {
4419                                 unsigned int eu_cnt;
4420
4421                                 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4422                                                        eu_mask[ss%2]);
4423                                 eu_tot += eu_cnt;
4424                                 eu_per = max(eu_per, eu_cnt);
4425                         }
4426                 }
4427         }
4428         seq_printf(m, "  Enabled Slice Total: %u\n", s_tot);
4429         seq_printf(m, "  Enabled Subslice Total: %u\n", ss_tot);
4430         seq_printf(m, "  Enabled Subslice Per Slice: %u\n", ss_per);
4431         seq_printf(m, "  Enabled EU Total: %u\n", eu_tot);
4432         seq_printf(m, "  Enabled EU Per Subslice: %u\n", eu_per);
4433
4434         return 0;
4435 }
4436
4437 static int i915_forcewake_open(struct inode *inode, struct file *file)
4438 {
4439         struct drm_device *dev = inode->i_private;
4440         struct drm_i915_private *dev_priv = dev->dev_private;
4441
4442         if (INTEL_INFO(dev)->gen < 6)
4443                 return 0;
4444
4445         intel_runtime_pm_get(dev_priv);
4446         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4447
4448         return 0;
4449 }
4450
4451 static int i915_forcewake_release(struct inode *inode, struct file *file)
4452 {
4453         struct drm_device *dev = inode->i_private;
4454         struct drm_i915_private *dev_priv = dev->dev_private;
4455
4456         if (INTEL_INFO(dev)->gen < 6)
4457                 return 0;
4458
4459         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4460         intel_runtime_pm_put(dev_priv);
4461
4462         return 0;
4463 }
4464
4465 static const struct file_operations i915_forcewake_fops = {
4466         .owner = THIS_MODULE,
4467         .open = i915_forcewake_open,
4468         .release = i915_forcewake_release,
4469 };
4470
4471 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4472 {
4473         struct drm_device *dev = minor->dev;
4474         struct dentry *ent;
4475
4476         ent = debugfs_create_file("i915_forcewake_user",
4477                                   S_IRUSR,
4478                                   root, dev,
4479                                   &i915_forcewake_fops);
4480         if (!ent)
4481                 return -ENOMEM;
4482
4483         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4484 }
4485
4486 static int i915_debugfs_create(struct dentry *root,
4487                                struct drm_minor *minor,
4488                                const char *name,
4489                                const struct file_operations *fops)
4490 {
4491         struct drm_device *dev = minor->dev;
4492         struct dentry *ent;
4493
4494         ent = debugfs_create_file(name,
4495                                   S_IRUGO | S_IWUSR,
4496                                   root, dev,
4497                                   fops);
4498         if (!ent)
4499                 return -ENOMEM;
4500
4501         return drm_add_fake_info_node(minor, ent, fops);
4502 }
4503
4504 static const struct drm_info_list i915_debugfs_list[] = {
4505         {"i915_capabilities", i915_capabilities, 0},
4506         {"i915_gem_objects", i915_gem_object_info, 0},
4507         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4508         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4509         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4510         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4511         {"i915_gem_stolen", i915_gem_stolen_list_info },
4512         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4513         {"i915_gem_request", i915_gem_request_info, 0},
4514         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4515         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4516         {"i915_gem_interrupt", i915_interrupt_info, 0},
4517         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4518         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4519         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4520         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4521         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4522         {"i915_frequency_info", i915_frequency_info, 0},
4523         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4524         {"i915_drpc_info", i915_drpc_info, 0},
4525         {"i915_emon_status", i915_emon_status, 0},
4526         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4527         {"i915_fbc_status", i915_fbc_status, 0},
4528         {"i915_ips_status", i915_ips_status, 0},
4529         {"i915_sr_status", i915_sr_status, 0},
4530         {"i915_opregion", i915_opregion, 0},
4531         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4532         {"i915_context_status", i915_context_status, 0},
4533         {"i915_dump_lrc", i915_dump_lrc, 0},
4534         {"i915_execlists", i915_execlists, 0},
4535         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4536         {"i915_swizzle_info", i915_swizzle_info, 0},
4537         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4538         {"i915_llc", i915_llc, 0},
4539         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4540         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4541         {"i915_energy_uJ", i915_energy_uJ, 0},
4542         {"i915_pc8_status", i915_pc8_status, 0},
4543         {"i915_power_domain_info", i915_power_domain_info, 0},
4544         {"i915_display_info", i915_display_info, 0},
4545         {"i915_semaphore_status", i915_semaphore_status, 0},
4546         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4547         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4548         {"i915_wa_registers", i915_wa_registers, 0},
4549         {"i915_ddb_info", i915_ddb_info, 0},
4550         {"i915_sseu_status", i915_sseu_status, 0},
4551 };
4552 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4553
4554 static const struct i915_debugfs_files {
4555         const char *name;
4556         const struct file_operations *fops;
4557 } i915_debugfs_files[] = {
4558         {"i915_wedged", &i915_wedged_fops},
4559         {"i915_max_freq", &i915_max_freq_fops},
4560         {"i915_min_freq", &i915_min_freq_fops},
4561         {"i915_cache_sharing", &i915_cache_sharing_fops},
4562         {"i915_ring_stop", &i915_ring_stop_fops},
4563         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4564         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4565         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4566         {"i915_error_state", &i915_error_state_fops},
4567         {"i915_next_seqno", &i915_next_seqno_fops},
4568         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4569         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4570         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4571         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4572         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4573 };
4574
4575 void intel_display_crc_init(struct drm_device *dev)
4576 {
4577         struct drm_i915_private *dev_priv = dev->dev_private;
4578         enum pipe pipe;
4579
4580         for_each_pipe(dev_priv, pipe) {
4581                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4582
4583                 pipe_crc->opened = false;
4584                 spin_lock_init(&pipe_crc->lock);
4585                 init_waitqueue_head(&pipe_crc->wq);
4586         }
4587 }
4588
4589 int i915_debugfs_init(struct drm_minor *minor)
4590 {
4591         int ret, i;
4592
4593         ret = i915_forcewake_create(minor->debugfs_root, minor);
4594         if (ret)
4595                 return ret;
4596
4597         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4598                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4599                 if (ret)
4600                         return ret;
4601         }
4602
4603         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4604                 ret = i915_debugfs_create(minor->debugfs_root, minor,
4605                                           i915_debugfs_files[i].name,
4606                                           i915_debugfs_files[i].fops);
4607                 if (ret)
4608                         return ret;
4609         }
4610
4611         return drm_debugfs_create_files(i915_debugfs_list,
4612                                         I915_DEBUGFS_ENTRIES,
4613                                         minor->debugfs_root, minor);
4614 }
4615
4616 void i915_debugfs_cleanup(struct drm_minor *minor)
4617 {
4618         int i;
4619
4620         drm_debugfs_remove_files(i915_debugfs_list,
4621                                  I915_DEBUGFS_ENTRIES, minor);
4622
4623         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4624                                  1, minor);
4625
4626         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4627                 struct drm_info_list *info_list =
4628                         (struct drm_info_list *)&i915_pipe_crc_data[i];
4629
4630                 drm_debugfs_remove_files(info_list, 1, minor);
4631         }
4632
4633         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4634                 struct drm_info_list *info_list =
4635                         (struct drm_info_list *) i915_debugfs_files[i].fops;
4636
4637                 drm_debugfs_remove_files(info_list, 1, minor);
4638         }
4639 }