drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (i915_gem_obj_is_pinned(obj))
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct i915_vma *vma;
 124         int pin_count = 0;
 125
 126         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
 127                    &obj->base,
 128                    get_pin_flag(obj),
 129                    get_tiling_flag(obj),
 130                    get_global_flag(obj),
 131                    obj->base.size / 1024,
 132                    obj->base.read_domains,
 133                    obj->base.write_domain,
 134                    i915_gem_request_get_seqno(obj->last_read_req),
 135                    i915_gem_request_get_seqno(obj->last_write_req),
 136                    i915_gem_request_get_seqno(obj->last_fenced_req),
 137                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 138                    obj->dirty ? " dirty" : "",
 139                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 140         if (obj->base.name)
 141                 seq_printf(m, " (name: %d)", obj->base.name);
 142         list_for_each_entry(vma, &obj->vma_list, vma_link)
 143                 if (vma->pin_count > 0)
 144                         pin_count++;
 145                 seq_printf(m, " (pinned x %d)", pin_count);
 146         if (obj->pin_display)
 147                 seq_printf(m, " (display)");
 148         if (obj->fence_reg != I915_FENCE_REG_NONE)
 149                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 150         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 151                 if (!i915_is_ggtt(vma->vm))
 152                         seq_puts(m, " (pp");
 153                 else
 154                         seq_puts(m, " (g");
 155                 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
 156                            vma->node.start, vma->node.size,
 157                            vma->ggtt_view.type);
 158         }
 159         if (obj->stolen)
 160                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 161         if (obj->pin_mappable || obj->fault_mappable) {
 162                 char s[3], *t = s;
 163                 if (obj->pin_mappable)
 164                         *t++ = 'p';
 165                 if (obj->fault_mappable)
 166                         *t++ = 'f';
 167                 *t = '\0';
 168                 seq_printf(m, " (%s mappable)", s);
 169         }
 170         if (obj->last_read_req != NULL)
 171                 seq_printf(m, " (%s)",
 172                            i915_gem_request_get_ring(obj->last_read_req)->name);
 173         if (obj->frontbuffer_bits)
 174                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 175 }
 176
 177 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 178 {
 179         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 180         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 181         seq_putc(m, ' ');
 182 }
 183
 184 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 185 {
 186         struct drm_info_node *node = m->private;
 187         uintptr_t list = (uintptr_t) node->info_ent->data;
 188         struct list_head *head;
 189         struct drm_device *dev = node->minor->dev;
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         struct i915_address_space *vm = &dev_priv->gtt.base;
 192         struct i915_vma *vma;
 193         size_t total_obj_size, total_gtt_size;
 194         int count, ret;
 195
 196         ret = mutex_lock_interruptible(&dev->struct_mutex);
 197         if (ret)
 198                 return ret;
 199
 200         /* FIXME: the user of this interface might want more than just GGTT */
 201         switch (list) {
 202         case ACTIVE_LIST:
 203                 seq_puts(m, "Active:\n");
 204                 head = &vm->active_list;
 205                 break;
 206         case INACTIVE_LIST:
 207                 seq_puts(m, "Inactive:\n");
 208                 head = &vm->inactive_list;
 209                 break;
 210         default:
 211                 mutex_unlock(&dev->struct_mutex);
 212                 return -EINVAL;
 213         }
 214
 215         total_obj_size = total_gtt_size = count = 0;
 216         list_for_each_entry(vma, head, mm_list) {
 217                 seq_printf(m, "   ");
 218                 describe_obj(m, vma->obj);
 219                 seq_printf(m, "\n");
 220                 total_obj_size += vma->obj->base.size;
 221                 total_gtt_size += vma->node.size;
 222                 count++;
 223         }
 224         mutex_unlock(&dev->struct_mutex);
 225
 226         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 227                    count, total_obj_size, total_gtt_size);
 228         return 0;
 229 }
 230
 231 static int obj_rank_by_stolen(void *priv,
 232                               struct list_head *A, struct list_head *B)
 233 {
 234         struct drm_i915_gem_object *a =
 235                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 236         struct drm_i915_gem_object *b =
 237                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 238
 239         return a->stolen->start - b->stolen->start;
 240 }
 241
 242 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 243 {
 244         struct drm_info_node *node = m->private;
 245         struct drm_device *dev = node->minor->dev;
 246         struct drm_i915_private *dev_priv = dev->dev_private;
 247         struct drm_i915_gem_object *obj;
 248         size_t total_obj_size, total_gtt_size;
 249         LIST_HEAD(stolen);
 250         int count, ret;
 251
 252         ret = mutex_lock_interruptible(&dev->struct_mutex);
 253         if (ret)
 254                 return ret;
 255
 256         total_obj_size = total_gtt_size = count = 0;
 257         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 258                 if (obj->stolen == NULL)
 259                         continue;
 260
 261                 list_add(&obj->obj_exec_link, &stolen);
 262
 263                 total_obj_size += obj->base.size;
 264                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 265                 count++;
 266         }
 267         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 268                 if (obj->stolen == NULL)
 269                         continue;
 270
 271                 list_add(&obj->obj_exec_link, &stolen);
 272
 273                 total_obj_size += obj->base.size;
 274                 count++;
 275         }
 276         list_sort(NULL, &stolen, obj_rank_by_stolen);
 277         seq_puts(m, "Stolen:\n");
 278         while (!list_empty(&stolen)) {
 279                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 280                 seq_puts(m, "   ");
 281                 describe_obj(m, obj);
 282                 seq_putc(m, '\n');
 283                 list_del_init(&obj->obj_exec_link);
 284         }
 285         mutex_unlock(&dev->struct_mutex);
 286
 287         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 288                    count, total_obj_size, total_gtt_size);
 289         return 0;
 290 }
 291
 292 #define count_objects(list, member) do { \
 293         list_for_each_entry(obj, list, member) { \
 294                 size += i915_gem_obj_ggtt_size(obj); \
 295                 ++count; \
 296                 if (obj->map_and_fenceable) { \
 297                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 298                         ++mappable_count; \
 299                 } \
 300         } \
 301 } while (0)
 302
 303 struct file_stats {
 304         struct drm_i915_file_private *file_priv;
 305         int count;
 306         size_t total, unbound;
 307         size_t global, shared;
 308         size_t active, inactive;
 309 };
 310
 311 static int per_file_stats(int id, void *ptr, void *data)
 312 {
 313         struct drm_i915_gem_object *obj = ptr;
 314         struct file_stats *stats = data;
 315         struct i915_vma *vma;
 316
 317         stats->count++;
 318         stats->total += obj->base.size;
 319
 320         if (obj->base.name || obj->base.dma_buf)
 321                 stats->shared += obj->base.size;
 322
 323         if (USES_FULL_PPGTT(obj->base.dev)) {
 324                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 325                         struct i915_hw_ppgtt *ppgtt;
 326
 327                         if (!drm_mm_node_allocated(&vma->node))
 328                                 continue;
 329
 330                         if (i915_is_ggtt(vma->vm)) {
 331                                 stats->global += obj->base.size;
 332                                 continue;
 333                         }
 334
 335                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 336                         if (ppgtt->file_priv != stats->file_priv)
 337                                 continue;
 338
 339                         if (obj->active) /* XXX per-vma statistic */
 340                                 stats->active += obj->base.size;
 341                         else
 342                                 stats->inactive += obj->base.size;
 343
 344                         return 0;
 345                 }
 346         } else {
 347                 if (i915_gem_obj_ggtt_bound(obj)) {
 348                         stats->global += obj->base.size;
 349                         if (obj->active)
 350                                 stats->active += obj->base.size;
 351                         else
 352                                 stats->inactive += obj->base.size;
 353                         return 0;
 354                 }
 355         }
 356
 357         if (!list_empty(&obj->global_list))
 358                 stats->unbound += obj->base.size;
 359
 360         return 0;
 361 }
 362
 363 #define print_file_stats(m, name, stats) \
 364         seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
 365                    name, \
 366                    stats.count, \
 367                    stats.total, \
 368                    stats.active, \
 369                    stats.inactive, \
 370                    stats.global, \
 371                    stats.shared, \
 372                    stats.unbound)
 373
 374 static void print_batch_pool_stats(struct seq_file *m,
 375                                    struct drm_i915_private *dev_priv)
 376 {
 377         struct drm_i915_gem_object *obj;
 378         struct file_stats stats;
 379
 380         memset(&stats, 0, sizeof(stats));
 381
 382         list_for_each_entry(obj,
 383                             &dev_priv->mm.batch_pool.cache_list,
 384                             batch_pool_list)
 385                 per_file_stats(0, obj, &stats);
 386
 387         print_file_stats(m, "batch pool", stats);
 388 }
 389
 390 #define count_vmas(list, member) do { \
 391         list_for_each_entry(vma, list, member) { \
 392                 size += i915_gem_obj_ggtt_size(vma->obj); \
 393                 ++count; \
 394                 if (vma->obj->map_and_fenceable) { \
 395                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 396                         ++mappable_count; \
 397                 } \
 398         } \
 399 } while (0)
 400
 401 static int i915_gem_object_info(struct seq_file *m, void* data)
 402 {
 403         struct drm_info_node *node = m->private;
 404         struct drm_device *dev = node->minor->dev;
 405         struct drm_i915_private *dev_priv = dev->dev_private;
 406         u32 count, mappable_count, purgeable_count;
 407         size_t size, mappable_size, purgeable_size;
 408         struct drm_i915_gem_object *obj;
 409         struct i915_address_space *vm = &dev_priv->gtt.base;
 410         struct drm_file *file;
 411         struct i915_vma *vma;
 412         int ret;
 413
 414         ret = mutex_lock_interruptible(&dev->struct_mutex);
 415         if (ret)
 416                 return ret;
 417
 418         seq_printf(m, "%u objects, %zu bytes\n",
 419                    dev_priv->mm.object_count,
 420                    dev_priv->mm.object_memory);
 421
 422         size = count = mappable_size = mappable_count = 0;
 423         count_objects(&dev_priv->mm.bound_list, global_list);
 424         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 425                    count, mappable_count, size, mappable_size);
 426
 427         size = count = mappable_size = mappable_count = 0;
 428         count_vmas(&vm->active_list, mm_list);
 429         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 430                    count, mappable_count, size, mappable_size);
 431
 432         size = count = mappable_size = mappable_count = 0;
 433         count_vmas(&vm->inactive_list, mm_list);
 434         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 435                    count, mappable_count, size, mappable_size);
 436
 437         size = count = purgeable_size = purgeable_count = 0;
 438         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 439                 size += obj->base.size, ++count;
 440                 if (obj->madv == I915_MADV_DONTNEED)
 441                         purgeable_size += obj->base.size, ++purgeable_count;
 442         }
 443         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 444
 445         size = count = mappable_size = mappable_count = 0;
 446         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 447                 if (obj->fault_mappable) {
 448                         size += i915_gem_obj_ggtt_size(obj);
 449                         ++count;
 450                 }
 451                 if (obj->pin_mappable) {
 452                         mappable_size += i915_gem_obj_ggtt_size(obj);
 453                         ++mappable_count;
 454                 }
 455                 if (obj->madv == I915_MADV_DONTNEED) {
 456                         purgeable_size += obj->base.size;
 457                         ++purgeable_count;
 458                 }
 459         }
 460         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 461                    purgeable_count, purgeable_size);
 462         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 463                    mappable_count, mappable_size);
 464         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 465                    count, size);
 466
 467         seq_printf(m, "%zu [%lu] gtt total\n",
 468                    dev_priv->gtt.base.total,
 469                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 470
 471         seq_putc(m, '\n');
 472         print_batch_pool_stats(m, dev_priv);
 473
 474         seq_putc(m, '\n');
 475         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 476                 struct file_stats stats;
 477                 struct task_struct *task;
 478
 479                 memset(&stats, 0, sizeof(stats));
 480                 stats.file_priv = file->driver_priv;
 481                 spin_lock(&file->table_lock);
 482                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 483                 spin_unlock(&file->table_lock);
 484                 /*
 485                  * Although we have a valid reference on file->pid, that does
 486                  * not guarantee that the task_struct who called get_pid() is
 487                  * still alive (e.g. get_pid(current) => fork() => exit()).
 488                  * Therefore, we need to protect this ->comm access using RCU.
 489                  */
 490                 rcu_read_lock();
 491                 task = pid_task(file->pid, PIDTYPE_PID);
 492                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 493                 rcu_read_unlock();
 494         }
 495
 496         mutex_unlock(&dev->struct_mutex);
 497
 498         return 0;
 499 }
 500
 501 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 502 {
 503         struct drm_info_node *node = m->private;
 504         struct drm_device *dev = node->minor->dev;
 505         uintptr_t list = (uintptr_t) node->info_ent->data;
 506         struct drm_i915_private *dev_priv = dev->dev_private;
 507         struct drm_i915_gem_object *obj;
 508         size_t total_obj_size, total_gtt_size;
 509         int count, ret;
 510
 511         ret = mutex_lock_interruptible(&dev->struct_mutex);
 512         if (ret)
 513                 return ret;
 514
 515         total_obj_size = total_gtt_size = count = 0;
 516         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 517                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 518                         continue;
 519
 520                 seq_puts(m, "   ");
 521                 describe_obj(m, obj);
 522                 seq_putc(m, '\n');
 523                 total_obj_size += obj->base.size;
 524                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 525                 count++;
 526         }
 527
 528         mutex_unlock(&dev->struct_mutex);
 529
 530         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 531                    count, total_obj_size, total_gtt_size);
 532
 533         return 0;
 534 }
 535
 536 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 537 {
 538         struct drm_info_node *node = m->private;
 539         struct drm_device *dev = node->minor->dev;
 540         struct drm_i915_private *dev_priv = dev->dev_private;
 541         struct intel_crtc *crtc;
 542         int ret;
 543
 544         ret = mutex_lock_interruptible(&dev->struct_mutex);
 545         if (ret)
 546                 return ret;
 547
 548         for_each_intel_crtc(dev, crtc) {
 549                 const char pipe = pipe_name(crtc->pipe);
 550                 const char plane = plane_name(crtc->plane);
 551                 struct intel_unpin_work *work;
 552
 553                 spin_lock_irq(&dev->event_lock);
 554                 work = crtc->unpin_work;
 555                 if (work == NULL) {
 556                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 557                                    pipe, plane);
 558                 } else {
 559                         u32 addr;
 560
 561                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 562                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 563                                            pipe, plane);
 564                         } else {
 565                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 566                                            pipe, plane);
 567                         }
 568                         if (work->flip_queued_req) {
 569                                 struct intel_engine_cs *ring =
 570                                         i915_gem_request_get_ring(work->flip_queued_req);
 571
 572                                 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
 573                                            ring->name,
 574                                            i915_gem_request_get_seqno(work->flip_queued_req),
 575                                            dev_priv->next_seqno,
 576                                            ring->get_seqno(ring, true),
 577                                            i915_gem_request_completed(work->flip_queued_req, true));
 578                         } else
 579                                 seq_printf(m, "Flip not associated with any ring\n");
 580                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 581                                    work->flip_queued_vblank,
 582                                    work->flip_ready_vblank,
 583                                    drm_vblank_count(dev, crtc->pipe));
 584                         if (work->enable_stall_check)
 585                                 seq_puts(m, "Stall check enabled, ");
 586                         else
 587                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 588                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 589
 590                         if (INTEL_INFO(dev)->gen >= 4)
 591                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 592                         else
 593                                 addr = I915_READ(DSPADDR(crtc->plane));
 594                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 595
 596                         if (work->pending_flip_obj) {
 597                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 598                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 599                         }
 600                 }
 601                 spin_unlock_irq(&dev->event_lock);
 602         }
 603
 604         mutex_unlock(&dev->struct_mutex);
 605
 606         return 0;
 607 }
 608
 609 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 610 {
 611         struct drm_info_node *node = m->private;
 612         struct drm_device *dev = node->minor->dev;
 613         struct drm_i915_private *dev_priv = dev->dev_private;
 614         struct drm_i915_gem_object *obj;
 615         int count = 0;
 616         int ret;
 617
 618         ret = mutex_lock_interruptible(&dev->struct_mutex);
 619         if (ret)
 620                 return ret;
 621
 622         seq_puts(m, "cache:\n");
 623         list_for_each_entry(obj,
 624                             &dev_priv->mm.batch_pool.cache_list,
 625                             batch_pool_list) {
 626                 seq_puts(m, "   ");
 627                 describe_obj(m, obj);
 628                 seq_putc(m, '\n');
 629                 count++;
 630         }
 631
 632         seq_printf(m, "total: %d\n", count);
 633
 634         mutex_unlock(&dev->struct_mutex);
 635
 636         return 0;
 637 }
 638
 639 static int i915_gem_request_info(struct seq_file *m, void *data)
 640 {
 641         struct drm_info_node *node = m->private;
 642         struct drm_device *dev = node->minor->dev;
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         struct intel_engine_cs *ring;
 645         struct drm_i915_gem_request *gem_request;
 646         int ret, count, i;
 647
 648         ret = mutex_lock_interruptible(&dev->struct_mutex);
 649         if (ret)
 650                 return ret;
 651
 652         count = 0;
 653         for_each_ring(ring, dev_priv, i) {
 654                 if (list_empty(&ring->request_list))
 655                         continue;
 656
 657                 seq_printf(m, "%s requests:\n", ring->name);
 658                 list_for_each_entry(gem_request,
 659                                     &ring->request_list,
 660                                     list) {
 661                         seq_printf(m, "    %d @ %d\n",
 662                                    gem_request->seqno,
 663                                    (int) (jiffies - gem_request->emitted_jiffies));
 664                 }
 665                 count++;
 666         }
 667         mutex_unlock(&dev->struct_mutex);
 668
 669         if (count == 0)
 670                 seq_puts(m, "No requests\n");
 671
 672         return 0;
 673 }
 674
 675 static void i915_ring_seqno_info(struct seq_file *m,
 676                                  struct intel_engine_cs *ring)
 677 {
 678         if (ring->get_seqno) {
 679                 seq_printf(m, "Current sequence (%s): %u\n",
 680                            ring->name, ring->get_seqno(ring, false));
 681         }
 682 }
 683
 684 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 685 {
 686         struct drm_info_node *node = m->private;
 687         struct drm_device *dev = node->minor->dev;
 688         struct drm_i915_private *dev_priv = dev->dev_private;
 689         struct intel_engine_cs *ring;
 690         int ret, i;
 691
 692         ret = mutex_lock_interruptible(&dev->struct_mutex);
 693         if (ret)
 694                 return ret;
 695         intel_runtime_pm_get(dev_priv);
 696
 697         for_each_ring(ring, dev_priv, i)
 698                 i915_ring_seqno_info(m, ring);
 699
 700         intel_runtime_pm_put(dev_priv);
 701         mutex_unlock(&dev->struct_mutex);
 702
 703         return 0;
 704 }
 705
 706
 707 static int i915_interrupt_info(struct seq_file *m, void *data)
 708 {
 709         struct drm_info_node *node = m->private;
 710         struct drm_device *dev = node->minor->dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         struct intel_engine_cs *ring;
 713         int ret, i, pipe;
 714
 715         ret = mutex_lock_interruptible(&dev->struct_mutex);
 716         if (ret)
 717                 return ret;
 718         intel_runtime_pm_get(dev_priv);
 719
 720         if (IS_CHERRYVIEW(dev)) {
 721                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 722                            I915_READ(GEN8_MASTER_IRQ));
 723
 724                 seq_printf(m, "Display IER:\t%08x\n",
 725                            I915_READ(VLV_IER));
 726                 seq_printf(m, "Display IIR:\t%08x\n",
 727                            I915_READ(VLV_IIR));
 728                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 729                            I915_READ(VLV_IIR_RW));
 730                 seq_printf(m, "Display IMR:\t%08x\n",
 731                            I915_READ(VLV_IMR));
 732                 for_each_pipe(dev_priv, pipe)
 733                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 734                                    pipe_name(pipe),
 735                                    I915_READ(PIPESTAT(pipe)));
 736
 737                 seq_printf(m, "Port hotplug:\t%08x\n",
 738                            I915_READ(PORT_HOTPLUG_EN));
 739                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 740                            I915_READ(VLV_DPFLIPSTAT));
 741                 seq_printf(m, "DPINVGTT:\t%08x\n",
 742                            I915_READ(DPINVGTT));
 743
 744                 for (i = 0; i < 4; i++) {
 745                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 746                                    i, I915_READ(GEN8_GT_IMR(i)));
 747                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 748                                    i, I915_READ(GEN8_GT_IIR(i)));
 749                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 750                                    i, I915_READ(GEN8_GT_IER(i)));
 751                 }
 752
 753                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 754                            I915_READ(GEN8_PCU_IMR));
 755                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 756                            I915_READ(GEN8_PCU_IIR));
 757                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 758                            I915_READ(GEN8_PCU_IER));
 759         } else if (INTEL_INFO(dev)->gen >= 8) {
 760                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 761                            I915_READ(GEN8_MASTER_IRQ));
 762
 763                 for (i = 0; i < 4; i++) {
 764                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 765                                    i, I915_READ(GEN8_GT_IMR(i)));
 766                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 767                                    i, I915_READ(GEN8_GT_IIR(i)));
 768                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 769                                    i, I915_READ(GEN8_GT_IER(i)));
 770                 }
 771
 772                 for_each_pipe(dev_priv, pipe) {
 773                         if (!intel_display_power_is_enabled(dev_priv,
 774                                                 POWER_DOMAIN_PIPE(pipe))) {
 775                                 seq_printf(m, "Pipe %c power disabled\n",
 776                                            pipe_name(pipe));
 777                                 continue;
 778                         }
 779                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 780                                    pipe_name(pipe),
 781                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 782                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 783                                    pipe_name(pipe),
 784                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 785                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 786                                    pipe_name(pipe),
 787                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 788                 }
 789
 790                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 791                            I915_READ(GEN8_DE_PORT_IMR));
 792                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 793                            I915_READ(GEN8_DE_PORT_IIR));
 794                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 795                            I915_READ(GEN8_DE_PORT_IER));
 796
 797                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 798                            I915_READ(GEN8_DE_MISC_IMR));
 799                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 800                            I915_READ(GEN8_DE_MISC_IIR));
 801                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 802                            I915_READ(GEN8_DE_MISC_IER));
 803
 804                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 805                            I915_READ(GEN8_PCU_IMR));
 806                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 807                            I915_READ(GEN8_PCU_IIR));
 808                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IER));
 810         } else if (IS_VALLEYVIEW(dev)) {
 811                 seq_printf(m, "Display IER:\t%08x\n",
 812                            I915_READ(VLV_IER));
 813                 seq_printf(m, "Display IIR:\t%08x\n",
 814                            I915_READ(VLV_IIR));
 815                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 816                            I915_READ(VLV_IIR_RW));
 817                 seq_printf(m, "Display IMR:\t%08x\n",
 818                            I915_READ(VLV_IMR));
 819                 for_each_pipe(dev_priv, pipe)
 820                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 821                                    pipe_name(pipe),
 822                                    I915_READ(PIPESTAT(pipe)));
 823
 824                 seq_printf(m, "Master IER:\t%08x\n",
 825                            I915_READ(VLV_MASTER_IER));
 826
 827                 seq_printf(m, "Render IER:\t%08x\n",
 828                            I915_READ(GTIER));
 829                 seq_printf(m, "Render IIR:\t%08x\n",
 830                            I915_READ(GTIIR));
 831                 seq_printf(m, "Render IMR:\t%08x\n",
 832                            I915_READ(GTIMR));
 833
 834                 seq_printf(m, "PM IER:\t\t%08x\n",
 835                            I915_READ(GEN6_PMIER));
 836                 seq_printf(m, "PM IIR:\t\t%08x\n",
 837                            I915_READ(GEN6_PMIIR));
 838                 seq_printf(m, "PM IMR:\t\t%08x\n",
 839                            I915_READ(GEN6_PMIMR));
 840
 841                 seq_printf(m, "Port hotplug:\t%08x\n",
 842                            I915_READ(PORT_HOTPLUG_EN));
 843                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 844                            I915_READ(VLV_DPFLIPSTAT));
 845                 seq_printf(m, "DPINVGTT:\t%08x\n",
 846                            I915_READ(DPINVGTT));
 847
 848         } else if (!HAS_PCH_SPLIT(dev)) {
 849                 seq_printf(m, "Interrupt enable:    %08x\n",
 850                            I915_READ(IER));
 851                 seq_printf(m, "Interrupt identity:  %08x\n",
 852                            I915_READ(IIR));
 853                 seq_printf(m, "Interrupt mask:      %08x\n",
 854                            I915_READ(IMR));
 855                 for_each_pipe(dev_priv, pipe)
 856                         seq_printf(m, "Pipe %c stat:         %08x\n",
 857                                    pipe_name(pipe),
 858                                    I915_READ(PIPESTAT(pipe)));
 859         } else {
 860                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 861                            I915_READ(DEIER));
 862                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 863                            I915_READ(DEIIR));
 864                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 865                            I915_READ(DEIMR));
 866                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 867                            I915_READ(SDEIER));
 868                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 869                            I915_READ(SDEIIR));
 870                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 871                            I915_READ(SDEIMR));
 872                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 873                            I915_READ(GTIER));
 874                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 875                            I915_READ(GTIIR));
 876                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 877                            I915_READ(GTIMR));
 878         }
 879         for_each_ring(ring, dev_priv, i) {
 880                 if (INTEL_INFO(dev)->gen >= 6) {
 881                         seq_printf(m,
 882                                    "Graphics Interrupt mask (%s):       %08x\n",
 883                                    ring->name, I915_READ_IMR(ring));
 884                 }
 885                 i915_ring_seqno_info(m, ring);
 886         }
 887         intel_runtime_pm_put(dev_priv);
 888         mutex_unlock(&dev->struct_mutex);
 889
 890         return 0;
 891 }
 892
 893 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 894 {
 895         struct drm_info_node *node = m->private;
 896         struct drm_device *dev = node->minor->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898         int i, ret;
 899
 900         ret = mutex_lock_interruptible(&dev->struct_mutex);
 901         if (ret)
 902                 return ret;
 903
 904         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 905         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 906         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 907                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 908
 909                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 910                            i, dev_priv->fence_regs[i].pin_count);
 911                 if (obj == NULL)
 912                         seq_puts(m, "unused");
 913                 else
 914                         describe_obj(m, obj);
 915                 seq_putc(m, '\n');
 916         }
 917
 918         mutex_unlock(&dev->struct_mutex);
 919         return 0;
 920 }
 921
 922 static int i915_hws_info(struct seq_file *m, void *data)
 923 {
 924         struct drm_info_node *node = m->private;
 925         struct drm_device *dev = node->minor->dev;
 926         struct drm_i915_private *dev_priv = dev->dev_private;
 927         struct intel_engine_cs *ring;
 928         const u32 *hws;
 929         int i;
 930
 931         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 932         hws = ring->status_page.page_addr;
 933         if (hws == NULL)
 934                 return 0;
 935
 936         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 937                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 938                            i * 4,
 939                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 940         }
 941         return 0;
 942 }
 943
 944 static ssize_t
 945 i915_error_state_write(struct file *filp,
 946                        const char __user *ubuf,
 947                        size_t cnt,
 948                        loff_t *ppos)
 949 {
 950         struct i915_error_state_file_priv *error_priv = filp->private_data;
 951         struct drm_device *dev = error_priv->dev;
 952         int ret;
 953
 954         DRM_DEBUG_DRIVER("Resetting error state\n");
 955
 956         ret = mutex_lock_interruptible(&dev->struct_mutex);
 957         if (ret)
 958                 return ret;
 959
 960         i915_destroy_error_state(dev);
 961         mutex_unlock(&dev->struct_mutex);
 962
 963         return cnt;
 964 }
 965
 966 static int i915_error_state_open(struct inode *inode, struct file *file)
 967 {
 968         struct drm_device *dev = inode->i_private;
 969         struct i915_error_state_file_priv *error_priv;
 970
 971         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 972         if (!error_priv)
 973                 return -ENOMEM;
 974
 975         error_priv->dev = dev;
 976
 977         i915_error_state_get(dev, error_priv);
 978
 979         file->private_data = error_priv;
 980
 981         return 0;
 982 }
 983
 984 static int i915_error_state_release(struct inode *inode, struct file *file)
 985 {
 986         struct i915_error_state_file_priv *error_priv = file->private_data;
 987
 988         i915_error_state_put(error_priv);
 989         kfree(error_priv);
 990
 991         return 0;
 992 }
 993
 994 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 995                                      size_t count, loff_t *pos)
 996 {
 997         struct i915_error_state_file_priv *error_priv = file->private_data;
 998         struct drm_i915_error_state_buf error_str;
 999         loff_t tmp_pos = 0;
1000         ssize_t ret_count = 0;
1001         int ret;
1002
1003         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1004         if (ret)
1005                 return ret;
1006
1007         ret = i915_error_state_to_str(&error_str, error_priv);
1008         if (ret)
1009                 goto out;
1010
1011         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1012                                             error_str.buf,
1013                                             error_str.bytes);
1014
1015         if (ret_count < 0)
1016                 ret = ret_count;
1017         else
1018                 *pos = error_str.start + ret_count;
1019 out:
1020         i915_error_state_buf_release(&error_str);
1021         return ret ?: ret_count;
1022 }
1023
1024 static const struct file_operations i915_error_state_fops = {
1025         .owner = THIS_MODULE,
1026         .open = i915_error_state_open,
1027         .read = i915_error_state_read,
1028         .write = i915_error_state_write,
1029         .llseek = default_llseek,
1030         .release = i915_error_state_release,
1031 };
1032
1033 static int
1034 i915_next_seqno_get(void *data, u64 *val)
1035 {
1036         struct drm_device *dev = data;
1037         struct drm_i915_private *dev_priv = dev->dev_private;
1038         int ret;
1039
1040         ret = mutex_lock_interruptible(&dev->struct_mutex);
1041         if (ret)
1042                 return ret;
1043
1044         *val = dev_priv->next_seqno;
1045         mutex_unlock(&dev->struct_mutex);
1046
1047         return 0;
1048 }
1049
1050 static int
1051 i915_next_seqno_set(void *data, u64 val)
1052 {
1053         struct drm_device *dev = data;
1054         int ret;
1055
1056         ret = mutex_lock_interruptible(&dev->struct_mutex);
1057         if (ret)
1058                 return ret;
1059
1060         ret = i915_gem_set_seqno(dev, val);
1061         mutex_unlock(&dev->struct_mutex);
1062
1063         return ret;
1064 }
1065
1066 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1067                         i915_next_seqno_get, i915_next_seqno_set,
1068                         "0x%llx\n");
1069
1070 static int i915_frequency_info(struct seq_file *m, void *unused)
1071 {
1072         struct drm_info_node *node = m->private;
1073         struct drm_device *dev = node->minor->dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         int ret = 0;
1076
1077         intel_runtime_pm_get(dev_priv);
1078
1079         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1080
1081         if (IS_GEN5(dev)) {
1082                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1083                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1084
1085                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1086                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1087                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1088                            MEMSTAT_VID_SHIFT);
1089                 seq_printf(m, "Current P-state: %d\n",
1090                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1091         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1092                    IS_BROADWELL(dev)) {
1093                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1094                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1095                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1096                 u32 rpmodectl, rpinclimit, rpdeclimit;
1097                 u32 rpstat, cagf, reqf;
1098                 u32 rpupei, rpcurup, rpprevup;
1099                 u32 rpdownei, rpcurdown, rpprevdown;
1100                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1101                 int max_freq;
1102
1103                 /* RPSTAT1 is in the GT power well */
1104                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1105                 if (ret)
1106                         goto out;
1107
1108                 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1109
1110                 reqf = I915_READ(GEN6_RPNSWREQ);
1111                 reqf &= ~GEN6_TURBO_DISABLE;
1112                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1113                         reqf >>= 24;
1114                 else
1115                         reqf >>= 25;
1116                 reqf *= GT_FREQUENCY_MULTIPLIER;
1117
1118                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1119                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1120                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1121
1122                 rpstat = I915_READ(GEN6_RPSTAT1);
1123                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1124                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1125                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1126                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1127                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1128                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1129                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1130                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1131                 else
1132                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1133                 cagf *= GT_FREQUENCY_MULTIPLIER;
1134
1135                 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1136                 mutex_unlock(&dev->struct_mutex);
1137
1138                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1139                         pm_ier = I915_READ(GEN6_PMIER);
1140                         pm_imr = I915_READ(GEN6_PMIMR);
1141                         pm_isr = I915_READ(GEN6_PMISR);
1142                         pm_iir = I915_READ(GEN6_PMIIR);
1143                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1144                 } else {
1145                         pm_ier = I915_READ(GEN8_GT_IER(2));
1146                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1147                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1148                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1149                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1150                 }
1151                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1152                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1153                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1154                 seq_printf(m, "Render p-state ratio: %d\n",
1155                            (gt_perf_status & 0xff00) >> 8);
1156                 seq_printf(m, "Render p-state VID: %d\n",
1157                            gt_perf_status & 0xff);
1158                 seq_printf(m, "Render p-state limit: %d\n",
1159                            rp_state_limits & 0xff);
1160                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1161                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1162                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1163                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1164                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1165                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1166                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1167                            GEN6_CURICONT_MASK);
1168                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1169                            GEN6_CURBSYTAVG_MASK);
1170                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1171                            GEN6_CURBSYTAVG_MASK);
1172                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1173                            GEN6_CURIAVG_MASK);
1174                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1175                            GEN6_CURBSYTAVG_MASK);
1176                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1177                            GEN6_CURBSYTAVG_MASK);
1178
1179                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1180                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1181                            max_freq * GT_FREQUENCY_MULTIPLIER);
1182
1183                 max_freq = (rp_state_cap & 0xff00) >> 8;
1184                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1185                            max_freq * GT_FREQUENCY_MULTIPLIER);
1186
1187                 max_freq = rp_state_cap & 0xff;
1188                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1189                            max_freq * GT_FREQUENCY_MULTIPLIER);
1190
1191                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1192                            dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1193         } else if (IS_VALLEYVIEW(dev)) {
1194                 u32 freq_sts;
1195
1196                 mutex_lock(&dev_priv->rps.hw_lock);
1197                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1198                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1199                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1200
1201                 seq_printf(m, "max GPU freq: %d MHz\n",
1202                            vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1203
1204                 seq_printf(m, "min GPU freq: %d MHz\n",
1205                            vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1206
1207                 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
1208                            vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1209
1210                 seq_printf(m, "current GPU freq: %d MHz\n",
1211                            vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1212                 mutex_unlock(&dev_priv->rps.hw_lock);
1213         } else {
1214                 seq_puts(m, "no P-state info available\n");
1215         }
1216
1217 out:
1218         intel_runtime_pm_put(dev_priv);
1219         return ret;
1220 }
1221
1222 static int ironlake_drpc_info(struct seq_file *m)
1223 {
1224         struct drm_info_node *node = m->private;
1225         struct drm_device *dev = node->minor->dev;
1226         struct drm_i915_private *dev_priv = dev->dev_private;
1227         u32 rgvmodectl, rstdbyctl;
1228         u16 crstandvid;
1229         int ret;
1230
1231         ret = mutex_lock_interruptible(&dev->struct_mutex);
1232         if (ret)
1233                 return ret;
1234         intel_runtime_pm_get(dev_priv);
1235
1236         rgvmodectl = I915_READ(MEMMODECTL);
1237         rstdbyctl = I915_READ(RSTDBYCTL);
1238         crstandvid = I915_READ16(CRSTANDVID);
1239
1240         intel_runtime_pm_put(dev_priv);
1241         mutex_unlock(&dev->struct_mutex);
1242
1243         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1244                    "yes" : "no");
1245         seq_printf(m, "Boost freq: %d\n",
1246                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1247                    MEMMODE_BOOST_FREQ_SHIFT);
1248         seq_printf(m, "HW control enabled: %s\n",
1249                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1250         seq_printf(m, "SW control enabled: %s\n",
1251                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1252         seq_printf(m, "Gated voltage change: %s\n",
1253                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1254         seq_printf(m, "Starting frequency: P%d\n",
1255                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1256         seq_printf(m, "Max P-state: P%d\n",
1257                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1258         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1259         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1260         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1261         seq_printf(m, "Render standby enabled: %s\n",
1262                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1263         seq_puts(m, "Current RS state: ");
1264         switch (rstdbyctl & RSX_STATUS_MASK) {
1265         case RSX_STATUS_ON:
1266                 seq_puts(m, "on\n");
1267                 break;
1268         case RSX_STATUS_RC1:
1269                 seq_puts(m, "RC1\n");
1270                 break;
1271         case RSX_STATUS_RC1E:
1272                 seq_puts(m, "RC1E\n");
1273                 break;
1274         case RSX_STATUS_RS1:
1275                 seq_puts(m, "RS1\n");
1276                 break;
1277         case RSX_STATUS_RS2:
1278                 seq_puts(m, "RS2 (RC6)\n");
1279                 break;
1280         case RSX_STATUS_RS3:
1281                 seq_puts(m, "RC3 (RC6+)\n");
1282                 break;
1283         default:
1284                 seq_puts(m, "unknown\n");
1285                 break;
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int vlv_drpc_info(struct seq_file *m)
1292 {
1293
1294         struct drm_info_node *node = m->private;
1295         struct drm_device *dev = node->minor->dev;
1296         struct drm_i915_private *dev_priv = dev->dev_private;
1297         u32 rpmodectl1, rcctl1, pw_status;
1298         unsigned fw_rendercount = 0, fw_mediacount = 0;
1299
1300         intel_runtime_pm_get(dev_priv);
1301
1302         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1303         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1304         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1305
1306         intel_runtime_pm_put(dev_priv);
1307
1308         seq_printf(m, "Video Turbo Mode: %s\n",
1309                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1310         seq_printf(m, "Turbo enabled: %s\n",
1311                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1312         seq_printf(m, "HW control enabled: %s\n",
1313                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1314         seq_printf(m, "SW control enabled: %s\n",
1315                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1316                           GEN6_RP_MEDIA_SW_MODE));
1317         seq_printf(m, "RC6 Enabled: %s\n",
1318                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1319                                         GEN6_RC_CTL_EI_MODE(1))));
1320         seq_printf(m, "Render Power Well: %s\n",
1321                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1322         seq_printf(m, "Media Power Well: %s\n",
1323                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1324
1325         seq_printf(m, "Render RC6 residency since boot: %u\n",
1326                    I915_READ(VLV_GT_RENDER_RC6));
1327         seq_printf(m, "Media RC6 residency since boot: %u\n",
1328                    I915_READ(VLV_GT_MEDIA_RC6));
1329
1330         spin_lock_irq(&dev_priv->uncore.lock);
1331         fw_rendercount = dev_priv->uncore.fw_rendercount;
1332         fw_mediacount = dev_priv->uncore.fw_mediacount;
1333         spin_unlock_irq(&dev_priv->uncore.lock);
1334
1335         seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1336         seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1337
1338
1339         return 0;
1340 }
1341
1342
1343 static int gen6_drpc_info(struct seq_file *m)
1344 {
1345
1346         struct drm_info_node *node = m->private;
1347         struct drm_device *dev = node->minor->dev;
1348         struct drm_i915_private *dev_priv = dev->dev_private;
1349         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1350         unsigned forcewake_count;
1351         int count = 0, ret;
1352
1353         ret = mutex_lock_interruptible(&dev->struct_mutex);
1354         if (ret)
1355                 return ret;
1356         intel_runtime_pm_get(dev_priv);
1357
1358         spin_lock_irq(&dev_priv->uncore.lock);
1359         forcewake_count = dev_priv->uncore.forcewake_count;
1360         spin_unlock_irq(&dev_priv->uncore.lock);
1361
1362         if (forcewake_count) {
1363                 seq_puts(m, "RC information inaccurate because somebody "
1364                             "holds a forcewake reference \n");
1365         } else {
1366                 /* NB: we cannot use forcewake, else we read the wrong values */
1367                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1368                         udelay(10);
1369                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1370         }
1371
1372         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1373         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1374
1375         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1376         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1377         mutex_unlock(&dev->struct_mutex);
1378         mutex_lock(&dev_priv->rps.hw_lock);
1379         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1380         mutex_unlock(&dev_priv->rps.hw_lock);
1381
1382         intel_runtime_pm_put(dev_priv);
1383
1384         seq_printf(m, "Video Turbo Mode: %s\n",
1385                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1386         seq_printf(m, "HW control enabled: %s\n",
1387                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1388         seq_printf(m, "SW control enabled: %s\n",
1389                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1390                           GEN6_RP_MEDIA_SW_MODE));
1391         seq_printf(m, "RC1e Enabled: %s\n",
1392                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1393         seq_printf(m, "RC6 Enabled: %s\n",
1394                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1395         seq_printf(m, "Deep RC6 Enabled: %s\n",
1396                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1397         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1398                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1399         seq_puts(m, "Current RC state: ");
1400         switch (gt_core_status & GEN6_RCn_MASK) {
1401         case GEN6_RC0:
1402                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1403                         seq_puts(m, "Core Power Down\n");
1404                 else
1405                         seq_puts(m, "on\n");
1406                 break;
1407         case GEN6_RC3:
1408                 seq_puts(m, "RC3\n");
1409                 break;
1410         case GEN6_RC6:
1411                 seq_puts(m, "RC6\n");
1412                 break;
1413         case GEN6_RC7:
1414                 seq_puts(m, "RC7\n");
1415                 break;
1416         default:
1417                 seq_puts(m, "Unknown\n");
1418                 break;
1419         }
1420
1421         seq_printf(m, "Core Power Down: %s\n",
1422                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1423
1424         /* Not exactly sure what this is */
1425         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1426                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1427         seq_printf(m, "RC6 residency since boot: %u\n",
1428                    I915_READ(GEN6_GT_GFX_RC6));
1429         seq_printf(m, "RC6+ residency since boot: %u\n",
1430                    I915_READ(GEN6_GT_GFX_RC6p));
1431         seq_printf(m, "RC6++ residency since boot: %u\n",
1432                    I915_READ(GEN6_GT_GFX_RC6pp));
1433
1434         seq_printf(m, "RC6   voltage: %dmV\n",
1435                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1436         seq_printf(m, "RC6+  voltage: %dmV\n",
1437                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1438         seq_printf(m, "RC6++ voltage: %dmV\n",
1439                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1440         return 0;
1441 }
1442
1443 static int i915_drpc_info(struct seq_file *m, void *unused)
1444 {
1445         struct drm_info_node *node = m->private;
1446         struct drm_device *dev = node->minor->dev;
1447
1448         if (IS_VALLEYVIEW(dev))
1449                 return vlv_drpc_info(m);
1450         else if (INTEL_INFO(dev)->gen >= 6)
1451                 return gen6_drpc_info(m);
1452         else
1453                 return ironlake_drpc_info(m);
1454 }
1455
1456 static int i915_fbc_status(struct seq_file *m, void *unused)
1457 {
1458         struct drm_info_node *node = m->private;
1459         struct drm_device *dev = node->minor->dev;
1460         struct drm_i915_private *dev_priv = dev->dev_private;
1461
1462         if (!HAS_FBC(dev)) {
1463                 seq_puts(m, "FBC unsupported on this chipset\n");
1464                 return 0;
1465         }
1466
1467         intel_runtime_pm_get(dev_priv);
1468
1469         if (intel_fbc_enabled(dev)) {
1470                 seq_puts(m, "FBC enabled\n");
1471         } else {
1472                 seq_puts(m, "FBC disabled: ");
1473                 switch (dev_priv->fbc.no_fbc_reason) {
1474                 case FBC_OK:
1475                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1476                         break;
1477                 case FBC_UNSUPPORTED:
1478                         seq_puts(m, "unsupported by this chipset");
1479                         break;
1480                 case FBC_NO_OUTPUT:
1481                         seq_puts(m, "no outputs");
1482                         break;
1483                 case FBC_STOLEN_TOO_SMALL:
1484                         seq_puts(m, "not enough stolen memory");
1485                         break;
1486                 case FBC_UNSUPPORTED_MODE:
1487                         seq_puts(m, "mode not supported");
1488                         break;
1489                 case FBC_MODE_TOO_LARGE:
1490                         seq_puts(m, "mode too large");
1491                         break;
1492                 case FBC_BAD_PLANE:
1493                         seq_puts(m, "FBC unsupported on plane");
1494                         break;
1495                 case FBC_NOT_TILED:
1496                         seq_puts(m, "scanout buffer not tiled");
1497                         break;
1498                 case FBC_MULTIPLE_PIPES:
1499                         seq_puts(m, "multiple pipes are enabled");
1500                         break;
1501                 case FBC_MODULE_PARAM:
1502                         seq_puts(m, "disabled per module param (default off)");
1503                         break;
1504                 case FBC_CHIP_DEFAULT:
1505                         seq_puts(m, "disabled per chip default");
1506                         break;
1507                 default:
1508                         seq_puts(m, "unknown reason");
1509                 }
1510                 seq_putc(m, '\n');
1511         }
1512
1513         intel_runtime_pm_put(dev_priv);
1514
1515         return 0;
1516 }
1517
1518 static int i915_fbc_fc_get(void *data, u64 *val)
1519 {
1520         struct drm_device *dev = data;
1521         struct drm_i915_private *dev_priv = dev->dev_private;
1522
1523         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1524                 return -ENODEV;
1525
1526         drm_modeset_lock_all(dev);
1527         *val = dev_priv->fbc.false_color;
1528         drm_modeset_unlock_all(dev);
1529
1530         return 0;
1531 }
1532
1533 static int i915_fbc_fc_set(void *data, u64 val)
1534 {
1535         struct drm_device *dev = data;
1536         struct drm_i915_private *dev_priv = dev->dev_private;
1537         u32 reg;
1538
1539         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1540                 return -ENODEV;
1541
1542         drm_modeset_lock_all(dev);
1543
1544         reg = I915_READ(ILK_DPFC_CONTROL);
1545         dev_priv->fbc.false_color = val;
1546
1547         I915_WRITE(ILK_DPFC_CONTROL, val ?
1548                    (reg | FBC_CTL_FALSE_COLOR) :
1549                    (reg & ~FBC_CTL_FALSE_COLOR));
1550
1551         drm_modeset_unlock_all(dev);
1552         return 0;
1553 }
1554
1555 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1556                         i915_fbc_fc_get, i915_fbc_fc_set,
1557                         "%llu\n");
1558
1559 static int i915_ips_status(struct seq_file *m, void *unused)
1560 {
1561         struct drm_info_node *node = m->private;
1562         struct drm_device *dev = node->minor->dev;
1563         struct drm_i915_private *dev_priv = dev->dev_private;
1564
1565         if (!HAS_IPS(dev)) {
1566                 seq_puts(m, "not supported\n");
1567                 return 0;
1568         }
1569
1570         intel_runtime_pm_get(dev_priv);
1571
1572         seq_printf(m, "Enabled by kernel parameter: %s\n",
1573                    yesno(i915.enable_ips));
1574
1575         if (INTEL_INFO(dev)->gen >= 8) {
1576                 seq_puts(m, "Currently: unknown\n");
1577         } else {
1578                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1579                         seq_puts(m, "Currently: enabled\n");
1580                 else
1581                         seq_puts(m, "Currently: disabled\n");
1582         }
1583
1584         intel_runtime_pm_put(dev_priv);
1585
1586         return 0;
1587 }
1588
1589 static int i915_sr_status(struct seq_file *m, void *unused)
1590 {
1591         struct drm_info_node *node = m->private;
1592         struct drm_device *dev = node->minor->dev;
1593         struct drm_i915_private *dev_priv = dev->dev_private;
1594         bool sr_enabled = false;
1595
1596         intel_runtime_pm_get(dev_priv);
1597
1598         if (HAS_PCH_SPLIT(dev))
1599                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1600         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1601                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1602         else if (IS_I915GM(dev))
1603                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1604         else if (IS_PINEVIEW(dev))
1605                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1606
1607         intel_runtime_pm_put(dev_priv);
1608
1609         seq_printf(m, "self-refresh: %s\n",
1610                    sr_enabled ? "enabled" : "disabled");
1611
1612         return 0;
1613 }
1614
1615 static int i915_emon_status(struct seq_file *m, void *unused)
1616 {
1617         struct drm_info_node *node = m->private;
1618         struct drm_device *dev = node->minor->dev;
1619         struct drm_i915_private *dev_priv = dev->dev_private;
1620         unsigned long temp, chipset, gfx;
1621         int ret;
1622
1623         if (!IS_GEN5(dev))
1624                 return -ENODEV;
1625
1626         ret = mutex_lock_interruptible(&dev->struct_mutex);
1627         if (ret)
1628                 return ret;
1629
1630         temp = i915_mch_val(dev_priv);
1631         chipset = i915_chipset_val(dev_priv);
1632         gfx = i915_gfx_val(dev_priv);
1633         mutex_unlock(&dev->struct_mutex);
1634
1635         seq_printf(m, "GMCH temp: %ld\n", temp);
1636         seq_printf(m, "Chipset power: %ld\n", chipset);
1637         seq_printf(m, "GFX power: %ld\n", gfx);
1638         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1639
1640         return 0;
1641 }
1642
1643 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1644 {
1645         struct drm_info_node *node = m->private;
1646         struct drm_device *dev = node->minor->dev;
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         int ret = 0;
1649         int gpu_freq, ia_freq;
1650
1651         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1652                 seq_puts(m, "unsupported on this chipset\n");
1653                 return 0;
1654         }
1655
1656         intel_runtime_pm_get(dev_priv);
1657
1658         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1659
1660         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1661         if (ret)
1662                 goto out;
1663
1664         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1665
1666         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1667              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1668              gpu_freq++) {
1669                 ia_freq = gpu_freq;
1670                 sandybridge_pcode_read(dev_priv,
1671                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1672                                        &ia_freq);
1673                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1674                            gpu_freq * GT_FREQUENCY_MULTIPLIER,
1675                            ((ia_freq >> 0) & 0xff) * 100,
1676                            ((ia_freq >> 8) & 0xff) * 100);
1677         }
1678
1679         mutex_unlock(&dev_priv->rps.hw_lock);
1680
1681 out:
1682         intel_runtime_pm_put(dev_priv);
1683         return ret;
1684 }
1685
1686 static int i915_opregion(struct seq_file *m, void *unused)
1687 {
1688         struct drm_info_node *node = m->private;
1689         struct drm_device *dev = node->minor->dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         struct intel_opregion *opregion = &dev_priv->opregion;
1692         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1693         int ret;
1694
1695         if (data == NULL)
1696                 return -ENOMEM;
1697
1698         ret = mutex_lock_interruptible(&dev->struct_mutex);
1699         if (ret)
1700                 goto out;
1701
1702         if (opregion->header) {
1703                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1704                 seq_write(m, data, OPREGION_SIZE);
1705         }
1706
1707         mutex_unlock(&dev->struct_mutex);
1708
1709 out:
1710         kfree(data);
1711         return 0;
1712 }
1713
1714 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1715 {
1716         struct drm_info_node *node = m->private;
1717         struct drm_device *dev = node->minor->dev;
1718         struct intel_fbdev *ifbdev = NULL;
1719         struct intel_framebuffer *fb;
1720
1721 #ifdef CONFIG_DRM_I915_FBDEV
1722         struct drm_i915_private *dev_priv = dev->dev_private;
1723
1724         ifbdev = dev_priv->fbdev;
1725         fb = to_intel_framebuffer(ifbdev->helper.fb);
1726
1727         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1728                    fb->base.width,
1729                    fb->base.height,
1730                    fb->base.depth,
1731                    fb->base.bits_per_pixel,
1732                    atomic_read(&fb->base.refcount.refcount));
1733         describe_obj(m, fb->obj);
1734         seq_putc(m, '\n');
1735 #endif
1736
1737         mutex_lock(&dev->mode_config.fb_lock);
1738         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1739                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1740                         continue;
1741
1742                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1743                            fb->base.width,
1744                            fb->base.height,
1745                            fb->base.depth,
1746                            fb->base.bits_per_pixel,
1747                            atomic_read(&fb->base.refcount.refcount));
1748                 describe_obj(m, fb->obj);
1749                 seq_putc(m, '\n');
1750         }
1751         mutex_unlock(&dev->mode_config.fb_lock);
1752
1753         return 0;
1754 }
1755
1756 static void describe_ctx_ringbuf(struct seq_file *m,
1757                                  struct intel_ringbuffer *ringbuf)
1758 {
1759         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1760                    ringbuf->space, ringbuf->head, ringbuf->tail,
1761                    ringbuf->last_retired_head);
1762 }
1763
1764 static int i915_context_status(struct seq_file *m, void *unused)
1765 {
1766         struct drm_info_node *node = m->private;
1767         struct drm_device *dev = node->minor->dev;
1768         struct drm_i915_private *dev_priv = dev->dev_private;
1769         struct intel_engine_cs *ring;
1770         struct intel_context *ctx;
1771         int ret, i;
1772
1773         ret = mutex_lock_interruptible(&dev->struct_mutex);
1774         if (ret)
1775                 return ret;
1776
1777         if (dev_priv->ips.pwrctx) {
1778                 seq_puts(m, "power context ");
1779                 describe_obj(m, dev_priv->ips.pwrctx);
1780                 seq_putc(m, '\n');
1781         }
1782
1783         if (dev_priv->ips.renderctx) {
1784                 seq_puts(m, "render context ");
1785                 describe_obj(m, dev_priv->ips.renderctx);
1786                 seq_putc(m, '\n');
1787         }
1788
1789         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1790                 if (!i915.enable_execlists &&
1791                     ctx->legacy_hw_ctx.rcs_state == NULL)
1792                         continue;
1793
1794                 seq_puts(m, "HW context ");
1795                 describe_ctx(m, ctx);
1796                 for_each_ring(ring, dev_priv, i) {
1797                         if (ring->default_context == ctx)
1798                                 seq_printf(m, "(default context %s) ",
1799                                            ring->name);
1800                 }
1801
1802                 if (i915.enable_execlists) {
1803                         seq_putc(m, '\n');
1804                         for_each_ring(ring, dev_priv, i) {
1805                                 struct drm_i915_gem_object *ctx_obj =
1806                                         ctx->engine[i].state;
1807                                 struct intel_ringbuffer *ringbuf =
1808                                         ctx->engine[i].ringbuf;
1809
1810                                 seq_printf(m, "%s: ", ring->name);
1811                                 if (ctx_obj)
1812                                         describe_obj(m, ctx_obj);
1813                                 if (ringbuf)
1814                                         describe_ctx_ringbuf(m, ringbuf);
1815                                 seq_putc(m, '\n');
1816                         }
1817                 } else {
1818                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1819                 }
1820
1821                 seq_putc(m, '\n');
1822         }
1823
1824         mutex_unlock(&dev->struct_mutex);
1825
1826         return 0;
1827 }
1828
1829 static void i915_dump_lrc_obj(struct seq_file *m,
1830                               struct intel_engine_cs *ring,
1831                               struct drm_i915_gem_object *ctx_obj)
1832 {
1833         struct page *page;
1834         uint32_t *reg_state;
1835         int j;
1836         unsigned long ggtt_offset = 0;
1837
1838         if (ctx_obj == NULL) {
1839                 seq_printf(m, "Context on %s with no gem object\n",
1840                            ring->name);
1841                 return;
1842         }
1843
1844         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1845                    intel_execlists_ctx_id(ctx_obj));
1846
1847         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1848                 seq_puts(m, "\tNot bound in GGTT\n");
1849         else
1850                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1851
1852         if (i915_gem_object_get_pages(ctx_obj)) {
1853                 seq_puts(m, "\tFailed to get pages for context object\n");
1854                 return;
1855         }
1856
1857         page = i915_gem_object_get_page(ctx_obj, 1);
1858         if (!WARN_ON(page == NULL)) {
1859                 reg_state = kmap_atomic(page);
1860
1861                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1862                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1863                                    ggtt_offset + 4096 + (j * 4),
1864                                    reg_state[j], reg_state[j + 1],
1865                                    reg_state[j + 2], reg_state[j + 3]);
1866                 }
1867                 kunmap_atomic(reg_state);
1868         }
1869
1870         seq_putc(m, '\n');
1871 }
1872
1873 static int i915_dump_lrc(struct seq_file *m, void *unused)
1874 {
1875         struct drm_info_node *node = (struct drm_info_node *) m->private;
1876         struct drm_device *dev = node->minor->dev;
1877         struct drm_i915_private *dev_priv = dev->dev_private;
1878         struct intel_engine_cs *ring;
1879         struct intel_context *ctx;
1880         int ret, i;
1881
1882         if (!i915.enable_execlists) {
1883                 seq_printf(m, "Logical Ring Contexts are disabled\n");
1884                 return 0;
1885         }
1886
1887         ret = mutex_lock_interruptible(&dev->struct_mutex);
1888         if (ret)
1889                 return ret;
1890
1891         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1892                 for_each_ring(ring, dev_priv, i) {
1893                         if (ring->default_context != ctx)
1894                                 i915_dump_lrc_obj(m, ring,
1895                                                   ctx->engine[i].state);
1896                 }
1897         }
1898
1899         mutex_unlock(&dev->struct_mutex);
1900
1901         return 0;
1902 }
1903
1904 static int i915_execlists(struct seq_file *m, void *data)
1905 {
1906         struct drm_info_node *node = (struct drm_info_node *)m->private;
1907         struct drm_device *dev = node->minor->dev;
1908         struct drm_i915_private *dev_priv = dev->dev_private;
1909         struct intel_engine_cs *ring;
1910         u32 status_pointer;
1911         u8 read_pointer;
1912         u8 write_pointer;
1913         u32 status;
1914         u32 ctx_id;
1915         struct list_head *cursor;
1916         int ring_id, i;
1917         int ret;
1918
1919         if (!i915.enable_execlists) {
1920                 seq_puts(m, "Logical Ring Contexts are disabled\n");
1921                 return 0;
1922         }
1923
1924         ret = mutex_lock_interruptible(&dev->struct_mutex);
1925         if (ret)
1926                 return ret;
1927
1928         intel_runtime_pm_get(dev_priv);
1929
1930         for_each_ring(ring, dev_priv, ring_id) {
1931                 struct intel_ctx_submit_request *head_req = NULL;
1932                 int count = 0;
1933                 unsigned long flags;
1934
1935                 seq_printf(m, "%s\n", ring->name);
1936
1937                 status = I915_READ(RING_EXECLIST_STATUS(ring));
1938                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1939                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1940                            status, ctx_id);
1941
1942                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1943                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1944
1945                 read_pointer = ring->next_context_status_buffer;
1946                 write_pointer = status_pointer & 0x07;
1947                 if (read_pointer > write_pointer)
1948                         write_pointer += 6;
1949                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1950                            read_pointer, write_pointer);
1951
1952                 for (i = 0; i < 6; i++) {
1953                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1954                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1955
1956                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1957                                    i, status, ctx_id);
1958                 }
1959
1960                 spin_lock_irqsave(&ring->execlist_lock, flags);
1961                 list_for_each(cursor, &ring->execlist_queue)
1962                         count++;
1963                 head_req = list_first_entry_or_null(&ring->execlist_queue,
1964                                 struct intel_ctx_submit_request, execlist_link);
1965                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1966
1967                 seq_printf(m, "\t%d requests in queue\n", count);
1968                 if (head_req) {
1969                         struct drm_i915_gem_object *ctx_obj;
1970
1971                         ctx_obj = head_req->ctx->engine[ring_id].state;
1972                         seq_printf(m, "\tHead request id: %u\n",
1973                                    intel_execlists_ctx_id(ctx_obj));
1974                         seq_printf(m, "\tHead request tail: %u\n",
1975                                    head_req->tail);
1976                 }
1977
1978                 seq_putc(m, '\n');
1979         }
1980
1981         intel_runtime_pm_put(dev_priv);
1982         mutex_unlock(&dev->struct_mutex);
1983
1984         return 0;
1985 }
1986
1987 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1988 {
1989         struct drm_info_node *node = m->private;
1990         struct drm_device *dev = node->minor->dev;
1991         struct drm_i915_private *dev_priv = dev->dev_private;
1992         unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1993
1994         spin_lock_irq(&dev_priv->uncore.lock);
1995         if (IS_VALLEYVIEW(dev)) {
1996                 fw_rendercount = dev_priv->uncore.fw_rendercount;
1997                 fw_mediacount = dev_priv->uncore.fw_mediacount;
1998         } else
1999                 forcewake_count = dev_priv->uncore.forcewake_count;
2000         spin_unlock_irq(&dev_priv->uncore.lock);
2001
2002         if (IS_VALLEYVIEW(dev)) {
2003                 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
2004                 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
2005         } else
2006                 seq_printf(m, "forcewake count = %u\n", forcewake_count);
2007
2008         return 0;
2009 }
2010
2011 static const char *swizzle_string(unsigned swizzle)
2012 {
2013         switch (swizzle) {
2014         case I915_BIT_6_SWIZZLE_NONE:
2015                 return "none";
2016         case I915_BIT_6_SWIZZLE_9:
2017                 return "bit9";
2018         case I915_BIT_6_SWIZZLE_9_10:
2019                 return "bit9/bit10";
2020         case I915_BIT_6_SWIZZLE_9_11:
2021                 return "bit9/bit11";
2022         case I915_BIT_6_SWIZZLE_9_10_11:
2023                 return "bit9/bit10/bit11";
2024         case I915_BIT_6_SWIZZLE_9_17:
2025                 return "bit9/bit17";
2026         case I915_BIT_6_SWIZZLE_9_10_17:
2027                 return "bit9/bit10/bit17";
2028         case I915_BIT_6_SWIZZLE_UNKNOWN:
2029                 return "unknown";
2030         }
2031
2032         return "bug";
2033 }
2034
2035 static int i915_swizzle_info(struct seq_file *m, void *data)
2036 {
2037         struct drm_info_node *node = m->private;
2038         struct drm_device *dev = node->minor->dev;
2039         struct drm_i915_private *dev_priv = dev->dev_private;
2040         int ret;
2041
2042         ret = mutex_lock_interruptible(&dev->struct_mutex);
2043         if (ret)
2044                 return ret;
2045         intel_runtime_pm_get(dev_priv);
2046
2047         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2048                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2049         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2050                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2051
2052         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2053                 seq_printf(m, "DDC = 0x%08x\n",
2054                            I915_READ(DCC));
2055                 seq_printf(m, "DDC2 = 0x%08x\n",
2056                            I915_READ(DCC2));
2057                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2058                            I915_READ16(C0DRB3));
2059                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2060                            I915_READ16(C1DRB3));
2061         } else if (INTEL_INFO(dev)->gen >= 6) {
2062                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2063                            I915_READ(MAD_DIMM_C0));
2064                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2065                            I915_READ(MAD_DIMM_C1));
2066                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2067                            I915_READ(MAD_DIMM_C2));
2068                 seq_printf(m, "TILECTL = 0x%08x\n",
2069                            I915_READ(TILECTL));
2070                 if (INTEL_INFO(dev)->gen >= 8)
2071                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2072                                    I915_READ(GAMTARBMODE));
2073                 else
2074                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2075                                    I915_READ(ARB_MODE));
2076                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2077                            I915_READ(DISP_ARB_CTL));
2078         }
2079
2080         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2081                 seq_puts(m, "L-shaped memory detected\n");
2082
2083         intel_runtime_pm_put(dev_priv);
2084         mutex_unlock(&dev->struct_mutex);
2085
2086         return 0;
2087 }
2088
2089 static int per_file_ctx(int id, void *ptr, void *data)
2090 {
2091         struct intel_context *ctx = ptr;
2092         struct seq_file *m = data;
2093         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2094
2095         if (!ppgtt) {
2096                 seq_printf(m, "  no ppgtt for context %d\n",
2097                            ctx->user_handle);
2098                 return 0;
2099         }
2100
2101         if (i915_gem_context_is_default(ctx))
2102                 seq_puts(m, "  default context:\n");
2103         else
2104                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2105         ppgtt->debug_dump(ppgtt, m);
2106
2107         return 0;
2108 }
2109
2110 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2111 {
2112         struct drm_i915_private *dev_priv = dev->dev_private;
2113         struct intel_engine_cs *ring;
2114         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2115         int unused, i;
2116
2117         if (!ppgtt)
2118                 return;
2119
2120         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2121         seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2122         for_each_ring(ring, dev_priv, unused) {
2123                 seq_printf(m, "%s\n", ring->name);
2124                 for (i = 0; i < 4; i++) {
2125                         u32 offset = 0x270 + i * 8;
2126                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2127                         pdp <<= 32;
2128                         pdp |= I915_READ(ring->mmio_base + offset);
2129                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2130                 }
2131         }
2132 }
2133
2134 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2135 {
2136         struct drm_i915_private *dev_priv = dev->dev_private;
2137         struct intel_engine_cs *ring;
2138         struct drm_file *file;
2139         int i;
2140
2141         if (INTEL_INFO(dev)->gen == 6)
2142                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2143
2144         for_each_ring(ring, dev_priv, i) {
2145                 seq_printf(m, "%s\n", ring->name);
2146                 if (INTEL_INFO(dev)->gen == 7)
2147                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2148                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2149                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2150                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2151         }
2152         if (dev_priv->mm.aliasing_ppgtt) {
2153                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2154
2155                 seq_puts(m, "aliasing PPGTT:\n");
2156                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
2157
2158                 ppgtt->debug_dump(ppgtt, m);
2159         }
2160
2161         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2162                 struct drm_i915_file_private *file_priv = file->driver_priv;
2163
2164                 seq_printf(m, "proc: %s\n",
2165                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2166                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2167         }
2168         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2169 }
2170
2171 static int i915_ppgtt_info(struct seq_file *m, void *data)
2172 {
2173         struct drm_info_node *node = m->private;
2174         struct drm_device *dev = node->minor->dev;
2175         struct drm_i915_private *dev_priv = dev->dev_private;
2176
2177         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2178         if (ret)
2179                 return ret;
2180         intel_runtime_pm_get(dev_priv);
2181
2182         if (INTEL_INFO(dev)->gen >= 8)
2183                 gen8_ppgtt_info(m, dev);
2184         else if (INTEL_INFO(dev)->gen >= 6)
2185                 gen6_ppgtt_info(m, dev);
2186
2187         intel_runtime_pm_put(dev_priv);
2188         mutex_unlock(&dev->struct_mutex);
2189
2190         return 0;
2191 }
2192
2193 static int i915_llc(struct seq_file *m, void *data)
2194 {
2195         struct drm_info_node *node = m->private;
2196         struct drm_device *dev = node->minor->dev;
2197         struct drm_i915_private *dev_priv = dev->dev_private;
2198
2199         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2200         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2201         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2202
2203         return 0;
2204 }
2205
2206 static int i915_edp_psr_status(struct seq_file *m, void *data)
2207 {
2208         struct drm_info_node *node = m->private;
2209         struct drm_device *dev = node->minor->dev;
2210         struct drm_i915_private *dev_priv = dev->dev_private;
2211         u32 psrperf = 0;
2212         u32 stat[3];
2213         enum pipe pipe;
2214         bool enabled = false;
2215
2216         intel_runtime_pm_get(dev_priv);
2217
2218         mutex_lock(&dev_priv->psr.lock);
2219         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2220         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2221         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2222         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2223         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2224                    dev_priv->psr.busy_frontbuffer_bits);
2225         seq_printf(m, "Re-enable work scheduled: %s\n",
2226                    yesno(work_busy(&dev_priv->psr.work.work)));
2227
2228         if (HAS_PSR(dev)) {
2229                 if (HAS_DDI(dev))
2230                         enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2231                 else {
2232                         for_each_pipe(dev_priv, pipe) {
2233                                 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2234                                         VLV_EDP_PSR_CURR_STATE_MASK;
2235                                 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2236                                     (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2237                                         enabled = true;
2238                         }
2239                 }
2240         }
2241         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2242
2243         if (!HAS_DDI(dev))
2244                 for_each_pipe(dev_priv, pipe) {
2245                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2246                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2247                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2248                 }
2249         seq_puts(m, "\n");
2250
2251         seq_printf(m, "Link standby: %s\n",
2252                    yesno((bool)dev_priv->psr.link_standby));
2253
2254         /* CHV PSR has no kind of performance counter */
2255         if (HAS_PSR(dev) && HAS_DDI(dev)) {
2256                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2257                         EDP_PSR_PERF_CNT_MASK;
2258
2259                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2260         }
2261         mutex_unlock(&dev_priv->psr.lock);
2262
2263         intel_runtime_pm_put(dev_priv);
2264         return 0;
2265 }
2266
2267 static int i915_sink_crc(struct seq_file *m, void *data)
2268 {
2269         struct drm_info_node *node = m->private;
2270         struct drm_device *dev = node->minor->dev;
2271         struct intel_encoder *encoder;
2272         struct intel_connector *connector;
2273         struct intel_dp *intel_dp = NULL;
2274         int ret;
2275         u8 crc[6];
2276
2277         drm_modeset_lock_all(dev);
2278         list_for_each_entry(connector, &dev->mode_config.connector_list,
2279                             base.head) {
2280
2281                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2282                         continue;
2283
2284                 if (!connector->base.encoder)
2285                         continue;
2286
2287                 encoder = to_intel_encoder(connector->base.encoder);
2288                 if (encoder->type != INTEL_OUTPUT_EDP)
2289                         continue;
2290
2291                 intel_dp = enc_to_intel_dp(&encoder->base);
2292
2293                 ret = intel_dp_sink_crc(intel_dp, crc);
2294                 if (ret)
2295                         goto out;
2296
2297                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2298                            crc[0], crc[1], crc[2],
2299                            crc[3], crc[4], crc[5]);
2300                 goto out;
2301         }
2302         ret = -ENODEV;
2303 out:
2304         drm_modeset_unlock_all(dev);
2305         return ret;
2306 }
2307
2308 static int i915_energy_uJ(struct seq_file *m, void *data)
2309 {
2310         struct drm_info_node *node = m->private;
2311         struct drm_device *dev = node->minor->dev;
2312         struct drm_i915_private *dev_priv = dev->dev_private;
2313         u64 power;
2314         u32 units;
2315
2316         if (INTEL_INFO(dev)->gen < 6)
2317                 return -ENODEV;
2318
2319         intel_runtime_pm_get(dev_priv);
2320
2321         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2322         power = (power & 0x1f00) >> 8;
2323         units = 1000000 / (1 << power); /* convert to uJ */
2324         power = I915_READ(MCH_SECP_NRG_STTS);
2325         power *= units;
2326
2327         intel_runtime_pm_put(dev_priv);
2328
2329         seq_printf(m, "%llu", (long long unsigned)power);
2330
2331         return 0;
2332 }
2333
2334 static int i915_pc8_status(struct seq_file *m, void *unused)
2335 {
2336         struct drm_info_node *node = m->private;
2337         struct drm_device *dev = node->minor->dev;
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339
2340         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2341                 seq_puts(m, "not supported\n");
2342                 return 0;
2343         }
2344
2345         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2346         seq_printf(m, "IRQs disabled: %s\n",
2347                    yesno(!intel_irqs_enabled(dev_priv)));
2348
2349         return 0;
2350 }
2351
2352 static const char *power_domain_str(enum intel_display_power_domain domain)
2353 {
2354         switch (domain) {
2355         case POWER_DOMAIN_PIPE_A:
2356                 return "PIPE_A";
2357         case POWER_DOMAIN_PIPE_B:
2358                 return "PIPE_B";
2359         case POWER_DOMAIN_PIPE_C:
2360                 return "PIPE_C";
2361         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2362                 return "PIPE_A_PANEL_FITTER";
2363         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2364                 return "PIPE_B_PANEL_FITTER";
2365         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2366                 return "PIPE_C_PANEL_FITTER";
2367         case POWER_DOMAIN_TRANSCODER_A:
2368                 return "TRANSCODER_A";
2369         case POWER_DOMAIN_TRANSCODER_B:
2370                 return "TRANSCODER_B";
2371         case POWER_DOMAIN_TRANSCODER_C:
2372                 return "TRANSCODER_C";
2373         case POWER_DOMAIN_TRANSCODER_EDP:
2374                 return "TRANSCODER_EDP";
2375         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2376                 return "PORT_DDI_A_2_LANES";
2377         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2378                 return "PORT_DDI_A_4_LANES";
2379         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2380                 return "PORT_DDI_B_2_LANES";
2381         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2382                 return "PORT_DDI_B_4_LANES";
2383         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2384                 return "PORT_DDI_C_2_LANES";
2385         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2386                 return "PORT_DDI_C_4_LANES";
2387         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2388                 return "PORT_DDI_D_2_LANES";
2389         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2390                 return "PORT_DDI_D_4_LANES";
2391         case POWER_DOMAIN_PORT_DSI:
2392                 return "PORT_DSI";
2393         case POWER_DOMAIN_PORT_CRT:
2394                 return "PORT_CRT";
2395         case POWER_DOMAIN_PORT_OTHER:
2396                 return "PORT_OTHER";
2397         case POWER_DOMAIN_VGA:
2398                 return "VGA";
2399         case POWER_DOMAIN_AUDIO:
2400                 return "AUDIO";
2401         case POWER_DOMAIN_PLLS:
2402                 return "PLLS";
2403         case POWER_DOMAIN_INIT:
2404                 return "INIT";
2405         default:
2406                 MISSING_CASE(domain);
2407                 return "?";
2408         }
2409 }
2410
2411 static int i915_power_domain_info(struct seq_file *m, void *unused)
2412 {
2413         struct drm_info_node *node = m->private;
2414         struct drm_device *dev = node->minor->dev;
2415         struct drm_i915_private *dev_priv = dev->dev_private;
2416         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2417         int i;
2418
2419         mutex_lock(&power_domains->lock);
2420
2421         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2422         for (i = 0; i < power_domains->power_well_count; i++) {
2423                 struct i915_power_well *power_well;
2424                 enum intel_display_power_domain power_domain;
2425
2426                 power_well = &power_domains->power_wells[i];
2427                 seq_printf(m, "%-25s %d\n", power_well->name,
2428                            power_well->count);
2429
2430                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2431                      power_domain++) {
2432                         if (!(BIT(power_domain) & power_well->domains))
2433                                 continue;
2434
2435                         seq_printf(m, "  %-23s %d\n",
2436                                  power_domain_str(power_domain),
2437                                  power_domains->domain_use_count[power_domain]);
2438                 }
2439         }
2440
2441         mutex_unlock(&power_domains->lock);
2442
2443         return 0;
2444 }
2445
2446 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2447                                  struct drm_display_mode *mode)
2448 {
2449         int i;
2450
2451         for (i = 0; i < tabs; i++)
2452                 seq_putc(m, '\t');
2453
2454         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2455                    mode->base.id, mode->name,
2456                    mode->vrefresh, mode->clock,
2457                    mode->hdisplay, mode->hsync_start,
2458                    mode->hsync_end, mode->htotal,
2459                    mode->vdisplay, mode->vsync_start,
2460                    mode->vsync_end, mode->vtotal,
2461                    mode->type, mode->flags);
2462 }
2463
2464 static void intel_encoder_info(struct seq_file *m,
2465                                struct intel_crtc *intel_crtc,
2466                                struct intel_encoder *intel_encoder)
2467 {
2468         struct drm_info_node *node = m->private;
2469         struct drm_device *dev = node->minor->dev;
2470         struct drm_crtc *crtc = &intel_crtc->base;
2471         struct intel_connector *intel_connector;
2472         struct drm_encoder *encoder;
2473
2474         encoder = &intel_encoder->base;
2475         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2476                    encoder->base.id, encoder->name);
2477         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2478                 struct drm_connector *connector = &intel_connector->base;
2479                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2480                            connector->base.id,
2481                            connector->name,
2482                            drm_get_connector_status_name(connector->status));
2483                 if (connector->status == connector_status_connected) {
2484                         struct drm_display_mode *mode = &crtc->mode;
2485                         seq_printf(m, ", mode:\n");
2486                         intel_seq_print_mode(m, 2, mode);
2487                 } else {
2488                         seq_putc(m, '\n');
2489                 }
2490         }
2491 }
2492
2493 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2494 {
2495         struct drm_info_node *node = m->private;
2496         struct drm_device *dev = node->minor->dev;
2497         struct drm_crtc *crtc = &intel_crtc->base;
2498         struct intel_encoder *intel_encoder;
2499
2500         if (crtc->primary->fb)
2501                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2502                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2503                            crtc->primary->fb->width, crtc->primary->fb->height);
2504         else
2505                 seq_puts(m, "\tprimary plane disabled\n");
2506         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2507                 intel_encoder_info(m, intel_crtc, intel_encoder);
2508 }
2509
2510 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2511 {
2512         struct drm_display_mode *mode = panel->fixed_mode;
2513
2514         seq_printf(m, "\tfixed mode:\n");
2515         intel_seq_print_mode(m, 2, mode);
2516 }
2517
2518 static void intel_dp_info(struct seq_file *m,
2519                           struct intel_connector *intel_connector)
2520 {
2521         struct intel_encoder *intel_encoder = intel_connector->encoder;
2522         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2523
2524         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2525         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2526                    "no");
2527         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2528                 intel_panel_info(m, &intel_connector->panel);
2529 }
2530
2531 static void intel_hdmi_info(struct seq_file *m,
2532                             struct intel_connector *intel_connector)
2533 {
2534         struct intel_encoder *intel_encoder = intel_connector->encoder;
2535         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2536
2537         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2538                    "no");
2539 }
2540
2541 static void intel_lvds_info(struct seq_file *m,
2542                             struct intel_connector *intel_connector)
2543 {
2544         intel_panel_info(m, &intel_connector->panel);
2545 }
2546
2547 static void intel_connector_info(struct seq_file *m,
2548                                  struct drm_connector *connector)
2549 {
2550         struct intel_connector *intel_connector = to_intel_connector(connector);
2551         struct intel_encoder *intel_encoder = intel_connector->encoder;
2552         struct drm_display_mode *mode;
2553
2554         seq_printf(m, "connector %d: type %s, status: %s\n",
2555                    connector->base.id, connector->name,
2556                    drm_get_connector_status_name(connector->status));
2557         if (connector->status == connector_status_connected) {
2558                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2559                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2560                            connector->display_info.width_mm,
2561                            connector->display_info.height_mm);
2562                 seq_printf(m, "\tsubpixel order: %s\n",
2563                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2564                 seq_printf(m, "\tCEA rev: %d\n",
2565                            connector->display_info.cea_rev);
2566         }
2567         if (intel_encoder) {
2568                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2569                     intel_encoder->type == INTEL_OUTPUT_EDP)
2570                         intel_dp_info(m, intel_connector);
2571                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2572                         intel_hdmi_info(m, intel_connector);
2573                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2574                         intel_lvds_info(m, intel_connector);
2575         }
2576
2577         seq_printf(m, "\tmodes:\n");
2578         list_for_each_entry(mode, &connector->modes, head)
2579                 intel_seq_print_mode(m, 2, mode);
2580 }
2581
2582 static bool cursor_active(struct drm_device *dev, int pipe)
2583 {
2584         struct drm_i915_private *dev_priv = dev->dev_private;
2585         u32 state;
2586
2587         if (IS_845G(dev) || IS_I865G(dev))
2588                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2589         else
2590                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2591
2592         return state;
2593 }
2594
2595 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2596 {
2597         struct drm_i915_private *dev_priv = dev->dev_private;
2598         u32 pos;
2599
2600         pos = I915_READ(CURPOS(pipe));
2601
2602         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2603         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2604                 *x = -*x;
2605
2606         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2607         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2608                 *y = -*y;
2609
2610         return cursor_active(dev, pipe);
2611 }
2612
2613 static int i915_display_info(struct seq_file *m, void *unused)
2614 {
2615         struct drm_info_node *node = m->private;
2616         struct drm_device *dev = node->minor->dev;
2617         struct drm_i915_private *dev_priv = dev->dev_private;
2618         struct intel_crtc *crtc;
2619         struct drm_connector *connector;
2620
2621         intel_runtime_pm_get(dev_priv);
2622         drm_modeset_lock_all(dev);
2623         seq_printf(m, "CRTC info\n");
2624         seq_printf(m, "---------\n");
2625         for_each_intel_crtc(dev, crtc) {
2626                 bool active;
2627                 int x, y;
2628
2629                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2630                            crtc->base.base.id, pipe_name(crtc->pipe),
2631                            yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
2632                 if (crtc->active) {
2633                         intel_crtc_info(m, crtc);
2634
2635                         active = cursor_position(dev, crtc->pipe, &x, &y);
2636                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2637                                    yesno(crtc->cursor_base),
2638                                    x, y, crtc->cursor_width, crtc->cursor_height,
2639                                    crtc->cursor_addr, yesno(active));
2640                 }
2641
2642                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2643                            yesno(!crtc->cpu_fifo_underrun_disabled),
2644                            yesno(!crtc->pch_fifo_underrun_disabled));
2645         }
2646
2647         seq_printf(m, "\n");
2648         seq_printf(m, "Connector info\n");
2649         seq_printf(m, "--------------\n");
2650         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2651                 intel_connector_info(m, connector);
2652         }
2653         drm_modeset_unlock_all(dev);
2654         intel_runtime_pm_put(dev_priv);
2655
2656         return 0;
2657 }
2658
2659 static int i915_semaphore_status(struct seq_file *m, void *unused)
2660 {
2661         struct drm_info_node *node = (struct drm_info_node *) m->private;
2662         struct drm_device *dev = node->minor->dev;
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         struct intel_engine_cs *ring;
2665         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2666         int i, j, ret;
2667
2668         if (!i915_semaphore_is_enabled(dev)) {
2669                 seq_puts(m, "Semaphores are disabled\n");
2670                 return 0;
2671         }
2672
2673         ret = mutex_lock_interruptible(&dev->struct_mutex);
2674         if (ret)
2675                 return ret;
2676         intel_runtime_pm_get(dev_priv);
2677
2678         if (IS_BROADWELL(dev)) {
2679                 struct page *page;
2680                 uint64_t *seqno;
2681
2682                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2683
2684                 seqno = (uint64_t *)kmap_atomic(page);
2685                 for_each_ring(ring, dev_priv, i) {
2686                         uint64_t offset;
2687
2688                         seq_printf(m, "%s\n", ring->name);
2689
2690                         seq_puts(m, "  Last signal:");
2691                         for (j = 0; j < num_rings; j++) {
2692                                 offset = i * I915_NUM_RINGS + j;
2693                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2694                                            seqno[offset], offset * 8);
2695                         }
2696                         seq_putc(m, '\n');
2697
2698                         seq_puts(m, "  Last wait:  ");
2699                         for (j = 0; j < num_rings; j++) {
2700                                 offset = i + (j * I915_NUM_RINGS);
2701                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2702                                            seqno[offset], offset * 8);
2703                         }
2704                         seq_putc(m, '\n');
2705
2706                 }
2707                 kunmap_atomic(seqno);
2708         } else {
2709                 seq_puts(m, "  Last signal:");
2710                 for_each_ring(ring, dev_priv, i)
2711                         for (j = 0; j < num_rings; j++)
2712                                 seq_printf(m, "0x%08x\n",
2713                                            I915_READ(ring->semaphore.mbox.signal[j]));
2714                 seq_putc(m, '\n');
2715         }
2716
2717         seq_puts(m, "\nSync seqno:\n");
2718         for_each_ring(ring, dev_priv, i) {
2719                 for (j = 0; j < num_rings; j++) {
2720                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2721                 }
2722                 seq_putc(m, '\n');
2723         }
2724         seq_putc(m, '\n');
2725
2726         intel_runtime_pm_put(dev_priv);
2727         mutex_unlock(&dev->struct_mutex);
2728         return 0;
2729 }
2730
2731 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2732 {
2733         struct drm_info_node *node = (struct drm_info_node *) m->private;
2734         struct drm_device *dev = node->minor->dev;
2735         struct drm_i915_private *dev_priv = dev->dev_private;
2736         int i;
2737
2738         drm_modeset_lock_all(dev);
2739         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2740                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2741
2742                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2743                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2744                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2745                 seq_printf(m, " tracked hardware state:\n");
2746                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2747                 seq_printf(m, " dpll_md: 0x%08x\n",
2748                            pll->config.hw_state.dpll_md);
2749                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2750                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2751                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2752         }
2753         drm_modeset_unlock_all(dev);
2754
2755         return 0;
2756 }
2757
2758 static int i915_wa_registers(struct seq_file *m, void *unused)
2759 {
2760         int i;
2761         int ret;
2762         struct drm_info_node *node = (struct drm_info_node *) m->private;
2763         struct drm_device *dev = node->minor->dev;
2764         struct drm_i915_private *dev_priv = dev->dev_private;
2765
2766         ret = mutex_lock_interruptible(&dev->struct_mutex);
2767         if (ret)
2768                 return ret;
2769
2770         intel_runtime_pm_get(dev_priv);
2771
2772         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2773         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2774                 u32 addr, mask, value, read;
2775                 bool ok;
2776
2777                 addr = dev_priv->workarounds.reg[i].addr;
2778                 mask = dev_priv->workarounds.reg[i].mask;
2779                 value = dev_priv->workarounds.reg[i].value;
2780                 read = I915_READ(addr);
2781                 ok = (value & mask) == (read & mask);
2782                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2783                            addr, value, mask, read, ok ? "OK" : "FAIL");
2784         }
2785
2786         intel_runtime_pm_put(dev_priv);
2787         mutex_unlock(&dev->struct_mutex);
2788
2789         return 0;
2790 }
2791
2792 static int i915_ddb_info(struct seq_file *m, void *unused)
2793 {
2794         struct drm_info_node *node = m->private;
2795         struct drm_device *dev = node->minor->dev;
2796         struct drm_i915_private *dev_priv = dev->dev_private;
2797         struct skl_ddb_allocation *ddb;
2798         struct skl_ddb_entry *entry;
2799         enum pipe pipe;
2800         int plane;
2801
2802         if (INTEL_INFO(dev)->gen < 9)
2803                 return 0;
2804
2805         drm_modeset_lock_all(dev);
2806
2807         ddb = &dev_priv->wm.skl_hw.ddb;
2808
2809         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2810
2811         for_each_pipe(dev_priv, pipe) {
2812                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2813
2814                 for_each_plane(pipe, plane) {
2815                         entry = &ddb->plane[pipe][plane];
2816                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2817                                    entry->start, entry->end,
2818                                    skl_ddb_entry_size(entry));
2819                 }
2820
2821                 entry = &ddb->cursor[pipe];
2822                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
2823                            entry->end, skl_ddb_entry_size(entry));
2824         }
2825
2826         drm_modeset_unlock_all(dev);
2827
2828         return 0;
2829 }
2830
2831 struct pipe_crc_info {
2832         const char *name;
2833         struct drm_device *dev;
2834         enum pipe pipe;
2835 };
2836
2837 static int i915_dp_mst_info(struct seq_file *m, void *unused)
2838 {
2839         struct drm_info_node *node = (struct drm_info_node *) m->private;
2840         struct drm_device *dev = node->minor->dev;
2841         struct drm_encoder *encoder;
2842         struct intel_encoder *intel_encoder;
2843         struct intel_digital_port *intel_dig_port;
2844         drm_modeset_lock_all(dev);
2845         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2846                 intel_encoder = to_intel_encoder(encoder);
2847                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2848                         continue;
2849                 intel_dig_port = enc_to_dig_port(encoder);
2850                 if (!intel_dig_port->dp.can_mst)
2851                         continue;
2852
2853                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2854         }
2855         drm_modeset_unlock_all(dev);
2856         return 0;
2857 }
2858
2859 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2860 {
2861         struct pipe_crc_info *info = inode->i_private;
2862         struct drm_i915_private *dev_priv = info->dev->dev_private;
2863         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2864
2865         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2866                 return -ENODEV;
2867
2868         spin_lock_irq(&pipe_crc->lock);
2869
2870         if (pipe_crc->opened) {
2871                 spin_unlock_irq(&pipe_crc->lock);
2872                 return -EBUSY; /* already open */
2873         }
2874
2875         pipe_crc->opened = true;
2876         filep->private_data = inode->i_private;
2877
2878         spin_unlock_irq(&pipe_crc->lock);
2879
2880         return 0;
2881 }
2882
2883 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2884 {
2885         struct pipe_crc_info *info = inode->i_private;
2886         struct drm_i915_private *dev_priv = info->dev->dev_private;
2887         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2888
2889         spin_lock_irq(&pipe_crc->lock);
2890         pipe_crc->opened = false;
2891         spin_unlock_irq(&pipe_crc->lock);
2892
2893         return 0;
2894 }
2895
2896 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2897 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2898 /* account for \'0' */
2899 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2900
2901 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2902 {
2903         assert_spin_locked(&pipe_crc->lock);
2904         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2905                         INTEL_PIPE_CRC_ENTRIES_NR);
2906 }
2907
2908 static ssize_t
2909 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2910                    loff_t *pos)
2911 {
2912         struct pipe_crc_info *info = filep->private_data;
2913         struct drm_device *dev = info->dev;
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2916         char buf[PIPE_CRC_BUFFER_LEN];
2917         int n_entries;
2918         ssize_t bytes_read;
2919
2920         /*
2921          * Don't allow user space to provide buffers not big enough to hold
2922          * a line of data.
2923          */
2924         if (count < PIPE_CRC_LINE_LEN)
2925                 return -EINVAL;
2926
2927         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2928                 return 0;
2929
2930         /* nothing to read */
2931         spin_lock_irq(&pipe_crc->lock);
2932         while (pipe_crc_data_count(pipe_crc) == 0) {
2933                 int ret;
2934
2935                 if (filep->f_flags & O_NONBLOCK) {
2936                         spin_unlock_irq(&pipe_crc->lock);
2937                         return -EAGAIN;
2938                 }
2939
2940                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2941                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2942                 if (ret) {
2943                         spin_unlock_irq(&pipe_crc->lock);
2944                         return ret;
2945                 }
2946         }
2947
2948         /* We now have one or more entries to read */
2949         n_entries = count / PIPE_CRC_LINE_LEN;
2950
2951         bytes_read = 0;
2952         while (n_entries > 0) {
2953                 struct intel_pipe_crc_entry *entry =
2954                         &pipe_crc->entries[pipe_crc->tail];
2955                 int ret;
2956
2957                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2958                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2959                         break;
2960
2961                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2962                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2963
2964                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2965                                        "%8u %8x %8x %8x %8x %8x\n",
2966                                        entry->frame, entry->crc[0],
2967                                        entry->crc[1], entry->crc[2],
2968                                        entry->crc[3], entry->crc[4]);
2969
2970                 spin_unlock_irq(&pipe_crc->lock);
2971
2972                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
2973                 if (ret == PIPE_CRC_LINE_LEN)
2974                         return -EFAULT;
2975
2976                 user_buf += PIPE_CRC_LINE_LEN;
2977                 n_entries--;
2978
2979                 spin_lock_irq(&pipe_crc->lock);
2980         }
2981
2982         spin_unlock_irq(&pipe_crc->lock);
2983
2984         return bytes_read;
2985 }
2986
2987 static const struct file_operations i915_pipe_crc_fops = {
2988         .owner = THIS_MODULE,
2989         .open = i915_pipe_crc_open,
2990         .read = i915_pipe_crc_read,
2991         .release = i915_pipe_crc_release,
2992 };
2993
2994 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2995         {
2996                 .name = "i915_pipe_A_crc",
2997                 .pipe = PIPE_A,
2998         },
2999         {
3000                 .name = "i915_pipe_B_crc",
3001                 .pipe = PIPE_B,
3002         },
3003         {
3004                 .name = "i915_pipe_C_crc",
3005                 .pipe = PIPE_C,
3006         },
3007 };
3008
3009 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3010                                 enum pipe pipe)
3011 {
3012         struct drm_device *dev = minor->dev;
3013         struct dentry *ent;
3014         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3015
3016         info->dev = dev;
3017         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3018                                   &i915_pipe_crc_fops);
3019         if (!ent)
3020                 return -ENOMEM;
3021
3022         return drm_add_fake_info_node(minor, ent, info);
3023 }
3024
3025 static const char * const pipe_crc_sources[] = {
3026         "none",
3027         "plane1",
3028         "plane2",
3029         "pf",
3030         "pipe",
3031         "TV",
3032         "DP-B",
3033         "DP-C",
3034         "DP-D",
3035         "auto",
3036 };
3037
3038 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3039 {
3040         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3041         return pipe_crc_sources[source];
3042 }
3043
3044 static int display_crc_ctl_show(struct seq_file *m, void *data)
3045 {
3046         struct drm_device *dev = m->private;
3047         struct drm_i915_private *dev_priv = dev->dev_private;
3048         int i;
3049
3050         for (i = 0; i < I915_MAX_PIPES; i++)
3051                 seq_printf(m, "%c %s\n", pipe_name(i),
3052                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3053
3054         return 0;
3055 }
3056
3057 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3058 {
3059         struct drm_device *dev = inode->i_private;
3060
3061         return single_open(file, display_crc_ctl_show, dev);
3062 }
3063
3064 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3065                                  uint32_t *val)
3066 {
3067         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3068                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3069
3070         switch (*source) {
3071         case INTEL_PIPE_CRC_SOURCE_PIPE:
3072                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3073                 break;
3074         case INTEL_PIPE_CRC_SOURCE_NONE:
3075                 *val = 0;
3076                 break;
3077         default:
3078                 return -EINVAL;
3079         }
3080
3081         return 0;
3082 }
3083
3084 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3085                                      enum intel_pipe_crc_source *source)
3086 {
3087         struct intel_encoder *encoder;
3088         struct intel_crtc *crtc;
3089         struct intel_digital_port *dig_port;
3090         int ret = 0;
3091
3092         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3093
3094         drm_modeset_lock_all(dev);
3095         for_each_intel_encoder(dev, encoder) {
3096                 if (!encoder->base.crtc)
3097                         continue;
3098
3099                 crtc = to_intel_crtc(encoder->base.crtc);
3100
3101                 if (crtc->pipe != pipe)
3102                         continue;
3103
3104                 switch (encoder->type) {
3105                 case INTEL_OUTPUT_TVOUT:
3106                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3107                         break;
3108                 case INTEL_OUTPUT_DISPLAYPORT:
3109                 case INTEL_OUTPUT_EDP:
3110                         dig_port = enc_to_dig_port(&encoder->base);
3111                         switch (dig_port->port) {
3112                         case PORT_B:
3113                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3114                                 break;
3115                         case PORT_C:
3116                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3117                                 break;
3118                         case PORT_D:
3119                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3120                                 break;
3121                         default:
3122                                 WARN(1, "nonexisting DP port %c\n",
3123                                      port_name(dig_port->port));
3124                                 break;
3125                         }
3126                         break;
3127                 default:
3128                         break;
3129                 }
3130         }
3131         drm_modeset_unlock_all(dev);
3132
3133         return ret;
3134 }
3135
3136 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3137                                 enum pipe pipe,
3138                                 enum intel_pipe_crc_source *source,
3139                                 uint32_t *val)
3140 {
3141         struct drm_i915_private *dev_priv = dev->dev_private;
3142         bool need_stable_symbols = false;
3143
3144         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3145                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3146                 if (ret)
3147                         return ret;
3148         }
3149
3150         switch (*source) {
3151         case INTEL_PIPE_CRC_SOURCE_PIPE:
3152                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3153                 break;
3154         case INTEL_PIPE_CRC_SOURCE_DP_B:
3155                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3156                 need_stable_symbols = true;
3157                 break;
3158         case INTEL_PIPE_CRC_SOURCE_DP_C:
3159                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3160                 need_stable_symbols = true;
3161                 break;
3162         case INTEL_PIPE_CRC_SOURCE_DP_D:
3163                 if (!IS_CHERRYVIEW(dev))
3164                         return -EINVAL;
3165                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3166                 need_stable_symbols = true;
3167                 break;
3168         case INTEL_PIPE_CRC_SOURCE_NONE:
3169                 *val = 0;
3170                 break;
3171         default:
3172                 return -EINVAL;
3173         }
3174
3175         /*
3176          * When the pipe CRC tap point is after the transcoders we need
3177          * to tweak symbol-level features to produce a deterministic series of
3178          * symbols for a given frame. We need to reset those features only once
3179          * a frame (instead of every nth symbol):
3180          *   - DC-balance: used to ensure a better clock recovery from the data
3181          *     link (SDVO)
3182          *   - DisplayPort scrambling: used for EMI reduction
3183          */
3184         if (need_stable_symbols) {
3185                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3186
3187                 tmp |= DC_BALANCE_RESET_VLV;
3188                 switch (pipe) {
3189                 case PIPE_A:
3190                         tmp |= PIPE_A_SCRAMBLE_RESET;
3191                         break;
3192                 case PIPE_B:
3193                         tmp |= PIPE_B_SCRAMBLE_RESET;
3194                         break;
3195                 case PIPE_C:
3196                         tmp |= PIPE_C_SCRAMBLE_RESET;
3197                         break;
3198                 default:
3199                         return -EINVAL;
3200                 }
3201                 I915_WRITE(PORT_DFT2_G4X, tmp);
3202         }
3203
3204         return 0;
3205 }
3206
3207 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3208                                  enum pipe pipe,
3209                                  enum intel_pipe_crc_source *source,
3210                                  uint32_t *val)
3211 {
3212         struct drm_i915_private *dev_priv = dev->dev_private;
3213         bool need_stable_symbols = false;
3214
3215         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3216                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3217                 if (ret)
3218                         return ret;
3219         }
3220
3221         switch (*source) {
3222         case INTEL_PIPE_CRC_SOURCE_PIPE:
3223                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3224                 break;
3225         case INTEL_PIPE_CRC_SOURCE_TV:
3226                 if (!SUPPORTS_TV(dev))
3227                         return -EINVAL;
3228                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3229                 break;
3230         case INTEL_PIPE_CRC_SOURCE_DP_B:
3231                 if (!IS_G4X(dev))
3232                         return -EINVAL;
3233                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3234                 need_stable_symbols = true;
3235                 break;
3236         case INTEL_PIPE_CRC_SOURCE_DP_C:
3237                 if (!IS_G4X(dev))
3238                         return -EINVAL;
3239                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3240                 need_stable_symbols = true;
3241                 break;
3242         case INTEL_PIPE_CRC_SOURCE_DP_D:
3243                 if (!IS_G4X(dev))
3244                         return -EINVAL;
3245                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3246                 need_stable_symbols = true;
3247                 break;
3248         case INTEL_PIPE_CRC_SOURCE_NONE:
3249                 *val = 0;
3250                 break;
3251         default:
3252                 return -EINVAL;
3253         }
3254
3255         /*
3256          * When the pipe CRC tap point is after the transcoders we need
3257          * to tweak symbol-level features to produce a deterministic series of
3258          * symbols for a given frame. We need to reset those features only once
3259          * a frame (instead of every nth symbol):
3260          *   - DC-balance: used to ensure a better clock recovery from the data
3261          *     link (SDVO)
3262          *   - DisplayPort scrambling: used for EMI reduction
3263          */
3264         if (need_stable_symbols) {
3265                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3266
3267                 WARN_ON(!IS_G4X(dev));
3268
3269                 I915_WRITE(PORT_DFT_I9XX,
3270                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3271
3272                 if (pipe == PIPE_A)
3273                         tmp |= PIPE_A_SCRAMBLE_RESET;
3274                 else
3275                         tmp |= PIPE_B_SCRAMBLE_RESET;
3276
3277                 I915_WRITE(PORT_DFT2_G4X, tmp);
3278         }
3279
3280         return 0;
3281 }
3282
3283 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3284                                          enum pipe pipe)
3285 {
3286         struct drm_i915_private *dev_priv = dev->dev_private;
3287         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3288
3289         switch (pipe) {
3290         case PIPE_A:
3291                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3292                 break;
3293         case PIPE_B:
3294                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3295                 break;
3296         case PIPE_C:
3297                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3298                 break;
3299         default:
3300                 return;
3301         }
3302         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3303                 tmp &= ~DC_BALANCE_RESET_VLV;
3304         I915_WRITE(PORT_DFT2_G4X, tmp);
3305
3306 }
3307
3308 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3309                                          enum pipe pipe)
3310 {
3311         struct drm_i915_private *dev_priv = dev->dev_private;
3312         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3313
3314         if (pipe == PIPE_A)
3315                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3316         else
3317                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3318         I915_WRITE(PORT_DFT2_G4X, tmp);
3319
3320         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3321                 I915_WRITE(PORT_DFT_I9XX,
3322                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3323         }
3324 }
3325
3326 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3327                                 uint32_t *val)
3328 {
3329         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3330                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3331
3332         switch (*source) {
3333         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3334                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3335                 break;
3336         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3337                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3338                 break;
3339         case INTEL_PIPE_CRC_SOURCE_PIPE:
3340                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3341                 break;
3342         case INTEL_PIPE_CRC_SOURCE_NONE:
3343                 *val = 0;
3344                 break;
3345         default:
3346                 return -EINVAL;
3347         }
3348
3349         return 0;
3350 }
3351
3352 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3353 {
3354         struct drm_i915_private *dev_priv = dev->dev_private;
3355         struct intel_crtc *crtc =
3356                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3357
3358         drm_modeset_lock_all(dev);
3359         /*
3360          * If we use the eDP transcoder we need to make sure that we don't
3361          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3362          * relevant on hsw with pipe A when using the always-on power well
3363          * routing.
3364          */
3365         if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
3366             !crtc->config.pch_pfit.enabled) {
3367                 crtc->config.pch_pfit.force_thru = true;
3368
3369                 intel_display_power_get(dev_priv,
3370                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3371
3372                 dev_priv->display.crtc_disable(&crtc->base);
3373                 dev_priv->display.crtc_enable(&crtc->base);
3374         }
3375         drm_modeset_unlock_all(dev);
3376 }
3377
3378 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3379 {
3380         struct drm_i915_private *dev_priv = dev->dev_private;
3381         struct intel_crtc *crtc =
3382                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3383
3384         drm_modeset_lock_all(dev);
3385         /*
3386          * If we use the eDP transcoder we need to make sure that we don't
3387          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3388          * relevant on hsw with pipe A when using the always-on power well
3389          * routing.
3390          */
3391         if (crtc->config.pch_pfit.force_thru) {
3392                 crtc->config.pch_pfit.force_thru = false;
3393
3394                 dev_priv->display.crtc_disable(&crtc->base);
3395                 dev_priv->display.crtc_enable(&crtc->base);
3396
3397                 intel_display_power_put(dev_priv,
3398                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3399         }
3400         drm_modeset_unlock_all(dev);
3401 }
3402
3403 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3404                                 enum pipe pipe,
3405                                 enum intel_pipe_crc_source *source,
3406                                 uint32_t *val)
3407 {
3408         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3409                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3410
3411         switch (*source) {
3412         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3413                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3414                 break;
3415         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3416                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3417                 break;
3418         case INTEL_PIPE_CRC_SOURCE_PF:
3419                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3420                         hsw_trans_edp_pipe_A_crc_wa(dev);
3421
3422                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3423                 break;
3424         case INTEL_PIPE_CRC_SOURCE_NONE:
3425                 *val = 0;
3426                 break;
3427         default:
3428                 return -EINVAL;
3429         }
3430
3431         return 0;
3432 }
3433
3434 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3435                                enum intel_pipe_crc_source source)
3436 {
3437         struct drm_i915_private *dev_priv = dev->dev_private;
3438         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3439         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3440                                                                         pipe));
3441         u32 val = 0; /* shut up gcc */
3442         int ret;
3443
3444         if (pipe_crc->source == source)
3445                 return 0;
3446
3447         /* forbid changing the source without going back to 'none' */
3448         if (pipe_crc->source && source)
3449                 return -EINVAL;
3450
3451         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3452                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3453                 return -EIO;
3454         }
3455
3456         if (IS_GEN2(dev))
3457                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3458         else if (INTEL_INFO(dev)->gen < 5)
3459                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3460         else if (IS_VALLEYVIEW(dev))
3461                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3462         else if (IS_GEN5(dev) || IS_GEN6(dev))
3463                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3464         else
3465                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3466
3467         if (ret != 0)
3468                 return ret;
3469
3470         /* none -> real source transition */
3471         if (source) {
3472                 struct intel_pipe_crc_entry *entries;
3473
3474                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3475                                  pipe_name(pipe), pipe_crc_source_name(source));
3476
3477                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3478                                   sizeof(pipe_crc->entries[0]),
3479                                   GFP_KERNEL);
3480                 if (!entries)
3481                         return -ENOMEM;
3482
3483                 /*
3484                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3485                  * enabled and disabled dynamically based on package C states,
3486                  * user space can't make reliable use of the CRCs, so let's just
3487                  * completely disable it.
3488                  */
3489                 hsw_disable_ips(crtc);
3490
3491                 spin_lock_irq(&pipe_crc->lock);
3492                 kfree(pipe_crc->entries);
3493                 pipe_crc->entries = entries;
3494                 pipe_crc->head = 0;
3495                 pipe_crc->tail = 0;
3496                 spin_unlock_irq(&pipe_crc->lock);
3497         }
3498
3499         pipe_crc->source = source;
3500
3501         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3502         POSTING_READ(PIPE_CRC_CTL(pipe));
3503
3504         /* real source -> none transition */
3505         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3506                 struct intel_pipe_crc_entry *entries;
3507                 struct intel_crtc *crtc =
3508                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3509
3510                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3511                                  pipe_name(pipe));
3512
3513                 drm_modeset_lock(&crtc->base.mutex, NULL);
3514                 if (crtc->active)
3515                         intel_wait_for_vblank(dev, pipe);
3516                 drm_modeset_unlock(&crtc->base.mutex);
3517
3518                 spin_lock_irq(&pipe_crc->lock);
3519                 entries = pipe_crc->entries;
3520                 pipe_crc->entries = NULL;
3521                 pipe_crc->head = 0;
3522                 pipe_crc->tail = 0;
3523                 spin_unlock_irq(&pipe_crc->lock);
3524
3525                 kfree(entries);
3526
3527                 if (IS_G4X(dev))
3528                         g4x_undo_pipe_scramble_reset(dev, pipe);
3529                 else if (IS_VALLEYVIEW(dev))
3530                         vlv_undo_pipe_scramble_reset(dev, pipe);
3531                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3532                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3533
3534                 hsw_enable_ips(crtc);
3535         }
3536
3537         return 0;
3538 }
3539
3540 /*
3541  * Parse pipe CRC command strings:
3542  *   command: wsp* object wsp+ name wsp+ source wsp*
3543  *   object: 'pipe'
3544  *   name: (A | B | C)
3545  *   source: (none | plane1 | plane2 | pf)
3546  *   wsp: (#0x20 | #0x9 | #0xA)+
3547  *
3548  * eg.:
3549  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3550  *  "pipe A none"    ->  Stop CRC
3551  */
3552 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3553 {
3554         int n_words = 0;
3555
3556         while (*buf) {
3557                 char *end;
3558
3559                 /* skip leading white space */
3560                 buf = skip_spaces(buf);
3561                 if (!*buf)
3562                         break;  /* end of buffer */
3563
3564                 /* find end of word */
3565                 for (end = buf; *end && !isspace(*end); end++)
3566                         ;
3567
3568                 if (n_words == max_words) {
3569                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3570                                          max_words);
3571                         return -EINVAL; /* ran out of words[] before bytes */
3572                 }
3573
3574                 if (*end)
3575                         *end++ = '\0';
3576                 words[n_words++] = buf;
3577                 buf = end;
3578         }
3579
3580         return n_words;
3581 }
3582
3583 enum intel_pipe_crc_object {
3584         PIPE_CRC_OBJECT_PIPE,
3585 };
3586
3587 static const char * const pipe_crc_objects[] = {
3588         "pipe",
3589 };
3590
3591 static int
3592 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3593 {
3594         int i;
3595
3596         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3597                 if (!strcmp(buf, pipe_crc_objects[i])) {
3598                         *o = i;
3599                         return 0;
3600                     }
3601
3602         return -EINVAL;
3603 }
3604
3605 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3606 {
3607         const char name = buf[0];
3608
3609         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3610                 return -EINVAL;
3611
3612         *pipe = name - 'A';
3613
3614         return 0;
3615 }
3616
3617 static int
3618 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3619 {
3620         int i;
3621
3622         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3623                 if (!strcmp(buf, pipe_crc_sources[i])) {
3624                         *s = i;
3625                         return 0;
3626                     }
3627
3628         return -EINVAL;
3629 }
3630
3631 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3632 {
3633 #define N_WORDS 3
3634         int n_words;
3635         char *words[N_WORDS];
3636         enum pipe pipe;
3637         enum intel_pipe_crc_object object;
3638         enum intel_pipe_crc_source source;
3639
3640         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3641         if (n_words != N_WORDS) {
3642                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3643                                  N_WORDS);
3644                 return -EINVAL;
3645         }
3646
3647         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3648                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3649                 return -EINVAL;
3650         }
3651
3652         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3653                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3654                 return -EINVAL;
3655         }
3656
3657         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3658                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3659                 return -EINVAL;
3660         }
3661
3662         return pipe_crc_set_source(dev, pipe, source);
3663 }
3664
3665 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3666                                      size_t len, loff_t *offp)
3667 {
3668         struct seq_file *m = file->private_data;
3669         struct drm_device *dev = m->private;
3670         char *tmpbuf;
3671         int ret;
3672
3673         if (len == 0)
3674                 return 0;
3675
3676         if (len > PAGE_SIZE - 1) {
3677                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3678                                  PAGE_SIZE);
3679                 return -E2BIG;
3680         }
3681
3682         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3683         if (!tmpbuf)
3684                 return -ENOMEM;
3685
3686         if (copy_from_user(tmpbuf, ubuf, len)) {
3687                 ret = -EFAULT;
3688                 goto out;
3689         }
3690         tmpbuf[len] = '\0';
3691
3692         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3693
3694 out:
3695         kfree(tmpbuf);
3696         if (ret < 0)
3697                 return ret;
3698
3699         *offp += len;
3700         return len;
3701 }
3702
3703 static const struct file_operations i915_display_crc_ctl_fops = {
3704         .owner = THIS_MODULE,
3705         .open = display_crc_ctl_open,
3706         .read = seq_read,
3707         .llseek = seq_lseek,
3708         .release = single_release,
3709         .write = display_crc_ctl_write
3710 };
3711
3712 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3713 {
3714         struct drm_device *dev = m->private;
3715         int num_levels = ilk_wm_max_level(dev) + 1;
3716         int level;
3717
3718         drm_modeset_lock_all(dev);
3719
3720         for (level = 0; level < num_levels; level++) {
3721                 unsigned int latency = wm[level];
3722
3723                 /*
3724                  * - WM1+ latency values in 0.5us units
3725                  * - latencies are in us on gen9
3726                  */
3727                 if (INTEL_INFO(dev)->gen >= 9)
3728                         latency *= 10;
3729                 else if (level > 0)
3730                         latency *= 5;
3731
3732                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3733                            level, wm[level], latency / 10, latency % 10);
3734         }
3735
3736         drm_modeset_unlock_all(dev);
3737 }
3738
3739 static int pri_wm_latency_show(struct seq_file *m, void *data)
3740 {
3741         struct drm_device *dev = m->private;
3742         struct drm_i915_private *dev_priv = dev->dev_private;
3743         const uint16_t *latencies;
3744
3745         if (INTEL_INFO(dev)->gen >= 9)
3746                 latencies = dev_priv->wm.skl_latency;
3747         else
3748                 latencies = to_i915(dev)->wm.pri_latency;
3749
3750         wm_latency_show(m, latencies);
3751
3752         return 0;
3753 }
3754
3755 static int spr_wm_latency_show(struct seq_file *m, void *data)
3756 {
3757         struct drm_device *dev = m->private;
3758         struct drm_i915_private *dev_priv = dev->dev_private;
3759         const uint16_t *latencies;
3760
3761         if (INTEL_INFO(dev)->gen >= 9)
3762                 latencies = dev_priv->wm.skl_latency;
3763         else
3764                 latencies = to_i915(dev)->wm.spr_latency;
3765
3766         wm_latency_show(m, latencies);
3767
3768         return 0;
3769 }
3770
3771 static int cur_wm_latency_show(struct seq_file *m, void *data)
3772 {
3773         struct drm_device *dev = m->private;
3774         struct drm_i915_private *dev_priv = dev->dev_private;
3775         const uint16_t *latencies;
3776
3777         if (INTEL_INFO(dev)->gen >= 9)
3778                 latencies = dev_priv->wm.skl_latency;
3779         else
3780                 latencies = to_i915(dev)->wm.cur_latency;
3781
3782         wm_latency_show(m, latencies);
3783
3784         return 0;
3785 }
3786
3787 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3788 {
3789         struct drm_device *dev = inode->i_private;
3790
3791         if (HAS_GMCH_DISPLAY(dev))
3792                 return -ENODEV;
3793
3794         return single_open(file, pri_wm_latency_show, dev);
3795 }
3796
3797 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3798 {
3799         struct drm_device *dev = inode->i_private;
3800
3801         if (HAS_GMCH_DISPLAY(dev))
3802                 return -ENODEV;
3803
3804         return single_open(file, spr_wm_latency_show, dev);
3805 }
3806
3807 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3808 {
3809         struct drm_device *dev = inode->i_private;
3810
3811         if (HAS_GMCH_DISPLAY(dev))
3812                 return -ENODEV;
3813
3814         return single_open(file, cur_wm_latency_show, dev);
3815 }
3816
3817 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3818                                 size_t len, loff_t *offp, uint16_t wm[8])
3819 {
3820         struct seq_file *m = file->private_data;
3821         struct drm_device *dev = m->private;
3822         uint16_t new[8] = { 0 };
3823         int num_levels = ilk_wm_max_level(dev) + 1;
3824         int level;
3825         int ret;
3826         char tmp[32];
3827
3828         if (len >= sizeof(tmp))
3829                 return -EINVAL;
3830
3831         if (copy_from_user(tmp, ubuf, len))
3832                 return -EFAULT;
3833
3834         tmp[len] = '\0';
3835
3836         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3837                      &new[0], &new[1], &new[2], &new[3],
3838                      &new[4], &new[5], &new[6], &new[7]);
3839         if (ret != num_levels)
3840                 return -EINVAL;
3841
3842         drm_modeset_lock_all(dev);
3843
3844         for (level = 0; level < num_levels; level++)
3845                 wm[level] = new[level];
3846
3847         drm_modeset_unlock_all(dev);
3848
3849         return len;
3850 }
3851
3852
3853 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3854                                     size_t len, loff_t *offp)
3855 {
3856         struct seq_file *m = file->private_data;
3857         struct drm_device *dev = m->private;
3858         struct drm_i915_private *dev_priv = dev->dev_private;
3859         uint16_t *latencies;
3860
3861         if (INTEL_INFO(dev)->gen >= 9)
3862                 latencies = dev_priv->wm.skl_latency;
3863         else
3864                 latencies = to_i915(dev)->wm.pri_latency;
3865
3866         return wm_latency_write(file, ubuf, len, offp, latencies);
3867 }
3868
3869 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3870                                     size_t len, loff_t *offp)
3871 {
3872         struct seq_file *m = file->private_data;
3873         struct drm_device *dev = m->private;
3874         struct drm_i915_private *dev_priv = dev->dev_private;
3875         uint16_t *latencies;
3876
3877         if (INTEL_INFO(dev)->gen >= 9)
3878                 latencies = dev_priv->wm.skl_latency;
3879         else
3880                 latencies = to_i915(dev)->wm.spr_latency;
3881
3882         return wm_latency_write(file, ubuf, len, offp, latencies);
3883 }
3884
3885 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3886                                     size_t len, loff_t *offp)
3887 {
3888         struct seq_file *m = file->private_data;
3889         struct drm_device *dev = m->private;
3890         struct drm_i915_private *dev_priv = dev->dev_private;
3891         uint16_t *latencies;
3892
3893         if (INTEL_INFO(dev)->gen >= 9)
3894                 latencies = dev_priv->wm.skl_latency;
3895         else
3896                 latencies = to_i915(dev)->wm.cur_latency;
3897
3898         return wm_latency_write(file, ubuf, len, offp, latencies);
3899 }
3900
3901 static const struct file_operations i915_pri_wm_latency_fops = {
3902         .owner = THIS_MODULE,
3903         .open = pri_wm_latency_open,
3904         .read = seq_read,
3905         .llseek = seq_lseek,
3906         .release = single_release,
3907         .write = pri_wm_latency_write
3908 };
3909
3910 static const struct file_operations i915_spr_wm_latency_fops = {
3911         .owner = THIS_MODULE,
3912         .open = spr_wm_latency_open,
3913         .read = seq_read,
3914         .llseek = seq_lseek,
3915         .release = single_release,
3916         .write = spr_wm_latency_write
3917 };
3918
3919 static const struct file_operations i915_cur_wm_latency_fops = {
3920         .owner = THIS_MODULE,
3921         .open = cur_wm_latency_open,
3922         .read = seq_read,
3923         .llseek = seq_lseek,
3924         .release = single_release,
3925         .write = cur_wm_latency_write
3926 };
3927
3928 static int
3929 i915_wedged_get(void *data, u64 *val)
3930 {
3931         struct drm_device *dev = data;
3932         struct drm_i915_private *dev_priv = dev->dev_private;
3933
3934         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3935
3936         return 0;
3937 }
3938
3939 static int
3940 i915_wedged_set(void *data, u64 val)
3941 {
3942         struct drm_device *dev = data;
3943         struct drm_i915_private *dev_priv = dev->dev_private;
3944
3945         intel_runtime_pm_get(dev_priv);
3946
3947         i915_handle_error(dev, val,
3948                           "Manually setting wedged to %llu", val);
3949
3950         intel_runtime_pm_put(dev_priv);
3951
3952         return 0;
3953 }
3954
3955 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3956                         i915_wedged_get, i915_wedged_set,
3957                         "%llu\n");
3958
3959 static int
3960 i915_ring_stop_get(void *data, u64 *val)
3961 {
3962         struct drm_device *dev = data;
3963         struct drm_i915_private *dev_priv = dev->dev_private;
3964
3965         *val = dev_priv->gpu_error.stop_rings;
3966
3967         return 0;
3968 }
3969
3970 static int
3971 i915_ring_stop_set(void *data, u64 val)
3972 {
3973         struct drm_device *dev = data;
3974         struct drm_i915_private *dev_priv = dev->dev_private;
3975         int ret;
3976
3977         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3978
3979         ret = mutex_lock_interruptible(&dev->struct_mutex);
3980         if (ret)
3981                 return ret;
3982
3983         dev_priv->gpu_error.stop_rings = val;
3984         mutex_unlock(&dev->struct_mutex);
3985
3986         return 0;
3987 }
3988
3989 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3990                         i915_ring_stop_get, i915_ring_stop_set,
3991                         "0x%08llx\n");
3992
3993 static int
3994 i915_ring_missed_irq_get(void *data, u64 *val)
3995 {
3996         struct drm_device *dev = data;
3997         struct drm_i915_private *dev_priv = dev->dev_private;
3998
3999         *val = dev_priv->gpu_error.missed_irq_rings;
4000         return 0;
4001 }
4002
4003 static int
4004 i915_ring_missed_irq_set(void *data, u64 val)
4005 {
4006         struct drm_device *dev = data;
4007         struct drm_i915_private *dev_priv = dev->dev_private;
4008         int ret;
4009
4010         /* Lock against concurrent debugfs callers */
4011         ret = mutex_lock_interruptible(&dev->struct_mutex);
4012         if (ret)
4013                 return ret;
4014         dev_priv->gpu_error.missed_irq_rings = val;
4015         mutex_unlock(&dev->struct_mutex);
4016
4017         return 0;
4018 }
4019
4020 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4021                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4022                         "0x%08llx\n");
4023
4024 static int
4025 i915_ring_test_irq_get(void *data, u64 *val)
4026 {
4027         struct drm_device *dev = data;
4028         struct drm_i915_private *dev_priv = dev->dev_private;
4029
4030         *val = dev_priv->gpu_error.test_irq_rings;
4031
4032         return 0;
4033 }
4034
4035 static int
4036 i915_ring_test_irq_set(void *data, u64 val)
4037 {
4038         struct drm_device *dev = data;
4039         struct drm_i915_private *dev_priv = dev->dev_private;
4040         int ret;
4041
4042         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4043
4044         /* Lock against concurrent debugfs callers */
4045         ret = mutex_lock_interruptible(&dev->struct_mutex);
4046         if (ret)
4047                 return ret;
4048
4049         dev_priv->gpu_error.test_irq_rings = val;
4050         mutex_unlock(&dev->struct_mutex);
4051
4052         return 0;
4053 }
4054
4055 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4056                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4057                         "0x%08llx\n");
4058
4059 #define DROP_UNBOUND 0x1
4060 #define DROP_BOUND 0x2
4061 #define DROP_RETIRE 0x4
4062 #define DROP_ACTIVE 0x8
4063 #define DROP_ALL (DROP_UNBOUND | \
4064                   DROP_BOUND | \
4065                   DROP_RETIRE | \
4066                   DROP_ACTIVE)
4067 static int
4068 i915_drop_caches_get(void *data, u64 *val)
4069 {
4070         *val = DROP_ALL;
4071
4072         return 0;
4073 }
4074
4075 static int
4076 i915_drop_caches_set(void *data, u64 val)
4077 {
4078         struct drm_device *dev = data;
4079         struct drm_i915_private *dev_priv = dev->dev_private;
4080         int ret;
4081
4082         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4083
4084         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4085          * on ioctls on -EAGAIN. */
4086         ret = mutex_lock_interruptible(&dev->struct_mutex);
4087         if (ret)
4088                 return ret;
4089
4090         if (val & DROP_ACTIVE) {
4091                 ret = i915_gpu_idle(dev);
4092                 if (ret)
4093                         goto unlock;
4094         }
4095
4096         if (val & (DROP_RETIRE | DROP_ACTIVE))
4097                 i915_gem_retire_requests(dev);
4098
4099         if (val & DROP_BOUND)
4100                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4101
4102         if (val & DROP_UNBOUND)
4103                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4104
4105 unlock:
4106         mutex_unlock(&dev->struct_mutex);
4107
4108         return ret;
4109 }
4110
4111 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4112                         i915_drop_caches_get, i915_drop_caches_set,
4113                         "0x%08llx\n");
4114
4115 static int
4116 i915_max_freq_get(void *data, u64 *val)
4117 {
4118         struct drm_device *dev = data;
4119         struct drm_i915_private *dev_priv = dev->dev_private;
4120         int ret;
4121
4122         if (INTEL_INFO(dev)->gen < 6)
4123                 return -ENODEV;
4124
4125         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4126
4127         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4128         if (ret)
4129                 return ret;
4130
4131         if (IS_VALLEYVIEW(dev))
4132                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4133         else
4134                 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4135         mutex_unlock(&dev_priv->rps.hw_lock);
4136
4137         return 0;
4138 }
4139
4140 static int
4141 i915_max_freq_set(void *data, u64 val)
4142 {
4143         struct drm_device *dev = data;
4144         struct drm_i915_private *dev_priv = dev->dev_private;
4145         u32 rp_state_cap, hw_max, hw_min;
4146         int ret;
4147
4148         if (INTEL_INFO(dev)->gen < 6)
4149                 return -ENODEV;
4150
4151         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4152
4153         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4154
4155         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4156         if (ret)
4157                 return ret;
4158
4159         /*
4160          * Turbo will still be enabled, but won't go above the set value.
4161          */
4162         if (IS_VALLEYVIEW(dev)) {
4163                 val = vlv_freq_opcode(dev_priv, val);
4164
4165                 hw_max = dev_priv->rps.max_freq;
4166                 hw_min = dev_priv->rps.min_freq;
4167         } else {
4168                 do_div(val, GT_FREQUENCY_MULTIPLIER);
4169
4170                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4171                 hw_max = dev_priv->rps.max_freq;
4172                 hw_min = (rp_state_cap >> 16) & 0xff;
4173         }
4174
4175         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4176                 mutex_unlock(&dev_priv->rps.hw_lock);
4177                 return -EINVAL;
4178         }
4179
4180         dev_priv->rps.max_freq_softlimit = val;
4181
4182         if (IS_VALLEYVIEW(dev))
4183                 valleyview_set_rps(dev, val);
4184         else
4185                 gen6_set_rps(dev, val);
4186
4187         mutex_unlock(&dev_priv->rps.hw_lock);
4188
4189         return 0;
4190 }
4191
4192 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4193                         i915_max_freq_get, i915_max_freq_set,
4194                         "%llu\n");
4195
4196 static int
4197 i915_min_freq_get(void *data, u64 *val)
4198 {
4199         struct drm_device *dev = data;
4200         struct drm_i915_private *dev_priv = dev->dev_private;
4201         int ret;
4202
4203         if (INTEL_INFO(dev)->gen < 6)
4204                 return -ENODEV;
4205
4206         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4207
4208         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4209         if (ret)
4210                 return ret;
4211
4212         if (IS_VALLEYVIEW(dev))
4213                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4214         else
4215                 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4216         mutex_unlock(&dev_priv->rps.hw_lock);
4217
4218         return 0;
4219 }
4220
4221 static int
4222 i915_min_freq_set(void *data, u64 val)
4223 {
4224         struct drm_device *dev = data;
4225         struct drm_i915_private *dev_priv = dev->dev_private;
4226         u32 rp_state_cap, hw_max, hw_min;
4227         int ret;
4228
4229         if (INTEL_INFO(dev)->gen < 6)
4230                 return -ENODEV;
4231
4232         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4233
4234         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4235
4236         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4237         if (ret)
4238                 return ret;
4239
4240         /*
4241          * Turbo will still be enabled, but won't go below the set value.
4242          */
4243         if (IS_VALLEYVIEW(dev)) {
4244                 val = vlv_freq_opcode(dev_priv, val);
4245
4246                 hw_max = dev_priv->rps.max_freq;
4247                 hw_min = dev_priv->rps.min_freq;
4248         } else {
4249                 do_div(val, GT_FREQUENCY_MULTIPLIER);
4250
4251                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4252                 hw_max = dev_priv->rps.max_freq;
4253                 hw_min = (rp_state_cap >> 16) & 0xff;
4254         }
4255
4256         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4257                 mutex_unlock(&dev_priv->rps.hw_lock);
4258                 return -EINVAL;
4259         }
4260
4261         dev_priv->rps.min_freq_softlimit = val;
4262
4263         if (IS_VALLEYVIEW(dev))
4264                 valleyview_set_rps(dev, val);
4265         else
4266                 gen6_set_rps(dev, val);
4267
4268         mutex_unlock(&dev_priv->rps.hw_lock);
4269
4270         return 0;
4271 }
4272
4273 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4274                         i915_min_freq_get, i915_min_freq_set,
4275                         "%llu\n");
4276
4277 static int
4278 i915_cache_sharing_get(void *data, u64 *val)
4279 {
4280         struct drm_device *dev = data;
4281         struct drm_i915_private *dev_priv = dev->dev_private;
4282         u32 snpcr;
4283         int ret;
4284
4285         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4286                 return -ENODEV;
4287
4288         ret = mutex_lock_interruptible(&dev->struct_mutex);
4289         if (ret)
4290                 return ret;
4291         intel_runtime_pm_get(dev_priv);
4292
4293         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4294
4295         intel_runtime_pm_put(dev_priv);
4296         mutex_unlock(&dev_priv->dev->struct_mutex);
4297
4298         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4299
4300         return 0;
4301 }
4302
4303 static int
4304 i915_cache_sharing_set(void *data, u64 val)
4305 {
4306         struct drm_device *dev = data;
4307         struct drm_i915_private *dev_priv = dev->dev_private;
4308         u32 snpcr;
4309
4310         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4311                 return -ENODEV;
4312
4313         if (val > 3)
4314                 return -EINVAL;
4315
4316         intel_runtime_pm_get(dev_priv);
4317         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4318
4319         /* Update the cache sharing policy here as well */
4320         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4321         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4322         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4323         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4324
4325         intel_runtime_pm_put(dev_priv);
4326         return 0;
4327 }
4328
4329 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4330                         i915_cache_sharing_get, i915_cache_sharing_set,
4331                         "%llu\n");
4332
4333 static int i915_forcewake_open(struct inode *inode, struct file *file)
4334 {
4335         struct drm_device *dev = inode->i_private;
4336         struct drm_i915_private *dev_priv = dev->dev_private;
4337
4338         if (INTEL_INFO(dev)->gen < 6)
4339                 return 0;
4340
4341         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4342
4343         return 0;
4344 }
4345
4346 static int i915_forcewake_release(struct inode *inode, struct file *file)
4347 {
4348         struct drm_device *dev = inode->i_private;
4349         struct drm_i915_private *dev_priv = dev->dev_private;
4350
4351         if (INTEL_INFO(dev)->gen < 6)
4352                 return 0;
4353
4354         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4355
4356         return 0;
4357 }
4358
4359 static const struct file_operations i915_forcewake_fops = {
4360         .owner = THIS_MODULE,
4361         .open = i915_forcewake_open,
4362         .release = i915_forcewake_release,
4363 };
4364
4365 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4366 {
4367         struct drm_device *dev = minor->dev;
4368         struct dentry *ent;
4369
4370         ent = debugfs_create_file("i915_forcewake_user",
4371                                   S_IRUSR,
4372                                   root, dev,
4373                                   &i915_forcewake_fops);
4374         if (!ent)
4375                 return -ENOMEM;
4376
4377         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4378 }
4379
4380 static int i915_debugfs_create(struct dentry *root,
4381                                struct drm_minor *minor,
4382                                const char *name,
4383                                const struct file_operations *fops)
4384 {
4385         struct drm_device *dev = minor->dev;
4386         struct dentry *ent;
4387
4388         ent = debugfs_create_file(name,
4389                                   S_IRUGO | S_IWUSR,
4390                                   root, dev,
4391                                   fops);
4392         if (!ent)
4393                 return -ENOMEM;
4394
4395         return drm_add_fake_info_node(minor, ent, fops);
4396 }
4397
4398 static const struct drm_info_list i915_debugfs_list[] = {
4399         {"i915_capabilities", i915_capabilities, 0},
4400         {"i915_gem_objects", i915_gem_object_info, 0},
4401         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4402         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4403         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4404         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4405         {"i915_gem_stolen", i915_gem_stolen_list_info },
4406         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4407         {"i915_gem_request", i915_gem_request_info, 0},
4408         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4409         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4410         {"i915_gem_interrupt", i915_interrupt_info, 0},
4411         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4412         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4413         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4414         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4415         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4416         {"i915_frequency_info", i915_frequency_info, 0},
4417         {"i915_drpc_info", i915_drpc_info, 0},
4418         {"i915_emon_status", i915_emon_status, 0},
4419         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4420         {"i915_fbc_status", i915_fbc_status, 0},
4421         {"i915_ips_status", i915_ips_status, 0},
4422         {"i915_sr_status", i915_sr_status, 0},
4423         {"i915_opregion", i915_opregion, 0},
4424         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4425         {"i915_context_status", i915_context_status, 0},
4426         {"i915_dump_lrc", i915_dump_lrc, 0},
4427         {"i915_execlists", i915_execlists, 0},
4428         {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
4429         {"i915_swizzle_info", i915_swizzle_info, 0},
4430         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4431         {"i915_llc", i915_llc, 0},
4432         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4433         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4434         {"i915_energy_uJ", i915_energy_uJ, 0},
4435         {"i915_pc8_status", i915_pc8_status, 0},
4436         {"i915_power_domain_info", i915_power_domain_info, 0},
4437         {"i915_display_info", i915_display_info, 0},
4438         {"i915_semaphore_status", i915_semaphore_status, 0},
4439         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4440         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4441         {"i915_wa_registers", i915_wa_registers, 0},
4442         {"i915_ddb_info", i915_ddb_info, 0},
4443 };
4444 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4445
4446 static const struct i915_debugfs_files {
4447         const char *name;
4448         const struct file_operations *fops;
4449 } i915_debugfs_files[] = {
4450         {"i915_wedged", &i915_wedged_fops},
4451         {"i915_max_freq", &i915_max_freq_fops},
4452         {"i915_min_freq", &i915_min_freq_fops},
4453         {"i915_cache_sharing", &i915_cache_sharing_fops},
4454         {"i915_ring_stop", &i915_ring_stop_fops},
4455         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4456         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4457         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4458         {"i915_error_state", &i915_error_state_fops},
4459         {"i915_next_seqno", &i915_next_seqno_fops},
4460         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4461         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4462         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4463         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4464         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4465 };
4466
4467 void intel_display_crc_init(struct drm_device *dev)
4468 {
4469         struct drm_i915_private *dev_priv = dev->dev_private;
4470         enum pipe pipe;
4471
4472         for_each_pipe(dev_priv, pipe) {
4473                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4474
4475                 pipe_crc->opened = false;
4476                 spin_lock_init(&pipe_crc->lock);
4477                 init_waitqueue_head(&pipe_crc->wq);
4478         }
4479 }
4480
4481 int i915_debugfs_init(struct drm_minor *minor)
4482 {
4483         int ret, i;
4484
4485         ret = i915_forcewake_create(minor->debugfs_root, minor);
4486         if (ret)
4487                 return ret;
4488
4489         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4490                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4491                 if (ret)
4492                         return ret;
4493         }
4494
4495         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4496                 ret = i915_debugfs_create(minor->debugfs_root, minor,
4497                                           i915_debugfs_files[i].name,
4498                                           i915_debugfs_files[i].fops);
4499                 if (ret)
4500                         return ret;
4501         }
4502
4503         return drm_debugfs_create_files(i915_debugfs_list,
4504                                         I915_DEBUGFS_ENTRIES,
4505                                         minor->debugfs_root, minor);
4506 }
4507
4508 void i915_debugfs_cleanup(struct drm_minor *minor)
4509 {
4510         int i;
4511
4512         drm_debugfs_remove_files(i915_debugfs_list,
4513                                  I915_DEBUGFS_ENTRIES, minor);
4514
4515         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4516                                  1, minor);
4517
4518         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4519                 struct drm_info_list *info_list =
4520                         (struct drm_info_list *)&i915_pipe_crc_data[i];
4521
4522                 drm_debugfs_remove_files(info_list, 1, minor);
4523         }
4524
4525         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4526                 struct drm_info_list *info_list =
4527                         (struct drm_info_list *) i915_debugfs_files[i].fops;
4528
4529                 drm_debugfs_remove_files(info_list, 1, minor);
4530         }
4531 }