drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include "intel_drv.h"
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include <linux/pci.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/acpi.h>
  41 #include <linux/pnp.h>
  42 #include <linux/vga_switcheroo.h>
  43 #include <linux/slab.h>
  44 #include <acpi/video.h>
  45
  46 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  47
  48 #define BEGIN_LP_RING(n) \
  49         intel_ring_begin(LP_RING(dev_priv), (n))
  50
  51 #define OUT_RING(x) \
  52         intel_ring_emit(LP_RING(dev_priv), x)
  53
  54 #define ADVANCE_LP_RING() \
  55         __intel_ring_advance(LP_RING(dev_priv))
  56
  57 /**
  58  * Lock test for when it's just for synchronization of ring access.
  59  *
  60  * In that case, we don't need to do it when GEM is initialized as nobody else
  61  * has access to the ring.
  62  */
  63 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  64         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  65                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  66 } while (0)
  67
  68 static inline u32
  69 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  70 {
  71         if (I915_NEED_GFX_HWS(dev_priv->dev))
  72                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  73         else
  74                 return intel_read_status_page(LP_RING(dev_priv), reg);
  75 }
  76
  77 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  78 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  79 #define I915_BREADCRUMB_INDEX           0x21
  80
  81 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  82 {
  83         drm_i915_private_t *dev_priv = dev->dev_private;
  84         struct drm_i915_master_private *master_priv;
  85
  86         if (dev->primary->master) {
  87                 master_priv = dev->primary->master->driver_priv;
  88                 if (master_priv->sarea_priv)
  89                         master_priv->sarea_priv->last_dispatch =
  90                                 READ_BREADCRUMB(dev_priv);
  91         }
  92 }
  93
  94 static void i915_write_hws_pga(struct drm_device *dev)
  95 {
  96         drm_i915_private_t *dev_priv = dev->dev_private;
  97         u32 addr;
  98
  99         addr = dev_priv->status_page_dmah->busaddr;
 100         if (INTEL_INFO(dev)->gen >= 4)
 101                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 102         I915_WRITE(HWS_PGA, addr);
 103 }
 104
 105 /**
 106  * Frees the hardware status page, whether it's a physical address or a virtual
 107  * address set up by the X Server.
 108  */
 109 static void i915_free_hws(struct drm_device *dev)
 110 {
 111         drm_i915_private_t *dev_priv = dev->dev_private;
 112         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 113
 114         if (dev_priv->status_page_dmah) {
 115                 drm_pci_free(dev, dev_priv->status_page_dmah);
 116                 dev_priv->status_page_dmah = NULL;
 117         }
 118
 119         if (ring->status_page.gfx_addr) {
 120                 ring->status_page.gfx_addr = 0;
 121                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 122         }
 123
 124         /* Need to rewrite hardware status page */
 125         I915_WRITE(HWS_PGA, 0x1ffff000);
 126 }
 127
 128 void i915_kernel_lost_context(struct drm_device * dev)
 129 {
 130         drm_i915_private_t *dev_priv = dev->dev_private;
 131         struct drm_i915_master_private *master_priv;
 132         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 133
 134         /*
 135          * We should never lose context on the ring with modesetting
 136          * as we don't expose it to userspace
 137          */
 138         if (drm_core_check_feature(dev, DRIVER_MODESET))
 139                 return;
 140
 141         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 142         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 143         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 144         if (ring->space < 0)
 145                 ring->space += ring->size;
 146
 147         if (!dev->primary->master)
 148                 return;
 149
 150         master_priv = dev->primary->master->driver_priv;
 151         if (ring->head == ring->tail && master_priv->sarea_priv)
 152                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 153 }
 154
 155 static int i915_dma_cleanup(struct drm_device * dev)
 156 {
 157         drm_i915_private_t *dev_priv = dev->dev_private;
 158         int i;
 159
 160         /* Make sure interrupts are disabled here because the uninstall ioctl
 161          * may not have been called from userspace and after dev_private
 162          * is freed, it's too late.
 163          */
 164         if (dev->irq_enabled)
 165                 drm_irq_uninstall(dev);
 166
 167         mutex_lock(&dev->struct_mutex);
 168         for (i = 0; i < I915_NUM_RINGS; i++)
 169                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 170         mutex_unlock(&dev->struct_mutex);
 171
 172         /* Clear the HWS virtual address at teardown */
 173         if (I915_NEED_GFX_HWS(dev))
 174                 i915_free_hws(dev);
 175
 176         return 0;
 177 }
 178
 179 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 180 {
 181         drm_i915_private_t *dev_priv = dev->dev_private;
 182         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 183         int ret;
 184
 185         master_priv->sarea = drm_getsarea(dev);
 186         if (master_priv->sarea) {
 187                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 188                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 189         } else {
 190                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 191         }
 192
 193         if (init->ring_size != 0) {
 194                 if (LP_RING(dev_priv)->obj != NULL) {
 195                         i915_dma_cleanup(dev);
 196                         DRM_ERROR("Client tried to initialize ringbuffer in "
 197                                   "GEM mode\n");
 198                         return -EINVAL;
 199                 }
 200
 201                 ret = intel_render_ring_init_dri(dev,
 202                                                  init->ring_start,
 203                                                  init->ring_size);
 204                 if (ret) {
 205                         i915_dma_cleanup(dev);
 206                         return ret;
 207                 }
 208         }
 209
 210         dev_priv->dri1.cpp = init->cpp;
 211         dev_priv->dri1.back_offset = init->back_offset;
 212         dev_priv->dri1.front_offset = init->front_offset;
 213         dev_priv->dri1.current_page = 0;
 214         if (master_priv->sarea_priv)
 215                 master_priv->sarea_priv->pf_current_page = 0;
 216
 217         /* Allow hardware batchbuffers unless told otherwise.
 218          */
 219         dev_priv->dri1.allow_batchbuffer = 1;
 220
 221         return 0;
 222 }
 223
 224 static int i915_dma_resume(struct drm_device * dev)
 225 {
 226         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 227         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 228
 229         DRM_DEBUG_DRIVER("%s\n", __func__);
 230
 231         if (ring->virtual_start == NULL) {
 232                 DRM_ERROR("can not ioremap virtual address for"
 233                           " ring buffer\n");
 234                 return -ENOMEM;
 235         }
 236
 237         /* Program Hardware Status Page */
 238         if (!ring->status_page.page_addr) {
 239                 DRM_ERROR("Can not find hardware status page\n");
 240                 return -EINVAL;
 241         }
 242         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 243                                 ring->status_page.page_addr);
 244         if (ring->status_page.gfx_addr != 0)
 245                 intel_ring_setup_status_page(ring);
 246         else
 247                 i915_write_hws_pga(dev);
 248
 249         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 250
 251         return 0;
 252 }
 253
 254 static int i915_dma_init(struct drm_device *dev, void *data,
 255                          struct drm_file *file_priv)
 256 {
 257         drm_i915_init_t *init = data;
 258         int retcode = 0;
 259
 260         if (drm_core_check_feature(dev, DRIVER_MODESET))
 261                 return -ENODEV;
 262
 263         switch (init->func) {
 264         case I915_INIT_DMA:
 265                 retcode = i915_initialize(dev, init);
 266                 break;
 267         case I915_CLEANUP_DMA:
 268                 retcode = i915_dma_cleanup(dev);
 269                 break;
 270         case I915_RESUME_DMA:
 271                 retcode = i915_dma_resume(dev);
 272                 break;
 273         default:
 274                 retcode = -EINVAL;
 275                 break;
 276         }
 277
 278         return retcode;
 279 }
 280
 281 /* Implement basically the same security restrictions as hardware does
 282  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 283  *
 284  * Most of the calculations below involve calculating the size of a
 285  * particular instruction.  It's important to get the size right as
 286  * that tells us where the next instruction to check is.  Any illegal
 287  * instruction detected will be given a size of zero, which is a
 288  * signal to abort the rest of the buffer.
 289  */
 290 static int validate_cmd(int cmd)
 291 {
 292         switch (((cmd >> 29) & 0x7)) {
 293         case 0x0:
 294                 switch ((cmd >> 23) & 0x3f) {
 295                 case 0x0:
 296                         return 1;       /* MI_NOOP */
 297                 case 0x4:
 298                         return 1;       /* MI_FLUSH */
 299                 default:
 300                         return 0;       /* disallow everything else */
 301                 }
 302                 break;
 303         case 0x1:
 304                 return 0;       /* reserved */
 305         case 0x2:
 306                 return (cmd & 0xff) + 2;        /* 2d commands */
 307         case 0x3:
 308                 if (((cmd >> 24) & 0x1f) <= 0x18)
 309                         return 1;
 310
 311                 switch ((cmd >> 24) & 0x1f) {
 312                 case 0x1c:
 313                         return 1;
 314                 case 0x1d:
 315                         switch ((cmd >> 16) & 0xff) {
 316                         case 0x3:
 317                                 return (cmd & 0x1f) + 2;
 318                         case 0x4:
 319                                 return (cmd & 0xf) + 2;
 320                         default:
 321                                 return (cmd & 0xffff) + 2;
 322                         }
 323                 case 0x1e:
 324                         if (cmd & (1 << 23))
 325                                 return (cmd & 0xffff) + 1;
 326                         else
 327                                 return 1;
 328                 case 0x1f:
 329                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 330                                 return (cmd & 0x1ffff) + 2;
 331                         else if (cmd & (1 << 17))       /* indirect random */
 332                                 if ((cmd & 0xffff) == 0)
 333                                         return 0;       /* unknown length, too hard */
 334                                 else
 335                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 336                         else
 337                                 return 2;       /* indirect sequential */
 338                 default:
 339                         return 0;
 340                 }
 341         default:
 342                 return 0;
 343         }
 344
 345         return 0;
 346 }
 347
 348 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 349 {
 350         drm_i915_private_t *dev_priv = dev->dev_private;
 351         int i, ret;
 352
 353         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 354                 return -EINVAL;
 355
 356         for (i = 0; i < dwords;) {
 357                 int sz = validate_cmd(buffer[i]);
 358                 if (sz == 0 || i + sz > dwords)
 359                         return -EINVAL;
 360                 i += sz;
 361         }
 362
 363         ret = BEGIN_LP_RING((dwords+1)&~1);
 364         if (ret)
 365                 return ret;
 366
 367         for (i = 0; i < dwords; i++)
 368                 OUT_RING(buffer[i]);
 369         if (dwords & 1)
 370                 OUT_RING(0);
 371
 372         ADVANCE_LP_RING();
 373
 374         return 0;
 375 }
 376
 377 int
 378 i915_emit_box(struct drm_device *dev,
 379               struct drm_clip_rect *box,
 380               int DR1, int DR4)
 381 {
 382         struct drm_i915_private *dev_priv = dev->dev_private;
 383         int ret;
 384
 385         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 386             box->y2 <= 0 || box->x2 <= 0) {
 387                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 388                           box->x1, box->y1, box->x2, box->y2);
 389                 return -EINVAL;
 390         }
 391
 392         if (INTEL_INFO(dev)->gen >= 4) {
 393                 ret = BEGIN_LP_RING(4);
 394                 if (ret)
 395                         return ret;
 396
 397                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 398                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 399                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 400                 OUT_RING(DR4);
 401         } else {
 402                 ret = BEGIN_LP_RING(6);
 403                 if (ret)
 404                         return ret;
 405
 406                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 407                 OUT_RING(DR1);
 408                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 409                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 410                 OUT_RING(DR4);
 411                 OUT_RING(0);
 412         }
 413         ADVANCE_LP_RING();
 414
 415         return 0;
 416 }
 417
 418 /* XXX: Emitting the counter should really be moved to part of the IRQ
 419  * emit. For now, do it in both places:
 420  */
 421
 422 static void i915_emit_breadcrumb(struct drm_device *dev)
 423 {
 424         drm_i915_private_t *dev_priv = dev->dev_private;
 425         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 426
 427         dev_priv->dri1.counter++;
 428         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 429                 dev_priv->dri1.counter = 0;
 430         if (master_priv->sarea_priv)
 431                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 432
 433         if (BEGIN_LP_RING(4) == 0) {
 434                 OUT_RING(MI_STORE_DWORD_INDEX);
 435                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 436                 OUT_RING(dev_priv->dri1.counter);
 437                 OUT_RING(0);
 438                 ADVANCE_LP_RING();
 439         }
 440 }
 441
 442 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 443                                    drm_i915_cmdbuffer_t *cmd,
 444                                    struct drm_clip_rect *cliprects,
 445                                    void *cmdbuf)
 446 {
 447         int nbox = cmd->num_cliprects;
 448         int i = 0, count, ret;
 449
 450         if (cmd->sz & 0x3) {
 451                 DRM_ERROR("alignment");
 452                 return -EINVAL;
 453         }
 454
 455         i915_kernel_lost_context(dev);
 456
 457         count = nbox ? nbox : 1;
 458
 459         for (i = 0; i < count; i++) {
 460                 if (i < nbox) {
 461                         ret = i915_emit_box(dev, &cliprects[i],
 462                                             cmd->DR1, cmd->DR4);
 463                         if (ret)
 464                                 return ret;
 465                 }
 466
 467                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 468                 if (ret)
 469                         return ret;
 470         }
 471
 472         i915_emit_breadcrumb(dev);
 473         return 0;
 474 }
 475
 476 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 477                                      drm_i915_batchbuffer_t * batch,
 478                                      struct drm_clip_rect *cliprects)
 479 {
 480         struct drm_i915_private *dev_priv = dev->dev_private;
 481         int nbox = batch->num_cliprects;
 482         int i, count, ret;
 483
 484         if ((batch->start | batch->used) & 0x7) {
 485                 DRM_ERROR("alignment");
 486                 return -EINVAL;
 487         }
 488
 489         i915_kernel_lost_context(dev);
 490
 491         count = nbox ? nbox : 1;
 492         for (i = 0; i < count; i++) {
 493                 if (i < nbox) {
 494                         ret = i915_emit_box(dev, &cliprects[i],
 495                                             batch->DR1, batch->DR4);
 496                         if (ret)
 497                                 return ret;
 498                 }
 499
 500                 if (!IS_I830(dev) && !IS_845G(dev)) {
 501                         ret = BEGIN_LP_RING(2);
 502                         if (ret)
 503                                 return ret;
 504
 505                         if (INTEL_INFO(dev)->gen >= 4) {
 506                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 507                                 OUT_RING(batch->start);
 508                         } else {
 509                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 510                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 511                         }
 512                 } else {
 513                         ret = BEGIN_LP_RING(4);
 514                         if (ret)
 515                                 return ret;
 516
 517                         OUT_RING(MI_BATCH_BUFFER);
 518                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 519                         OUT_RING(batch->start + batch->used - 4);
 520                         OUT_RING(0);
 521                 }
 522                 ADVANCE_LP_RING();
 523         }
 524
 525
 526         if (IS_G4X(dev) || IS_GEN5(dev)) {
 527                 if (BEGIN_LP_RING(2) == 0) {
 528                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 529                         OUT_RING(MI_NOOP);
 530                         ADVANCE_LP_RING();
 531                 }
 532         }
 533
 534         i915_emit_breadcrumb(dev);
 535         return 0;
 536 }
 537
 538 static int i915_dispatch_flip(struct drm_device * dev)
 539 {
 540         drm_i915_private_t *dev_priv = dev->dev_private;
 541         struct drm_i915_master_private *master_priv =
 542                 dev->primary->master->driver_priv;
 543         int ret;
 544
 545         if (!master_priv->sarea_priv)
 546                 return -EINVAL;
 547
 548         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 549                           __func__,
 550                          dev_priv->dri1.current_page,
 551                          master_priv->sarea_priv->pf_current_page);
 552
 553         i915_kernel_lost_context(dev);
 554
 555         ret = BEGIN_LP_RING(10);
 556         if (ret)
 557                 return ret;
 558
 559         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 560         OUT_RING(0);
 561
 562         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 563         OUT_RING(0);
 564         if (dev_priv->dri1.current_page == 0) {
 565                 OUT_RING(dev_priv->dri1.back_offset);
 566                 dev_priv->dri1.current_page = 1;
 567         } else {
 568                 OUT_RING(dev_priv->dri1.front_offset);
 569                 dev_priv->dri1.current_page = 0;
 570         }
 571         OUT_RING(0);
 572
 573         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 574         OUT_RING(0);
 575
 576         ADVANCE_LP_RING();
 577
 578         master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 579
 580         if (BEGIN_LP_RING(4) == 0) {
 581                 OUT_RING(MI_STORE_DWORD_INDEX);
 582                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 583                 OUT_RING(dev_priv->dri1.counter);
 584                 OUT_RING(0);
 585                 ADVANCE_LP_RING();
 586         }
 587
 588         master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 589         return 0;
 590 }
 591
 592 static int i915_quiescent(struct drm_device *dev)
 593 {
 594         i915_kernel_lost_context(dev);
 595         return intel_ring_idle(LP_RING(dev->dev_private));
 596 }
 597
 598 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 599                             struct drm_file *file_priv)
 600 {
 601         int ret;
 602
 603         if (drm_core_check_feature(dev, DRIVER_MODESET))
 604                 return -ENODEV;
 605
 606         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 607
 608         mutex_lock(&dev->struct_mutex);
 609         ret = i915_quiescent(dev);
 610         mutex_unlock(&dev->struct_mutex);
 611
 612         return ret;
 613 }
 614
 615 static int i915_batchbuffer(struct drm_device *dev, void *data,
 616                             struct drm_file *file_priv)
 617 {
 618         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 619         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 620         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 621             master_priv->sarea_priv;
 622         drm_i915_batchbuffer_t *batch = data;
 623         int ret;
 624         struct drm_clip_rect *cliprects = NULL;
 625
 626         if (drm_core_check_feature(dev, DRIVER_MODESET))
 627                 return -ENODEV;
 628
 629         if (!dev_priv->dri1.allow_batchbuffer) {
 630                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 631                 return -EINVAL;
 632         }
 633
 634         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 635                         batch->start, batch->used, batch->num_cliprects);
 636
 637         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 638
 639         if (batch->num_cliprects < 0)
 640                 return -EINVAL;
 641
 642         if (batch->num_cliprects) {
 643                 cliprects = kcalloc(batch->num_cliprects,
 644                                     sizeof(*cliprects),
 645                                     GFP_KERNEL);
 646                 if (cliprects == NULL)
 647                         return -ENOMEM;
 648
 649                 ret = copy_from_user(cliprects, batch->cliprects,
 650                                      batch->num_cliprects *
 651                                      sizeof(struct drm_clip_rect));
 652                 if (ret != 0) {
 653                         ret = -EFAULT;
 654                         goto fail_free;
 655                 }
 656         }
 657
 658         mutex_lock(&dev->struct_mutex);
 659         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 660         mutex_unlock(&dev->struct_mutex);
 661
 662         if (sarea_priv)
 663                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 664
 665 fail_free:
 666         kfree(cliprects);
 667
 668         return ret;
 669 }
 670
 671 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 672                           struct drm_file *file_priv)
 673 {
 674         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 675         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 676         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 677             master_priv->sarea_priv;
 678         drm_i915_cmdbuffer_t *cmdbuf = data;
 679         struct drm_clip_rect *cliprects = NULL;
 680         void *batch_data;
 681         int ret;
 682
 683         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 684                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 685
 686         if (drm_core_check_feature(dev, DRIVER_MODESET))
 687                 return -ENODEV;
 688
 689         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 690
 691         if (cmdbuf->num_cliprects < 0)
 692                 return -EINVAL;
 693
 694         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 695         if (batch_data == NULL)
 696                 return -ENOMEM;
 697
 698         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 699         if (ret != 0) {
 700                 ret = -EFAULT;
 701                 goto fail_batch_free;
 702         }
 703
 704         if (cmdbuf->num_cliprects) {
 705                 cliprects = kcalloc(cmdbuf->num_cliprects,
 706                                     sizeof(*cliprects), GFP_KERNEL);
 707                 if (cliprects == NULL) {
 708                         ret = -ENOMEM;
 709                         goto fail_batch_free;
 710                 }
 711
 712                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 713                                      cmdbuf->num_cliprects *
 714                                      sizeof(struct drm_clip_rect));
 715                 if (ret != 0) {
 716                         ret = -EFAULT;
 717                         goto fail_clip_free;
 718                 }
 719         }
 720
 721         mutex_lock(&dev->struct_mutex);
 722         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 723         mutex_unlock(&dev->struct_mutex);
 724         if (ret) {
 725                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 726                 goto fail_clip_free;
 727         }
 728
 729         if (sarea_priv)
 730                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 731
 732 fail_clip_free:
 733         kfree(cliprects);
 734 fail_batch_free:
 735         kfree(batch_data);
 736
 737         return ret;
 738 }
 739
 740 static int i915_emit_irq(struct drm_device * dev)
 741 {
 742         drm_i915_private_t *dev_priv = dev->dev_private;
 743         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 744
 745         i915_kernel_lost_context(dev);
 746
 747         DRM_DEBUG_DRIVER("\n");
 748
 749         dev_priv->dri1.counter++;
 750         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 751                 dev_priv->dri1.counter = 1;
 752         if (master_priv->sarea_priv)
 753                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 754
 755         if (BEGIN_LP_RING(4) == 0) {
 756                 OUT_RING(MI_STORE_DWORD_INDEX);
 757                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 758                 OUT_RING(dev_priv->dri1.counter);
 759                 OUT_RING(MI_USER_INTERRUPT);
 760                 ADVANCE_LP_RING();
 761         }
 762
 763         return dev_priv->dri1.counter;
 764 }
 765
 766 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 767 {
 768         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 769         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 770         int ret = 0;
 771         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 772
 773         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 774                   READ_BREADCRUMB(dev_priv));
 775
 776         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 777                 if (master_priv->sarea_priv)
 778                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 779                 return 0;
 780         }
 781
 782         if (master_priv->sarea_priv)
 783                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 784
 785         if (ring->irq_get(ring)) {
 786                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 787                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 788                 ring->irq_put(ring);
 789         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 790                 ret = -EBUSY;
 791
 792         if (ret == -EBUSY) {
 793                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 794                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 795         }
 796
 797         return ret;
 798 }
 799
 800 /* Needs the lock as it touches the ring.
 801  */
 802 static int i915_irq_emit(struct drm_device *dev, void *data,
 803                          struct drm_file *file_priv)
 804 {
 805         drm_i915_private_t *dev_priv = dev->dev_private;
 806         drm_i915_irq_emit_t *emit = data;
 807         int result;
 808
 809         if (drm_core_check_feature(dev, DRIVER_MODESET))
 810                 return -ENODEV;
 811
 812         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 813                 DRM_ERROR("called with no initialization\n");
 814                 return -EINVAL;
 815         }
 816
 817         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 818
 819         mutex_lock(&dev->struct_mutex);
 820         result = i915_emit_irq(dev);
 821         mutex_unlock(&dev->struct_mutex);
 822
 823         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 824                 DRM_ERROR("copy_to_user\n");
 825                 return -EFAULT;
 826         }
 827
 828         return 0;
 829 }
 830
 831 /* Doesn't need the hardware lock.
 832  */
 833 static int i915_irq_wait(struct drm_device *dev, void *data,
 834                          struct drm_file *file_priv)
 835 {
 836         drm_i915_private_t *dev_priv = dev->dev_private;
 837         drm_i915_irq_wait_t *irqwait = data;
 838
 839         if (drm_core_check_feature(dev, DRIVER_MODESET))
 840                 return -ENODEV;
 841
 842         if (!dev_priv) {
 843                 DRM_ERROR("called with no initialization\n");
 844                 return -EINVAL;
 845         }
 846
 847         return i915_wait_irq(dev, irqwait->irq_seq);
 848 }
 849
 850 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 851                          struct drm_file *file_priv)
 852 {
 853         drm_i915_private_t *dev_priv = dev->dev_private;
 854         drm_i915_vblank_pipe_t *pipe = data;
 855
 856         if (drm_core_check_feature(dev, DRIVER_MODESET))
 857                 return -ENODEV;
 858
 859         if (!dev_priv) {
 860                 DRM_ERROR("called with no initialization\n");
 861                 return -EINVAL;
 862         }
 863
 864         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 865
 866         return 0;
 867 }
 868
 869 /**
 870  * Schedule buffer swap at given vertical blank.
 871  */
 872 static int i915_vblank_swap(struct drm_device *dev, void *data,
 873                      struct drm_file *file_priv)
 874 {
 875         /* The delayed swap mechanism was fundamentally racy, and has been
 876          * removed.  The model was that the client requested a delayed flip/swap
 877          * from the kernel, then waited for vblank before continuing to perform
 878          * rendering.  The problem was that the kernel might wake the client
 879          * up before it dispatched the vblank swap (since the lock has to be
 880          * held while touching the ringbuffer), in which case the client would
 881          * clear and start the next frame before the swap occurred, and
 882          * flicker would occur in addition to likely missing the vblank.
 883          *
 884          * In the absence of this ioctl, userland falls back to a correct path
 885          * of waiting for a vblank, then dispatching the swap on its own.
 886          * Context switching to userland and back is plenty fast enough for
 887          * meeting the requirements of vblank swapping.
 888          */
 889         return -EINVAL;
 890 }
 891
 892 static int i915_flip_bufs(struct drm_device *dev, void *data,
 893                           struct drm_file *file_priv)
 894 {
 895         int ret;
 896
 897         if (drm_core_check_feature(dev, DRIVER_MODESET))
 898                 return -ENODEV;
 899
 900         DRM_DEBUG_DRIVER("%s\n", __func__);
 901
 902         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 903
 904         mutex_lock(&dev->struct_mutex);
 905         ret = i915_dispatch_flip(dev);
 906         mutex_unlock(&dev->struct_mutex);
 907
 908         return ret;
 909 }
 910
 911 static int i915_getparam(struct drm_device *dev, void *data,
 912                          struct drm_file *file_priv)
 913 {
 914         drm_i915_private_t *dev_priv = dev->dev_private;
 915         drm_i915_getparam_t *param = data;
 916         int value;
 917
 918         if (!dev_priv) {
 919                 DRM_ERROR("called with no initialization\n");
 920                 return -EINVAL;
 921         }
 922
 923         switch (param->param) {
 924         case I915_PARAM_IRQ_ACTIVE:
 925                 value = dev->pdev->irq ? 1 : 0;
 926                 break;
 927         case I915_PARAM_ALLOW_BATCHBUFFER:
 928                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 929                 break;
 930         case I915_PARAM_LAST_DISPATCH:
 931                 value = READ_BREADCRUMB(dev_priv);
 932                 break;
 933         case I915_PARAM_CHIPSET_ID:
 934                 value = dev->pdev->device;
 935                 break;
 936         case I915_PARAM_HAS_GEM:
 937                 value = 1;
 938                 break;
 939         case I915_PARAM_NUM_FENCES_AVAIL:
 940                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 941                 break;
 942         case I915_PARAM_HAS_OVERLAY:
 943                 value = dev_priv->overlay ? 1 : 0;
 944                 break;
 945         case I915_PARAM_HAS_PAGEFLIPPING:
 946                 value = 1;
 947                 break;
 948         case I915_PARAM_HAS_EXECBUF2:
 949                 /* depends on GEM */
 950                 value = 1;
 951                 break;
 952         case I915_PARAM_HAS_BSD:
 953                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 954                 break;
 955         case I915_PARAM_HAS_BLT:
 956                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 957                 break;
 958         case I915_PARAM_HAS_VEBOX:
 959                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
 960                 break;
 961         case I915_PARAM_HAS_RELAXED_FENCING:
 962                 value = 1;
 963                 break;
 964         case I915_PARAM_HAS_COHERENT_RINGS:
 965                 value = 1;
 966                 break;
 967         case I915_PARAM_HAS_EXEC_CONSTANTS:
 968                 value = INTEL_INFO(dev)->gen >= 4;
 969                 break;
 970         case I915_PARAM_HAS_RELAXED_DELTA:
 971                 value = 1;
 972                 break;
 973         case I915_PARAM_HAS_GEN7_SOL_RESET:
 974                 value = 1;
 975                 break;
 976         case I915_PARAM_HAS_LLC:
 977                 value = HAS_LLC(dev);
 978                 break;
 979         case I915_PARAM_HAS_WT:
 980                 value = HAS_WT(dev);
 981                 break;
 982         case I915_PARAM_HAS_ALIASING_PPGTT:
 983                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 984                 break;
 985         case I915_PARAM_HAS_WAIT_TIMEOUT:
 986                 value = 1;
 987                 break;
 988         case I915_PARAM_HAS_SEMAPHORES:
 989                 value = i915_semaphore_is_enabled(dev);
 990                 break;
 991         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 992                 value = 1;
 993                 break;
 994         case I915_PARAM_HAS_SECURE_BATCHES:
 995                 value = capable(CAP_SYS_ADMIN);
 996                 break;
 997         case I915_PARAM_HAS_PINNED_BATCHES:
 998                 value = 1;
 999                 break;
1000         case I915_PARAM_HAS_EXEC_NO_RELOC:
1001                 value = 1;
1002                 break;
1003         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1004                 value = 1;
1005                 break;
1006         default:
1007                 DRM_DEBUG("Unknown parameter %d\n", param->param);
1008                 return -EINVAL;
1009         }
1010
1011         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1012                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1013                 return -EFAULT;
1014         }
1015
1016         return 0;
1017 }
1018
1019 static int i915_setparam(struct drm_device *dev, void *data,
1020                          struct drm_file *file_priv)
1021 {
1022         drm_i915_private_t *dev_priv = dev->dev_private;
1023         drm_i915_setparam_t *param = data;
1024
1025         if (!dev_priv) {
1026                 DRM_ERROR("called with no initialization\n");
1027                 return -EINVAL;
1028         }
1029
1030         switch (param->param) {
1031         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1032                 break;
1033         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1034                 break;
1035         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1036                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1037                 break;
1038         case I915_SETPARAM_NUM_USED_FENCES:
1039                 if (param->value > dev_priv->num_fence_regs ||
1040                     param->value < 0)
1041                         return -EINVAL;
1042                 /* Userspace can use first N regs */
1043                 dev_priv->fence_reg_start = param->value;
1044                 break;
1045         default:
1046                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1047                                         param->param);
1048                 return -EINVAL;
1049         }
1050
1051         return 0;
1052 }
1053
1054 static int i915_set_status_page(struct drm_device *dev, void *data,
1055                                 struct drm_file *file_priv)
1056 {
1057         drm_i915_private_t *dev_priv = dev->dev_private;
1058         drm_i915_hws_addr_t *hws = data;
1059         struct intel_ring_buffer *ring;
1060
1061         if (drm_core_check_feature(dev, DRIVER_MODESET))
1062                 return -ENODEV;
1063
1064         if (!I915_NEED_GFX_HWS(dev))
1065                 return -EINVAL;
1066
1067         if (!dev_priv) {
1068                 DRM_ERROR("called with no initialization\n");
1069                 return -EINVAL;
1070         }
1071
1072         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1073                 WARN(1, "tried to set status page when mode setting active\n");
1074                 return 0;
1075         }
1076
1077         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1078
1079         ring = LP_RING(dev_priv);
1080         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1081
1082         dev_priv->dri1.gfx_hws_cpu_addr =
1083                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1084         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1085                 i915_dma_cleanup(dev);
1086                 ring->status_page.gfx_addr = 0;
1087                 DRM_ERROR("can not ioremap virtual address for"
1088                                 " G33 hw status page\n");
1089                 return -ENOMEM;
1090         }
1091
1092         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1093         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1094
1095         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1096                          ring->status_page.gfx_addr);
1097         DRM_DEBUG_DRIVER("load hws at %p\n",
1098                          ring->status_page.page_addr);
1099         return 0;
1100 }
1101
1102 static int i915_get_bridge_dev(struct drm_device *dev)
1103 {
1104         struct drm_i915_private *dev_priv = dev->dev_private;
1105
1106         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1107         if (!dev_priv->bridge_dev) {
1108                 DRM_ERROR("bridge device not found\n");
1109                 return -1;
1110         }
1111         return 0;
1112 }
1113
1114 #define MCHBAR_I915 0x44
1115 #define MCHBAR_I965 0x48
1116 #define MCHBAR_SIZE (4*4096)
1117
1118 #define DEVEN_REG 0x54
1119 #define   DEVEN_MCHBAR_EN (1 << 28)
1120
1121 /* Allocate space for the MCH regs if needed, return nonzero on error */
1122 static int
1123 intel_alloc_mchbar_resource(struct drm_device *dev)
1124 {
1125         drm_i915_private_t *dev_priv = dev->dev_private;
1126         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1127         u32 temp_lo, temp_hi = 0;
1128         u64 mchbar_addr;
1129         int ret;
1130
1131         if (INTEL_INFO(dev)->gen >= 4)
1132                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1133         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1134         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1135
1136         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1137 #ifdef CONFIG_PNP
1138         if (mchbar_addr &&
1139             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1140                 return 0;
1141 #endif
1142
1143         /* Get some space for it */
1144         dev_priv->mch_res.name = "i915 MCHBAR";
1145         dev_priv->mch_res.flags = IORESOURCE_MEM;
1146         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1147                                      &dev_priv->mch_res,
1148                                      MCHBAR_SIZE, MCHBAR_SIZE,
1149                                      PCIBIOS_MIN_MEM,
1150                                      0, pcibios_align_resource,
1151                                      dev_priv->bridge_dev);
1152         if (ret) {
1153                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1154                 dev_priv->mch_res.start = 0;
1155                 return ret;
1156         }
1157
1158         if (INTEL_INFO(dev)->gen >= 4)
1159                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1160                                        upper_32_bits(dev_priv->mch_res.start));
1161
1162         pci_write_config_dword(dev_priv->bridge_dev, reg,
1163                                lower_32_bits(dev_priv->mch_res.start));
1164         return 0;
1165 }
1166
1167 /* Setup MCHBAR if possible, return true if we should disable it again */
1168 static void
1169 intel_setup_mchbar(struct drm_device *dev)
1170 {
1171         drm_i915_private_t *dev_priv = dev->dev_private;
1172         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1173         u32 temp;
1174         bool enabled;
1175
1176         dev_priv->mchbar_need_disable = false;
1177
1178         if (IS_I915G(dev) || IS_I915GM(dev)) {
1179                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1180                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1181         } else {
1182                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1183                 enabled = temp & 1;
1184         }
1185
1186         /* If it's already enabled, don't have to do anything */
1187         if (enabled)
1188                 return;
1189
1190         if (intel_alloc_mchbar_resource(dev))
1191                 return;
1192
1193         dev_priv->mchbar_need_disable = true;
1194
1195         /* Space is allocated or reserved, so enable it. */
1196         if (IS_I915G(dev) || IS_I915GM(dev)) {
1197                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1198                                        temp | DEVEN_MCHBAR_EN);
1199         } else {
1200                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1201                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1202         }
1203 }
1204
1205 static void
1206 intel_teardown_mchbar(struct drm_device *dev)
1207 {
1208         drm_i915_private_t *dev_priv = dev->dev_private;
1209         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1210         u32 temp;
1211
1212         if (dev_priv->mchbar_need_disable) {
1213                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1214                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1215                         temp &= ~DEVEN_MCHBAR_EN;
1216                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1217                 } else {
1218                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1219                         temp &= ~1;
1220                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1221                 }
1222         }
1223
1224         if (dev_priv->mch_res.start)
1225                 release_resource(&dev_priv->mch_res);
1226 }
1227
1228 /* true = enable decode, false = disable decoder */
1229 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1230 {
1231         struct drm_device *dev = cookie;
1232
1233         intel_modeset_vga_set_state(dev, state);
1234         if (state)
1235                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1236                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1237         else
1238                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1239 }
1240
1241 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1242 {
1243         struct drm_device *dev = pci_get_drvdata(pdev);
1244         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1245         if (state == VGA_SWITCHEROO_ON) {
1246                 pr_info("switched on\n");
1247                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1248                 /* i915 resume handler doesn't set to D0 */
1249                 pci_set_power_state(dev->pdev, PCI_D0);
1250                 i915_resume(dev);
1251                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1252         } else {
1253                 pr_err("switched off\n");
1254                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1255                 i915_suspend(dev, pmm);
1256                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1257         }
1258 }
1259
1260 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1261 {
1262         struct drm_device *dev = pci_get_drvdata(pdev);
1263         bool can_switch;
1264
1265         spin_lock(&dev->count_lock);
1266         can_switch = (dev->open_count == 0);
1267         spin_unlock(&dev->count_lock);
1268         return can_switch;
1269 }
1270
1271 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1272         .set_gpu_state = i915_switcheroo_set_state,
1273         .reprobe = NULL,
1274         .can_switch = i915_switcheroo_can_switch,
1275 };
1276
1277 static int i915_load_modeset_init(struct drm_device *dev)
1278 {
1279         struct drm_i915_private *dev_priv = dev->dev_private;
1280         int ret;
1281
1282         ret = intel_parse_bios(dev);
1283         if (ret)
1284                 DRM_INFO("failed to find VBIOS tables\n");
1285
1286         /* If we have > 1 VGA cards, then we need to arbitrate access
1287          * to the common VGA resources.
1288          *
1289          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1290          * then we do not take part in VGA arbitration and the
1291          * vga_client_register() fails with -ENODEV.
1292          */
1293         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1294         if (ret && ret != -ENODEV)
1295                 goto out;
1296
1297         intel_register_dsm_handler();
1298
1299         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1300         if (ret)
1301                 goto cleanup_vga_client;
1302
1303         /* Initialise stolen first so that we may reserve preallocated
1304          * objects for the BIOS to KMS transition.
1305          */
1306         ret = i915_gem_init_stolen(dev);
1307         if (ret)
1308                 goto cleanup_vga_switcheroo;
1309
1310         ret = drm_irq_install(dev);
1311         if (ret)
1312                 goto cleanup_gem_stolen;
1313
1314         intel_power_domains_init_hw(dev);
1315
1316         /* Important: The output setup functions called by modeset_init need
1317          * working irqs for e.g. gmbus and dp aux transfers. */
1318         intel_modeset_init(dev);
1319
1320         ret = i915_gem_init(dev);
1321         if (ret)
1322                 goto cleanup_power;
1323
1324         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1325
1326         intel_modeset_gem_init(dev);
1327
1328         /* Always safe in the mode setting case. */
1329         /* FIXME: do pre/post-mode set stuff in core KMS code */
1330         dev->vblank_disable_allowed = true;
1331         if (INTEL_INFO(dev)->num_pipes == 0) {
1332                 intel_display_power_put(dev, POWER_DOMAIN_VGA);
1333                 return 0;
1334         }
1335
1336         ret = intel_fbdev_init(dev);
1337         if (ret)
1338                 goto cleanup_gem;
1339
1340         /* Only enable hotplug handling once the fbdev is fully set up. */
1341         intel_hpd_init(dev);
1342
1343         /*
1344          * Some ports require correctly set-up hpd registers for detection to
1345          * work properly (leading to ghost connected connector status), e.g. VGA
1346          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1347          * irqs are fully enabled. Now we should scan for the initial config
1348          * only once hotplug handling is enabled, but due to screwed-up locking
1349          * around kms/fbdev init we can't protect the fdbev initial config
1350          * scanning against hotplug events. Hence do this first and ignore the
1351          * tiny window where we will loose hotplug notifactions.
1352          */
1353         intel_fbdev_initial_config(dev);
1354
1355         /* Only enable hotplug handling once the fbdev is fully set up. */
1356         dev_priv->enable_hotplug_processing = true;
1357
1358         drm_kms_helper_poll_init(dev);
1359
1360         return 0;
1361
1362 cleanup_gem:
1363         mutex_lock(&dev->struct_mutex);
1364         i915_gem_cleanup_ringbuffer(dev);
1365         i915_gem_context_fini(dev);
1366         mutex_unlock(&dev->struct_mutex);
1367         i915_gem_cleanup_aliasing_ppgtt(dev);
1368         drm_mm_takedown(&dev_priv->gtt.base.mm);
1369 cleanup_power:
1370         intel_display_power_put(dev, POWER_DOMAIN_VGA);
1371         drm_irq_uninstall(dev);
1372 cleanup_gem_stolen:
1373         i915_gem_cleanup_stolen(dev);
1374 cleanup_vga_switcheroo:
1375         vga_switcheroo_unregister_client(dev->pdev);
1376 cleanup_vga_client:
1377         vga_client_register(dev->pdev, NULL, NULL, NULL);
1378 out:
1379         return ret;
1380 }
1381
1382 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1383 {
1384         struct drm_i915_master_private *master_priv;
1385
1386         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1387         if (!master_priv)
1388                 return -ENOMEM;
1389
1390         master->driver_priv = master_priv;
1391         return 0;
1392 }
1393
1394 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1395 {
1396         struct drm_i915_master_private *master_priv = master->driver_priv;
1397
1398         if (!master_priv)
1399                 return;
1400
1401         kfree(master_priv);
1402
1403         master->driver_priv = NULL;
1404 }
1405
1406 #ifdef CONFIG_DRM_I915_FBDEV
1407 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1408 {
1409         struct apertures_struct *ap;
1410         struct pci_dev *pdev = dev_priv->dev->pdev;
1411         bool primary;
1412
1413         ap = alloc_apertures(1);
1414         if (!ap)
1415                 return;
1416
1417         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1418         ap->ranges[0].size = dev_priv->gtt.mappable_end;
1419
1420         primary =
1421                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1422
1423         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1424
1425         kfree(ap);
1426 }
1427 #else
1428 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1429 {
1430 }
1431 #endif
1432
1433 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1434 {
1435         const struct intel_device_info *info = dev_priv->info;
1436
1437 #define PRINT_S(name) "%s"
1438 #define SEP_EMPTY
1439 #define PRINT_FLAG(name) info->name ? #name "," : ""
1440 #define SEP_COMMA ,
1441         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1442                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1443                          info->gen,
1444                          dev_priv->dev->pdev->device,
1445                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1446 #undef PRINT_S
1447 #undef SEP_EMPTY
1448 #undef PRINT_FLAG
1449 #undef SEP_COMMA
1450 }
1451
1452 /**
1453  * i915_driver_load - setup chip and create an initial config
1454  * @dev: DRM device
1455  * @flags: startup flags
1456  *
1457  * The driver load routine has to do several things:
1458  *   - drive output discovery via intel_modeset_init()
1459  *   - initialize the memory manager
1460  *   - allocate initial config memory
1461  *   - setup the DRM framebuffer with the allocated memory
1462  */
1463 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1464 {
1465         struct drm_i915_private *dev_priv;
1466         struct intel_device_info *info;
1467         int ret = 0, mmio_bar, mmio_size;
1468         uint32_t aperture_size;
1469
1470         info = (struct intel_device_info *) flags;
1471
1472         /* Refuse to load on gen6+ without kms enabled. */
1473         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1474                 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1475                 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1476                 return -ENODEV;
1477         }
1478
1479         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1480         if (dev_priv == NULL)
1481                 return -ENOMEM;
1482
1483         dev->dev_private = (void *)dev_priv;
1484         dev_priv->dev = dev;
1485         dev_priv->info = info;
1486
1487         spin_lock_init(&dev_priv->irq_lock);
1488         spin_lock_init(&dev_priv->gpu_error.lock);
1489         spin_lock_init(&dev_priv->backlight.lock);
1490         spin_lock_init(&dev_priv->uncore.lock);
1491         spin_lock_init(&dev_priv->mm.object_stat_lock);
1492         mutex_init(&dev_priv->dpio_lock);
1493         mutex_init(&dev_priv->rps.hw_lock);
1494         mutex_init(&dev_priv->modeset_restore_lock);
1495
1496         mutex_init(&dev_priv->pc8.lock);
1497         dev_priv->pc8.requirements_met = false;
1498         dev_priv->pc8.gpu_idle = false;
1499         dev_priv->pc8.irqs_disabled = false;
1500         dev_priv->pc8.enabled = false;
1501         dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
1502         INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
1503
1504         intel_display_crc_init(dev);
1505
1506         i915_dump_device_info(dev_priv);
1507
1508         /* Not all pre-production machines fall into this category, only the
1509          * very first ones. Almost everything should work, except for maybe
1510          * suspend/resume. And we don't implement workarounds that affect only
1511          * pre-production machines. */
1512         if (IS_HSW_EARLY_SDV(dev))
1513                 DRM_INFO("This is an early pre-production Haswell machine. "
1514                          "It may not be fully functional.\n");
1515
1516         if (i915_get_bridge_dev(dev)) {
1517                 ret = -EIO;
1518                 goto free_priv;
1519         }
1520
1521         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1522         /* Before gen4, the registers and the GTT are behind different BARs.
1523          * However, from gen4 onwards, the registers and the GTT are shared
1524          * in the same BAR, so we want to restrict this ioremap from
1525          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1526          * the register BAR remains the same size for all the earlier
1527          * generations up to Ironlake.
1528          */
1529         if (info->gen < 5)
1530                 mmio_size = 512*1024;
1531         else
1532                 mmio_size = 2*1024*1024;
1533
1534         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1535         if (!dev_priv->regs) {
1536                 DRM_ERROR("failed to map registers\n");
1537                 ret = -EIO;
1538                 goto put_bridge;
1539         }
1540
1541         intel_uncore_early_sanitize(dev);
1542
1543         /* This must be called before any calls to HAS_PCH_* */
1544         intel_detect_pch(dev);
1545
1546         intel_uncore_init(dev);
1547
1548         ret = i915_gem_gtt_init(dev);
1549         if (ret)
1550                 goto out_regs;
1551
1552         if (drm_core_check_feature(dev, DRIVER_MODESET))
1553                 i915_kick_out_firmware_fb(dev_priv);
1554
1555         pci_set_master(dev->pdev);
1556
1557         /* overlay on gen2 is broken and can't address above 1G */
1558         if (IS_GEN2(dev))
1559                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1560
1561         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1562          * using 32bit addressing, overwriting memory if HWS is located
1563          * above 4GB.
1564          *
1565          * The documentation also mentions an issue with undefined
1566          * behaviour if any general state is accessed within a page above 4GB,
1567          * which also needs to be handled carefully.
1568          */
1569         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1570                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1571
1572         aperture_size = dev_priv->gtt.mappable_end;
1573
1574         dev_priv->gtt.mappable =
1575                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1576                                      aperture_size);
1577         if (dev_priv->gtt.mappable == NULL) {
1578                 ret = -EIO;
1579                 goto out_gtt;
1580         }
1581
1582         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1583                                               aperture_size);
1584
1585         /* The i915 workqueue is primarily used for batched retirement of
1586          * requests (and thus managing bo) once the task has been completed
1587          * by the GPU. i915_gem_retire_requests() is called directly when we
1588          * need high-priority retirement, such as waiting for an explicit
1589          * bo.
1590          *
1591          * It is also used for periodic low-priority events, such as
1592          * idle-timers and recording error state.
1593          *
1594          * All tasks on the workqueue are expected to acquire the dev mutex
1595          * so there is no point in running more than one instance of the
1596          * workqueue at any time.  Use an ordered one.
1597          */
1598         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1599         if (dev_priv->wq == NULL) {
1600                 DRM_ERROR("Failed to create our workqueue.\n");
1601                 ret = -ENOMEM;
1602                 goto out_mtrrfree;
1603         }
1604
1605         intel_irq_init(dev);
1606         intel_pm_init(dev);
1607         intel_uncore_sanitize(dev);
1608
1609         /* Try to make sure MCHBAR is enabled before poking at it */
1610         intel_setup_mchbar(dev);
1611         intel_setup_gmbus(dev);
1612         intel_opregion_setup(dev);
1613
1614         intel_setup_bios(dev);
1615
1616         i915_gem_load(dev);
1617
1618         /* On the 945G/GM, the chipset reports the MSI capability on the
1619          * integrated graphics even though the support isn't actually there
1620          * according to the published specs.  It doesn't appear to function
1621          * correctly in testing on 945G.
1622          * This may be a side effect of MSI having been made available for PEG
1623          * and the registers being closely associated.
1624          *
1625          * According to chipset errata, on the 965GM, MSI interrupts may
1626          * be lost or delayed, but we use them anyways to avoid
1627          * stuck interrupts on some machines.
1628          */
1629         if (!IS_I945G(dev) && !IS_I945GM(dev))
1630                 pci_enable_msi(dev->pdev);
1631
1632         dev_priv->num_plane = 1;
1633         if (IS_VALLEYVIEW(dev))
1634                 dev_priv->num_plane = 2;
1635
1636         if (INTEL_INFO(dev)->num_pipes) {
1637                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1638                 if (ret)
1639                         goto out_gem_unload;
1640         }
1641
1642         if (HAS_POWER_WELL(dev))
1643                 intel_power_domains_init(dev);
1644
1645         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1646                 ret = i915_load_modeset_init(dev);
1647                 if (ret < 0) {
1648                         DRM_ERROR("failed to init modeset\n");
1649                         goto out_power_well;
1650                 }
1651         } else {
1652                 /* Start out suspended in ums mode. */
1653                 dev_priv->ums.mm_suspended = 1;
1654         }
1655
1656         i915_setup_sysfs(dev);
1657
1658         if (INTEL_INFO(dev)->num_pipes) {
1659                 /* Must be done after probing outputs */
1660                 intel_opregion_init(dev);
1661                 acpi_video_register();
1662         }
1663
1664         if (IS_GEN5(dev))
1665                 intel_gpu_ips_init(dev_priv);
1666
1667         return 0;
1668
1669 out_power_well:
1670         if (HAS_POWER_WELL(dev))
1671                 intel_power_domains_remove(dev);
1672         drm_vblank_cleanup(dev);
1673 out_gem_unload:
1674         if (dev_priv->mm.inactive_shrinker.scan_objects)
1675                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1676
1677         if (dev->pdev->msi_enabled)
1678                 pci_disable_msi(dev->pdev);
1679
1680         intel_teardown_gmbus(dev);
1681         intel_teardown_mchbar(dev);
1682         destroy_workqueue(dev_priv->wq);
1683 out_mtrrfree:
1684         arch_phys_wc_del(dev_priv->gtt.mtrr);
1685         io_mapping_free(dev_priv->gtt.mappable);
1686 out_gtt:
1687         list_del(&dev_priv->gtt.base.global_link);
1688         drm_mm_takedown(&dev_priv->gtt.base.mm);
1689         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1690 out_regs:
1691         intel_uncore_fini(dev);
1692         pci_iounmap(dev->pdev, dev_priv->regs);
1693 put_bridge:
1694         pci_dev_put(dev_priv->bridge_dev);
1695 free_priv:
1696         if (dev_priv->slab)
1697                 kmem_cache_destroy(dev_priv->slab);
1698         kfree(dev_priv);
1699         return ret;
1700 }
1701
1702 int i915_driver_unload(struct drm_device *dev)
1703 {
1704         struct drm_i915_private *dev_priv = dev->dev_private;
1705         int ret;
1706
1707         intel_gpu_ips_teardown();
1708
1709         if (HAS_POWER_WELL(dev)) {
1710                 /* The i915.ko module is still not prepared to be loaded when
1711                  * the power well is not enabled, so just enable it in case
1712                  * we're going to unload/reload. */
1713                 intel_display_set_init_power(dev, true);
1714                 intel_power_domains_remove(dev);
1715         }
1716
1717         i915_teardown_sysfs(dev);
1718
1719         if (dev_priv->mm.inactive_shrinker.scan_objects)
1720                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1721
1722         ret = i915_gem_suspend(dev);
1723         if (ret)
1724                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1725
1726         io_mapping_free(dev_priv->gtt.mappable);
1727         arch_phys_wc_del(dev_priv->gtt.mtrr);
1728
1729         acpi_video_unregister();
1730
1731         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1732                 intel_fbdev_fini(dev);
1733                 intel_modeset_cleanup(dev);
1734                 cancel_work_sync(&dev_priv->console_resume_work);
1735
1736                 /*
1737                  * free the memory space allocated for the child device
1738                  * config parsed from VBT
1739                  */
1740                 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1741                         kfree(dev_priv->vbt.child_dev);
1742                         dev_priv->vbt.child_dev = NULL;
1743                         dev_priv->vbt.child_dev_num = 0;
1744                 }
1745
1746                 vga_switcheroo_unregister_client(dev->pdev);
1747                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1748         }
1749
1750         /* Free error state after interrupts are fully disabled. */
1751         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1752         cancel_work_sync(&dev_priv->gpu_error.work);
1753         i915_destroy_error_state(dev);
1754
1755         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
1756
1757         if (dev->pdev->msi_enabled)
1758                 pci_disable_msi(dev->pdev);
1759
1760         intel_opregion_fini(dev);
1761
1762         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1763                 /* Flush any outstanding unpin_work. */
1764                 flush_workqueue(dev_priv->wq);
1765
1766                 mutex_lock(&dev->struct_mutex);
1767                 i915_gem_free_all_phys_object(dev);
1768                 i915_gem_cleanup_ringbuffer(dev);
1769                 i915_gem_context_fini(dev);
1770                 mutex_unlock(&dev->struct_mutex);
1771                 i915_gem_cleanup_aliasing_ppgtt(dev);
1772                 i915_gem_cleanup_stolen(dev);
1773
1774                 if (!I915_NEED_GFX_HWS(dev))
1775                         i915_free_hws(dev);
1776         }
1777
1778         list_del(&dev_priv->gtt.base.global_link);
1779         WARN_ON(!list_empty(&dev_priv->vm_list));
1780         drm_mm_takedown(&dev_priv->gtt.base.mm);
1781
1782         drm_vblank_cleanup(dev);
1783
1784         intel_teardown_gmbus(dev);
1785         intel_teardown_mchbar(dev);
1786
1787         destroy_workqueue(dev_priv->wq);
1788         pm_qos_remove_request(&dev_priv->pm_qos);
1789
1790         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1791
1792         intel_uncore_fini(dev);
1793         if (dev_priv->regs != NULL)
1794                 pci_iounmap(dev->pdev, dev_priv->regs);
1795
1796         if (dev_priv->slab)
1797                 kmem_cache_destroy(dev_priv->slab);
1798
1799         pci_dev_put(dev_priv->bridge_dev);
1800         kfree(dev->dev_private);
1801
1802         return 0;
1803 }
1804
1805 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1806 {
1807         int ret;
1808
1809         ret = i915_gem_open(dev, file);
1810         if (ret)
1811                 return ret;
1812
1813         return 0;
1814 }
1815
1816 /**
1817  * i915_driver_lastclose - clean up after all DRM clients have exited
1818  * @dev: DRM device
1819  *
1820  * Take care of cleaning up after all DRM clients have exited.  In the
1821  * mode setting case, we want to restore the kernel's initial mode (just
1822  * in case the last client left us in a bad state).
1823  *
1824  * Additionally, in the non-mode setting case, we'll tear down the GTT
1825  * and DMA structures, since the kernel won't be using them, and clea
1826  * up any GEM state.
1827  */
1828 void i915_driver_lastclose(struct drm_device * dev)
1829 {
1830         drm_i915_private_t *dev_priv = dev->dev_private;
1831
1832         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1833          * goes right around and calls lastclose. Check for this and don't clean
1834          * up anything. */
1835         if (!dev_priv)
1836                 return;
1837
1838         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1839                 intel_fbdev_restore_mode(dev);
1840                 vga_switcheroo_process_delayed_switch();
1841                 return;
1842         }
1843
1844         i915_gem_lastclose(dev);
1845
1846         i915_dma_cleanup(dev);
1847 }
1848
1849 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1850 {
1851         i915_gem_context_close(dev, file_priv);
1852         i915_gem_release(dev, file_priv);
1853 }
1854
1855 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1856 {
1857         struct drm_i915_file_private *file_priv = file->driver_priv;
1858
1859         kfree(file_priv);
1860 }
1861
1862 const struct drm_ioctl_desc i915_ioctls[] = {
1863         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1864         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1865         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1866         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1867         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1868         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1869         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1870         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1871         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1872         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1873         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1874         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1875         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1876         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1877         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1878         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1879         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1880         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1881         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1882         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1883         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1884         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1885         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1886         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1887         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1888         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1889         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1890         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1891         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1892         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1893         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1894         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1895         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1896         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1897         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1898         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1899         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1900         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1901         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1902         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1903         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1904         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1905         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1906         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1907         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1908         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1909         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1910         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1911 };
1912
1913 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1914
1915 /*
1916  * This is really ugly: Because old userspace abused the linux agp interface to
1917  * manage the gtt, we need to claim that all intel devices are agp.  For
1918  * otherwise the drm core refuses to initialize the agp support code.
1919  */
1920 int i915_driver_device_is_agp(struct drm_device * dev)
1921 {
1922         return 1;
1923 }