drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include <drm/drm_legacy.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38 #include "i915_vgpu.h"
  39 #include "i915_trace.h"
  40 #include <linux/pci.h>
  41 #include <linux/console.h>
  42 #include <linux/vt.h>
  43 #include <linux/vgaarb.h>
  44 #include <linux/acpi.h>
  45 #include <linux/pnp.h>
  46 #include <linux/vga_switcheroo.h>
  47 #include <linux/slab.h>
  48 #include <acpi/video.h>
  49 #include <linux/pm.h>
  50 #include <linux/pm_runtime.h>
  51 #include <linux/oom.h>
  52
  53 static unsigned int i915_load_fail_count;
  54
  55 bool __i915_inject_load_failure(const char *func, int line)
  56 {
  57         if (i915_load_fail_count >= i915.inject_load_failure)
  58                 return false;
  59
  60         if (++i915_load_fail_count == i915.inject_load_failure) {
  61                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  62                          i915.inject_load_failure, func, line);
  63                 return true;
  64         }
  65
  66         return false;
  67 }
  68
  69 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  70 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  71                     "providing the dmesg log by booting with drm.debug=0xf"
  72
  73 void
  74 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  75               const char *fmt, ...)
  76 {
  77         static bool shown_bug_once;
  78         struct device *dev = dev_priv->dev->dev;
  79         bool is_error = level[1] <= KERN_ERR[1];
  80         bool is_debug = level[1] == KERN_DEBUG[1];
  81         struct va_format vaf;
  82         va_list args;
  83
  84         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  85                 return;
  86
  87         va_start(args, fmt);
  88
  89         vaf.fmt = fmt;
  90         vaf.va = &args;
  91
  92         dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
  93                    __builtin_return_address(0), &vaf);
  94
  95         if (is_error && !shown_bug_once) {
  96                 dev_notice(dev, "%s", FDO_BUG_MSG);
  97                 shown_bug_once = true;
  98         }
  99
 100         va_end(args);
 101 }
 102
 103 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 104 {
 105         return i915.inject_load_failure &&
 106                i915_load_fail_count == i915.inject_load_failure;
 107 }
 108
 109 #define i915_load_error(dev_priv, fmt, ...)                                  \
 110         __i915_printk(dev_priv,                                              \
 111                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 112                       fmt, ##__VA_ARGS__)
 113
 114 static int i915_getparam(struct drm_device *dev, void *data,
 115                          struct drm_file *file_priv)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118         drm_i915_getparam_t *param = data;
 119         int value;
 120
 121         switch (param->param) {
 122         case I915_PARAM_IRQ_ACTIVE:
 123         case I915_PARAM_ALLOW_BATCHBUFFER:
 124         case I915_PARAM_LAST_DISPATCH:
 125                 /* Reject all old ums/dri params. */
 126                 return -ENODEV;
 127         case I915_PARAM_CHIPSET_ID:
 128                 value = dev->pdev->device;
 129                 break;
 130         case I915_PARAM_REVISION:
 131                 value = dev->pdev->revision;
 132                 break;
 133         case I915_PARAM_HAS_GEM:
 134                 value = 1;
 135                 break;
 136         case I915_PARAM_NUM_FENCES_AVAIL:
 137                 value = dev_priv->num_fence_regs;
 138                 break;
 139         case I915_PARAM_HAS_OVERLAY:
 140                 value = dev_priv->overlay ? 1 : 0;
 141                 break;
 142         case I915_PARAM_HAS_PAGEFLIPPING:
 143                 value = 1;
 144                 break;
 145         case I915_PARAM_HAS_EXECBUF2:
 146                 /* depends on GEM */
 147                 value = 1;
 148                 break;
 149         case I915_PARAM_HAS_BSD:
 150                 value = intel_engine_initialized(&dev_priv->engine[VCS]);
 151                 break;
 152         case I915_PARAM_HAS_BLT:
 153                 value = intel_engine_initialized(&dev_priv->engine[BCS]);
 154                 break;
 155         case I915_PARAM_HAS_VEBOX:
 156                 value = intel_engine_initialized(&dev_priv->engine[VECS]);
 157                 break;
 158         case I915_PARAM_HAS_BSD2:
 159                 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
 160                 break;
 161         case I915_PARAM_HAS_RELAXED_FENCING:
 162                 value = 1;
 163                 break;
 164         case I915_PARAM_HAS_COHERENT_RINGS:
 165                 value = 1;
 166                 break;
 167         case I915_PARAM_HAS_EXEC_CONSTANTS:
 168                 value = INTEL_INFO(dev)->gen >= 4;
 169                 break;
 170         case I915_PARAM_HAS_RELAXED_DELTA:
 171                 value = 1;
 172                 break;
 173         case I915_PARAM_HAS_GEN7_SOL_RESET:
 174                 value = 1;
 175                 break;
 176         case I915_PARAM_HAS_LLC:
 177                 value = HAS_LLC(dev);
 178                 break;
 179         case I915_PARAM_HAS_WT:
 180                 value = HAS_WT(dev);
 181                 break;
 182         case I915_PARAM_HAS_ALIASING_PPGTT:
 183                 value = USES_PPGTT(dev);
 184                 break;
 185         case I915_PARAM_HAS_WAIT_TIMEOUT:
 186                 value = 1;
 187                 break;
 188         case I915_PARAM_HAS_SEMAPHORES:
 189                 value = i915_semaphore_is_enabled(dev);
 190                 break;
 191         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 192                 value = 1;
 193                 break;
 194         case I915_PARAM_HAS_SECURE_BATCHES:
 195                 value = capable(CAP_SYS_ADMIN);
 196                 break;
 197         case I915_PARAM_HAS_PINNED_BATCHES:
 198                 value = 1;
 199                 break;
 200         case I915_PARAM_HAS_EXEC_NO_RELOC:
 201                 value = 1;
 202                 break;
 203         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 204                 value = 1;
 205                 break;
 206         case I915_PARAM_CMD_PARSER_VERSION:
 207                 value = i915_cmd_parser_get_version();
 208                 break;
 209         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 210                 value = 1;
 211                 break;
 212         case I915_PARAM_MMAP_VERSION:
 213                 value = 1;
 214                 break;
 215         case I915_PARAM_SUBSLICE_TOTAL:
 216                 value = INTEL_INFO(dev)->subslice_total;
 217                 if (!value)
 218                         return -ENODEV;
 219                 break;
 220         case I915_PARAM_EU_TOTAL:
 221                 value = INTEL_INFO(dev)->eu_total;
 222                 if (!value)
 223                         return -ENODEV;
 224                 break;
 225         case I915_PARAM_HAS_GPU_RESET:
 226                 value = i915.enable_hangcheck &&
 227                         intel_has_gpu_reset(dev);
 228                 break;
 229         case I915_PARAM_HAS_RESOURCE_STREAMER:
 230                 value = HAS_RESOURCE_STREAMER(dev);
 231                 break;
 232         case I915_PARAM_HAS_EXEC_SOFTPIN:
 233                 value = 1;
 234                 break;
 235         default:
 236                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 237                 return -EINVAL;
 238         }
 239
 240         if (copy_to_user(param->value, &value, sizeof(int))) {
 241                 DRM_ERROR("copy_to_user failed\n");
 242                 return -EFAULT;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static int i915_get_bridge_dev(struct drm_device *dev)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251
 252         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 253         if (!dev_priv->bridge_dev) {
 254                 DRM_ERROR("bridge device not found\n");
 255                 return -1;
 256         }
 257         return 0;
 258 }
 259
 260 /* Allocate space for the MCH regs if needed, return nonzero on error */
 261 static int
 262 intel_alloc_mchbar_resource(struct drm_device *dev)
 263 {
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 266         u32 temp_lo, temp_hi = 0;
 267         u64 mchbar_addr;
 268         int ret;
 269
 270         if (INTEL_INFO(dev)->gen >= 4)
 271                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 272         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 273         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 274
 275         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 276 #ifdef CONFIG_PNP
 277         if (mchbar_addr &&
 278             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 279                 return 0;
 280 #endif
 281
 282         /* Get some space for it */
 283         dev_priv->mch_res.name = "i915 MCHBAR";
 284         dev_priv->mch_res.flags = IORESOURCE_MEM;
 285         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 286                                      &dev_priv->mch_res,
 287                                      MCHBAR_SIZE, MCHBAR_SIZE,
 288                                      PCIBIOS_MIN_MEM,
 289                                      0, pcibios_align_resource,
 290                                      dev_priv->bridge_dev);
 291         if (ret) {
 292                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 293                 dev_priv->mch_res.start = 0;
 294                 return ret;
 295         }
 296
 297         if (INTEL_INFO(dev)->gen >= 4)
 298                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 299                                        upper_32_bits(dev_priv->mch_res.start));
 300
 301         pci_write_config_dword(dev_priv->bridge_dev, reg,
 302                                lower_32_bits(dev_priv->mch_res.start));
 303         return 0;
 304 }
 305
 306 /* Setup MCHBAR if possible, return true if we should disable it again */
 307 static void
 308 intel_setup_mchbar(struct drm_device *dev)
 309 {
 310         struct drm_i915_private *dev_priv = dev->dev_private;
 311         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 312         u32 temp;
 313         bool enabled;
 314
 315         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 316                 return;
 317
 318         dev_priv->mchbar_need_disable = false;
 319
 320         if (IS_I915G(dev) || IS_I915GM(dev)) {
 321                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 322                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 323         } else {
 324                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 325                 enabled = temp & 1;
 326         }
 327
 328         /* If it's already enabled, don't have to do anything */
 329         if (enabled)
 330                 return;
 331
 332         if (intel_alloc_mchbar_resource(dev))
 333                 return;
 334
 335         dev_priv->mchbar_need_disable = true;
 336
 337         /* Space is allocated or reserved, so enable it. */
 338         if (IS_I915G(dev) || IS_I915GM(dev)) {
 339                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 340                                        temp | DEVEN_MCHBAR_EN);
 341         } else {
 342                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 343                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 344         }
 345 }
 346
 347 static void
 348 intel_teardown_mchbar(struct drm_device *dev)
 349 {
 350         struct drm_i915_private *dev_priv = dev->dev_private;
 351         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 352
 353         if (dev_priv->mchbar_need_disable) {
 354                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 355                         u32 deven_val;
 356
 357                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 358                                               &deven_val);
 359                         deven_val &= ~DEVEN_MCHBAR_EN;
 360                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 361                                                deven_val);
 362                 } else {
 363                         u32 mchbar_val;
 364
 365                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 366                                               &mchbar_val);
 367                         mchbar_val &= ~1;
 368                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 369                                                mchbar_val);
 370                 }
 371         }
 372
 373         if (dev_priv->mch_res.start)
 374                 release_resource(&dev_priv->mch_res);
 375 }
 376
 377 /* true = enable decode, false = disable decoder */
 378 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 379 {
 380         struct drm_device *dev = cookie;
 381
 382         intel_modeset_vga_set_state(dev, state);
 383         if (state)
 384                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 385                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 386         else
 387                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 388 }
 389
 390 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 391 {
 392         struct drm_device *dev = pci_get_drvdata(pdev);
 393         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 394
 395         if (state == VGA_SWITCHEROO_ON) {
 396                 pr_info("switched on\n");
 397                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 398                 /* i915 resume handler doesn't set to D0 */
 399                 pci_set_power_state(dev->pdev, PCI_D0);
 400                 i915_resume_switcheroo(dev);
 401                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 402         } else {
 403                 pr_info("switched off\n");
 404                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 405                 i915_suspend_switcheroo(dev, pmm);
 406                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 407         }
 408 }
 409
 410 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 411 {
 412         struct drm_device *dev = pci_get_drvdata(pdev);
 413
 414         /*
 415          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 416          * locking inversion with the driver load path. And the access here is
 417          * completely racy anyway. So don't bother with locking for now.
 418          */
 419         return dev->open_count == 0;
 420 }
 421
 422 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 423         .set_gpu_state = i915_switcheroo_set_state,
 424         .reprobe = NULL,
 425         .can_switch = i915_switcheroo_can_switch,
 426 };
 427
 428 static int i915_load_modeset_init(struct drm_device *dev)
 429 {
 430         struct drm_i915_private *dev_priv = dev->dev_private;
 431         int ret;
 432
 433         if (i915_inject_load_failure())
 434                 return -ENODEV;
 435
 436         ret = intel_bios_init(dev_priv);
 437         if (ret)
 438                 DRM_INFO("failed to find VBIOS tables\n");
 439
 440         /* If we have > 1 VGA cards, then we need to arbitrate access
 441          * to the common VGA resources.
 442          *
 443          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 444          * then we do not take part in VGA arbitration and the
 445          * vga_client_register() fails with -ENODEV.
 446          */
 447         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 448         if (ret && ret != -ENODEV)
 449                 goto out;
 450
 451         intel_register_dsm_handler();
 452
 453         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 454         if (ret)
 455                 goto cleanup_vga_client;
 456
 457         intel_power_domains_init_hw(dev_priv, false);
 458
 459         intel_csr_ucode_init(dev_priv);
 460
 461         ret = intel_irq_install(dev_priv);
 462         if (ret)
 463                 goto cleanup_csr;
 464
 465         intel_setup_gmbus(dev);
 466
 467         /* Important: The output setup functions called by modeset_init need
 468          * working irqs for e.g. gmbus and dp aux transfers. */
 469         intel_modeset_init(dev);
 470
 471         intel_guc_ucode_init(dev);
 472
 473         ret = i915_gem_init(dev);
 474         if (ret)
 475                 goto cleanup_irq;
 476
 477         intel_modeset_gem_init(dev);
 478
 479         /* Always safe in the mode setting case. */
 480         /* FIXME: do pre/post-mode set stuff in core KMS code */
 481         dev->vblank_disable_allowed = true;
 482         if (INTEL_INFO(dev)->num_pipes == 0)
 483                 return 0;
 484
 485         ret = intel_fbdev_init(dev);
 486         if (ret)
 487                 goto cleanup_gem;
 488
 489         /* Only enable hotplug handling once the fbdev is fully set up. */
 490         intel_hpd_init(dev_priv);
 491
 492         /*
 493          * Some ports require correctly set-up hpd registers for detection to
 494          * work properly (leading to ghost connected connector status), e.g. VGA
 495          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 496          * irqs are fully enabled. Now we should scan for the initial config
 497          * only once hotplug handling is enabled, but due to screwed-up locking
 498          * around kms/fbdev init we can't protect the fdbev initial config
 499          * scanning against hotplug events. Hence do this first and ignore the
 500          * tiny window where we will loose hotplug notifactions.
 501          */
 502         intel_fbdev_initial_config_async(dev);
 503
 504         drm_kms_helper_poll_init(dev);
 505
 506         return 0;
 507
 508 cleanup_gem:
 509         mutex_lock(&dev->struct_mutex);
 510         i915_gem_cleanup_engines(dev);
 511         i915_gem_context_fini(dev);
 512         mutex_unlock(&dev->struct_mutex);
 513 cleanup_irq:
 514         intel_guc_ucode_fini(dev);
 515         drm_irq_uninstall(dev);
 516         intel_teardown_gmbus(dev);
 517 cleanup_csr:
 518         intel_csr_ucode_fini(dev_priv);
 519         intel_power_domains_fini(dev_priv);
 520         vga_switcheroo_unregister_client(dev->pdev);
 521 cleanup_vga_client:
 522         vga_client_register(dev->pdev, NULL, NULL, NULL);
 523 out:
 524         return ret;
 525 }
 526
 527 #if IS_ENABLED(CONFIG_FB)
 528 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 529 {
 530         struct apertures_struct *ap;
 531         struct pci_dev *pdev = dev_priv->dev->pdev;
 532         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 533         bool primary;
 534         int ret;
 535
 536         ap = alloc_apertures(1);
 537         if (!ap)
 538                 return -ENOMEM;
 539
 540         ap->ranges[0].base = ggtt->mappable_base;
 541         ap->ranges[0].size = ggtt->mappable_end;
 542
 543         primary =
 544                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 545
 546         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 547
 548         kfree(ap);
 549
 550         return ret;
 551 }
 552 #else
 553 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 554 {
 555         return 0;
 556 }
 557 #endif
 558
 559 #if !defined(CONFIG_VGA_CONSOLE)
 560 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 561 {
 562         return 0;
 563 }
 564 #elif !defined(CONFIG_DUMMY_CONSOLE)
 565 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 566 {
 567         return -ENODEV;
 568 }
 569 #else
 570 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 571 {
 572         int ret = 0;
 573
 574         DRM_INFO("Replacing VGA console driver\n");
 575
 576         console_lock();
 577         if (con_is_bound(&vga_con))
 578                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 579         if (ret == 0) {
 580                 ret = do_unregister_con_driver(&vga_con);
 581
 582                 /* Ignore "already unregistered". */
 583                 if (ret == -ENODEV)
 584                         ret = 0;
 585         }
 586         console_unlock();
 587
 588         return ret;
 589 }
 590 #endif
 591
 592 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 593 {
 594         const struct intel_device_info *info = &dev_priv->info;
 595
 596 #define PRINT_S(name) "%s"
 597 #define SEP_EMPTY
 598 #define PRINT_FLAG(name) info->name ? #name "," : ""
 599 #define SEP_COMMA ,
 600         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 601                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 602                          info->gen,
 603                          dev_priv->dev->pdev->device,
 604                          dev_priv->dev->pdev->revision,
 605                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 606 #undef PRINT_S
 607 #undef SEP_EMPTY
 608 #undef PRINT_FLAG
 609 #undef SEP_COMMA
 610 }
 611
 612 static void cherryview_sseu_info_init(struct drm_device *dev)
 613 {
 614         struct drm_i915_private *dev_priv = dev->dev_private;
 615         struct intel_device_info *info;
 616         u32 fuse, eu_dis;
 617
 618         info = (struct intel_device_info *)&dev_priv->info;
 619         fuse = I915_READ(CHV_FUSE_GT);
 620
 621         info->slice_total = 1;
 622
 623         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 624                 info->subslice_per_slice++;
 625                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 626                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 627                 info->eu_total += 8 - hweight32(eu_dis);
 628         }
 629
 630         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 631                 info->subslice_per_slice++;
 632                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 633                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 634                 info->eu_total += 8 - hweight32(eu_dis);
 635         }
 636
 637         info->subslice_total = info->subslice_per_slice;
 638         /*
 639          * CHV expected to always have a uniform distribution of EU
 640          * across subslices.
 641         */
 642         info->eu_per_subslice = info->subslice_total ?
 643                                 info->eu_total / info->subslice_total :
 644                                 0;
 645         /*
 646          * CHV supports subslice power gating on devices with more than
 647          * one subslice, and supports EU power gating on devices with
 648          * more than one EU pair per subslice.
 649         */
 650         info->has_slice_pg = 0;
 651         info->has_subslice_pg = (info->subslice_total > 1);
 652         info->has_eu_pg = (info->eu_per_subslice > 2);
 653 }
 654
 655 static void gen9_sseu_info_init(struct drm_device *dev)
 656 {
 657         struct drm_i915_private *dev_priv = dev->dev_private;
 658         struct intel_device_info *info;
 659         int s_max = 3, ss_max = 4, eu_max = 8;
 660         int s, ss;
 661         u32 fuse2, s_enable, ss_disable, eu_disable;
 662         u8 eu_mask = 0xff;
 663
 664         info = (struct intel_device_info *)&dev_priv->info;
 665         fuse2 = I915_READ(GEN8_FUSE2);
 666         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
 667                    GEN8_F2_S_ENA_SHIFT;
 668         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 669                      GEN9_F2_SS_DIS_SHIFT;
 670
 671         info->slice_total = hweight32(s_enable);
 672         /*
 673          * The subslice disable field is global, i.e. it applies
 674          * to each of the enabled slices.
 675         */
 676         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 677         info->subslice_total = info->slice_total *
 678                                info->subslice_per_slice;
 679
 680         /*
 681          * Iterate through enabled slices and subslices to
 682          * count the total enabled EU.
 683         */
 684         for (s = 0; s < s_max; s++) {
 685                 if (!(s_enable & (0x1 << s)))
 686                         /* skip disabled slice */
 687                         continue;
 688
 689                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 690                 for (ss = 0; ss < ss_max; ss++) {
 691                         int eu_per_ss;
 692
 693                         if (ss_disable & (0x1 << ss))
 694                                 /* skip disabled subslice */
 695                                 continue;
 696
 697                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 698                                                       eu_mask);
 699
 700                         /*
 701                          * Record which subslice(s) has(have) 7 EUs. we
 702                          * can tune the hash used to spread work among
 703                          * subslices if they are unbalanced.
 704                          */
 705                         if (eu_per_ss == 7)
 706                                 info->subslice_7eu[s] |= 1 << ss;
 707
 708                         info->eu_total += eu_per_ss;
 709                 }
 710         }
 711
 712         /*
 713          * SKL is expected to always have a uniform distribution
 714          * of EU across subslices with the exception that any one
 715          * EU in any one subslice may be fused off for die
 716          * recovery. BXT is expected to be perfectly uniform in EU
 717          * distribution.
 718         */
 719         info->eu_per_subslice = info->subslice_total ?
 720                                 DIV_ROUND_UP(info->eu_total,
 721                                              info->subslice_total) : 0;
 722         /*
 723          * SKL supports slice power gating on devices with more than
 724          * one slice, and supports EU power gating on devices with
 725          * more than one EU pair per subslice. BXT supports subslice
 726          * power gating on devices with more than one subslice, and
 727          * supports EU power gating on devices with more than one EU
 728          * pair per subslice.
 729         */
 730         info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
 731                                (info->slice_total > 1));
 732         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 733         info->has_eu_pg = (info->eu_per_subslice > 2);
 734 }
 735
 736 static void broadwell_sseu_info_init(struct drm_device *dev)
 737 {
 738         struct drm_i915_private *dev_priv = dev->dev_private;
 739         struct intel_device_info *info;
 740         const int s_max = 3, ss_max = 3, eu_max = 8;
 741         int s, ss;
 742         u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
 743
 744         fuse2 = I915_READ(GEN8_FUSE2);
 745         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 746         ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
 747
 748         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
 749         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
 750                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
 751                          (32 - GEN8_EU_DIS0_S1_SHIFT));
 752         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
 753                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
 754                          (32 - GEN8_EU_DIS1_S2_SHIFT));
 755
 756
 757         info = (struct intel_device_info *)&dev_priv->info;
 758         info->slice_total = hweight32(s_enable);
 759
 760         /*
 761          * The subslice disable field is global, i.e. it applies
 762          * to each of the enabled slices.
 763          */
 764         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 765         info->subslice_total = info->slice_total * info->subslice_per_slice;
 766
 767         /*
 768          * Iterate through enabled slices and subslices to
 769          * count the total enabled EU.
 770          */
 771         for (s = 0; s < s_max; s++) {
 772                 if (!(s_enable & (0x1 << s)))
 773                         /* skip disabled slice */
 774                         continue;
 775
 776                 for (ss = 0; ss < ss_max; ss++) {
 777                         u32 n_disabled;
 778
 779                         if (ss_disable & (0x1 << ss))
 780                                 /* skip disabled subslice */
 781                                 continue;
 782
 783                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
 784
 785                         /*
 786                          * Record which subslices have 7 EUs.
 787                          */
 788                         if (eu_max - n_disabled == 7)
 789                                 info->subslice_7eu[s] |= 1 << ss;
 790
 791                         info->eu_total += eu_max - n_disabled;
 792                 }
 793         }
 794
 795         /*
 796          * BDW is expected to always have a uniform distribution of EU across
 797          * subslices with the exception that any one EU in any one subslice may
 798          * be fused off for die recovery.
 799          */
 800         info->eu_per_subslice = info->subslice_total ?
 801                 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
 802
 803         /*
 804          * BDW supports slice power gating on devices with more than
 805          * one slice.
 806          */
 807         info->has_slice_pg = (info->slice_total > 1);
 808         info->has_subslice_pg = 0;
 809         info->has_eu_pg = 0;
 810 }
 811
 812 /*
 813  * Determine various intel_device_info fields at runtime.
 814  *
 815  * Use it when either:
 816  *   - it's judged too laborious to fill n static structures with the limit
 817  *     when a simple if statement does the job,
 818  *   - run-time checks (eg read fuse/strap registers) are needed.
 819  *
 820  * This function needs to be called:
 821  *   - after the MMIO has been setup as we are reading registers,
 822  *   - after the PCH has been detected,
 823  *   - before the first usage of the fields it can tweak.
 824  */
 825 static void intel_device_info_runtime_init(struct drm_device *dev)
 826 {
 827         struct drm_i915_private *dev_priv = dev->dev_private;
 828         struct intel_device_info *info;
 829         enum pipe pipe;
 830
 831         info = (struct intel_device_info *)&dev_priv->info;
 832
 833         /*
 834          * Skylake and Broxton currently don't expose the topmost plane as its
 835          * use is exclusive with the legacy cursor and we only want to expose
 836          * one of those, not both. Until we can safely expose the topmost plane
 837          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 838          * we don't expose the topmost plane at all to prevent ABI breakage
 839          * down the line.
 840          */
 841         if (IS_BROXTON(dev)) {
 842                 info->num_sprites[PIPE_A] = 2;
 843                 info->num_sprites[PIPE_B] = 2;
 844                 info->num_sprites[PIPE_C] = 1;
 845         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 846                 for_each_pipe(dev_priv, pipe)
 847                         info->num_sprites[pipe] = 2;
 848         else
 849                 for_each_pipe(dev_priv, pipe)
 850                         info->num_sprites[pipe] = 1;
 851
 852         if (i915.disable_display) {
 853                 DRM_INFO("Display disabled (module parameter)\n");
 854                 info->num_pipes = 0;
 855         } else if (info->num_pipes > 0 &&
 856                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 857                    HAS_PCH_SPLIT(dev)) {
 858                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 859                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 860
 861                 /*
 862                  * SFUSE_STRAP is supposed to have a bit signalling the display
 863                  * is fused off. Unfortunately it seems that, at least in
 864                  * certain cases, fused off display means that PCH display
 865                  * reads don't land anywhere. In that case, we read 0s.
 866                  *
 867                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 868                  * should be set when taking over after the firmware.
 869                  */
 870                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 871                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 872                     (dev_priv->pch_type == PCH_CPT &&
 873                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 874                         DRM_INFO("Display fused off, disabling\n");
 875                         info->num_pipes = 0;
 876                 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
 877                         DRM_INFO("PipeC fused off\n");
 878                         info->num_pipes -= 1;
 879                 }
 880         } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
 881                 u32 dfsm = I915_READ(SKL_DFSM);
 882                 u8 disabled_mask = 0;
 883                 bool invalid;
 884                 int num_bits;
 885
 886                 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
 887                         disabled_mask |= BIT(PIPE_A);
 888                 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
 889                         disabled_mask |= BIT(PIPE_B);
 890                 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
 891                         disabled_mask |= BIT(PIPE_C);
 892
 893                 num_bits = hweight8(disabled_mask);
 894
 895                 switch (disabled_mask) {
 896                 case BIT(PIPE_A):
 897                 case BIT(PIPE_B):
 898                 case BIT(PIPE_A) | BIT(PIPE_B):
 899                 case BIT(PIPE_A) | BIT(PIPE_C):
 900                         invalid = true;
 901                         break;
 902                 default:
 903                         invalid = false;
 904                 }
 905
 906                 if (num_bits > info->num_pipes || invalid)
 907                         DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
 908                                   disabled_mask);
 909                 else
 910                         info->num_pipes -= num_bits;
 911         }
 912
 913         /* Initialize slice/subslice/EU info */
 914         if (IS_CHERRYVIEW(dev))
 915                 cherryview_sseu_info_init(dev);
 916         else if (IS_BROADWELL(dev))
 917                 broadwell_sseu_info_init(dev);
 918         else if (INTEL_INFO(dev)->gen >= 9)
 919                 gen9_sseu_info_init(dev);
 920
 921         /* Snooping is broken on BXT A stepping. */
 922         info->has_snoop = !info->has_llc;
 923         info->has_snoop &= !IS_BXT_REVID(dev, 0, BXT_REVID_A1);
 924
 925         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
 926         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
 927         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
 928         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
 929         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
 930         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 931                          info->has_slice_pg ? "y" : "n");
 932         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 933                          info->has_subslice_pg ? "y" : "n");
 934         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 935                          info->has_eu_pg ? "y" : "n");
 936 }
 937
 938 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 939 {
 940         /*
 941          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 942          * CHV x1 PHY (DP/HDMI D)
 943          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 944          */
 945         if (IS_CHERRYVIEW(dev_priv)) {
 946                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 947                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 948         } else if (IS_VALLEYVIEW(dev_priv)) {
 949                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 950         }
 951 }
 952
 953 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 954 {
 955         /*
 956          * The i915 workqueue is primarily used for batched retirement of
 957          * requests (and thus managing bo) once the task has been completed
 958          * by the GPU. i915_gem_retire_requests() is called directly when we
 959          * need high-priority retirement, such as waiting for an explicit
 960          * bo.
 961          *
 962          * It is also used for periodic low-priority events, such as
 963          * idle-timers and recording error state.
 964          *
 965          * All tasks on the workqueue are expected to acquire the dev mutex
 966          * so there is no point in running more than one instance of the
 967          * workqueue at any time.  Use an ordered one.
 968          */
 969         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 970         if (dev_priv->wq == NULL)
 971                 goto out_err;
 972
 973         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 974         if (dev_priv->hotplug.dp_wq == NULL)
 975                 goto out_free_wq;
 976
 977         dev_priv->gpu_error.hangcheck_wq =
 978                 alloc_ordered_workqueue("i915-hangcheck", 0);
 979         if (dev_priv->gpu_error.hangcheck_wq == NULL)
 980                 goto out_free_dp_wq;
 981
 982         return 0;
 983
 984 out_free_dp_wq:
 985         destroy_workqueue(dev_priv->hotplug.dp_wq);
 986 out_free_wq:
 987         destroy_workqueue(dev_priv->wq);
 988 out_err:
 989         DRM_ERROR("Failed to allocate workqueues.\n");
 990
 991         return -ENOMEM;
 992 }
 993
 994 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 995 {
 996         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
 997         destroy_workqueue(dev_priv->hotplug.dp_wq);
 998         destroy_workqueue(dev_priv->wq);
 999 }
1000
1001 /**
1002  * i915_driver_init_early - setup state not requiring device access
1003  * @dev_priv: device private
1004  *
1005  * Initialize everything that is a "SW-only" state, that is state not
1006  * requiring accessing the device or exposing the driver via kernel internal
1007  * or userspace interfaces. Example steps belonging here: lock initialization,
1008  * system memory allocation, setting up device specific attributes and
1009  * function hooks not requiring accessing the device.
1010  */
1011 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
1012                                   struct drm_device *dev,
1013                                   struct intel_device_info *info)
1014 {
1015         struct intel_device_info *device_info;
1016         int ret = 0;
1017
1018         if (i915_inject_load_failure())
1019                 return -ENODEV;
1020
1021         /* Setup the write-once "constant" device info */
1022         device_info = (struct intel_device_info *)&dev_priv->info;
1023         memcpy(device_info, info, sizeof(dev_priv->info));
1024         device_info->device_id = dev->pdev->device;
1025
1026         spin_lock_init(&dev_priv->irq_lock);
1027         spin_lock_init(&dev_priv->gpu_error.lock);
1028         mutex_init(&dev_priv->backlight_lock);
1029         spin_lock_init(&dev_priv->uncore.lock);
1030         spin_lock_init(&dev_priv->mm.object_stat_lock);
1031         spin_lock_init(&dev_priv->mmio_flip_lock);
1032         mutex_init(&dev_priv->sb_lock);
1033         mutex_init(&dev_priv->modeset_restore_lock);
1034         mutex_init(&dev_priv->av_mutex);
1035         mutex_init(&dev_priv->wm.wm_mutex);
1036         mutex_init(&dev_priv->pps_mutex);
1037
1038         ret = i915_workqueues_init(dev_priv);
1039         if (ret < 0)
1040                 return ret;
1041
1042         /* This must be called before any calls to HAS_PCH_* */
1043         intel_detect_pch(dev);
1044
1045         intel_pm_setup(dev);
1046         intel_init_dpio(dev_priv);
1047         intel_power_domains_init(dev_priv);
1048         intel_irq_init(dev_priv);
1049         intel_init_display_hooks(dev_priv);
1050         intel_init_clock_gating_hooks(dev_priv);
1051         intel_init_audio_hooks(dev_priv);
1052         i915_gem_load_init(dev);
1053
1054         intel_display_crc_init(dev);
1055
1056         i915_dump_device_info(dev_priv);
1057
1058         /* Not all pre-production machines fall into this category, only the
1059          * very first ones. Almost everything should work, except for maybe
1060          * suspend/resume. And we don't implement workarounds that affect only
1061          * pre-production machines. */
1062         if (IS_HSW_EARLY_SDV(dev))
1063                 DRM_INFO("This is an early pre-production Haswell machine. "
1064                          "It may not be fully functional.\n");
1065
1066         return 0;
1067 }
1068
1069 /**
1070  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
1071  * @dev_priv: device private
1072  */
1073 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
1074 {
1075         i915_gem_load_cleanup(dev_priv->dev);
1076         i915_workqueues_cleanup(dev_priv);
1077 }
1078
1079 static int i915_mmio_setup(struct drm_device *dev)
1080 {
1081         struct drm_i915_private *dev_priv = to_i915(dev);
1082         int mmio_bar;
1083         int mmio_size;
1084
1085         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1086         /*
1087          * Before gen4, the registers and the GTT are behind different BARs.
1088          * However, from gen4 onwards, the registers and the GTT are shared
1089          * in the same BAR, so we want to restrict this ioremap from
1090          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1091          * the register BAR remains the same size for all the earlier
1092          * generations up to Ironlake.
1093          */
1094         if (INTEL_INFO(dev)->gen < 5)
1095                 mmio_size = 512 * 1024;
1096         else
1097                 mmio_size = 2 * 1024 * 1024;
1098         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1099         if (dev_priv->regs == NULL) {
1100                 DRM_ERROR("failed to map registers\n");
1101
1102                 return -EIO;
1103         }
1104
1105         /* Try to make sure MCHBAR is enabled before poking at it */
1106         intel_setup_mchbar(dev);
1107
1108         return 0;
1109 }
1110
1111 static void i915_mmio_cleanup(struct drm_device *dev)
1112 {
1113         struct drm_i915_private *dev_priv = to_i915(dev);
1114
1115         intel_teardown_mchbar(dev);
1116         pci_iounmap(dev->pdev, dev_priv->regs);
1117 }
1118
1119 /**
1120  * i915_driver_init_mmio - setup device MMIO
1121  * @dev_priv: device private
1122  *
1123  * Setup minimal device state necessary for MMIO accesses later in the
1124  * initialization sequence. The setup here should avoid any other device-wide
1125  * side effects or exposing the driver via kernel internal or user space
1126  * interfaces.
1127  */
1128 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1129 {
1130         struct drm_device *dev = dev_priv->dev;
1131         int ret;
1132
1133         if (i915_inject_load_failure())
1134                 return -ENODEV;
1135
1136         if (i915_get_bridge_dev(dev))
1137                 return -EIO;
1138
1139         ret = i915_mmio_setup(dev);
1140         if (ret < 0)
1141                 goto put_bridge;
1142
1143         intel_uncore_init(dev);
1144
1145         return 0;
1146
1147 put_bridge:
1148         pci_dev_put(dev_priv->bridge_dev);
1149
1150         return ret;
1151 }
1152
1153 /**
1154  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1155  * @dev_priv: device private
1156  */
1157 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160
1161         intel_uncore_fini(dev);
1162         i915_mmio_cleanup(dev);
1163         pci_dev_put(dev_priv->bridge_dev);
1164 }
1165
1166 /**
1167  * i915_driver_init_hw - setup state requiring device access
1168  * @dev_priv: device private
1169  *
1170  * Setup state that requires accessing the device, but doesn't require
1171  * exposing the driver via kernel internal or userspace interfaces.
1172  */
1173 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1174 {
1175         struct drm_device *dev = dev_priv->dev;
1176         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1177         uint32_t aperture_size;
1178         int ret;
1179
1180         if (i915_inject_load_failure())
1181                 return -ENODEV;
1182
1183         intel_device_info_runtime_init(dev);
1184
1185         ret = i915_ggtt_init_hw(dev);
1186         if (ret)
1187                 return ret;
1188
1189         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1190          * otherwise the vga fbdev driver falls over. */
1191         ret = i915_kick_out_firmware_fb(dev_priv);
1192         if (ret) {
1193                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1194                 goto out_ggtt;
1195         }
1196
1197         ret = i915_kick_out_vgacon(dev_priv);
1198         if (ret) {
1199                 DRM_ERROR("failed to remove conflicting VGA console\n");
1200                 goto out_ggtt;
1201         }
1202
1203         pci_set_master(dev->pdev);
1204
1205         /* overlay on gen2 is broken and can't address above 1G */
1206         if (IS_GEN2(dev))
1207                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1208
1209         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1210          * using 32bit addressing, overwriting memory if HWS is located
1211          * above 4GB.
1212          *
1213          * The documentation also mentions an issue with undefined
1214          * behaviour if any general state is accessed within a page above 4GB,
1215          * which also needs to be handled carefully.
1216          */
1217         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1218                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1219
1220         aperture_size = ggtt->mappable_end;
1221
1222         ggtt->mappable =
1223                 io_mapping_create_wc(ggtt->mappable_base,
1224                                      aperture_size);
1225         if (!ggtt->mappable) {
1226                 ret = -EIO;
1227                 goto out_ggtt;
1228         }
1229
1230         ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
1231                                               aperture_size);
1232
1233         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1234                            PM_QOS_DEFAULT_VALUE);
1235
1236         intel_uncore_sanitize(dev);
1237
1238         intel_opregion_setup(dev);
1239
1240         i915_gem_load_init_fences(dev_priv);
1241
1242         /* On the 945G/GM, the chipset reports the MSI capability on the
1243          * integrated graphics even though the support isn't actually there
1244          * according to the published specs.  It doesn't appear to function
1245          * correctly in testing on 945G.
1246          * This may be a side effect of MSI having been made available for PEG
1247          * and the registers being closely associated.
1248          *
1249          * According to chipset errata, on the 965GM, MSI interrupts may
1250          * be lost or delayed, but we use them anyways to avoid
1251          * stuck interrupts on some machines.
1252          */
1253         if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1254                 if (pci_enable_msi(dev->pdev) < 0)
1255                         DRM_DEBUG_DRIVER("can't enable MSI");
1256         }
1257
1258         return 0;
1259
1260 out_ggtt:
1261         i915_ggtt_cleanup_hw(dev);
1262
1263         return ret;
1264 }
1265
1266 /**
1267  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1268  * @dev_priv: device private
1269  */
1270 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1271 {
1272         struct drm_device *dev = dev_priv->dev;
1273         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1274
1275         if (dev->pdev->msi_enabled)
1276                 pci_disable_msi(dev->pdev);
1277
1278         pm_qos_remove_request(&dev_priv->pm_qos);
1279         arch_phys_wc_del(ggtt->mtrr);
1280         io_mapping_free(ggtt->mappable);
1281         i915_ggtt_cleanup_hw(dev);
1282 }
1283
1284 /**
1285  * i915_driver_register - register the driver with the rest of the system
1286  * @dev_priv: device private
1287  *
1288  * Perform any steps necessary to make the driver available via kernel
1289  * internal or userspace interfaces.
1290  */
1291 static void i915_driver_register(struct drm_i915_private *dev_priv)
1292 {
1293         struct drm_device *dev = dev_priv->dev;
1294
1295         i915_gem_shrinker_init(dev_priv);
1296         /*
1297          * Notify a valid surface after modesetting,
1298          * when running inside a VM.
1299          */
1300         if (intel_vgpu_active(dev))
1301                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1302
1303         i915_setup_sysfs(dev);
1304
1305         if (INTEL_INFO(dev_priv)->num_pipes) {
1306                 /* Must be done after probing outputs */
1307                 intel_opregion_init(dev);
1308                 acpi_video_register();
1309         }
1310
1311         if (IS_GEN5(dev_priv))
1312                 intel_gpu_ips_init(dev_priv);
1313
1314         i915_audio_component_init(dev_priv);
1315 }
1316
1317 /**
1318  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1319  * @dev_priv: device private
1320  */
1321 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1322 {
1323         i915_audio_component_cleanup(dev_priv);
1324         intel_gpu_ips_teardown();
1325         acpi_video_unregister();
1326         intel_opregion_fini(dev_priv->dev);
1327         i915_teardown_sysfs(dev_priv->dev);
1328         i915_gem_shrinker_cleanup(dev_priv);
1329 }
1330
1331 /**
1332  * i915_driver_load - setup chip and create an initial config
1333  * @dev: DRM device
1334  * @flags: startup flags
1335  *
1336  * The driver load routine has to do several things:
1337  *   - drive output discovery via intel_modeset_init()
1338  *   - initialize the memory manager
1339  *   - allocate initial config memory
1340  *   - setup the DRM framebuffer with the allocated memory
1341  */
1342 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1343 {
1344         struct drm_i915_private *dev_priv;
1345         int ret = 0;
1346
1347         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1348         if (dev_priv == NULL)
1349                 return -ENOMEM;
1350
1351         dev->dev_private = dev_priv;
1352         /* Must be set before calling __i915_printk */
1353         dev_priv->dev = dev;
1354
1355         ret = i915_driver_init_early(dev_priv, dev,
1356                                      (struct intel_device_info *)flags);
1357
1358         if (ret < 0)
1359                 goto out_free_priv;
1360
1361         intel_runtime_pm_get(dev_priv);
1362
1363         ret = i915_driver_init_mmio(dev_priv);
1364         if (ret < 0)
1365                 goto out_runtime_pm_put;
1366
1367         ret = i915_driver_init_hw(dev_priv);
1368         if (ret < 0)
1369                 goto out_cleanup_mmio;
1370
1371         /*
1372          * TODO: move the vblank init and parts of modeset init steps into one
1373          * of the i915_driver_init_/i915_driver_register functions according
1374          * to the role/effect of the given init step.
1375          */
1376         if (INTEL_INFO(dev)->num_pipes) {
1377                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1378                 if (ret)
1379                         goto out_cleanup_hw;
1380         }
1381
1382         ret = i915_load_modeset_init(dev);
1383         if (ret < 0)
1384                 goto out_cleanup_vblank;
1385
1386         i915_driver_register(dev_priv);
1387
1388         intel_runtime_pm_enable(dev_priv);
1389
1390         intel_runtime_pm_put(dev_priv);
1391
1392         return 0;
1393
1394 out_cleanup_vblank:
1395         drm_vblank_cleanup(dev);
1396 out_cleanup_hw:
1397         i915_driver_cleanup_hw(dev_priv);
1398 out_cleanup_mmio:
1399         i915_driver_cleanup_mmio(dev_priv);
1400 out_runtime_pm_put:
1401         intel_runtime_pm_put(dev_priv);
1402         i915_driver_cleanup_early(dev_priv);
1403 out_free_priv:
1404         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1405
1406         kfree(dev_priv);
1407
1408         return ret;
1409 }
1410
1411 int i915_driver_unload(struct drm_device *dev)
1412 {
1413         struct drm_i915_private *dev_priv = dev->dev_private;
1414         int ret;
1415
1416         intel_fbdev_fini(dev);
1417
1418         ret = i915_gem_suspend(dev);
1419         if (ret) {
1420                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1421                 return ret;
1422         }
1423
1424         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1425
1426         i915_driver_unregister(dev_priv);
1427
1428         drm_vblank_cleanup(dev);
1429
1430         intel_modeset_cleanup(dev);
1431
1432         /*
1433          * free the memory space allocated for the child device
1434          * config parsed from VBT
1435          */
1436         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1437                 kfree(dev_priv->vbt.child_dev);
1438                 dev_priv->vbt.child_dev = NULL;
1439                 dev_priv->vbt.child_dev_num = 0;
1440         }
1441         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1442         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1443         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1444         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1445
1446         vga_switcheroo_unregister_client(dev->pdev);
1447         vga_client_register(dev->pdev, NULL, NULL, NULL);
1448
1449         intel_csr_ucode_fini(dev_priv);
1450
1451         /* Free error state after interrupts are fully disabled. */
1452         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1453         i915_destroy_error_state(dev);
1454
1455         /* Flush any outstanding unpin_work. */
1456         flush_workqueue(dev_priv->wq);
1457
1458         intel_guc_ucode_fini(dev);
1459         mutex_lock(&dev->struct_mutex);
1460         i915_gem_cleanup_engines(dev);
1461         i915_gem_context_fini(dev);
1462         mutex_unlock(&dev->struct_mutex);
1463         intel_fbc_cleanup_cfb(dev_priv);
1464
1465         intel_power_domains_fini(dev_priv);
1466
1467         i915_driver_cleanup_hw(dev_priv);
1468         i915_driver_cleanup_mmio(dev_priv);
1469
1470         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1471
1472         i915_driver_cleanup_early(dev_priv);
1473         kfree(dev_priv);
1474
1475         return 0;
1476 }
1477
1478 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1479 {
1480         int ret;
1481
1482         ret = i915_gem_open(dev, file);
1483         if (ret)
1484                 return ret;
1485
1486         return 0;
1487 }
1488
1489 /**
1490  * i915_driver_lastclose - clean up after all DRM clients have exited
1491  * @dev: DRM device
1492  *
1493  * Take care of cleaning up after all DRM clients have exited.  In the
1494  * mode setting case, we want to restore the kernel's initial mode (just
1495  * in case the last client left us in a bad state).
1496  *
1497  * Additionally, in the non-mode setting case, we'll tear down the GTT
1498  * and DMA structures, since the kernel won't be using them, and clea
1499  * up any GEM state.
1500  */
1501 void i915_driver_lastclose(struct drm_device *dev)
1502 {
1503         intel_fbdev_restore_mode(dev);
1504         vga_switcheroo_process_delayed_switch();
1505 }
1506
1507 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1508 {
1509         mutex_lock(&dev->struct_mutex);
1510         i915_gem_context_close(dev, file);
1511         i915_gem_release(dev, file);
1512         mutex_unlock(&dev->struct_mutex);
1513 }
1514
1515 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1516 {
1517         struct drm_i915_file_private *file_priv = file->driver_priv;
1518
1519         kfree(file_priv);
1520 }
1521
1522 static int
1523 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1524                           struct drm_file *file)
1525 {
1526         return -ENODEV;
1527 }
1528
1529 const struct drm_ioctl_desc i915_ioctls[] = {
1530         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1531         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1532         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1533         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1534         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1535         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1536         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1537         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1538         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1539         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1540         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1541         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1542         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1543         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1544         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1545         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1546         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1547         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1548         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1549         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
1550         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1551         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1552         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1553         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1554         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1555         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1556         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1557         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1558         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1559         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1560         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1561         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1562         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
1563         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1564         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1565         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
1566         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
1567         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1568         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1569         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1570         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1571         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1572         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
1573         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
1574         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1575         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1576         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1577         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1578         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW),
1579         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1580         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1581         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1582 };
1583
1584 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);