drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/async.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_legacy.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <linux/pci.h>
  41 #include <linux/console.h>
  42 #include <linux/vt.h>
  43 #include <linux/vgaarb.h>
  44 #include <linux/acpi.h>
  45 #include <linux/pnp.h>
  46 #include <linux/vga_switcheroo.h>
  47 #include <linux/slab.h>
  48 #include <acpi/video.h>
  49 #include <linux/pm.h>
  50 #include <linux/pm_runtime.h>
  51 #include <linux/oom.h>
  52
  53
  54 static int i915_getparam(struct drm_device *dev, void *data,
  55                          struct drm_file *file_priv)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58         drm_i915_getparam_t *param = data;
  59         int value;
  60
  61         switch (param->param) {
  62         case I915_PARAM_IRQ_ACTIVE:
  63         case I915_PARAM_ALLOW_BATCHBUFFER:
  64         case I915_PARAM_LAST_DISPATCH:
  65                 /* Reject all old ums/dri params. */
  66                 return -ENODEV;
  67         case I915_PARAM_CHIPSET_ID:
  68                 value = dev->pdev->device;
  69                 break;
  70         case I915_PARAM_HAS_GEM:
  71                 value = 1;
  72                 break;
  73         case I915_PARAM_NUM_FENCES_AVAIL:
  74                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  75                 break;
  76         case I915_PARAM_HAS_OVERLAY:
  77                 value = dev_priv->overlay ? 1 : 0;
  78                 break;
  79         case I915_PARAM_HAS_PAGEFLIPPING:
  80                 value = 1;
  81                 break;
  82         case I915_PARAM_HAS_EXECBUF2:
  83                 /* depends on GEM */
  84                 value = 1;
  85                 break;
  86         case I915_PARAM_HAS_BSD:
  87                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  88                 break;
  89         case I915_PARAM_HAS_BLT:
  90                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  91                 break;
  92         case I915_PARAM_HAS_VEBOX:
  93                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
  94                 break;
  95         case I915_PARAM_HAS_RELAXED_FENCING:
  96                 value = 1;
  97                 break;
  98         case I915_PARAM_HAS_COHERENT_RINGS:
  99                 value = 1;
 100                 break;
 101         case I915_PARAM_HAS_EXEC_CONSTANTS:
 102                 value = INTEL_INFO(dev)->gen >= 4;
 103                 break;
 104         case I915_PARAM_HAS_RELAXED_DELTA:
 105                 value = 1;
 106                 break;
 107         case I915_PARAM_HAS_GEN7_SOL_RESET:
 108                 value = 1;
 109                 break;
 110         case I915_PARAM_HAS_LLC:
 111                 value = HAS_LLC(dev);
 112                 break;
 113         case I915_PARAM_HAS_WT:
 114                 value = HAS_WT(dev);
 115                 break;
 116         case I915_PARAM_HAS_ALIASING_PPGTT:
 117                 value = USES_PPGTT(dev);
 118                 break;
 119         case I915_PARAM_HAS_WAIT_TIMEOUT:
 120                 value = 1;
 121                 break;
 122         case I915_PARAM_HAS_SEMAPHORES:
 123                 value = i915_semaphore_is_enabled(dev);
 124                 break;
 125         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 126                 value = 1;
 127                 break;
 128         case I915_PARAM_HAS_SECURE_BATCHES:
 129                 value = capable(CAP_SYS_ADMIN);
 130                 break;
 131         case I915_PARAM_HAS_PINNED_BATCHES:
 132                 value = 1;
 133                 break;
 134         case I915_PARAM_HAS_EXEC_NO_RELOC:
 135                 value = 1;
 136                 break;
 137         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 138                 value = 1;
 139                 break;
 140         case I915_PARAM_CMD_PARSER_VERSION:
 141                 value = i915_cmd_parser_get_version();
 142                 break;
 143         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 144                 value = 1;
 145                 break;
 146         default:
 147                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 148                 return -EINVAL;
 149         }
 150
 151         if (copy_to_user(param->value, &value, sizeof(int))) {
 152                 DRM_ERROR("copy_to_user failed\n");
 153                 return -EFAULT;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static int i915_setparam(struct drm_device *dev, void *data,
 160                          struct drm_file *file_priv)
 161 {
 162         struct drm_i915_private *dev_priv = dev->dev_private;
 163         drm_i915_setparam_t *param = data;
 164
 165         switch (param->param) {
 166         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 167         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 168         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 169                 /* Reject all old ums/dri params. */
 170                 return -ENODEV;
 171
 172         case I915_SETPARAM_NUM_USED_FENCES:
 173                 if (param->value > dev_priv->num_fence_regs ||
 174                     param->value < 0)
 175                         return -EINVAL;
 176                 /* Userspace can use first N regs */
 177                 dev_priv->fence_reg_start = param->value;
 178                 break;
 179         default:
 180                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 181                                         param->param);
 182                 return -EINVAL;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static int i915_get_bridge_dev(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191
 192         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 193         if (!dev_priv->bridge_dev) {
 194                 DRM_ERROR("bridge device not found\n");
 195                 return -1;
 196         }
 197         return 0;
 198 }
 199
 200 #define MCHBAR_I915 0x44
 201 #define MCHBAR_I965 0x48
 202 #define MCHBAR_SIZE (4*4096)
 203
 204 #define DEVEN_REG 0x54
 205 #define   DEVEN_MCHBAR_EN (1 << 28)
 206
 207 /* Allocate space for the MCH regs if needed, return nonzero on error */
 208 static int
 209 intel_alloc_mchbar_resource(struct drm_device *dev)
 210 {
 211         struct drm_i915_private *dev_priv = dev->dev_private;
 212         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 213         u32 temp_lo, temp_hi = 0;
 214         u64 mchbar_addr;
 215         int ret;
 216
 217         if (INTEL_INFO(dev)->gen >= 4)
 218                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 219         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 220         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 221
 222         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 223 #ifdef CONFIG_PNP
 224         if (mchbar_addr &&
 225             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 226                 return 0;
 227 #endif
 228
 229         /* Get some space for it */
 230         dev_priv->mch_res.name = "i915 MCHBAR";
 231         dev_priv->mch_res.flags = IORESOURCE_MEM;
 232         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 233                                      &dev_priv->mch_res,
 234                                      MCHBAR_SIZE, MCHBAR_SIZE,
 235                                      PCIBIOS_MIN_MEM,
 236                                      0, pcibios_align_resource,
 237                                      dev_priv->bridge_dev);
 238         if (ret) {
 239                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 240                 dev_priv->mch_res.start = 0;
 241                 return ret;
 242         }
 243
 244         if (INTEL_INFO(dev)->gen >= 4)
 245                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 246                                        upper_32_bits(dev_priv->mch_res.start));
 247
 248         pci_write_config_dword(dev_priv->bridge_dev, reg,
 249                                lower_32_bits(dev_priv->mch_res.start));
 250         return 0;
 251 }
 252
 253 /* Setup MCHBAR if possible, return true if we should disable it again */
 254 static void
 255 intel_setup_mchbar(struct drm_device *dev)
 256 {
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 259         u32 temp;
 260         bool enabled;
 261
 262         if (IS_VALLEYVIEW(dev))
 263                 return;
 264
 265         dev_priv->mchbar_need_disable = false;
 266
 267         if (IS_I915G(dev) || IS_I915GM(dev)) {
 268                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 269                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 270         } else {
 271                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 272                 enabled = temp & 1;
 273         }
 274
 275         /* If it's already enabled, don't have to do anything */
 276         if (enabled)
 277                 return;
 278
 279         if (intel_alloc_mchbar_resource(dev))
 280                 return;
 281
 282         dev_priv->mchbar_need_disable = true;
 283
 284         /* Space is allocated or reserved, so enable it. */
 285         if (IS_I915G(dev) || IS_I915GM(dev)) {
 286                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 287                                        temp | DEVEN_MCHBAR_EN);
 288         } else {
 289                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 290                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 291         }
 292 }
 293
 294 static void
 295 intel_teardown_mchbar(struct drm_device *dev)
 296 {
 297         struct drm_i915_private *dev_priv = dev->dev_private;
 298         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 299         u32 temp;
 300
 301         if (dev_priv->mchbar_need_disable) {
 302                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 303                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 304                         temp &= ~DEVEN_MCHBAR_EN;
 305                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 306                 } else {
 307                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 308                         temp &= ~1;
 309                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 310                 }
 311         }
 312
 313         if (dev_priv->mch_res.start)
 314                 release_resource(&dev_priv->mch_res);
 315 }
 316
 317 /* true = enable decode, false = disable decoder */
 318 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 319 {
 320         struct drm_device *dev = cookie;
 321
 322         intel_modeset_vga_set_state(dev, state);
 323         if (state)
 324                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 325                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 326         else
 327                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 328 }
 329
 330 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 331 {
 332         struct drm_device *dev = pci_get_drvdata(pdev);
 333         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 334
 335         if (state == VGA_SWITCHEROO_ON) {
 336                 pr_info("switched on\n");
 337                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 338                 /* i915 resume handler doesn't set to D0 */
 339                 pci_set_power_state(dev->pdev, PCI_D0);
 340                 i915_resume_legacy(dev);
 341                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 342         } else {
 343                 pr_err("switched off\n");
 344                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 345                 i915_suspend_legacy(dev, pmm);
 346                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 347         }
 348 }
 349
 350 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 351 {
 352         struct drm_device *dev = pci_get_drvdata(pdev);
 353
 354         /*
 355          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 356          * locking inversion with the driver load path. And the access here is
 357          * completely racy anyway. So don't bother with locking for now.
 358          */
 359         return dev->open_count == 0;
 360 }
 361
 362 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 363         .set_gpu_state = i915_switcheroo_set_state,
 364         .reprobe = NULL,
 365         .can_switch = i915_switcheroo_can_switch,
 366 };
 367
 368 static int i915_load_modeset_init(struct drm_device *dev)
 369 {
 370         struct drm_i915_private *dev_priv = dev->dev_private;
 371         int ret;
 372
 373         ret = intel_parse_bios(dev);
 374         if (ret)
 375                 DRM_INFO("failed to find VBIOS tables\n");
 376
 377         /* If we have > 1 VGA cards, then we need to arbitrate access
 378          * to the common VGA resources.
 379          *
 380          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 381          * then we do not take part in VGA arbitration and the
 382          * vga_client_register() fails with -ENODEV.
 383          */
 384         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 385         if (ret && ret != -ENODEV)
 386                 goto out;
 387
 388         intel_register_dsm_handler();
 389
 390         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 391         if (ret)
 392                 goto cleanup_vga_client;
 393
 394         /* Initialise stolen first so that we may reserve preallocated
 395          * objects for the BIOS to KMS transition.
 396          */
 397         ret = i915_gem_init_stolen(dev);
 398         if (ret)
 399                 goto cleanup_vga_switcheroo;
 400
 401         intel_power_domains_init_hw(dev_priv);
 402
 403         ret = intel_irq_install(dev_priv);
 404         if (ret)
 405                 goto cleanup_gem_stolen;
 406
 407         /* Important: The output setup functions called by modeset_init need
 408          * working irqs for e.g. gmbus and dp aux transfers. */
 409         intel_modeset_init(dev);
 410
 411         ret = i915_gem_init(dev);
 412         if (ret)
 413                 goto cleanup_irq;
 414
 415         intel_modeset_gem_init(dev);
 416
 417         /* Always safe in the mode setting case. */
 418         /* FIXME: do pre/post-mode set stuff in core KMS code */
 419         dev->vblank_disable_allowed = true;
 420         if (INTEL_INFO(dev)->num_pipes == 0)
 421                 return 0;
 422
 423         ret = intel_fbdev_init(dev);
 424         if (ret)
 425                 goto cleanup_gem;
 426
 427         /* Only enable hotplug handling once the fbdev is fully set up. */
 428         intel_hpd_init(dev_priv);
 429
 430         /*
 431          * Some ports require correctly set-up hpd registers for detection to
 432          * work properly (leading to ghost connected connector status), e.g. VGA
 433          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 434          * irqs are fully enabled. Now we should scan for the initial config
 435          * only once hotplug handling is enabled, but due to screwed-up locking
 436          * around kms/fbdev init we can't protect the fdbev initial config
 437          * scanning against hotplug events. Hence do this first and ignore the
 438          * tiny window where we will loose hotplug notifactions.
 439          */
 440         async_schedule(intel_fbdev_initial_config, dev_priv);
 441
 442         drm_kms_helper_poll_init(dev);
 443
 444         return 0;
 445
 446 cleanup_gem:
 447         mutex_lock(&dev->struct_mutex);
 448         i915_gem_cleanup_ringbuffer(dev);
 449         i915_gem_context_fini(dev);
 450         mutex_unlock(&dev->struct_mutex);
 451 cleanup_irq:
 452         drm_irq_uninstall(dev);
 453 cleanup_gem_stolen:
 454         i915_gem_cleanup_stolen(dev);
 455 cleanup_vga_switcheroo:
 456         vga_switcheroo_unregister_client(dev->pdev);
 457 cleanup_vga_client:
 458         vga_client_register(dev->pdev, NULL, NULL, NULL);
 459 out:
 460         return ret;
 461 }
 462
 463 #if IS_ENABLED(CONFIG_FB)
 464 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 465 {
 466         struct apertures_struct *ap;
 467         struct pci_dev *pdev = dev_priv->dev->pdev;
 468         bool primary;
 469         int ret;
 470
 471         ap = alloc_apertures(1);
 472         if (!ap)
 473                 return -ENOMEM;
 474
 475         ap->ranges[0].base = dev_priv->gtt.mappable_base;
 476         ap->ranges[0].size = dev_priv->gtt.mappable_end;
 477
 478         primary =
 479                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 480
 481         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 482
 483         kfree(ap);
 484
 485         return ret;
 486 }
 487 #else
 488 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 489 {
 490         return 0;
 491 }
 492 #endif
 493
 494 #if !defined(CONFIG_VGA_CONSOLE)
 495 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 496 {
 497         return 0;
 498 }
 499 #elif !defined(CONFIG_DUMMY_CONSOLE)
 500 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 501 {
 502         return -ENODEV;
 503 }
 504 #else
 505 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 506 {
 507         int ret = 0;
 508
 509         DRM_INFO("Replacing VGA console driver\n");
 510
 511         console_lock();
 512         if (con_is_bound(&vga_con))
 513                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 514         if (ret == 0) {
 515                 ret = do_unregister_con_driver(&vga_con);
 516
 517                 /* Ignore "already unregistered". */
 518                 if (ret == -ENODEV)
 519                         ret = 0;
 520         }
 521         console_unlock();
 522
 523         return ret;
 524 }
 525 #endif
 526
 527 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 528 {
 529         const struct intel_device_info *info = &dev_priv->info;
 530
 531 #define PRINT_S(name) "%s"
 532 #define SEP_EMPTY
 533 #define PRINT_FLAG(name) info->name ? #name "," : ""
 534 #define SEP_COMMA ,
 535         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 536                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 537                          info->gen,
 538                          dev_priv->dev->pdev->device,
 539                          dev_priv->dev->pdev->revision,
 540                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 541 #undef PRINT_S
 542 #undef SEP_EMPTY
 543 #undef PRINT_FLAG
 544 #undef SEP_COMMA
 545 }
 546
 547 /*
 548  * Determine various intel_device_info fields at runtime.
 549  *
 550  * Use it when either:
 551  *   - it's judged too laborious to fill n static structures with the limit
 552  *     when a simple if statement does the job,
 553  *   - run-time checks (eg read fuse/strap registers) are needed.
 554  *
 555  * This function needs to be called:
 556  *   - after the MMIO has been setup as we are reading registers,
 557  *   - after the PCH has been detected,
 558  *   - before the first usage of the fields it can tweak.
 559  */
 560 static void intel_device_info_runtime_init(struct drm_device *dev)
 561 {
 562         struct drm_i915_private *dev_priv = dev->dev_private;
 563         struct intel_device_info *info;
 564         enum pipe pipe;
 565
 566         info = (struct intel_device_info *)&dev_priv->info;
 567
 568         if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9)
 569                 for_each_pipe(dev_priv, pipe)
 570                         info->num_sprites[pipe] = 2;
 571         else
 572                 for_each_pipe(dev_priv, pipe)
 573                         info->num_sprites[pipe] = 1;
 574
 575         if (i915.disable_display) {
 576                 DRM_INFO("Display disabled (module parameter)\n");
 577                 info->num_pipes = 0;
 578         } else if (info->num_pipes > 0 &&
 579                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 580                    !IS_VALLEYVIEW(dev)) {
 581                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 582                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 583
 584                 /*
 585                  * SFUSE_STRAP is supposed to have a bit signalling the display
 586                  * is fused off. Unfortunately it seems that, at least in
 587                  * certain cases, fused off display means that PCH display
 588                  * reads don't land anywhere. In that case, we read 0s.
 589                  *
 590                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 591                  * should be set when taking over after the firmware.
 592                  */
 593                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 594                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 595                     (dev_priv->pch_type == PCH_CPT &&
 596                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 597                         DRM_INFO("Display fused off, disabling\n");
 598                         info->num_pipes = 0;
 599                 }
 600         }
 601 }
 602
 603 /**
 604  * i915_driver_load - setup chip and create an initial config
 605  * @dev: DRM device
 606  * @flags: startup flags
 607  *
 608  * The driver load routine has to do several things:
 609  *   - drive output discovery via intel_modeset_init()
 610  *   - initialize the memory manager
 611  *   - allocate initial config memory
 612  *   - setup the DRM framebuffer with the allocated memory
 613  */
 614 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 615 {
 616         struct drm_i915_private *dev_priv;
 617         struct intel_device_info *info, *device_info;
 618         int ret = 0, mmio_bar, mmio_size;
 619         uint32_t aperture_size;
 620
 621         info = (struct intel_device_info *) flags;
 622
 623         /* Refuse to load on gen6+ without kms enabled. */
 624         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
 625                 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
 626                 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
 627                 return -ENODEV;
 628         }
 629
 630         /* UMS needs agp support. */
 631         if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
 632                 return -EINVAL;
 633
 634         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 635         if (dev_priv == NULL)
 636                 return -ENOMEM;
 637
 638         dev->dev_private = dev_priv;
 639         dev_priv->dev = dev;
 640
 641         /* Setup the write-once "constant" device info */
 642         device_info = (struct intel_device_info *)&dev_priv->info;
 643         memcpy(device_info, info, sizeof(dev_priv->info));
 644         device_info->device_id = dev->pdev->device;
 645
 646         spin_lock_init(&dev_priv->irq_lock);
 647         spin_lock_init(&dev_priv->gpu_error.lock);
 648         mutex_init(&dev_priv->backlight_lock);
 649         spin_lock_init(&dev_priv->uncore.lock);
 650         spin_lock_init(&dev_priv->mm.object_stat_lock);
 651         spin_lock_init(&dev_priv->mmio_flip_lock);
 652         mutex_init(&dev_priv->dpio_lock);
 653         mutex_init(&dev_priv->modeset_restore_lock);
 654
 655         intel_pm_setup(dev);
 656
 657         intel_display_crc_init(dev);
 658
 659         i915_dump_device_info(dev_priv);
 660
 661         /* Not all pre-production machines fall into this category, only the
 662          * very first ones. Almost everything should work, except for maybe
 663          * suspend/resume. And we don't implement workarounds that affect only
 664          * pre-production machines. */
 665         if (IS_HSW_EARLY_SDV(dev))
 666                 DRM_INFO("This is an early pre-production Haswell machine. "
 667                          "It may not be fully functional.\n");
 668
 669         if (i915_get_bridge_dev(dev)) {
 670                 ret = -EIO;
 671                 goto free_priv;
 672         }
 673
 674         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 675         /* Before gen4, the registers and the GTT are behind different BARs.
 676          * However, from gen4 onwards, the registers and the GTT are shared
 677          * in the same BAR, so we want to restrict this ioremap from
 678          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 679          * the register BAR remains the same size for all the earlier
 680          * generations up to Ironlake.
 681          */
 682         if (info->gen < 5)
 683                 mmio_size = 512*1024;
 684         else
 685                 mmio_size = 2*1024*1024;
 686
 687         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 688         if (!dev_priv->regs) {
 689                 DRM_ERROR("failed to map registers\n");
 690                 ret = -EIO;
 691                 goto put_bridge;
 692         }
 693
 694         /* This must be called before any calls to HAS_PCH_* */
 695         intel_detect_pch(dev);
 696
 697         intel_uncore_init(dev);
 698
 699         ret = i915_gem_gtt_init(dev);
 700         if (ret)
 701                 goto out_regs;
 702
 703         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 704                 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 705                  * otherwise the vga fbdev driver falls over. */
 706                 ret = i915_kick_out_firmware_fb(dev_priv);
 707                 if (ret) {
 708                         DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 709                         goto out_gtt;
 710                 }
 711
 712                 ret = i915_kick_out_vgacon(dev_priv);
 713                 if (ret) {
 714                         DRM_ERROR("failed to remove conflicting VGA console\n");
 715                         goto out_gtt;
 716                 }
 717         }
 718
 719         pci_set_master(dev->pdev);
 720
 721         /* overlay on gen2 is broken and can't address above 1G */
 722         if (IS_GEN2(dev))
 723                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 724
 725         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
 726          * using 32bit addressing, overwriting memory if HWS is located
 727          * above 4GB.
 728          *
 729          * The documentation also mentions an issue with undefined
 730          * behaviour if any general state is accessed within a page above 4GB,
 731          * which also needs to be handled carefully.
 732          */
 733         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 734                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 735
 736         aperture_size = dev_priv->gtt.mappable_end;
 737
 738         dev_priv->gtt.mappable =
 739                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
 740                                      aperture_size);
 741         if (dev_priv->gtt.mappable == NULL) {
 742                 ret = -EIO;
 743                 goto out_gtt;
 744         }
 745
 746         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
 747                                               aperture_size);
 748
 749         /* The i915 workqueue is primarily used for batched retirement of
 750          * requests (and thus managing bo) once the task has been completed
 751          * by the GPU. i915_gem_retire_requests() is called directly when we
 752          * need high-priority retirement, such as waiting for an explicit
 753          * bo.
 754          *
 755          * It is also used for periodic low-priority events, such as
 756          * idle-timers and recording error state.
 757          *
 758          * All tasks on the workqueue are expected to acquire the dev mutex
 759          * so there is no point in running more than one instance of the
 760          * workqueue at any time.  Use an ordered one.
 761          */
 762         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 763         if (dev_priv->wq == NULL) {
 764                 DRM_ERROR("Failed to create our workqueue.\n");
 765                 ret = -ENOMEM;
 766                 goto out_mtrrfree;
 767         }
 768
 769         dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 770         if (dev_priv->dp_wq == NULL) {
 771                 DRM_ERROR("Failed to create our dp workqueue.\n");
 772                 ret = -ENOMEM;
 773                 goto out_freewq;
 774         }
 775
 776         intel_irq_init(dev_priv);
 777         intel_uncore_sanitize(dev);
 778
 779         /* Try to make sure MCHBAR is enabled before poking at it */
 780         intel_setup_mchbar(dev);
 781         intel_setup_gmbus(dev);
 782         intel_opregion_setup(dev);
 783
 784         intel_setup_bios(dev);
 785
 786         i915_gem_load(dev);
 787
 788         /* On the 945G/GM, the chipset reports the MSI capability on the
 789          * integrated graphics even though the support isn't actually there
 790          * according to the published specs.  It doesn't appear to function
 791          * correctly in testing on 945G.
 792          * This may be a side effect of MSI having been made available for PEG
 793          * and the registers being closely associated.
 794          *
 795          * According to chipset errata, on the 965GM, MSI interrupts may
 796          * be lost or delayed, but we use them anyways to avoid
 797          * stuck interrupts on some machines.
 798          */
 799         if (!IS_I945G(dev) && !IS_I945GM(dev))
 800                 pci_enable_msi(dev->pdev);
 801
 802         intel_device_info_runtime_init(dev);
 803
 804         if (INTEL_INFO(dev)->num_pipes) {
 805                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 806                 if (ret)
 807                         goto out_gem_unload;
 808         }
 809
 810         intel_power_domains_init(dev_priv);
 811
 812         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 813                 ret = i915_load_modeset_init(dev);
 814                 if (ret < 0) {
 815                         DRM_ERROR("failed to init modeset\n");
 816                         goto out_power_well;
 817                 }
 818         }
 819
 820         i915_setup_sysfs(dev);
 821
 822         if (INTEL_INFO(dev)->num_pipes) {
 823                 /* Must be done after probing outputs */
 824                 intel_opregion_init(dev);
 825                 acpi_video_register();
 826         }
 827
 828         if (IS_GEN5(dev))
 829                 intel_gpu_ips_init(dev_priv);
 830
 831         intel_runtime_pm_enable(dev_priv);
 832
 833         return 0;
 834
 835 out_power_well:
 836         intel_power_domains_fini(dev_priv);
 837         drm_vblank_cleanup(dev);
 838 out_gem_unload:
 839         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
 840         unregister_shrinker(&dev_priv->mm.shrinker);
 841
 842         if (dev->pdev->msi_enabled)
 843                 pci_disable_msi(dev->pdev);
 844
 845         intel_teardown_gmbus(dev);
 846         intel_teardown_mchbar(dev);
 847         pm_qos_remove_request(&dev_priv->pm_qos);
 848         destroy_workqueue(dev_priv->dp_wq);
 849 out_freewq:
 850         destroy_workqueue(dev_priv->wq);
 851 out_mtrrfree:
 852         arch_phys_wc_del(dev_priv->gtt.mtrr);
 853         io_mapping_free(dev_priv->gtt.mappable);
 854 out_gtt:
 855         i915_global_gtt_cleanup(dev);
 856 out_regs:
 857         intel_uncore_fini(dev);
 858         pci_iounmap(dev->pdev, dev_priv->regs);
 859 put_bridge:
 860         pci_dev_put(dev_priv->bridge_dev);
 861 free_priv:
 862         if (dev_priv->slab)
 863                 kmem_cache_destroy(dev_priv->slab);
 864         kfree(dev_priv);
 865         return ret;
 866 }
 867
 868 int i915_driver_unload(struct drm_device *dev)
 869 {
 870         struct drm_i915_private *dev_priv = dev->dev_private;
 871         int ret;
 872
 873         ret = i915_gem_suspend(dev);
 874         if (ret) {
 875                 DRM_ERROR("failed to idle hardware: %d\n", ret);
 876                 return ret;
 877         }
 878
 879         intel_power_domains_fini(dev_priv);
 880
 881         intel_gpu_ips_teardown();
 882
 883         i915_teardown_sysfs(dev);
 884
 885         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
 886         unregister_shrinker(&dev_priv->mm.shrinker);
 887
 888         io_mapping_free(dev_priv->gtt.mappable);
 889         arch_phys_wc_del(dev_priv->gtt.mtrr);
 890
 891         acpi_video_unregister();
 892
 893         if (drm_core_check_feature(dev, DRIVER_MODESET))
 894                 intel_fbdev_fini(dev);
 895
 896         drm_vblank_cleanup(dev);
 897
 898         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 899                 intel_modeset_cleanup(dev);
 900
 901                 /*
 902                  * free the memory space allocated for the child device
 903                  * config parsed from VBT
 904                  */
 905                 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
 906                         kfree(dev_priv->vbt.child_dev);
 907                         dev_priv->vbt.child_dev = NULL;
 908                         dev_priv->vbt.child_dev_num = 0;
 909                 }
 910
 911                 vga_switcheroo_unregister_client(dev->pdev);
 912                 vga_client_register(dev->pdev, NULL, NULL, NULL);
 913         }
 914
 915         /* Free error state after interrupts are fully disabled. */
 916         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
 917         cancel_work_sync(&dev_priv->gpu_error.work);
 918         i915_destroy_error_state(dev);
 919
 920         if (dev->pdev->msi_enabled)
 921                 pci_disable_msi(dev->pdev);
 922
 923         intel_opregion_fini(dev);
 924
 925         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 926                 /* Flush any outstanding unpin_work. */
 927                 flush_workqueue(dev_priv->wq);
 928
 929                 mutex_lock(&dev->struct_mutex);
 930                 i915_gem_cleanup_ringbuffer(dev);
 931                 i915_gem_context_fini(dev);
 932                 mutex_unlock(&dev->struct_mutex);
 933                 i915_gem_cleanup_stolen(dev);
 934         }
 935
 936         intel_teardown_gmbus(dev);
 937         intel_teardown_mchbar(dev);
 938
 939         destroy_workqueue(dev_priv->dp_wq);
 940         destroy_workqueue(dev_priv->wq);
 941         pm_qos_remove_request(&dev_priv->pm_qos);
 942
 943         i915_global_gtt_cleanup(dev);
 944
 945         intel_uncore_fini(dev);
 946         if (dev_priv->regs != NULL)
 947                 pci_iounmap(dev->pdev, dev_priv->regs);
 948
 949         if (dev_priv->slab)
 950                 kmem_cache_destroy(dev_priv->slab);
 951
 952         pci_dev_put(dev_priv->bridge_dev);
 953         kfree(dev_priv);
 954
 955         return 0;
 956 }
 957
 958 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 959 {
 960         int ret;
 961
 962         ret = i915_gem_open(dev, file);
 963         if (ret)
 964                 return ret;
 965
 966         return 0;
 967 }
 968
 969 /**
 970  * i915_driver_lastclose - clean up after all DRM clients have exited
 971  * @dev: DRM device
 972  *
 973  * Take care of cleaning up after all DRM clients have exited.  In the
 974  * mode setting case, we want to restore the kernel's initial mode (just
 975  * in case the last client left us in a bad state).
 976  *
 977  * Additionally, in the non-mode setting case, we'll tear down the GTT
 978  * and DMA structures, since the kernel won't be using them, and clea
 979  * up any GEM state.
 980  */
 981 void i915_driver_lastclose(struct drm_device *dev)
 982 {
 983         intel_fbdev_restore_mode(dev);
 984         vga_switcheroo_process_delayed_switch();
 985 }
 986
 987 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
 988 {
 989         mutex_lock(&dev->struct_mutex);
 990         i915_gem_context_close(dev, file);
 991         i915_gem_release(dev, file);
 992         mutex_unlock(&dev->struct_mutex);
 993
 994         if (drm_core_check_feature(dev, DRIVER_MODESET))
 995                 intel_modeset_preclose(dev, file);
 996 }
 997
 998 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
 999 {
1000         struct drm_i915_file_private *file_priv = file->driver_priv;
1001
1002         if (file_priv && file_priv->bsd_ring)
1003                 file_priv->bsd_ring = NULL;
1004         kfree(file_priv);
1005 }
1006
1007 const struct drm_ioctl_desc i915_ioctls[] = {
1008         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1009         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1010         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1011         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1012         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1013         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1014         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1015         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1016         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1017         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1018         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1019         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1020         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1021         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1022         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1023         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1024         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1025         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1026         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1027         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1028         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1029         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1030         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1031         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1032         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1033         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1034         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1035         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1036         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1037         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1038         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1039         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1040         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1041         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1042         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1043         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1044         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1045         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1046         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1047         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1048         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1049         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1050         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1051         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1052         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1053         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1054         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1055         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1056         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1057         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1058 };
1059
1060 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
1061
1062 /*
1063  * This is really ugly: Because old userspace abused the linux agp interface to
1064  * manage the gtt, we need to claim that all intel devices are agp.  For
1065  * otherwise the drm core refuses to initialize the agp support code.
1066  */
1067 int i915_driver_device_is_agp(struct drm_device *dev)
1068 {
1069         return 1;
1070 }