drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/i915_drm.h>
  47
  48 #include "i915_drv.h"
  49 #include "i915_trace.h"
  50 #include "i915_vgpu.h"
  51 #include "intel_drv.h"
  52
  53 static struct drm_driver driver;
  54
  55 static unsigned int i915_load_fail_count;
  56
  57 bool __i915_inject_load_failure(const char *func, int line)
  58 {
  59         if (i915_load_fail_count >= i915.inject_load_failure)
  60                 return false;
  61
  62         if (++i915_load_fail_count == i915.inject_load_failure) {
  63                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  64                          i915.inject_load_failure, func, line);
  65                 return true;
  66         }
  67
  68         return false;
  69 }
  70
  71 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  72 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  73                     "providing the dmesg log by booting with drm.debug=0xf"
  74
  75 void
  76 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  77               const char *fmt, ...)
  78 {
  79         static bool shown_bug_once;
  80         struct device *dev = dev_priv->drm.dev;
  81         bool is_error = level[1] <= KERN_ERR[1];
  82         bool is_debug = level[1] == KERN_DEBUG[1];
  83         struct va_format vaf;
  84         va_list args;
  85
  86         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  87                 return;
  88
  89         va_start(args, fmt);
  90
  91         vaf.fmt = fmt;
  92         vaf.va = &args;
  93
  94         dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
  95                    __builtin_return_address(0), &vaf);
  96
  97         if (is_error && !shown_bug_once) {
  98                 dev_notice(dev, "%s", FDO_BUG_MSG);
  99                 shown_bug_once = true;
 100         }
 101
 102         va_end(args);
 103 }
 104
 105 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 106 {
 107         return i915.inject_load_failure &&
 108                i915_load_fail_count == i915.inject_load_failure;
 109 }
 110
 111 #define i915_load_error(dev_priv, fmt, ...)                                  \
 112         __i915_printk(dev_priv,                                              \
 113                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 114                       fmt, ##__VA_ARGS__)
 115
 116
 117 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 118 {
 119         enum intel_pch ret = PCH_NOP;
 120
 121         /*
 122          * In a virtualized passthrough environment we can be in a
 123          * setup where the ISA bridge is not able to be passed through.
 124          * In this case, a south bridge can be emulated and we have to
 125          * make an educated guess as to which PCH is really there.
 126          */
 127
 128         if (IS_GEN5(dev)) {
 129                 ret = PCH_IBX;
 130                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 131         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 132                 ret = PCH_CPT;
 133                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 134         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 135                 ret = PCH_LPT;
 136                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 137         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 138                 ret = PCH_SPT;
 139                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 140         }
 141
 142         return ret;
 143 }
 144
 145 static void intel_detect_pch(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = to_i915(dev);
 148         struct pci_dev *pch = NULL;
 149
 150         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 151          * (which really amounts to a PCH but no South Display).
 152          */
 153         if (INTEL_INFO(dev)->num_pipes == 0) {
 154                 dev_priv->pch_type = PCH_NOP;
 155                 return;
 156         }
 157
 158         /*
 159          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 160          * make graphics device passthrough work easy for VMM, that only
 161          * need to expose ISA bridge to let driver know the real hardware
 162          * underneath. This is a requirement from virtualization team.
 163          *
 164          * In some virtualized environments (e.g. XEN), there is irrelevant
 165          * ISA bridge in the system. To work reliably, we should scan trhough
 166          * all the ISA bridge devices and check for the first match, instead
 167          * of only checking the first one.
 168          */
 169         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 170                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 171                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 172                         dev_priv->pch_id = id;
 173
 174                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 175                                 dev_priv->pch_type = PCH_IBX;
 176                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 177                                 WARN_ON(!IS_GEN5(dev));
 178                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 179                                 dev_priv->pch_type = PCH_CPT;
 180                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 181                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 182                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 183                                 /* PantherPoint is CPT compatible */
 184                                 dev_priv->pch_type = PCH_CPT;
 185                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 186                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 187                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 188                                 dev_priv->pch_type = PCH_LPT;
 189                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 190                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 191                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 192                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 193                                 dev_priv->pch_type = PCH_LPT;
 194                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 195                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 196                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 197                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 198                                 dev_priv->pch_type = PCH_SPT;
 199                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 200                                 WARN_ON(!IS_SKYLAKE(dev) &&
 201                                         !IS_KABYLAKE(dev));
 202                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 203                                 dev_priv->pch_type = PCH_SPT;
 204                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 205                                 WARN_ON(!IS_SKYLAKE(dev) &&
 206                                         !IS_KABYLAKE(dev));
 207                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 208                                 dev_priv->pch_type = PCH_KBP;
 209                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 210                                 WARN_ON(!IS_KABYLAKE(dev));
 211                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 212                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 213                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 214                                     pch->subsystem_vendor ==
 215                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 216                                     pch->subsystem_device ==
 217                                             PCI_SUBDEVICE_ID_QEMU)) {
 218                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
 219                         } else
 220                                 continue;
 221
 222                         break;
 223                 }
 224         }
 225         if (!pch)
 226                 DRM_DEBUG_KMS("No PCH found.\n");
 227
 228         pci_dev_put(pch);
 229 }
 230
 231 bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
 232 {
 233         if (INTEL_GEN(dev_priv) < 6)
 234                 return false;
 235
 236         if (i915.semaphores >= 0)
 237                 return i915.semaphores;
 238
 239         /* TODO: make semaphores and Execlists play nicely together */
 240         if (i915.enable_execlists)
 241                 return false;
 242
 243 #ifdef CONFIG_INTEL_IOMMU
 244         /* Enable semaphores on SNB when IO remapping is off */
 245         if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped)
 246                 return false;
 247 #endif
 248
 249         return true;
 250 }
 251
 252 static int i915_getparam(struct drm_device *dev, void *data,
 253                          struct drm_file *file_priv)
 254 {
 255         struct drm_i915_private *dev_priv = to_i915(dev);
 256         drm_i915_getparam_t *param = data;
 257         int value;
 258
 259         switch (param->param) {
 260         case I915_PARAM_IRQ_ACTIVE:
 261         case I915_PARAM_ALLOW_BATCHBUFFER:
 262         case I915_PARAM_LAST_DISPATCH:
 263                 /* Reject all old ums/dri params. */
 264                 return -ENODEV;
 265         case I915_PARAM_CHIPSET_ID:
 266                 value = dev->pdev->device;
 267                 break;
 268         case I915_PARAM_REVISION:
 269                 value = dev->pdev->revision;
 270                 break;
 271         case I915_PARAM_HAS_GEM:
 272                 value = 1;
 273                 break;
 274         case I915_PARAM_NUM_FENCES_AVAIL:
 275                 value = dev_priv->num_fence_regs;
 276                 break;
 277         case I915_PARAM_HAS_OVERLAY:
 278                 value = dev_priv->overlay ? 1 : 0;
 279                 break;
 280         case I915_PARAM_HAS_PAGEFLIPPING:
 281                 value = 1;
 282                 break;
 283         case I915_PARAM_HAS_EXECBUF2:
 284                 /* depends on GEM */
 285                 value = 1;
 286                 break;
 287         case I915_PARAM_HAS_BSD:
 288                 value = intel_engine_initialized(&dev_priv->engine[VCS]);
 289                 break;
 290         case I915_PARAM_HAS_BLT:
 291                 value = intel_engine_initialized(&dev_priv->engine[BCS]);
 292                 break;
 293         case I915_PARAM_HAS_VEBOX:
 294                 value = intel_engine_initialized(&dev_priv->engine[VECS]);
 295                 break;
 296         case I915_PARAM_HAS_BSD2:
 297                 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
 298                 break;
 299         case I915_PARAM_HAS_RELAXED_FENCING:
 300                 value = 1;
 301                 break;
 302         case I915_PARAM_HAS_COHERENT_RINGS:
 303                 value = 1;
 304                 break;
 305         case I915_PARAM_HAS_EXEC_CONSTANTS:
 306                 value = INTEL_INFO(dev)->gen >= 4;
 307                 break;
 308         case I915_PARAM_HAS_RELAXED_DELTA:
 309                 value = 1;
 310                 break;
 311         case I915_PARAM_HAS_GEN7_SOL_RESET:
 312                 value = 1;
 313                 break;
 314         case I915_PARAM_HAS_LLC:
 315                 value = HAS_LLC(dev);
 316                 break;
 317         case I915_PARAM_HAS_WT:
 318                 value = HAS_WT(dev);
 319                 break;
 320         case I915_PARAM_HAS_ALIASING_PPGTT:
 321                 value = USES_PPGTT(dev);
 322                 break;
 323         case I915_PARAM_HAS_WAIT_TIMEOUT:
 324                 value = 1;
 325                 break;
 326         case I915_PARAM_HAS_SEMAPHORES:
 327                 value = i915_semaphore_is_enabled(dev_priv);
 328                 break;
 329         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 330                 value = 1;
 331                 break;
 332         case I915_PARAM_HAS_SECURE_BATCHES:
 333                 value = capable(CAP_SYS_ADMIN);
 334                 break;
 335         case I915_PARAM_HAS_PINNED_BATCHES:
 336                 value = 1;
 337                 break;
 338         case I915_PARAM_HAS_EXEC_NO_RELOC:
 339                 value = 1;
 340                 break;
 341         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 342                 value = 1;
 343                 break;
 344         case I915_PARAM_CMD_PARSER_VERSION:
 345                 value = i915_cmd_parser_get_version(dev_priv);
 346                 break;
 347         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 348                 value = 1;
 349                 break;
 350         case I915_PARAM_MMAP_VERSION:
 351                 value = 1;
 352                 break;
 353         case I915_PARAM_SUBSLICE_TOTAL:
 354                 value = INTEL_INFO(dev)->subslice_total;
 355                 if (!value)
 356                         return -ENODEV;
 357                 break;
 358         case I915_PARAM_EU_TOTAL:
 359                 value = INTEL_INFO(dev)->eu_total;
 360                 if (!value)
 361                         return -ENODEV;
 362                 break;
 363         case I915_PARAM_HAS_GPU_RESET:
 364                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 365                 break;
 366         case I915_PARAM_HAS_RESOURCE_STREAMER:
 367                 value = HAS_RESOURCE_STREAMER(dev);
 368                 break;
 369         case I915_PARAM_HAS_EXEC_SOFTPIN:
 370                 value = 1;
 371                 break;
 372         case I915_PARAM_HAS_POOLED_EU:
 373                 value = HAS_POOLED_EU(dev);
 374                 break;
 375         case I915_PARAM_MIN_EU_IN_POOL:
 376                 value = INTEL_INFO(dev)->min_eu_in_pool;
 377                 break;
 378         default:
 379                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 380                 return -EINVAL;
 381         }
 382
 383         if (put_user(value, param->value))
 384                 return -EFAULT;
 385
 386         return 0;
 387 }
 388
 389 static int i915_get_bridge_dev(struct drm_device *dev)
 390 {
 391         struct drm_i915_private *dev_priv = to_i915(dev);
 392
 393         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 394         if (!dev_priv->bridge_dev) {
 395                 DRM_ERROR("bridge device not found\n");
 396                 return -1;
 397         }
 398         return 0;
 399 }
 400
 401 /* Allocate space for the MCH regs if needed, return nonzero on error */
 402 static int
 403 intel_alloc_mchbar_resource(struct drm_device *dev)
 404 {
 405         struct drm_i915_private *dev_priv = to_i915(dev);
 406         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 407         u32 temp_lo, temp_hi = 0;
 408         u64 mchbar_addr;
 409         int ret;
 410
 411         if (INTEL_INFO(dev)->gen >= 4)
 412                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 413         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 414         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 415
 416         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 417 #ifdef CONFIG_PNP
 418         if (mchbar_addr &&
 419             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 420                 return 0;
 421 #endif
 422
 423         /* Get some space for it */
 424         dev_priv->mch_res.name = "i915 MCHBAR";
 425         dev_priv->mch_res.flags = IORESOURCE_MEM;
 426         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 427                                      &dev_priv->mch_res,
 428                                      MCHBAR_SIZE, MCHBAR_SIZE,
 429                                      PCIBIOS_MIN_MEM,
 430                                      0, pcibios_align_resource,
 431                                      dev_priv->bridge_dev);
 432         if (ret) {
 433                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 434                 dev_priv->mch_res.start = 0;
 435                 return ret;
 436         }
 437
 438         if (INTEL_INFO(dev)->gen >= 4)
 439                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 440                                        upper_32_bits(dev_priv->mch_res.start));
 441
 442         pci_write_config_dword(dev_priv->bridge_dev, reg,
 443                                lower_32_bits(dev_priv->mch_res.start));
 444         return 0;
 445 }
 446
 447 /* Setup MCHBAR if possible, return true if we should disable it again */
 448 static void
 449 intel_setup_mchbar(struct drm_device *dev)
 450 {
 451         struct drm_i915_private *dev_priv = to_i915(dev);
 452         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 453         u32 temp;
 454         bool enabled;
 455
 456         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 457                 return;
 458
 459         dev_priv->mchbar_need_disable = false;
 460
 461         if (IS_I915G(dev) || IS_I915GM(dev)) {
 462                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 463                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 464         } else {
 465                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 466                 enabled = temp & 1;
 467         }
 468
 469         /* If it's already enabled, don't have to do anything */
 470         if (enabled)
 471                 return;
 472
 473         if (intel_alloc_mchbar_resource(dev))
 474                 return;
 475
 476         dev_priv->mchbar_need_disable = true;
 477
 478         /* Space is allocated or reserved, so enable it. */
 479         if (IS_I915G(dev) || IS_I915GM(dev)) {
 480                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 481                                        temp | DEVEN_MCHBAR_EN);
 482         } else {
 483                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 484                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 485         }
 486 }
 487
 488 static void
 489 intel_teardown_mchbar(struct drm_device *dev)
 490 {
 491         struct drm_i915_private *dev_priv = to_i915(dev);
 492         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 493
 494         if (dev_priv->mchbar_need_disable) {
 495                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 496                         u32 deven_val;
 497
 498                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 499                                               &deven_val);
 500                         deven_val &= ~DEVEN_MCHBAR_EN;
 501                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 502                                                deven_val);
 503                 } else {
 504                         u32 mchbar_val;
 505
 506                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 507                                               &mchbar_val);
 508                         mchbar_val &= ~1;
 509                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 510                                                mchbar_val);
 511                 }
 512         }
 513
 514         if (dev_priv->mch_res.start)
 515                 release_resource(&dev_priv->mch_res);
 516 }
 517
 518 /* true = enable decode, false = disable decoder */
 519 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 520 {
 521         struct drm_device *dev = cookie;
 522
 523         intel_modeset_vga_set_state(dev, state);
 524         if (state)
 525                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 526                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 527         else
 528                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 529 }
 530
 531 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 532 {
 533         struct drm_device *dev = pci_get_drvdata(pdev);
 534         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 535
 536         if (state == VGA_SWITCHEROO_ON) {
 537                 pr_info("switched on\n");
 538                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 539                 /* i915 resume handler doesn't set to D0 */
 540                 pci_set_power_state(dev->pdev, PCI_D0);
 541                 i915_resume_switcheroo(dev);
 542                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 543         } else {
 544                 pr_info("switched off\n");
 545                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 546                 i915_suspend_switcheroo(dev, pmm);
 547                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 548         }
 549 }
 550
 551 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 552 {
 553         struct drm_device *dev = pci_get_drvdata(pdev);
 554
 555         /*
 556          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 557          * locking inversion with the driver load path. And the access here is
 558          * completely racy anyway. So don't bother with locking for now.
 559          */
 560         return dev->open_count == 0;
 561 }
 562
 563 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 564         .set_gpu_state = i915_switcheroo_set_state,
 565         .reprobe = NULL,
 566         .can_switch = i915_switcheroo_can_switch,
 567 };
 568
 569 static void i915_gem_fini(struct drm_device *dev)
 570 {
 571         struct drm_i915_private *dev_priv = to_i915(dev);
 572
 573         /*
 574          * Neither the BIOS, ourselves or any other kernel
 575          * expects the system to be in execlists mode on startup,
 576          * so we need to reset the GPU back to legacy mode. And the only
 577          * known way to disable logical contexts is through a GPU reset.
 578          *
 579          * So in order to leave the system in a known default configuration,
 580          * always reset the GPU upon unload. Afterwards we then clean up the
 581          * GEM state tracking, flushing off the requests and leaving the
 582          * system in a known idle state.
 583          *
 584          * Note that is of the upmost importance that the GPU is idle and
 585          * all stray writes are flushed *before* we dismantle the backing
 586          * storage for the pinned objects.
 587          *
 588          * However, since we are uncertain that reseting the GPU on older
 589          * machines is a good idea, we don't - just in case it leaves the
 590          * machine in an unusable condition.
 591          */
 592         if (HAS_HW_CONTEXTS(dev)) {
 593                 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
 594                 WARN_ON(reset && reset != -ENODEV);
 595         }
 596
 597         mutex_lock(&dev->struct_mutex);
 598         i915_gem_reset(dev);
 599         i915_gem_cleanup_engines(dev);
 600         i915_gem_context_fini(dev);
 601         mutex_unlock(&dev->struct_mutex);
 602
 603         WARN_ON(!list_empty(&to_i915(dev)->context_list));
 604 }
 605
 606 static int i915_load_modeset_init(struct drm_device *dev)
 607 {
 608         struct drm_i915_private *dev_priv = to_i915(dev);
 609         int ret;
 610
 611         if (i915_inject_load_failure())
 612                 return -ENODEV;
 613
 614         ret = intel_bios_init(dev_priv);
 615         if (ret)
 616                 DRM_INFO("failed to find VBIOS tables\n");
 617
 618         /* If we have > 1 VGA cards, then we need to arbitrate access
 619          * to the common VGA resources.
 620          *
 621          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 622          * then we do not take part in VGA arbitration and the
 623          * vga_client_register() fails with -ENODEV.
 624          */
 625         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 626         if (ret && ret != -ENODEV)
 627                 goto out;
 628
 629         intel_register_dsm_handler();
 630
 631         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 632         if (ret)
 633                 goto cleanup_vga_client;
 634
 635         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 636         intel_update_rawclk(dev_priv);
 637
 638         intel_power_domains_init_hw(dev_priv, false);
 639
 640         intel_csr_ucode_init(dev_priv);
 641
 642         ret = intel_irq_install(dev_priv);
 643         if (ret)
 644                 goto cleanup_csr;
 645
 646         intel_setup_gmbus(dev);
 647
 648         /* Important: The output setup functions called by modeset_init need
 649          * working irqs for e.g. gmbus and dp aux transfers. */
 650         intel_modeset_init(dev);
 651
 652         intel_guc_init(dev);
 653
 654         ret = i915_gem_init(dev);
 655         if (ret)
 656                 goto cleanup_irq;
 657
 658         intel_modeset_gem_init(dev);
 659
 660         if (INTEL_INFO(dev)->num_pipes == 0)
 661                 return 0;
 662
 663         ret = intel_fbdev_init(dev);
 664         if (ret)
 665                 goto cleanup_gem;
 666
 667         /* Only enable hotplug handling once the fbdev is fully set up. */
 668         intel_hpd_init(dev_priv);
 669
 670         drm_kms_helper_poll_init(dev);
 671
 672         return 0;
 673
 674 cleanup_gem:
 675         i915_gem_fini(dev);
 676 cleanup_irq:
 677         intel_guc_fini(dev);
 678         drm_irq_uninstall(dev);
 679         intel_teardown_gmbus(dev);
 680 cleanup_csr:
 681         intel_csr_ucode_fini(dev_priv);
 682         intel_power_domains_fini(dev_priv);
 683         vga_switcheroo_unregister_client(dev->pdev);
 684 cleanup_vga_client:
 685         vga_client_register(dev->pdev, NULL, NULL, NULL);
 686 out:
 687         return ret;
 688 }
 689
 690 #if IS_ENABLED(CONFIG_FB)
 691 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 692 {
 693         struct apertures_struct *ap;
 694         struct pci_dev *pdev = dev_priv->drm.pdev;
 695         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 696         bool primary;
 697         int ret;
 698
 699         ap = alloc_apertures(1);
 700         if (!ap)
 701                 return -ENOMEM;
 702
 703         ap->ranges[0].base = ggtt->mappable_base;
 704         ap->ranges[0].size = ggtt->mappable_end;
 705
 706         primary =
 707                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 708
 709         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 710
 711         kfree(ap);
 712
 713         return ret;
 714 }
 715 #else
 716 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 717 {
 718         return 0;
 719 }
 720 #endif
 721
 722 #if !defined(CONFIG_VGA_CONSOLE)
 723 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 724 {
 725         return 0;
 726 }
 727 #elif !defined(CONFIG_DUMMY_CONSOLE)
 728 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 729 {
 730         return -ENODEV;
 731 }
 732 #else
 733 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 734 {
 735         int ret = 0;
 736
 737         DRM_INFO("Replacing VGA console driver\n");
 738
 739         console_lock();
 740         if (con_is_bound(&vga_con))
 741                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 742         if (ret == 0) {
 743                 ret = do_unregister_con_driver(&vga_con);
 744
 745                 /* Ignore "already unregistered". */
 746                 if (ret == -ENODEV)
 747                         ret = 0;
 748         }
 749         console_unlock();
 750
 751         return ret;
 752 }
 753 #endif
 754
 755 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 756 {
 757         /*
 758          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 759          * CHV x1 PHY (DP/HDMI D)
 760          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 761          */
 762         if (IS_CHERRYVIEW(dev_priv)) {
 763                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 764                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 765         } else if (IS_VALLEYVIEW(dev_priv)) {
 766                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 767         }
 768 }
 769
 770 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 771 {
 772         /*
 773          * The i915 workqueue is primarily used for batched retirement of
 774          * requests (and thus managing bo) once the task has been completed
 775          * by the GPU. i915_gem_retire_requests() is called directly when we
 776          * need high-priority retirement, such as waiting for an explicit
 777          * bo.
 778          *
 779          * It is also used for periodic low-priority events, such as
 780          * idle-timers and recording error state.
 781          *
 782          * All tasks on the workqueue are expected to acquire the dev mutex
 783          * so there is no point in running more than one instance of the
 784          * workqueue at any time.  Use an ordered one.
 785          */
 786         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 787         if (dev_priv->wq == NULL)
 788                 goto out_err;
 789
 790         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 791         if (dev_priv->hotplug.dp_wq == NULL)
 792                 goto out_free_wq;
 793
 794         return 0;
 795
 796 out_free_wq:
 797         destroy_workqueue(dev_priv->wq);
 798 out_err:
 799         DRM_ERROR("Failed to allocate workqueues.\n");
 800
 801         return -ENOMEM;
 802 }
 803
 804 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 805 {
 806         destroy_workqueue(dev_priv->hotplug.dp_wq);
 807         destroy_workqueue(dev_priv->wq);
 808 }
 809
 810 /**
 811  * i915_driver_init_early - setup state not requiring device access
 812  * @dev_priv: device private
 813  *
 814  * Initialize everything that is a "SW-only" state, that is state not
 815  * requiring accessing the device or exposing the driver via kernel internal
 816  * or userspace interfaces. Example steps belonging here: lock initialization,
 817  * system memory allocation, setting up device specific attributes and
 818  * function hooks not requiring accessing the device.
 819  */
 820 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 821                                   const struct pci_device_id *ent)
 822 {
 823         const struct intel_device_info *match_info =
 824                 (struct intel_device_info *)ent->driver_data;
 825         struct intel_device_info *device_info;
 826         int ret = 0;
 827
 828         if (i915_inject_load_failure())
 829                 return -ENODEV;
 830
 831         /* Setup the write-once "constant" device info */
 832         device_info = mkwrite_device_info(dev_priv);
 833         memcpy(device_info, match_info, sizeof(*device_info));
 834         device_info->device_id = dev_priv->drm.pdev->device;
 835
 836         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 837         device_info->gen_mask = BIT(device_info->gen - 1);
 838
 839         spin_lock_init(&dev_priv->irq_lock);
 840         spin_lock_init(&dev_priv->gpu_error.lock);
 841         mutex_init(&dev_priv->backlight_lock);
 842         spin_lock_init(&dev_priv->uncore.lock);
 843         spin_lock_init(&dev_priv->mm.object_stat_lock);
 844         spin_lock_init(&dev_priv->mmio_flip_lock);
 845         mutex_init(&dev_priv->sb_lock);
 846         mutex_init(&dev_priv->modeset_restore_lock);
 847         mutex_init(&dev_priv->av_mutex);
 848         mutex_init(&dev_priv->wm.wm_mutex);
 849         mutex_init(&dev_priv->pps_mutex);
 850
 851         ret = i915_workqueues_init(dev_priv);
 852         if (ret < 0)
 853                 return ret;
 854
 855         ret = intel_gvt_init(dev_priv);
 856         if (ret < 0)
 857                 goto err_workqueues;
 858
 859         /* This must be called before any calls to HAS_PCH_* */
 860         intel_detect_pch(&dev_priv->drm);
 861
 862         intel_pm_setup(&dev_priv->drm);
 863         intel_init_dpio(dev_priv);
 864         intel_power_domains_init(dev_priv);
 865         intel_irq_init(dev_priv);
 866         intel_init_display_hooks(dev_priv);
 867         intel_init_clock_gating_hooks(dev_priv);
 868         intel_init_audio_hooks(dev_priv);
 869         i915_gem_load_init(&dev_priv->drm);
 870
 871         intel_display_crc_init(&dev_priv->drm);
 872
 873         intel_device_info_dump(dev_priv);
 874
 875         /* Not all pre-production machines fall into this category, only the
 876          * very first ones. Almost everything should work, except for maybe
 877          * suspend/resume. And we don't implement workarounds that affect only
 878          * pre-production machines. */
 879         if (IS_HSW_EARLY_SDV(dev_priv))
 880                 DRM_INFO("This is an early pre-production Haswell machine. "
 881                          "It may not be fully functional.\n");
 882
 883         return 0;
 884
 885 err_workqueues:
 886         i915_workqueues_cleanup(dev_priv);
 887         return ret;
 888 }
 889
 890 /**
 891  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 892  * @dev_priv: device private
 893  */
 894 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 895 {
 896         i915_gem_load_cleanup(&dev_priv->drm);
 897         i915_workqueues_cleanup(dev_priv);
 898 }
 899
 900 static int i915_mmio_setup(struct drm_device *dev)
 901 {
 902         struct drm_i915_private *dev_priv = to_i915(dev);
 903         int mmio_bar;
 904         int mmio_size;
 905
 906         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 907         /*
 908          * Before gen4, the registers and the GTT are behind different BARs.
 909          * However, from gen4 onwards, the registers and the GTT are shared
 910          * in the same BAR, so we want to restrict this ioremap from
 911          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 912          * the register BAR remains the same size for all the earlier
 913          * generations up to Ironlake.
 914          */
 915         if (INTEL_INFO(dev)->gen < 5)
 916                 mmio_size = 512 * 1024;
 917         else
 918                 mmio_size = 2 * 1024 * 1024;
 919         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 920         if (dev_priv->regs == NULL) {
 921                 DRM_ERROR("failed to map registers\n");
 922
 923                 return -EIO;
 924         }
 925
 926         /* Try to make sure MCHBAR is enabled before poking at it */
 927         intel_setup_mchbar(dev);
 928
 929         return 0;
 930 }
 931
 932 static void i915_mmio_cleanup(struct drm_device *dev)
 933 {
 934         struct drm_i915_private *dev_priv = to_i915(dev);
 935
 936         intel_teardown_mchbar(dev);
 937         pci_iounmap(dev->pdev, dev_priv->regs);
 938 }
 939
 940 /**
 941  * i915_driver_init_mmio - setup device MMIO
 942  * @dev_priv: device private
 943  *
 944  * Setup minimal device state necessary for MMIO accesses later in the
 945  * initialization sequence. The setup here should avoid any other device-wide
 946  * side effects or exposing the driver via kernel internal or user space
 947  * interfaces.
 948  */
 949 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 950 {
 951         struct drm_device *dev = &dev_priv->drm;
 952         int ret;
 953
 954         if (i915_inject_load_failure())
 955                 return -ENODEV;
 956
 957         if (i915_get_bridge_dev(dev))
 958                 return -EIO;
 959
 960         ret = i915_mmio_setup(dev);
 961         if (ret < 0)
 962                 goto put_bridge;
 963
 964         intel_uncore_init(dev_priv);
 965
 966         return 0;
 967
 968 put_bridge:
 969         pci_dev_put(dev_priv->bridge_dev);
 970
 971         return ret;
 972 }
 973
 974 /**
 975  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 976  * @dev_priv: device private
 977  */
 978 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 979 {
 980         struct drm_device *dev = &dev_priv->drm;
 981
 982         intel_uncore_fini(dev_priv);
 983         i915_mmio_cleanup(dev);
 984         pci_dev_put(dev_priv->bridge_dev);
 985 }
 986
 987 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 988 {
 989         i915.enable_execlists =
 990                 intel_sanitize_enable_execlists(dev_priv,
 991                                                 i915.enable_execlists);
 992
 993         /*
 994          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 995          * user's requested state against the hardware/driver capabilities.  We
 996          * do this now so that we can print out any log messages once rather
 997          * than every time we check intel_enable_ppgtt().
 998          */
 999         i915.enable_ppgtt =
1000                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1001         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1002 }
1003
1004 /**
1005  * i915_driver_init_hw - setup state requiring device access
1006  * @dev_priv: device private
1007  *
1008  * Setup state that requires accessing the device, but doesn't require
1009  * exposing the driver via kernel internal or userspace interfaces.
1010  */
1011 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1012 {
1013         struct drm_device *dev = &dev_priv->drm;
1014         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1015         uint32_t aperture_size;
1016         int ret;
1017
1018         if (i915_inject_load_failure())
1019                 return -ENODEV;
1020
1021         intel_device_info_runtime_init(dev_priv);
1022
1023         intel_sanitize_options(dev_priv);
1024
1025         ret = i915_ggtt_init_hw(dev);
1026         if (ret)
1027                 return ret;
1028
1029         ret = i915_ggtt_enable_hw(dev);
1030         if (ret) {
1031                 DRM_ERROR("failed to enable GGTT\n");
1032                 goto out_ggtt;
1033         }
1034
1035         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1036          * otherwise the vga fbdev driver falls over. */
1037         ret = i915_kick_out_firmware_fb(dev_priv);
1038         if (ret) {
1039                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1040                 goto out_ggtt;
1041         }
1042
1043         ret = i915_kick_out_vgacon(dev_priv);
1044         if (ret) {
1045                 DRM_ERROR("failed to remove conflicting VGA console\n");
1046                 goto out_ggtt;
1047         }
1048
1049         pci_set_master(dev->pdev);
1050
1051         /* overlay on gen2 is broken and can't address above 1G */
1052         if (IS_GEN2(dev)) {
1053                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1054                 if (ret) {
1055                         DRM_ERROR("failed to set DMA mask\n");
1056
1057                         goto out_ggtt;
1058                 }
1059         }
1060
1061
1062         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1063          * using 32bit addressing, overwriting memory if HWS is located
1064          * above 4GB.
1065          *
1066          * The documentation also mentions an issue with undefined
1067          * behaviour if any general state is accessed within a page above 4GB,
1068          * which also needs to be handled carefully.
1069          */
1070         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1071                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1072
1073                 if (ret) {
1074                         DRM_ERROR("failed to set DMA mask\n");
1075
1076                         goto out_ggtt;
1077                 }
1078         }
1079
1080         aperture_size = ggtt->mappable_end;
1081
1082         ggtt->mappable =
1083                 io_mapping_create_wc(ggtt->mappable_base,
1084                                      aperture_size);
1085         if (!ggtt->mappable) {
1086                 ret = -EIO;
1087                 goto out_ggtt;
1088         }
1089
1090         ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
1091                                               aperture_size);
1092
1093         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1094                            PM_QOS_DEFAULT_VALUE);
1095
1096         intel_uncore_sanitize(dev_priv);
1097
1098         intel_opregion_setup(dev_priv);
1099
1100         i915_gem_load_init_fences(dev_priv);
1101
1102         /* On the 945G/GM, the chipset reports the MSI capability on the
1103          * integrated graphics even though the support isn't actually there
1104          * according to the published specs.  It doesn't appear to function
1105          * correctly in testing on 945G.
1106          * This may be a side effect of MSI having been made available for PEG
1107          * and the registers being closely associated.
1108          *
1109          * According to chipset errata, on the 965GM, MSI interrupts may
1110          * be lost or delayed, but we use them anyways to avoid
1111          * stuck interrupts on some machines.
1112          */
1113         if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1114                 if (pci_enable_msi(dev->pdev) < 0)
1115                         DRM_DEBUG_DRIVER("can't enable MSI");
1116         }
1117
1118         return 0;
1119
1120 out_ggtt:
1121         i915_ggtt_cleanup_hw(dev);
1122
1123         return ret;
1124 }
1125
1126 /**
1127  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1128  * @dev_priv: device private
1129  */
1130 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1131 {
1132         struct drm_device *dev = &dev_priv->drm;
1133         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1134
1135         if (dev->pdev->msi_enabled)
1136                 pci_disable_msi(dev->pdev);
1137
1138         pm_qos_remove_request(&dev_priv->pm_qos);
1139         arch_phys_wc_del(ggtt->mtrr);
1140         io_mapping_free(ggtt->mappable);
1141         i915_ggtt_cleanup_hw(dev);
1142 }
1143
1144 /**
1145  * i915_driver_register - register the driver with the rest of the system
1146  * @dev_priv: device private
1147  *
1148  * Perform any steps necessary to make the driver available via kernel
1149  * internal or userspace interfaces.
1150  */
1151 static void i915_driver_register(struct drm_i915_private *dev_priv)
1152 {
1153         struct drm_device *dev = &dev_priv->drm;
1154
1155         i915_gem_shrinker_init(dev_priv);
1156
1157         /*
1158          * Notify a valid surface after modesetting,
1159          * when running inside a VM.
1160          */
1161         if (intel_vgpu_active(dev_priv))
1162                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1163
1164         /* Reveal our presence to userspace */
1165         if (drm_dev_register(dev, 0) == 0) {
1166                 i915_debugfs_register(dev_priv);
1167                 i915_setup_sysfs(dev);
1168         } else
1169                 DRM_ERROR("Failed to register driver for userspace access!\n");
1170
1171         if (INTEL_INFO(dev_priv)->num_pipes) {
1172                 /* Must be done after probing outputs */
1173                 intel_opregion_register(dev_priv);
1174                 acpi_video_register();
1175         }
1176
1177         if (IS_GEN5(dev_priv))
1178                 intel_gpu_ips_init(dev_priv);
1179
1180         i915_audio_component_init(dev_priv);
1181
1182         /*
1183          * Some ports require correctly set-up hpd registers for detection to
1184          * work properly (leading to ghost connected connector status), e.g. VGA
1185          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1186          * irqs are fully enabled. We do it last so that the async config
1187          * cannot run before the connectors are registered.
1188          */
1189         intel_fbdev_initial_config_async(dev);
1190 }
1191
1192 /**
1193  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1194  * @dev_priv: device private
1195  */
1196 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1197 {
1198         i915_audio_component_cleanup(dev_priv);
1199
1200         intel_gpu_ips_teardown();
1201         acpi_video_unregister();
1202         intel_opregion_unregister(dev_priv);
1203
1204         i915_teardown_sysfs(&dev_priv->drm);
1205         i915_debugfs_unregister(dev_priv);
1206         drm_dev_unregister(&dev_priv->drm);
1207
1208         i915_gem_shrinker_cleanup(dev_priv);
1209 }
1210
1211 /**
1212  * i915_driver_load - setup chip and create an initial config
1213  * @dev: DRM device
1214  * @flags: startup flags
1215  *
1216  * The driver load routine has to do several things:
1217  *   - drive output discovery via intel_modeset_init()
1218  *   - initialize the memory manager
1219  *   - allocate initial config memory
1220  *   - setup the DRM framebuffer with the allocated memory
1221  */
1222 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1223 {
1224         struct drm_i915_private *dev_priv;
1225         int ret;
1226
1227         if (i915.nuclear_pageflip)
1228                 driver.driver_features |= DRIVER_ATOMIC;
1229
1230         ret = -ENOMEM;
1231         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1232         if (dev_priv)
1233                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1234         if (ret) {
1235                 dev_printk(KERN_ERR, &pdev->dev,
1236                            "[" DRM_NAME ":%s] allocation failed\n", __func__);
1237                 kfree(dev_priv);
1238                 return ret;
1239         }
1240
1241         dev_priv->drm.pdev = pdev;
1242         dev_priv->drm.dev_private = dev_priv;
1243
1244         ret = pci_enable_device(pdev);
1245         if (ret)
1246                 goto out_free_priv;
1247
1248         pci_set_drvdata(pdev, &dev_priv->drm);
1249
1250         ret = i915_driver_init_early(dev_priv, ent);
1251         if (ret < 0)
1252                 goto out_pci_disable;
1253
1254         intel_runtime_pm_get(dev_priv);
1255
1256         ret = i915_driver_init_mmio(dev_priv);
1257         if (ret < 0)
1258                 goto out_runtime_pm_put;
1259
1260         ret = i915_driver_init_hw(dev_priv);
1261         if (ret < 0)
1262                 goto out_cleanup_mmio;
1263
1264         /*
1265          * TODO: move the vblank init and parts of modeset init steps into one
1266          * of the i915_driver_init_/i915_driver_register functions according
1267          * to the role/effect of the given init step.
1268          */
1269         if (INTEL_INFO(dev_priv)->num_pipes) {
1270                 ret = drm_vblank_init(&dev_priv->drm,
1271                                       INTEL_INFO(dev_priv)->num_pipes);
1272                 if (ret)
1273                         goto out_cleanup_hw;
1274         }
1275
1276         ret = i915_load_modeset_init(&dev_priv->drm);
1277         if (ret < 0)
1278                 goto out_cleanup_vblank;
1279
1280         i915_driver_register(dev_priv);
1281
1282         intel_runtime_pm_enable(dev_priv);
1283
1284         /* Everything is in place, we can now relax! */
1285         DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1286                  driver.name, driver.major, driver.minor, driver.patchlevel,
1287                  driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1288
1289         intel_runtime_pm_put(dev_priv);
1290
1291         return 0;
1292
1293 out_cleanup_vblank:
1294         drm_vblank_cleanup(&dev_priv->drm);
1295 out_cleanup_hw:
1296         i915_driver_cleanup_hw(dev_priv);
1297 out_cleanup_mmio:
1298         i915_driver_cleanup_mmio(dev_priv);
1299 out_runtime_pm_put:
1300         intel_runtime_pm_put(dev_priv);
1301         i915_driver_cleanup_early(dev_priv);
1302 out_pci_disable:
1303         pci_disable_device(pdev);
1304 out_free_priv:
1305         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1306         drm_dev_unref(&dev_priv->drm);
1307         return ret;
1308 }
1309
1310 void i915_driver_unload(struct drm_device *dev)
1311 {
1312         struct drm_i915_private *dev_priv = to_i915(dev);
1313
1314         intel_fbdev_fini(dev);
1315
1316         if (i915_gem_suspend(dev))
1317                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1318
1319         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1320
1321         i915_driver_unregister(dev_priv);
1322
1323         drm_vblank_cleanup(dev);
1324
1325         intel_modeset_cleanup(dev);
1326
1327         /*
1328          * free the memory space allocated for the child device
1329          * config parsed from VBT
1330          */
1331         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1332                 kfree(dev_priv->vbt.child_dev);
1333                 dev_priv->vbt.child_dev = NULL;
1334                 dev_priv->vbt.child_dev_num = 0;
1335         }
1336         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1337         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1338         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1339         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1340
1341         vga_switcheroo_unregister_client(dev->pdev);
1342         vga_client_register(dev->pdev, NULL, NULL, NULL);
1343
1344         intel_csr_ucode_fini(dev_priv);
1345
1346         /* Free error state after interrupts are fully disabled. */
1347         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1348         i915_destroy_error_state(dev);
1349
1350         /* Flush any outstanding unpin_work. */
1351         flush_workqueue(dev_priv->wq);
1352
1353         intel_guc_fini(dev);
1354         i915_gem_fini(dev);
1355         intel_fbc_cleanup_cfb(dev_priv);
1356
1357         intel_power_domains_fini(dev_priv);
1358
1359         i915_driver_cleanup_hw(dev_priv);
1360         i915_driver_cleanup_mmio(dev_priv);
1361
1362         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1363
1364         i915_driver_cleanup_early(dev_priv);
1365 }
1366
1367 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1368 {
1369         int ret;
1370
1371         ret = i915_gem_open(dev, file);
1372         if (ret)
1373                 return ret;
1374
1375         return 0;
1376 }
1377
1378 /**
1379  * i915_driver_lastclose - clean up after all DRM clients have exited
1380  * @dev: DRM device
1381  *
1382  * Take care of cleaning up after all DRM clients have exited.  In the
1383  * mode setting case, we want to restore the kernel's initial mode (just
1384  * in case the last client left us in a bad state).
1385  *
1386  * Additionally, in the non-mode setting case, we'll tear down the GTT
1387  * and DMA structures, since the kernel won't be using them, and clea
1388  * up any GEM state.
1389  */
1390 static void i915_driver_lastclose(struct drm_device *dev)
1391 {
1392         intel_fbdev_restore_mode(dev);
1393         vga_switcheroo_process_delayed_switch();
1394 }
1395
1396 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1397 {
1398         mutex_lock(&dev->struct_mutex);
1399         i915_gem_context_close(dev, file);
1400         i915_gem_release(dev, file);
1401         mutex_unlock(&dev->struct_mutex);
1402 }
1403
1404 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1405 {
1406         struct drm_i915_file_private *file_priv = file->driver_priv;
1407
1408         kfree(file_priv);
1409 }
1410
1411 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1412 {
1413         struct drm_device *dev = &dev_priv->drm;
1414         struct intel_encoder *encoder;
1415
1416         drm_modeset_lock_all(dev);
1417         for_each_intel_encoder(dev, encoder)
1418                 if (encoder->suspend)
1419                         encoder->suspend(encoder);
1420         drm_modeset_unlock_all(dev);
1421 }
1422
1423 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1424                               bool rpm_resume);
1425 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1426
1427 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1428 {
1429 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1430         if (acpi_target_system_state() < ACPI_STATE_S3)
1431                 return true;
1432 #endif
1433         return false;
1434 }
1435
1436 static int i915_drm_suspend(struct drm_device *dev)
1437 {
1438         struct drm_i915_private *dev_priv = to_i915(dev);
1439         pci_power_t opregion_target_state;
1440         int error;
1441
1442         /* ignore lid events during suspend */
1443         mutex_lock(&dev_priv->modeset_restore_lock);
1444         dev_priv->modeset_restore = MODESET_SUSPENDED;
1445         mutex_unlock(&dev_priv->modeset_restore_lock);
1446
1447         disable_rpm_wakeref_asserts(dev_priv);
1448
1449         /* We do a lot of poking in a lot of registers, make sure they work
1450          * properly. */
1451         intel_display_set_init_power(dev_priv, true);
1452
1453         drm_kms_helper_poll_disable(dev);
1454
1455         pci_save_state(dev->pdev);
1456
1457         error = i915_gem_suspend(dev);
1458         if (error) {
1459                 dev_err(&dev->pdev->dev,
1460                         "GEM idle failed, resume might fail\n");
1461                 goto out;
1462         }
1463
1464         intel_guc_suspend(dev);
1465
1466         intel_suspend_gt_powersave(dev_priv);
1467
1468         intel_display_suspend(dev);
1469
1470         intel_dp_mst_suspend(dev);
1471
1472         intel_runtime_pm_disable_interrupts(dev_priv);
1473         intel_hpd_cancel_work(dev_priv);
1474
1475         intel_suspend_encoders(dev_priv);
1476
1477         intel_suspend_hw(dev);
1478
1479         i915_gem_suspend_gtt_mappings(dev);
1480
1481         i915_save_state(dev);
1482
1483         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1484         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1485
1486         intel_uncore_forcewake_reset(dev_priv, false);
1487         intel_opregion_unregister(dev_priv);
1488
1489         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1490
1491         dev_priv->suspend_count++;
1492
1493         intel_display_set_init_power(dev_priv, false);
1494
1495         intel_csr_ucode_suspend(dev_priv);
1496
1497 out:
1498         enable_rpm_wakeref_asserts(dev_priv);
1499
1500         return error;
1501 }
1502
1503 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
1504 {
1505         struct drm_i915_private *dev_priv = to_i915(drm_dev);
1506         bool fw_csr;
1507         int ret;
1508
1509         disable_rpm_wakeref_asserts(dev_priv);
1510
1511         fw_csr = !IS_BROXTON(dev_priv) &&
1512                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1513         /*
1514          * In case of firmware assisted context save/restore don't manually
1515          * deinit the power domains. This also means the CSR/DMC firmware will
1516          * stay active, it will power down any HW resources as required and
1517          * also enable deeper system power states that would be blocked if the
1518          * firmware was inactive.
1519          */
1520         if (!fw_csr)
1521                 intel_power_domains_suspend(dev_priv);
1522
1523         ret = 0;
1524         if (IS_BROXTON(dev_priv))
1525                 bxt_enable_dc9(dev_priv);
1526         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1527                 hsw_enable_pc8(dev_priv);
1528         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1529                 ret = vlv_suspend_complete(dev_priv);
1530
1531         if (ret) {
1532                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1533                 if (!fw_csr)
1534                         intel_power_domains_init_hw(dev_priv, true);
1535
1536                 goto out;
1537         }
1538
1539         pci_disable_device(drm_dev->pdev);
1540         /*
1541          * During hibernation on some platforms the BIOS may try to access
1542          * the device even though it's already in D3 and hang the machine. So
1543          * leave the device in D0 on those platforms and hope the BIOS will
1544          * power down the device properly. The issue was seen on multiple old
1545          * GENs with different BIOS vendors, so having an explicit blacklist
1546          * is inpractical; apply the workaround on everything pre GEN6. The
1547          * platforms where the issue was seen:
1548          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1549          * Fujitsu FSC S7110
1550          * Acer Aspire 1830T
1551          */
1552         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
1553                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
1554
1555         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1556
1557 out:
1558         enable_rpm_wakeref_asserts(dev_priv);
1559
1560         return ret;
1561 }
1562
1563 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1564 {
1565         int error;
1566
1567         if (!dev) {
1568                 DRM_ERROR("dev: %p\n", dev);
1569                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1570                 return -ENODEV;
1571         }
1572
1573         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1574                          state.event != PM_EVENT_FREEZE))
1575                 return -EINVAL;
1576
1577         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1578                 return 0;
1579
1580         error = i915_drm_suspend(dev);
1581         if (error)
1582                 return error;
1583
1584         return i915_drm_suspend_late(dev, false);
1585 }
1586
1587 static int i915_drm_resume(struct drm_device *dev)
1588 {
1589         struct drm_i915_private *dev_priv = to_i915(dev);
1590         int ret;
1591
1592         disable_rpm_wakeref_asserts(dev_priv);
1593
1594         ret = i915_ggtt_enable_hw(dev);
1595         if (ret)
1596                 DRM_ERROR("failed to re-enable GGTT\n");
1597
1598         intel_csr_ucode_resume(dev_priv);
1599
1600         mutex_lock(&dev->struct_mutex);
1601         i915_gem_restore_gtt_mappings(dev);
1602         mutex_unlock(&dev->struct_mutex);
1603
1604         i915_restore_state(dev);
1605         intel_opregion_setup(dev_priv);
1606
1607         intel_init_pch_refclk(dev);
1608         drm_mode_config_reset(dev);
1609
1610         /*
1611          * Interrupts have to be enabled before any batches are run. If not the
1612          * GPU will hang. i915_gem_init_hw() will initiate batches to
1613          * update/restore the context.
1614          *
1615          * Modeset enabling in intel_modeset_init_hw() also needs working
1616          * interrupts.
1617          */
1618         intel_runtime_pm_enable_interrupts(dev_priv);
1619
1620         mutex_lock(&dev->struct_mutex);
1621         if (i915_gem_init_hw(dev)) {
1622                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1623                 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
1624         }
1625         mutex_unlock(&dev->struct_mutex);
1626
1627         intel_guc_resume(dev);
1628
1629         intel_modeset_init_hw(dev);
1630
1631         spin_lock_irq(&dev_priv->irq_lock);
1632         if (dev_priv->display.hpd_irq_setup)
1633                 dev_priv->display.hpd_irq_setup(dev_priv);
1634         spin_unlock_irq(&dev_priv->irq_lock);
1635
1636         intel_dp_mst_resume(dev);
1637
1638         intel_display_resume(dev);
1639
1640         /*
1641          * ... but also need to make sure that hotplug processing
1642          * doesn't cause havoc. Like in the driver load code we don't
1643          * bother with the tiny race here where we might loose hotplug
1644          * notifications.
1645          * */
1646         intel_hpd_init(dev_priv);
1647         /* Config may have changed between suspend and resume */
1648         drm_helper_hpd_irq_event(dev);
1649
1650         intel_opregion_register(dev_priv);
1651
1652         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1653
1654         mutex_lock(&dev_priv->modeset_restore_lock);
1655         dev_priv->modeset_restore = MODESET_DONE;
1656         mutex_unlock(&dev_priv->modeset_restore_lock);
1657
1658         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1659
1660         drm_kms_helper_poll_enable(dev);
1661
1662         enable_rpm_wakeref_asserts(dev_priv);
1663
1664         return 0;
1665 }
1666
1667 static int i915_drm_resume_early(struct drm_device *dev)
1668 {
1669         struct drm_i915_private *dev_priv = to_i915(dev);
1670         int ret;
1671
1672         /*
1673          * We have a resume ordering issue with the snd-hda driver also
1674          * requiring our device to be power up. Due to the lack of a
1675          * parent/child relationship we currently solve this with an early
1676          * resume hook.
1677          *
1678          * FIXME: This should be solved with a special hdmi sink device or
1679          * similar so that power domains can be employed.
1680          */
1681
1682         /*
1683          * Note that we need to set the power state explicitly, since we
1684          * powered off the device during freeze and the PCI core won't power
1685          * it back up for us during thaw. Powering off the device during
1686          * freeze is not a hard requirement though, and during the
1687          * suspend/resume phases the PCI core makes sure we get here with the
1688          * device powered on. So in case we change our freeze logic and keep
1689          * the device powered we can also remove the following set power state
1690          * call.
1691          */
1692         ret = pci_set_power_state(dev->pdev, PCI_D0);
1693         if (ret) {
1694                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1695                 goto out;
1696         }
1697
1698         /*
1699          * Note that pci_enable_device() first enables any parent bridge
1700          * device and only then sets the power state for this device. The
1701          * bridge enabling is a nop though, since bridge devices are resumed
1702          * first. The order of enabling power and enabling the device is
1703          * imposed by the PCI core as described above, so here we preserve the
1704          * same order for the freeze/thaw phases.
1705          *
1706          * TODO: eventually we should remove pci_disable_device() /
1707          * pci_enable_enable_device() from suspend/resume. Due to how they
1708          * depend on the device enable refcount we can't anyway depend on them
1709          * disabling/enabling the device.
1710          */
1711         if (pci_enable_device(dev->pdev)) {
1712                 ret = -EIO;
1713                 goto out;
1714         }
1715
1716         pci_set_master(dev->pdev);
1717
1718         disable_rpm_wakeref_asserts(dev_priv);
1719
1720         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1721                 ret = vlv_resume_prepare(dev_priv, false);
1722         if (ret)
1723                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1724                           ret);
1725
1726         intel_uncore_early_sanitize(dev_priv, true);
1727
1728         if (IS_BROXTON(dev_priv)) {
1729                 if (!dev_priv->suspended_to_idle)
1730                         gen9_sanitize_dc_state(dev_priv);
1731                 bxt_disable_dc9(dev_priv);
1732         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1733                 hsw_disable_pc8(dev_priv);
1734         }
1735
1736         intel_uncore_sanitize(dev_priv);
1737
1738         if (IS_BROXTON(dev_priv) ||
1739             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1740                 intel_power_domains_init_hw(dev_priv, true);
1741
1742         enable_rpm_wakeref_asserts(dev_priv);
1743
1744 out:
1745         dev_priv->suspended_to_idle = false;
1746
1747         return ret;
1748 }
1749
1750 int i915_resume_switcheroo(struct drm_device *dev)
1751 {
1752         int ret;
1753
1754         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1755                 return 0;
1756
1757         ret = i915_drm_resume_early(dev);
1758         if (ret)
1759                 return ret;
1760
1761         return i915_drm_resume(dev);
1762 }
1763
1764 /**
1765  * i915_reset - reset chip after a hang
1766  * @dev: drm device to reset
1767  *
1768  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
1769  * reset or otherwise an error code.
1770  *
1771  * Procedure is fairly simple:
1772  *   - reset the chip using the reset reg
1773  *   - re-init context state
1774  *   - re-init hardware status page
1775  *   - re-init ring buffer
1776  *   - re-init interrupt state
1777  *   - re-init display
1778  */
1779 int i915_reset(struct drm_i915_private *dev_priv)
1780 {
1781         struct drm_device *dev = &dev_priv->drm;
1782         struct i915_gpu_error *error = &dev_priv->gpu_error;
1783         unsigned reset_counter;
1784         int ret;
1785
1786         intel_reset_gt_powersave(dev_priv);
1787
1788         mutex_lock(&dev->struct_mutex);
1789
1790         /* Clear any previous failed attempts at recovery. Time to try again. */
1791         atomic_andnot(I915_WEDGED, &error->reset_counter);
1792
1793         /* Clear the reset-in-progress flag and increment the reset epoch. */
1794         reset_counter = atomic_inc_return(&error->reset_counter);
1795         if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
1796                 ret = -EIO;
1797                 goto error;
1798         }
1799
1800         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1801
1802         i915_gem_reset(dev);
1803
1804         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1805         if (ret) {
1806                 if (ret != -ENODEV)
1807                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1808                 else
1809                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1810                 goto error;
1811         }
1812
1813         intel_overlay_reset(dev_priv);
1814
1815         /* Ok, now get things going again... */
1816
1817         /*
1818          * Everything depends on having the GTT running, so we need to start
1819          * there.  Fortunately we don't need to do this unless we reset the
1820          * chip at a PCI level.
1821          *
1822          * Next we need to restore the context, but we don't use those
1823          * yet either...
1824          *
1825          * Ring buffer needs to be re-initialized in the KMS case, or if X
1826          * was running at the time of the reset (i.e. we weren't VT
1827          * switched away).
1828          */
1829         ret = i915_gem_init_hw(dev);
1830         if (ret) {
1831                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1832                 goto error;
1833         }
1834
1835         mutex_unlock(&dev->struct_mutex);
1836
1837         /*
1838          * rps/rc6 re-init is necessary to restore state lost after the
1839          * reset and the re-install of gt irqs. Skip for ironlake per
1840          * previous concerns that it doesn't respond well to some forms
1841          * of re-init after reset.
1842          */
1843         if (INTEL_INFO(dev)->gen > 5)
1844                 intel_enable_gt_powersave(dev_priv);
1845
1846         return 0;
1847
1848 error:
1849         atomic_or(I915_WEDGED, &error->reset_counter);
1850         mutex_unlock(&dev->struct_mutex);
1851         return ret;
1852 }
1853
1854 static int i915_pm_suspend(struct device *dev)
1855 {
1856         struct pci_dev *pdev = to_pci_dev(dev);
1857         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1858
1859         if (!drm_dev) {
1860                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1861                 return -ENODEV;
1862         }
1863
1864         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1865                 return 0;
1866
1867         return i915_drm_suspend(drm_dev);
1868 }
1869
1870 static int i915_pm_suspend_late(struct device *dev)
1871 {
1872         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1873
1874         /*
1875          * We have a suspend ordering issue with the snd-hda driver also
1876          * requiring our device to be power up. Due to the lack of a
1877          * parent/child relationship we currently solve this with an late
1878          * suspend hook.
1879          *
1880          * FIXME: This should be solved with a special hdmi sink device or
1881          * similar so that power domains can be employed.
1882          */
1883         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1884                 return 0;
1885
1886         return i915_drm_suspend_late(drm_dev, false);
1887 }
1888
1889 static int i915_pm_poweroff_late(struct device *dev)
1890 {
1891         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1892
1893         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1894                 return 0;
1895
1896         return i915_drm_suspend_late(drm_dev, true);
1897 }
1898
1899 static int i915_pm_resume_early(struct device *dev)
1900 {
1901         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1902
1903         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1904                 return 0;
1905
1906         return i915_drm_resume_early(drm_dev);
1907 }
1908
1909 static int i915_pm_resume(struct device *dev)
1910 {
1911         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1912
1913         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1914                 return 0;
1915
1916         return i915_drm_resume(drm_dev);
1917 }
1918
1919 /* freeze: before creating the hibernation_image */
1920 static int i915_pm_freeze(struct device *dev)
1921 {
1922         return i915_pm_suspend(dev);
1923 }
1924
1925 static int i915_pm_freeze_late(struct device *dev)
1926 {
1927         int ret;
1928
1929         ret = i915_pm_suspend_late(dev);
1930         if (ret)
1931                 return ret;
1932
1933         ret = i915_gem_freeze_late(dev_to_i915(dev));
1934         if (ret)
1935                 return ret;
1936
1937         return 0;
1938 }
1939
1940 /* thaw: called after creating the hibernation image, but before turning off. */
1941 static int i915_pm_thaw_early(struct device *dev)
1942 {
1943         return i915_pm_resume_early(dev);
1944 }
1945
1946 static int i915_pm_thaw(struct device *dev)
1947 {
1948         return i915_pm_resume(dev);
1949 }
1950
1951 /* restore: called after loading the hibernation image. */
1952 static int i915_pm_restore_early(struct device *dev)
1953 {
1954         return i915_pm_resume_early(dev);
1955 }
1956
1957 static int i915_pm_restore(struct device *dev)
1958 {
1959         return i915_pm_resume(dev);
1960 }
1961
1962 /*
1963  * Save all Gunit registers that may be lost after a D3 and a subsequent
1964  * S0i[R123] transition. The list of registers needing a save/restore is
1965  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1966  * registers in the following way:
1967  * - Driver: saved/restored by the driver
1968  * - Punit : saved/restored by the Punit firmware
1969  * - No, w/o marking: no need to save/restore, since the register is R/O or
1970  *                    used internally by the HW in a way that doesn't depend
1971  *                    keeping the content across a suspend/resume.
1972  * - Debug : used for debugging
1973  *
1974  * We save/restore all registers marked with 'Driver', with the following
1975  * exceptions:
1976  * - Registers out of use, including also registers marked with 'Debug'.
1977  *   These have no effect on the driver's operation, so we don't save/restore
1978  *   them to reduce the overhead.
1979  * - Registers that are fully setup by an initialization function called from
1980  *   the resume path. For example many clock gating and RPS/RC6 registers.
1981  * - Registers that provide the right functionality with their reset defaults.
1982  *
1983  * TODO: Except for registers that based on the above 3 criteria can be safely
1984  * ignored, we save/restore all others, practically treating the HW context as
1985  * a black-box for the driver. Further investigation is needed to reduce the
1986  * saved/restored registers even further, by following the same 3 criteria.
1987  */
1988 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1989 {
1990         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1991         int i;
1992
1993         /* GAM 0x4000-0x4770 */
1994         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1995         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1996         s->arb_mode             = I915_READ(ARB_MODE);
1997         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1998         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1999
2000         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2001                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2002
2003         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2004         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2005
2006         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2007         s->ecochk               = I915_READ(GAM_ECOCHK);
2008         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2009         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2010
2011         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2012
2013         /* MBC 0x9024-0x91D0, 0x8500 */
2014         s->g3dctl               = I915_READ(VLV_G3DCTL);
2015         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2016         s->mbctl                = I915_READ(GEN6_MBCTL);
2017
2018         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2019         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2020         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2021         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2022         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2023         s->rstctl               = I915_READ(GEN6_RSTCTL);
2024         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2025
2026         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2027         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2028         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2029         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2030         s->ecobus               = I915_READ(ECOBUS);
2031         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2032         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2033         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2034         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2035         s->rcedata              = I915_READ(VLV_RCEDATA);
2036         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2037
2038         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2039         s->gt_imr               = I915_READ(GTIMR);
2040         s->gt_ier               = I915_READ(GTIER);
2041         s->pm_imr               = I915_READ(GEN6_PMIMR);
2042         s->pm_ier               = I915_READ(GEN6_PMIER);
2043
2044         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2045                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2046
2047         /* GT SA CZ domain, 0x100000-0x138124 */
2048         s->tilectl              = I915_READ(TILECTL);
2049         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2050         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2051         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2052         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2053
2054         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2055         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2056         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2057         s->pcbr                 = I915_READ(VLV_PCBR);
2058         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2059
2060         /*
2061          * Not saving any of:
2062          * DFT,         0x9800-0x9EC0
2063          * SARB,        0xB000-0xB1FC
2064          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2065          * PCI CFG
2066          */
2067 }
2068
2069 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2070 {
2071         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2072         u32 val;
2073         int i;
2074
2075         /* GAM 0x4000-0x4770 */
2076         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2077         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2078         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2079         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2080         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2081
2082         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2083                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2084
2085         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2086         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2087
2088         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2089         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2090         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2091         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2092
2093         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2094
2095         /* MBC 0x9024-0x91D0, 0x8500 */
2096         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2097         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2098         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2099
2100         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2101         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2102         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2103         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2104         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2105         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2106         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2107
2108         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2109         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2110         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2111         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2112         I915_WRITE(ECOBUS,              s->ecobus);
2113         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2114         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2115         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2116         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2117         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2118         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2119
2120         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2121         I915_WRITE(GTIMR,               s->gt_imr);
2122         I915_WRITE(GTIER,               s->gt_ier);
2123         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2124         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2125
2126         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2127                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2128
2129         /* GT SA CZ domain, 0x100000-0x138124 */
2130         I915_WRITE(TILECTL,                     s->tilectl);
2131         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2132         /*
2133          * Preserve the GT allow wake and GFX force clock bit, they are not
2134          * be restored, as they are used to control the s0ix suspend/resume
2135          * sequence by the caller.
2136          */
2137         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2138         val &= VLV_GTLC_ALLOWWAKEREQ;
2139         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2140         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2141
2142         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2143         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2144         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2145         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2146
2147         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2148
2149         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2150         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2151         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2152         I915_WRITE(VLV_PCBR,                    s->pcbr);
2153         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2154 }
2155
2156 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2157 {
2158         u32 val;
2159         int err;
2160
2161         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2162         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2163         if (force_on)
2164                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2165         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2166
2167         if (!force_on)
2168                 return 0;
2169
2170         err = intel_wait_for_register(dev_priv,
2171                                       VLV_GTLC_SURVIVABILITY_REG,
2172                                       VLV_GFX_CLK_STATUS_BIT,
2173                                       VLV_GFX_CLK_STATUS_BIT,
2174                                       20);
2175         if (err)
2176                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2177                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2178
2179         return err;
2180 }
2181
2182 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2183 {
2184         u32 val;
2185         int err = 0;
2186
2187         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2188         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2189         if (allow)
2190                 val |= VLV_GTLC_ALLOWWAKEREQ;
2191         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2192         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2193
2194         err = intel_wait_for_register(dev_priv,
2195                                       VLV_GTLC_PW_STATUS,
2196                                       VLV_GTLC_ALLOWWAKEACK,
2197                                       allow,
2198                                       1);
2199         if (err)
2200                 DRM_ERROR("timeout disabling GT waking\n");
2201
2202         return err;
2203 }
2204
2205 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2206                                  bool wait_for_on)
2207 {
2208         u32 mask;
2209         u32 val;
2210         int err;
2211
2212         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2213         val = wait_for_on ? mask : 0;
2214         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2215                 return 0;
2216
2217         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2218                       onoff(wait_for_on),
2219                       I915_READ(VLV_GTLC_PW_STATUS));
2220
2221         /*
2222          * RC6 transitioning can be delayed up to 2 msec (see
2223          * valleyview_enable_rps), use 3 msec for safety.
2224          */
2225         err = intel_wait_for_register(dev_priv,
2226                                       VLV_GTLC_PW_STATUS, mask, val,
2227                                       3);
2228         if (err)
2229                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2230                           onoff(wait_for_on));
2231
2232         return err;
2233 }
2234
2235 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2236 {
2237         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2238                 return;
2239
2240         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2241         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2242 }
2243
2244 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2245 {
2246         u32 mask;
2247         int err;
2248
2249         /*
2250          * Bspec defines the following GT well on flags as debug only, so
2251          * don't treat them as hard failures.
2252          */
2253         (void)vlv_wait_for_gt_wells(dev_priv, false);
2254
2255         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2256         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2257
2258         vlv_check_no_gt_access(dev_priv);
2259
2260         err = vlv_force_gfx_clock(dev_priv, true);
2261         if (err)
2262                 goto err1;
2263
2264         err = vlv_allow_gt_wake(dev_priv, false);
2265         if (err)
2266                 goto err2;
2267
2268         if (!IS_CHERRYVIEW(dev_priv))
2269                 vlv_save_gunit_s0ix_state(dev_priv);
2270
2271         err = vlv_force_gfx_clock(dev_priv, false);
2272         if (err)
2273                 goto err2;
2274
2275         return 0;
2276
2277 err2:
2278         /* For safety always re-enable waking and disable gfx clock forcing */
2279         vlv_allow_gt_wake(dev_priv, true);
2280 err1:
2281         vlv_force_gfx_clock(dev_priv, false);
2282
2283         return err;
2284 }
2285
2286 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2287                                 bool rpm_resume)
2288 {
2289         struct drm_device *dev = &dev_priv->drm;
2290         int err;
2291         int ret;
2292
2293         /*
2294          * If any of the steps fail just try to continue, that's the best we
2295          * can do at this point. Return the first error code (which will also
2296          * leave RPM permanently disabled).
2297          */
2298         ret = vlv_force_gfx_clock(dev_priv, true);
2299
2300         if (!IS_CHERRYVIEW(dev_priv))
2301                 vlv_restore_gunit_s0ix_state(dev_priv);
2302
2303         err = vlv_allow_gt_wake(dev_priv, true);
2304         if (!ret)
2305                 ret = err;
2306
2307         err = vlv_force_gfx_clock(dev_priv, false);
2308         if (!ret)
2309                 ret = err;
2310
2311         vlv_check_no_gt_access(dev_priv);
2312
2313         if (rpm_resume) {
2314                 intel_init_clock_gating(dev);
2315                 i915_gem_restore_fences(dev);
2316         }
2317
2318         return ret;
2319 }
2320
2321 static int intel_runtime_suspend(struct device *device)
2322 {
2323         struct pci_dev *pdev = to_pci_dev(device);
2324         struct drm_device *dev = pci_get_drvdata(pdev);
2325         struct drm_i915_private *dev_priv = to_i915(dev);
2326         int ret;
2327
2328         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2329                 return -ENODEV;
2330
2331         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2332                 return -ENODEV;
2333
2334         DRM_DEBUG_KMS("Suspending device\n");
2335
2336         /*
2337          * We could deadlock here in case another thread holding struct_mutex
2338          * calls RPM suspend concurrently, since the RPM suspend will wait
2339          * first for this RPM suspend to finish. In this case the concurrent
2340          * RPM resume will be followed by its RPM suspend counterpart. Still
2341          * for consistency return -EAGAIN, which will reschedule this suspend.
2342          */
2343         if (!mutex_trylock(&dev->struct_mutex)) {
2344                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2345                 /*
2346                  * Bump the expiration timestamp, otherwise the suspend won't
2347                  * be rescheduled.
2348                  */
2349                 pm_runtime_mark_last_busy(device);
2350
2351                 return -EAGAIN;
2352         }
2353
2354         disable_rpm_wakeref_asserts(dev_priv);
2355
2356         /*
2357          * We are safe here against re-faults, since the fault handler takes
2358          * an RPM reference.
2359          */
2360         i915_gem_release_all_mmaps(dev_priv);
2361         mutex_unlock(&dev->struct_mutex);
2362
2363         intel_guc_suspend(dev);
2364
2365         intel_runtime_pm_disable_interrupts(dev_priv);
2366
2367         ret = 0;
2368         if (IS_BROXTON(dev_priv)) {
2369                 bxt_display_core_uninit(dev_priv);
2370                 bxt_enable_dc9(dev_priv);
2371         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2372                 hsw_enable_pc8(dev_priv);
2373         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2374                 ret = vlv_suspend_complete(dev_priv);
2375         }
2376
2377         if (ret) {
2378                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2379                 intel_runtime_pm_enable_interrupts(dev_priv);
2380
2381                 enable_rpm_wakeref_asserts(dev_priv);
2382
2383                 return ret;
2384         }
2385
2386         intel_uncore_forcewake_reset(dev_priv, false);
2387
2388         enable_rpm_wakeref_asserts(dev_priv);
2389         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2390
2391         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2392                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2393
2394         dev_priv->pm.suspended = true;
2395
2396         /*
2397          * FIXME: We really should find a document that references the arguments
2398          * used below!
2399          */
2400         if (IS_BROADWELL(dev_priv)) {
2401                 /*
2402                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2403                  * being detected, and the call we do at intel_runtime_resume()
2404                  * won't be able to restore them. Since PCI_D3hot matches the
2405                  * actual specification and appears to be working, use it.
2406                  */
2407                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2408         } else {
2409                 /*
2410                  * current versions of firmware which depend on this opregion
2411                  * notification have repurposed the D1 definition to mean
2412                  * "runtime suspended" vs. what you would normally expect (D3)
2413                  * to distinguish it from notifications that might be sent via
2414                  * the suspend path.
2415                  */
2416                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2417         }
2418
2419         assert_forcewakes_inactive(dev_priv);
2420
2421         if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
2422                 intel_hpd_poll_init(dev_priv);
2423
2424         DRM_DEBUG_KMS("Device suspended\n");
2425         return 0;
2426 }
2427
2428 static int intel_runtime_resume(struct device *device)
2429 {
2430         struct pci_dev *pdev = to_pci_dev(device);
2431         struct drm_device *dev = pci_get_drvdata(pdev);
2432         struct drm_i915_private *dev_priv = to_i915(dev);
2433         int ret = 0;
2434
2435         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2436                 return -ENODEV;
2437
2438         DRM_DEBUG_KMS("Resuming device\n");
2439
2440         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2441         disable_rpm_wakeref_asserts(dev_priv);
2442
2443         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2444         dev_priv->pm.suspended = false;
2445         if (intel_uncore_unclaimed_mmio(dev_priv))
2446                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2447
2448         intel_guc_resume(dev);
2449
2450         if (IS_GEN6(dev_priv))
2451                 intel_init_pch_refclk(dev);
2452
2453         if (IS_BROXTON(dev)) {
2454                 bxt_disable_dc9(dev_priv);
2455                 bxt_display_core_init(dev_priv, true);
2456                 if (dev_priv->csr.dmc_payload &&
2457                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2458                         gen9_enable_dc5(dev_priv);
2459         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2460                 hsw_disable_pc8(dev_priv);
2461         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2462                 ret = vlv_resume_prepare(dev_priv, true);
2463         }
2464
2465         /*
2466          * No point of rolling back things in case of an error, as the best
2467          * we can do is to hope that things will still work (and disable RPM).
2468          */
2469         i915_gem_init_swizzling(dev);
2470         gen6_update_ring_freq(dev_priv);
2471
2472         intel_runtime_pm_enable_interrupts(dev_priv);
2473
2474         /*
2475          * On VLV/CHV display interrupts are part of the display
2476          * power well, so hpd is reinitialized from there. For
2477          * everyone else do it here.
2478          */
2479         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2480                 intel_hpd_init(dev_priv);
2481
2482         enable_rpm_wakeref_asserts(dev_priv);
2483
2484         if (ret)
2485                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2486         else
2487                 DRM_DEBUG_KMS("Device resumed\n");
2488
2489         return ret;
2490 }
2491
2492 const struct dev_pm_ops i915_pm_ops = {
2493         /*
2494          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2495          * PMSG_RESUME]
2496          */
2497         .suspend = i915_pm_suspend,
2498         .suspend_late = i915_pm_suspend_late,
2499         .resume_early = i915_pm_resume_early,
2500         .resume = i915_pm_resume,
2501
2502         /*
2503          * S4 event handlers
2504          * @freeze, @freeze_late    : called (1) before creating the
2505          *                            hibernation image [PMSG_FREEZE] and
2506          *                            (2) after rebooting, before restoring
2507          *                            the image [PMSG_QUIESCE]
2508          * @thaw, @thaw_early       : called (1) after creating the hibernation
2509          *                            image, before writing it [PMSG_THAW]
2510          *                            and (2) after failing to create or
2511          *                            restore the image [PMSG_RECOVER]
2512          * @poweroff, @poweroff_late: called after writing the hibernation
2513          *                            image, before rebooting [PMSG_HIBERNATE]
2514          * @restore, @restore_early : called after rebooting and restoring the
2515          *                            hibernation image [PMSG_RESTORE]
2516          */
2517         .freeze = i915_pm_freeze,
2518         .freeze_late = i915_pm_freeze_late,
2519         .thaw_early = i915_pm_thaw_early,
2520         .thaw = i915_pm_thaw,
2521         .poweroff = i915_pm_suspend,
2522         .poweroff_late = i915_pm_poweroff_late,
2523         .restore_early = i915_pm_restore_early,
2524         .restore = i915_pm_restore,
2525
2526         /* S0ix (via runtime suspend) event handlers */
2527         .runtime_suspend = intel_runtime_suspend,
2528         .runtime_resume = intel_runtime_resume,
2529 };
2530
2531 static const struct vm_operations_struct i915_gem_vm_ops = {
2532         .fault = i915_gem_fault,
2533         .open = drm_gem_vm_open,
2534         .close = drm_gem_vm_close,
2535 };
2536
2537 static const struct file_operations i915_driver_fops = {
2538         .owner = THIS_MODULE,
2539         .open = drm_open,
2540         .release = drm_release,
2541         .unlocked_ioctl = drm_ioctl,
2542         .mmap = drm_gem_mmap,
2543         .poll = drm_poll,
2544         .read = drm_read,
2545 #ifdef CONFIG_COMPAT
2546         .compat_ioctl = i915_compat_ioctl,
2547 #endif
2548         .llseek = noop_llseek,
2549 };
2550
2551 static int
2552 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2553                           struct drm_file *file)
2554 {
2555         return -ENODEV;
2556 }
2557
2558 static const struct drm_ioctl_desc i915_ioctls[] = {
2559         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2560         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2561         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2562         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2563         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2564         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2565         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2566         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2567         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2568         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2569         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2570         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2571         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2572         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2573         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2574         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2575         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2576         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2577         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2578         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2579         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2580         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2581         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2582         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2583         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2584         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2585         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2586         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2587         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2588         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2589         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2590         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2591         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2592         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2593         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2594         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2595         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2596         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2597         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2598         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2599         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2600         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2601         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2602         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2603         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2604         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2605         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2606         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2607         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2608         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2609         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2610         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2611 };
2612
2613 static struct drm_driver driver = {
2614         /* Don't use MTRRs here; the Xserver or userspace app should
2615          * deal with them for Intel hardware.
2616          */
2617         .driver_features =
2618             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2619             DRIVER_RENDER | DRIVER_MODESET,
2620         .open = i915_driver_open,
2621         .lastclose = i915_driver_lastclose,
2622         .preclose = i915_driver_preclose,
2623         .postclose = i915_driver_postclose,
2624         .set_busid = drm_pci_set_busid,
2625
2626         .gem_free_object = i915_gem_free_object,
2627         .gem_vm_ops = &i915_gem_vm_ops,
2628
2629         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2630         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2631         .gem_prime_export = i915_gem_prime_export,
2632         .gem_prime_import = i915_gem_prime_import,
2633
2634         .dumb_create = i915_gem_dumb_create,
2635         .dumb_map_offset = i915_gem_mmap_gtt,
2636         .dumb_destroy = drm_gem_dumb_destroy,
2637         .ioctls = i915_ioctls,
2638         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2639         .fops = &i915_driver_fops,
2640         .name = DRIVER_NAME,
2641         .desc = DRIVER_DESC,
2642         .date = DRIVER_DATE,
2643         .major = DRIVER_MAJOR,
2644         .minor = DRIVER_MINOR,
2645         .patchlevel = DRIVER_PATCHLEVEL,
2646 };