drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fpga_dbg = 1,
 307         .has_fbc = 1,
 308         GEN_DEFAULT_PIPEOFFSETS,
 309         IVB_CURSOR_OFFSETS,
 310 };
 311
 312 static const struct intel_device_info intel_broadwell_m_info = {
 313         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 314         .need_gfx_hws = 1, .has_hotplug = 1,
 315         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 316         .has_llc = 1,
 317         .has_ddi = 1,
 318         .has_fpga_dbg = 1,
 319         .has_fbc = 1,
 320         GEN_DEFAULT_PIPEOFFSETS,
 321         IVB_CURSOR_OFFSETS,
 322 };
 323
 324 static const struct intel_device_info intel_broadwell_gt3d_info = {
 325         .gen = 8, .num_pipes = 3,
 326         .need_gfx_hws = 1, .has_hotplug = 1,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328         .has_llc = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333         IVB_CURSOR_OFFSETS,
 334 };
 335
 336 static const struct intel_device_info intel_broadwell_gt3m_info = {
 337         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 338         .need_gfx_hws = 1, .has_hotplug = 1,
 339         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 340         .has_llc = 1,
 341         .has_ddi = 1,
 342         .has_fpga_dbg = 1,
 343         .has_fbc = 1,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346 };
 347
 348 static const struct intel_device_info intel_cherryview_info = {
 349         .gen = 8, .num_pipes = 3,
 350         .need_gfx_hws = 1, .has_hotplug = 1,
 351         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 352         .is_valleyview = 1,
 353         .display_mmio_offset = VLV_DISPLAY_BASE,
 354         GEN_CHV_PIPEOFFSETS,
 355         CURSOR_OFFSETS,
 356 };
 357
 358 static const struct intel_device_info intel_skylake_info = {
 359         .is_preliminary = 1,
 360         .is_skylake = 1,
 361         .gen = 9, .num_pipes = 3,
 362         .need_gfx_hws = 1, .has_hotplug = 1,
 363         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 364         .has_llc = 1,
 365         .has_ddi = 1,
 366         .has_fbc = 1,
 367         GEN_DEFAULT_PIPEOFFSETS,
 368         IVB_CURSOR_OFFSETS,
 369 };
 370
 371 static const struct intel_device_info intel_skylake_gt3_info = {
 372         .is_preliminary = 1,
 373         .is_skylake = 1,
 374         .gen = 9, .num_pipes = 3,
 375         .need_gfx_hws = 1, .has_hotplug = 1,
 376         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 377         .has_llc = 1,
 378         .has_ddi = 1,
 379         .has_fbc = 1,
 380         GEN_DEFAULT_PIPEOFFSETS,
 381         IVB_CURSOR_OFFSETS,
 382 };
 383
 384 /*
 385  * Make sure any device matches here are from most specific to most
 386  * general.  For example, since the Quanta match is based on the subsystem
 387  * and subvendor IDs, we need it to come before the more general IVB
 388  * PCI ID matches, otherwise we'll use the wrong info struct above.
 389  */
 390 #define INTEL_PCI_IDS \
 391         INTEL_I830_IDS(&intel_i830_info),       \
 392         INTEL_I845G_IDS(&intel_845g_info),      \
 393         INTEL_I85X_IDS(&intel_i85x_info),       \
 394         INTEL_I865G_IDS(&intel_i865g_info),     \
 395         INTEL_I915G_IDS(&intel_i915g_info),     \
 396         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 397         INTEL_I945G_IDS(&intel_i945g_info),     \
 398         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 399         INTEL_I965G_IDS(&intel_i965g_info),     \
 400         INTEL_G33_IDS(&intel_g33_info),         \
 401         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 402         INTEL_GM45_IDS(&intel_gm45_info),       \
 403         INTEL_G45_IDS(&intel_g45_info),         \
 404         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 405         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 406         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 407         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 408         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 409         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 410         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 411         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 412         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 413         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 414         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 415         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 416         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 417         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 418         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 419         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 420         INTEL_CHV_IDS(&intel_cherryview_info),  \
 421         INTEL_SKL_GT1_IDS(&intel_skylake_info), \
 422         INTEL_SKL_GT2_IDS(&intel_skylake_info), \
 423         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info)      \
 424
 425 static const struct pci_device_id pciidlist[] = {               /* aka */
 426         INTEL_PCI_IDS,
 427         {0, 0, 0}
 428 };
 429
 430 #if defined(CONFIG_DRM_I915_KMS)
 431 MODULE_DEVICE_TABLE(pci, pciidlist);
 432 #endif
 433
 434 void intel_detect_pch(struct drm_device *dev)
 435 {
 436         struct drm_i915_private *dev_priv = dev->dev_private;
 437         struct pci_dev *pch = NULL;
 438
 439         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 440          * (which really amounts to a PCH but no South Display).
 441          */
 442         if (INTEL_INFO(dev)->num_pipes == 0) {
 443                 dev_priv->pch_type = PCH_NOP;
 444                 return;
 445         }
 446
 447         /*
 448          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 449          * make graphics device passthrough work easy for VMM, that only
 450          * need to expose ISA bridge to let driver know the real hardware
 451          * underneath. This is a requirement from virtualization team.
 452          *
 453          * In some virtualized environments (e.g. XEN), there is irrelevant
 454          * ISA bridge in the system. To work reliably, we should scan trhough
 455          * all the ISA bridge devices and check for the first match, instead
 456          * of only checking the first one.
 457          */
 458         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 459                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 460                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 461                         dev_priv->pch_id = id;
 462
 463                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 464                                 dev_priv->pch_type = PCH_IBX;
 465                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 466                                 WARN_ON(!IS_GEN5(dev));
 467                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 468                                 dev_priv->pch_type = PCH_CPT;
 469                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 470                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 471                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 472                                 /* PantherPoint is CPT compatible */
 473                                 dev_priv->pch_type = PCH_CPT;
 474                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 475                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 476                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 477                                 dev_priv->pch_type = PCH_LPT;
 478                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 479                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 480                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 481                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 482                                 dev_priv->pch_type = PCH_LPT;
 483                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 484                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 485                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 486                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 487                                 dev_priv->pch_type = PCH_SPT;
 488                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 489                                 WARN_ON(!IS_SKYLAKE(dev));
 490                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 491                                 dev_priv->pch_type = PCH_SPT;
 492                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 493                                 WARN_ON(!IS_SKYLAKE(dev));
 494                         } else
 495                                 continue;
 496
 497                         break;
 498                 }
 499         }
 500         if (!pch)
 501                 DRM_DEBUG_KMS("No PCH found.\n");
 502
 503         pci_dev_put(pch);
 504 }
 505
 506 bool i915_semaphore_is_enabled(struct drm_device *dev)
 507 {
 508         if (INTEL_INFO(dev)->gen < 6)
 509                 return false;
 510
 511         if (i915.semaphores >= 0)
 512                 return i915.semaphores;
 513
 514         /* TODO: make semaphores and Execlists play nicely together */
 515         if (i915.enable_execlists)
 516                 return false;
 517
 518         /* Until we get further testing... */
 519         if (IS_GEN8(dev))
 520                 return false;
 521
 522 #ifdef CONFIG_INTEL_IOMMU
 523         /* Enable semaphores on SNB when IO remapping is off */
 524         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 525                 return false;
 526 #endif
 527
 528         return true;
 529 }
 530
 531 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
 532 {
 533         spin_lock_irq(&dev_priv->irq_lock);
 534
 535         dev_priv->long_hpd_port_mask = 0;
 536         dev_priv->short_hpd_port_mask = 0;
 537         dev_priv->hpd_event_bits = 0;
 538
 539         spin_unlock_irq(&dev_priv->irq_lock);
 540
 541         cancel_work_sync(&dev_priv->dig_port_work);
 542         cancel_work_sync(&dev_priv->hotplug_work);
 543         cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
 544 }
 545
 546 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 547 {
 548         struct drm_device *dev = dev_priv->dev;
 549         struct drm_encoder *encoder;
 550
 551         drm_modeset_lock_all(dev);
 552         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 553                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 554
 555                 if (intel_encoder->suspend)
 556                         intel_encoder->suspend(intel_encoder);
 557         }
 558         drm_modeset_unlock_all(dev);
 559 }
 560
 561 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 562 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 563                               bool rpm_resume);
 564
 565 static int i915_drm_suspend(struct drm_device *dev)
 566 {
 567         struct drm_i915_private *dev_priv = dev->dev_private;
 568         struct drm_crtc *crtc;
 569         pci_power_t opregion_target_state;
 570         int error;
 571
 572         /* ignore lid events during suspend */
 573         mutex_lock(&dev_priv->modeset_restore_lock);
 574         dev_priv->modeset_restore = MODESET_SUSPENDED;
 575         mutex_unlock(&dev_priv->modeset_restore_lock);
 576
 577         /* We do a lot of poking in a lot of registers, make sure they work
 578          * properly. */
 579         intel_display_set_init_power(dev_priv, true);
 580
 581         drm_kms_helper_poll_disable(dev);
 582
 583         pci_save_state(dev->pdev);
 584
 585         error = i915_gem_suspend(dev);
 586         if (error) {
 587                 dev_err(&dev->pdev->dev,
 588                         "GEM idle failed, resume might fail\n");
 589                 return error;
 590         }
 591
 592         intel_suspend_gt_powersave(dev);
 593
 594         /*
 595          * Disable CRTCs directly since we want to preserve sw state
 596          * for _thaw. Also, power gate the CRTC power wells.
 597          */
 598         drm_modeset_lock_all(dev);
 599         for_each_crtc(dev, crtc)
 600                 intel_crtc_control(crtc, false);
 601         drm_modeset_unlock_all(dev);
 602
 603         intel_dp_mst_suspend(dev);
 604
 605         intel_runtime_pm_disable_interrupts(dev_priv);
 606         intel_hpd_cancel_work(dev_priv);
 607
 608         intel_suspend_encoders(dev_priv);
 609
 610         intel_suspend_hw(dev);
 611
 612         i915_gem_suspend_gtt_mappings(dev);
 613
 614         i915_save_state(dev);
 615
 616         opregion_target_state = PCI_D3cold;
 617 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 618         if (acpi_target_system_state() < ACPI_STATE_S3)
 619                 opregion_target_state = PCI_D1;
 620 #endif
 621         intel_opregion_notify_adapter(dev, opregion_target_state);
 622
 623         intel_uncore_forcewake_reset(dev, false);
 624         intel_opregion_fini(dev);
 625
 626         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 627
 628         dev_priv->suspend_count++;
 629
 630         intel_display_set_init_power(dev_priv, false);
 631
 632         return 0;
 633 }
 634
 635 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 636 {
 637         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 638         int ret;
 639
 640         ret = intel_suspend_complete(dev_priv);
 641
 642         if (ret) {
 643                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 644
 645                 return ret;
 646         }
 647
 648         pci_disable_device(drm_dev->pdev);
 649         /*
 650          * During hibernation on some GEN4 platforms the BIOS may try to access
 651          * the device even though it's already in D3 and hang the machine. So
 652          * leave the device in D0 on those platforms and hope the BIOS will
 653          * power down the device properly. Platforms where this was seen:
 654          * Lenovo Thinkpad X301, X61s
 655          */
 656         if (!(hibernation &&
 657               drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
 658               INTEL_INFO(dev_priv)->gen == 4))
 659                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 660
 661         return 0;
 662 }
 663
 664 int i915_suspend_legacy(struct drm_device *dev, pm_message_t state)
 665 {
 666         int error;
 667
 668         if (!dev || !dev->dev_private) {
 669                 DRM_ERROR("dev: %p\n", dev);
 670                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 671                 return -ENODEV;
 672         }
 673
 674         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 675                          state.event != PM_EVENT_FREEZE))
 676                 return -EINVAL;
 677
 678         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 679                 return 0;
 680
 681         error = i915_drm_suspend(dev);
 682         if (error)
 683                 return error;
 684
 685         return i915_drm_suspend_late(dev, false);
 686 }
 687
 688 static int i915_drm_resume(struct drm_device *dev)
 689 {
 690         struct drm_i915_private *dev_priv = dev->dev_private;
 691
 692         mutex_lock(&dev->struct_mutex);
 693         i915_gem_restore_gtt_mappings(dev);
 694         mutex_unlock(&dev->struct_mutex);
 695
 696         i915_restore_state(dev);
 697         intel_opregion_setup(dev);
 698
 699         intel_init_pch_refclk(dev);
 700         drm_mode_config_reset(dev);
 701
 702         mutex_lock(&dev->struct_mutex);
 703         if (i915_gem_init_hw(dev)) {
 704                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 705                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 706         }
 707         mutex_unlock(&dev->struct_mutex);
 708
 709         /* We need working interrupts for modeset enabling ... */
 710         intel_runtime_pm_enable_interrupts(dev_priv);
 711
 712         intel_modeset_init_hw(dev);
 713
 714         spin_lock_irq(&dev_priv->irq_lock);
 715         if (dev_priv->display.hpd_irq_setup)
 716                 dev_priv->display.hpd_irq_setup(dev);
 717         spin_unlock_irq(&dev_priv->irq_lock);
 718
 719         drm_modeset_lock_all(dev);
 720         intel_modeset_setup_hw_state(dev, true);
 721         drm_modeset_unlock_all(dev);
 722
 723         intel_dp_mst_resume(dev);
 724
 725         /*
 726          * ... but also need to make sure that hotplug processing
 727          * doesn't cause havoc. Like in the driver load code we don't
 728          * bother with the tiny race here where we might loose hotplug
 729          * notifications.
 730          * */
 731         intel_hpd_init(dev_priv);
 732         /* Config may have changed between suspend and resume */
 733         drm_helper_hpd_irq_event(dev);
 734
 735         intel_opregion_init(dev);
 736
 737         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 738
 739         mutex_lock(&dev_priv->modeset_restore_lock);
 740         dev_priv->modeset_restore = MODESET_DONE;
 741         mutex_unlock(&dev_priv->modeset_restore_lock);
 742
 743         intel_opregion_notify_adapter(dev, PCI_D0);
 744
 745         drm_kms_helper_poll_enable(dev);
 746
 747         return 0;
 748 }
 749
 750 static int i915_drm_resume_early(struct drm_device *dev)
 751 {
 752         struct drm_i915_private *dev_priv = dev->dev_private;
 753         int ret = 0;
 754
 755         /*
 756          * We have a resume ordering issue with the snd-hda driver also
 757          * requiring our device to be power up. Due to the lack of a
 758          * parent/child relationship we currently solve this with an early
 759          * resume hook.
 760          *
 761          * FIXME: This should be solved with a special hdmi sink device or
 762          * similar so that power domains can be employed.
 763          */
 764         if (pci_enable_device(dev->pdev))
 765                 return -EIO;
 766
 767         pci_set_master(dev->pdev);
 768
 769         if (IS_VALLEYVIEW(dev_priv))
 770                 ret = vlv_resume_prepare(dev_priv, false);
 771         if (ret)
 772                 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
 773
 774         intel_uncore_early_sanitize(dev, true);
 775
 776         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 777                 hsw_disable_pc8(dev_priv);
 778
 779         intel_uncore_sanitize(dev);
 780         intel_power_domains_init_hw(dev_priv);
 781
 782         return ret;
 783 }
 784
 785 int i915_resume_legacy(struct drm_device *dev)
 786 {
 787         int ret;
 788
 789         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 790                 return 0;
 791
 792         ret = i915_drm_resume_early(dev);
 793         if (ret)
 794                 return ret;
 795
 796         return i915_drm_resume(dev);
 797 }
 798
 799 /**
 800  * i915_reset - reset chip after a hang
 801  * @dev: drm device to reset
 802  *
 803  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 804  * reset or otherwise an error code.
 805  *
 806  * Procedure is fairly simple:
 807  *   - reset the chip using the reset reg
 808  *   - re-init context state
 809  *   - re-init hardware status page
 810  *   - re-init ring buffer
 811  *   - re-init interrupt state
 812  *   - re-init display
 813  */
 814 int i915_reset(struct drm_device *dev)
 815 {
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         bool simulated;
 818         int ret;
 819
 820         if (!i915.reset)
 821                 return 0;
 822
 823         intel_reset_gt_powersave(dev);
 824
 825         mutex_lock(&dev->struct_mutex);
 826
 827         i915_gem_reset(dev);
 828
 829         simulated = dev_priv->gpu_error.stop_rings != 0;
 830
 831         ret = intel_gpu_reset(dev);
 832
 833         /* Also reset the gpu hangman. */
 834         if (simulated) {
 835                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 836                 dev_priv->gpu_error.stop_rings = 0;
 837                 if (ret == -ENODEV) {
 838                         DRM_INFO("Reset not implemented, but ignoring "
 839                                  "error for simulated gpu hangs\n");
 840                         ret = 0;
 841                 }
 842         }
 843
 844         if (i915_stop_ring_allow_warn(dev_priv))
 845                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 846
 847         if (ret) {
 848                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 849                 mutex_unlock(&dev->struct_mutex);
 850                 return ret;
 851         }
 852
 853         intel_overlay_reset(dev_priv);
 854
 855         /* Ok, now get things going again... */
 856
 857         /*
 858          * Everything depends on having the GTT running, so we need to start
 859          * there.  Fortunately we don't need to do this unless we reset the
 860          * chip at a PCI level.
 861          *
 862          * Next we need to restore the context, but we don't use those
 863          * yet either...
 864          *
 865          * Ring buffer needs to be re-initialized in the KMS case, or if X
 866          * was running at the time of the reset (i.e. we weren't VT
 867          * switched away).
 868          */
 869
 870         /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 871         dev_priv->gpu_error.reload_in_reset = true;
 872
 873         ret = i915_gem_init_hw(dev);
 874
 875         dev_priv->gpu_error.reload_in_reset = false;
 876
 877         mutex_unlock(&dev->struct_mutex);
 878         if (ret) {
 879                 DRM_ERROR("Failed hw init on reset %d\n", ret);
 880                 return ret;
 881         }
 882
 883         /*
 884          * rps/rc6 re-init is necessary to restore state lost after the
 885          * reset and the re-install of gt irqs. Skip for ironlake per
 886          * previous concerns that it doesn't respond well to some forms
 887          * of re-init after reset.
 888          */
 889         if (INTEL_INFO(dev)->gen > 5)
 890                 intel_enable_gt_powersave(dev);
 891
 892         return 0;
 893 }
 894
 895 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 896 {
 897         struct intel_device_info *intel_info =
 898                 (struct intel_device_info *) ent->driver_data;
 899
 900         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 901                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 902                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 903                 return -ENODEV;
 904         }
 905
 906         /* Only bind to function 0 of the device. Early generations
 907          * used function 1 as a placeholder for multi-head. This causes
 908          * us confusion instead, especially on the systems where both
 909          * functions have the same PCI-ID!
 910          */
 911         if (PCI_FUNC(pdev->devfn))
 912                 return -ENODEV;
 913
 914         driver.driver_features &= ~(DRIVER_USE_AGP);
 915
 916         return drm_get_pci_dev(pdev, ent, &driver);
 917 }
 918
 919 static void
 920 i915_pci_remove(struct pci_dev *pdev)
 921 {
 922         struct drm_device *dev = pci_get_drvdata(pdev);
 923
 924         drm_put_dev(dev);
 925 }
 926
 927 static int i915_pm_suspend(struct device *dev)
 928 {
 929         struct pci_dev *pdev = to_pci_dev(dev);
 930         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 931
 932         if (!drm_dev || !drm_dev->dev_private) {
 933                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 934                 return -ENODEV;
 935         }
 936
 937         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 938                 return 0;
 939
 940         return i915_drm_suspend(drm_dev);
 941 }
 942
 943 static int i915_pm_suspend_late(struct device *dev)
 944 {
 945         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 946
 947         /*
 948          * We have a suspedn ordering issue with the snd-hda driver also
 949          * requiring our device to be power up. Due to the lack of a
 950          * parent/child relationship we currently solve this with an late
 951          * suspend hook.
 952          *
 953          * FIXME: This should be solved with a special hdmi sink device or
 954          * similar so that power domains can be employed.
 955          */
 956         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 957                 return 0;
 958
 959         return i915_drm_suspend_late(drm_dev, false);
 960 }
 961
 962 static int i915_pm_poweroff_late(struct device *dev)
 963 {
 964         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 965
 966         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 967                 return 0;
 968
 969         return i915_drm_suspend_late(drm_dev, true);
 970 }
 971
 972 static int i915_pm_resume_early(struct device *dev)
 973 {
 974         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 975
 976         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 977                 return 0;
 978
 979         return i915_drm_resume_early(drm_dev);
 980 }
 981
 982 static int i915_pm_resume(struct device *dev)
 983 {
 984         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 985
 986         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 987                 return 0;
 988
 989         return i915_drm_resume(drm_dev);
 990 }
 991
 992 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
 993 {
 994         hsw_enable_pc8(dev_priv);
 995
 996         return 0;
 997 }
 998
 999 /*
1000  * Save all Gunit registers that may be lost after a D3 and a subsequent
1001  * S0i[R123] transition. The list of registers needing a save/restore is
1002  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1003  * registers in the following way:
1004  * - Driver: saved/restored by the driver
1005  * - Punit : saved/restored by the Punit firmware
1006  * - No, w/o marking: no need to save/restore, since the register is R/O or
1007  *                    used internally by the HW in a way that doesn't depend
1008  *                    keeping the content across a suspend/resume.
1009  * - Debug : used for debugging
1010  *
1011  * We save/restore all registers marked with 'Driver', with the following
1012  * exceptions:
1013  * - Registers out of use, including also registers marked with 'Debug'.
1014  *   These have no effect on the driver's operation, so we don't save/restore
1015  *   them to reduce the overhead.
1016  * - Registers that are fully setup by an initialization function called from
1017  *   the resume path. For example many clock gating and RPS/RC6 registers.
1018  * - Registers that provide the right functionality with their reset defaults.
1019  *
1020  * TODO: Except for registers that based on the above 3 criteria can be safely
1021  * ignored, we save/restore all others, practically treating the HW context as
1022  * a black-box for the driver. Further investigation is needed to reduce the
1023  * saved/restored registers even further, by following the same 3 criteria.
1024  */
1025 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1026 {
1027         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1028         int i;
1029
1030         /* GAM 0x4000-0x4770 */
1031         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1032         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1033         s->arb_mode             = I915_READ(ARB_MODE);
1034         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1035         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1036
1037         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1038                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1039
1040         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1041         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1042
1043         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1044         s->ecochk               = I915_READ(GAM_ECOCHK);
1045         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1046         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1047
1048         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1049
1050         /* MBC 0x9024-0x91D0, 0x8500 */
1051         s->g3dctl               = I915_READ(VLV_G3DCTL);
1052         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1053         s->mbctl                = I915_READ(GEN6_MBCTL);
1054
1055         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1056         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1057         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1058         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1059         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1060         s->rstctl               = I915_READ(GEN6_RSTCTL);
1061         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1062
1063         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1064         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1065         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1066         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1067         s->ecobus               = I915_READ(ECOBUS);
1068         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1069         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1070         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1071         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1072         s->rcedata              = I915_READ(VLV_RCEDATA);
1073         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1074
1075         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1076         s->gt_imr               = I915_READ(GTIMR);
1077         s->gt_ier               = I915_READ(GTIER);
1078         s->pm_imr               = I915_READ(GEN6_PMIMR);
1079         s->pm_ier               = I915_READ(GEN6_PMIER);
1080
1081         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1082                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1083
1084         /* GT SA CZ domain, 0x100000-0x138124 */
1085         s->tilectl              = I915_READ(TILECTL);
1086         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1087         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1088         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1089         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1090
1091         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1092         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1093         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1094         s->pcbr                 = I915_READ(VLV_PCBR);
1095         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1096
1097         /*
1098          * Not saving any of:
1099          * DFT,         0x9800-0x9EC0
1100          * SARB,        0xB000-0xB1FC
1101          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1102          * PCI CFG
1103          */
1104 }
1105
1106 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1107 {
1108         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1109         u32 val;
1110         int i;
1111
1112         /* GAM 0x4000-0x4770 */
1113         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1114         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1115         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1116         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1117         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1118
1119         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1120                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1121
1122         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1123         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1124
1125         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1126         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1127         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1128         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1129
1130         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1131
1132         /* MBC 0x9024-0x91D0, 0x8500 */
1133         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1134         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1135         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1136
1137         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1138         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1139         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1140         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1141         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1142         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1143         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1144
1145         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1146         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1147         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1148         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1149         I915_WRITE(ECOBUS,              s->ecobus);
1150         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1151         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1152         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1153         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1154         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1155         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1156
1157         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1158         I915_WRITE(GTIMR,               s->gt_imr);
1159         I915_WRITE(GTIER,               s->gt_ier);
1160         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1161         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1162
1163         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1164                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1165
1166         /* GT SA CZ domain, 0x100000-0x138124 */
1167         I915_WRITE(TILECTL,                     s->tilectl);
1168         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1169         /*
1170          * Preserve the GT allow wake and GFX force clock bit, they are not
1171          * be restored, as they are used to control the s0ix suspend/resume
1172          * sequence by the caller.
1173          */
1174         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1175         val &= VLV_GTLC_ALLOWWAKEREQ;
1176         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1177         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1178
1179         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1180         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1181         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1182         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1183
1184         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1185
1186         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1187         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1188         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1189         I915_WRITE(VLV_PCBR,                    s->pcbr);
1190         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1191 }
1192
1193 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1194 {
1195         u32 val;
1196         int err;
1197
1198 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1199
1200         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1201         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1202         if (force_on)
1203                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1204         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1205
1206         if (!force_on)
1207                 return 0;
1208
1209         err = wait_for(COND, 20);
1210         if (err)
1211                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1212                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1213
1214         return err;
1215 #undef COND
1216 }
1217
1218 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1219 {
1220         u32 val;
1221         int err = 0;
1222
1223         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1224         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1225         if (allow)
1226                 val |= VLV_GTLC_ALLOWWAKEREQ;
1227         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1228         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1229
1230 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1231               allow)
1232         err = wait_for(COND, 1);
1233         if (err)
1234                 DRM_ERROR("timeout disabling GT waking\n");
1235         return err;
1236 #undef COND
1237 }
1238
1239 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1240                                  bool wait_for_on)
1241 {
1242         u32 mask;
1243         u32 val;
1244         int err;
1245
1246         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1247         val = wait_for_on ? mask : 0;
1248 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1249         if (COND)
1250                 return 0;
1251
1252         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1253                         wait_for_on ? "on" : "off",
1254                         I915_READ(VLV_GTLC_PW_STATUS));
1255
1256         /*
1257          * RC6 transitioning can be delayed up to 2 msec (see
1258          * valleyview_enable_rps), use 3 msec for safety.
1259          */
1260         err = wait_for(COND, 3);
1261         if (err)
1262                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1263                           wait_for_on ? "on" : "off");
1264
1265         return err;
1266 #undef COND
1267 }
1268
1269 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1270 {
1271         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1272                 return;
1273
1274         DRM_ERROR("GT register access while GT waking disabled\n");
1275         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1276 }
1277
1278 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1279 {
1280         u32 mask;
1281         int err;
1282
1283         /*
1284          * Bspec defines the following GT well on flags as debug only, so
1285          * don't treat them as hard failures.
1286          */
1287         (void)vlv_wait_for_gt_wells(dev_priv, false);
1288
1289         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1290         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1291
1292         vlv_check_no_gt_access(dev_priv);
1293
1294         err = vlv_force_gfx_clock(dev_priv, true);
1295         if (err)
1296                 goto err1;
1297
1298         err = vlv_allow_gt_wake(dev_priv, false);
1299         if (err)
1300                 goto err2;
1301
1302         if (!IS_CHERRYVIEW(dev_priv->dev))
1303                 vlv_save_gunit_s0ix_state(dev_priv);
1304
1305         err = vlv_force_gfx_clock(dev_priv, false);
1306         if (err)
1307                 goto err2;
1308
1309         return 0;
1310
1311 err2:
1312         /* For safety always re-enable waking and disable gfx clock forcing */
1313         vlv_allow_gt_wake(dev_priv, true);
1314 err1:
1315         vlv_force_gfx_clock(dev_priv, false);
1316
1317         return err;
1318 }
1319
1320 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1321                                 bool rpm_resume)
1322 {
1323         struct drm_device *dev = dev_priv->dev;
1324         int err;
1325         int ret;
1326
1327         /*
1328          * If any of the steps fail just try to continue, that's the best we
1329          * can do at this point. Return the first error code (which will also
1330          * leave RPM permanently disabled).
1331          */
1332         ret = vlv_force_gfx_clock(dev_priv, true);
1333
1334         if (!IS_CHERRYVIEW(dev_priv->dev))
1335                 vlv_restore_gunit_s0ix_state(dev_priv);
1336
1337         err = vlv_allow_gt_wake(dev_priv, true);
1338         if (!ret)
1339                 ret = err;
1340
1341         err = vlv_force_gfx_clock(dev_priv, false);
1342         if (!ret)
1343                 ret = err;
1344
1345         vlv_check_no_gt_access(dev_priv);
1346
1347         if (rpm_resume) {
1348                 intel_init_clock_gating(dev);
1349                 i915_gem_restore_fences(dev);
1350         }
1351
1352         return ret;
1353 }
1354
1355 static int intel_runtime_suspend(struct device *device)
1356 {
1357         struct pci_dev *pdev = to_pci_dev(device);
1358         struct drm_device *dev = pci_get_drvdata(pdev);
1359         struct drm_i915_private *dev_priv = dev->dev_private;
1360         int ret;
1361
1362         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1363                 return -ENODEV;
1364
1365         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1366                 return -ENODEV;
1367
1368         DRM_DEBUG_KMS("Suspending device\n");
1369
1370         /*
1371          * We could deadlock here in case another thread holding struct_mutex
1372          * calls RPM suspend concurrently, since the RPM suspend will wait
1373          * first for this RPM suspend to finish. In this case the concurrent
1374          * RPM resume will be followed by its RPM suspend counterpart. Still
1375          * for consistency return -EAGAIN, which will reschedule this suspend.
1376          */
1377         if (!mutex_trylock(&dev->struct_mutex)) {
1378                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1379                 /*
1380                  * Bump the expiration timestamp, otherwise the suspend won't
1381                  * be rescheduled.
1382                  */
1383                 pm_runtime_mark_last_busy(device);
1384
1385                 return -EAGAIN;
1386         }
1387         /*
1388          * We are safe here against re-faults, since the fault handler takes
1389          * an RPM reference.
1390          */
1391         i915_gem_release_all_mmaps(dev_priv);
1392         mutex_unlock(&dev->struct_mutex);
1393
1394         intel_suspend_gt_powersave(dev);
1395         intel_runtime_pm_disable_interrupts(dev_priv);
1396
1397         ret = intel_suspend_complete(dev_priv);
1398         if (ret) {
1399                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1400                 intel_runtime_pm_enable_interrupts(dev_priv);
1401
1402                 return ret;
1403         }
1404
1405         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1406         intel_uncore_forcewake_reset(dev, false);
1407         dev_priv->pm.suspended = true;
1408
1409         /*
1410          * FIXME: We really should find a document that references the arguments
1411          * used below!
1412          */
1413         if (IS_HASWELL(dev)) {
1414                 /*
1415                  * current versions of firmware which depend on this opregion
1416                  * notification have repurposed the D1 definition to mean
1417                  * "runtime suspended" vs. what you would normally expect (D3)
1418                  * to distinguish it from notifications that might be sent via
1419                  * the suspend path.
1420                  */
1421                 intel_opregion_notify_adapter(dev, PCI_D1);
1422         } else {
1423                 /*
1424                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1425                  * being detected, and the call we do at intel_runtime_resume()
1426                  * won't be able to restore them. Since PCI_D3hot matches the
1427                  * actual specification and appears to be working, use it. Let's
1428                  * assume the other non-Haswell platforms will stay the same as
1429                  * Broadwell.
1430                  */
1431                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1432         }
1433
1434         assert_forcewakes_inactive(dev_priv);
1435
1436         DRM_DEBUG_KMS("Device suspended\n");
1437         return 0;
1438 }
1439
1440 static int intel_runtime_resume(struct device *device)
1441 {
1442         struct pci_dev *pdev = to_pci_dev(device);
1443         struct drm_device *dev = pci_get_drvdata(pdev);
1444         struct drm_i915_private *dev_priv = dev->dev_private;
1445         int ret = 0;
1446
1447         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1448                 return -ENODEV;
1449
1450         DRM_DEBUG_KMS("Resuming device\n");
1451
1452         intel_opregion_notify_adapter(dev, PCI_D0);
1453         dev_priv->pm.suspended = false;
1454
1455         if (IS_GEN6(dev_priv))
1456                 intel_init_pch_refclk(dev);
1457         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1458                 hsw_disable_pc8(dev_priv);
1459         else if (IS_VALLEYVIEW(dev_priv))
1460                 ret = vlv_resume_prepare(dev_priv, true);
1461
1462         /*
1463          * No point of rolling back things in case of an error, as the best
1464          * we can do is to hope that things will still work (and disable RPM).
1465          */
1466         i915_gem_init_swizzling(dev);
1467         gen6_update_ring_freq(dev);
1468
1469         intel_runtime_pm_enable_interrupts(dev_priv);
1470         intel_enable_gt_powersave(dev);
1471
1472         if (ret)
1473                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1474         else
1475                 DRM_DEBUG_KMS("Device resumed\n");
1476
1477         return ret;
1478 }
1479
1480 /*
1481  * This function implements common functionality of runtime and system
1482  * suspend sequence.
1483  */
1484 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1485 {
1486         struct drm_device *dev = dev_priv->dev;
1487         int ret;
1488
1489         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1490                 ret = hsw_suspend_complete(dev_priv);
1491         else if (IS_VALLEYVIEW(dev))
1492                 ret = vlv_suspend_complete(dev_priv);
1493         else
1494                 ret = 0;
1495
1496         return ret;
1497 }
1498
1499 static const struct dev_pm_ops i915_pm_ops = {
1500         /*
1501          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1502          * PMSG_RESUME]
1503          */
1504         .suspend = i915_pm_suspend,
1505         .suspend_late = i915_pm_suspend_late,
1506         .resume_early = i915_pm_resume_early,
1507         .resume = i915_pm_resume,
1508
1509         /*
1510          * S4 event handlers
1511          * @freeze, @freeze_late    : called (1) before creating the
1512          *                            hibernation image [PMSG_FREEZE] and
1513          *                            (2) after rebooting, before restoring
1514          *                            the image [PMSG_QUIESCE]
1515          * @thaw, @thaw_early       : called (1) after creating the hibernation
1516          *                            image, before writing it [PMSG_THAW]
1517          *                            and (2) after failing to create or
1518          *                            restore the image [PMSG_RECOVER]
1519          * @poweroff, @poweroff_late: called after writing the hibernation
1520          *                            image, before rebooting [PMSG_HIBERNATE]
1521          * @restore, @restore_early : called after rebooting and restoring the
1522          *                            hibernation image [PMSG_RESTORE]
1523          */
1524         .freeze = i915_pm_suspend,
1525         .freeze_late = i915_pm_suspend_late,
1526         .thaw_early = i915_pm_resume_early,
1527         .thaw = i915_pm_resume,
1528         .poweroff = i915_pm_suspend,
1529         .poweroff_late = i915_pm_poweroff_late,
1530         .restore_early = i915_pm_resume_early,
1531         .restore = i915_pm_resume,
1532
1533         /* S0ix (via runtime suspend) event handlers */
1534         .runtime_suspend = intel_runtime_suspend,
1535         .runtime_resume = intel_runtime_resume,
1536 };
1537
1538 static const struct vm_operations_struct i915_gem_vm_ops = {
1539         .fault = i915_gem_fault,
1540         .open = drm_gem_vm_open,
1541         .close = drm_gem_vm_close,
1542 };
1543
1544 static const struct file_operations i915_driver_fops = {
1545         .owner = THIS_MODULE,
1546         .open = drm_open,
1547         .release = drm_release,
1548         .unlocked_ioctl = drm_ioctl,
1549         .mmap = drm_gem_mmap,
1550         .poll = drm_poll,
1551         .read = drm_read,
1552 #ifdef CONFIG_COMPAT
1553         .compat_ioctl = i915_compat_ioctl,
1554 #endif
1555         .llseek = noop_llseek,
1556 };
1557
1558 static struct drm_driver driver = {
1559         /* Don't use MTRRs here; the Xserver or userspace app should
1560          * deal with them for Intel hardware.
1561          */
1562         .driver_features =
1563             DRIVER_USE_AGP |
1564             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1565             DRIVER_RENDER,
1566         .load = i915_driver_load,
1567         .unload = i915_driver_unload,
1568         .open = i915_driver_open,
1569         .lastclose = i915_driver_lastclose,
1570         .preclose = i915_driver_preclose,
1571         .postclose = i915_driver_postclose,
1572         .set_busid = drm_pci_set_busid,
1573
1574         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1575         .suspend = i915_suspend_legacy,
1576         .resume = i915_resume_legacy,
1577
1578         .device_is_agp = i915_driver_device_is_agp,
1579 #if defined(CONFIG_DEBUG_FS)
1580         .debugfs_init = i915_debugfs_init,
1581         .debugfs_cleanup = i915_debugfs_cleanup,
1582 #endif
1583         .gem_free_object = i915_gem_free_object,
1584         .gem_vm_ops = &i915_gem_vm_ops,
1585
1586         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1587         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1588         .gem_prime_export = i915_gem_prime_export,
1589         .gem_prime_import = i915_gem_prime_import,
1590
1591         .dumb_create = i915_gem_dumb_create,
1592         .dumb_map_offset = i915_gem_mmap_gtt,
1593         .dumb_destroy = drm_gem_dumb_destroy,
1594         .ioctls = i915_ioctls,
1595         .fops = &i915_driver_fops,
1596         .name = DRIVER_NAME,
1597         .desc = DRIVER_DESC,
1598         .date = DRIVER_DATE,
1599         .major = DRIVER_MAJOR,
1600         .minor = DRIVER_MINOR,
1601         .patchlevel = DRIVER_PATCHLEVEL,
1602 };
1603
1604 static struct pci_driver i915_pci_driver = {
1605         .name = DRIVER_NAME,
1606         .id_table = pciidlist,
1607         .probe = i915_pci_probe,
1608         .remove = i915_pci_remove,
1609         .driver.pm = &i915_pm_ops,
1610 };
1611
1612 static int __init i915_init(void)
1613 {
1614         driver.num_ioctls = i915_max_ioctl;
1615
1616         /*
1617          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1618          * explicitly disabled with the module pararmeter.
1619          *
1620          * Otherwise, just follow the parameter (defaulting to off).
1621          *
1622          * Allow optional vga_text_mode_force boot option to override
1623          * the default behavior.
1624          */
1625 #if defined(CONFIG_DRM_I915_KMS)
1626         if (i915.modeset != 0)
1627                 driver.driver_features |= DRIVER_MODESET;
1628 #endif
1629         if (i915.modeset == 1)
1630                 driver.driver_features |= DRIVER_MODESET;
1631
1632 #ifdef CONFIG_VGA_CONSOLE
1633         if (vgacon_text_force() && i915.modeset == -1)
1634                 driver.driver_features &= ~DRIVER_MODESET;
1635 #endif
1636
1637         if (!(driver.driver_features & DRIVER_MODESET)) {
1638                 driver.get_vblank_timestamp = NULL;
1639                 /* Silently fail loading to not upset userspace. */
1640                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1641                 return 0;
1642         }
1643
1644         /*
1645          * FIXME: Note that we're lying to the DRM core here so that we can get access
1646          * to the atomic ioctl and the atomic properties.  Only plane operations on
1647          * a single CRTC will actually work.
1648          */
1649         if (i915.nuclear_pageflip)
1650                 driver.driver_features |= DRIVER_ATOMIC;
1651
1652         return drm_pci_init(&driver, &i915_pci_driver);
1653 }
1654
1655 static void __exit i915_exit(void)
1656 {
1657         if (!(driver.driver_features & DRIVER_MODESET))
1658                 return; /* Never loaded a driver. */
1659
1660         drm_pci_exit(&driver, &i915_pci_driver);
1661 }
1662
1663 module_init(i915_init);
1664 module_exit(i915_exit);
1665
1666 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1667 MODULE_AUTHOR("Intel Corporation");
1668
1669 MODULE_DESCRIPTION(DRIVER_DESC);
1670 MODULE_LICENSE("GPL and additional rights");