drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fpga_dbg = 1,
 307         .has_fbc = 1,
 308         GEN_DEFAULT_PIPEOFFSETS,
 309         IVB_CURSOR_OFFSETS,
 310 };
 311
 312 static const struct intel_device_info intel_broadwell_m_info = {
 313         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 314         .need_gfx_hws = 1, .has_hotplug = 1,
 315         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 316         .has_llc = 1,
 317         .has_ddi = 1,
 318         .has_fpga_dbg = 1,
 319         .has_fbc = 1,
 320         GEN_DEFAULT_PIPEOFFSETS,
 321         IVB_CURSOR_OFFSETS,
 322 };
 323
 324 static const struct intel_device_info intel_broadwell_gt3d_info = {
 325         .gen = 8, .num_pipes = 3,
 326         .need_gfx_hws = 1, .has_hotplug = 1,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328         .has_llc = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333         IVB_CURSOR_OFFSETS,
 334 };
 335
 336 static const struct intel_device_info intel_broadwell_gt3m_info = {
 337         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 338         .need_gfx_hws = 1, .has_hotplug = 1,
 339         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 340         .has_llc = 1,
 341         .has_ddi = 1,
 342         .has_fpga_dbg = 1,
 343         .has_fbc = 1,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346 };
 347
 348 static const struct intel_device_info intel_cherryview_info = {
 349         .is_preliminary = 1,
 350         .gen = 8, .num_pipes = 3,
 351         .need_gfx_hws = 1, .has_hotplug = 1,
 352         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 353         .is_valleyview = 1,
 354         .display_mmio_offset = VLV_DISPLAY_BASE,
 355         GEN_CHV_PIPEOFFSETS,
 356         CURSOR_OFFSETS,
 357 };
 358
 359 /*
 360  * Make sure any device matches here are from most specific to most
 361  * general.  For example, since the Quanta match is based on the subsystem
 362  * and subvendor IDs, we need it to come before the more general IVB
 363  * PCI ID matches, otherwise we'll use the wrong info struct above.
 364  */
 365 #define INTEL_PCI_IDS \
 366         INTEL_I830_IDS(&intel_i830_info),       \
 367         INTEL_I845G_IDS(&intel_845g_info),      \
 368         INTEL_I85X_IDS(&intel_i85x_info),       \
 369         INTEL_I865G_IDS(&intel_i865g_info),     \
 370         INTEL_I915G_IDS(&intel_i915g_info),     \
 371         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 372         INTEL_I945G_IDS(&intel_i945g_info),     \
 373         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 374         INTEL_I965G_IDS(&intel_i965g_info),     \
 375         INTEL_G33_IDS(&intel_g33_info),         \
 376         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 377         INTEL_GM45_IDS(&intel_gm45_info),       \
 378         INTEL_G45_IDS(&intel_g45_info),         \
 379         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 380         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 381         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 382         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 383         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 384         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 385         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 386         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 387         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 388         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 389         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 390         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 391         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 392         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 393         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 394         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 395         INTEL_CHV_IDS(&intel_cherryview_info)
 396
 397 static const struct pci_device_id pciidlist[] = {               /* aka */
 398         INTEL_PCI_IDS,
 399         {0, 0, 0}
 400 };
 401
 402 #if defined(CONFIG_DRM_I915_KMS)
 403 MODULE_DEVICE_TABLE(pci, pciidlist);
 404 #endif
 405
 406 void intel_detect_pch(struct drm_device *dev)
 407 {
 408         struct drm_i915_private *dev_priv = dev->dev_private;
 409         struct pci_dev *pch = NULL;
 410
 411         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 412          * (which really amounts to a PCH but no South Display).
 413          */
 414         if (INTEL_INFO(dev)->num_pipes == 0) {
 415                 dev_priv->pch_type = PCH_NOP;
 416                 return;
 417         }
 418
 419         /*
 420          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 421          * make graphics device passthrough work easy for VMM, that only
 422          * need to expose ISA bridge to let driver know the real hardware
 423          * underneath. This is a requirement from virtualization team.
 424          *
 425          * In some virtualized environments (e.g. XEN), there is irrelevant
 426          * ISA bridge in the system. To work reliably, we should scan trhough
 427          * all the ISA bridge devices and check for the first match, instead
 428          * of only checking the first one.
 429          */
 430         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 431                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 432                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 433                         dev_priv->pch_id = id;
 434
 435                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 436                                 dev_priv->pch_type = PCH_IBX;
 437                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 438                                 WARN_ON(!IS_GEN5(dev));
 439                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 440                                 dev_priv->pch_type = PCH_CPT;
 441                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 442                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 443                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 444                                 /* PantherPoint is CPT compatible */
 445                                 dev_priv->pch_type = PCH_CPT;
 446                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 447                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 448                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 449                                 dev_priv->pch_type = PCH_LPT;
 450                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 451                                 WARN_ON(!IS_HASWELL(dev));
 452                                 WARN_ON(IS_ULT(dev));
 453                         } else if (IS_BROADWELL(dev)) {
 454                                 dev_priv->pch_type = PCH_LPT;
 455                                 dev_priv->pch_id =
 456                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 457                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 458                                               "LynxPoint LP PCH\n");
 459                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 460                                 dev_priv->pch_type = PCH_LPT;
 461                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 462                                 WARN_ON(!IS_HASWELL(dev));
 463                                 WARN_ON(!IS_ULT(dev));
 464                         } else
 465                                 continue;
 466
 467                         break;
 468                 }
 469         }
 470         if (!pch)
 471                 DRM_DEBUG_KMS("No PCH found.\n");
 472
 473         pci_dev_put(pch);
 474 }
 475
 476 bool i915_semaphore_is_enabled(struct drm_device *dev)
 477 {
 478         if (INTEL_INFO(dev)->gen < 6)
 479                 return false;
 480
 481         if (i915.semaphores >= 0)
 482                 return i915.semaphores;
 483
 484         /* Until we get further testing... */
 485         if (IS_GEN8(dev))
 486                 return false;
 487
 488 #ifdef CONFIG_INTEL_IOMMU
 489         /* Enable semaphores on SNB when IO remapping is off */
 490         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 491                 return false;
 492 #endif
 493
 494         return true;
 495 }
 496
 497 static int i915_drm_freeze(struct drm_device *dev)
 498 {
 499         struct drm_i915_private *dev_priv = dev->dev_private;
 500         struct drm_crtc *crtc;
 501         pci_power_t opregion_target_state;
 502
 503         /* ignore lid events during suspend */
 504         mutex_lock(&dev_priv->modeset_restore_lock);
 505         dev_priv->modeset_restore = MODESET_SUSPENDED;
 506         mutex_unlock(&dev_priv->modeset_restore_lock);
 507
 508         /* We do a lot of poking in a lot of registers, make sure they work
 509          * properly. */
 510         intel_display_set_init_power(dev_priv, true);
 511
 512         drm_kms_helper_poll_disable(dev);
 513
 514         pci_save_state(dev->pdev);
 515
 516         /* If KMS is active, we do the leavevt stuff here */
 517         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 518                 int error;
 519
 520                 error = i915_gem_suspend(dev);
 521                 if (error) {
 522                         dev_err(&dev->pdev->dev,
 523                                 "GEM idle failed, resume might fail\n");
 524                         return error;
 525                 }
 526
 527                 /*
 528                  * Disable CRTCs directly since we want to preserve sw state
 529                  * for _thaw. Also, power gate the CRTC power wells.
 530                  */
 531                 drm_modeset_lock_all(dev);
 532                 for_each_crtc(dev, crtc)
 533                         intel_crtc_control(crtc, false);
 534                 drm_modeset_unlock_all(dev);
 535
 536                 intel_dp_mst_suspend(dev);
 537
 538                 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
 539
 540                 intel_runtime_pm_disable_interrupts(dev);
 541
 542                 intel_suspend_gt_powersave(dev);
 543
 544                 intel_modeset_suspend_hw(dev);
 545         }
 546
 547         i915_gem_suspend_gtt_mappings(dev);
 548
 549         i915_save_state(dev);
 550
 551         opregion_target_state = PCI_D3cold;
 552 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 553         if (acpi_target_system_state() < ACPI_STATE_S3)
 554                 opregion_target_state = PCI_D1;
 555 #endif
 556         intel_opregion_notify_adapter(dev, opregion_target_state);
 557
 558         intel_uncore_forcewake_reset(dev, false);
 559         intel_opregion_fini(dev);
 560
 561         console_lock();
 562         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 563         console_unlock();
 564
 565         dev_priv->suspend_count++;
 566
 567         intel_display_set_init_power(dev_priv, false);
 568
 569         return 0;
 570 }
 571
 572 int i915_suspend(struct drm_device *dev, pm_message_t state)
 573 {
 574         int error;
 575
 576         if (!dev || !dev->dev_private) {
 577                 DRM_ERROR("dev: %p\n", dev);
 578                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 579                 return -ENODEV;
 580         }
 581
 582         if (state.event == PM_EVENT_PRETHAW)
 583                 return 0;
 584
 585
 586         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 587                 return 0;
 588
 589         error = i915_drm_freeze(dev);
 590         if (error)
 591                 return error;
 592
 593         if (state.event == PM_EVENT_SUSPEND) {
 594                 /* Shut down the device */
 595                 pci_disable_device(dev->pdev);
 596                 pci_set_power_state(dev->pdev, PCI_D3hot);
 597         }
 598
 599         return 0;
 600 }
 601
 602 void intel_console_resume(struct work_struct *work)
 603 {
 604         struct drm_i915_private *dev_priv =
 605                 container_of(work, struct drm_i915_private,
 606                              console_resume_work);
 607         struct drm_device *dev = dev_priv->dev;
 608
 609         console_lock();
 610         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 611         console_unlock();
 612 }
 613
 614 static int i915_drm_thaw_early(struct drm_device *dev)
 615 {
 616         struct drm_i915_private *dev_priv = dev->dev_private;
 617
 618         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 619                 hsw_disable_pc8(dev_priv);
 620
 621         intel_uncore_early_sanitize(dev, true);
 622         intel_uncore_sanitize(dev);
 623         intel_power_domains_init_hw(dev_priv);
 624
 625         return 0;
 626 }
 627
 628 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 629 {
 630         struct drm_i915_private *dev_priv = dev->dev_private;
 631
 632         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 633             restore_gtt_mappings) {
 634                 mutex_lock(&dev->struct_mutex);
 635                 i915_gem_restore_gtt_mappings(dev);
 636                 mutex_unlock(&dev->struct_mutex);
 637         }
 638
 639         i915_restore_state(dev);
 640         intel_opregion_setup(dev);
 641
 642         /* KMS EnterVT equivalent */
 643         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 644                 intel_init_pch_refclk(dev);
 645                 drm_mode_config_reset(dev);
 646
 647                 mutex_lock(&dev->struct_mutex);
 648                 if (i915_gem_init_hw(dev)) {
 649                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 650                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 651                 }
 652                 mutex_unlock(&dev->struct_mutex);
 653
 654                 intel_runtime_pm_restore_interrupts(dev);
 655
 656                 intel_modeset_init_hw(dev);
 657
 658                 {
 659                         unsigned long irqflags;
 660                         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 661                         if (dev_priv->display.hpd_irq_setup)
 662                                 dev_priv->display.hpd_irq_setup(dev);
 663                         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 664                 }
 665
 666                 intel_dp_mst_resume(dev);
 667                 drm_modeset_lock_all(dev);
 668                 intel_modeset_setup_hw_state(dev, true);
 669                 drm_modeset_unlock_all(dev);
 670
 671                 /*
 672                  * ... but also need to make sure that hotplug processing
 673                  * doesn't cause havoc. Like in the driver load code we don't
 674                  * bother with the tiny race here where we might loose hotplug
 675                  * notifications.
 676                  * */
 677                 intel_hpd_init(dev);
 678                 /* Config may have changed between suspend and resume */
 679                 drm_helper_hpd_irq_event(dev);
 680         }
 681
 682         intel_opregion_init(dev);
 683
 684         /*
 685          * The console lock can be pretty contented on resume due
 686          * to all the printk activity.  Try to keep it out of the hot
 687          * path of resume if possible.
 688          */
 689         if (console_trylock()) {
 690                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 691                 console_unlock();
 692         } else {
 693                 schedule_work(&dev_priv->console_resume_work);
 694         }
 695
 696         mutex_lock(&dev_priv->modeset_restore_lock);
 697         dev_priv->modeset_restore = MODESET_DONE;
 698         mutex_unlock(&dev_priv->modeset_restore_lock);
 699
 700         intel_opregion_notify_adapter(dev, PCI_D0);
 701
 702         return 0;
 703 }
 704
 705 static int i915_drm_thaw(struct drm_device *dev)
 706 {
 707         if (drm_core_check_feature(dev, DRIVER_MODESET))
 708                 i915_check_and_clear_faults(dev);
 709
 710         return __i915_drm_thaw(dev, true);
 711 }
 712
 713 static int i915_resume_early(struct drm_device *dev)
 714 {
 715         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 716                 return 0;
 717
 718         /*
 719          * We have a resume ordering issue with the snd-hda driver also
 720          * requiring our device to be power up. Due to the lack of a
 721          * parent/child relationship we currently solve this with an early
 722          * resume hook.
 723          *
 724          * FIXME: This should be solved with a special hdmi sink device or
 725          * similar so that power domains can be employed.
 726          */
 727         if (pci_enable_device(dev->pdev))
 728                 return -EIO;
 729
 730         pci_set_master(dev->pdev);
 731
 732         return i915_drm_thaw_early(dev);
 733 }
 734
 735 int i915_resume(struct drm_device *dev)
 736 {
 737         struct drm_i915_private *dev_priv = dev->dev_private;
 738         int ret;
 739
 740         /*
 741          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 742          * earlier) need to restore the GTT mappings since the BIOS might clear
 743          * all our scratch PTEs.
 744          */
 745         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 746         if (ret)
 747                 return ret;
 748
 749         drm_kms_helper_poll_enable(dev);
 750         return 0;
 751 }
 752
 753 static int i915_resume_legacy(struct drm_device *dev)
 754 {
 755         i915_resume_early(dev);
 756         i915_resume(dev);
 757
 758         return 0;
 759 }
 760
 761 /**
 762  * i915_reset - reset chip after a hang
 763  * @dev: drm device to reset
 764  *
 765  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 766  * reset or otherwise an error code.
 767  *
 768  * Procedure is fairly simple:
 769  *   - reset the chip using the reset reg
 770  *   - re-init context state
 771  *   - re-init hardware status page
 772  *   - re-init ring buffer
 773  *   - re-init interrupt state
 774  *   - re-init display
 775  */
 776 int i915_reset(struct drm_device *dev)
 777 {
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         bool simulated;
 780         int ret;
 781
 782         if (!i915.reset)
 783                 return 0;
 784
 785         mutex_lock(&dev->struct_mutex);
 786
 787         i915_gem_reset(dev);
 788
 789         simulated = dev_priv->gpu_error.stop_rings != 0;
 790
 791         ret = intel_gpu_reset(dev);
 792
 793         /* Also reset the gpu hangman. */
 794         if (simulated) {
 795                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 796                 dev_priv->gpu_error.stop_rings = 0;
 797                 if (ret == -ENODEV) {
 798                         DRM_INFO("Reset not implemented, but ignoring "
 799                                  "error for simulated gpu hangs\n");
 800                         ret = 0;
 801                 }
 802         }
 803
 804         if (ret) {
 805                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 806                 mutex_unlock(&dev->struct_mutex);
 807                 return ret;
 808         }
 809
 810         /* Ok, now get things going again... */
 811
 812         /*
 813          * Everything depends on having the GTT running, so we need to start
 814          * there.  Fortunately we don't need to do this unless we reset the
 815          * chip at a PCI level.
 816          *
 817          * Next we need to restore the context, but we don't use those
 818          * yet either...
 819          *
 820          * Ring buffer needs to be re-initialized in the KMS case, or if X
 821          * was running at the time of the reset (i.e. we weren't VT
 822          * switched away).
 823          */
 824         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 825                         !dev_priv->ums.mm_suspended) {
 826                 dev_priv->ums.mm_suspended = 0;
 827
 828                 ret = i915_gem_init_hw(dev);
 829                 mutex_unlock(&dev->struct_mutex);
 830                 if (ret) {
 831                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 832                         return ret;
 833                 }
 834
 835                 /*
 836                  * FIXME: This races pretty badly against concurrent holders of
 837                  * ring interrupts. This is possible since we've started to drop
 838                  * dev->struct_mutex in select places when waiting for the gpu.
 839                  */
 840
 841                 /*
 842                  * rps/rc6 re-init is necessary to restore state lost after the
 843                  * reset and the re-install of gt irqs. Skip for ironlake per
 844                  * previous concerns that it doesn't respond well to some forms
 845                  * of re-init after reset.
 846                  */
 847                 if (INTEL_INFO(dev)->gen > 5)
 848                         intel_reset_gt_powersave(dev);
 849
 850                 intel_hpd_init(dev);
 851         } else {
 852                 mutex_unlock(&dev->struct_mutex);
 853         }
 854
 855         return 0;
 856 }
 857
 858 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 859 {
 860         struct intel_device_info *intel_info =
 861                 (struct intel_device_info *) ent->driver_data;
 862
 863         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 864                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 865                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 866                 return -ENODEV;
 867         }
 868
 869         /* Only bind to function 0 of the device. Early generations
 870          * used function 1 as a placeholder for multi-head. This causes
 871          * us confusion instead, especially on the systems where both
 872          * functions have the same PCI-ID!
 873          */
 874         if (PCI_FUNC(pdev->devfn))
 875                 return -ENODEV;
 876
 877         driver.driver_features &= ~(DRIVER_USE_AGP);
 878
 879         return drm_get_pci_dev(pdev, ent, &driver);
 880 }
 881
 882 static void
 883 i915_pci_remove(struct pci_dev *pdev)
 884 {
 885         struct drm_device *dev = pci_get_drvdata(pdev);
 886
 887         drm_put_dev(dev);
 888 }
 889
 890 static int i915_pm_suspend(struct device *dev)
 891 {
 892         struct pci_dev *pdev = to_pci_dev(dev);
 893         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 894
 895         if (!drm_dev || !drm_dev->dev_private) {
 896                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 897                 return -ENODEV;
 898         }
 899
 900         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 901                 return 0;
 902
 903         return i915_drm_freeze(drm_dev);
 904 }
 905
 906 static int i915_pm_suspend_late(struct device *dev)
 907 {
 908         struct pci_dev *pdev = to_pci_dev(dev);
 909         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 910         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 911
 912         /*
 913          * We have a suspedn ordering issue with the snd-hda driver also
 914          * requiring our device to be power up. Due to the lack of a
 915          * parent/child relationship we currently solve this with an late
 916          * suspend hook.
 917          *
 918          * FIXME: This should be solved with a special hdmi sink device or
 919          * similar so that power domains can be employed.
 920          */
 921         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 922                 return 0;
 923
 924         if (IS_HASWELL(drm_dev) || IS_BROADWELL(drm_dev))
 925                 hsw_enable_pc8(dev_priv);
 926
 927         pci_disable_device(pdev);
 928         pci_set_power_state(pdev, PCI_D3hot);
 929
 930         return 0;
 931 }
 932
 933 static int i915_pm_resume_early(struct device *dev)
 934 {
 935         struct pci_dev *pdev = to_pci_dev(dev);
 936         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 937
 938         return i915_resume_early(drm_dev);
 939 }
 940
 941 static int i915_pm_resume(struct device *dev)
 942 {
 943         struct pci_dev *pdev = to_pci_dev(dev);
 944         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 945
 946         return i915_resume(drm_dev);
 947 }
 948
 949 static int i915_pm_freeze(struct device *dev)
 950 {
 951         struct pci_dev *pdev = to_pci_dev(dev);
 952         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 953
 954         if (!drm_dev || !drm_dev->dev_private) {
 955                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 956                 return -ENODEV;
 957         }
 958
 959         return i915_drm_freeze(drm_dev);
 960 }
 961
 962 static int i915_pm_thaw_early(struct device *dev)
 963 {
 964         struct pci_dev *pdev = to_pci_dev(dev);
 965         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 966
 967         return i915_drm_thaw_early(drm_dev);
 968 }
 969
 970 static int i915_pm_thaw(struct device *dev)
 971 {
 972         struct pci_dev *pdev = to_pci_dev(dev);
 973         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 974
 975         return i915_drm_thaw(drm_dev);
 976 }
 977
 978 static int i915_pm_poweroff(struct device *dev)
 979 {
 980         struct pci_dev *pdev = to_pci_dev(dev);
 981         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 982
 983         return i915_drm_freeze(drm_dev);
 984 }
 985
 986 static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
 987 {
 988         hsw_enable_pc8(dev_priv);
 989
 990         return 0;
 991 }
 992
 993 static int snb_runtime_resume(struct drm_i915_private *dev_priv)
 994 {
 995         struct drm_device *dev = dev_priv->dev;
 996
 997         intel_init_pch_refclk(dev);
 998
 999         return 0;
1000 }
1001
1002 static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
1003 {
1004         hsw_disable_pc8(dev_priv);
1005
1006         return 0;
1007 }
1008
1009 /*
1010  * Save all Gunit registers that may be lost after a D3 and a subsequent
1011  * S0i[R123] transition. The list of registers needing a save/restore is
1012  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1013  * registers in the following way:
1014  * - Driver: saved/restored by the driver
1015  * - Punit : saved/restored by the Punit firmware
1016  * - No, w/o marking: no need to save/restore, since the register is R/O or
1017  *                    used internally by the HW in a way that doesn't depend
1018  *                    keeping the content across a suspend/resume.
1019  * - Debug : used for debugging
1020  *
1021  * We save/restore all registers marked with 'Driver', with the following
1022  * exceptions:
1023  * - Registers out of use, including also registers marked with 'Debug'.
1024  *   These have no effect on the driver's operation, so we don't save/restore
1025  *   them to reduce the overhead.
1026  * - Registers that are fully setup by an initialization function called from
1027  *   the resume path. For example many clock gating and RPS/RC6 registers.
1028  * - Registers that provide the right functionality with their reset defaults.
1029  *
1030  * TODO: Except for registers that based on the above 3 criteria can be safely
1031  * ignored, we save/restore all others, practically treating the HW context as
1032  * a black-box for the driver. Further investigation is needed to reduce the
1033  * saved/restored registers even further, by following the same 3 criteria.
1034  */
1035 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1036 {
1037         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1038         int i;
1039
1040         /* GAM 0x4000-0x4770 */
1041         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1042         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1043         s->arb_mode             = I915_READ(ARB_MODE);
1044         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1045         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1046
1047         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1048                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1049
1050         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1051         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1052
1053         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1054         s->ecochk               = I915_READ(GAM_ECOCHK);
1055         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1056         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1057
1058         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1059
1060         /* MBC 0x9024-0x91D0, 0x8500 */
1061         s->g3dctl               = I915_READ(VLV_G3DCTL);
1062         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1063         s->mbctl                = I915_READ(GEN6_MBCTL);
1064
1065         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1066         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1067         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1068         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1069         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1070         s->rstctl               = I915_READ(GEN6_RSTCTL);
1071         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1072
1073         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1074         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1075         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1076         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1077         s->ecobus               = I915_READ(ECOBUS);
1078         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1079         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1080         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1081         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1082         s->rcedata              = I915_READ(VLV_RCEDATA);
1083         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1084
1085         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1086         s->gt_imr               = I915_READ(GTIMR);
1087         s->gt_ier               = I915_READ(GTIER);
1088         s->pm_imr               = I915_READ(GEN6_PMIMR);
1089         s->pm_ier               = I915_READ(GEN6_PMIER);
1090
1091         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1092                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1093
1094         /* GT SA CZ domain, 0x100000-0x138124 */
1095         s->tilectl              = I915_READ(TILECTL);
1096         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1097         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1098         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1099         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1100
1101         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1102         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1103         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1104         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1105
1106         /*
1107          * Not saving any of:
1108          * DFT,         0x9800-0x9EC0
1109          * SARB,        0xB000-0xB1FC
1110          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1111          * PCI CFG
1112          */
1113 }
1114
1115 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1116 {
1117         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1118         u32 val;
1119         int i;
1120
1121         /* GAM 0x4000-0x4770 */
1122         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1123         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1124         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1125         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1126         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1127
1128         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1129                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1130
1131         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1132         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1133
1134         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1135         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1136         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1137         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1138
1139         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1140
1141         /* MBC 0x9024-0x91D0, 0x8500 */
1142         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1143         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1144         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1145
1146         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1147         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1148         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1149         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1150         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1151         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1152         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1153
1154         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1155         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1156         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1157         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1158         I915_WRITE(ECOBUS,              s->ecobus);
1159         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1160         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1161         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1162         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1163         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1164         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1165
1166         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1167         I915_WRITE(GTIMR,               s->gt_imr);
1168         I915_WRITE(GTIER,               s->gt_ier);
1169         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1170         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1171
1172         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1173                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1174
1175         /* GT SA CZ domain, 0x100000-0x138124 */
1176         I915_WRITE(TILECTL,                     s->tilectl);
1177         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1178         /*
1179          * Preserve the GT allow wake and GFX force clock bit, they are not
1180          * be restored, as they are used to control the s0ix suspend/resume
1181          * sequence by the caller.
1182          */
1183         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1184         val &= VLV_GTLC_ALLOWWAKEREQ;
1185         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1186         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1187
1188         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1189         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1190         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1191         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1192
1193         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1194
1195         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1196         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1197         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1198         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1199 }
1200
1201 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1202 {
1203         u32 val;
1204         int err;
1205
1206         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1207         WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1208
1209 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1210         /* Wait for a previous force-off to settle */
1211         if (force_on) {
1212                 err = wait_for(!COND, 20);
1213                 if (err) {
1214                         DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1215                                   I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1216                         return err;
1217                 }
1218         }
1219
1220         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1221         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1222         if (force_on)
1223                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1224         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1225
1226         if (!force_on)
1227                 return 0;
1228
1229         err = wait_for(COND, 20);
1230         if (err)
1231                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1232                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1233
1234         return err;
1235 #undef COND
1236 }
1237
1238 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1239 {
1240         u32 val;
1241         int err = 0;
1242
1243         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1244         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1245         if (allow)
1246                 val |= VLV_GTLC_ALLOWWAKEREQ;
1247         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1248         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1249
1250 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1251               allow)
1252         err = wait_for(COND, 1);
1253         if (err)
1254                 DRM_ERROR("timeout disabling GT waking\n");
1255         return err;
1256 #undef COND
1257 }
1258
1259 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1260                                  bool wait_for_on)
1261 {
1262         u32 mask;
1263         u32 val;
1264         int err;
1265
1266         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1267         val = wait_for_on ? mask : 0;
1268 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1269         if (COND)
1270                 return 0;
1271
1272         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1273                         wait_for_on ? "on" : "off",
1274                         I915_READ(VLV_GTLC_PW_STATUS));
1275
1276         /*
1277          * RC6 transitioning can be delayed up to 2 msec (see
1278          * valleyview_enable_rps), use 3 msec for safety.
1279          */
1280         err = wait_for(COND, 3);
1281         if (err)
1282                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1283                           wait_for_on ? "on" : "off");
1284
1285         return err;
1286 #undef COND
1287 }
1288
1289 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1290 {
1291         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1292                 return;
1293
1294         DRM_ERROR("GT register access while GT waking disabled\n");
1295         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1296 }
1297
1298 static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1299 {
1300         u32 mask;
1301         int err;
1302
1303         /*
1304          * Bspec defines the following GT well on flags as debug only, so
1305          * don't treat them as hard failures.
1306          */
1307         (void)vlv_wait_for_gt_wells(dev_priv, false);
1308
1309         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1310         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1311
1312         vlv_check_no_gt_access(dev_priv);
1313
1314         err = vlv_force_gfx_clock(dev_priv, true);
1315         if (err)
1316                 goto err1;
1317
1318         err = vlv_allow_gt_wake(dev_priv, false);
1319         if (err)
1320                 goto err2;
1321         vlv_save_gunit_s0ix_state(dev_priv);
1322
1323         err = vlv_force_gfx_clock(dev_priv, false);
1324         if (err)
1325                 goto err2;
1326
1327         return 0;
1328
1329 err2:
1330         /* For safety always re-enable waking and disable gfx clock forcing */
1331         vlv_allow_gt_wake(dev_priv, true);
1332 err1:
1333         vlv_force_gfx_clock(dev_priv, false);
1334
1335         return err;
1336 }
1337
1338 static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1339 {
1340         struct drm_device *dev = dev_priv->dev;
1341         int err;
1342         int ret;
1343
1344         /*
1345          * If any of the steps fail just try to continue, that's the best we
1346          * can do at this point. Return the first error code (which will also
1347          * leave RPM permanently disabled).
1348          */
1349         ret = vlv_force_gfx_clock(dev_priv, true);
1350
1351         vlv_restore_gunit_s0ix_state(dev_priv);
1352
1353         err = vlv_allow_gt_wake(dev_priv, true);
1354         if (!ret)
1355                 ret = err;
1356
1357         err = vlv_force_gfx_clock(dev_priv, false);
1358         if (!ret)
1359                 ret = err;
1360
1361         vlv_check_no_gt_access(dev_priv);
1362
1363         intel_init_clock_gating(dev);
1364         i915_gem_restore_fences(dev);
1365
1366         return ret;
1367 }
1368
1369 static int intel_runtime_suspend(struct device *device)
1370 {
1371         struct pci_dev *pdev = to_pci_dev(device);
1372         struct drm_device *dev = pci_get_drvdata(pdev);
1373         struct drm_i915_private *dev_priv = dev->dev_private;
1374         int ret;
1375
1376         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1377                 return -ENODEV;
1378
1379         WARN_ON(!HAS_RUNTIME_PM(dev));
1380         assert_force_wake_inactive(dev_priv);
1381
1382         DRM_DEBUG_KMS("Suspending device\n");
1383
1384         /*
1385          * We could deadlock here in case another thread holding struct_mutex
1386          * calls RPM suspend concurrently, since the RPM suspend will wait
1387          * first for this RPM suspend to finish. In this case the concurrent
1388          * RPM resume will be followed by its RPM suspend counterpart. Still
1389          * for consistency return -EAGAIN, which will reschedule this suspend.
1390          */
1391         if (!mutex_trylock(&dev->struct_mutex)) {
1392                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1393                 /*
1394                  * Bump the expiration timestamp, otherwise the suspend won't
1395                  * be rescheduled.
1396                  */
1397                 pm_runtime_mark_last_busy(device);
1398
1399                 return -EAGAIN;
1400         }
1401         /*
1402          * We are safe here against re-faults, since the fault handler takes
1403          * an RPM reference.
1404          */
1405         i915_gem_release_all_mmaps(dev_priv);
1406         mutex_unlock(&dev->struct_mutex);
1407
1408         /*
1409          * rps.work can't be rearmed here, since we get here only after making
1410          * sure the GPU is idle and the RPS freq is set to the minimum. See
1411          * intel_mark_idle().
1412          */
1413         cancel_work_sync(&dev_priv->rps.work);
1414         intel_runtime_pm_disable_interrupts(dev);
1415
1416         if (IS_GEN6(dev)) {
1417                 ret = 0;
1418         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1419                 ret = hsw_runtime_suspend(dev_priv);
1420         } else if (IS_VALLEYVIEW(dev)) {
1421                 ret = vlv_runtime_suspend(dev_priv);
1422         } else {
1423                 ret = -ENODEV;
1424                 WARN_ON(1);
1425         }
1426
1427         if (ret) {
1428                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1429                 intel_runtime_pm_restore_interrupts(dev);
1430
1431                 return ret;
1432         }
1433
1434         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1435         dev_priv->pm.suspended = true;
1436
1437         /*
1438          * current versions of firmware which depend on this opregion
1439          * notification have repurposed the D1 definition to mean
1440          * "runtime suspended" vs. what you would normally expect (D3)
1441          * to distinguish it from notifications that might be sent
1442          * via the suspend path.
1443          */
1444         intel_opregion_notify_adapter(dev, PCI_D1);
1445
1446         DRM_DEBUG_KMS("Device suspended\n");
1447         return 0;
1448 }
1449
1450 static int intel_runtime_resume(struct device *device)
1451 {
1452         struct pci_dev *pdev = to_pci_dev(device);
1453         struct drm_device *dev = pci_get_drvdata(pdev);
1454         struct drm_i915_private *dev_priv = dev->dev_private;
1455         int ret;
1456
1457         WARN_ON(!HAS_RUNTIME_PM(dev));
1458
1459         DRM_DEBUG_KMS("Resuming device\n");
1460
1461         intel_opregion_notify_adapter(dev, PCI_D0);
1462         dev_priv->pm.suspended = false;
1463
1464         if (IS_GEN6(dev)) {
1465                 ret = snb_runtime_resume(dev_priv);
1466         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1467                 ret = hsw_runtime_resume(dev_priv);
1468         } else if (IS_VALLEYVIEW(dev)) {
1469                 ret = vlv_runtime_resume(dev_priv);
1470         } else {
1471                 WARN_ON(1);
1472                 ret = -ENODEV;
1473         }
1474
1475         /*
1476          * No point of rolling back things in case of an error, as the best
1477          * we can do is to hope that things will still work (and disable RPM).
1478          */
1479         i915_gem_init_swizzling(dev);
1480         gen6_update_ring_freq(dev);
1481
1482         intel_runtime_pm_restore_interrupts(dev);
1483         intel_reset_gt_powersave(dev);
1484
1485         if (ret)
1486                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1487         else
1488                 DRM_DEBUG_KMS("Device resumed\n");
1489
1490         return ret;
1491 }
1492
1493 static const struct dev_pm_ops i915_pm_ops = {
1494         .suspend = i915_pm_suspend,
1495         .suspend_late = i915_pm_suspend_late,
1496         .resume_early = i915_pm_resume_early,
1497         .resume = i915_pm_resume,
1498         .freeze = i915_pm_freeze,
1499         .thaw_early = i915_pm_thaw_early,
1500         .thaw = i915_pm_thaw,
1501         .poweroff = i915_pm_poweroff,
1502         .restore_early = i915_pm_resume_early,
1503         .restore = i915_pm_resume,
1504         .runtime_suspend = intel_runtime_suspend,
1505         .runtime_resume = intel_runtime_resume,
1506 };
1507
1508 static const struct vm_operations_struct i915_gem_vm_ops = {
1509         .fault = i915_gem_fault,
1510         .open = drm_gem_vm_open,
1511         .close = drm_gem_vm_close,
1512 };
1513
1514 static const struct file_operations i915_driver_fops = {
1515         .owner = THIS_MODULE,
1516         .open = drm_open,
1517         .release = drm_release,
1518         .unlocked_ioctl = drm_ioctl,
1519         .mmap = drm_gem_mmap,
1520         .poll = drm_poll,
1521         .read = drm_read,
1522 #ifdef CONFIG_COMPAT
1523         .compat_ioctl = i915_compat_ioctl,
1524 #endif
1525         .llseek = noop_llseek,
1526 };
1527
1528 static struct drm_driver driver = {
1529         /* Don't use MTRRs here; the Xserver or userspace app should
1530          * deal with them for Intel hardware.
1531          */
1532         .driver_features =
1533             DRIVER_USE_AGP |
1534             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1535             DRIVER_RENDER,
1536         .load = i915_driver_load,
1537         .unload = i915_driver_unload,
1538         .open = i915_driver_open,
1539         .lastclose = i915_driver_lastclose,
1540         .preclose = i915_driver_preclose,
1541         .postclose = i915_driver_postclose,
1542
1543         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1544         .suspend = i915_suspend,
1545         .resume = i915_resume_legacy,
1546
1547         .device_is_agp = i915_driver_device_is_agp,
1548         .master_create = i915_master_create,
1549         .master_destroy = i915_master_destroy,
1550 #if defined(CONFIG_DEBUG_FS)
1551         .debugfs_init = i915_debugfs_init,
1552         .debugfs_cleanup = i915_debugfs_cleanup,
1553 #endif
1554         .gem_free_object = i915_gem_free_object,
1555         .gem_vm_ops = &i915_gem_vm_ops,
1556
1557         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1558         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1559         .gem_prime_export = i915_gem_prime_export,
1560         .gem_prime_import = i915_gem_prime_import,
1561
1562         .dumb_create = i915_gem_dumb_create,
1563         .dumb_map_offset = i915_gem_mmap_gtt,
1564         .dumb_destroy = drm_gem_dumb_destroy,
1565         .ioctls = i915_ioctls,
1566         .fops = &i915_driver_fops,
1567         .name = DRIVER_NAME,
1568         .desc = DRIVER_DESC,
1569         .date = DRIVER_DATE,
1570         .major = DRIVER_MAJOR,
1571         .minor = DRIVER_MINOR,
1572         .patchlevel = DRIVER_PATCHLEVEL,
1573 };
1574
1575 static struct pci_driver i915_pci_driver = {
1576         .name = DRIVER_NAME,
1577         .id_table = pciidlist,
1578         .probe = i915_pci_probe,
1579         .remove = i915_pci_remove,
1580         .driver.pm = &i915_pm_ops,
1581 };
1582
1583 static int __init i915_init(void)
1584 {
1585         driver.num_ioctls = i915_max_ioctl;
1586
1587         /*
1588          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1589          * explicitly disabled with the module pararmeter.
1590          *
1591          * Otherwise, just follow the parameter (defaulting to off).
1592          *
1593          * Allow optional vga_text_mode_force boot option to override
1594          * the default behavior.
1595          */
1596 #if defined(CONFIG_DRM_I915_KMS)
1597         if (i915.modeset != 0)
1598                 driver.driver_features |= DRIVER_MODESET;
1599 #endif
1600         if (i915.modeset == 1)
1601                 driver.driver_features |= DRIVER_MODESET;
1602
1603 #ifdef CONFIG_VGA_CONSOLE
1604         if (vgacon_text_force() && i915.modeset == -1)
1605                 driver.driver_features &= ~DRIVER_MODESET;
1606 #endif
1607
1608         if (!(driver.driver_features & DRIVER_MODESET)) {
1609                 driver.get_vblank_timestamp = NULL;
1610 #ifndef CONFIG_DRM_I915_UMS
1611                 /* Silently fail loading to not upset userspace. */
1612                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1613                 return 0;
1614 #endif
1615         }
1616
1617         return drm_pci_init(&driver, &i915_pci_driver);
1618 }
1619
1620 static void __exit i915_exit(void)
1621 {
1622 #ifndef CONFIG_DRM_I915_UMS
1623         if (!(driver.driver_features & DRIVER_MODESET))
1624                 return; /* Never loaded a driver. */
1625 #endif
1626
1627         drm_pci_exit(&driver, &i915_pci_driver);
1628 }
1629
1630 module_init(i915_init);
1631 module_exit(i915_exit);
1632
1633 MODULE_AUTHOR(DRIVER_AUTHOR);
1634 MODULE_DESCRIPTION(DRIVER_DESC);
1635 MODULE_LICENSE("GPL and additional rights");