1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <drm/drm_crtc_helper.h>
43 static struct drm_driver driver;
45 #define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
52 #define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
57 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
60 #define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
63 #define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
66 static const struct intel_device_info intel_i830_info = {
67 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
68 .has_overlay = 1, .overlay_needs_physical = 1,
69 .ring_mask = RENDER_RING,
70 GEN_DEFAULT_PIPEOFFSETS,
74 static const struct intel_device_info intel_845g_info = {
75 .gen = 2, .num_pipes = 1,
76 .has_overlay = 1, .overlay_needs_physical = 1,
77 .ring_mask = RENDER_RING,
78 GEN_DEFAULT_PIPEOFFSETS,
82 static const struct intel_device_info intel_i85x_info = {
83 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
84 .cursor_needs_physical = 1,
85 .has_overlay = 1, .overlay_needs_physical = 1,
87 .ring_mask = RENDER_RING,
88 GEN_DEFAULT_PIPEOFFSETS,
92 static const struct intel_device_info intel_i865g_info = {
93 .gen = 2, .num_pipes = 1,
94 .has_overlay = 1, .overlay_needs_physical = 1,
95 .ring_mask = RENDER_RING,
96 GEN_DEFAULT_PIPEOFFSETS,
100 static const struct intel_device_info intel_i915g_info = {
101 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
102 .has_overlay = 1, .overlay_needs_physical = 1,
103 .ring_mask = RENDER_RING,
104 GEN_DEFAULT_PIPEOFFSETS,
107 static const struct intel_device_info intel_i915gm_info = {
108 .gen = 3, .is_mobile = 1, .num_pipes = 2,
109 .cursor_needs_physical = 1,
110 .has_overlay = 1, .overlay_needs_physical = 1,
113 .ring_mask = RENDER_RING,
114 GEN_DEFAULT_PIPEOFFSETS,
117 static const struct intel_device_info intel_i945g_info = {
118 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
119 .has_overlay = 1, .overlay_needs_physical = 1,
120 .ring_mask = RENDER_RING,
121 GEN_DEFAULT_PIPEOFFSETS,
124 static const struct intel_device_info intel_i945gm_info = {
125 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
126 .has_hotplug = 1, .cursor_needs_physical = 1,
127 .has_overlay = 1, .overlay_needs_physical = 1,
130 .ring_mask = RENDER_RING,
131 GEN_DEFAULT_PIPEOFFSETS,
135 static const struct intel_device_info intel_i965g_info = {
136 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
139 .ring_mask = RENDER_RING,
140 GEN_DEFAULT_PIPEOFFSETS,
144 static const struct intel_device_info intel_i965gm_info = {
145 .gen = 4, .is_crestline = 1, .num_pipes = 2,
146 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
149 .ring_mask = RENDER_RING,
150 GEN_DEFAULT_PIPEOFFSETS,
154 static const struct intel_device_info intel_g33_info = {
155 .gen = 3, .is_g33 = 1, .num_pipes = 2,
156 .need_gfx_hws = 1, .has_hotplug = 1,
158 .ring_mask = RENDER_RING,
159 GEN_DEFAULT_PIPEOFFSETS,
163 static const struct intel_device_info intel_g45_info = {
164 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
165 .has_pipe_cxsr = 1, .has_hotplug = 1,
166 .ring_mask = RENDER_RING | BSD_RING,
167 GEN_DEFAULT_PIPEOFFSETS,
171 static const struct intel_device_info intel_gm45_info = {
172 .gen = 4, .is_g4x = 1, .num_pipes = 2,
173 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
174 .has_pipe_cxsr = 1, .has_hotplug = 1,
176 .ring_mask = RENDER_RING | BSD_RING,
177 GEN_DEFAULT_PIPEOFFSETS,
181 static const struct intel_device_info intel_pineview_info = {
182 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
183 .need_gfx_hws = 1, .has_hotplug = 1,
185 GEN_DEFAULT_PIPEOFFSETS,
189 static const struct intel_device_info intel_ironlake_d_info = {
190 .gen = 5, .num_pipes = 2,
191 .need_gfx_hws = 1, .has_hotplug = 1,
192 .ring_mask = RENDER_RING | BSD_RING,
193 GEN_DEFAULT_PIPEOFFSETS,
197 static const struct intel_device_info intel_ironlake_m_info = {
198 .gen = 5, .is_mobile = 1, .num_pipes = 2,
199 .need_gfx_hws = 1, .has_hotplug = 1,
201 .ring_mask = RENDER_RING | BSD_RING,
202 GEN_DEFAULT_PIPEOFFSETS,
206 static const struct intel_device_info intel_sandybridge_d_info = {
207 .gen = 6, .num_pipes = 2,
208 .need_gfx_hws = 1, .has_hotplug = 1,
210 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
212 GEN_DEFAULT_PIPEOFFSETS,
216 static const struct intel_device_info intel_sandybridge_m_info = {
217 .gen = 6, .is_mobile = 1, .num_pipes = 2,
218 .need_gfx_hws = 1, .has_hotplug = 1,
220 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
222 GEN_DEFAULT_PIPEOFFSETS,
226 #define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
233 static const struct intel_device_info intel_ivybridge_d_info = {
236 GEN_DEFAULT_PIPEOFFSETS,
240 static const struct intel_device_info intel_ivybridge_m_info = {
244 GEN_DEFAULT_PIPEOFFSETS,
248 static const struct intel_device_info intel_ivybridge_q_info = {
251 .num_pipes = 0, /* legal, last one wins */
252 GEN_DEFAULT_PIPEOFFSETS,
256 static const struct intel_device_info intel_valleyview_m_info = {
261 .display_mmio_offset = VLV_DISPLAY_BASE,
262 .has_fbc = 0, /* legal, last one wins */
263 .has_llc = 0, /* legal, last one wins */
264 GEN_DEFAULT_PIPEOFFSETS,
268 static const struct intel_device_info intel_valleyview_d_info = {
272 .display_mmio_offset = VLV_DISPLAY_BASE,
273 .has_fbc = 0, /* legal, last one wins */
274 .has_llc = 0, /* legal, last one wins */
275 GEN_DEFAULT_PIPEOFFSETS,
279 static const struct intel_device_info intel_haswell_d_info = {
284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
285 GEN_DEFAULT_PIPEOFFSETS,
289 static const struct intel_device_info intel_haswell_m_info = {
295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
296 GEN_DEFAULT_PIPEOFFSETS,
300 static const struct intel_device_info intel_broadwell_d_info = {
301 .gen = 8, .num_pipes = 3,
302 .need_gfx_hws = 1, .has_hotplug = 1,
303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
308 GEN_DEFAULT_PIPEOFFSETS,
312 static const struct intel_device_info intel_broadwell_m_info = {
313 .gen = 8, .is_mobile = 1, .num_pipes = 3,
314 .need_gfx_hws = 1, .has_hotplug = 1,
315 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
320 GEN_DEFAULT_PIPEOFFSETS,
324 static const struct intel_device_info intel_broadwell_gt3d_info = {
325 .gen = 8, .num_pipes = 3,
326 .need_gfx_hws = 1, .has_hotplug = 1,
327 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
332 GEN_DEFAULT_PIPEOFFSETS,
336 static const struct intel_device_info intel_broadwell_gt3m_info = {
337 .gen = 8, .is_mobile = 1, .num_pipes = 3,
338 .need_gfx_hws = 1, .has_hotplug = 1,
339 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
344 GEN_DEFAULT_PIPEOFFSETS,
348 static const struct intel_device_info intel_cherryview_info = {
350 .gen = 8, .num_pipes = 3,
351 .need_gfx_hws = 1, .has_hotplug = 1,
352 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
354 .display_mmio_offset = VLV_DISPLAY_BASE,
359 static const struct intel_device_info intel_skylake_info = {
362 .gen = 9, .num_pipes = 3,
363 .need_gfx_hws = 1, .has_hotplug = 1,
364 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
368 GEN_DEFAULT_PIPEOFFSETS,
373 * Make sure any device matches here are from most specific to most
374 * general. For example, since the Quanta match is based on the subsystem
375 * and subvendor IDs, we need it to come before the more general IVB
376 * PCI ID matches, otherwise we'll use the wrong info struct above.
378 #define INTEL_PCI_IDS \
379 INTEL_I830_IDS(&intel_i830_info), \
380 INTEL_I845G_IDS(&intel_845g_info), \
381 INTEL_I85X_IDS(&intel_i85x_info), \
382 INTEL_I865G_IDS(&intel_i865g_info), \
383 INTEL_I915G_IDS(&intel_i915g_info), \
384 INTEL_I915GM_IDS(&intel_i915gm_info), \
385 INTEL_I945G_IDS(&intel_i945g_info), \
386 INTEL_I945GM_IDS(&intel_i945gm_info), \
387 INTEL_I965G_IDS(&intel_i965g_info), \
388 INTEL_G33_IDS(&intel_g33_info), \
389 INTEL_I965GM_IDS(&intel_i965gm_info), \
390 INTEL_GM45_IDS(&intel_gm45_info), \
391 INTEL_G45_IDS(&intel_g45_info), \
392 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
393 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
394 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
395 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
396 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
397 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
398 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
399 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
400 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
401 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
402 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
403 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
404 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
405 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
406 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
407 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
408 INTEL_CHV_IDS(&intel_cherryview_info), \
409 INTEL_SKL_IDS(&intel_skylake_info)
411 static const struct pci_device_id pciidlist[] = { /* aka */
416 #if defined(CONFIG_DRM_I915_KMS)
417 MODULE_DEVICE_TABLE(pci, pciidlist);
420 void intel_detect_pch(struct drm_device *dev)
422 struct drm_i915_private *dev_priv = dev->dev_private;
423 struct pci_dev *pch = NULL;
425 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
426 * (which really amounts to a PCH but no South Display).
428 if (INTEL_INFO(dev)->num_pipes == 0) {
429 dev_priv->pch_type = PCH_NOP;
434 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
435 * make graphics device passthrough work easy for VMM, that only
436 * need to expose ISA bridge to let driver know the real hardware
437 * underneath. This is a requirement from virtualization team.
439 * In some virtualized environments (e.g. XEN), there is irrelevant
440 * ISA bridge in the system. To work reliably, we should scan trhough
441 * all the ISA bridge devices and check for the first match, instead
442 * of only checking the first one.
444 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
445 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
446 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
447 dev_priv->pch_id = id;
449 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
450 dev_priv->pch_type = PCH_IBX;
451 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
452 WARN_ON(!IS_GEN5(dev));
453 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
454 dev_priv->pch_type = PCH_CPT;
455 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
456 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
457 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
458 /* PantherPoint is CPT compatible */
459 dev_priv->pch_type = PCH_CPT;
460 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
461 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
462 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
463 dev_priv->pch_type = PCH_LPT;
464 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
465 WARN_ON(!IS_HASWELL(dev));
466 WARN_ON(IS_HSW_ULT(dev));
467 } else if (IS_BROADWELL(dev)) {
468 dev_priv->pch_type = PCH_LPT;
470 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
471 DRM_DEBUG_KMS("This is Broadwell, assuming "
472 "LynxPoint LP PCH\n");
473 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
474 dev_priv->pch_type = PCH_LPT;
475 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
476 WARN_ON(!IS_HASWELL(dev));
477 WARN_ON(!IS_HSW_ULT(dev));
478 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
479 dev_priv->pch_type = PCH_SPT;
480 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
481 WARN_ON(!IS_SKYLAKE(dev));
482 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
483 dev_priv->pch_type = PCH_SPT;
484 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
485 WARN_ON(!IS_SKYLAKE(dev));
493 DRM_DEBUG_KMS("No PCH found.\n");
498 bool i915_semaphore_is_enabled(struct drm_device *dev)
500 if (INTEL_INFO(dev)->gen < 6)
503 if (i915.semaphores >= 0)
504 return i915.semaphores;
506 /* TODO: make semaphores and Execlists play nicely together */
507 if (i915.enable_execlists)
510 /* Until we get further testing... */
514 #ifdef CONFIG_INTEL_IOMMU
515 /* Enable semaphores on SNB when IO remapping is off */
516 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
523 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
525 spin_lock_irq(&dev_priv->irq_lock);
527 dev_priv->long_hpd_port_mask = 0;
528 dev_priv->short_hpd_port_mask = 0;
529 dev_priv->hpd_event_bits = 0;
531 spin_unlock_irq(&dev_priv->irq_lock);
533 cancel_work_sync(&dev_priv->dig_port_work);
534 cancel_work_sync(&dev_priv->hotplug_work);
535 cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
538 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
540 struct drm_device *dev = dev_priv->dev;
541 struct drm_encoder *encoder;
543 drm_modeset_lock_all(dev);
544 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
545 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
547 if (intel_encoder->suspend)
548 intel_encoder->suspend(intel_encoder);
550 drm_modeset_unlock_all(dev);
553 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
554 static int intel_resume_prepare(struct drm_i915_private *dev_priv,
557 static int i915_drm_freeze(struct drm_device *dev)
559 struct drm_i915_private *dev_priv = dev->dev_private;
560 struct drm_crtc *crtc;
561 pci_power_t opregion_target_state;
563 /* ignore lid events during suspend */
564 mutex_lock(&dev_priv->modeset_restore_lock);
565 dev_priv->modeset_restore = MODESET_SUSPENDED;
566 mutex_unlock(&dev_priv->modeset_restore_lock);
568 /* We do a lot of poking in a lot of registers, make sure they work
570 intel_display_set_init_power(dev_priv, true);
572 drm_kms_helper_poll_disable(dev);
574 pci_save_state(dev->pdev);
576 /* If KMS is active, we do the leavevt stuff here */
577 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
580 error = i915_gem_suspend(dev);
582 dev_err(&dev->pdev->dev,
583 "GEM idle failed, resume might fail\n");
588 * Disable CRTCs directly since we want to preserve sw state
589 * for _thaw. Also, power gate the CRTC power wells.
591 drm_modeset_lock_all(dev);
592 for_each_crtc(dev, crtc)
593 intel_crtc_control(crtc, false);
594 drm_modeset_unlock_all(dev);
596 intel_dp_mst_suspend(dev);
598 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
600 intel_runtime_pm_disable_interrupts(dev_priv);
601 intel_hpd_cancel_work(dev_priv);
603 intel_suspend_encoders(dev_priv);
605 intel_suspend_gt_powersave(dev);
607 intel_suspend_hw(dev);
610 i915_gem_suspend_gtt_mappings(dev);
612 i915_save_state(dev);
614 opregion_target_state = PCI_D3cold;
615 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
616 if (acpi_target_system_state() < ACPI_STATE_S3)
617 opregion_target_state = PCI_D1;
619 intel_opregion_notify_adapter(dev, opregion_target_state);
621 intel_uncore_forcewake_reset(dev, false);
622 intel_opregion_fini(dev);
624 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
626 dev_priv->suspend_count++;
628 intel_display_set_init_power(dev_priv, false);
633 int i915_suspend(struct drm_device *dev, pm_message_t state)
637 if (!dev || !dev->dev_private) {
638 DRM_ERROR("dev: %p\n", dev);
639 DRM_ERROR("DRM not initialized, aborting suspend.\n");
643 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
644 state.event != PM_EVENT_FREEZE))
647 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
650 error = i915_drm_freeze(dev);
654 if (state.event == PM_EVENT_SUSPEND) {
655 /* Shut down the device */
656 pci_disable_device(dev->pdev);
657 pci_set_power_state(dev->pdev, PCI_D3hot);
663 static int i915_drm_thaw_early(struct drm_device *dev)
665 struct drm_i915_private *dev_priv = dev->dev_private;
668 ret = intel_resume_prepare(dev_priv, false);
670 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
672 intel_uncore_early_sanitize(dev, true);
673 intel_uncore_sanitize(dev);
674 intel_power_domains_init_hw(dev_priv);
679 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
681 struct drm_i915_private *dev_priv = dev->dev_private;
683 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
684 restore_gtt_mappings) {
685 mutex_lock(&dev->struct_mutex);
686 i915_gem_restore_gtt_mappings(dev);
687 mutex_unlock(&dev->struct_mutex);
690 i915_restore_state(dev);
691 intel_opregion_setup(dev);
693 /* KMS EnterVT equivalent */
694 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
695 intel_init_pch_refclk(dev);
696 drm_mode_config_reset(dev);
698 mutex_lock(&dev->struct_mutex);
699 if (i915_gem_init_hw(dev)) {
700 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
701 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
703 mutex_unlock(&dev->struct_mutex);
705 /* We need working interrupts for modeset enabling ... */
706 intel_runtime_pm_enable_interrupts(dev_priv);
708 intel_modeset_init_hw(dev);
711 spin_lock_irq(&dev_priv->irq_lock);
712 if (dev_priv->display.hpd_irq_setup)
713 dev_priv->display.hpd_irq_setup(dev);
714 spin_unlock_irq(&dev_priv->irq_lock);
717 intel_dp_mst_resume(dev);
718 drm_modeset_lock_all(dev);
719 intel_modeset_setup_hw_state(dev, true);
720 drm_modeset_unlock_all(dev);
723 * ... but also need to make sure that hotplug processing
724 * doesn't cause havoc. Like in the driver load code we don't
725 * bother with the tiny race here where we might loose hotplug
728 intel_hpd_init(dev_priv);
729 /* Config may have changed between suspend and resume */
730 drm_helper_hpd_irq_event(dev);
733 intel_opregion_init(dev);
735 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
737 mutex_lock(&dev_priv->modeset_restore_lock);
738 dev_priv->modeset_restore = MODESET_DONE;
739 mutex_unlock(&dev_priv->modeset_restore_lock);
741 intel_opregion_notify_adapter(dev, PCI_D0);
746 static int i915_drm_thaw(struct drm_device *dev)
748 if (drm_core_check_feature(dev, DRIVER_MODESET))
749 i915_check_and_clear_faults(dev);
751 return __i915_drm_thaw(dev, true);
754 static int i915_resume_early(struct drm_device *dev)
756 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
760 * We have a resume ordering issue with the snd-hda driver also
761 * requiring our device to be power up. Due to the lack of a
762 * parent/child relationship we currently solve this with an early
765 * FIXME: This should be solved with a special hdmi sink device or
766 * similar so that power domains can be employed.
768 if (pci_enable_device(dev->pdev))
771 pci_set_master(dev->pdev);
773 return i915_drm_thaw_early(dev);
776 int i915_resume(struct drm_device *dev)
778 struct drm_i915_private *dev_priv = dev->dev_private;
782 * Platforms with opregion should have sane BIOS, older ones (gen3 and
783 * earlier) need to restore the GTT mappings since the BIOS might clear
784 * all our scratch PTEs.
786 ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
790 drm_kms_helper_poll_enable(dev);
794 static int i915_resume_legacy(struct drm_device *dev)
796 i915_resume_early(dev);
803 * i915_reset - reset chip after a hang
804 * @dev: drm device to reset
806 * Reset the chip. Useful if a hang is detected. Returns zero on successful
807 * reset or otherwise an error code.
809 * Procedure is fairly simple:
810 * - reset the chip using the reset reg
811 * - re-init context state
812 * - re-init hardware status page
813 * - re-init ring buffer
814 * - re-init interrupt state
817 int i915_reset(struct drm_device *dev)
819 struct drm_i915_private *dev_priv = dev->dev_private;
826 mutex_lock(&dev->struct_mutex);
830 simulated = dev_priv->gpu_error.stop_rings != 0;
832 ret = intel_gpu_reset(dev);
834 /* Also reset the gpu hangman. */
836 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
837 dev_priv->gpu_error.stop_rings = 0;
838 if (ret == -ENODEV) {
839 DRM_INFO("Reset not implemented, but ignoring "
840 "error for simulated gpu hangs\n");
845 if (i915_stop_ring_allow_warn(dev_priv))
846 pr_notice("drm/i915: Resetting chip after gpu hang\n");
849 DRM_ERROR("Failed to reset chip: %i\n", ret);
850 mutex_unlock(&dev->struct_mutex);
854 /* Ok, now get things going again... */
857 * Everything depends on having the GTT running, so we need to start
858 * there. Fortunately we don't need to do this unless we reset the
859 * chip at a PCI level.
861 * Next we need to restore the context, but we don't use those
864 * Ring buffer needs to be re-initialized in the KMS case, or if X
865 * was running at the time of the reset (i.e. we weren't VT
868 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
869 !dev_priv->ums.mm_suspended) {
870 dev_priv->ums.mm_suspended = 0;
872 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
873 dev_priv->gpu_error.reload_in_reset = true;
875 ret = i915_gem_init_hw(dev);
877 dev_priv->gpu_error.reload_in_reset = false;
879 mutex_unlock(&dev->struct_mutex);
881 DRM_ERROR("Failed hw init on reset %d\n", ret);
886 * FIXME: This races pretty badly against concurrent holders of
887 * ring interrupts. This is possible since we've started to drop
888 * dev->struct_mutex in select places when waiting for the gpu.
892 * rps/rc6 re-init is necessary to restore state lost after the
893 * reset and the re-install of gt irqs. Skip for ironlake per
894 * previous concerns that it doesn't respond well to some forms
895 * of re-init after reset.
897 if (INTEL_INFO(dev)->gen > 5)
898 intel_reset_gt_powersave(dev);
900 mutex_unlock(&dev->struct_mutex);
906 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
908 struct intel_device_info *intel_info =
909 (struct intel_device_info *) ent->driver_data;
911 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
912 DRM_INFO("This hardware requires preliminary hardware support.\n"
913 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
917 /* Only bind to function 0 of the device. Early generations
918 * used function 1 as a placeholder for multi-head. This causes
919 * us confusion instead, especially on the systems where both
920 * functions have the same PCI-ID!
922 if (PCI_FUNC(pdev->devfn))
925 driver.driver_features &= ~(DRIVER_USE_AGP);
927 return drm_get_pci_dev(pdev, ent, &driver);
931 i915_pci_remove(struct pci_dev *pdev)
933 struct drm_device *dev = pci_get_drvdata(pdev);
938 static int i915_pm_suspend(struct device *dev)
940 struct pci_dev *pdev = to_pci_dev(dev);
941 struct drm_device *drm_dev = pci_get_drvdata(pdev);
943 if (!drm_dev || !drm_dev->dev_private) {
944 dev_err(dev, "DRM not initialized, aborting suspend.\n");
948 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
951 return i915_drm_freeze(drm_dev);
954 static int i915_pm_suspend_late(struct device *dev)
956 struct pci_dev *pdev = to_pci_dev(dev);
957 struct drm_device *drm_dev = pci_get_drvdata(pdev);
958 struct drm_i915_private *dev_priv = drm_dev->dev_private;
962 * We have a suspedn ordering issue with the snd-hda driver also
963 * requiring our device to be power up. Due to the lack of a
964 * parent/child relationship we currently solve this with an late
967 * FIXME: This should be solved with a special hdmi sink device or
968 * similar so that power domains can be employed.
970 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
973 ret = intel_suspend_complete(dev_priv);
976 DRM_ERROR("Suspend complete failed: %d\n", ret);
978 pci_disable_device(pdev);
979 pci_set_power_state(pdev, PCI_D3hot);
985 static int i915_pm_resume_early(struct device *dev)
987 struct pci_dev *pdev = to_pci_dev(dev);
988 struct drm_device *drm_dev = pci_get_drvdata(pdev);
990 return i915_resume_early(drm_dev);
993 static int i915_pm_resume(struct device *dev)
995 struct pci_dev *pdev = to_pci_dev(dev);
996 struct drm_device *drm_dev = pci_get_drvdata(pdev);
998 return i915_resume(drm_dev);
1001 static int i915_pm_freeze(struct device *dev)
1003 struct pci_dev *pdev = to_pci_dev(dev);
1004 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1006 if (!drm_dev || !drm_dev->dev_private) {
1007 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1011 return i915_drm_freeze(drm_dev);
1014 static int i915_pm_thaw_early(struct device *dev)
1016 struct pci_dev *pdev = to_pci_dev(dev);
1017 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1019 return i915_drm_thaw_early(drm_dev);
1022 static int i915_pm_thaw(struct device *dev)
1024 struct pci_dev *pdev = to_pci_dev(dev);
1025 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1027 return i915_drm_thaw(drm_dev);
1030 static int i915_pm_poweroff(struct device *dev)
1032 struct pci_dev *pdev = to_pci_dev(dev);
1033 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1035 return i915_drm_freeze(drm_dev);
1038 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1040 hsw_enable_pc8(dev_priv);
1045 static int snb_resume_prepare(struct drm_i915_private *dev_priv,
1048 struct drm_device *dev = dev_priv->dev;
1051 intel_init_pch_refclk(dev);
1056 static int hsw_resume_prepare(struct drm_i915_private *dev_priv,
1059 hsw_disable_pc8(dev_priv);
1065 * Save all Gunit registers that may be lost after a D3 and a subsequent
1066 * S0i[R123] transition. The list of registers needing a save/restore is
1067 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1068 * registers in the following way:
1069 * - Driver: saved/restored by the driver
1070 * - Punit : saved/restored by the Punit firmware
1071 * - No, w/o marking: no need to save/restore, since the register is R/O or
1072 * used internally by the HW in a way that doesn't depend
1073 * keeping the content across a suspend/resume.
1074 * - Debug : used for debugging
1076 * We save/restore all registers marked with 'Driver', with the following
1078 * - Registers out of use, including also registers marked with 'Debug'.
1079 * These have no effect on the driver's operation, so we don't save/restore
1080 * them to reduce the overhead.
1081 * - Registers that are fully setup by an initialization function called from
1082 * the resume path. For example many clock gating and RPS/RC6 registers.
1083 * - Registers that provide the right functionality with their reset defaults.
1085 * TODO: Except for registers that based on the above 3 criteria can be safely
1086 * ignored, we save/restore all others, practically treating the HW context as
1087 * a black-box for the driver. Further investigation is needed to reduce the
1088 * saved/restored registers even further, by following the same 3 criteria.
1090 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1092 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1095 /* GAM 0x4000-0x4770 */
1096 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1097 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1098 s->arb_mode = I915_READ(ARB_MODE);
1099 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1100 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1102 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1103 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1105 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1106 s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1108 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1109 s->ecochk = I915_READ(GAM_ECOCHK);
1110 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1111 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1113 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1115 /* MBC 0x9024-0x91D0, 0x8500 */
1116 s->g3dctl = I915_READ(VLV_G3DCTL);
1117 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1118 s->mbctl = I915_READ(GEN6_MBCTL);
1120 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1121 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1122 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1123 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1124 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1125 s->rstctl = I915_READ(GEN6_RSTCTL);
1126 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1128 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1129 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1130 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1131 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1132 s->ecobus = I915_READ(ECOBUS);
1133 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1134 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1135 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1136 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1137 s->rcedata = I915_READ(VLV_RCEDATA);
1138 s->spare2gh = I915_READ(VLV_SPAREG2H);
1140 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1141 s->gt_imr = I915_READ(GTIMR);
1142 s->gt_ier = I915_READ(GTIER);
1143 s->pm_imr = I915_READ(GEN6_PMIMR);
1144 s->pm_ier = I915_READ(GEN6_PMIER);
1146 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1147 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1149 /* GT SA CZ domain, 0x100000-0x138124 */
1150 s->tilectl = I915_READ(TILECTL);
1151 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1152 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1153 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1154 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1156 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1157 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1158 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1159 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1162 * Not saving any of:
1163 * DFT, 0x9800-0x9EC0
1164 * SARB, 0xB000-0xB1FC
1165 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1170 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1172 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1176 /* GAM 0x4000-0x4770 */
1177 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1178 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1179 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1180 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1181 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1183 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1184 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1186 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1187 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1189 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1190 I915_WRITE(GAM_ECOCHK, s->ecochk);
1191 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1192 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1194 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1196 /* MBC 0x9024-0x91D0, 0x8500 */
1197 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1198 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1199 I915_WRITE(GEN6_MBCTL, s->mbctl);
1201 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1202 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1203 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1204 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1205 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1206 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1207 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1209 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1210 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1211 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1212 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1213 I915_WRITE(ECOBUS, s->ecobus);
1214 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1215 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1216 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1217 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1218 I915_WRITE(VLV_RCEDATA, s->rcedata);
1219 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1221 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1222 I915_WRITE(GTIMR, s->gt_imr);
1223 I915_WRITE(GTIER, s->gt_ier);
1224 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1225 I915_WRITE(GEN6_PMIER, s->pm_ier);
1227 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1228 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1230 /* GT SA CZ domain, 0x100000-0x138124 */
1231 I915_WRITE(TILECTL, s->tilectl);
1232 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1234 * Preserve the GT allow wake and GFX force clock bit, they are not
1235 * be restored, as they are used to control the s0ix suspend/resume
1236 * sequence by the caller.
1238 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1239 val &= VLV_GTLC_ALLOWWAKEREQ;
1240 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1241 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1243 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1244 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1245 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1246 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1248 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1250 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1251 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1252 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1253 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1256 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1261 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1262 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1264 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1265 /* Wait for a previous force-off to settle */
1267 err = wait_for(!COND, 20);
1269 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1270 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1275 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1276 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1278 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1279 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1284 err = wait_for(COND, 20);
1286 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1287 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1293 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1298 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1299 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1301 val |= VLV_GTLC_ALLOWWAKEREQ;
1302 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1303 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1305 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1307 err = wait_for(COND, 1);
1309 DRM_ERROR("timeout disabling GT waking\n");
1314 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1321 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1322 val = wait_for_on ? mask : 0;
1323 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1327 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1328 wait_for_on ? "on" : "off",
1329 I915_READ(VLV_GTLC_PW_STATUS));
1332 * RC6 transitioning can be delayed up to 2 msec (see
1333 * valleyview_enable_rps), use 3 msec for safety.
1335 err = wait_for(COND, 3);
1337 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1338 wait_for_on ? "on" : "off");
1344 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1346 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1349 DRM_ERROR("GT register access while GT waking disabled\n");
1350 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1353 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1359 * Bspec defines the following GT well on flags as debug only, so
1360 * don't treat them as hard failures.
1362 (void)vlv_wait_for_gt_wells(dev_priv, false);
1364 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1365 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1367 vlv_check_no_gt_access(dev_priv);
1369 err = vlv_force_gfx_clock(dev_priv, true);
1373 err = vlv_allow_gt_wake(dev_priv, false);
1376 vlv_save_gunit_s0ix_state(dev_priv);
1378 err = vlv_force_gfx_clock(dev_priv, false);
1385 /* For safety always re-enable waking and disable gfx clock forcing */
1386 vlv_allow_gt_wake(dev_priv, true);
1388 vlv_force_gfx_clock(dev_priv, false);
1393 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1396 struct drm_device *dev = dev_priv->dev;
1401 * If any of the steps fail just try to continue, that's the best we
1402 * can do at this point. Return the first error code (which will also
1403 * leave RPM permanently disabled).
1405 ret = vlv_force_gfx_clock(dev_priv, true);
1407 vlv_restore_gunit_s0ix_state(dev_priv);
1409 err = vlv_allow_gt_wake(dev_priv, true);
1413 err = vlv_force_gfx_clock(dev_priv, false);
1417 vlv_check_no_gt_access(dev_priv);
1420 intel_init_clock_gating(dev);
1421 i915_gem_restore_fences(dev);
1427 static int intel_runtime_suspend(struct device *device)
1429 struct pci_dev *pdev = to_pci_dev(device);
1430 struct drm_device *dev = pci_get_drvdata(pdev);
1431 struct drm_i915_private *dev_priv = dev->dev_private;
1434 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1437 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1440 assert_force_wake_inactive(dev_priv);
1442 DRM_DEBUG_KMS("Suspending device\n");
1445 * We could deadlock here in case another thread holding struct_mutex
1446 * calls RPM suspend concurrently, since the RPM suspend will wait
1447 * first for this RPM suspend to finish. In this case the concurrent
1448 * RPM resume will be followed by its RPM suspend counterpart. Still
1449 * for consistency return -EAGAIN, which will reschedule this suspend.
1451 if (!mutex_trylock(&dev->struct_mutex)) {
1452 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1454 * Bump the expiration timestamp, otherwise the suspend won't
1457 pm_runtime_mark_last_busy(device);
1462 * We are safe here against re-faults, since the fault handler takes
1465 i915_gem_release_all_mmaps(dev_priv);
1466 mutex_unlock(&dev->struct_mutex);
1469 * rps.work can't be rearmed here, since we get here only after making
1470 * sure the GPU is idle and the RPS freq is set to the minimum. See
1471 * intel_mark_idle().
1473 cancel_work_sync(&dev_priv->rps.work);
1474 intel_runtime_pm_disable_interrupts(dev_priv);
1476 ret = intel_suspend_complete(dev_priv);
1478 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1479 intel_runtime_pm_enable_interrupts(dev_priv);
1484 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1485 dev_priv->pm.suspended = true;
1488 * FIXME: We really should find a document that references the arguments
1491 if (IS_HASWELL(dev)) {
1493 * current versions of firmware which depend on this opregion
1494 * notification have repurposed the D1 definition to mean
1495 * "runtime suspended" vs. what you would normally expect (D3)
1496 * to distinguish it from notifications that might be sent via
1499 intel_opregion_notify_adapter(dev, PCI_D1);
1502 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1503 * being detected, and the call we do at intel_runtime_resume()
1504 * won't be able to restore them. Since PCI_D3hot matches the
1505 * actual specification and appears to be working, use it. Let's
1506 * assume the other non-Haswell platforms will stay the same as
1509 intel_opregion_notify_adapter(dev, PCI_D3hot);
1512 DRM_DEBUG_KMS("Device suspended\n");
1516 static int intel_runtime_resume(struct device *device)
1518 struct pci_dev *pdev = to_pci_dev(device);
1519 struct drm_device *dev = pci_get_drvdata(pdev);
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1523 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1526 DRM_DEBUG_KMS("Resuming device\n");
1528 intel_opregion_notify_adapter(dev, PCI_D0);
1529 dev_priv->pm.suspended = false;
1531 ret = intel_resume_prepare(dev_priv, true);
1533 * No point of rolling back things in case of an error, as the best
1534 * we can do is to hope that things will still work (and disable RPM).
1536 i915_gem_init_swizzling(dev);
1537 gen6_update_ring_freq(dev);
1539 intel_runtime_pm_enable_interrupts(dev_priv);
1540 intel_reset_gt_powersave(dev);
1543 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1545 DRM_DEBUG_KMS("Device resumed\n");
1551 * This function implements common functionality of runtime and system
1554 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1556 struct drm_device *dev = dev_priv->dev;
1559 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1560 ret = hsw_suspend_complete(dev_priv);
1561 else if (IS_VALLEYVIEW(dev))
1562 ret = vlv_suspend_complete(dev_priv);
1570 * This function implements common functionality of runtime and system
1571 * resume sequence. Variable rpm_resume used for implementing different
1574 static int intel_resume_prepare(struct drm_i915_private *dev_priv,
1577 struct drm_device *dev = dev_priv->dev;
1581 ret = snb_resume_prepare(dev_priv, rpm_resume);
1582 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1583 ret = hsw_resume_prepare(dev_priv, rpm_resume);
1584 else if (IS_VALLEYVIEW(dev))
1585 ret = vlv_resume_prepare(dev_priv, rpm_resume);
1592 static const struct dev_pm_ops i915_pm_ops = {
1593 .suspend = i915_pm_suspend,
1594 .suspend_late = i915_pm_suspend_late,
1595 .resume_early = i915_pm_resume_early,
1596 .resume = i915_pm_resume,
1597 .freeze = i915_pm_freeze,
1598 .thaw_early = i915_pm_thaw_early,
1599 .thaw = i915_pm_thaw,
1600 .poweroff = i915_pm_poweroff,
1601 .restore_early = i915_pm_resume_early,
1602 .restore = i915_pm_resume,
1603 .runtime_suspend = intel_runtime_suspend,
1604 .runtime_resume = intel_runtime_resume,
1607 static const struct vm_operations_struct i915_gem_vm_ops = {
1608 .fault = i915_gem_fault,
1609 .open = drm_gem_vm_open,
1610 .close = drm_gem_vm_close,
1613 static const struct file_operations i915_driver_fops = {
1614 .owner = THIS_MODULE,
1616 .release = drm_release,
1617 .unlocked_ioctl = drm_ioctl,
1618 .mmap = drm_gem_mmap,
1621 #ifdef CONFIG_COMPAT
1622 .compat_ioctl = i915_compat_ioctl,
1624 .llseek = noop_llseek,
1627 static struct drm_driver driver = {
1628 /* Don't use MTRRs here; the Xserver or userspace app should
1629 * deal with them for Intel hardware.
1633 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1635 .load = i915_driver_load,
1636 .unload = i915_driver_unload,
1637 .open = i915_driver_open,
1638 .lastclose = i915_driver_lastclose,
1639 .preclose = i915_driver_preclose,
1640 .postclose = i915_driver_postclose,
1641 .set_busid = drm_pci_set_busid,
1643 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1644 .suspend = i915_suspend,
1645 .resume = i915_resume_legacy,
1647 .device_is_agp = i915_driver_device_is_agp,
1648 .master_create = i915_master_create,
1649 .master_destroy = i915_master_destroy,
1650 #if defined(CONFIG_DEBUG_FS)
1651 .debugfs_init = i915_debugfs_init,
1652 .debugfs_cleanup = i915_debugfs_cleanup,
1654 .gem_free_object = i915_gem_free_object,
1655 .gem_vm_ops = &i915_gem_vm_ops,
1657 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1658 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1659 .gem_prime_export = i915_gem_prime_export,
1660 .gem_prime_import = i915_gem_prime_import,
1662 .dumb_create = i915_gem_dumb_create,
1663 .dumb_map_offset = i915_gem_mmap_gtt,
1664 .dumb_destroy = drm_gem_dumb_destroy,
1665 .ioctls = i915_ioctls,
1666 .fops = &i915_driver_fops,
1667 .name = DRIVER_NAME,
1668 .desc = DRIVER_DESC,
1669 .date = DRIVER_DATE,
1670 .major = DRIVER_MAJOR,
1671 .minor = DRIVER_MINOR,
1672 .patchlevel = DRIVER_PATCHLEVEL,
1675 static struct pci_driver i915_pci_driver = {
1676 .name = DRIVER_NAME,
1677 .id_table = pciidlist,
1678 .probe = i915_pci_probe,
1679 .remove = i915_pci_remove,
1680 .driver.pm = &i915_pm_ops,
1683 static int __init i915_init(void)
1685 driver.num_ioctls = i915_max_ioctl;
1688 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1689 * explicitly disabled with the module pararmeter.
1691 * Otherwise, just follow the parameter (defaulting to off).
1693 * Allow optional vga_text_mode_force boot option to override
1694 * the default behavior.
1696 #if defined(CONFIG_DRM_I915_KMS)
1697 if (i915.modeset != 0)
1698 driver.driver_features |= DRIVER_MODESET;
1700 if (i915.modeset == 1)
1701 driver.driver_features |= DRIVER_MODESET;
1703 #ifdef CONFIG_VGA_CONSOLE
1704 if (vgacon_text_force() && i915.modeset == -1)
1705 driver.driver_features &= ~DRIVER_MODESET;
1708 if (!(driver.driver_features & DRIVER_MODESET)) {
1709 driver.get_vblank_timestamp = NULL;
1710 #ifndef CONFIG_DRM_I915_UMS
1711 /* Silently fail loading to not upset userspace. */
1712 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1717 return drm_pci_init(&driver, &i915_pci_driver);
1720 static void __exit i915_exit(void)
1722 #ifndef CONFIG_DRM_I915_UMS
1723 if (!(driver.driver_features & DRIVER_MODESET))
1724 return; /* Never loaded a driver. */
1727 drm_pci_exit(&driver, &i915_pci_driver);
1730 module_init(i915_init);
1731 module_exit(i915_exit);
1733 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1734 MODULE_AUTHOR("Intel Corporation");
1736 MODULE_DESCRIPTION(DRIVER_DESC);
1737 MODULE_LICENSE("GPL and additional rights");