drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fpga_dbg = 1,
 307         .has_fbc = 1,
 308         GEN_DEFAULT_PIPEOFFSETS,
 309         IVB_CURSOR_OFFSETS,
 310 };
 311
 312 static const struct intel_device_info intel_broadwell_m_info = {
 313         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 314         .need_gfx_hws = 1, .has_hotplug = 1,
 315         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 316         .has_llc = 1,
 317         .has_ddi = 1,
 318         .has_fpga_dbg = 1,
 319         .has_fbc = 1,
 320         GEN_DEFAULT_PIPEOFFSETS,
 321         IVB_CURSOR_OFFSETS,
 322 };
 323
 324 static const struct intel_device_info intel_broadwell_gt3d_info = {
 325         .gen = 8, .num_pipes = 3,
 326         .need_gfx_hws = 1, .has_hotplug = 1,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328         .has_llc = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333         IVB_CURSOR_OFFSETS,
 334 };
 335
 336 static const struct intel_device_info intel_broadwell_gt3m_info = {
 337         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 338         .need_gfx_hws = 1, .has_hotplug = 1,
 339         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 340         .has_llc = 1,
 341         .has_ddi = 1,
 342         .has_fpga_dbg = 1,
 343         .has_fbc = 1,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346 };
 347
 348 static const struct intel_device_info intel_cherryview_info = {
 349         .is_preliminary = 1,
 350         .gen = 8, .num_pipes = 3,
 351         .need_gfx_hws = 1, .has_hotplug = 1,
 352         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 353         .is_valleyview = 1,
 354         .display_mmio_offset = VLV_DISPLAY_BASE,
 355         GEN_CHV_PIPEOFFSETS,
 356         CURSOR_OFFSETS,
 357 };
 358
 359 /*
 360  * Make sure any device matches here are from most specific to most
 361  * general.  For example, since the Quanta match is based on the subsystem
 362  * and subvendor IDs, we need it to come before the more general IVB
 363  * PCI ID matches, otherwise we'll use the wrong info struct above.
 364  */
 365 #define INTEL_PCI_IDS \
 366         INTEL_I830_IDS(&intel_i830_info),       \
 367         INTEL_I845G_IDS(&intel_845g_info),      \
 368         INTEL_I85X_IDS(&intel_i85x_info),       \
 369         INTEL_I865G_IDS(&intel_i865g_info),     \
 370         INTEL_I915G_IDS(&intel_i915g_info),     \
 371         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 372         INTEL_I945G_IDS(&intel_i945g_info),     \
 373         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 374         INTEL_I965G_IDS(&intel_i965g_info),     \
 375         INTEL_G33_IDS(&intel_g33_info),         \
 376         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 377         INTEL_GM45_IDS(&intel_gm45_info),       \
 378         INTEL_G45_IDS(&intel_g45_info),         \
 379         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 380         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 381         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 382         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 383         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 384         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 385         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 386         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 387         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 388         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 389         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 390         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 391         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 392         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 393         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 394         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 395         INTEL_CHV_IDS(&intel_cherryview_info)
 396
 397 static const struct pci_device_id pciidlist[] = {               /* aka */
 398         INTEL_PCI_IDS,
 399         {0, 0, 0}
 400 };
 401
 402 #if defined(CONFIG_DRM_I915_KMS)
 403 MODULE_DEVICE_TABLE(pci, pciidlist);
 404 #endif
 405
 406 void intel_detect_pch(struct drm_device *dev)
 407 {
 408         struct drm_i915_private *dev_priv = dev->dev_private;
 409         struct pci_dev *pch = NULL;
 410
 411         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 412          * (which really amounts to a PCH but no South Display).
 413          */
 414         if (INTEL_INFO(dev)->num_pipes == 0) {
 415                 dev_priv->pch_type = PCH_NOP;
 416                 return;
 417         }
 418
 419         /*
 420          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 421          * make graphics device passthrough work easy for VMM, that only
 422          * need to expose ISA bridge to let driver know the real hardware
 423          * underneath. This is a requirement from virtualization team.
 424          *
 425          * In some virtualized environments (e.g. XEN), there is irrelevant
 426          * ISA bridge in the system. To work reliably, we should scan trhough
 427          * all the ISA bridge devices and check for the first match, instead
 428          * of only checking the first one.
 429          */
 430         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 431                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 432                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 433                         dev_priv->pch_id = id;
 434
 435                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 436                                 dev_priv->pch_type = PCH_IBX;
 437                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 438                                 WARN_ON(!IS_GEN5(dev));
 439                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 440                                 dev_priv->pch_type = PCH_CPT;
 441                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 442                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 443                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 444                                 /* PantherPoint is CPT compatible */
 445                                 dev_priv->pch_type = PCH_CPT;
 446                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 447                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 448                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 449                                 dev_priv->pch_type = PCH_LPT;
 450                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 451                                 WARN_ON(!IS_HASWELL(dev));
 452                                 WARN_ON(IS_ULT(dev));
 453                         } else if (IS_BROADWELL(dev)) {
 454                                 dev_priv->pch_type = PCH_LPT;
 455                                 dev_priv->pch_id =
 456                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 457                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 458                                               "LynxPoint LP PCH\n");
 459                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 460                                 dev_priv->pch_type = PCH_LPT;
 461                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 462                                 WARN_ON(!IS_HASWELL(dev));
 463                                 WARN_ON(!IS_ULT(dev));
 464                         } else
 465                                 continue;
 466
 467                         break;
 468                 }
 469         }
 470         if (!pch)
 471                 DRM_DEBUG_KMS("No PCH found.\n");
 472
 473         pci_dev_put(pch);
 474 }
 475
 476 bool i915_semaphore_is_enabled(struct drm_device *dev)
 477 {
 478         if (INTEL_INFO(dev)->gen < 6)
 479                 return false;
 480
 481         if (i915.semaphores >= 0)
 482                 return i915.semaphores;
 483
 484         /* TODO: make semaphores and Execlists play nicely together */
 485         if (i915.enable_execlists)
 486                 return false;
 487
 488         /* Until we get further testing... */
 489         if (IS_GEN8(dev))
 490                 return false;
 491
 492 #ifdef CONFIG_INTEL_IOMMU
 493         /* Enable semaphores on SNB when IO remapping is off */
 494         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 495                 return false;
 496 #endif
 497
 498         return true;
 499 }
 500
 501 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
 502 {
 503         spin_lock_irq(&dev_priv->irq_lock);
 504
 505         dev_priv->long_hpd_port_mask = 0;
 506         dev_priv->short_hpd_port_mask = 0;
 507         dev_priv->hpd_event_bits = 0;
 508
 509         spin_unlock_irq(&dev_priv->irq_lock);
 510
 511         cancel_work_sync(&dev_priv->dig_port_work);
 512         cancel_work_sync(&dev_priv->hotplug_work);
 513         cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
 514 }
 515
 516 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 517 {
 518         struct drm_device *dev = dev_priv->dev;
 519         struct drm_encoder *encoder;
 520
 521         drm_modeset_lock_all(dev);
 522         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 523                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 524
 525                 if (intel_encoder->suspend)
 526                         intel_encoder->suspend(intel_encoder);
 527         }
 528         drm_modeset_unlock_all(dev);
 529 }
 530
 531 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 532 static int intel_resume_prepare(struct drm_i915_private *dev_priv,
 533                                 bool rpm_resume);
 534
 535 static int i915_drm_freeze(struct drm_device *dev)
 536 {
 537         struct drm_i915_private *dev_priv = dev->dev_private;
 538         struct drm_crtc *crtc;
 539         pci_power_t opregion_target_state;
 540
 541         /* ignore lid events during suspend */
 542         mutex_lock(&dev_priv->modeset_restore_lock);
 543         dev_priv->modeset_restore = MODESET_SUSPENDED;
 544         mutex_unlock(&dev_priv->modeset_restore_lock);
 545
 546         /* We do a lot of poking in a lot of registers, make sure they work
 547          * properly. */
 548         intel_display_set_init_power(dev_priv, true);
 549
 550         drm_kms_helper_poll_disable(dev);
 551
 552         pci_save_state(dev->pdev);
 553
 554         /* If KMS is active, we do the leavevt stuff here */
 555         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 556                 int error;
 557
 558                 error = i915_gem_suspend(dev);
 559                 if (error) {
 560                         dev_err(&dev->pdev->dev,
 561                                 "GEM idle failed, resume might fail\n");
 562                         return error;
 563                 }
 564
 565                 /*
 566                  * Disable CRTCs directly since we want to preserve sw state
 567                  * for _thaw. Also, power gate the CRTC power wells.
 568                  */
 569                 drm_modeset_lock_all(dev);
 570                 for_each_crtc(dev, crtc)
 571                         intel_crtc_control(crtc, false);
 572                 drm_modeset_unlock_all(dev);
 573
 574                 intel_dp_mst_suspend(dev);
 575
 576                 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
 577
 578                 intel_runtime_pm_disable_interrupts(dev);
 579                 intel_hpd_cancel_work(dev_priv);
 580
 581                 intel_suspend_encoders(dev_priv);
 582
 583                 intel_suspend_gt_powersave(dev);
 584
 585                 intel_modeset_suspend_hw(dev);
 586         }
 587
 588         i915_gem_suspend_gtt_mappings(dev);
 589
 590         i915_save_state(dev);
 591
 592         opregion_target_state = PCI_D3cold;
 593 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 594         if (acpi_target_system_state() < ACPI_STATE_S3)
 595                 opregion_target_state = PCI_D1;
 596 #endif
 597         intel_opregion_notify_adapter(dev, opregion_target_state);
 598
 599         intel_uncore_forcewake_reset(dev, false);
 600         intel_opregion_fini(dev);
 601
 602         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 603
 604         dev_priv->suspend_count++;
 605
 606         intel_display_set_init_power(dev_priv, false);
 607
 608         return 0;
 609 }
 610
 611 int i915_suspend(struct drm_device *dev, pm_message_t state)
 612 {
 613         int error;
 614
 615         if (!dev || !dev->dev_private) {
 616                 DRM_ERROR("dev: %p\n", dev);
 617                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 618                 return -ENODEV;
 619         }
 620
 621         if (state.event == PM_EVENT_PRETHAW)
 622                 return 0;
 623
 624
 625         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 626                 return 0;
 627
 628         error = i915_drm_freeze(dev);
 629         if (error)
 630                 return error;
 631
 632         if (state.event == PM_EVENT_SUSPEND) {
 633                 /* Shut down the device */
 634                 pci_disable_device(dev->pdev);
 635                 pci_set_power_state(dev->pdev, PCI_D3hot);
 636         }
 637
 638         return 0;
 639 }
 640
 641 static int i915_drm_thaw_early(struct drm_device *dev)
 642 {
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         int ret;
 645
 646         ret = intel_resume_prepare(dev_priv, false);
 647         if (ret)
 648                 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
 649
 650         intel_uncore_early_sanitize(dev, true);
 651         intel_uncore_sanitize(dev);
 652         intel_power_domains_init_hw(dev_priv);
 653
 654         return ret;
 655 }
 656
 657 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 658 {
 659         struct drm_i915_private *dev_priv = dev->dev_private;
 660
 661         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 662             restore_gtt_mappings) {
 663                 mutex_lock(&dev->struct_mutex);
 664                 i915_gem_restore_gtt_mappings(dev);
 665                 mutex_unlock(&dev->struct_mutex);
 666         }
 667
 668         i915_restore_state(dev);
 669         intel_opregion_setup(dev);
 670
 671         /* KMS EnterVT equivalent */
 672         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 673                 intel_init_pch_refclk(dev);
 674                 drm_mode_config_reset(dev);
 675
 676                 mutex_lock(&dev->struct_mutex);
 677                 if (i915_gem_init_hw(dev)) {
 678                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 679                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 680                 }
 681                 mutex_unlock(&dev->struct_mutex);
 682
 683                 intel_runtime_pm_restore_interrupts(dev);
 684
 685                 intel_modeset_init_hw(dev);
 686
 687                 {
 688                         unsigned long irqflags;
 689                         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 690                         if (dev_priv->display.hpd_irq_setup)
 691                                 dev_priv->display.hpd_irq_setup(dev);
 692                         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 693                 }
 694
 695                 intel_dp_mst_resume(dev);
 696                 drm_modeset_lock_all(dev);
 697                 intel_modeset_setup_hw_state(dev, true);
 698                 drm_modeset_unlock_all(dev);
 699
 700                 /*
 701                  * ... but also need to make sure that hotplug processing
 702                  * doesn't cause havoc. Like in the driver load code we don't
 703                  * bother with the tiny race here where we might loose hotplug
 704                  * notifications.
 705                  * */
 706                 intel_hpd_init(dev);
 707                 /* Config may have changed between suspend and resume */
 708                 drm_helper_hpd_irq_event(dev);
 709         }
 710
 711         intel_opregion_init(dev);
 712
 713         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 714
 715         mutex_lock(&dev_priv->modeset_restore_lock);
 716         dev_priv->modeset_restore = MODESET_DONE;
 717         mutex_unlock(&dev_priv->modeset_restore_lock);
 718
 719         intel_opregion_notify_adapter(dev, PCI_D0);
 720
 721         return 0;
 722 }
 723
 724 static int i915_drm_thaw(struct drm_device *dev)
 725 {
 726         if (drm_core_check_feature(dev, DRIVER_MODESET))
 727                 i915_check_and_clear_faults(dev);
 728
 729         return __i915_drm_thaw(dev, true);
 730 }
 731
 732 static int i915_resume_early(struct drm_device *dev)
 733 {
 734         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 735                 return 0;
 736
 737         /*
 738          * We have a resume ordering issue with the snd-hda driver also
 739          * requiring our device to be power up. Due to the lack of a
 740          * parent/child relationship we currently solve this with an early
 741          * resume hook.
 742          *
 743          * FIXME: This should be solved with a special hdmi sink device or
 744          * similar so that power domains can be employed.
 745          */
 746         if (pci_enable_device(dev->pdev))
 747                 return -EIO;
 748
 749         pci_set_master(dev->pdev);
 750
 751         return i915_drm_thaw_early(dev);
 752 }
 753
 754 int i915_resume(struct drm_device *dev)
 755 {
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         int ret;
 758
 759         /*
 760          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 761          * earlier) need to restore the GTT mappings since the BIOS might clear
 762          * all our scratch PTEs.
 763          */
 764         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 765         if (ret)
 766                 return ret;
 767
 768         drm_kms_helper_poll_enable(dev);
 769         return 0;
 770 }
 771
 772 static int i915_resume_legacy(struct drm_device *dev)
 773 {
 774         i915_resume_early(dev);
 775         i915_resume(dev);
 776
 777         return 0;
 778 }
 779
 780 /**
 781  * i915_reset - reset chip after a hang
 782  * @dev: drm device to reset
 783  *
 784  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 785  * reset or otherwise an error code.
 786  *
 787  * Procedure is fairly simple:
 788  *   - reset the chip using the reset reg
 789  *   - re-init context state
 790  *   - re-init hardware status page
 791  *   - re-init ring buffer
 792  *   - re-init interrupt state
 793  *   - re-init display
 794  */
 795 int i915_reset(struct drm_device *dev)
 796 {
 797         struct drm_i915_private *dev_priv = dev->dev_private;
 798         bool simulated;
 799         int ret;
 800
 801         if (!i915.reset)
 802                 return 0;
 803
 804         mutex_lock(&dev->struct_mutex);
 805
 806         i915_gem_reset(dev);
 807
 808         simulated = dev_priv->gpu_error.stop_rings != 0;
 809
 810         ret = intel_gpu_reset(dev);
 811
 812         /* Also reset the gpu hangman. */
 813         if (simulated) {
 814                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 815                 dev_priv->gpu_error.stop_rings = 0;
 816                 if (ret == -ENODEV) {
 817                         DRM_INFO("Reset not implemented, but ignoring "
 818                                  "error for simulated gpu hangs\n");
 819                         ret = 0;
 820                 }
 821         }
 822
 823         if (ret) {
 824                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 825                 mutex_unlock(&dev->struct_mutex);
 826                 return ret;
 827         }
 828
 829         /* Ok, now get things going again... */
 830
 831         /*
 832          * Everything depends on having the GTT running, so we need to start
 833          * there.  Fortunately we don't need to do this unless we reset the
 834          * chip at a PCI level.
 835          *
 836          * Next we need to restore the context, but we don't use those
 837          * yet either...
 838          *
 839          * Ring buffer needs to be re-initialized in the KMS case, or if X
 840          * was running at the time of the reset (i.e. we weren't VT
 841          * switched away).
 842          */
 843         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 844                         !dev_priv->ums.mm_suspended) {
 845                 dev_priv->ums.mm_suspended = 0;
 846
 847                 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 848                 dev_priv->gpu_error.reload_in_reset = true;
 849
 850                 ret = i915_gem_init_hw(dev);
 851
 852                 dev_priv->gpu_error.reload_in_reset = false;
 853
 854                 mutex_unlock(&dev->struct_mutex);
 855                 if (ret) {
 856                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 857                         return ret;
 858                 }
 859
 860                 /*
 861                  * FIXME: This races pretty badly against concurrent holders of
 862                  * ring interrupts. This is possible since we've started to drop
 863                  * dev->struct_mutex in select places when waiting for the gpu.
 864                  */
 865
 866                 /*
 867                  * rps/rc6 re-init is necessary to restore state lost after the
 868                  * reset and the re-install of gt irqs. Skip for ironlake per
 869                  * previous concerns that it doesn't respond well to some forms
 870                  * of re-init after reset.
 871                  */
 872                 if (INTEL_INFO(dev)->gen > 5)
 873                         intel_reset_gt_powersave(dev);
 874         } else {
 875                 mutex_unlock(&dev->struct_mutex);
 876         }
 877
 878         return 0;
 879 }
 880
 881 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 882 {
 883         struct intel_device_info *intel_info =
 884                 (struct intel_device_info *) ent->driver_data;
 885
 886         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 887                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 888                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 889                 return -ENODEV;
 890         }
 891
 892         /* Only bind to function 0 of the device. Early generations
 893          * used function 1 as a placeholder for multi-head. This causes
 894          * us confusion instead, especially on the systems where both
 895          * functions have the same PCI-ID!
 896          */
 897         if (PCI_FUNC(pdev->devfn))
 898                 return -ENODEV;
 899
 900         driver.driver_features &= ~(DRIVER_USE_AGP);
 901
 902         return drm_get_pci_dev(pdev, ent, &driver);
 903 }
 904
 905 static void
 906 i915_pci_remove(struct pci_dev *pdev)
 907 {
 908         struct drm_device *dev = pci_get_drvdata(pdev);
 909
 910         drm_put_dev(dev);
 911 }
 912
 913 static int i915_pm_suspend(struct device *dev)
 914 {
 915         struct pci_dev *pdev = to_pci_dev(dev);
 916         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 917
 918         if (!drm_dev || !drm_dev->dev_private) {
 919                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 920                 return -ENODEV;
 921         }
 922
 923         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 924                 return 0;
 925
 926         return i915_drm_freeze(drm_dev);
 927 }
 928
 929 static int i915_pm_suspend_late(struct device *dev)
 930 {
 931         struct pci_dev *pdev = to_pci_dev(dev);
 932         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 933         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 934         int ret;
 935
 936         /*
 937          * We have a suspedn ordering issue with the snd-hda driver also
 938          * requiring our device to be power up. Due to the lack of a
 939          * parent/child relationship we currently solve this with an late
 940          * suspend hook.
 941          *
 942          * FIXME: This should be solved with a special hdmi sink device or
 943          * similar so that power domains can be employed.
 944          */
 945         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 946                 return 0;
 947
 948         ret = intel_suspend_complete(dev_priv);
 949
 950         if (ret)
 951                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 952         else {
 953                 pci_disable_device(pdev);
 954                 pci_set_power_state(pdev, PCI_D3hot);
 955         }
 956
 957         return ret;
 958 }
 959
 960 static int i915_pm_resume_early(struct device *dev)
 961 {
 962         struct pci_dev *pdev = to_pci_dev(dev);
 963         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 964
 965         return i915_resume_early(drm_dev);
 966 }
 967
 968 static int i915_pm_resume(struct device *dev)
 969 {
 970         struct pci_dev *pdev = to_pci_dev(dev);
 971         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 972
 973         return i915_resume(drm_dev);
 974 }
 975
 976 static int i915_pm_freeze(struct device *dev)
 977 {
 978         struct pci_dev *pdev = to_pci_dev(dev);
 979         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 980
 981         if (!drm_dev || !drm_dev->dev_private) {
 982                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 983                 return -ENODEV;
 984         }
 985
 986         return i915_drm_freeze(drm_dev);
 987 }
 988
 989 static int i915_pm_freeze_late(struct device *dev)
 990 {
 991         struct pci_dev *pdev = to_pci_dev(dev);
 992         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 993         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 994
 995         return intel_suspend_complete(dev_priv);
 996 }
 997
 998 static int i915_pm_thaw_early(struct device *dev)
 999 {
1000         struct pci_dev *pdev = to_pci_dev(dev);
1001         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1002
1003         return i915_drm_thaw_early(drm_dev);
1004 }
1005
1006 static int i915_pm_thaw(struct device *dev)
1007 {
1008         struct pci_dev *pdev = to_pci_dev(dev);
1009         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1010
1011         return i915_drm_thaw(drm_dev);
1012 }
1013
1014 static int i915_pm_poweroff(struct device *dev)
1015 {
1016         struct pci_dev *pdev = to_pci_dev(dev);
1017         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1018
1019         return i915_drm_freeze(drm_dev);
1020 }
1021
1022 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1023 {
1024         hsw_enable_pc8(dev_priv);
1025
1026         return 0;
1027 }
1028
1029 static int snb_resume_prepare(struct drm_i915_private *dev_priv,
1030                                 bool rpm_resume)
1031 {
1032         struct drm_device *dev = dev_priv->dev;
1033
1034         if (rpm_resume)
1035                 intel_init_pch_refclk(dev);
1036
1037         return 0;
1038 }
1039
1040 static int hsw_resume_prepare(struct drm_i915_private *dev_priv,
1041                                 bool rpm_resume)
1042 {
1043         hsw_disable_pc8(dev_priv);
1044
1045         return 0;
1046 }
1047
1048 /*
1049  * Save all Gunit registers that may be lost after a D3 and a subsequent
1050  * S0i[R123] transition. The list of registers needing a save/restore is
1051  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1052  * registers in the following way:
1053  * - Driver: saved/restored by the driver
1054  * - Punit : saved/restored by the Punit firmware
1055  * - No, w/o marking: no need to save/restore, since the register is R/O or
1056  *                    used internally by the HW in a way that doesn't depend
1057  *                    keeping the content across a suspend/resume.
1058  * - Debug : used for debugging
1059  *
1060  * We save/restore all registers marked with 'Driver', with the following
1061  * exceptions:
1062  * - Registers out of use, including also registers marked with 'Debug'.
1063  *   These have no effect on the driver's operation, so we don't save/restore
1064  *   them to reduce the overhead.
1065  * - Registers that are fully setup by an initialization function called from
1066  *   the resume path. For example many clock gating and RPS/RC6 registers.
1067  * - Registers that provide the right functionality with their reset defaults.
1068  *
1069  * TODO: Except for registers that based on the above 3 criteria can be safely
1070  * ignored, we save/restore all others, practically treating the HW context as
1071  * a black-box for the driver. Further investigation is needed to reduce the
1072  * saved/restored registers even further, by following the same 3 criteria.
1073  */
1074 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1075 {
1076         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1077         int i;
1078
1079         /* GAM 0x4000-0x4770 */
1080         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1081         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1082         s->arb_mode             = I915_READ(ARB_MODE);
1083         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1084         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1085
1086         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1087                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1088
1089         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1090         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1091
1092         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1093         s->ecochk               = I915_READ(GAM_ECOCHK);
1094         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1095         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1096
1097         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1098
1099         /* MBC 0x9024-0x91D0, 0x8500 */
1100         s->g3dctl               = I915_READ(VLV_G3DCTL);
1101         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1102         s->mbctl                = I915_READ(GEN6_MBCTL);
1103
1104         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1105         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1106         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1107         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1108         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1109         s->rstctl               = I915_READ(GEN6_RSTCTL);
1110         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1111
1112         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1113         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1114         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1115         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1116         s->ecobus               = I915_READ(ECOBUS);
1117         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1118         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1119         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1120         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1121         s->rcedata              = I915_READ(VLV_RCEDATA);
1122         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1123
1124         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1125         s->gt_imr               = I915_READ(GTIMR);
1126         s->gt_ier               = I915_READ(GTIER);
1127         s->pm_imr               = I915_READ(GEN6_PMIMR);
1128         s->pm_ier               = I915_READ(GEN6_PMIER);
1129
1130         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1131                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1132
1133         /* GT SA CZ domain, 0x100000-0x138124 */
1134         s->tilectl              = I915_READ(TILECTL);
1135         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1136         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1137         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1138         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1139
1140         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1141         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1142         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1143         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1144
1145         /*
1146          * Not saving any of:
1147          * DFT,         0x9800-0x9EC0
1148          * SARB,        0xB000-0xB1FC
1149          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1150          * PCI CFG
1151          */
1152 }
1153
1154 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1155 {
1156         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1157         u32 val;
1158         int i;
1159
1160         /* GAM 0x4000-0x4770 */
1161         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1162         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1163         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1164         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1165         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1166
1167         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1168                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1169
1170         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1171         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1172
1173         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1174         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1175         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1176         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1177
1178         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1179
1180         /* MBC 0x9024-0x91D0, 0x8500 */
1181         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1182         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1183         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1184
1185         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1186         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1187         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1188         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1189         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1190         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1191         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1192
1193         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1194         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1195         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1196         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1197         I915_WRITE(ECOBUS,              s->ecobus);
1198         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1199         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1200         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1201         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1202         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1203         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1204
1205         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1206         I915_WRITE(GTIMR,               s->gt_imr);
1207         I915_WRITE(GTIER,               s->gt_ier);
1208         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1209         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1210
1211         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1212                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1213
1214         /* GT SA CZ domain, 0x100000-0x138124 */
1215         I915_WRITE(TILECTL,                     s->tilectl);
1216         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1217         /*
1218          * Preserve the GT allow wake and GFX force clock bit, they are not
1219          * be restored, as they are used to control the s0ix suspend/resume
1220          * sequence by the caller.
1221          */
1222         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1223         val &= VLV_GTLC_ALLOWWAKEREQ;
1224         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1225         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1226
1227         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1228         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1229         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1230         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1231
1232         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1233
1234         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1235         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1236         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1237         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1238 }
1239
1240 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1241 {
1242         u32 val;
1243         int err;
1244
1245         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1246         WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1247
1248 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1249         /* Wait for a previous force-off to settle */
1250         if (force_on) {
1251                 err = wait_for(!COND, 20);
1252                 if (err) {
1253                         DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1254                                   I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1255                         return err;
1256                 }
1257         }
1258
1259         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1260         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1261         if (force_on)
1262                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1263         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1264
1265         if (!force_on)
1266                 return 0;
1267
1268         err = wait_for(COND, 20);
1269         if (err)
1270                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1271                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1272
1273         return err;
1274 #undef COND
1275 }
1276
1277 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1278 {
1279         u32 val;
1280         int err = 0;
1281
1282         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1283         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1284         if (allow)
1285                 val |= VLV_GTLC_ALLOWWAKEREQ;
1286         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1287         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1288
1289 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1290               allow)
1291         err = wait_for(COND, 1);
1292         if (err)
1293                 DRM_ERROR("timeout disabling GT waking\n");
1294         return err;
1295 #undef COND
1296 }
1297
1298 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1299                                  bool wait_for_on)
1300 {
1301         u32 mask;
1302         u32 val;
1303         int err;
1304
1305         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1306         val = wait_for_on ? mask : 0;
1307 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1308         if (COND)
1309                 return 0;
1310
1311         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1312                         wait_for_on ? "on" : "off",
1313                         I915_READ(VLV_GTLC_PW_STATUS));
1314
1315         /*
1316          * RC6 transitioning can be delayed up to 2 msec (see
1317          * valleyview_enable_rps), use 3 msec for safety.
1318          */
1319         err = wait_for(COND, 3);
1320         if (err)
1321                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1322                           wait_for_on ? "on" : "off");
1323
1324         return err;
1325 #undef COND
1326 }
1327
1328 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1329 {
1330         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1331                 return;
1332
1333         DRM_ERROR("GT register access while GT waking disabled\n");
1334         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1335 }
1336
1337 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1338 {
1339         u32 mask;
1340         int err;
1341
1342         /*
1343          * Bspec defines the following GT well on flags as debug only, so
1344          * don't treat them as hard failures.
1345          */
1346         (void)vlv_wait_for_gt_wells(dev_priv, false);
1347
1348         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1349         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1350
1351         vlv_check_no_gt_access(dev_priv);
1352
1353         err = vlv_force_gfx_clock(dev_priv, true);
1354         if (err)
1355                 goto err1;
1356
1357         err = vlv_allow_gt_wake(dev_priv, false);
1358         if (err)
1359                 goto err2;
1360         vlv_save_gunit_s0ix_state(dev_priv);
1361
1362         err = vlv_force_gfx_clock(dev_priv, false);
1363         if (err)
1364                 goto err2;
1365
1366         return 0;
1367
1368 err2:
1369         /* For safety always re-enable waking and disable gfx clock forcing */
1370         vlv_allow_gt_wake(dev_priv, true);
1371 err1:
1372         vlv_force_gfx_clock(dev_priv, false);
1373
1374         return err;
1375 }
1376
1377 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1378                                 bool rpm_resume)
1379 {
1380         struct drm_device *dev = dev_priv->dev;
1381         int err;
1382         int ret;
1383
1384         /*
1385          * If any of the steps fail just try to continue, that's the best we
1386          * can do at this point. Return the first error code (which will also
1387          * leave RPM permanently disabled).
1388          */
1389         ret = vlv_force_gfx_clock(dev_priv, true);
1390
1391         vlv_restore_gunit_s0ix_state(dev_priv);
1392
1393         err = vlv_allow_gt_wake(dev_priv, true);
1394         if (!ret)
1395                 ret = err;
1396
1397         err = vlv_force_gfx_clock(dev_priv, false);
1398         if (!ret)
1399                 ret = err;
1400
1401         vlv_check_no_gt_access(dev_priv);
1402
1403         if (rpm_resume) {
1404                 intel_init_clock_gating(dev);
1405                 i915_gem_restore_fences(dev);
1406         }
1407
1408         return ret;
1409 }
1410
1411 static int intel_runtime_suspend(struct device *device)
1412 {
1413         struct pci_dev *pdev = to_pci_dev(device);
1414         struct drm_device *dev = pci_get_drvdata(pdev);
1415         struct drm_i915_private *dev_priv = dev->dev_private;
1416         int ret;
1417
1418         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1419                 return -ENODEV;
1420
1421         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1422                 return -ENODEV;
1423
1424         assert_force_wake_inactive(dev_priv);
1425
1426         DRM_DEBUG_KMS("Suspending device\n");
1427
1428         /*
1429          * We could deadlock here in case another thread holding struct_mutex
1430          * calls RPM suspend concurrently, since the RPM suspend will wait
1431          * first for this RPM suspend to finish. In this case the concurrent
1432          * RPM resume will be followed by its RPM suspend counterpart. Still
1433          * for consistency return -EAGAIN, which will reschedule this suspend.
1434          */
1435         if (!mutex_trylock(&dev->struct_mutex)) {
1436                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1437                 /*
1438                  * Bump the expiration timestamp, otherwise the suspend won't
1439                  * be rescheduled.
1440                  */
1441                 pm_runtime_mark_last_busy(device);
1442
1443                 return -EAGAIN;
1444         }
1445         /*
1446          * We are safe here against re-faults, since the fault handler takes
1447          * an RPM reference.
1448          */
1449         i915_gem_release_all_mmaps(dev_priv);
1450         mutex_unlock(&dev->struct_mutex);
1451
1452         /*
1453          * rps.work can't be rearmed here, since we get here only after making
1454          * sure the GPU is idle and the RPS freq is set to the minimum. See
1455          * intel_mark_idle().
1456          */
1457         cancel_work_sync(&dev_priv->rps.work);
1458         intel_runtime_pm_disable_interrupts(dev);
1459
1460         ret = intel_suspend_complete(dev_priv);
1461         if (ret) {
1462                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1463                 intel_runtime_pm_restore_interrupts(dev);
1464
1465                 return ret;
1466         }
1467
1468         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1469         dev_priv->pm.suspended = true;
1470
1471         /*
1472          * FIXME: We really should find a document that references the arguments
1473          * used below!
1474          */
1475         if (IS_HASWELL(dev)) {
1476                 /*
1477                  * current versions of firmware which depend on this opregion
1478                  * notification have repurposed the D1 definition to mean
1479                  * "runtime suspended" vs. what you would normally expect (D3)
1480                  * to distinguish it from notifications that might be sent via
1481                  * the suspend path.
1482                  */
1483                 intel_opregion_notify_adapter(dev, PCI_D1);
1484         } else {
1485                 /*
1486                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1487                  * being detected, and the call we do at intel_runtime_resume()
1488                  * won't be able to restore them. Since PCI_D3hot matches the
1489                  * actual specification and appears to be working, use it. Let's
1490                  * assume the other non-Haswell platforms will stay the same as
1491                  * Broadwell.
1492                  */
1493                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1494         }
1495
1496         DRM_DEBUG_KMS("Device suspended\n");
1497         return 0;
1498 }
1499
1500 static int intel_runtime_resume(struct device *device)
1501 {
1502         struct pci_dev *pdev = to_pci_dev(device);
1503         struct drm_device *dev = pci_get_drvdata(pdev);
1504         struct drm_i915_private *dev_priv = dev->dev_private;
1505         int ret;
1506
1507         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1508                 return -ENODEV;
1509
1510         DRM_DEBUG_KMS("Resuming device\n");
1511
1512         intel_opregion_notify_adapter(dev, PCI_D0);
1513         dev_priv->pm.suspended = false;
1514
1515         ret = intel_resume_prepare(dev_priv, true);
1516         /*
1517          * No point of rolling back things in case of an error, as the best
1518          * we can do is to hope that things will still work (and disable RPM).
1519          */
1520         i915_gem_init_swizzling(dev);
1521         gen6_update_ring_freq(dev);
1522
1523         intel_runtime_pm_restore_interrupts(dev);
1524         intel_reset_gt_powersave(dev);
1525
1526         if (ret)
1527                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1528         else
1529                 DRM_DEBUG_KMS("Device resumed\n");
1530
1531         return ret;
1532 }
1533
1534 /*
1535  * This function implements common functionality of runtime and system
1536  * suspend sequence.
1537  */
1538 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1539 {
1540         struct drm_device *dev = dev_priv->dev;
1541         int ret;
1542
1543         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1544                 ret = hsw_suspend_complete(dev_priv);
1545         else if (IS_VALLEYVIEW(dev))
1546                 ret = vlv_suspend_complete(dev_priv);
1547         else
1548                 ret = 0;
1549
1550         return ret;
1551 }
1552
1553 /*
1554  * This function implements common functionality of runtime and system
1555  * resume sequence. Variable rpm_resume used for implementing different
1556  * code paths.
1557  */
1558 static int intel_resume_prepare(struct drm_i915_private *dev_priv,
1559                                 bool rpm_resume)
1560 {
1561         struct drm_device *dev = dev_priv->dev;
1562         int ret;
1563
1564         if (IS_GEN6(dev))
1565                 ret = snb_resume_prepare(dev_priv, rpm_resume);
1566         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1567                 ret = hsw_resume_prepare(dev_priv, rpm_resume);
1568         else if (IS_VALLEYVIEW(dev))
1569                 ret = vlv_resume_prepare(dev_priv, rpm_resume);
1570         else
1571                 ret = 0;
1572
1573         return ret;
1574 }
1575
1576 static const struct dev_pm_ops i915_pm_ops = {
1577         .suspend = i915_pm_suspend,
1578         .suspend_late = i915_pm_suspend_late,
1579         .resume_early = i915_pm_resume_early,
1580         .resume = i915_pm_resume,
1581         .freeze = i915_pm_freeze,
1582         .freeze_late = i915_pm_freeze_late,
1583         .thaw_early = i915_pm_thaw_early,
1584         .thaw = i915_pm_thaw,
1585         .poweroff = i915_pm_poweroff,
1586         .restore_early = i915_pm_resume_early,
1587         .restore = i915_pm_resume,
1588         .runtime_suspend = intel_runtime_suspend,
1589         .runtime_resume = intel_runtime_resume,
1590 };
1591
1592 static const struct vm_operations_struct i915_gem_vm_ops = {
1593         .fault = i915_gem_fault,
1594         .open = drm_gem_vm_open,
1595         .close = drm_gem_vm_close,
1596 };
1597
1598 static const struct file_operations i915_driver_fops = {
1599         .owner = THIS_MODULE,
1600         .open = drm_open,
1601         .release = drm_release,
1602         .unlocked_ioctl = drm_ioctl,
1603         .mmap = drm_gem_mmap,
1604         .poll = drm_poll,
1605         .read = drm_read,
1606 #ifdef CONFIG_COMPAT
1607         .compat_ioctl = i915_compat_ioctl,
1608 #endif
1609         .llseek = noop_llseek,
1610 };
1611
1612 static struct drm_driver driver = {
1613         /* Don't use MTRRs here; the Xserver or userspace app should
1614          * deal with them for Intel hardware.
1615          */
1616         .driver_features =
1617             DRIVER_USE_AGP |
1618             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1619             DRIVER_RENDER,
1620         .load = i915_driver_load,
1621         .unload = i915_driver_unload,
1622         .open = i915_driver_open,
1623         .lastclose = i915_driver_lastclose,
1624         .preclose = i915_driver_preclose,
1625         .postclose = i915_driver_postclose,
1626         .set_busid = drm_pci_set_busid,
1627
1628         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1629         .suspend = i915_suspend,
1630         .resume = i915_resume_legacy,
1631
1632         .device_is_agp = i915_driver_device_is_agp,
1633         .master_create = i915_master_create,
1634         .master_destroy = i915_master_destroy,
1635 #if defined(CONFIG_DEBUG_FS)
1636         .debugfs_init = i915_debugfs_init,
1637         .debugfs_cleanup = i915_debugfs_cleanup,
1638 #endif
1639         .gem_free_object = i915_gem_free_object,
1640         .gem_vm_ops = &i915_gem_vm_ops,
1641
1642         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1643         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1644         .gem_prime_export = i915_gem_prime_export,
1645         .gem_prime_import = i915_gem_prime_import,
1646
1647         .dumb_create = i915_gem_dumb_create,
1648         .dumb_map_offset = i915_gem_mmap_gtt,
1649         .dumb_destroy = drm_gem_dumb_destroy,
1650         .ioctls = i915_ioctls,
1651         .fops = &i915_driver_fops,
1652         .name = DRIVER_NAME,
1653         .desc = DRIVER_DESC,
1654         .date = DRIVER_DATE,
1655         .major = DRIVER_MAJOR,
1656         .minor = DRIVER_MINOR,
1657         .patchlevel = DRIVER_PATCHLEVEL,
1658 };
1659
1660 static struct pci_driver i915_pci_driver = {
1661         .name = DRIVER_NAME,
1662         .id_table = pciidlist,
1663         .probe = i915_pci_probe,
1664         .remove = i915_pci_remove,
1665         .driver.pm = &i915_pm_ops,
1666 };
1667
1668 static int __init i915_init(void)
1669 {
1670         driver.num_ioctls = i915_max_ioctl;
1671
1672         /*
1673          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1674          * explicitly disabled with the module pararmeter.
1675          *
1676          * Otherwise, just follow the parameter (defaulting to off).
1677          *
1678          * Allow optional vga_text_mode_force boot option to override
1679          * the default behavior.
1680          */
1681 #if defined(CONFIG_DRM_I915_KMS)
1682         if (i915.modeset != 0)
1683                 driver.driver_features |= DRIVER_MODESET;
1684 #endif
1685         if (i915.modeset == 1)
1686                 driver.driver_features |= DRIVER_MODESET;
1687
1688 #ifdef CONFIG_VGA_CONSOLE
1689         if (vgacon_text_force() && i915.modeset == -1)
1690                 driver.driver_features &= ~DRIVER_MODESET;
1691 #endif
1692
1693         if (!(driver.driver_features & DRIVER_MODESET)) {
1694                 driver.get_vblank_timestamp = NULL;
1695 #ifndef CONFIG_DRM_I915_UMS
1696                 /* Silently fail loading to not upset userspace. */
1697                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1698                 return 0;
1699 #endif
1700         }
1701
1702         return drm_pci_init(&driver, &i915_pci_driver);
1703 }
1704
1705 static void __exit i915_exit(void)
1706 {
1707 #ifndef CONFIG_DRM_I915_UMS
1708         if (!(driver.driver_features & DRIVER_MODESET))
1709                 return; /* Never loaded a driver. */
1710 #endif
1711
1712         drm_pci_exit(&driver, &i915_pci_driver);
1713 }
1714
1715 module_init(i915_init);
1716 module_exit(i915_exit);
1717
1718 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1719 MODULE_AUTHOR("Intel Corporation");
1720
1721 MODULE_DESCRIPTION(DRIVER_DESC);
1722 MODULE_LICENSE("GPL and additional rights");