drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fpga_dbg = 1,
 307         .has_fbc = 1,
 308         GEN_DEFAULT_PIPEOFFSETS,
 309         IVB_CURSOR_OFFSETS,
 310 };
 311
 312 static const struct intel_device_info intel_broadwell_m_info = {
 313         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 314         .need_gfx_hws = 1, .has_hotplug = 1,
 315         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 316         .has_llc = 1,
 317         .has_ddi = 1,
 318         .has_fpga_dbg = 1,
 319         .has_fbc = 1,
 320         GEN_DEFAULT_PIPEOFFSETS,
 321         IVB_CURSOR_OFFSETS,
 322 };
 323
 324 static const struct intel_device_info intel_broadwell_gt3d_info = {
 325         .gen = 8, .num_pipes = 3,
 326         .need_gfx_hws = 1, .has_hotplug = 1,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328         .has_llc = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333         IVB_CURSOR_OFFSETS,
 334 };
 335
 336 static const struct intel_device_info intel_broadwell_gt3m_info = {
 337         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 338         .need_gfx_hws = 1, .has_hotplug = 1,
 339         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 340         .has_llc = 1,
 341         .has_ddi = 1,
 342         .has_fpga_dbg = 1,
 343         .has_fbc = 1,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346 };
 347
 348 static const struct intel_device_info intel_cherryview_info = {
 349         .is_preliminary = 1,
 350         .gen = 8, .num_pipes = 3,
 351         .need_gfx_hws = 1, .has_hotplug = 1,
 352         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 353         .is_valleyview = 1,
 354         .display_mmio_offset = VLV_DISPLAY_BASE,
 355         GEN_CHV_PIPEOFFSETS,
 356         CURSOR_OFFSETS,
 357 };
 358
 359 static const struct intel_device_info intel_skylake_info = {
 360         .is_preliminary = 1,
 361         .is_skylake = 1,
 362         .gen = 9, .num_pipes = 3,
 363         .need_gfx_hws = 1, .has_hotplug = 1,
 364         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 365         .has_llc = 1,
 366         .has_ddi = 1,
 367         .has_fbc = 1,
 368         GEN_DEFAULT_PIPEOFFSETS,
 369         IVB_CURSOR_OFFSETS,
 370 };
 371
 372 /*
 373  * Make sure any device matches here are from most specific to most
 374  * general.  For example, since the Quanta match is based on the subsystem
 375  * and subvendor IDs, we need it to come before the more general IVB
 376  * PCI ID matches, otherwise we'll use the wrong info struct above.
 377  */
 378 #define INTEL_PCI_IDS \
 379         INTEL_I830_IDS(&intel_i830_info),       \
 380         INTEL_I845G_IDS(&intel_845g_info),      \
 381         INTEL_I85X_IDS(&intel_i85x_info),       \
 382         INTEL_I865G_IDS(&intel_i865g_info),     \
 383         INTEL_I915G_IDS(&intel_i915g_info),     \
 384         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 385         INTEL_I945G_IDS(&intel_i945g_info),     \
 386         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 387         INTEL_I965G_IDS(&intel_i965g_info),     \
 388         INTEL_G33_IDS(&intel_g33_info),         \
 389         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 390         INTEL_GM45_IDS(&intel_gm45_info),       \
 391         INTEL_G45_IDS(&intel_g45_info),         \
 392         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 393         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 394         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 395         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 396         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 397         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 398         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 399         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 400         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 401         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 402         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 403         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 404         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 405         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 406         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 407         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 408         INTEL_CHV_IDS(&intel_cherryview_info),  \
 409         INTEL_SKL_IDS(&intel_skylake_info)
 410
 411 static const struct pci_device_id pciidlist[] = {               /* aka */
 412         INTEL_PCI_IDS,
 413         {0, 0, 0}
 414 };
 415
 416 #if defined(CONFIG_DRM_I915_KMS)
 417 MODULE_DEVICE_TABLE(pci, pciidlist);
 418 #endif
 419
 420 void intel_detect_pch(struct drm_device *dev)
 421 {
 422         struct drm_i915_private *dev_priv = dev->dev_private;
 423         struct pci_dev *pch = NULL;
 424
 425         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 426          * (which really amounts to a PCH but no South Display).
 427          */
 428         if (INTEL_INFO(dev)->num_pipes == 0) {
 429                 dev_priv->pch_type = PCH_NOP;
 430                 return;
 431         }
 432
 433         /*
 434          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 435          * make graphics device passthrough work easy for VMM, that only
 436          * need to expose ISA bridge to let driver know the real hardware
 437          * underneath. This is a requirement from virtualization team.
 438          *
 439          * In some virtualized environments (e.g. XEN), there is irrelevant
 440          * ISA bridge in the system. To work reliably, we should scan trhough
 441          * all the ISA bridge devices and check for the first match, instead
 442          * of only checking the first one.
 443          */
 444         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 445                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 446                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 447                         dev_priv->pch_id = id;
 448
 449                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 450                                 dev_priv->pch_type = PCH_IBX;
 451                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 452                                 WARN_ON(!IS_GEN5(dev));
 453                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 454                                 dev_priv->pch_type = PCH_CPT;
 455                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 456                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 457                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 458                                 /* PantherPoint is CPT compatible */
 459                                 dev_priv->pch_type = PCH_CPT;
 460                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 461                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 462                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 463                                 dev_priv->pch_type = PCH_LPT;
 464                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 465                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 466                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 467                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 468                                 dev_priv->pch_type = PCH_LPT;
 469                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 470                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 471                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 472                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 473                                 dev_priv->pch_type = PCH_SPT;
 474                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 475                                 WARN_ON(!IS_SKYLAKE(dev));
 476                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 477                                 dev_priv->pch_type = PCH_SPT;
 478                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 479                                 WARN_ON(!IS_SKYLAKE(dev));
 480                         } else
 481                                 continue;
 482
 483                         break;
 484                 }
 485         }
 486         if (!pch)
 487                 DRM_DEBUG_KMS("No PCH found.\n");
 488
 489         pci_dev_put(pch);
 490 }
 491
 492 bool i915_semaphore_is_enabled(struct drm_device *dev)
 493 {
 494         if (INTEL_INFO(dev)->gen < 6)
 495                 return false;
 496
 497         if (i915.semaphores >= 0)
 498                 return i915.semaphores;
 499
 500         /* TODO: make semaphores and Execlists play nicely together */
 501         if (i915.enable_execlists)
 502                 return false;
 503
 504         /* Until we get further testing... */
 505         if (IS_GEN8(dev))
 506                 return false;
 507
 508 #ifdef CONFIG_INTEL_IOMMU
 509         /* Enable semaphores on SNB when IO remapping is off */
 510         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 511                 return false;
 512 #endif
 513
 514         return true;
 515 }
 516
 517 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
 518 {
 519         spin_lock_irq(&dev_priv->irq_lock);
 520
 521         dev_priv->long_hpd_port_mask = 0;
 522         dev_priv->short_hpd_port_mask = 0;
 523         dev_priv->hpd_event_bits = 0;
 524
 525         spin_unlock_irq(&dev_priv->irq_lock);
 526
 527         cancel_work_sync(&dev_priv->dig_port_work);
 528         cancel_work_sync(&dev_priv->hotplug_work);
 529         cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
 530 }
 531
 532 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 533 {
 534         struct drm_device *dev = dev_priv->dev;
 535         struct drm_encoder *encoder;
 536
 537         drm_modeset_lock_all(dev);
 538         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 539                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 540
 541                 if (intel_encoder->suspend)
 542                         intel_encoder->suspend(intel_encoder);
 543         }
 544         drm_modeset_unlock_all(dev);
 545 }
 546
 547 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 548 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 549                               bool rpm_resume);
 550
 551 static int i915_drm_suspend(struct drm_device *dev)
 552 {
 553         struct drm_i915_private *dev_priv = dev->dev_private;
 554         struct drm_crtc *crtc;
 555         pci_power_t opregion_target_state;
 556
 557         /* ignore lid events during suspend */
 558         mutex_lock(&dev_priv->modeset_restore_lock);
 559         dev_priv->modeset_restore = MODESET_SUSPENDED;
 560         mutex_unlock(&dev_priv->modeset_restore_lock);
 561
 562         /* We do a lot of poking in a lot of registers, make sure they work
 563          * properly. */
 564         intel_display_set_init_power(dev_priv, true);
 565
 566         drm_kms_helper_poll_disable(dev);
 567
 568         pci_save_state(dev->pdev);
 569
 570         /* If KMS is active, we do the leavevt stuff here */
 571         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 572                 int error;
 573
 574                 error = i915_gem_suspend(dev);
 575                 if (error) {
 576                         dev_err(&dev->pdev->dev,
 577                                 "GEM idle failed, resume might fail\n");
 578                         return error;
 579                 }
 580
 581                 intel_suspend_gt_powersave(dev);
 582
 583                 /*
 584                  * Disable CRTCs directly since we want to preserve sw state
 585                  * for _thaw. Also, power gate the CRTC power wells.
 586                  */
 587                 drm_modeset_lock_all(dev);
 588                 for_each_crtc(dev, crtc)
 589                         intel_crtc_control(crtc, false);
 590                 drm_modeset_unlock_all(dev);
 591
 592                 intel_dp_mst_suspend(dev);
 593
 594                 intel_runtime_pm_disable_interrupts(dev_priv);
 595                 intel_hpd_cancel_work(dev_priv);
 596
 597                 intel_suspend_encoders(dev_priv);
 598
 599                 intel_suspend_hw(dev);
 600         }
 601
 602         i915_gem_suspend_gtt_mappings(dev);
 603
 604         i915_save_state(dev);
 605
 606         opregion_target_state = PCI_D3cold;
 607 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 608         if (acpi_target_system_state() < ACPI_STATE_S3)
 609                 opregion_target_state = PCI_D1;
 610 #endif
 611         intel_opregion_notify_adapter(dev, opregion_target_state);
 612
 613         intel_uncore_forcewake_reset(dev, false);
 614         intel_opregion_fini(dev);
 615
 616         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 617
 618         dev_priv->suspend_count++;
 619
 620         intel_display_set_init_power(dev_priv, false);
 621
 622         return 0;
 623 }
 624
 625 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 626 {
 627         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 628         int ret;
 629
 630         ret = intel_suspend_complete(dev_priv);
 631
 632         if (ret) {
 633                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 634
 635                 return ret;
 636         }
 637
 638         pci_disable_device(drm_dev->pdev);
 639         /*
 640          * During hibernation on some GEN4 platforms the BIOS may try to access
 641          * the device even though it's already in D3 and hang the machine. So
 642          * leave the device in D0 on those platforms and hope the BIOS will
 643          * power down the device properly. Platforms where this was seen:
 644          * Lenovo Thinkpad X301, X61s
 645          */
 646         if (!(hibernation &&
 647               drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
 648               INTEL_INFO(dev_priv)->gen == 4))
 649                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 650
 651         return 0;
 652 }
 653
 654 int i915_suspend_legacy(struct drm_device *dev, pm_message_t state)
 655 {
 656         int error;
 657
 658         if (!dev || !dev->dev_private) {
 659                 DRM_ERROR("dev: %p\n", dev);
 660                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 661                 return -ENODEV;
 662         }
 663
 664         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 665                          state.event != PM_EVENT_FREEZE))
 666                 return -EINVAL;
 667
 668         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 669                 return 0;
 670
 671         error = i915_drm_suspend(dev);
 672         if (error)
 673                 return error;
 674
 675         return i915_drm_suspend_late(dev, false);
 676 }
 677
 678 static int i915_drm_resume(struct drm_device *dev)
 679 {
 680         struct drm_i915_private *dev_priv = dev->dev_private;
 681
 682         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 683                 mutex_lock(&dev->struct_mutex);
 684                 i915_gem_restore_gtt_mappings(dev);
 685                 mutex_unlock(&dev->struct_mutex);
 686         }
 687
 688         i915_restore_state(dev);
 689         intel_opregion_setup(dev);
 690
 691         /* KMS EnterVT equivalent */
 692         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 693                 intel_init_pch_refclk(dev);
 694                 drm_mode_config_reset(dev);
 695
 696                 mutex_lock(&dev->struct_mutex);
 697                 if (i915_gem_init_hw(dev)) {
 698                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 699                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 700                 }
 701                 mutex_unlock(&dev->struct_mutex);
 702
 703                 /* We need working interrupts for modeset enabling ... */
 704                 intel_runtime_pm_enable_interrupts(dev_priv);
 705
 706                 intel_modeset_init_hw(dev);
 707
 708                 spin_lock_irq(&dev_priv->irq_lock);
 709                 if (dev_priv->display.hpd_irq_setup)
 710                         dev_priv->display.hpd_irq_setup(dev);
 711                 spin_unlock_irq(&dev_priv->irq_lock);
 712
 713                 drm_modeset_lock_all(dev);
 714                 intel_modeset_setup_hw_state(dev, true);
 715                 drm_modeset_unlock_all(dev);
 716
 717                 intel_dp_mst_resume(dev);
 718
 719                 /*
 720                  * ... but also need to make sure that hotplug processing
 721                  * doesn't cause havoc. Like in the driver load code we don't
 722                  * bother with the tiny race here where we might loose hotplug
 723                  * notifications.
 724                  * */
 725                 intel_hpd_init(dev_priv);
 726                 /* Config may have changed between suspend and resume */
 727                 drm_helper_hpd_irq_event(dev);
 728         }
 729
 730         intel_opregion_init(dev);
 731
 732         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 733
 734         mutex_lock(&dev_priv->modeset_restore_lock);
 735         dev_priv->modeset_restore = MODESET_DONE;
 736         mutex_unlock(&dev_priv->modeset_restore_lock);
 737
 738         intel_opregion_notify_adapter(dev, PCI_D0);
 739
 740         drm_kms_helper_poll_enable(dev);
 741
 742         return 0;
 743 }
 744
 745 static int i915_drm_resume_early(struct drm_device *dev)
 746 {
 747         struct drm_i915_private *dev_priv = dev->dev_private;
 748         int ret = 0;
 749
 750         /*
 751          * We have a resume ordering issue with the snd-hda driver also
 752          * requiring our device to be power up. Due to the lack of a
 753          * parent/child relationship we currently solve this with an early
 754          * resume hook.
 755          *
 756          * FIXME: This should be solved with a special hdmi sink device or
 757          * similar so that power domains can be employed.
 758          */
 759         if (pci_enable_device(dev->pdev))
 760                 return -EIO;
 761
 762         pci_set_master(dev->pdev);
 763
 764         if (IS_VALLEYVIEW(dev_priv))
 765                 ret = vlv_resume_prepare(dev_priv, false);
 766         if (ret)
 767                 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
 768
 769         intel_uncore_early_sanitize(dev, true);
 770
 771         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 772                 hsw_disable_pc8(dev_priv);
 773
 774         intel_uncore_sanitize(dev);
 775         intel_power_domains_init_hw(dev_priv);
 776
 777         return ret;
 778 }
 779
 780 int i915_resume_legacy(struct drm_device *dev)
 781 {
 782         int ret;
 783
 784         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 785                 return 0;
 786
 787         ret = i915_drm_resume_early(dev);
 788         if (ret)
 789                 return ret;
 790
 791         return i915_drm_resume(dev);
 792 }
 793
 794 /**
 795  * i915_reset - reset chip after a hang
 796  * @dev: drm device to reset
 797  *
 798  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 799  * reset or otherwise an error code.
 800  *
 801  * Procedure is fairly simple:
 802  *   - reset the chip using the reset reg
 803  *   - re-init context state
 804  *   - re-init hardware status page
 805  *   - re-init ring buffer
 806  *   - re-init interrupt state
 807  *   - re-init display
 808  */
 809 int i915_reset(struct drm_device *dev)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         bool simulated;
 813         int ret;
 814
 815         if (!i915.reset)
 816                 return 0;
 817
 818         intel_reset_gt_powersave(dev);
 819
 820         mutex_lock(&dev->struct_mutex);
 821
 822         i915_gem_reset(dev);
 823
 824         simulated = dev_priv->gpu_error.stop_rings != 0;
 825
 826         ret = intel_gpu_reset(dev);
 827
 828         /* Also reset the gpu hangman. */
 829         if (simulated) {
 830                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 831                 dev_priv->gpu_error.stop_rings = 0;
 832                 if (ret == -ENODEV) {
 833                         DRM_INFO("Reset not implemented, but ignoring "
 834                                  "error for simulated gpu hangs\n");
 835                         ret = 0;
 836                 }
 837         }
 838
 839         if (i915_stop_ring_allow_warn(dev_priv))
 840                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 841
 842         if (ret) {
 843                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 844                 mutex_unlock(&dev->struct_mutex);
 845                 return ret;
 846         }
 847
 848         intel_overlay_reset(dev_priv);
 849
 850         /* Ok, now get things going again... */
 851
 852         /*
 853          * Everything depends on having the GTT running, so we need to start
 854          * there.  Fortunately we don't need to do this unless we reset the
 855          * chip at a PCI level.
 856          *
 857          * Next we need to restore the context, but we don't use those
 858          * yet either...
 859          *
 860          * Ring buffer needs to be re-initialized in the KMS case, or if X
 861          * was running at the time of the reset (i.e. we weren't VT
 862          * switched away).
 863          */
 864         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 865                 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 866                 dev_priv->gpu_error.reload_in_reset = true;
 867
 868                 ret = i915_gem_init_hw(dev);
 869
 870                 dev_priv->gpu_error.reload_in_reset = false;
 871
 872                 mutex_unlock(&dev->struct_mutex);
 873                 if (ret) {
 874                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 875                         return ret;
 876                 }
 877
 878                 /*
 879                  * FIXME: This races pretty badly against concurrent holders of
 880                  * ring interrupts. This is possible since we've started to drop
 881                  * dev->struct_mutex in select places when waiting for the gpu.
 882                  */
 883
 884                 /*
 885                  * rps/rc6 re-init is necessary to restore state lost after the
 886                  * reset and the re-install of gt irqs. Skip for ironlake per
 887                  * previous concerns that it doesn't respond well to some forms
 888                  * of re-init after reset.
 889                  */
 890                 if (INTEL_INFO(dev)->gen > 5)
 891                         intel_enable_gt_powersave(dev);
 892         } else {
 893                 mutex_unlock(&dev->struct_mutex);
 894         }
 895
 896         return 0;
 897 }
 898
 899 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 900 {
 901         struct intel_device_info *intel_info =
 902                 (struct intel_device_info *) ent->driver_data;
 903
 904         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 905                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 906                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 907                 return -ENODEV;
 908         }
 909
 910         /* Only bind to function 0 of the device. Early generations
 911          * used function 1 as a placeholder for multi-head. This causes
 912          * us confusion instead, especially on the systems where both
 913          * functions have the same PCI-ID!
 914          */
 915         if (PCI_FUNC(pdev->devfn))
 916                 return -ENODEV;
 917
 918         driver.driver_features &= ~(DRIVER_USE_AGP);
 919
 920         return drm_get_pci_dev(pdev, ent, &driver);
 921 }
 922
 923 static void
 924 i915_pci_remove(struct pci_dev *pdev)
 925 {
 926         struct drm_device *dev = pci_get_drvdata(pdev);
 927
 928         drm_put_dev(dev);
 929 }
 930
 931 static int i915_pm_suspend(struct device *dev)
 932 {
 933         struct pci_dev *pdev = to_pci_dev(dev);
 934         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 935
 936         if (!drm_dev || !drm_dev->dev_private) {
 937                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 938                 return -ENODEV;
 939         }
 940
 941         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 942                 return 0;
 943
 944         return i915_drm_suspend(drm_dev);
 945 }
 946
 947 static int i915_pm_suspend_late(struct device *dev)
 948 {
 949         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 950
 951         /*
 952          * We have a suspedn ordering issue with the snd-hda driver also
 953          * requiring our device to be power up. Due to the lack of a
 954          * parent/child relationship we currently solve this with an late
 955          * suspend hook.
 956          *
 957          * FIXME: This should be solved with a special hdmi sink device or
 958          * similar so that power domains can be employed.
 959          */
 960         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 961                 return 0;
 962
 963         return i915_drm_suspend_late(drm_dev, false);
 964 }
 965
 966 static int i915_pm_poweroff_late(struct device *dev)
 967 {
 968         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 969
 970         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 971                 return 0;
 972
 973         return i915_drm_suspend_late(drm_dev, true);
 974 }
 975
 976 static int i915_pm_resume_early(struct device *dev)
 977 {
 978         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 979
 980         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 981                 return 0;
 982
 983         return i915_drm_resume_early(drm_dev);
 984 }
 985
 986 static int i915_pm_resume(struct device *dev)
 987 {
 988         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 989
 990         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 991                 return 0;
 992
 993         return i915_drm_resume(drm_dev);
 994 }
 995
 996 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
 997 {
 998         hsw_enable_pc8(dev_priv);
 999
1000         return 0;
1001 }
1002
1003 /*
1004  * Save all Gunit registers that may be lost after a D3 and a subsequent
1005  * S0i[R123] transition. The list of registers needing a save/restore is
1006  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1007  * registers in the following way:
1008  * - Driver: saved/restored by the driver
1009  * - Punit : saved/restored by the Punit firmware
1010  * - No, w/o marking: no need to save/restore, since the register is R/O or
1011  *                    used internally by the HW in a way that doesn't depend
1012  *                    keeping the content across a suspend/resume.
1013  * - Debug : used for debugging
1014  *
1015  * We save/restore all registers marked with 'Driver', with the following
1016  * exceptions:
1017  * - Registers out of use, including also registers marked with 'Debug'.
1018  *   These have no effect on the driver's operation, so we don't save/restore
1019  *   them to reduce the overhead.
1020  * - Registers that are fully setup by an initialization function called from
1021  *   the resume path. For example many clock gating and RPS/RC6 registers.
1022  * - Registers that provide the right functionality with their reset defaults.
1023  *
1024  * TODO: Except for registers that based on the above 3 criteria can be safely
1025  * ignored, we save/restore all others, practically treating the HW context as
1026  * a black-box for the driver. Further investigation is needed to reduce the
1027  * saved/restored registers even further, by following the same 3 criteria.
1028  */
1029 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1030 {
1031         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1032         int i;
1033
1034         /* GAM 0x4000-0x4770 */
1035         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1036         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1037         s->arb_mode             = I915_READ(ARB_MODE);
1038         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1039         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1040
1041         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1042                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1043
1044         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1045         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1046
1047         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1048         s->ecochk               = I915_READ(GAM_ECOCHK);
1049         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1050         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1051
1052         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1053
1054         /* MBC 0x9024-0x91D0, 0x8500 */
1055         s->g3dctl               = I915_READ(VLV_G3DCTL);
1056         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1057         s->mbctl                = I915_READ(GEN6_MBCTL);
1058
1059         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1060         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1061         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1062         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1063         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1064         s->rstctl               = I915_READ(GEN6_RSTCTL);
1065         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1066
1067         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1068         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1069         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1070         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1071         s->ecobus               = I915_READ(ECOBUS);
1072         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1073         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1074         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1075         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1076         s->rcedata              = I915_READ(VLV_RCEDATA);
1077         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1078
1079         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1080         s->gt_imr               = I915_READ(GTIMR);
1081         s->gt_ier               = I915_READ(GTIER);
1082         s->pm_imr               = I915_READ(GEN6_PMIMR);
1083         s->pm_ier               = I915_READ(GEN6_PMIER);
1084
1085         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1086                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1087
1088         /* GT SA CZ domain, 0x100000-0x138124 */
1089         s->tilectl              = I915_READ(TILECTL);
1090         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1091         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1092         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1093         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1094
1095         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1096         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1097         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1098         s->pcbr                 = I915_READ(VLV_PCBR);
1099         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1100
1101         /*
1102          * Not saving any of:
1103          * DFT,         0x9800-0x9EC0
1104          * SARB,        0xB000-0xB1FC
1105          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1106          * PCI CFG
1107          */
1108 }
1109
1110 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1111 {
1112         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1113         u32 val;
1114         int i;
1115
1116         /* GAM 0x4000-0x4770 */
1117         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1118         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1119         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1120         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1121         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1122
1123         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1124                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1125
1126         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1127         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1128
1129         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1130         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1131         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1132         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1133
1134         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1135
1136         /* MBC 0x9024-0x91D0, 0x8500 */
1137         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1138         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1139         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1140
1141         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1142         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1143         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1144         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1145         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1146         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1147         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1148
1149         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1150         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1151         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1152         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1153         I915_WRITE(ECOBUS,              s->ecobus);
1154         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1155         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1156         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1157         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1158         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1159         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1160
1161         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1162         I915_WRITE(GTIMR,               s->gt_imr);
1163         I915_WRITE(GTIER,               s->gt_ier);
1164         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1165         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1166
1167         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1168                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1169
1170         /* GT SA CZ domain, 0x100000-0x138124 */
1171         I915_WRITE(TILECTL,                     s->tilectl);
1172         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1173         /*
1174          * Preserve the GT allow wake and GFX force clock bit, they are not
1175          * be restored, as they are used to control the s0ix suspend/resume
1176          * sequence by the caller.
1177          */
1178         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1179         val &= VLV_GTLC_ALLOWWAKEREQ;
1180         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1181         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1182
1183         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1184         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1185         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1186         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1187
1188         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1189
1190         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1191         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1192         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1193         I915_WRITE(VLV_PCBR,                    s->pcbr);
1194         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1195 }
1196
1197 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1198 {
1199         u32 val;
1200         int err;
1201
1202 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1203
1204         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1205         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1206         if (force_on)
1207                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1208         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1209
1210         if (!force_on)
1211                 return 0;
1212
1213         err = wait_for(COND, 20);
1214         if (err)
1215                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1216                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1217
1218         return err;
1219 #undef COND
1220 }
1221
1222 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1223 {
1224         u32 val;
1225         int err = 0;
1226
1227         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1228         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1229         if (allow)
1230                 val |= VLV_GTLC_ALLOWWAKEREQ;
1231         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1232         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1233
1234 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1235               allow)
1236         err = wait_for(COND, 1);
1237         if (err)
1238                 DRM_ERROR("timeout disabling GT waking\n");
1239         return err;
1240 #undef COND
1241 }
1242
1243 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1244                                  bool wait_for_on)
1245 {
1246         u32 mask;
1247         u32 val;
1248         int err;
1249
1250         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1251         val = wait_for_on ? mask : 0;
1252 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1253         if (COND)
1254                 return 0;
1255
1256         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1257                         wait_for_on ? "on" : "off",
1258                         I915_READ(VLV_GTLC_PW_STATUS));
1259
1260         /*
1261          * RC6 transitioning can be delayed up to 2 msec (see
1262          * valleyview_enable_rps), use 3 msec for safety.
1263          */
1264         err = wait_for(COND, 3);
1265         if (err)
1266                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1267                           wait_for_on ? "on" : "off");
1268
1269         return err;
1270 #undef COND
1271 }
1272
1273 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1274 {
1275         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1276                 return;
1277
1278         DRM_ERROR("GT register access while GT waking disabled\n");
1279         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1280 }
1281
1282 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1283 {
1284         u32 mask;
1285         int err;
1286
1287         /*
1288          * Bspec defines the following GT well on flags as debug only, so
1289          * don't treat them as hard failures.
1290          */
1291         (void)vlv_wait_for_gt_wells(dev_priv, false);
1292
1293         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1294         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1295
1296         vlv_check_no_gt_access(dev_priv);
1297
1298         err = vlv_force_gfx_clock(dev_priv, true);
1299         if (err)
1300                 goto err1;
1301
1302         err = vlv_allow_gt_wake(dev_priv, false);
1303         if (err)
1304                 goto err2;
1305
1306         if (!IS_CHERRYVIEW(dev_priv->dev))
1307                 vlv_save_gunit_s0ix_state(dev_priv);
1308
1309         err = vlv_force_gfx_clock(dev_priv, false);
1310         if (err)
1311                 goto err2;
1312
1313         return 0;
1314
1315 err2:
1316         /* For safety always re-enable waking and disable gfx clock forcing */
1317         vlv_allow_gt_wake(dev_priv, true);
1318 err1:
1319         vlv_force_gfx_clock(dev_priv, false);
1320
1321         return err;
1322 }
1323
1324 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1325                                 bool rpm_resume)
1326 {
1327         struct drm_device *dev = dev_priv->dev;
1328         int err;
1329         int ret;
1330
1331         /*
1332          * If any of the steps fail just try to continue, that's the best we
1333          * can do at this point. Return the first error code (which will also
1334          * leave RPM permanently disabled).
1335          */
1336         ret = vlv_force_gfx_clock(dev_priv, true);
1337
1338         if (!IS_CHERRYVIEW(dev_priv->dev))
1339                 vlv_restore_gunit_s0ix_state(dev_priv);
1340
1341         err = vlv_allow_gt_wake(dev_priv, true);
1342         if (!ret)
1343                 ret = err;
1344
1345         err = vlv_force_gfx_clock(dev_priv, false);
1346         if (!ret)
1347                 ret = err;
1348
1349         vlv_check_no_gt_access(dev_priv);
1350
1351         if (rpm_resume) {
1352                 intel_init_clock_gating(dev);
1353                 i915_gem_restore_fences(dev);
1354         }
1355
1356         return ret;
1357 }
1358
1359 static int intel_runtime_suspend(struct device *device)
1360 {
1361         struct pci_dev *pdev = to_pci_dev(device);
1362         struct drm_device *dev = pci_get_drvdata(pdev);
1363         struct drm_i915_private *dev_priv = dev->dev_private;
1364         int ret;
1365
1366         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1367                 return -ENODEV;
1368
1369         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1370                 return -ENODEV;
1371
1372         DRM_DEBUG_KMS("Suspending device\n");
1373
1374         /*
1375          * We could deadlock here in case another thread holding struct_mutex
1376          * calls RPM suspend concurrently, since the RPM suspend will wait
1377          * first for this RPM suspend to finish. In this case the concurrent
1378          * RPM resume will be followed by its RPM suspend counterpart. Still
1379          * for consistency return -EAGAIN, which will reschedule this suspend.
1380          */
1381         if (!mutex_trylock(&dev->struct_mutex)) {
1382                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1383                 /*
1384                  * Bump the expiration timestamp, otherwise the suspend won't
1385                  * be rescheduled.
1386                  */
1387                 pm_runtime_mark_last_busy(device);
1388
1389                 return -EAGAIN;
1390         }
1391         /*
1392          * We are safe here against re-faults, since the fault handler takes
1393          * an RPM reference.
1394          */
1395         i915_gem_release_all_mmaps(dev_priv);
1396         mutex_unlock(&dev->struct_mutex);
1397
1398         intel_suspend_gt_powersave(dev);
1399         intel_runtime_pm_disable_interrupts(dev_priv);
1400
1401         ret = intel_suspend_complete(dev_priv);
1402         if (ret) {
1403                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1404                 intel_runtime_pm_enable_interrupts(dev_priv);
1405
1406                 return ret;
1407         }
1408
1409         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1410         intel_uncore_forcewake_reset(dev, false);
1411         dev_priv->pm.suspended = true;
1412
1413         /*
1414          * FIXME: We really should find a document that references the arguments
1415          * used below!
1416          */
1417         if (IS_HASWELL(dev)) {
1418                 /*
1419                  * current versions of firmware which depend on this opregion
1420                  * notification have repurposed the D1 definition to mean
1421                  * "runtime suspended" vs. what you would normally expect (D3)
1422                  * to distinguish it from notifications that might be sent via
1423                  * the suspend path.
1424                  */
1425                 intel_opregion_notify_adapter(dev, PCI_D1);
1426         } else {
1427                 /*
1428                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1429                  * being detected, and the call we do at intel_runtime_resume()
1430                  * won't be able to restore them. Since PCI_D3hot matches the
1431                  * actual specification and appears to be working, use it. Let's
1432                  * assume the other non-Haswell platforms will stay the same as
1433                  * Broadwell.
1434                  */
1435                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1436         }
1437
1438         assert_forcewakes_inactive(dev_priv);
1439
1440         DRM_DEBUG_KMS("Device suspended\n");
1441         return 0;
1442 }
1443
1444 static int intel_runtime_resume(struct device *device)
1445 {
1446         struct pci_dev *pdev = to_pci_dev(device);
1447         struct drm_device *dev = pci_get_drvdata(pdev);
1448         struct drm_i915_private *dev_priv = dev->dev_private;
1449         int ret = 0;
1450
1451         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1452                 return -ENODEV;
1453
1454         DRM_DEBUG_KMS("Resuming device\n");
1455
1456         intel_opregion_notify_adapter(dev, PCI_D0);
1457         dev_priv->pm.suspended = false;
1458
1459         if (IS_GEN6(dev_priv))
1460                 intel_init_pch_refclk(dev);
1461         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1462                 hsw_disable_pc8(dev_priv);
1463         else if (IS_VALLEYVIEW(dev_priv))
1464                 ret = vlv_resume_prepare(dev_priv, true);
1465
1466         /*
1467          * No point of rolling back things in case of an error, as the best
1468          * we can do is to hope that things will still work (and disable RPM).
1469          */
1470         i915_gem_init_swizzling(dev);
1471         gen6_update_ring_freq(dev);
1472
1473         intel_runtime_pm_enable_interrupts(dev_priv);
1474         intel_enable_gt_powersave(dev);
1475
1476         if (ret)
1477                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1478         else
1479                 DRM_DEBUG_KMS("Device resumed\n");
1480
1481         return ret;
1482 }
1483
1484 /*
1485  * This function implements common functionality of runtime and system
1486  * suspend sequence.
1487  */
1488 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1489 {
1490         struct drm_device *dev = dev_priv->dev;
1491         int ret;
1492
1493         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1494                 ret = hsw_suspend_complete(dev_priv);
1495         else if (IS_VALLEYVIEW(dev))
1496                 ret = vlv_suspend_complete(dev_priv);
1497         else
1498                 ret = 0;
1499
1500         return ret;
1501 }
1502
1503 static const struct dev_pm_ops i915_pm_ops = {
1504         /*
1505          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1506          * PMSG_RESUME]
1507          */
1508         .suspend = i915_pm_suspend,
1509         .suspend_late = i915_pm_suspend_late,
1510         .resume_early = i915_pm_resume_early,
1511         .resume = i915_pm_resume,
1512
1513         /*
1514          * S4 event handlers
1515          * @freeze, @freeze_late    : called (1) before creating the
1516          *                            hibernation image [PMSG_FREEZE] and
1517          *                            (2) after rebooting, before restoring
1518          *                            the image [PMSG_QUIESCE]
1519          * @thaw, @thaw_early       : called (1) after creating the hibernation
1520          *                            image, before writing it [PMSG_THAW]
1521          *                            and (2) after failing to create or
1522          *                            restore the image [PMSG_RECOVER]
1523          * @poweroff, @poweroff_late: called after writing the hibernation
1524          *                            image, before rebooting [PMSG_HIBERNATE]
1525          * @restore, @restore_early : called after rebooting and restoring the
1526          *                            hibernation image [PMSG_RESTORE]
1527          */
1528         .freeze = i915_pm_suspend,
1529         .freeze_late = i915_pm_suspend_late,
1530         .thaw_early = i915_pm_resume_early,
1531         .thaw = i915_pm_resume,
1532         .poweroff = i915_pm_suspend,
1533         .poweroff_late = i915_pm_poweroff_late,
1534         .restore_early = i915_pm_resume_early,
1535         .restore = i915_pm_resume,
1536
1537         /* S0ix (via runtime suspend) event handlers */
1538         .runtime_suspend = intel_runtime_suspend,
1539         .runtime_resume = intel_runtime_resume,
1540 };
1541
1542 static const struct vm_operations_struct i915_gem_vm_ops = {
1543         .fault = i915_gem_fault,
1544         .open = drm_gem_vm_open,
1545         .close = drm_gem_vm_close,
1546 };
1547
1548 static const struct file_operations i915_driver_fops = {
1549         .owner = THIS_MODULE,
1550         .open = drm_open,
1551         .release = drm_release,
1552         .unlocked_ioctl = drm_ioctl,
1553         .mmap = drm_gem_mmap,
1554         .poll = drm_poll,
1555         .read = drm_read,
1556 #ifdef CONFIG_COMPAT
1557         .compat_ioctl = i915_compat_ioctl,
1558 #endif
1559         .llseek = noop_llseek,
1560 };
1561
1562 static struct drm_driver driver = {
1563         /* Don't use MTRRs here; the Xserver or userspace app should
1564          * deal with them for Intel hardware.
1565          */
1566         .driver_features =
1567             DRIVER_USE_AGP |
1568             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1569             DRIVER_RENDER,
1570         .load = i915_driver_load,
1571         .unload = i915_driver_unload,
1572         .open = i915_driver_open,
1573         .lastclose = i915_driver_lastclose,
1574         .preclose = i915_driver_preclose,
1575         .postclose = i915_driver_postclose,
1576         .set_busid = drm_pci_set_busid,
1577
1578         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1579         .suspend = i915_suspend_legacy,
1580         .resume = i915_resume_legacy,
1581
1582         .device_is_agp = i915_driver_device_is_agp,
1583 #if defined(CONFIG_DEBUG_FS)
1584         .debugfs_init = i915_debugfs_init,
1585         .debugfs_cleanup = i915_debugfs_cleanup,
1586 #endif
1587         .gem_free_object = i915_gem_free_object,
1588         .gem_vm_ops = &i915_gem_vm_ops,
1589
1590         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1591         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1592         .gem_prime_export = i915_gem_prime_export,
1593         .gem_prime_import = i915_gem_prime_import,
1594
1595         .dumb_create = i915_gem_dumb_create,
1596         .dumb_map_offset = i915_gem_mmap_gtt,
1597         .dumb_destroy = drm_gem_dumb_destroy,
1598         .ioctls = i915_ioctls,
1599         .fops = &i915_driver_fops,
1600         .name = DRIVER_NAME,
1601         .desc = DRIVER_DESC,
1602         .date = DRIVER_DATE,
1603         .major = DRIVER_MAJOR,
1604         .minor = DRIVER_MINOR,
1605         .patchlevel = DRIVER_PATCHLEVEL,
1606 };
1607
1608 static struct pci_driver i915_pci_driver = {
1609         .name = DRIVER_NAME,
1610         .id_table = pciidlist,
1611         .probe = i915_pci_probe,
1612         .remove = i915_pci_remove,
1613         .driver.pm = &i915_pm_ops,
1614 };
1615
1616 static int __init i915_init(void)
1617 {
1618         driver.num_ioctls = i915_max_ioctl;
1619
1620         /*
1621          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1622          * explicitly disabled with the module pararmeter.
1623          *
1624          * Otherwise, just follow the parameter (defaulting to off).
1625          *
1626          * Allow optional vga_text_mode_force boot option to override
1627          * the default behavior.
1628          */
1629 #if defined(CONFIG_DRM_I915_KMS)
1630         if (i915.modeset != 0)
1631                 driver.driver_features |= DRIVER_MODESET;
1632 #endif
1633         if (i915.modeset == 1)
1634                 driver.driver_features |= DRIVER_MODESET;
1635
1636 #ifdef CONFIG_VGA_CONSOLE
1637         if (vgacon_text_force() && i915.modeset == -1)
1638                 driver.driver_features &= ~DRIVER_MODESET;
1639 #endif
1640
1641         if (!(driver.driver_features & DRIVER_MODESET)) {
1642                 driver.get_vblank_timestamp = NULL;
1643 #ifndef CONFIG_DRM_I915_UMS
1644                 /* Silently fail loading to not upset userspace. */
1645                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1646                 return 0;
1647 #endif
1648         }
1649
1650         /*
1651          * FIXME: Note that we're lying to the DRM core here so that we can get access
1652          * to the atomic ioctl and the atomic properties.  Only plane operations on
1653          * a single CRTC will actually work.
1654          */
1655         if (i915.nuclear_pageflip)
1656                 driver.driver_features |= DRIVER_ATOMIC;
1657
1658         return drm_pci_init(&driver, &i915_pci_driver);
1659 }
1660
1661 static void __exit i915_exit(void)
1662 {
1663 #ifndef CONFIG_DRM_I915_UMS
1664         if (!(driver.driver_features & DRIVER_MODESET))
1665                 return; /* Never loaded a driver. */
1666 #endif
1667
1668         drm_pci_exit(&driver, &i915_pci_driver);
1669 }
1670
1671 module_init(i915_init);
1672 module_exit(i915_exit);
1673
1674 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1675 MODULE_AUTHOR("Intel Corporation");
1676
1677 MODULE_DESCRIPTION(DRIVER_DESC);
1678 MODULE_LICENSE("GPL and additional rights");