1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150227"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
73 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
74 (long) (x), __func__);
76 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
77 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
78 * which may not necessarily be a user visible problem. This will either
79 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
80 * enable distros and users to tailor their preferred amount of i915 abrt
83 #define I915_STATE_WARN(condition, format...) ({ \
84 int __ret_warn_on = !!(condition); \
85 if (unlikely(__ret_warn_on)) { \
86 if (i915.verbose_state_checks) \
91 unlikely(__ret_warn_on); \
94 #define I915_STATE_WARN_ON(condition) ({ \
95 int __ret_warn_on = !!(condition); \
96 if (unlikely(__ret_warn_on)) { \
97 if (i915.verbose_state_checks) \
98 WARN(1, "WARN_ON(" #condition ")\n"); \
100 DRM_ERROR("WARN_ON(" #condition ")\n"); \
102 unlikely(__ret_warn_on); \
111 I915_MAX_PIPES = _PIPE_EDP
113 #define pipe_name(p) ((p) + 'A')
122 #define transcoder_name(t) ((t) + 'A')
125 * This is the maximum (across all platforms) number of planes (primary +
126 * sprites) that can be active at the same time on one pipe.
128 * This value doesn't count the cursor plane.
130 #define I915_MAX_PLANES 3
137 #define plane_name(p) ((p) + 'A')
139 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
149 #define port_name(p) ((p) + 'A')
151 #define I915_NUM_PHYS_VLV 2
163 enum intel_display_power_domain {
167 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
168 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
169 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
170 POWER_DOMAIN_TRANSCODER_A,
171 POWER_DOMAIN_TRANSCODER_B,
172 POWER_DOMAIN_TRANSCODER_C,
173 POWER_DOMAIN_TRANSCODER_EDP,
174 POWER_DOMAIN_PORT_DDI_A_2_LANES,
175 POWER_DOMAIN_PORT_DDI_A_4_LANES,
176 POWER_DOMAIN_PORT_DDI_B_2_LANES,
177 POWER_DOMAIN_PORT_DDI_B_4_LANES,
178 POWER_DOMAIN_PORT_DDI_C_2_LANES,
179 POWER_DOMAIN_PORT_DDI_C_4_LANES,
180 POWER_DOMAIN_PORT_DDI_D_2_LANES,
181 POWER_DOMAIN_PORT_DDI_D_4_LANES,
182 POWER_DOMAIN_PORT_DSI,
183 POWER_DOMAIN_PORT_CRT,
184 POWER_DOMAIN_PORT_OTHER,
197 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
198 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
199 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
200 #define POWER_DOMAIN_TRANSCODER(tran) \
201 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
202 (tran) + POWER_DOMAIN_TRANSCODER_A)
206 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
207 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
217 #define I915_GEM_GPU_DOMAINS \
218 (I915_GEM_DOMAIN_RENDER | \
219 I915_GEM_DOMAIN_SAMPLER | \
220 I915_GEM_DOMAIN_COMMAND | \
221 I915_GEM_DOMAIN_INSTRUCTION | \
222 I915_GEM_DOMAIN_VERTEX)
224 #define for_each_pipe(__dev_priv, __p) \
225 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
226 #define for_each_plane(pipe, p) \
227 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
228 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
230 #define for_each_crtc(dev, crtc) \
231 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
233 #define for_each_intel_crtc(dev, intel_crtc) \
234 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
236 #define for_each_intel_encoder(dev, intel_encoder) \
237 list_for_each_entry(intel_encoder, \
238 &(dev)->mode_config.encoder_list, \
241 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
242 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
243 if ((intel_encoder)->base.crtc == (__crtc))
245 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
246 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
247 if ((intel_connector)->base.encoder == (__encoder))
249 #define for_each_power_domain(domain, mask) \
250 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
251 if ((1 << (domain)) & (mask))
253 struct drm_i915_private;
254 struct i915_mm_struct;
255 struct i915_mmu_object;
258 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
259 /* real shared dpll ids must be >= 0 */
260 DPLL_ID_PCH_PLL_A = 0,
261 DPLL_ID_PCH_PLL_B = 1,
266 DPLL_ID_SKL_DPLL1 = 0,
267 DPLL_ID_SKL_DPLL2 = 1,
268 DPLL_ID_SKL_DPLL3 = 2,
270 #define I915_NUM_PLLS 3
272 struct intel_dpll_hw_state {
284 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
285 * lower part of crtl1 and they get shifted into position when writing
286 * the register. This allows us to easily compare the state to share
290 /* HDMI only, 0 when used for DP */
291 uint32_t cfgcr1, cfgcr2;
294 struct intel_shared_dpll_config {
295 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
296 struct intel_dpll_hw_state hw_state;
299 struct intel_shared_dpll {
300 struct intel_shared_dpll_config config;
301 struct intel_shared_dpll_config *new_config;
303 int active; /* count of number of active CRTCs (i.e. DPMS on) */
304 bool on; /* is the PLL actually active? Disabled during modeset */
306 /* should match the index in the dev_priv->shared_dplls array */
307 enum intel_dpll_id id;
308 /* The mode_set hook is optional and should be used together with the
309 * intel_prepare_shared_dpll function. */
310 void (*mode_set)(struct drm_i915_private *dev_priv,
311 struct intel_shared_dpll *pll);
312 void (*enable)(struct drm_i915_private *dev_priv,
313 struct intel_shared_dpll *pll);
314 void (*disable)(struct drm_i915_private *dev_priv,
315 struct intel_shared_dpll *pll);
316 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
317 struct intel_shared_dpll *pll,
318 struct intel_dpll_hw_state *hw_state);
326 /* Used by dp and fdi links */
327 struct intel_link_m_n {
335 void intel_link_compute_m_n(int bpp, int nlanes,
336 int pixel_clock, int link_clock,
337 struct intel_link_m_n *m_n);
339 /* Interface history:
342 * 1.2: Add Power Management
343 * 1.3: Add vblank support
344 * 1.4: Fix cmdbuffer path, add heap destroy
345 * 1.5: Add vblank pipe configuration
346 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
347 * - Support vertical blank on secondary display pipe
349 #define DRIVER_MAJOR 1
350 #define DRIVER_MINOR 6
351 #define DRIVER_PATCHLEVEL 0
353 #define WATCH_LISTS 0
355 struct opregion_header;
356 struct opregion_acpi;
357 struct opregion_swsci;
358 struct opregion_asle;
360 struct intel_opregion {
361 struct opregion_header __iomem *header;
362 struct opregion_acpi __iomem *acpi;
363 struct opregion_swsci __iomem *swsci;
364 u32 swsci_gbda_sub_functions;
365 u32 swsci_sbcb_sub_functions;
366 struct opregion_asle __iomem *asle;
368 u32 __iomem *lid_state;
369 struct work_struct asle_work;
371 #define OPREGION_SIZE (8*1024)
373 struct intel_overlay;
374 struct intel_overlay_error_state;
376 #define I915_FENCE_REG_NONE -1
377 #define I915_MAX_NUM_FENCES 32
378 /* 32 fences + sign bit for FENCE_REG_NONE */
379 #define I915_MAX_NUM_FENCE_BITS 6
381 struct drm_i915_fence_reg {
382 struct list_head lru_list;
383 struct drm_i915_gem_object *obj;
387 struct sdvo_device_mapping {
396 struct intel_display_error_state;
398 struct drm_i915_error_state {
406 /* Generic register state */
414 u32 error; /* gen6+ */
415 u32 err_int; /* gen7 */
421 u32 extra_instdone[I915_NUM_INSTDONE_REG];
422 u64 fence[I915_MAX_NUM_FENCES];
423 struct intel_overlay_error_state *overlay;
424 struct intel_display_error_state *display;
425 struct drm_i915_error_object *semaphore_obj;
427 struct drm_i915_error_ring {
429 /* Software tracked state */
432 enum intel_ring_hangcheck_action hangcheck_action;
435 /* our own tracking of ring head and tail */
439 u32 semaphore_seqno[I915_NUM_RINGS - 1];
457 u32 rc_psmi; /* sleep state */
458 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
460 struct drm_i915_error_object {
464 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
466 struct drm_i915_error_request {
481 char comm[TASK_COMM_LEN];
482 } ring[I915_NUM_RINGS];
484 struct drm_i915_error_buffer {
491 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
499 } **active_bo, **pinned_bo;
501 u32 *active_bo_count, *pinned_bo_count;
505 struct intel_connector;
506 struct intel_encoder;
507 struct intel_crtc_state;
508 struct intel_initial_plane_config;
513 struct drm_i915_display_funcs {
514 bool (*fbc_enabled)(struct drm_device *dev);
515 void (*enable_fbc)(struct drm_crtc *crtc);
516 void (*disable_fbc)(struct drm_device *dev);
517 int (*get_display_clock_speed)(struct drm_device *dev);
518 int (*get_fifo_size)(struct drm_device *dev, int plane);
520 * find_dpll() - Find the best values for the PLL
521 * @limit: limits for the PLL
522 * @crtc: current CRTC
523 * @target: target frequency in kHz
524 * @refclk: reference clock frequency in kHz
525 * @match_clock: if provided, @best_clock P divider must
526 * match the P divider from @match_clock
527 * used for LVDS downclocking
528 * @best_clock: best PLL values found
530 * Returns true on success, false on failure.
532 bool (*find_dpll)(const struct intel_limit *limit,
533 struct intel_crtc *crtc,
534 int target, int refclk,
535 struct dpll *match_clock,
536 struct dpll *best_clock);
537 void (*update_wm)(struct drm_crtc *crtc);
538 void (*update_sprite_wm)(struct drm_plane *plane,
539 struct drm_crtc *crtc,
540 uint32_t sprite_width, uint32_t sprite_height,
541 int pixel_size, bool enable, bool scaled);
542 void (*modeset_global_resources)(struct drm_device *dev);
543 /* Returns the active state of the crtc, and if the crtc is active,
544 * fills out the pipe-config with the hw state. */
545 bool (*get_pipe_config)(struct intel_crtc *,
546 struct intel_crtc_state *);
547 void (*get_initial_plane_config)(struct intel_crtc *,
548 struct intel_initial_plane_config *);
549 int (*crtc_compute_clock)(struct intel_crtc *crtc,
550 struct intel_crtc_state *crtc_state);
551 void (*crtc_enable)(struct drm_crtc *crtc);
552 void (*crtc_disable)(struct drm_crtc *crtc);
553 void (*off)(struct drm_crtc *crtc);
554 void (*audio_codec_enable)(struct drm_connector *connector,
555 struct intel_encoder *encoder,
556 struct drm_display_mode *mode);
557 void (*audio_codec_disable)(struct intel_encoder *encoder);
558 void (*fdi_link_train)(struct drm_crtc *crtc);
559 void (*init_clock_gating)(struct drm_device *dev);
560 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
561 struct drm_framebuffer *fb,
562 struct drm_i915_gem_object *obj,
563 struct intel_engine_cs *ring,
565 void (*update_primary_plane)(struct drm_crtc *crtc,
566 struct drm_framebuffer *fb,
568 void (*hpd_irq_setup)(struct drm_device *dev);
569 /* clock updates for mode set */
571 /* render clock increase/decrease */
572 /* display clock increase/decrease */
573 /* pll clock increase/decrease */
575 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
576 uint32_t (*get_backlight)(struct intel_connector *connector);
577 void (*set_backlight)(struct intel_connector *connector,
579 void (*disable_backlight)(struct intel_connector *connector);
580 void (*enable_backlight)(struct intel_connector *connector);
583 enum forcewake_domain_id {
584 FW_DOMAIN_ID_RENDER = 0,
585 FW_DOMAIN_ID_BLITTER,
591 enum forcewake_domains {
592 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
593 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
594 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
595 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
600 struct intel_uncore_funcs {
601 void (*force_wake_get)(struct drm_i915_private *dev_priv,
602 enum forcewake_domains domains);
603 void (*force_wake_put)(struct drm_i915_private *dev_priv,
604 enum forcewake_domains domains);
606 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
607 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
608 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
609 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
611 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
612 uint8_t val, bool trace);
613 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
614 uint16_t val, bool trace);
615 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
616 uint32_t val, bool trace);
617 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
618 uint64_t val, bool trace);
621 struct intel_uncore {
622 spinlock_t lock; /** lock is also taken in irq contexts. */
624 struct intel_uncore_funcs funcs;
627 enum forcewake_domains fw_domains;
629 struct intel_uncore_forcewake_domain {
630 struct drm_i915_private *i915;
631 enum forcewake_domain_id id;
633 struct timer_list timer;
640 } fw_domain[FW_DOMAIN_ID_COUNT];
643 /* Iterate over initialised fw domains */
644 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
645 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
646 (i__) < FW_DOMAIN_ID_COUNT; \
647 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
648 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
650 #define for_each_fw_domain(domain__, dev_priv__, i__) \
651 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
653 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
654 func(is_mobile) sep \
657 func(is_i945gm) sep \
659 func(need_gfx_hws) sep \
661 func(is_pineview) sep \
662 func(is_broadwater) sep \
663 func(is_crestline) sep \
664 func(is_ivybridge) sep \
665 func(is_valleyview) sep \
666 func(is_haswell) sep \
667 func(is_skylake) sep \
668 func(is_preliminary) sep \
670 func(has_pipe_cxsr) sep \
671 func(has_hotplug) sep \
672 func(cursor_needs_physical) sep \
673 func(has_overlay) sep \
674 func(overlay_needs_physical) sep \
675 func(supports_tv) sep \
680 #define DEFINE_FLAG(name) u8 name:1
681 #define SEP_SEMICOLON ;
683 struct intel_device_info {
684 u32 display_mmio_offset;
687 u8 num_sprites[I915_MAX_PIPES];
689 u8 ring_mask; /* Rings supported by the HW */
690 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
691 /* Register offsets for the various display pipes and transcoders */
692 int pipe_offsets[I915_MAX_TRANSCODERS];
693 int trans_offsets[I915_MAX_TRANSCODERS];
694 int palette_offsets[I915_MAX_PIPES];
695 int cursor_offsets[I915_MAX_PIPES];
697 /* Slice/subslice/EU info */
700 u8 subslice_per_slice;
703 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
706 u8 has_subslice_pg:1;
713 enum i915_cache_level {
715 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
716 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
717 caches, eg sampler/render caches, and the
718 large Last-Level-Cache. LLC is coherent with
719 the CPU, but L3 is only visible to the GPU. */
720 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
723 struct i915_ctx_hang_stats {
724 /* This context had batch pending when hang was declared */
725 unsigned batch_pending;
727 /* This context had batch active when hang was declared */
728 unsigned batch_active;
730 /* Time when this context was last blamed for a GPU reset */
731 unsigned long guilty_ts;
733 /* If the contexts causes a second GPU hang within this time,
734 * it is permanently banned from submitting any more work.
736 unsigned long ban_period_seconds;
738 /* This context is banned to submit more work */
742 /* This must match up with the value previously used for execbuf2.rsvd1. */
743 #define DEFAULT_CONTEXT_HANDLE 0
745 * struct intel_context - as the name implies, represents a context.
746 * @ref: reference count.
747 * @user_handle: userspace tracking identity for this context.
748 * @remap_slice: l3 row remapping information.
749 * @file_priv: filp associated with this context (NULL for global default
751 * @hang_stats: information about the role of this context in possible GPU
753 * @vm: virtual memory space used by this context.
754 * @legacy_hw_ctx: render context backing object and whether it is correctly
755 * initialized (legacy ring submission mechanism only).
756 * @link: link in the global list of contexts.
758 * Contexts are memory images used by the hardware to store copies of their
761 struct intel_context {
765 struct drm_i915_file_private *file_priv;
766 struct i915_ctx_hang_stats hang_stats;
767 struct i915_hw_ppgtt *ppgtt;
769 /* Legacy ring buffer submission */
771 struct drm_i915_gem_object *rcs_state;
776 bool rcs_initialized;
778 struct drm_i915_gem_object *state;
779 struct intel_ringbuffer *ringbuf;
781 } engine[I915_NUM_RINGS];
783 struct list_head link;
787 unsigned long uncompressed_size;
790 struct intel_crtc *crtc;
793 struct drm_mm_node compressed_fb;
794 struct drm_mm_node *compressed_llb;
798 /* Tracks whether the HW is actually enabled, not whether the feature is
802 /* On gen8 some rings cannont perform fbc clean operation so for now
803 * we are doing this on SW with mmio.
804 * This variable works in the opposite information direction
805 * of ring->fbc_dirty telling software on frontbuffer tracking
806 * to perform the cache clean on sw side.
808 bool need_sw_cache_clean;
810 struct intel_fbc_work {
811 struct delayed_work work;
812 struct drm_crtc *crtc;
813 struct drm_framebuffer *fb;
817 FBC_OK, /* FBC is enabled */
818 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
819 FBC_NO_OUTPUT, /* no outputs enabled to compress */
820 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
821 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
822 FBC_MODE_TOO_LARGE, /* mode too large for compression */
823 FBC_BAD_PLANE, /* fbc not supported on plane */
824 FBC_NOT_TILED, /* buffer not tiled */
825 FBC_MULTIPLE_PIPES, /* more than one pipe active */
827 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
832 * HIGH_RR is the highest eDP panel refresh rate read from EDID
833 * LOW_RR is the lowest eDP panel refresh rate found from EDID
834 * parsing for same resolution.
836 enum drrs_refresh_rate_type {
839 DRRS_MAX_RR, /* RR count */
842 enum drrs_support_type {
843 DRRS_NOT_SUPPORTED = 0,
844 STATIC_DRRS_SUPPORT = 1,
845 SEAMLESS_DRRS_SUPPORT = 2
851 struct delayed_work work;
853 unsigned busy_frontbuffer_bits;
854 enum drrs_refresh_rate_type refresh_rate_type;
855 enum drrs_support_type type;
862 struct intel_dp *enabled;
864 struct delayed_work work;
865 unsigned busy_frontbuffer_bits;
870 PCH_NONE = 0, /* No PCH present */
871 PCH_IBX, /* Ibexpeak PCH */
872 PCH_CPT, /* Cougarpoint PCH */
873 PCH_LPT, /* Lynxpoint PCH */
874 PCH_SPT, /* Sunrisepoint PCH */
878 enum intel_sbi_destination {
883 #define QUIRK_PIPEA_FORCE (1<<0)
884 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
885 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
886 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
887 #define QUIRK_PIPEB_FORCE (1<<4)
888 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
891 struct intel_fbc_work;
894 struct i2c_adapter adapter;
898 struct i2c_algo_bit_data bit_algo;
899 struct drm_i915_private *dev_priv;
902 struct i915_suspend_saved_registers {
905 u32 savePP_ON_DELAYS;
906 u32 savePP_OFF_DELAYS;
912 u32 saveCACHE_MODE_0;
913 u32 saveMI_ARB_STATE;
917 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
918 u32 savePCH_PORT_HOTPLUG;
922 struct vlv_s0ix_state {
929 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
930 u32 media_max_req_count;
931 u32 gfx_max_req_count;
963 /* Display 1 CZ domain */
968 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
970 /* GT SA CZ domain */
977 /* Display 2 CZ domain */
983 struct intel_rps_ei {
989 struct intel_gen6_power_mgmt {
991 * work, interrupts_enabled and pm_iir are protected by
994 struct work_struct work;
995 bool interrupts_enabled;
998 /* Frequencies are stored in potentially platform dependent multiples.
999 * In other words, *_freq needs to be multiplied by X to be interesting.
1000 * Soft limits are those which are used for the dynamic reclocking done
1001 * by the driver (raise frequencies under heavy loads, and lower for
1002 * lighter loads). Hard limits are those imposed by the hardware.
1004 * A distinction is made for overclocking, which is never enabled by
1005 * default, and is considered to be above the hard limit if it's
1008 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1009 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1010 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1011 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1012 u8 min_freq; /* AKA RPn. Minimum frequency */
1013 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1014 u8 rp1_freq; /* "less than" RP0 power/freqency */
1015 u8 rp0_freq; /* Non-overclocked max frequency. */
1018 u32 ei_interrupt_count;
1021 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1024 struct delayed_work delayed_resume_work;
1026 /* manual wa residency calculations */
1027 struct intel_rps_ei up_ei, down_ei;
1030 * Protects RPS/RC6 register access and PCU communication.
1031 * Must be taken after struct_mutex if nested.
1033 struct mutex hw_lock;
1036 /* defined intel_pm.c */
1037 extern spinlock_t mchdev_lock;
1039 struct intel_ilk_power_mgmt {
1047 unsigned long last_time1;
1048 unsigned long chipset_power;
1051 unsigned long gfx_power;
1057 struct drm_i915_gem_object *pwrctx;
1058 struct drm_i915_gem_object *renderctx;
1061 struct drm_i915_private;
1062 struct i915_power_well;
1064 struct i915_power_well_ops {
1066 * Synchronize the well's hw state to match the current sw state, for
1067 * example enable/disable it based on the current refcount. Called
1068 * during driver init and resume time, possibly after first calling
1069 * the enable/disable handlers.
1071 void (*sync_hw)(struct drm_i915_private *dev_priv,
1072 struct i915_power_well *power_well);
1074 * Enable the well and resources that depend on it (for example
1075 * interrupts located on the well). Called after the 0->1 refcount
1078 void (*enable)(struct drm_i915_private *dev_priv,
1079 struct i915_power_well *power_well);
1081 * Disable the well and resources that depend on it. Called after
1082 * the 1->0 refcount transition.
1084 void (*disable)(struct drm_i915_private *dev_priv,
1085 struct i915_power_well *power_well);
1086 /* Returns the hw enabled state. */
1087 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1088 struct i915_power_well *power_well);
1091 /* Power well structure for haswell */
1092 struct i915_power_well {
1095 /* power well enable/disable usage count */
1097 /* cached hw enabled state */
1099 unsigned long domains;
1101 const struct i915_power_well_ops *ops;
1104 struct i915_power_domains {
1106 * Power wells needed for initialization at driver init and suspend
1107 * time are on. They are kept on until after the first modeset.
1111 int power_well_count;
1114 int domain_use_count[POWER_DOMAIN_NUM];
1115 struct i915_power_well *power_wells;
1118 #define MAX_L3_SLICES 2
1119 struct intel_l3_parity {
1120 u32 *remap_info[MAX_L3_SLICES];
1121 struct work_struct error_work;
1125 struct i915_gem_batch_pool {
1126 struct drm_device *dev;
1127 struct list_head cache_list;
1130 struct i915_gem_mm {
1131 /** Memory allocator for GTT stolen memory */
1132 struct drm_mm stolen;
1133 /** List of all objects in gtt_space. Used to restore gtt
1134 * mappings on resume */
1135 struct list_head bound_list;
1137 * List of objects which are not bound to the GTT (thus
1138 * are idle and not used by the GPU) but still have
1139 * (presumably uncached) pages still attached.
1141 struct list_head unbound_list;
1144 * A pool of objects to use as shadow copies of client batch buffers
1145 * when the command parser is enabled. Prevents the client from
1146 * modifying the batch contents after software parsing.
1148 struct i915_gem_batch_pool batch_pool;
1150 /** Usable portion of the GTT for GEM */
1151 unsigned long stolen_base; /* limited to low memory (32-bit) */
1153 /** PPGTT used for aliasing the PPGTT with the GTT */
1154 struct i915_hw_ppgtt *aliasing_ppgtt;
1156 struct notifier_block oom_notifier;
1157 struct shrinker shrinker;
1158 bool shrinker_no_lock_stealing;
1160 /** LRU list of objects with fence regs on them. */
1161 struct list_head fence_list;
1164 * We leave the user IRQ off as much as possible,
1165 * but this means that requests will finish and never
1166 * be retired once the system goes idle. Set a timer to
1167 * fire periodically while the ring is running. When it
1168 * fires, go retire requests.
1170 struct delayed_work retire_work;
1173 * When we detect an idle GPU, we want to turn on
1174 * powersaving features. So once we see that there
1175 * are no more requests outstanding and no more
1176 * arrive within a small period of time, we fire
1177 * off the idle_work.
1179 struct delayed_work idle_work;
1182 * Are we in a non-interruptible section of code like
1188 * Is the GPU currently considered idle, or busy executing userspace
1189 * requests? Whilst idle, we attempt to power down the hardware and
1190 * display clocks. In order to reduce the effect on performance, there
1191 * is a slight delay before we do so.
1195 /* the indicator for dispatch video commands on two BSD rings */
1196 int bsd_ring_dispatch_index;
1198 /** Bit 6 swizzling required for X tiling */
1199 uint32_t bit_6_swizzle_x;
1200 /** Bit 6 swizzling required for Y tiling */
1201 uint32_t bit_6_swizzle_y;
1203 /* accounting, useful for userland debugging */
1204 spinlock_t object_stat_lock;
1205 size_t object_memory;
1209 struct drm_i915_error_state_buf {
1210 struct drm_i915_private *i915;
1219 struct i915_error_state_file_priv {
1220 struct drm_device *dev;
1221 struct drm_i915_error_state *error;
1224 struct i915_gpu_error {
1225 /* For hangcheck timer */
1226 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1227 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1228 /* Hang gpu twice in this window and your context gets banned */
1229 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1231 struct workqueue_struct *hangcheck_wq;
1232 struct delayed_work hangcheck_work;
1234 /* For reset and error_state handling. */
1236 /* Protected by the above dev->gpu_error.lock. */
1237 struct drm_i915_error_state *first_error;
1239 unsigned long missed_irq_rings;
1242 * State variable controlling the reset flow and count
1244 * This is a counter which gets incremented when reset is triggered,
1245 * and again when reset has been handled. So odd values (lowest bit set)
1246 * means that reset is in progress and even values that
1247 * (reset_counter >> 1):th reset was successfully completed.
1249 * If reset is not completed succesfully, the I915_WEDGE bit is
1250 * set meaning that hardware is terminally sour and there is no
1251 * recovery. All waiters on the reset_queue will be woken when
1254 * This counter is used by the wait_seqno code to notice that reset
1255 * event happened and it needs to restart the entire ioctl (since most
1256 * likely the seqno it waited for won't ever signal anytime soon).
1258 * This is important for lock-free wait paths, where no contended lock
1259 * naturally enforces the correct ordering between the bail-out of the
1260 * waiter and the gpu reset work code.
1262 atomic_t reset_counter;
1264 #define I915_RESET_IN_PROGRESS_FLAG 1
1265 #define I915_WEDGED (1 << 31)
1268 * Waitqueue to signal when the reset has completed. Used by clients
1269 * that wait for dev_priv->mm.wedged to settle.
1271 wait_queue_head_t reset_queue;
1273 /* Userspace knobs for gpu hang simulation;
1274 * combines both a ring mask, and extra flags
1277 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1278 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1280 /* For missed irq/seqno simulation. */
1281 unsigned int test_irq_rings;
1283 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1284 bool reload_in_reset;
1287 enum modeset_restore {
1288 MODESET_ON_LID_OPEN,
1293 struct ddi_vbt_port_info {
1295 * This is an index in the HDMI/DVI DDI buffer translation table.
1296 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1297 * populate this field.
1299 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1300 uint8_t hdmi_level_shift;
1302 uint8_t supports_dvi:1;
1303 uint8_t supports_hdmi:1;
1304 uint8_t supports_dp:1;
1307 enum psr_lines_to_wait {
1308 PSR_0_LINES_TO_WAIT = 0,
1310 PSR_4_LINES_TO_WAIT,
1314 struct intel_vbt_data {
1315 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1316 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1319 unsigned int int_tv_support:1;
1320 unsigned int lvds_dither:1;
1321 unsigned int lvds_vbt:1;
1322 unsigned int int_crt_support:1;
1323 unsigned int lvds_use_ssc:1;
1324 unsigned int display_clock_mode:1;
1325 unsigned int fdi_rx_polarity_inverted:1;
1326 unsigned int has_mipi:1;
1328 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1330 enum drrs_support_type drrs_type;
1335 int edp_preemphasis;
1337 bool edp_initialized;
1340 bool edp_low_vswing;
1341 struct edp_power_seq edp_pps;
1345 bool require_aux_wakeup;
1347 enum psr_lines_to_wait lines_to_wait;
1348 int tp1_wakeup_time;
1349 int tp2_tp3_wakeup_time;
1355 bool active_low_pwm;
1356 u8 min_brightness; /* min_brightness/255 of max */
1363 struct mipi_config *config;
1364 struct mipi_pps_data *pps;
1368 u8 *sequence[MIPI_SEQ_MAX];
1374 union child_device_config *child_dev;
1376 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1379 enum intel_ddb_partitioning {
1381 INTEL_DDB_PART_5_6, /* IVB+ */
1384 struct intel_wm_level {
1392 struct ilk_wm_values {
1393 uint32_t wm_pipe[3];
1395 uint32_t wm_lp_spr[3];
1396 uint32_t wm_linetime[3];
1398 enum intel_ddb_partitioning partitioning;
1401 struct skl_ddb_entry {
1402 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1405 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1407 return entry->end - entry->start;
1410 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1411 const struct skl_ddb_entry *e2)
1413 if (e1->start == e2->start && e1->end == e2->end)
1419 struct skl_ddb_allocation {
1420 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1421 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1422 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1425 struct skl_wm_values {
1426 bool dirty[I915_MAX_PIPES];
1427 struct skl_ddb_allocation ddb;
1428 uint32_t wm_linetime[I915_MAX_PIPES];
1429 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1430 uint32_t cursor[I915_MAX_PIPES][8];
1431 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1432 uint32_t cursor_trans[I915_MAX_PIPES];
1435 struct skl_wm_level {
1436 bool plane_en[I915_MAX_PLANES];
1438 uint16_t plane_res_b[I915_MAX_PLANES];
1439 uint8_t plane_res_l[I915_MAX_PLANES];
1440 uint16_t cursor_res_b;
1441 uint8_t cursor_res_l;
1445 * This struct helps tracking the state needed for runtime PM, which puts the
1446 * device in PCI D3 state. Notice that when this happens, nothing on the
1447 * graphics device works, even register access, so we don't get interrupts nor
1450 * Every piece of our code that needs to actually touch the hardware needs to
1451 * either call intel_runtime_pm_get or call intel_display_power_get with the
1452 * appropriate power domain.
1454 * Our driver uses the autosuspend delay feature, which means we'll only really
1455 * suspend if we stay with zero refcount for a certain amount of time. The
1456 * default value is currently very conservative (see intel_runtime_pm_enable), but
1457 * it can be changed with the standard runtime PM files from sysfs.
1459 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1460 * goes back to false exactly before we reenable the IRQs. We use this variable
1461 * to check if someone is trying to enable/disable IRQs while they're supposed
1462 * to be disabled. This shouldn't happen and we'll print some error messages in
1465 * For more, read the Documentation/power/runtime_pm.txt.
1467 struct i915_runtime_pm {
1472 enum intel_pipe_crc_source {
1473 INTEL_PIPE_CRC_SOURCE_NONE,
1474 INTEL_PIPE_CRC_SOURCE_PLANE1,
1475 INTEL_PIPE_CRC_SOURCE_PLANE2,
1476 INTEL_PIPE_CRC_SOURCE_PF,
1477 INTEL_PIPE_CRC_SOURCE_PIPE,
1478 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1479 INTEL_PIPE_CRC_SOURCE_TV,
1480 INTEL_PIPE_CRC_SOURCE_DP_B,
1481 INTEL_PIPE_CRC_SOURCE_DP_C,
1482 INTEL_PIPE_CRC_SOURCE_DP_D,
1483 INTEL_PIPE_CRC_SOURCE_AUTO,
1484 INTEL_PIPE_CRC_SOURCE_MAX,
1487 struct intel_pipe_crc_entry {
1492 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1493 struct intel_pipe_crc {
1495 bool opened; /* exclusive access to the result file */
1496 struct intel_pipe_crc_entry *entries;
1497 enum intel_pipe_crc_source source;
1499 wait_queue_head_t wq;
1502 struct i915_frontbuffer_tracking {
1506 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1513 struct i915_wa_reg {
1516 /* bitmask representing WA bits */
1520 #define I915_MAX_WA_REGS 16
1522 struct i915_workarounds {
1523 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1527 struct i915_virtual_gpu {
1531 struct drm_i915_private {
1532 struct drm_device *dev;
1533 struct kmem_cache *slab;
1535 const struct intel_device_info info;
1537 int relative_constants_mode;
1541 struct intel_uncore uncore;
1543 struct i915_virtual_gpu vgpu;
1545 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1548 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1549 * controller on different i2c buses. */
1550 struct mutex gmbus_mutex;
1553 * Base address of the gmbus and gpio block.
1555 uint32_t gpio_mmio_base;
1557 /* MMIO base address for MIPI regs */
1558 uint32_t mipi_mmio_base;
1560 wait_queue_head_t gmbus_wait_queue;
1562 struct pci_dev *bridge_dev;
1563 struct intel_engine_cs ring[I915_NUM_RINGS];
1564 struct drm_i915_gem_object *semaphore_obj;
1565 uint32_t last_seqno, next_seqno;
1567 struct drm_dma_handle *status_page_dmah;
1568 struct resource mch_res;
1570 /* protects the irq masks */
1571 spinlock_t irq_lock;
1573 /* protects the mmio flip data */
1574 spinlock_t mmio_flip_lock;
1576 bool display_irqs_enabled;
1578 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1579 struct pm_qos_request pm_qos;
1581 /* DPIO indirect register protection */
1582 struct mutex dpio_lock;
1584 /** Cached value of IMR to avoid reads in updating the bitfield */
1587 u32 de_irq_mask[I915_MAX_PIPES];
1592 u32 pipestat_irq_mask[I915_MAX_PIPES];
1594 struct work_struct hotplug_work;
1596 unsigned long hpd_last_jiffies;
1601 HPD_MARK_DISABLED = 2
1603 } hpd_stats[HPD_NUM_PINS];
1605 struct delayed_work hotplug_reenable_work;
1607 struct i915_fbc fbc;
1608 struct i915_drrs drrs;
1609 struct intel_opregion opregion;
1610 struct intel_vbt_data vbt;
1612 bool preserve_bios_swizzle;
1615 struct intel_overlay *overlay;
1617 /* backlight registers and fields in struct intel_panel */
1618 struct mutex backlight_lock;
1621 bool no_aux_handshake;
1623 /* protects panel power sequencer state */
1624 struct mutex pps_mutex;
1626 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1627 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1628 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1630 unsigned int fsb_freq, mem_freq, is_ddr3;
1631 unsigned int vlv_cdclk_freq;
1632 unsigned int hpll_freq;
1635 * wq - Driver workqueue for GEM.
1637 * NOTE: Work items scheduled here are not allowed to grab any modeset
1638 * locks, for otherwise the flushing done in the pageflip code will
1639 * result in deadlocks.
1641 struct workqueue_struct *wq;
1643 /* Display functions */
1644 struct drm_i915_display_funcs display;
1646 /* PCH chipset type */
1647 enum intel_pch pch_type;
1648 unsigned short pch_id;
1650 unsigned long quirks;
1652 enum modeset_restore modeset_restore;
1653 struct mutex modeset_restore_lock;
1655 struct list_head vm_list; /* Global list of all address spaces */
1656 struct i915_gtt gtt; /* VM representing the global address space */
1658 struct i915_gem_mm mm;
1659 DECLARE_HASHTABLE(mm_structs, 7);
1660 struct mutex mm_lock;
1662 /* Kernel Modesetting */
1664 struct sdvo_device_mapping sdvo_mappings[2];
1666 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1667 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1668 wait_queue_head_t pending_flip_queue;
1670 #ifdef CONFIG_DEBUG_FS
1671 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1674 int num_shared_dpll;
1675 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1676 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1678 struct i915_workarounds workarounds;
1680 /* Reclocking support */
1681 bool render_reclock_avail;
1682 bool lvds_downclock_avail;
1683 /* indicates the reduced downclock for LVDS*/
1686 struct i915_frontbuffer_tracking fb_tracking;
1690 bool mchbar_need_disable;
1692 struct intel_l3_parity l3_parity;
1694 /* Cannot be determined by PCIID. You must always read a register. */
1697 /* gen6+ rps state */
1698 struct intel_gen6_power_mgmt rps;
1700 /* ilk-only ips/rps state. Everything in here is protected by the global
1701 * mchdev_lock in intel_pm.c */
1702 struct intel_ilk_power_mgmt ips;
1704 struct i915_power_domains power_domains;
1706 struct i915_psr psr;
1708 struct i915_gpu_error gpu_error;
1710 struct drm_i915_gem_object *vlv_pctx;
1712 #ifdef CONFIG_DRM_I915_FBDEV
1713 /* list of fbdev register on this device */
1714 struct intel_fbdev *fbdev;
1715 struct work_struct fbdev_suspend_work;
1718 struct drm_property *broadcast_rgb_property;
1719 struct drm_property *force_audio_property;
1721 /* hda/i915 audio component */
1722 bool audio_component_registered;
1724 uint32_t hw_context_size;
1725 struct list_head context_list;
1730 struct i915_suspend_saved_registers regfile;
1731 struct vlv_s0ix_state vlv_s0ix_state;
1735 * Raw watermark latency values:
1736 * in 0.1us units for WM0,
1737 * in 0.5us units for WM1+.
1740 uint16_t pri_latency[5];
1742 uint16_t spr_latency[5];
1744 uint16_t cur_latency[5];
1746 * Raw watermark memory latency values
1747 * for SKL for all 8 levels
1750 uint16_t skl_latency[8];
1753 * The skl_wm_values structure is a bit too big for stack
1754 * allocation, so we keep the staging struct where we store
1755 * intermediate results here instead.
1757 struct skl_wm_values skl_results;
1759 /* current hardware state */
1761 struct ilk_wm_values hw;
1762 struct skl_wm_values skl_hw;
1766 struct i915_runtime_pm pm;
1768 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1769 u32 long_hpd_port_mask;
1770 u32 short_hpd_port_mask;
1771 struct work_struct dig_port_work;
1774 * if we get a HPD irq from DP and a HPD irq from non-DP
1775 * the non-DP HPD could block the workqueue on a mode config
1776 * mutex getting, that userspace may have taken. However
1777 * userspace is waiting on the DP workqueue to run which is
1778 * blocked behind the non-DP one.
1780 struct workqueue_struct *dp_wq;
1782 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1784 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1785 struct intel_engine_cs *ring,
1786 struct intel_context *ctx,
1787 struct drm_i915_gem_execbuffer2 *args,
1788 struct list_head *vmas,
1789 struct drm_i915_gem_object *batch_obj,
1790 u64 exec_start, u32 flags);
1791 int (*init_rings)(struct drm_device *dev);
1792 void (*cleanup_ring)(struct intel_engine_cs *ring);
1793 void (*stop_ring)(struct intel_engine_cs *ring);
1796 uint32_t request_uniq;
1799 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1800 * will be rejected. Instead look for a better place.
1804 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1806 return dev->dev_private;
1809 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1811 return to_i915(dev_get_drvdata(dev));
1814 /* Iterate over initialised rings */
1815 #define for_each_ring(ring__, dev_priv__, i__) \
1816 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1817 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1819 enum hdmi_force_audio {
1820 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1821 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1822 HDMI_AUDIO_AUTO, /* trust EDID */
1823 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1826 #define I915_GTT_OFFSET_NONE ((u32)-1)
1828 struct drm_i915_gem_object_ops {
1829 /* Interface between the GEM object and its backing storage.
1830 * get_pages() is called once prior to the use of the associated set
1831 * of pages before to binding them into the GTT, and put_pages() is
1832 * called after we no longer need them. As we expect there to be
1833 * associated cost with migrating pages between the backing storage
1834 * and making them available for the GPU (e.g. clflush), we may hold
1835 * onto the pages after they are no longer referenced by the GPU
1836 * in case they may be used again shortly (for example migrating the
1837 * pages to a different memory domain within the GTT). put_pages()
1838 * will therefore most likely be called when the object itself is
1839 * being released or under memory pressure (where we attempt to
1840 * reap pages for the shrinker).
1842 int (*get_pages)(struct drm_i915_gem_object *);
1843 void (*put_pages)(struct drm_i915_gem_object *);
1844 int (*dmabuf_export)(struct drm_i915_gem_object *);
1845 void (*release)(struct drm_i915_gem_object *);
1849 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1850 * considered to be the frontbuffer for the given plane interface-vise. This
1851 * doesn't mean that the hw necessarily already scans it out, but that any
1852 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1854 * We have one bit per pipe and per scanout plane type.
1856 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1857 #define INTEL_FRONTBUFFER_BITS \
1858 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1859 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1860 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1861 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1862 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1863 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1864 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1865 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1866 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1867 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1868 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1870 struct drm_i915_gem_object {
1871 struct drm_gem_object base;
1873 const struct drm_i915_gem_object_ops *ops;
1875 /** List of VMAs backed by this object */
1876 struct list_head vma_list;
1878 /** Stolen memory for this object, instead of being backed by shmem. */
1879 struct drm_mm_node *stolen;
1880 struct list_head global_list;
1882 struct list_head ring_list;
1883 /** Used in execbuf to temporarily hold a ref */
1884 struct list_head obj_exec_link;
1886 struct list_head batch_pool_list;
1889 * This is set if the object is on the active lists (has pending
1890 * rendering and so a non-zero seqno), and is not set if it i s on
1891 * inactive (ready to be unbound) list.
1893 unsigned int active:1;
1896 * This is set if the object has been written to since last bound
1899 unsigned int dirty:1;
1902 * Fence register bits (if any) for this object. Will be set
1903 * as needed when mapped into the GTT.
1904 * Protected by dev->struct_mutex.
1906 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1909 * Advice: are the backing pages purgeable?
1911 unsigned int madv:2;
1914 * Current tiling mode for the object.
1916 unsigned int tiling_mode:2;
1918 * Whether the tiling parameters for the currently associated fence
1919 * register have changed. Note that for the purposes of tracking
1920 * tiling changes we also treat the unfenced register, the register
1921 * slot that the object occupies whilst it executes a fenced
1922 * command (such as BLT on gen2/3), as a "fence".
1924 unsigned int fence_dirty:1;
1927 * Is the object at the current location in the gtt mappable and
1928 * fenceable? Used to avoid costly recalculations.
1930 unsigned int map_and_fenceable:1;
1933 * Whether the current gtt mapping needs to be mappable (and isn't just
1934 * mappable by accident). Track pin and fault separate for a more
1935 * accurate mappable working set.
1937 unsigned int fault_mappable:1;
1938 unsigned int pin_mappable:1;
1939 unsigned int pin_display:1;
1942 * Is the object to be mapped as read-only to the GPU
1943 * Only honoured if hardware has relevant pte bit
1945 unsigned long gt_ro:1;
1946 unsigned int cache_level:3;
1947 unsigned int cache_dirty:1;
1949 unsigned int has_dma_mapping:1;
1951 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1953 struct sg_table *pages;
1954 int pages_pin_count;
1956 /* prime dma-buf support */
1957 void *dma_buf_vmapping;
1960 /** Breadcrumb of last rendering to the buffer. */
1961 struct drm_i915_gem_request *last_read_req;
1962 struct drm_i915_gem_request *last_write_req;
1963 /** Breadcrumb of last fenced GPU access to the buffer. */
1964 struct drm_i915_gem_request *last_fenced_req;
1966 /** Current tiling stride for the object, if it's tiled. */
1969 /** References from framebuffers, locks out tiling changes. */
1970 unsigned long framebuffer_references;
1972 /** Record of address bit 17 of each page at last unbind. */
1973 unsigned long *bit_17;
1976 /** for phy allocated objects */
1977 struct drm_dma_handle *phys_handle;
1979 struct i915_gem_userptr {
1981 unsigned read_only :1;
1982 unsigned workers :4;
1983 #define I915_GEM_USERPTR_MAX_WORKERS 15
1985 struct i915_mm_struct *mm;
1986 struct i915_mmu_object *mmu_object;
1987 struct work_struct *work;
1991 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1993 void i915_gem_track_fb(struct drm_i915_gem_object *old,
1994 struct drm_i915_gem_object *new,
1995 unsigned frontbuffer_bits);
1998 * Request queue structure.
2000 * The request queue allows us to note sequence numbers that have been emitted
2001 * and may be associated with active buffers to be retired.
2003 * By keeping this list, we can avoid having to do questionable sequence
2004 * number comparisons on buffer last_read|write_seqno. It also allows an
2005 * emission time to be associated with the request for tracking how far ahead
2006 * of the GPU the submission is.
2008 struct drm_i915_gem_request {
2011 /** On Which ring this request was generated */
2012 struct intel_engine_cs *ring;
2014 /** GEM sequence number associated with this request. */
2017 /** Position in the ringbuffer of the start of the request */
2021 * Position in the ringbuffer of the start of the postfix.
2022 * This is required to calculate the maximum available ringbuffer
2023 * space without overwriting the postfix.
2027 /** Position in the ringbuffer of the end of the whole request */
2030 /** Context and ring buffer related to this request */
2031 struct intel_context *ctx;
2032 struct intel_ringbuffer *ringbuf;
2034 /** Batch buffer related to this request if any */
2035 struct drm_i915_gem_object *batch_obj;
2037 /** Time at which this request was emitted, in jiffies. */
2038 unsigned long emitted_jiffies;
2040 /** global list entry for this request */
2041 struct list_head list;
2043 struct drm_i915_file_private *file_priv;
2044 /** file_priv list entry for this request */
2045 struct list_head client_list;
2047 /** process identifier submitting this request */
2053 * The ELSP only accepts two elements at a time, so we queue
2054 * context/tail pairs on a given queue (ring->execlist_queue) until the
2055 * hardware is available. The queue serves a double purpose: we also use
2056 * it to keep track of the up to 2 contexts currently in the hardware
2057 * (usually one in execution and the other queued up by the GPU): We
2058 * only remove elements from the head of the queue when the hardware
2059 * informs us that an element has been completed.
2061 * All accesses to the queue are mediated by a spinlock
2062 * (ring->execlist_lock).
2065 /** Execlist link in the submission queue.*/
2066 struct list_head execlist_link;
2068 /** Execlists no. of times this request has been sent to the ELSP */
2073 void i915_gem_request_free(struct kref *req_ref);
2075 static inline uint32_t
2076 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2078 return req ? req->seqno : 0;
2081 static inline struct intel_engine_cs *
2082 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2084 return req ? req->ring : NULL;
2088 i915_gem_request_reference(struct drm_i915_gem_request *req)
2090 kref_get(&req->ref);
2094 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2096 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2097 kref_put(&req->ref, i915_gem_request_free);
2100 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2101 struct drm_i915_gem_request *src)
2104 i915_gem_request_reference(src);
2107 i915_gem_request_unreference(*pdst);
2113 * XXX: i915_gem_request_completed should be here but currently needs the
2114 * definition of i915_seqno_passed() which is below. It will be moved in
2115 * a later patch when the call to i915_seqno_passed() is obsoleted...
2118 struct drm_i915_file_private {
2119 struct drm_i915_private *dev_priv;
2120 struct drm_file *file;
2124 struct list_head request_list;
2125 struct delayed_work idle_work;
2127 struct idr context_idr;
2129 atomic_t rps_wait_boost;
2130 struct intel_engine_cs *bsd_ring;
2134 * A command that requires special handling by the command parser.
2136 struct drm_i915_cmd_descriptor {
2138 * Flags describing how the command parser processes the command.
2140 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2141 * a length mask if not set
2142 * CMD_DESC_SKIP: The command is allowed but does not follow the
2143 * standard length encoding for the opcode range in
2145 * CMD_DESC_REJECT: The command is never allowed
2146 * CMD_DESC_REGISTER: The command should be checked against the
2147 * register whitelist for the appropriate ring
2148 * CMD_DESC_MASTER: The command is allowed if the submitting process
2152 #define CMD_DESC_FIXED (1<<0)
2153 #define CMD_DESC_SKIP (1<<1)
2154 #define CMD_DESC_REJECT (1<<2)
2155 #define CMD_DESC_REGISTER (1<<3)
2156 #define CMD_DESC_BITMASK (1<<4)
2157 #define CMD_DESC_MASTER (1<<5)
2160 * The command's unique identification bits and the bitmask to get them.
2161 * This isn't strictly the opcode field as defined in the spec and may
2162 * also include type, subtype, and/or subop fields.
2170 * The command's length. The command is either fixed length (i.e. does
2171 * not include a length field) or has a length field mask. The flag
2172 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2173 * a length mask. All command entries in a command table must include
2174 * length information.
2182 * Describes where to find a register address in the command to check
2183 * against the ring's register whitelist. Only valid if flags has the
2184 * CMD_DESC_REGISTER bit set.
2191 #define MAX_CMD_DESC_BITMASKS 3
2193 * Describes command checks where a particular dword is masked and
2194 * compared against an expected value. If the command does not match
2195 * the expected value, the parser rejects it. Only valid if flags has
2196 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2199 * If the check specifies a non-zero condition_mask then the parser
2200 * only performs the check when the bits specified by condition_mask
2207 u32 condition_offset;
2209 } bits[MAX_CMD_DESC_BITMASKS];
2213 * A table of commands requiring special handling by the command parser.
2215 * Each ring has an array of tables. Each table consists of an array of command
2216 * descriptors, which must be sorted with command opcodes in ascending order.
2218 struct drm_i915_cmd_table {
2219 const struct drm_i915_cmd_descriptor *table;
2223 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2224 #define __I915__(p) ({ \
2225 struct drm_i915_private *__p; \
2226 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2227 __p = (struct drm_i915_private *)p; \
2228 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2229 __p = to_i915((struct drm_device *)p); \
2234 #define INTEL_INFO(p) (&__I915__(p)->info)
2235 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2236 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2238 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2239 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2240 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2241 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2242 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2243 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2244 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2245 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2246 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2247 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2248 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2249 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2250 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2251 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2252 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2253 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2254 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2255 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2256 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2257 INTEL_DEVID(dev) == 0x0152 || \
2258 INTEL_DEVID(dev) == 0x015a)
2259 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2260 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2261 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2262 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2263 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2264 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2265 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2266 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2267 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2268 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2269 (INTEL_DEVID(dev) & 0xf) == 0xe))
2270 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2271 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2272 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2273 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2274 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2275 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2276 /* ULX machines are also considered ULT. */
2277 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2278 INTEL_DEVID(dev) == 0x0A1E)
2279 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2281 #define SKL_REVID_A0 (0x0)
2282 #define SKL_REVID_B0 (0x1)
2283 #define SKL_REVID_C0 (0x2)
2284 #define SKL_REVID_D0 (0x3)
2285 #define SKL_REVID_E0 (0x4)
2288 * The genX designation typically refers to the render engine, so render
2289 * capability related checks should use IS_GEN, while display and other checks
2290 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2293 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2294 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2295 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2296 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2297 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2298 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2299 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2300 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2302 #define RENDER_RING (1<<RCS)
2303 #define BSD_RING (1<<VCS)
2304 #define BLT_RING (1<<BCS)
2305 #define VEBOX_RING (1<<VECS)
2306 #define BSD2_RING (1<<VCS2)
2307 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2308 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2309 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2310 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2311 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2312 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2313 __I915__(dev)->ellc_size)
2314 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2316 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2317 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2318 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2319 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2321 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2322 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2324 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2325 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2327 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2328 * even when in MSI mode. This results in spurious interrupt warnings if the
2329 * legacy irq no. is shared with another device. The kernel then disables that
2330 * interrupt source and so prevents the other device from working properly.
2332 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2333 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2335 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2336 * rows, which changed the alignment requirements and fence programming.
2338 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2340 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2341 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2342 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2343 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2344 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2346 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2347 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2348 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2350 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2352 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2353 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2354 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2355 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2357 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2358 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2359 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2360 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2362 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2363 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2364 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2365 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2366 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2367 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2368 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2369 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2371 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2372 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2373 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2374 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2375 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2376 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2377 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2379 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2381 /* DPF == dynamic parity feature */
2382 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2383 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2385 #define GT_FREQUENCY_MULTIPLIER 50
2387 #include "i915_trace.h"
2389 extern const struct drm_ioctl_desc i915_ioctls[];
2390 extern int i915_max_ioctl;
2392 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2393 extern int i915_resume_legacy(struct drm_device *dev);
2396 struct i915_params {
2398 int panel_ignore_lid;
2399 unsigned int powersave;
2401 unsigned int lvds_downclock;
2402 int lvds_channel_mode;
2404 int vbt_sdvo_panel_type;
2408 int enable_execlists;
2410 unsigned int preliminary_hw_support;
2411 int disable_power_well;
2413 int invert_brightness;
2414 int enable_cmd_parser;
2415 /* leave bools at the end to not create holes */
2416 bool enable_hangcheck;
2418 bool prefault_disable;
2420 bool disable_display;
2421 bool disable_vtd_wa;
2424 bool verbose_state_checks;
2425 bool nuclear_pageflip;
2427 extern struct i915_params i915 __read_mostly;
2430 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2431 extern int i915_driver_unload(struct drm_device *);
2432 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2433 extern void i915_driver_lastclose(struct drm_device * dev);
2434 extern void i915_driver_preclose(struct drm_device *dev,
2435 struct drm_file *file);
2436 extern void i915_driver_postclose(struct drm_device *dev,
2437 struct drm_file *file);
2438 extern int i915_driver_device_is_agp(struct drm_device * dev);
2439 #ifdef CONFIG_COMPAT
2440 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2443 extern int intel_gpu_reset(struct drm_device *dev);
2444 extern int i915_reset(struct drm_device *dev);
2445 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2446 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2447 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2448 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2449 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2450 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2453 void i915_queue_hangcheck(struct drm_device *dev);
2455 void i915_handle_error(struct drm_device *dev, bool wedged,
2456 const char *fmt, ...);
2458 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2459 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2460 int intel_irq_install(struct drm_i915_private *dev_priv);
2461 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2463 extern void intel_uncore_sanitize(struct drm_device *dev);
2464 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2465 bool restore_forcewake);
2466 extern void intel_uncore_init(struct drm_device *dev);
2467 extern void intel_uncore_check_errors(struct drm_device *dev);
2468 extern void intel_uncore_fini(struct drm_device *dev);
2469 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2470 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2471 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2472 enum forcewake_domains domains);
2473 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2474 enum forcewake_domains domains);
2475 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2476 static inline bool intel_vgpu_active(struct drm_device *dev)
2478 return to_i915(dev)->vgpu.active;
2482 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2486 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2489 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2490 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2492 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2494 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2495 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2496 uint32_t interrupt_mask,
2497 uint32_t enabled_irq_mask);
2498 #define ibx_enable_display_interrupt(dev_priv, bits) \
2499 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2500 #define ibx_disable_display_interrupt(dev_priv, bits) \
2501 ibx_display_interrupt_update((dev_priv), (bits), 0)
2504 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2505 struct drm_file *file_priv);
2506 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2507 struct drm_file *file_priv);
2508 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2509 struct drm_file *file_priv);
2510 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2511 struct drm_file *file_priv);
2512 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2513 struct drm_file *file_priv);
2514 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2515 struct drm_file *file_priv);
2516 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2517 struct drm_file *file_priv);
2518 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2519 struct intel_engine_cs *ring);
2520 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2521 struct drm_file *file,
2522 struct intel_engine_cs *ring,
2523 struct drm_i915_gem_object *obj);
2524 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2525 struct drm_file *file,
2526 struct intel_engine_cs *ring,
2527 struct intel_context *ctx,
2528 struct drm_i915_gem_execbuffer2 *args,
2529 struct list_head *vmas,
2530 struct drm_i915_gem_object *batch_obj,
2531 u64 exec_start, u32 flags);
2532 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2533 struct drm_file *file_priv);
2534 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2535 struct drm_file *file_priv);
2536 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2537 struct drm_file *file_priv);
2538 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2539 struct drm_file *file);
2540 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2541 struct drm_file *file);
2542 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2543 struct drm_file *file_priv);
2544 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2545 struct drm_file *file_priv);
2546 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2547 struct drm_file *file_priv);
2548 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2549 struct drm_file *file_priv);
2550 int i915_gem_init_userptr(struct drm_device *dev);
2551 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2552 struct drm_file *file);
2553 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2554 struct drm_file *file_priv);
2555 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2556 struct drm_file *file_priv);
2557 void i915_gem_load(struct drm_device *dev);
2558 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2561 #define I915_SHRINK_PURGEABLE 0x1
2562 #define I915_SHRINK_UNBOUND 0x2
2563 #define I915_SHRINK_BOUND 0x4
2564 void *i915_gem_object_alloc(struct drm_device *dev);
2565 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2566 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2567 const struct drm_i915_gem_object_ops *ops);
2568 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2570 void i915_init_vm(struct drm_i915_private *dev_priv,
2571 struct i915_address_space *vm);
2572 void i915_gem_free_object(struct drm_gem_object *obj);
2573 void i915_gem_vma_destroy(struct i915_vma *vma);
2575 #define PIN_MAPPABLE 0x1
2576 #define PIN_NONBLOCK 0x2
2577 #define PIN_GLOBAL 0x4
2578 #define PIN_OFFSET_BIAS 0x8
2579 #define PIN_OFFSET_MASK (~4095)
2580 int __must_check i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
2581 struct i915_address_space *vm,
2584 const struct i915_ggtt_view *view);
2586 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2587 struct i915_address_space *vm,
2591 return i915_gem_object_pin_view(obj, vm, alignment, flags,
2592 &i915_ggtt_view_normal);
2595 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2597 int __must_check i915_vma_unbind(struct i915_vma *vma);
2598 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2599 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2600 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2602 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2603 int *needs_clflush);
2605 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2606 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2608 struct sg_page_iter sg_iter;
2610 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2611 return sg_page_iter_page(&sg_iter);
2615 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2617 BUG_ON(obj->pages == NULL);
2618 obj->pages_pin_count++;
2620 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2622 BUG_ON(obj->pages_pin_count == 0);
2623 obj->pages_pin_count--;
2626 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2627 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2628 struct intel_engine_cs *to);
2629 void i915_vma_move_to_active(struct i915_vma *vma,
2630 struct intel_engine_cs *ring);
2631 int i915_gem_dumb_create(struct drm_file *file_priv,
2632 struct drm_device *dev,
2633 struct drm_mode_create_dumb *args);
2634 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2635 uint32_t handle, uint64_t *offset);
2637 * Returns true if seq1 is later than seq2.
2640 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2642 return (int32_t)(seq1 - seq2) >= 0;
2645 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2646 bool lazy_coherency)
2650 BUG_ON(req == NULL);
2652 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2654 return i915_seqno_passed(seqno, req->seqno);
2657 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2658 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2659 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2660 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2662 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2663 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2665 struct drm_i915_gem_request *
2666 i915_gem_find_active_request(struct intel_engine_cs *ring);
2668 bool i915_gem_retire_requests(struct drm_device *dev);
2669 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2670 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2671 bool interruptible);
2672 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
2674 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2676 return unlikely(atomic_read(&error->reset_counter)
2677 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2680 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2682 return atomic_read(&error->reset_counter) & I915_WEDGED;
2685 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2687 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2690 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2692 return dev_priv->gpu_error.stop_rings == 0 ||
2693 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2696 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2698 return dev_priv->gpu_error.stop_rings == 0 ||
2699 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2702 void i915_gem_reset(struct drm_device *dev);
2703 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2704 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2705 int __must_check i915_gem_init(struct drm_device *dev);
2706 int i915_gem_init_rings(struct drm_device *dev);
2707 int __must_check i915_gem_init_hw(struct drm_device *dev);
2708 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2709 void i915_gem_init_swizzling(struct drm_device *dev);
2710 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2711 int __must_check i915_gpu_idle(struct drm_device *dev);
2712 int __must_check i915_gem_suspend(struct drm_device *dev);
2713 int __i915_add_request(struct intel_engine_cs *ring,
2714 struct drm_file *file,
2715 struct drm_i915_gem_object *batch_obj);
2716 #define i915_add_request(ring) \
2717 __i915_add_request(ring, NULL, NULL)
2718 int __i915_wait_request(struct drm_i915_gem_request *req,
2719 unsigned reset_counter,
2722 struct drm_i915_file_private *file_priv);
2723 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2724 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2726 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2729 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2731 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2733 struct intel_engine_cs *pipelined);
2734 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2735 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2737 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2738 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2741 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2743 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2744 int tiling_mode, bool fenced);
2746 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2747 enum i915_cache_level cache_level);
2749 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2750 struct dma_buf *dma_buf);
2752 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2753 struct drm_gem_object *gem_obj, int flags);
2755 void i915_gem_restore_fences(struct drm_device *dev);
2757 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o,
2758 struct i915_address_space *vm,
2759 enum i915_ggtt_view_type view);
2761 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2762 struct i915_address_space *vm)
2764 return i915_gem_obj_offset_view(o, vm, I915_GGTT_VIEW_NORMAL);
2766 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2767 bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o,
2768 struct i915_address_space *vm,
2769 enum i915_ggtt_view_type view);
2771 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2772 struct i915_address_space *vm)
2774 return i915_gem_obj_bound_view(o, vm, I915_GGTT_VIEW_NORMAL);
2777 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2778 struct i915_address_space *vm);
2779 struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj,
2780 struct i915_address_space *vm,
2781 const struct i915_ggtt_view *view);
2783 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2784 struct i915_address_space *vm)
2786 return i915_gem_obj_to_vma_view(obj, vm, &i915_ggtt_view_normal);
2790 i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj,
2791 struct i915_address_space *vm,
2792 const struct i915_ggtt_view *view);
2796 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2797 struct i915_address_space *vm)
2799 return i915_gem_obj_lookup_or_create_vma_view(obj, vm,
2800 &i915_ggtt_view_normal);
2803 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2804 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2805 struct i915_vma *vma;
2806 list_for_each_entry(vma, &obj->vma_list, vma_link)
2807 if (vma->pin_count > 0)
2812 /* Some GGTT VM helpers */
2813 #define i915_obj_to_ggtt(obj) \
2814 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2815 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2817 struct i915_address_space *ggtt =
2818 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2822 static inline struct i915_hw_ppgtt *
2823 i915_vm_to_ppgtt(struct i915_address_space *vm)
2825 WARN_ON(i915_is_ggtt(vm));
2827 return container_of(vm, struct i915_hw_ppgtt, base);
2831 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2833 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
2836 static inline unsigned long
2837 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2839 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
2842 static inline unsigned long
2843 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2845 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2848 static inline int __must_check
2849 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2853 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2854 alignment, flags | PIN_GLOBAL);
2858 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2860 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2863 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2865 /* i915_gem_context.c */
2866 int __must_check i915_gem_context_init(struct drm_device *dev);
2867 void i915_gem_context_fini(struct drm_device *dev);
2868 void i915_gem_context_reset(struct drm_device *dev);
2869 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2870 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2871 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2872 int i915_switch_context(struct intel_engine_cs *ring,
2873 struct intel_context *to);
2874 struct intel_context *
2875 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2876 void i915_gem_context_free(struct kref *ctx_ref);
2877 struct drm_i915_gem_object *
2878 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
2879 static inline void i915_gem_context_reference(struct intel_context *ctx)
2881 kref_get(&ctx->ref);
2884 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2886 kref_put(&ctx->ref, i915_gem_context_free);
2889 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2891 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2894 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2895 struct drm_file *file);
2896 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2897 struct drm_file *file);
2898 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2899 struct drm_file *file_priv);
2900 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2901 struct drm_file *file_priv);
2903 /* i915_gem_evict.c */
2904 int __must_check i915_gem_evict_something(struct drm_device *dev,
2905 struct i915_address_space *vm,
2908 unsigned cache_level,
2909 unsigned long start,
2912 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2913 int i915_gem_evict_everything(struct drm_device *dev);
2915 /* belongs in i915_gem_gtt.h */
2916 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2918 if (INTEL_INFO(dev)->gen < 6)
2919 intel_gtt_chipset_flush();
2922 /* i915_gem_stolen.c */
2923 int i915_gem_init_stolen(struct drm_device *dev);
2924 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2925 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2926 void i915_gem_cleanup_stolen(struct drm_device *dev);
2927 struct drm_i915_gem_object *
2928 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2929 struct drm_i915_gem_object *
2930 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2935 /* i915_gem_tiling.c */
2936 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2938 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2940 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2941 obj->tiling_mode != I915_TILING_NONE;
2944 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2945 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2946 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2948 /* i915_gem_debug.c */
2950 int i915_verify_lists(struct drm_device *dev);
2952 #define i915_verify_lists(dev) 0
2955 /* i915_debugfs.c */
2956 int i915_debugfs_init(struct drm_minor *minor);
2957 void i915_debugfs_cleanup(struct drm_minor *minor);
2958 #ifdef CONFIG_DEBUG_FS
2959 void intel_display_crc_init(struct drm_device *dev);
2961 static inline void intel_display_crc_init(struct drm_device *dev) {}
2964 /* i915_gpu_error.c */
2966 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2967 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2968 const struct i915_error_state_file_priv *error);
2969 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2970 struct drm_i915_private *i915,
2971 size_t count, loff_t pos);
2972 static inline void i915_error_state_buf_release(
2973 struct drm_i915_error_state_buf *eb)
2977 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2978 const char *error_msg);
2979 void i915_error_state_get(struct drm_device *dev,
2980 struct i915_error_state_file_priv *error_priv);
2981 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2982 void i915_destroy_error_state(struct drm_device *dev);
2984 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2985 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2987 /* i915_gem_batch_pool.c */
2988 void i915_gem_batch_pool_init(struct drm_device *dev,
2989 struct i915_gem_batch_pool *pool);
2990 void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool);
2991 struct drm_i915_gem_object*
2992 i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size);
2994 /* i915_cmd_parser.c */
2995 int i915_cmd_parser_get_version(void);
2996 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2997 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2998 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2999 int i915_parse_cmds(struct intel_engine_cs *ring,
3000 struct drm_i915_gem_object *batch_obj,
3001 struct drm_i915_gem_object *shadow_batch_obj,
3002 u32 batch_start_offset,
3006 /* i915_suspend.c */
3007 extern int i915_save_state(struct drm_device *dev);
3008 extern int i915_restore_state(struct drm_device *dev);
3011 void i915_setup_sysfs(struct drm_device *dev_priv);
3012 void i915_teardown_sysfs(struct drm_device *dev_priv);
3015 extern int intel_setup_gmbus(struct drm_device *dev);
3016 extern void intel_teardown_gmbus(struct drm_device *dev);
3017 static inline bool intel_gmbus_is_port_valid(unsigned port)
3019 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
3022 extern struct i2c_adapter *intel_gmbus_get_adapter(
3023 struct drm_i915_private *dev_priv, unsigned port);
3024 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3025 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3026 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3028 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3030 extern void intel_i2c_reset(struct drm_device *dev);
3032 /* intel_opregion.c */
3034 extern int intel_opregion_setup(struct drm_device *dev);
3035 extern void intel_opregion_init(struct drm_device *dev);
3036 extern void intel_opregion_fini(struct drm_device *dev);
3037 extern void intel_opregion_asle_intr(struct drm_device *dev);
3038 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3040 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3043 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3044 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3045 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3046 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3048 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3053 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3061 extern void intel_register_dsm_handler(void);
3062 extern void intel_unregister_dsm_handler(void);
3064 static inline void intel_register_dsm_handler(void) { return; }
3065 static inline void intel_unregister_dsm_handler(void) { return; }
3066 #endif /* CONFIG_ACPI */
3069 extern void intel_modeset_init_hw(struct drm_device *dev);
3070 extern void intel_modeset_init(struct drm_device *dev);
3071 extern void intel_modeset_gem_init(struct drm_device *dev);
3072 extern void intel_modeset_cleanup(struct drm_device *dev);
3073 extern void intel_connector_unregister(struct intel_connector *);
3074 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3075 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3076 bool force_restore);
3077 extern void i915_redisable_vga(struct drm_device *dev);
3078 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3079 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3080 extern void intel_init_pch_refclk(struct drm_device *dev);
3081 extern void intel_set_rps(struct drm_device *dev, u8 val);
3082 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3084 extern void intel_detect_pch(struct drm_device *dev);
3085 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3086 extern int intel_enable_rc6(const struct drm_device *dev);
3088 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3089 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3090 struct drm_file *file);
3091 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3092 struct drm_file *file);
3095 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3096 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3097 struct intel_overlay_error_state *error);
3099 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3100 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3101 struct drm_device *dev,
3102 struct intel_display_error_state *error);
3104 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3105 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3107 /* intel_sideband.c */
3108 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3109 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3110 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3111 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3112 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3113 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3114 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3115 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3116 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3117 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3118 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3119 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3120 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3121 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3122 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3123 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3124 enum intel_sbi_destination destination);
3125 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3126 enum intel_sbi_destination destination);
3127 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3128 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3130 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3131 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3133 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3134 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3136 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3137 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3138 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3139 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3141 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3142 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3143 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3144 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3146 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3147 * will be implemented using 2 32-bit writes in an arbitrary order with
3148 * an arbitrary delay between them. This can cause the hardware to
3149 * act upon the intermediate value, possibly leading to corruption and
3150 * machine death. You have been warned.
3152 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3153 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3155 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3156 u32 upper = I915_READ(upper_reg); \
3157 u32 lower = I915_READ(lower_reg); \
3158 u32 tmp = I915_READ(upper_reg); \
3159 if (upper != tmp) { \
3161 lower = I915_READ(lower_reg); \
3162 WARN_ON(I915_READ(upper_reg) != upper); \
3164 (u64)upper << 32 | lower; })
3166 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3167 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3169 /* "Broadcast RGB" property */
3170 #define INTEL_BROADCAST_RGB_AUTO 0
3171 #define INTEL_BROADCAST_RGB_FULL 1
3172 #define INTEL_BROADCAST_RGB_LIMITED 2
3174 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3176 if (IS_VALLEYVIEW(dev))
3177 return VLV_VGACNTRL;
3178 else if (INTEL_INFO(dev)->gen >= 5)
3179 return CPU_VGACNTRL;
3184 static inline void __user *to_user_ptr(u64 address)
3186 return (void __user *)(uintptr_t)address;
3189 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3191 unsigned long j = msecs_to_jiffies(m);
3193 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3196 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3198 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3201 static inline unsigned long
3202 timespec_to_jiffies_timeout(const struct timespec *value)
3204 unsigned long j = timespec_to_jiffies(value);
3206 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3210 * If you need to wait X milliseconds between events A and B, but event B
3211 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3212 * when event A happened, then just before event B you call this function and
3213 * pass the timestamp as the first argument, and X as the second argument.
3216 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3218 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3221 * Don't re-read the value of "jiffies" every time since it may change
3222 * behind our back and break the math.
3224 tmp_jiffies = jiffies;
3225 target_jiffies = timestamp_jiffies +
3226 msecs_to_jiffies_timeout(to_wait_ms);
3228 if (time_after(target_jiffies, tmp_jiffies)) {
3229 remaining_jiffies = target_jiffies - tmp_jiffies;
3230 while (remaining_jiffies)
3232 schedule_timeout_uninterruptible(remaining_jiffies);
3236 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3237 struct drm_i915_gem_request *req)
3239 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3240 i915_gem_request_assign(&ring->trace_irq_req, req);