drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33 #include <linux/shmem_fs.h>
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-buf.h>
  38
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  42                                                     unsigned alignment,
  43                                                     bool map_and_fenceable,
  44                                                     bool nonblocking);
  45 static int i915_gem_phys_pwrite(struct drm_device *dev,
  46                                 struct drm_i915_gem_object *obj,
  47                                 struct drm_i915_gem_pwrite *args,
  48                                 struct drm_file *file);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  57                                     struct shrink_control *sc);
  58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  61
  62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  63 {
  64         if (obj->tiling_mode)
  65                 i915_gem_release_mmap(obj);
  66
  67         /* As we do not have an associated fence register, we will force
  68          * a tiling change if we ever need to acquire one.
  69          */
  70         obj->fence_dirty = false;
  71         obj->fence_reg = I915_FENCE_REG_NONE;
  72 }
  73
  74 /* some bookkeeping */
  75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  76                                   size_t size)
  77 {
  78         dev_priv->mm.object_count++;
  79         dev_priv->mm.object_memory += size;
  80 }
  81
  82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  83                                      size_t size)
  84 {
  85         dev_priv->mm.object_count--;
  86         dev_priv->mm.object_memory -= size;
  87 }
  88
  89 static int
  90 i915_gem_wait_for_error(struct i915_gpu_error *error)
  91 {
  92         int ret;
  93
  94 #define EXIT_COND (!i915_reset_in_progress(error) || \
  95                    i915_terminally_wedged(error))
  96         if (EXIT_COND)
  97                 return 0;
  98
  99         /*
 100          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 101          * userspace. If it takes that long something really bad is going on and
 102          * we should simply try to bail out and fail as gracefully as possible.
 103          */
 104         ret = wait_event_interruptible_timeout(error->reset_queue,
 105                                                EXIT_COND,
 106                                                10*HZ);
 107         if (ret == 0) {
 108                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 109                 return -EIO;
 110         } else if (ret < 0) {
 111                 return ret;
 112         }
 113 #undef EXIT_COND
 114
 115         return 0;
 116 }
 117
 118 int i915_mutex_lock_interruptible(struct drm_device *dev)
 119 {
 120         struct drm_i915_private *dev_priv = dev->dev_private;
 121         int ret;
 122
 123         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 124         if (ret)
 125                 return ret;
 126
 127         ret = mutex_lock_interruptible(&dev->struct_mutex);
 128         if (ret)
 129                 return ret;
 130
 131         WARN_ON(i915_verify_lists(dev));
 132         return 0;
 133 }
 134
 135 static inline bool
 136 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 137 {
 138         return i915_gem_obj_ggtt_bound(obj) && !obj->active;
 139 }
 140
 141 int
 142 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 143                     struct drm_file *file)
 144 {
 145         struct drm_i915_private *dev_priv = dev->dev_private;
 146         struct drm_i915_gem_init *args = data;
 147
 148         if (drm_core_check_feature(dev, DRIVER_MODESET))
 149                 return -ENODEV;
 150
 151         if (args->gtt_start >= args->gtt_end ||
 152             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 153                 return -EINVAL;
 154
 155         /* GEM with user mode setting was never supported on ilk and later. */
 156         if (INTEL_INFO(dev)->gen >= 5)
 157                 return -ENODEV;
 158
 159         mutex_lock(&dev->struct_mutex);
 160         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 161                                   args->gtt_end);
 162         dev_priv->gtt.mappable_end = args->gtt_end;
 163         mutex_unlock(&dev->struct_mutex);
 164
 165         return 0;
 166 }
 167
 168 int
 169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 170                             struct drm_file *file)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct drm_i915_gem_get_aperture *args = data;
 174         struct drm_i915_gem_object *obj;
 175         size_t pinned;
 176
 177         pinned = 0;
 178         mutex_lock(&dev->struct_mutex);
 179         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 180                 if (obj->pin_count)
 181                         pinned += i915_gem_obj_ggtt_size(obj);
 182         mutex_unlock(&dev->struct_mutex);
 183
 184         args->aper_size = dev_priv->gtt.base.total;
 185         args->aper_available_size = args->aper_size - pinned;
 186
 187         return 0;
 188 }
 189
 190 void *i915_gem_object_alloc(struct drm_device *dev)
 191 {
 192         struct drm_i915_private *dev_priv = dev->dev_private;
 193         return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
 194 }
 195
 196 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 197 {
 198         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 199         kmem_cache_free(dev_priv->slab, obj);
 200 }
 201
 202 static int
 203 i915_gem_create(struct drm_file *file,
 204                 struct drm_device *dev,
 205                 uint64_t size,
 206                 uint32_t *handle_p)
 207 {
 208         struct drm_i915_gem_object *obj;
 209         int ret;
 210         u32 handle;
 211
 212         size = roundup(size, PAGE_SIZE);
 213         if (size == 0)
 214                 return -EINVAL;
 215
 216         /* Allocate the new object */
 217         obj = i915_gem_alloc_object(dev, size);
 218         if (obj == NULL)
 219                 return -ENOMEM;
 220
 221         ret = drm_gem_handle_create(file, &obj->base, &handle);
 222         /* drop reference from allocate - handle holds it now */
 223         drm_gem_object_unreference_unlocked(&obj->base);
 224         if (ret)
 225                 return ret;
 226
 227         *handle_p = handle;
 228         return 0;
 229 }
 230
 231 int
 232 i915_gem_dumb_create(struct drm_file *file,
 233                      struct drm_device *dev,
 234                      struct drm_mode_create_dumb *args)
 235 {
 236         /* have to work out size/pitch and return them */
 237         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 238         args->size = args->pitch * args->height;
 239         return i915_gem_create(file, dev,
 240                                args->size, &args->handle);
 241 }
 242
 243 int i915_gem_dumb_destroy(struct drm_file *file,
 244                           struct drm_device *dev,
 245                           uint32_t handle)
 246 {
 247         return drm_gem_handle_delete(file, handle);
 248 }
 249
 250 /**
 251  * Creates a new mm object and returns a handle to it.
 252  */
 253 int
 254 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 255                       struct drm_file *file)
 256 {
 257         struct drm_i915_gem_create *args = data;
 258
 259         return i915_gem_create(file, dev,
 260                                args->size, &args->handle);
 261 }
 262
 263 static inline int
 264 __copy_to_user_swizzled(char __user *cpu_vaddr,
 265                         const char *gpu_vaddr, int gpu_offset,
 266                         int length)
 267 {
 268         int ret, cpu_offset = 0;
 269
 270         while (length > 0) {
 271                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 272                 int this_length = min(cacheline_end - gpu_offset, length);
 273                 int swizzled_gpu_offset = gpu_offset ^ 64;
 274
 275                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 276                                      gpu_vaddr + swizzled_gpu_offset,
 277                                      this_length);
 278                 if (ret)
 279                         return ret + length;
 280
 281                 cpu_offset += this_length;
 282                 gpu_offset += this_length;
 283                 length -= this_length;
 284         }
 285
 286         return 0;
 287 }
 288
 289 static inline int
 290 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 291                           const char __user *cpu_vaddr,
 292                           int length)
 293 {
 294         int ret, cpu_offset = 0;
 295
 296         while (length > 0) {
 297                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 298                 int this_length = min(cacheline_end - gpu_offset, length);
 299                 int swizzled_gpu_offset = gpu_offset ^ 64;
 300
 301                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 302                                        cpu_vaddr + cpu_offset,
 303                                        this_length);
 304                 if (ret)
 305                         return ret + length;
 306
 307                 cpu_offset += this_length;
 308                 gpu_offset += this_length;
 309                 length -= this_length;
 310         }
 311
 312         return 0;
 313 }
 314
 315 /* Per-page copy function for the shmem pread fastpath.
 316  * Flushes invalid cachelines before reading the target if
 317  * needs_clflush is set. */
 318 static int
 319 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 320                  char __user *user_data,
 321                  bool page_do_bit17_swizzling, bool needs_clflush)
 322 {
 323         char *vaddr;
 324         int ret;
 325
 326         if (unlikely(page_do_bit17_swizzling))
 327                 return -EINVAL;
 328
 329         vaddr = kmap_atomic(page);
 330         if (needs_clflush)
 331                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 332                                        page_length);
 333         ret = __copy_to_user_inatomic(user_data,
 334                                       vaddr + shmem_page_offset,
 335                                       page_length);
 336         kunmap_atomic(vaddr);
 337
 338         return ret ? -EFAULT : 0;
 339 }
 340
 341 static void
 342 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 343                              bool swizzled)
 344 {
 345         if (unlikely(swizzled)) {
 346                 unsigned long start = (unsigned long) addr;
 347                 unsigned long end = (unsigned long) addr + length;
 348
 349                 /* For swizzling simply ensure that we always flush both
 350                  * channels. Lame, but simple and it works. Swizzled
 351                  * pwrite/pread is far from a hotpath - current userspace
 352                  * doesn't use it at all. */
 353                 start = round_down(start, 128);
 354                 end = round_up(end, 128);
 355
 356                 drm_clflush_virt_range((void *)start, end - start);
 357         } else {
 358                 drm_clflush_virt_range(addr, length);
 359         }
 360
 361 }
 362
 363 /* Only difference to the fast-path function is that this can handle bit17
 364  * and uses non-atomic copy and kmap functions. */
 365 static int
 366 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 367                  char __user *user_data,
 368                  bool page_do_bit17_swizzling, bool needs_clflush)
 369 {
 370         char *vaddr;
 371         int ret;
 372
 373         vaddr = kmap(page);
 374         if (needs_clflush)
 375                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 376                                              page_length,
 377                                              page_do_bit17_swizzling);
 378
 379         if (page_do_bit17_swizzling)
 380                 ret = __copy_to_user_swizzled(user_data,
 381                                               vaddr, shmem_page_offset,
 382                                               page_length);
 383         else
 384                 ret = __copy_to_user(user_data,
 385                                      vaddr + shmem_page_offset,
 386                                      page_length);
 387         kunmap(page);
 388
 389         return ret ? - EFAULT : 0;
 390 }
 391
 392 static int
 393 i915_gem_shmem_pread(struct drm_device *dev,
 394                      struct drm_i915_gem_object *obj,
 395                      struct drm_i915_gem_pread *args,
 396                      struct drm_file *file)
 397 {
 398         char __user *user_data;
 399         ssize_t remain;
 400         loff_t offset;
 401         int shmem_page_offset, page_length, ret = 0;
 402         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 403         int prefaulted = 0;
 404         int needs_clflush = 0;
 405         struct sg_page_iter sg_iter;
 406
 407         user_data = to_user_ptr(args->data_ptr);
 408         remain = args->size;
 409
 410         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 411
 412         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 413                 /* If we're not in the cpu read domain, set ourself into the gtt
 414                  * read domain and manually flush cachelines (if required). This
 415                  * optimizes for the case when the gpu will dirty the data
 416                  * anyway again before the next pread happens. */
 417                 if (obj->cache_level == I915_CACHE_NONE)
 418                         needs_clflush = 1;
 419                 if (i915_gem_obj_ggtt_bound(obj)) {
 420                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 421                         if (ret)
 422                                 return ret;
 423                 }
 424         }
 425
 426         ret = i915_gem_object_get_pages(obj);
 427         if (ret)
 428                 return ret;
 429
 430         i915_gem_object_pin_pages(obj);
 431
 432         offset = args->offset;
 433
 434         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 435                          offset >> PAGE_SHIFT) {
 436                 struct page *page = sg_page_iter_page(&sg_iter);
 437
 438                 if (remain <= 0)
 439                         break;
 440
 441                 /* Operation in this page
 442                  *
 443                  * shmem_page_offset = offset within page in shmem file
 444                  * page_length = bytes to copy for this page
 445                  */
 446                 shmem_page_offset = offset_in_page(offset);
 447                 page_length = remain;
 448                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 449                         page_length = PAGE_SIZE - shmem_page_offset;
 450
 451                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 452                         (page_to_phys(page) & (1 << 17)) != 0;
 453
 454                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 455                                        user_data, page_do_bit17_swizzling,
 456                                        needs_clflush);
 457                 if (ret == 0)
 458                         goto next_page;
 459
 460                 mutex_unlock(&dev->struct_mutex);
 461
 462                 if (likely(!i915_prefault_disable) && !prefaulted) {
 463                         ret = fault_in_multipages_writeable(user_data, remain);
 464                         /* Userspace is tricking us, but we've already clobbered
 465                          * its pages with the prefault and promised to write the
 466                          * data up to the first fault. Hence ignore any errors
 467                          * and just continue. */
 468                         (void)ret;
 469                         prefaulted = 1;
 470                 }
 471
 472                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 473                                        user_data, page_do_bit17_swizzling,
 474                                        needs_clflush);
 475
 476                 mutex_lock(&dev->struct_mutex);
 477
 478 next_page:
 479                 mark_page_accessed(page);
 480
 481                 if (ret)
 482                         goto out;
 483
 484                 remain -= page_length;
 485                 user_data += page_length;
 486                 offset += page_length;
 487         }
 488
 489 out:
 490         i915_gem_object_unpin_pages(obj);
 491
 492         return ret;
 493 }
 494
 495 /**
 496  * Reads data from the object referenced by handle.
 497  *
 498  * On error, the contents of *data are undefined.
 499  */
 500 int
 501 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 502                      struct drm_file *file)
 503 {
 504         struct drm_i915_gem_pread *args = data;
 505         struct drm_i915_gem_object *obj;
 506         int ret = 0;
 507
 508         if (args->size == 0)
 509                 return 0;
 510
 511         if (!access_ok(VERIFY_WRITE,
 512                        to_user_ptr(args->data_ptr),
 513                        args->size))
 514                 return -EFAULT;
 515
 516         ret = i915_mutex_lock_interruptible(dev);
 517         if (ret)
 518                 return ret;
 519
 520         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 521         if (&obj->base == NULL) {
 522                 ret = -ENOENT;
 523                 goto unlock;
 524         }
 525
 526         /* Bounds check source.  */
 527         if (args->offset > obj->base.size ||
 528             args->size > obj->base.size - args->offset) {
 529                 ret = -EINVAL;
 530                 goto out;
 531         }
 532
 533         /* prime objects have no backing filp to GEM pread/pwrite
 534          * pages from.
 535          */
 536         if (!obj->base.filp) {
 537                 ret = -EINVAL;
 538                 goto out;
 539         }
 540
 541         trace_i915_gem_object_pread(obj, args->offset, args->size);
 542
 543         ret = i915_gem_shmem_pread(dev, obj, args, file);
 544
 545 out:
 546         drm_gem_object_unreference(&obj->base);
 547 unlock:
 548         mutex_unlock(&dev->struct_mutex);
 549         return ret;
 550 }
 551
 552 /* This is the fast write path which cannot handle
 553  * page faults in the source data
 554  */
 555
 556 static inline int
 557 fast_user_write(struct io_mapping *mapping,
 558                 loff_t page_base, int page_offset,
 559                 char __user *user_data,
 560                 int length)
 561 {
 562         void __iomem *vaddr_atomic;
 563         void *vaddr;
 564         unsigned long unwritten;
 565
 566         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 567         /* We can use the cpu mem copy function because this is X86. */
 568         vaddr = (void __force*)vaddr_atomic + page_offset;
 569         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 570                                                       user_data, length);
 571         io_mapping_unmap_atomic(vaddr_atomic);
 572         return unwritten;
 573 }
 574
 575 /**
 576  * This is the fast pwrite path, where we copy the data directly from the
 577  * user into the GTT, uncached.
 578  */
 579 static int
 580 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 581                          struct drm_i915_gem_object *obj,
 582                          struct drm_i915_gem_pwrite *args,
 583                          struct drm_file *file)
 584 {
 585         drm_i915_private_t *dev_priv = dev->dev_private;
 586         ssize_t remain;
 587         loff_t offset, page_base;
 588         char __user *user_data;
 589         int page_offset, page_length, ret;
 590
 591         ret = i915_gem_object_pin(obj, 0, true, true);
 592         if (ret)
 593                 goto out;
 594
 595         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 596         if (ret)
 597                 goto out_unpin;
 598
 599         ret = i915_gem_object_put_fence(obj);
 600         if (ret)
 601                 goto out_unpin;
 602
 603         user_data = to_user_ptr(args->data_ptr);
 604         remain = args->size;
 605
 606         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 607
 608         while (remain > 0) {
 609                 /* Operation in this page
 610                  *
 611                  * page_base = page offset within aperture
 612                  * page_offset = offset within page
 613                  * page_length = bytes to copy for this page
 614                  */
 615                 page_base = offset & PAGE_MASK;
 616                 page_offset = offset_in_page(offset);
 617                 page_length = remain;
 618                 if ((page_offset + remain) > PAGE_SIZE)
 619                         page_length = PAGE_SIZE - page_offset;
 620
 621                 /* If we get a fault while copying data, then (presumably) our
 622                  * source page isn't available.  Return the error and we'll
 623                  * retry in the slow path.
 624                  */
 625                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 626                                     page_offset, user_data, page_length)) {
 627                         ret = -EFAULT;
 628                         goto out_unpin;
 629                 }
 630
 631                 remain -= page_length;
 632                 user_data += page_length;
 633                 offset += page_length;
 634         }
 635
 636 out_unpin:
 637         i915_gem_object_unpin(obj);
 638 out:
 639         return ret;
 640 }
 641
 642 /* Per-page copy function for the shmem pwrite fastpath.
 643  * Flushes invalid cachelines before writing to the target if
 644  * needs_clflush_before is set and flushes out any written cachelines after
 645  * writing if needs_clflush is set. */
 646 static int
 647 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 648                   char __user *user_data,
 649                   bool page_do_bit17_swizzling,
 650                   bool needs_clflush_before,
 651                   bool needs_clflush_after)
 652 {
 653         char *vaddr;
 654         int ret;
 655
 656         if (unlikely(page_do_bit17_swizzling))
 657                 return -EINVAL;
 658
 659         vaddr = kmap_atomic(page);
 660         if (needs_clflush_before)
 661                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 662                                        page_length);
 663         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
 664                                                 user_data,
 665                                                 page_length);
 666         if (needs_clflush_after)
 667                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 668                                        page_length);
 669         kunmap_atomic(vaddr);
 670
 671         return ret ? -EFAULT : 0;
 672 }
 673
 674 /* Only difference to the fast-path function is that this can handle bit17
 675  * and uses non-atomic copy and kmap functions. */
 676 static int
 677 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 678                   char __user *user_data,
 679                   bool page_do_bit17_swizzling,
 680                   bool needs_clflush_before,
 681                   bool needs_clflush_after)
 682 {
 683         char *vaddr;
 684         int ret;
 685
 686         vaddr = kmap(page);
 687         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 688                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 689                                              page_length,
 690                                              page_do_bit17_swizzling);
 691         if (page_do_bit17_swizzling)
 692                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 693                                                 user_data,
 694                                                 page_length);
 695         else
 696                 ret = __copy_from_user(vaddr + shmem_page_offset,
 697                                        user_data,
 698                                        page_length);
 699         if (needs_clflush_after)
 700                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 701                                              page_length,
 702                                              page_do_bit17_swizzling);
 703         kunmap(page);
 704
 705         return ret ? -EFAULT : 0;
 706 }
 707
 708 static int
 709 i915_gem_shmem_pwrite(struct drm_device *dev,
 710                       struct drm_i915_gem_object *obj,
 711                       struct drm_i915_gem_pwrite *args,
 712                       struct drm_file *file)
 713 {
 714         ssize_t remain;
 715         loff_t offset;
 716         char __user *user_data;
 717         int shmem_page_offset, page_length, ret = 0;
 718         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 719         int hit_slowpath = 0;
 720         int needs_clflush_after = 0;
 721         int needs_clflush_before = 0;
 722         struct sg_page_iter sg_iter;
 723
 724         user_data = to_user_ptr(args->data_ptr);
 725         remain = args->size;
 726
 727         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 728
 729         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 730                 /* If we're not in the cpu write domain, set ourself into the gtt
 731                  * write domain and manually flush cachelines (if required). This
 732                  * optimizes for the case when the gpu will use the data
 733                  * right away and we therefore have to clflush anyway. */
 734                 if (obj->cache_level == I915_CACHE_NONE)
 735                         needs_clflush_after = 1;
 736                 if (i915_gem_obj_ggtt_bound(obj)) {
 737                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 738                         if (ret)
 739                                 return ret;
 740                 }
 741         }
 742         /* Same trick applies for invalidate partially written cachelines before
 743          * writing.  */
 744         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
 745             && obj->cache_level == I915_CACHE_NONE)
 746                 needs_clflush_before = 1;
 747
 748         ret = i915_gem_object_get_pages(obj);
 749         if (ret)
 750                 return ret;
 751
 752         i915_gem_object_pin_pages(obj);
 753
 754         offset = args->offset;
 755         obj->dirty = 1;
 756
 757         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 758                          offset >> PAGE_SHIFT) {
 759                 struct page *page = sg_page_iter_page(&sg_iter);
 760                 int partial_cacheline_write;
 761
 762                 if (remain <= 0)
 763                         break;
 764
 765                 /* Operation in this page
 766                  *
 767                  * shmem_page_offset = offset within page in shmem file
 768                  * page_length = bytes to copy for this page
 769                  */
 770                 shmem_page_offset = offset_in_page(offset);
 771
 772                 page_length = remain;
 773                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 774                         page_length = PAGE_SIZE - shmem_page_offset;
 775
 776                 /* If we don't overwrite a cacheline completely we need to be
 777                  * careful to have up-to-date data by first clflushing. Don't
 778                  * overcomplicate things and flush the entire patch. */
 779                 partial_cacheline_write = needs_clflush_before &&
 780                         ((shmem_page_offset | page_length)
 781                                 & (boot_cpu_data.x86_clflush_size - 1));
 782
 783                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 784                         (page_to_phys(page) & (1 << 17)) != 0;
 785
 786                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 787                                         user_data, page_do_bit17_swizzling,
 788                                         partial_cacheline_write,
 789                                         needs_clflush_after);
 790                 if (ret == 0)
 791                         goto next_page;
 792
 793                 hit_slowpath = 1;
 794                 mutex_unlock(&dev->struct_mutex);
 795                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 796                                         user_data, page_do_bit17_swizzling,
 797                                         partial_cacheline_write,
 798                                         needs_clflush_after);
 799
 800                 mutex_lock(&dev->struct_mutex);
 801
 802 next_page:
 803                 set_page_dirty(page);
 804                 mark_page_accessed(page);
 805
 806                 if (ret)
 807                         goto out;
 808
 809                 remain -= page_length;
 810                 user_data += page_length;
 811                 offset += page_length;
 812         }
 813
 814 out:
 815         i915_gem_object_unpin_pages(obj);
 816
 817         if (hit_slowpath) {
 818                 /*
 819                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 820                  * cachelines in-line while writing and the object moved
 821                  * out of the cpu write domain while we've dropped the lock.
 822                  */
 823                 if (!needs_clflush_after &&
 824                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 825                         i915_gem_clflush_object(obj);
 826                         i915_gem_chipset_flush(dev);
 827                 }
 828         }
 829
 830         if (needs_clflush_after)
 831                 i915_gem_chipset_flush(dev);
 832
 833         return ret;
 834 }
 835
 836 /**
 837  * Writes data to the object referenced by handle.
 838  *
 839  * On error, the contents of the buffer that were to be modified are undefined.
 840  */
 841 int
 842 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 843                       struct drm_file *file)
 844 {
 845         struct drm_i915_gem_pwrite *args = data;
 846         struct drm_i915_gem_object *obj;
 847         int ret;
 848
 849         if (args->size == 0)
 850                 return 0;
 851
 852         if (!access_ok(VERIFY_READ,
 853                        to_user_ptr(args->data_ptr),
 854                        args->size))
 855                 return -EFAULT;
 856
 857         if (likely(!i915_prefault_disable)) {
 858                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
 859                                                    args->size);
 860                 if (ret)
 861                         return -EFAULT;
 862         }
 863
 864         ret = i915_mutex_lock_interruptible(dev);
 865         if (ret)
 866                 return ret;
 867
 868         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 869         if (&obj->base == NULL) {
 870                 ret = -ENOENT;
 871                 goto unlock;
 872         }
 873
 874         /* Bounds check destination. */
 875         if (args->offset > obj->base.size ||
 876             args->size > obj->base.size - args->offset) {
 877                 ret = -EINVAL;
 878                 goto out;
 879         }
 880
 881         /* prime objects have no backing filp to GEM pread/pwrite
 882          * pages from.
 883          */
 884         if (!obj->base.filp) {
 885                 ret = -EINVAL;
 886                 goto out;
 887         }
 888
 889         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 890
 891         ret = -EFAULT;
 892         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 893          * it would end up going through the fenced access, and we'll get
 894          * different detiling behavior between reading and writing.
 895          * pread/pwrite currently are reading and writing from the CPU
 896          * perspective, requiring manual detiling by the client.
 897          */
 898         if (obj->phys_obj) {
 899                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 900                 goto out;
 901         }
 902
 903         if (obj->cache_level == I915_CACHE_NONE &&
 904             obj->tiling_mode == I915_TILING_NONE &&
 905             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 906                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 907                 /* Note that the gtt paths might fail with non-page-backed user
 908                  * pointers (e.g. gtt mappings when moving data between
 909                  * textures). Fallback to the shmem path in that case. */
 910         }
 911
 912         if (ret == -EFAULT || ret == -ENOSPC)
 913                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 914
 915 out:
 916         drm_gem_object_unreference(&obj->base);
 917 unlock:
 918         mutex_unlock(&dev->struct_mutex);
 919         return ret;
 920 }
 921
 922 int
 923 i915_gem_check_wedge(struct i915_gpu_error *error,
 924                      bool interruptible)
 925 {
 926         if (i915_reset_in_progress(error)) {
 927                 /* Non-interruptible callers can't handle -EAGAIN, hence return
 928                  * -EIO unconditionally for these. */
 929                 if (!interruptible)
 930                         return -EIO;
 931
 932                 /* Recovery complete, but the reset failed ... */
 933                 if (i915_terminally_wedged(error))
 934                         return -EIO;
 935
 936                 return -EAGAIN;
 937         }
 938
 939         return 0;
 940 }
 941
 942 /*
 943  * Compare seqno against outstanding lazy request. Emit a request if they are
 944  * equal.
 945  */
 946 static int
 947 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
 948 {
 949         int ret;
 950
 951         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 952
 953         ret = 0;
 954         if (seqno == ring->outstanding_lazy_request)
 955                 ret = i915_add_request(ring, NULL);
 956
 957         return ret;
 958 }
 959
 960 /**
 961  * __wait_seqno - wait until execution of seqno has finished
 962  * @ring: the ring expected to report seqno
 963  * @seqno: duh!
 964  * @reset_counter: reset sequence associated with the given seqno
 965  * @interruptible: do an interruptible wait (normally yes)
 966  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 967  *
 968  * Note: It is of utmost importance that the passed in seqno and reset_counter
 969  * values have been read by the caller in an smp safe manner. Where read-side
 970  * locks are involved, it is sufficient to read the reset_counter before
 971  * unlocking the lock that protects the seqno. For lockless tricks, the
 972  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
 973  * inserted.
 974  *
 975  * Returns 0 if the seqno was found within the alloted time. Else returns the
 976  * errno with remaining time filled in timeout argument.
 977  */
 978 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
 979                         unsigned reset_counter,
 980                         bool interruptible, struct timespec *timeout)
 981 {
 982         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 983         struct timespec before, now, wait_time={1,0};
 984         unsigned long timeout_jiffies;
 985         long end;
 986         bool wait_forever = true;
 987         int ret;
 988
 989         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
 990                 return 0;
 991
 992         trace_i915_gem_request_wait_begin(ring, seqno);
 993
 994         if (timeout != NULL) {
 995                 wait_time = *timeout;
 996                 wait_forever = false;
 997         }
 998
 999         timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1000
1001         if (WARN_ON(!ring->irq_get(ring)))
1002                 return -ENODEV;
1003
1004         /* Record current time in case interrupted by signal, or wedged * */
1005         getrawmonotonic(&before);
1006
1007 #define EXIT_COND \
1008         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1009          i915_reset_in_progress(&dev_priv->gpu_error) || \
1010          reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1011         do {
1012                 if (interruptible)
1013                         end = wait_event_interruptible_timeout(ring->irq_queue,
1014                                                                EXIT_COND,
1015                                                                timeout_jiffies);
1016                 else
1017                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1018                                                  timeout_jiffies);
1019
1020                 /* We need to check whether any gpu reset happened in between
1021                  * the caller grabbing the seqno and now ... */
1022                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1023                         end = -EAGAIN;
1024
1025                 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1026                  * gone. */
1027                 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1028                 if (ret)
1029                         end = ret;
1030         } while (end == 0 && wait_forever);
1031
1032         getrawmonotonic(&now);
1033
1034         ring->irq_put(ring);
1035         trace_i915_gem_request_wait_end(ring, seqno);
1036 #undef EXIT_COND
1037
1038         if (timeout) {
1039                 struct timespec sleep_time = timespec_sub(now, before);
1040                 *timeout = timespec_sub(*timeout, sleep_time);
1041                 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1042                         set_normalized_timespec(timeout, 0, 0);
1043         }
1044
1045         switch (end) {
1046         case -EIO:
1047         case -EAGAIN: /* Wedged */
1048         case -ERESTARTSYS: /* Signal */
1049                 return (int)end;
1050         case 0: /* Timeout */
1051                 return -ETIME;
1052         default: /* Completed */
1053                 WARN_ON(end < 0); /* We're not aware of other errors */
1054                 return 0;
1055         }
1056 }
1057
1058 /**
1059  * Waits for a sequence number to be signaled, and cleans up the
1060  * request and object lists appropriately for that event.
1061  */
1062 int
1063 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1064 {
1065         struct drm_device *dev = ring->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         bool interruptible = dev_priv->mm.interruptible;
1068         int ret;
1069
1070         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1071         BUG_ON(seqno == 0);
1072
1073         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1074         if (ret)
1075                 return ret;
1076
1077         ret = i915_gem_check_olr(ring, seqno);
1078         if (ret)
1079                 return ret;
1080
1081         return __wait_seqno(ring, seqno,
1082                             atomic_read(&dev_priv->gpu_error.reset_counter),
1083                             interruptible, NULL);
1084 }
1085
1086 static int
1087 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1088                                      struct intel_ring_buffer *ring)
1089 {
1090         i915_gem_retire_requests_ring(ring);
1091
1092         /* Manually manage the write flush as we may have not yet
1093          * retired the buffer.
1094          *
1095          * Note that the last_write_seqno is always the earlier of
1096          * the two (read/write) seqno, so if we haved successfully waited,
1097          * we know we have passed the last write.
1098          */
1099         obj->last_write_seqno = 0;
1100         obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1101
1102         return 0;
1103 }
1104
1105 /**
1106  * Ensures that all rendering to the object has completed and the object is
1107  * safe to unbind from the GTT or access from the CPU.
1108  */
1109 static __must_check int
1110 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1111                                bool readonly)
1112 {
1113         struct intel_ring_buffer *ring = obj->ring;
1114         u32 seqno;
1115         int ret;
1116
1117         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1118         if (seqno == 0)
1119                 return 0;
1120
1121         ret = i915_wait_seqno(ring, seqno);
1122         if (ret)
1123                 return ret;
1124
1125         return i915_gem_object_wait_rendering__tail(obj, ring);
1126 }
1127
1128 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1129  * as the object state may change during this call.
1130  */
1131 static __must_check int
1132 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1133                                             bool readonly)
1134 {
1135         struct drm_device *dev = obj->base.dev;
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137         struct intel_ring_buffer *ring = obj->ring;
1138         unsigned reset_counter;
1139         u32 seqno;
1140         int ret;
1141
1142         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1143         BUG_ON(!dev_priv->mm.interruptible);
1144
1145         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1146         if (seqno == 0)
1147                 return 0;
1148
1149         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1150         if (ret)
1151                 return ret;
1152
1153         ret = i915_gem_check_olr(ring, seqno);
1154         if (ret)
1155                 return ret;
1156
1157         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1158         mutex_unlock(&dev->struct_mutex);
1159         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1160         mutex_lock(&dev->struct_mutex);
1161         if (ret)
1162                 return ret;
1163
1164         return i915_gem_object_wait_rendering__tail(obj, ring);
1165 }
1166
1167 /**
1168  * Called when user space prepares to use an object with the CPU, either
1169  * through the mmap ioctl's mapping or a GTT mapping.
1170  */
1171 int
1172 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1173                           struct drm_file *file)
1174 {
1175         struct drm_i915_gem_set_domain *args = data;
1176         struct drm_i915_gem_object *obj;
1177         uint32_t read_domains = args->read_domains;
1178         uint32_t write_domain = args->write_domain;
1179         int ret;
1180
1181         /* Only handle setting domains to types used by the CPU. */
1182         if (write_domain & I915_GEM_GPU_DOMAINS)
1183                 return -EINVAL;
1184
1185         if (read_domains & I915_GEM_GPU_DOMAINS)
1186                 return -EINVAL;
1187
1188         /* Having something in the write domain implies it's in the read
1189          * domain, and only that read domain.  Enforce that in the request.
1190          */
1191         if (write_domain != 0 && read_domains != write_domain)
1192                 return -EINVAL;
1193
1194         ret = i915_mutex_lock_interruptible(dev);
1195         if (ret)
1196                 return ret;
1197
1198         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1199         if (&obj->base == NULL) {
1200                 ret = -ENOENT;
1201                 goto unlock;
1202         }
1203
1204         /* Try to flush the object off the GPU without holding the lock.
1205          * We will repeat the flush holding the lock in the normal manner
1206          * to catch cases where we are gazumped.
1207          */
1208         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1209         if (ret)
1210                 goto unref;
1211
1212         if (read_domains & I915_GEM_DOMAIN_GTT) {
1213                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1214
1215                 /* Silently promote "you're not bound, there was nothing to do"
1216                  * to success, since the client was just asking us to
1217                  * make sure everything was done.
1218                  */
1219                 if (ret == -EINVAL)
1220                         ret = 0;
1221         } else {
1222                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1223         }
1224
1225 unref:
1226         drm_gem_object_unreference(&obj->base);
1227 unlock:
1228         mutex_unlock(&dev->struct_mutex);
1229         return ret;
1230 }
1231
1232 /**
1233  * Called when user space has done writes to this buffer
1234  */
1235 int
1236 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1237                          struct drm_file *file)
1238 {
1239         struct drm_i915_gem_sw_finish *args = data;
1240         struct drm_i915_gem_object *obj;
1241         int ret = 0;
1242
1243         ret = i915_mutex_lock_interruptible(dev);
1244         if (ret)
1245                 return ret;
1246
1247         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1248         if (&obj->base == NULL) {
1249                 ret = -ENOENT;
1250                 goto unlock;
1251         }
1252
1253         /* Pinned buffers may be scanout, so flush the cache */
1254         if (obj->pin_count)
1255                 i915_gem_object_flush_cpu_write_domain(obj);
1256
1257         drm_gem_object_unreference(&obj->base);
1258 unlock:
1259         mutex_unlock(&dev->struct_mutex);
1260         return ret;
1261 }
1262
1263 /**
1264  * Maps the contents of an object, returning the address it is mapped
1265  * into.
1266  *
1267  * While the mapping holds a reference on the contents of the object, it doesn't
1268  * imply a ref on the object itself.
1269  */
1270 int
1271 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1272                     struct drm_file *file)
1273 {
1274         struct drm_i915_gem_mmap *args = data;
1275         struct drm_gem_object *obj;
1276         unsigned long addr;
1277
1278         obj = drm_gem_object_lookup(dev, file, args->handle);
1279         if (obj == NULL)
1280                 return -ENOENT;
1281
1282         /* prime objects have no backing filp to GEM mmap
1283          * pages from.
1284          */
1285         if (!obj->filp) {
1286                 drm_gem_object_unreference_unlocked(obj);
1287                 return -EINVAL;
1288         }
1289
1290         addr = vm_mmap(obj->filp, 0, args->size,
1291                        PROT_READ | PROT_WRITE, MAP_SHARED,
1292                        args->offset);
1293         drm_gem_object_unreference_unlocked(obj);
1294         if (IS_ERR((void *)addr))
1295                 return addr;
1296
1297         args->addr_ptr = (uint64_t) addr;
1298
1299         return 0;
1300 }
1301
1302 /**
1303  * i915_gem_fault - fault a page into the GTT
1304  * vma: VMA in question
1305  * vmf: fault info
1306  *
1307  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1308  * from userspace.  The fault handler takes care of binding the object to
1309  * the GTT (if needed), allocating and programming a fence register (again,
1310  * only if needed based on whether the old reg is still valid or the object
1311  * is tiled) and inserting a new PTE into the faulting process.
1312  *
1313  * Note that the faulting process may involve evicting existing objects
1314  * from the GTT and/or fence registers to make room.  So performance may
1315  * suffer if the GTT working set is large or there are few fence registers
1316  * left.
1317  */
1318 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1319 {
1320         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1321         struct drm_device *dev = obj->base.dev;
1322         drm_i915_private_t *dev_priv = dev->dev_private;
1323         pgoff_t page_offset;
1324         unsigned long pfn;
1325         int ret = 0;
1326         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1327
1328         /* We don't use vmf->pgoff since that has the fake offset */
1329         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1330                 PAGE_SHIFT;
1331
1332         ret = i915_mutex_lock_interruptible(dev);
1333         if (ret)
1334                 goto out;
1335
1336         trace_i915_gem_object_fault(obj, page_offset, true, write);
1337
1338         /* Access to snoopable pages through the GTT is incoherent. */
1339         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1340                 ret = -EINVAL;
1341                 goto unlock;
1342         }
1343
1344         /* Now bind it into the GTT if needed */
1345         ret = i915_gem_object_pin(obj, 0, true, false);
1346         if (ret)
1347                 goto unlock;
1348
1349         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1350         if (ret)
1351                 goto unpin;
1352
1353         ret = i915_gem_object_get_fence(obj);
1354         if (ret)
1355                 goto unpin;
1356
1357         obj->fault_mappable = true;
1358
1359         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1360         pfn >>= PAGE_SHIFT;
1361         pfn += page_offset;
1362
1363         /* Finally, remap it using the new GTT offset */
1364         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1365 unpin:
1366         i915_gem_object_unpin(obj);
1367 unlock:
1368         mutex_unlock(&dev->struct_mutex);
1369 out:
1370         switch (ret) {
1371         case -EIO:
1372                 /* If this -EIO is due to a gpu hang, give the reset code a
1373                  * chance to clean up the mess. Otherwise return the proper
1374                  * SIGBUS. */
1375                 if (i915_terminally_wedged(&dev_priv->gpu_error))
1376                         return VM_FAULT_SIGBUS;
1377         case -EAGAIN:
1378                 /* Give the error handler a chance to run and move the
1379                  * objects off the GPU active list. Next time we service the
1380                  * fault, we should be able to transition the page into the
1381                  * GTT without touching the GPU (and so avoid further
1382                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1383                  * with coherency, just lost writes.
1384                  */
1385                 set_need_resched();
1386         case 0:
1387         case -ERESTARTSYS:
1388         case -EINTR:
1389         case -EBUSY:
1390                 /*
1391                  * EBUSY is ok: this just means that another thread
1392                  * already did the job.
1393                  */
1394                 return VM_FAULT_NOPAGE;
1395         case -ENOMEM:
1396                 return VM_FAULT_OOM;
1397         case -ENOSPC:
1398                 return VM_FAULT_SIGBUS;
1399         default:
1400                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1401                 return VM_FAULT_SIGBUS;
1402         }
1403 }
1404
1405 /**
1406  * i915_gem_release_mmap - remove physical page mappings
1407  * @obj: obj in question
1408  *
1409  * Preserve the reservation of the mmapping with the DRM core code, but
1410  * relinquish ownership of the pages back to the system.
1411  *
1412  * It is vital that we remove the page mapping if we have mapped a tiled
1413  * object through the GTT and then lose the fence register due to
1414  * resource pressure. Similarly if the object has been moved out of the
1415  * aperture, than pages mapped into userspace must be revoked. Removing the
1416  * mapping will then trigger a page fault on the next user access, allowing
1417  * fixup by i915_gem_fault().
1418  */
1419 void
1420 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1421 {
1422         if (!obj->fault_mappable)
1423                 return;
1424
1425         if (obj->base.dev->dev_mapping)
1426                 unmap_mapping_range(obj->base.dev->dev_mapping,
1427                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1428                                     obj->base.size, 1);
1429
1430         obj->fault_mappable = false;
1431 }
1432
1433 uint32_t
1434 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1435 {
1436         uint32_t gtt_size;
1437
1438         if (INTEL_INFO(dev)->gen >= 4 ||
1439             tiling_mode == I915_TILING_NONE)
1440                 return size;
1441
1442         /* Previous chips need a power-of-two fence region when tiling */
1443         if (INTEL_INFO(dev)->gen == 3)
1444                 gtt_size = 1024*1024;
1445         else
1446                 gtt_size = 512*1024;
1447
1448         while (gtt_size < size)
1449                 gtt_size <<= 1;
1450
1451         return gtt_size;
1452 }
1453
1454 /**
1455  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1456  * @obj: object to check
1457  *
1458  * Return the required GTT alignment for an object, taking into account
1459  * potential fence register mapping.
1460  */
1461 uint32_t
1462 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1463                            int tiling_mode, bool fenced)
1464 {
1465         /*
1466          * Minimum alignment is 4k (GTT page size), but might be greater
1467          * if a fence register is needed for the object.
1468          */
1469         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1470             tiling_mode == I915_TILING_NONE)
1471                 return 4096;
1472
1473         /*
1474          * Previous chips need to be aligned to the size of the smallest
1475          * fence register that can contain the object.
1476          */
1477         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1478 }
1479
1480 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1481 {
1482         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1483         int ret;
1484
1485         if (obj->base.map_list.map)
1486                 return 0;
1487
1488         dev_priv->mm.shrinker_no_lock_stealing = true;
1489
1490         ret = drm_gem_create_mmap_offset(&obj->base);
1491         if (ret != -ENOSPC)
1492                 goto out;
1493
1494         /* Badly fragmented mmap space? The only way we can recover
1495          * space is by destroying unwanted objects. We can't randomly release
1496          * mmap_offsets as userspace expects them to be persistent for the
1497          * lifetime of the objects. The closest we can is to release the
1498          * offsets on purgeable objects by truncating it and marking it purged,
1499          * which prevents userspace from ever using that object again.
1500          */
1501         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1502         ret = drm_gem_create_mmap_offset(&obj->base);
1503         if (ret != -ENOSPC)
1504                 goto out;
1505
1506         i915_gem_shrink_all(dev_priv);
1507         ret = drm_gem_create_mmap_offset(&obj->base);
1508 out:
1509         dev_priv->mm.shrinker_no_lock_stealing = false;
1510
1511         return ret;
1512 }
1513
1514 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1515 {
1516         if (!obj->base.map_list.map)
1517                 return;
1518
1519         drm_gem_free_mmap_offset(&obj->base);
1520 }
1521
1522 int
1523 i915_gem_mmap_gtt(struct drm_file *file,
1524                   struct drm_device *dev,
1525                   uint32_t handle,
1526                   uint64_t *offset)
1527 {
1528         struct drm_i915_private *dev_priv = dev->dev_private;
1529         struct drm_i915_gem_object *obj;
1530         int ret;
1531
1532         ret = i915_mutex_lock_interruptible(dev);
1533         if (ret)
1534                 return ret;
1535
1536         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1537         if (&obj->base == NULL) {
1538                 ret = -ENOENT;
1539                 goto unlock;
1540         }
1541
1542         if (obj->base.size > dev_priv->gtt.mappable_end) {
1543                 ret = -E2BIG;
1544                 goto out;
1545         }
1546
1547         if (obj->madv != I915_MADV_WILLNEED) {
1548                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1549                 ret = -EINVAL;
1550                 goto out;
1551         }
1552
1553         ret = i915_gem_object_create_mmap_offset(obj);
1554         if (ret)
1555                 goto out;
1556
1557         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1558
1559 out:
1560         drm_gem_object_unreference(&obj->base);
1561 unlock:
1562         mutex_unlock(&dev->struct_mutex);
1563         return ret;
1564 }
1565
1566 /**
1567  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1568  * @dev: DRM device
1569  * @data: GTT mapping ioctl data
1570  * @file: GEM object info
1571  *
1572  * Simply returns the fake offset to userspace so it can mmap it.
1573  * The mmap call will end up in drm_gem_mmap(), which will set things
1574  * up so we can get faults in the handler above.
1575  *
1576  * The fault handler will take care of binding the object into the GTT
1577  * (since it may have been evicted to make room for something), allocating
1578  * a fence register, and mapping the appropriate aperture address into
1579  * userspace.
1580  */
1581 int
1582 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1583                         struct drm_file *file)
1584 {
1585         struct drm_i915_gem_mmap_gtt *args = data;
1586
1587         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1588 }
1589
1590 /* Immediately discard the backing storage */
1591 static void
1592 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1593 {
1594         struct inode *inode;
1595
1596         i915_gem_object_free_mmap_offset(obj);
1597
1598         if (obj->base.filp == NULL)
1599                 return;
1600
1601         /* Our goal here is to return as much of the memory as
1602          * is possible back to the system as we are called from OOM.
1603          * To do this we must instruct the shmfs to drop all of its
1604          * backing pages, *now*.
1605          */
1606         inode = file_inode(obj->base.filp);
1607         shmem_truncate_range(inode, 0, (loff_t)-1);
1608
1609         obj->madv = __I915_MADV_PURGED;
1610 }
1611
1612 static inline int
1613 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1614 {
1615         return obj->madv == I915_MADV_DONTNEED;
1616 }
1617
1618 static void
1619 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1620 {
1621         struct sg_page_iter sg_iter;
1622         int ret;
1623
1624         BUG_ON(obj->madv == __I915_MADV_PURGED);
1625
1626         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1627         if (ret) {
1628                 /* In the event of a disaster, abandon all caches and
1629                  * hope for the best.
1630                  */
1631                 WARN_ON(ret != -EIO);
1632                 i915_gem_clflush_object(obj);
1633                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1634         }
1635
1636         if (i915_gem_object_needs_bit17_swizzle(obj))
1637                 i915_gem_object_save_bit_17_swizzle(obj);
1638
1639         if (obj->madv == I915_MADV_DONTNEED)
1640                 obj->dirty = 0;
1641
1642         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1643                 struct page *page = sg_page_iter_page(&sg_iter);
1644
1645                 if (obj->dirty)
1646                         set_page_dirty(page);
1647
1648                 if (obj->madv == I915_MADV_WILLNEED)
1649                         mark_page_accessed(page);
1650
1651                 page_cache_release(page);
1652         }
1653         obj->dirty = 0;
1654
1655         sg_free_table(obj->pages);
1656         kfree(obj->pages);
1657 }
1658
1659 int
1660 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1661 {
1662         const struct drm_i915_gem_object_ops *ops = obj->ops;
1663
1664         if (obj->pages == NULL)
1665                 return 0;
1666
1667         BUG_ON(i915_gem_obj_ggtt_bound(obj));
1668
1669         if (obj->pages_pin_count)
1670                 return -EBUSY;
1671
1672         /* ->put_pages might need to allocate memory for the bit17 swizzle
1673          * array, hence protect them from being reaped by removing them from gtt
1674          * lists early. */
1675         list_del(&obj->global_list);
1676
1677         ops->put_pages(obj);
1678         obj->pages = NULL;
1679
1680         if (i915_gem_object_is_purgeable(obj))
1681                 i915_gem_object_truncate(obj);
1682
1683         return 0;
1684 }
1685
1686 static long
1687 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1688                   bool purgeable_only)
1689 {
1690         struct drm_i915_gem_object *obj, *next;
1691         struct i915_address_space *vm = &dev_priv->gtt.base;
1692         long count = 0;
1693
1694         list_for_each_entry_safe(obj, next,
1695                                  &dev_priv->mm.unbound_list,
1696                                  global_list) {
1697                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1698                     i915_gem_object_put_pages(obj) == 0) {
1699                         count += obj->base.size >> PAGE_SHIFT;
1700                         if (count >= target)
1701                                 return count;
1702                 }
1703         }
1704
1705         list_for_each_entry_safe(obj, next, &vm->inactive_list, mm_list) {
1706                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1707                     i915_gem_object_unbind(obj) == 0 &&
1708                     i915_gem_object_put_pages(obj) == 0) {
1709                         count += obj->base.size >> PAGE_SHIFT;
1710                         if (count >= target)
1711                                 return count;
1712                 }
1713         }
1714
1715         return count;
1716 }
1717
1718 static long
1719 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1720 {
1721         return __i915_gem_shrink(dev_priv, target, true);
1722 }
1723
1724 static void
1725 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1726 {
1727         struct drm_i915_gem_object *obj, *next;
1728
1729         i915_gem_evict_everything(dev_priv->dev);
1730
1731         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1732                                  global_list)
1733                 i915_gem_object_put_pages(obj);
1734 }
1735
1736 static int
1737 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1738 {
1739         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1740         int page_count, i;
1741         struct address_space *mapping;
1742         struct sg_table *st;
1743         struct scatterlist *sg;
1744         struct sg_page_iter sg_iter;
1745         struct page *page;
1746         unsigned long last_pfn = 0;     /* suppress gcc warning */
1747         gfp_t gfp;
1748
1749         /* Assert that the object is not currently in any GPU domain. As it
1750          * wasn't in the GTT, there shouldn't be any way it could have been in
1751          * a GPU cache
1752          */
1753         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1754         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1755
1756         st = kmalloc(sizeof(*st), GFP_KERNEL);
1757         if (st == NULL)
1758                 return -ENOMEM;
1759
1760         page_count = obj->base.size / PAGE_SIZE;
1761         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1762                 sg_free_table(st);
1763                 kfree(st);
1764                 return -ENOMEM;
1765         }
1766
1767         /* Get the list of pages out of our struct file.  They'll be pinned
1768          * at this point until we release them.
1769          *
1770          * Fail silently without starting the shrinker
1771          */
1772         mapping = file_inode(obj->base.filp)->i_mapping;
1773         gfp = mapping_gfp_mask(mapping);
1774         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1775         gfp &= ~(__GFP_IO | __GFP_WAIT);
1776         sg = st->sgl;
1777         st->nents = 0;
1778         for (i = 0; i < page_count; i++) {
1779                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1780                 if (IS_ERR(page)) {
1781                         i915_gem_purge(dev_priv, page_count);
1782                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1783                 }
1784                 if (IS_ERR(page)) {
1785                         /* We've tried hard to allocate the memory by reaping
1786                          * our own buffer, now let the real VM do its job and
1787                          * go down in flames if truly OOM.
1788                          */
1789                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1790                         gfp |= __GFP_IO | __GFP_WAIT;
1791
1792                         i915_gem_shrink_all(dev_priv);
1793                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1794                         if (IS_ERR(page))
1795                                 goto err_pages;
1796
1797                         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1798                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1799                 }
1800 #ifdef CONFIG_SWIOTLB
1801                 if (swiotlb_nr_tbl()) {
1802                         st->nents++;
1803                         sg_set_page(sg, page, PAGE_SIZE, 0);
1804                         sg = sg_next(sg);
1805                         continue;
1806                 }
1807 #endif
1808                 if (!i || page_to_pfn(page) != last_pfn + 1) {
1809                         if (i)
1810                                 sg = sg_next(sg);
1811                         st->nents++;
1812                         sg_set_page(sg, page, PAGE_SIZE, 0);
1813                 } else {
1814                         sg->length += PAGE_SIZE;
1815                 }
1816                 last_pfn = page_to_pfn(page);
1817         }
1818 #ifdef CONFIG_SWIOTLB
1819         if (!swiotlb_nr_tbl())
1820 #endif
1821                 sg_mark_end(sg);
1822         obj->pages = st;
1823
1824         if (i915_gem_object_needs_bit17_swizzle(obj))
1825                 i915_gem_object_do_bit_17_swizzle(obj);
1826
1827         return 0;
1828
1829 err_pages:
1830         sg_mark_end(sg);
1831         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1832                 page_cache_release(sg_page_iter_page(&sg_iter));
1833         sg_free_table(st);
1834         kfree(st);
1835         return PTR_ERR(page);
1836 }
1837
1838 /* Ensure that the associated pages are gathered from the backing storage
1839  * and pinned into our object. i915_gem_object_get_pages() may be called
1840  * multiple times before they are released by a single call to
1841  * i915_gem_object_put_pages() - once the pages are no longer referenced
1842  * either as a result of memory pressure (reaping pages under the shrinker)
1843  * or as the object is itself released.
1844  */
1845 int
1846 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1847 {
1848         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1849         const struct drm_i915_gem_object_ops *ops = obj->ops;
1850         int ret;
1851
1852         if (obj->pages)
1853                 return 0;
1854
1855         if (obj->madv != I915_MADV_WILLNEED) {
1856                 DRM_ERROR("Attempting to obtain a purgeable object\n");
1857                 return -EINVAL;
1858         }
1859
1860         BUG_ON(obj->pages_pin_count);
1861
1862         ret = ops->get_pages(obj);
1863         if (ret)
1864                 return ret;
1865
1866         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1867         return 0;
1868 }
1869
1870 void
1871 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1872                                struct intel_ring_buffer *ring)
1873 {
1874         struct drm_device *dev = obj->base.dev;
1875         struct drm_i915_private *dev_priv = dev->dev_private;
1876         struct i915_address_space *vm = &dev_priv->gtt.base;
1877         u32 seqno = intel_ring_get_seqno(ring);
1878
1879         BUG_ON(ring == NULL);
1880         obj->ring = ring;
1881
1882         /* Add a reference if we're newly entering the active list. */
1883         if (!obj->active) {
1884                 drm_gem_object_reference(&obj->base);
1885                 obj->active = 1;
1886         }
1887
1888         /* Move from whatever list we were on to the tail of execution. */
1889         list_move_tail(&obj->mm_list, &vm->active_list);
1890         list_move_tail(&obj->ring_list, &ring->active_list);
1891
1892         obj->last_read_seqno = seqno;
1893
1894         if (obj->fenced_gpu_access) {
1895                 obj->last_fenced_seqno = seqno;
1896
1897                 /* Bump MRU to take account of the delayed flush */
1898                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1899                         struct drm_i915_fence_reg *reg;
1900
1901                         reg = &dev_priv->fence_regs[obj->fence_reg];
1902                         list_move_tail(&reg->lru_list,
1903                                        &dev_priv->mm.fence_list);
1904                 }
1905         }
1906 }
1907
1908 static void
1909 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1910 {
1911         struct drm_device *dev = obj->base.dev;
1912         struct drm_i915_private *dev_priv = dev->dev_private;
1913         struct i915_address_space *vm = &dev_priv->gtt.base;
1914
1915         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1916         BUG_ON(!obj->active);
1917
1918         list_move_tail(&obj->mm_list, &vm->inactive_list);
1919
1920         list_del_init(&obj->ring_list);
1921         obj->ring = NULL;
1922
1923         obj->last_read_seqno = 0;
1924         obj->last_write_seqno = 0;
1925         obj->base.write_domain = 0;
1926
1927         obj->last_fenced_seqno = 0;
1928         obj->fenced_gpu_access = false;
1929
1930         obj->active = 0;
1931         drm_gem_object_unreference(&obj->base);
1932
1933         WARN_ON(i915_verify_lists(dev));
1934 }
1935
1936 static int
1937 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1938 {
1939         struct drm_i915_private *dev_priv = dev->dev_private;
1940         struct intel_ring_buffer *ring;
1941         int ret, i, j;
1942
1943         /* Carefully retire all requests without writing to the rings */
1944         for_each_ring(ring, dev_priv, i) {
1945                 ret = intel_ring_idle(ring);
1946                 if (ret)
1947                         return ret;
1948         }
1949         i915_gem_retire_requests(dev);
1950
1951         /* Finally reset hw state */
1952         for_each_ring(ring, dev_priv, i) {
1953                 intel_ring_init_seqno(ring, seqno);
1954
1955                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1956                         ring->sync_seqno[j] = 0;
1957         }
1958
1959         return 0;
1960 }
1961
1962 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1963 {
1964         struct drm_i915_private *dev_priv = dev->dev_private;
1965         int ret;
1966
1967         if (seqno == 0)
1968                 return -EINVAL;
1969
1970         /* HWS page needs to be set less than what we
1971          * will inject to ring
1972          */
1973         ret = i915_gem_init_seqno(dev, seqno - 1);
1974         if (ret)
1975                 return ret;
1976
1977         /* Carefully set the last_seqno value so that wrap
1978          * detection still works
1979          */
1980         dev_priv->next_seqno = seqno;
1981         dev_priv->last_seqno = seqno - 1;
1982         if (dev_priv->last_seqno == 0)
1983                 dev_priv->last_seqno--;
1984
1985         return 0;
1986 }
1987
1988 int
1989 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1990 {
1991         struct drm_i915_private *dev_priv = dev->dev_private;
1992
1993         /* reserve 0 for non-seqno */
1994         if (dev_priv->next_seqno == 0) {
1995                 int ret = i915_gem_init_seqno(dev, 0);
1996                 if (ret)
1997                         return ret;
1998
1999                 dev_priv->next_seqno = 1;
2000         }
2001
2002         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2003         return 0;
2004 }
2005
2006 int __i915_add_request(struct intel_ring_buffer *ring,
2007                        struct drm_file *file,
2008                        struct drm_i915_gem_object *obj,
2009                        u32 *out_seqno)
2010 {
2011         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2012         struct drm_i915_gem_request *request;
2013         u32 request_ring_position, request_start;
2014         int was_empty;
2015         int ret;
2016
2017         request_start = intel_ring_get_tail(ring);
2018         /*
2019          * Emit any outstanding flushes - execbuf can fail to emit the flush
2020          * after having emitted the batchbuffer command. Hence we need to fix
2021          * things up similar to emitting the lazy request. The difference here
2022          * is that the flush _must_ happen before the next request, no matter
2023          * what.
2024          */
2025         ret = intel_ring_flush_all_caches(ring);
2026         if (ret)
2027                 return ret;
2028
2029         request = kmalloc(sizeof(*request), GFP_KERNEL);
2030         if (request == NULL)
2031                 return -ENOMEM;
2032
2033
2034         /* Record the position of the start of the request so that
2035          * should we detect the updated seqno part-way through the
2036          * GPU processing the request, we never over-estimate the
2037          * position of the head.
2038          */
2039         request_ring_position = intel_ring_get_tail(ring);
2040
2041         ret = ring->add_request(ring);
2042         if (ret) {
2043                 kfree(request);
2044                 return ret;
2045         }
2046
2047         request->seqno = intel_ring_get_seqno(ring);
2048         request->ring = ring;
2049         request->head = request_start;
2050         request->tail = request_ring_position;
2051         request->ctx = ring->last_context;
2052         request->batch_obj = obj;
2053
2054         /* Whilst this request exists, batch_obj will be on the
2055          * active_list, and so will hold the active reference. Only when this
2056          * request is retired will the the batch_obj be moved onto the
2057          * inactive_list and lose its active reference. Hence we do not need
2058          * to explicitly hold another reference here.
2059          */
2060
2061         if (request->ctx)
2062                 i915_gem_context_reference(request->ctx);
2063
2064         request->emitted_jiffies = jiffies;
2065         was_empty = list_empty(&ring->request_list);
2066         list_add_tail(&request->list, &ring->request_list);
2067         request->file_priv = NULL;
2068
2069         if (file) {
2070                 struct drm_i915_file_private *file_priv = file->driver_priv;
2071
2072                 spin_lock(&file_priv->mm.lock);
2073                 request->file_priv = file_priv;
2074                 list_add_tail(&request->client_list,
2075                               &file_priv->mm.request_list);
2076                 spin_unlock(&file_priv->mm.lock);
2077         }
2078
2079         trace_i915_gem_request_add(ring, request->seqno);
2080         ring->outstanding_lazy_request = 0;
2081
2082         if (!dev_priv->ums.mm_suspended) {
2083                 i915_queue_hangcheck(ring->dev);
2084
2085                 if (was_empty) {
2086                         queue_delayed_work(dev_priv->wq,
2087                                            &dev_priv->mm.retire_work,
2088                                            round_jiffies_up_relative(HZ));
2089                         intel_mark_busy(dev_priv->dev);
2090                 }
2091         }
2092
2093         if (out_seqno)
2094                 *out_seqno = request->seqno;
2095         return 0;
2096 }
2097
2098 static inline void
2099 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2100 {
2101         struct drm_i915_file_private *file_priv = request->file_priv;
2102
2103         if (!file_priv)
2104                 return;
2105
2106         spin_lock(&file_priv->mm.lock);
2107         if (request->file_priv) {
2108                 list_del(&request->client_list);
2109                 request->file_priv = NULL;
2110         }
2111         spin_unlock(&file_priv->mm.lock);
2112 }
2113
2114 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2115 {
2116         if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
2117             acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
2118                 return true;
2119
2120         return false;
2121 }
2122
2123 static bool i915_head_inside_request(const u32 acthd_unmasked,
2124                                      const u32 request_start,
2125                                      const u32 request_end)
2126 {
2127         const u32 acthd = acthd_unmasked & HEAD_ADDR;
2128
2129         if (request_start < request_end) {
2130                 if (acthd >= request_start && acthd < request_end)
2131                         return true;
2132         } else if (request_start > request_end) {
2133                 if (acthd >= request_start || acthd < request_end)
2134                         return true;
2135         }
2136
2137         return false;
2138 }
2139
2140 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2141                                 const u32 acthd, bool *inside)
2142 {
2143         /* There is a possibility that unmasked head address
2144          * pointing inside the ring, matches the batch_obj address range.
2145          * However this is extremely unlikely.
2146          */
2147
2148         if (request->batch_obj) {
2149                 if (i915_head_inside_object(acthd, request->batch_obj)) {
2150                         *inside = true;
2151                         return true;
2152                 }
2153         }
2154
2155         if (i915_head_inside_request(acthd, request->head, request->tail)) {
2156                 *inside = false;
2157                 return true;
2158         }
2159
2160         return false;
2161 }
2162
2163 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2164                                   struct drm_i915_gem_request *request,
2165                                   u32 acthd)
2166 {
2167         struct i915_ctx_hang_stats *hs = NULL;
2168         bool inside, guilty;
2169
2170         /* Innocent until proven guilty */
2171         guilty = false;
2172
2173         if (ring->hangcheck.action != wait &&
2174             i915_request_guilty(request, acthd, &inside)) {
2175                 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2176                           ring->name,
2177                           inside ? "inside" : "flushing",
2178                           request->batch_obj ?
2179                           i915_gem_obj_ggtt_offset(request->batch_obj) : 0,
2180                           request->ctx ? request->ctx->id : 0,
2181                           acthd);
2182
2183                 guilty = true;
2184         }
2185
2186         /* If contexts are disabled or this is the default context, use
2187          * file_priv->reset_state
2188          */
2189         if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2190                 hs = &request->ctx->hang_stats;
2191         else if (request->file_priv)
2192                 hs = &request->file_priv->hang_stats;
2193
2194         if (hs) {
2195                 if (guilty)
2196                         hs->batch_active++;
2197                 else
2198                         hs->batch_pending++;
2199         }
2200 }
2201
2202 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2203 {
2204         list_del(&request->list);
2205         i915_gem_request_remove_from_client(request);
2206
2207         if (request->ctx)
2208                 i915_gem_context_unreference(request->ctx);
2209
2210         kfree(request);
2211 }
2212
2213 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2214                                       struct intel_ring_buffer *ring)
2215 {
2216         u32 completed_seqno;
2217         u32 acthd;
2218
2219         acthd = intel_ring_get_active_head(ring);
2220         completed_seqno = ring->get_seqno(ring, false);
2221
2222         while (!list_empty(&ring->request_list)) {
2223                 struct drm_i915_gem_request *request;
2224
2225                 request = list_first_entry(&ring->request_list,
2226                                            struct drm_i915_gem_request,
2227                                            list);
2228
2229                 if (request->seqno > completed_seqno)
2230                         i915_set_reset_status(ring, request, acthd);
2231
2232                 i915_gem_free_request(request);
2233         }
2234
2235         while (!list_empty(&ring->active_list)) {
2236                 struct drm_i915_gem_object *obj;
2237
2238                 obj = list_first_entry(&ring->active_list,
2239                                        struct drm_i915_gem_object,
2240                                        ring_list);
2241
2242                 i915_gem_object_move_to_inactive(obj);
2243         }
2244 }
2245
2246 static void i915_gem_reset_fences(struct drm_device *dev)
2247 {
2248         struct drm_i915_private *dev_priv = dev->dev_private;
2249         int i;
2250
2251         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2252                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2253
2254                 if (reg->obj)
2255                         i915_gem_object_fence_lost(reg->obj);
2256
2257                 i915_gem_write_fence(dev, i, NULL);
2258
2259                 reg->pin_count = 0;
2260                 reg->obj = NULL;
2261                 INIT_LIST_HEAD(&reg->lru_list);
2262         }
2263
2264         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2265 }
2266
2267 void i915_gem_reset(struct drm_device *dev)
2268 {
2269         struct drm_i915_private *dev_priv = dev->dev_private;
2270         struct i915_address_space *vm = &dev_priv->gtt.base;
2271         struct drm_i915_gem_object *obj;
2272         struct intel_ring_buffer *ring;
2273         int i;
2274
2275         for_each_ring(ring, dev_priv, i)
2276                 i915_gem_reset_ring_lists(dev_priv, ring);
2277
2278         /* Move everything out of the GPU domains to ensure we do any
2279          * necessary invalidation upon reuse.
2280          */
2281         list_for_each_entry(obj, &vm->inactive_list, mm_list)
2282                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2283
2284         /* The fence registers are invalidated so clear them out */
2285         i915_gem_reset_fences(dev);
2286 }
2287
2288 /**
2289  * This function clears the request list as sequence numbers are passed.
2290  */
2291 void
2292 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2293 {
2294         uint32_t seqno;
2295
2296         if (list_empty(&ring->request_list))
2297                 return;
2298
2299         WARN_ON(i915_verify_lists(ring->dev));
2300
2301         seqno = ring->get_seqno(ring, true);
2302
2303         while (!list_empty(&ring->request_list)) {
2304                 struct drm_i915_gem_request *request;
2305
2306                 request = list_first_entry(&ring->request_list,
2307                                            struct drm_i915_gem_request,
2308                                            list);
2309
2310                 if (!i915_seqno_passed(seqno, request->seqno))
2311                         break;
2312
2313                 trace_i915_gem_request_retire(ring, request->seqno);
2314                 /* We know the GPU must have read the request to have
2315                  * sent us the seqno + interrupt, so use the position
2316                  * of tail of the request to update the last known position
2317                  * of the GPU head.
2318                  */
2319                 ring->last_retired_head = request->tail;
2320
2321                 i915_gem_free_request(request);
2322         }
2323
2324         /* Move any buffers on the active list that are no longer referenced
2325          * by the ringbuffer to the flushing/inactive lists as appropriate.
2326          */
2327         while (!list_empty(&ring->active_list)) {
2328                 struct drm_i915_gem_object *obj;
2329
2330                 obj = list_first_entry(&ring->active_list,
2331                                       struct drm_i915_gem_object,
2332                                       ring_list);
2333
2334                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2335                         break;
2336
2337                 i915_gem_object_move_to_inactive(obj);
2338         }
2339
2340         if (unlikely(ring->trace_irq_seqno &&
2341                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2342                 ring->irq_put(ring);
2343                 ring->trace_irq_seqno = 0;
2344         }
2345
2346         WARN_ON(i915_verify_lists(ring->dev));
2347 }
2348
2349 void
2350 i915_gem_retire_requests(struct drm_device *dev)
2351 {
2352         drm_i915_private_t *dev_priv = dev->dev_private;
2353         struct intel_ring_buffer *ring;
2354         int i;
2355
2356         for_each_ring(ring, dev_priv, i)
2357                 i915_gem_retire_requests_ring(ring);
2358 }
2359
2360 static void
2361 i915_gem_retire_work_handler(struct work_struct *work)
2362 {
2363         drm_i915_private_t *dev_priv;
2364         struct drm_device *dev;
2365         struct intel_ring_buffer *ring;
2366         bool idle;
2367         int i;
2368
2369         dev_priv = container_of(work, drm_i915_private_t,
2370                                 mm.retire_work.work);
2371         dev = dev_priv->dev;
2372
2373         /* Come back later if the device is busy... */
2374         if (!mutex_trylock(&dev->struct_mutex)) {
2375                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2376                                    round_jiffies_up_relative(HZ));
2377                 return;
2378         }
2379
2380         i915_gem_retire_requests(dev);
2381
2382         /* Send a periodic flush down the ring so we don't hold onto GEM
2383          * objects indefinitely.
2384          */
2385         idle = true;
2386         for_each_ring(ring, dev_priv, i) {
2387                 if (ring->gpu_caches_dirty)
2388                         i915_add_request(ring, NULL);
2389
2390                 idle &= list_empty(&ring->request_list);
2391         }
2392
2393         if (!dev_priv->ums.mm_suspended && !idle)
2394                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2395                                    round_jiffies_up_relative(HZ));
2396         if (idle)
2397                 intel_mark_idle(dev);
2398
2399         mutex_unlock(&dev->struct_mutex);
2400 }
2401
2402 /**
2403  * Ensures that an object will eventually get non-busy by flushing any required
2404  * write domains, emitting any outstanding lazy request and retiring and
2405  * completed requests.
2406  */
2407 static int
2408 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2409 {
2410         int ret;
2411
2412         if (obj->active) {
2413                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2414                 if (ret)
2415                         return ret;
2416
2417                 i915_gem_retire_requests_ring(obj->ring);
2418         }
2419
2420         return 0;
2421 }
2422
2423 /**
2424  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2425  * @DRM_IOCTL_ARGS: standard ioctl arguments
2426  *
2427  * Returns 0 if successful, else an error is returned with the remaining time in
2428  * the timeout parameter.
2429  *  -ETIME: object is still busy after timeout
2430  *  -ERESTARTSYS: signal interrupted the wait
2431  *  -ENONENT: object doesn't exist
2432  * Also possible, but rare:
2433  *  -EAGAIN: GPU wedged
2434  *  -ENOMEM: damn
2435  *  -ENODEV: Internal IRQ fail
2436  *  -E?: The add request failed
2437  *
2438  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2439  * non-zero timeout parameter the wait ioctl will wait for the given number of
2440  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2441  * without holding struct_mutex the object may become re-busied before this
2442  * function completes. A similar but shorter * race condition exists in the busy
2443  * ioctl
2444  */
2445 int
2446 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2447 {
2448         drm_i915_private_t *dev_priv = dev->dev_private;
2449         struct drm_i915_gem_wait *args = data;
2450         struct drm_i915_gem_object *obj;
2451         struct intel_ring_buffer *ring = NULL;
2452         struct timespec timeout_stack, *timeout = NULL;
2453         unsigned reset_counter;
2454         u32 seqno = 0;
2455         int ret = 0;
2456
2457         if (args->timeout_ns >= 0) {
2458                 timeout_stack = ns_to_timespec(args->timeout_ns);
2459                 timeout = &timeout_stack;
2460         }
2461
2462         ret = i915_mutex_lock_interruptible(dev);
2463         if (ret)
2464                 return ret;
2465
2466         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2467         if (&obj->base == NULL) {
2468                 mutex_unlock(&dev->struct_mutex);
2469                 return -ENOENT;
2470         }
2471
2472         /* Need to make sure the object gets inactive eventually. */
2473         ret = i915_gem_object_flush_active(obj);
2474         if (ret)
2475                 goto out;
2476
2477         if (obj->active) {
2478                 seqno = obj->last_read_seqno;
2479                 ring = obj->ring;
2480         }
2481
2482         if (seqno == 0)
2483                  goto out;
2484
2485         /* Do this after OLR check to make sure we make forward progress polling
2486          * on this IOCTL with a 0 timeout (like busy ioctl)
2487          */
2488         if (!args->timeout_ns) {
2489                 ret = -ETIME;
2490                 goto out;
2491         }
2492
2493         drm_gem_object_unreference(&obj->base);
2494         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2495         mutex_unlock(&dev->struct_mutex);
2496
2497         ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2498         if (timeout)
2499                 args->timeout_ns = timespec_to_ns(timeout);
2500         return ret;
2501
2502 out:
2503         drm_gem_object_unreference(&obj->base);
2504         mutex_unlock(&dev->struct_mutex);
2505         return ret;
2506 }
2507
2508 /**
2509  * i915_gem_object_sync - sync an object to a ring.
2510  *
2511  * @obj: object which may be in use on another ring.
2512  * @to: ring we wish to use the object on. May be NULL.
2513  *
2514  * This code is meant to abstract object synchronization with the GPU.
2515  * Calling with NULL implies synchronizing the object with the CPU
2516  * rather than a particular GPU ring.
2517  *
2518  * Returns 0 if successful, else propagates up the lower layer error.
2519  */
2520 int
2521 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2522                      struct intel_ring_buffer *to)
2523 {
2524         struct intel_ring_buffer *from = obj->ring;
2525         u32 seqno;
2526         int ret, idx;
2527
2528         if (from == NULL || to == from)
2529                 return 0;
2530
2531         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2532                 return i915_gem_object_wait_rendering(obj, false);
2533
2534         idx = intel_ring_sync_index(from, to);
2535
2536         seqno = obj->last_read_seqno;
2537         if (seqno <= from->sync_seqno[idx])
2538                 return 0;
2539
2540         ret = i915_gem_check_olr(obj->ring, seqno);
2541         if (ret)
2542                 return ret;
2543
2544         ret = to->sync_to(to, from, seqno);
2545         if (!ret)
2546                 /* We use last_read_seqno because sync_to()
2547                  * might have just caused seqno wrap under
2548                  * the radar.
2549                  */
2550                 from->sync_seqno[idx] = obj->last_read_seqno;
2551
2552         return ret;
2553 }
2554
2555 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2556 {
2557         u32 old_write_domain, old_read_domains;
2558
2559         /* Force a pagefault for domain tracking on next user access */
2560         i915_gem_release_mmap(obj);
2561
2562         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2563                 return;
2564
2565         /* Wait for any direct GTT access to complete */
2566         mb();
2567
2568         old_read_domains = obj->base.read_domains;
2569         old_write_domain = obj->base.write_domain;
2570
2571         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2572         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2573
2574         trace_i915_gem_object_change_domain(obj,
2575                                             old_read_domains,
2576                                             old_write_domain);
2577 }
2578
2579 /**
2580  * Unbinds an object from the GTT aperture.
2581  */
2582 int
2583 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2584 {
2585         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2586         struct i915_vma *vma;
2587         int ret;
2588
2589         if (!i915_gem_obj_ggtt_bound(obj))
2590                 return 0;
2591
2592         if (obj->pin_count)
2593                 return -EBUSY;
2594
2595         BUG_ON(obj->pages == NULL);
2596
2597         ret = i915_gem_object_finish_gpu(obj);
2598         if (ret)
2599                 return ret;
2600         /* Continue on if we fail due to EIO, the GPU is hung so we
2601          * should be safe and we need to cleanup or else we might
2602          * cause memory corruption through use-after-free.
2603          */
2604
2605         i915_gem_object_finish_gtt(obj);
2606
2607         /* release the fence reg _after_ flushing */
2608         ret = i915_gem_object_put_fence(obj);
2609         if (ret)
2610                 return ret;
2611
2612         trace_i915_gem_object_unbind(obj);
2613
2614         if (obj->has_global_gtt_mapping)
2615                 i915_gem_gtt_unbind_object(obj);
2616         if (obj->has_aliasing_ppgtt_mapping) {
2617                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2618                 obj->has_aliasing_ppgtt_mapping = 0;
2619         }
2620         i915_gem_gtt_finish_object(obj);
2621         i915_gem_object_unpin_pages(obj);
2622
2623         list_del(&obj->mm_list);
2624         /* Avoid an unnecessary call to unbind on rebind. */
2625         obj->map_and_fenceable = true;
2626
2627         vma = __i915_gem_obj_to_vma(obj);
2628         list_del(&vma->vma_link);
2629         drm_mm_remove_node(&vma->node);
2630         i915_gem_vma_destroy(vma);
2631
2632         /* Since the unbound list is global, only move to that list if
2633          * no more VMAs exist.
2634          * NB: Until we have real VMAs there will only ever be one */
2635         WARN_ON(!list_empty(&obj->vma_list));
2636         if (list_empty(&obj->vma_list))
2637                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2638
2639         return 0;
2640 }
2641
2642 int i915_gpu_idle(struct drm_device *dev)
2643 {
2644         drm_i915_private_t *dev_priv = dev->dev_private;
2645         struct intel_ring_buffer *ring;
2646         int ret, i;
2647
2648         /* Flush everything onto the inactive list. */
2649         for_each_ring(ring, dev_priv, i) {
2650                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2651                 if (ret)
2652                         return ret;
2653
2654                 ret = intel_ring_idle(ring);
2655                 if (ret)
2656                         return ret;
2657         }
2658
2659         return 0;
2660 }
2661
2662 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2663                                  struct drm_i915_gem_object *obj)
2664 {
2665         drm_i915_private_t *dev_priv = dev->dev_private;
2666         int fence_reg;
2667         int fence_pitch_shift;
2668         uint64_t val;
2669
2670         if (INTEL_INFO(dev)->gen >= 6) {
2671                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2672                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2673         } else {
2674                 fence_reg = FENCE_REG_965_0;
2675                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2676         }
2677
2678         if (obj) {
2679                 u32 size = i915_gem_obj_ggtt_size(obj);
2680
2681                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2682                                  0xfffff000) << 32;
2683                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2684                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2685                 if (obj->tiling_mode == I915_TILING_Y)
2686                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2687                 val |= I965_FENCE_REG_VALID;
2688         } else
2689                 val = 0;
2690
2691         fence_reg += reg * 8;
2692         I915_WRITE64(fence_reg, val);
2693         POSTING_READ(fence_reg);
2694 }
2695
2696 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2697                                  struct drm_i915_gem_object *obj)
2698 {
2699         drm_i915_private_t *dev_priv = dev->dev_private;
2700         u32 val;
2701
2702         if (obj) {
2703                 u32 size = i915_gem_obj_ggtt_size(obj);
2704                 int pitch_val;
2705                 int tile_width;
2706
2707                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2708                      (size & -size) != size ||
2709                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2710                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2711                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2712
2713                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2714                         tile_width = 128;
2715                 else
2716                         tile_width = 512;
2717
2718                 /* Note: pitch better be a power of two tile widths */
2719                 pitch_val = obj->stride / tile_width;
2720                 pitch_val = ffs(pitch_val) - 1;
2721
2722                 val = i915_gem_obj_ggtt_offset(obj);
2723                 if (obj->tiling_mode == I915_TILING_Y)
2724                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2725                 val |= I915_FENCE_SIZE_BITS(size);
2726                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2727                 val |= I830_FENCE_REG_VALID;
2728         } else
2729                 val = 0;
2730
2731         if (reg < 8)
2732                 reg = FENCE_REG_830_0 + reg * 4;
2733         else
2734                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2735
2736         I915_WRITE(reg, val);
2737         POSTING_READ(reg);
2738 }
2739
2740 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2741                                 struct drm_i915_gem_object *obj)
2742 {
2743         drm_i915_private_t *dev_priv = dev->dev_private;
2744         uint32_t val;
2745
2746         if (obj) {
2747                 u32 size = i915_gem_obj_ggtt_size(obj);
2748                 uint32_t pitch_val;
2749
2750                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2751                      (size & -size) != size ||
2752                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2753                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2754                      i915_gem_obj_ggtt_offset(obj), size);
2755
2756                 pitch_val = obj->stride / 128;
2757                 pitch_val = ffs(pitch_val) - 1;
2758
2759                 val = i915_gem_obj_ggtt_offset(obj);
2760                 if (obj->tiling_mode == I915_TILING_Y)
2761                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2762                 val |= I830_FENCE_SIZE_BITS(size);
2763                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2764                 val |= I830_FENCE_REG_VALID;
2765         } else
2766                 val = 0;
2767
2768         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2769         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2770 }
2771
2772 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2773 {
2774         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2775 }
2776
2777 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2778                                  struct drm_i915_gem_object *obj)
2779 {
2780         struct drm_i915_private *dev_priv = dev->dev_private;
2781
2782         /* Ensure that all CPU reads are completed before installing a fence
2783          * and all writes before removing the fence.
2784          */
2785         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2786                 mb();
2787
2788         switch (INTEL_INFO(dev)->gen) {
2789         case 7:
2790         case 6:
2791         case 5:
2792         case 4: i965_write_fence_reg(dev, reg, obj); break;
2793         case 3: i915_write_fence_reg(dev, reg, obj); break;
2794         case 2: i830_write_fence_reg(dev, reg, obj); break;
2795         default: BUG();
2796         }
2797
2798         /* And similarly be paranoid that no direct access to this region
2799          * is reordered to before the fence is installed.
2800          */
2801         if (i915_gem_object_needs_mb(obj))
2802                 mb();
2803 }
2804
2805 static inline int fence_number(struct drm_i915_private *dev_priv,
2806                                struct drm_i915_fence_reg *fence)
2807 {
2808         return fence - dev_priv->fence_regs;
2809 }
2810
2811 struct write_fence {
2812         struct drm_device *dev;
2813         struct drm_i915_gem_object *obj;
2814         int fence;
2815 };
2816
2817 static void i915_gem_write_fence__ipi(void *data)
2818 {
2819         struct write_fence *args = data;
2820
2821         /* Required for SNB+ with LLC */
2822         wbinvd();
2823
2824         /* Required for VLV */
2825         i915_gem_write_fence(args->dev, args->fence, args->obj);
2826 }
2827
2828 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2829                                          struct drm_i915_fence_reg *fence,
2830                                          bool enable)
2831 {
2832         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2833         struct write_fence args = {
2834                 .dev = obj->base.dev,
2835                 .fence = fence_number(dev_priv, fence),
2836                 .obj = enable ? obj : NULL,
2837         };
2838
2839         /* In order to fully serialize access to the fenced region and
2840          * the update to the fence register we need to take extreme
2841          * measures on SNB+. In theory, the write to the fence register
2842          * flushes all memory transactions before, and coupled with the
2843          * mb() placed around the register write we serialise all memory
2844          * operations with respect to the changes in the tiler. Yet, on
2845          * SNB+ we need to take a step further and emit an explicit wbinvd()
2846          * on each processor in order to manually flush all memory
2847          * transactions before updating the fence register.
2848          *
2849          * However, Valleyview complicates matter. There the wbinvd is
2850          * insufficient and unlike SNB/IVB requires the serialising
2851          * register write. (Note that that register write by itself is
2852          * conversely not sufficient for SNB+.) To compromise, we do both.
2853          */
2854         if (INTEL_INFO(args.dev)->gen >= 6)
2855                 on_each_cpu(i915_gem_write_fence__ipi, &args, 1);
2856         else
2857                 i915_gem_write_fence(args.dev, args.fence, args.obj);
2858
2859         if (enable) {
2860                 obj->fence_reg = args.fence;
2861                 fence->obj = obj;
2862                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2863         } else {
2864                 obj->fence_reg = I915_FENCE_REG_NONE;
2865                 fence->obj = NULL;
2866                 list_del_init(&fence->lru_list);
2867         }
2868 }
2869
2870 static int
2871 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2872 {
2873         if (obj->last_fenced_seqno) {
2874                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2875                 if (ret)
2876                         return ret;
2877
2878                 obj->last_fenced_seqno = 0;
2879         }
2880
2881         obj->fenced_gpu_access = false;
2882         return 0;
2883 }
2884
2885 int
2886 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2887 {
2888         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2889         struct drm_i915_fence_reg *fence;
2890         int ret;
2891
2892         ret = i915_gem_object_wait_fence(obj);
2893         if (ret)
2894                 return ret;
2895
2896         if (obj->fence_reg == I915_FENCE_REG_NONE)
2897                 return 0;
2898
2899         fence = &dev_priv->fence_regs[obj->fence_reg];
2900
2901         i915_gem_object_fence_lost(obj);
2902         i915_gem_object_update_fence(obj, fence, false);
2903
2904         return 0;
2905 }
2906
2907 static struct drm_i915_fence_reg *
2908 i915_find_fence_reg(struct drm_device *dev)
2909 {
2910         struct drm_i915_private *dev_priv = dev->dev_private;
2911         struct drm_i915_fence_reg *reg, *avail;
2912         int i;
2913
2914         /* First try to find a free reg */
2915         avail = NULL;
2916         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2917                 reg = &dev_priv->fence_regs[i];
2918                 if (!reg->obj)
2919                         return reg;
2920
2921                 if (!reg->pin_count)
2922                         avail = reg;
2923         }
2924
2925         if (avail == NULL)
2926                 return NULL;
2927
2928         /* None available, try to steal one or wait for a user to finish */
2929         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2930                 if (reg->pin_count)
2931                         continue;
2932
2933                 return reg;
2934         }
2935
2936         return NULL;
2937 }
2938
2939 /**
2940  * i915_gem_object_get_fence - set up fencing for an object
2941  * @obj: object to map through a fence reg
2942  *
2943  * When mapping objects through the GTT, userspace wants to be able to write
2944  * to them without having to worry about swizzling if the object is tiled.
2945  * This function walks the fence regs looking for a free one for @obj,
2946  * stealing one if it can't find any.
2947  *
2948  * It then sets up the reg based on the object's properties: address, pitch
2949  * and tiling format.
2950  *
2951  * For an untiled surface, this removes any existing fence.
2952  */
2953 int
2954 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2955 {
2956         struct drm_device *dev = obj->base.dev;
2957         struct drm_i915_private *dev_priv = dev->dev_private;
2958         bool enable = obj->tiling_mode != I915_TILING_NONE;
2959         struct drm_i915_fence_reg *reg;
2960         int ret;
2961
2962         /* Have we updated the tiling parameters upon the object and so
2963          * will need to serialise the write to the associated fence register?
2964          */
2965         if (obj->fence_dirty) {
2966                 ret = i915_gem_object_wait_fence(obj);
2967                 if (ret)
2968                         return ret;
2969         }
2970
2971         /* Just update our place in the LRU if our fence is getting reused. */
2972         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2973                 reg = &dev_priv->fence_regs[obj->fence_reg];
2974                 if (!obj->fence_dirty) {
2975                         list_move_tail(&reg->lru_list,
2976                                        &dev_priv->mm.fence_list);
2977                         return 0;
2978                 }
2979         } else if (enable) {
2980                 reg = i915_find_fence_reg(dev);
2981                 if (reg == NULL)
2982                         return -EDEADLK;
2983
2984                 if (reg->obj) {
2985                         struct drm_i915_gem_object *old = reg->obj;
2986
2987                         ret = i915_gem_object_wait_fence(old);
2988                         if (ret)
2989                                 return ret;
2990
2991                         i915_gem_object_fence_lost(old);
2992                 }
2993         } else
2994                 return 0;
2995
2996         i915_gem_object_update_fence(obj, reg, enable);
2997         obj->fence_dirty = false;
2998
2999         return 0;
3000 }
3001
3002 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3003                                      struct drm_mm_node *gtt_space,
3004                                      unsigned long cache_level)
3005 {
3006         struct drm_mm_node *other;
3007
3008         /* On non-LLC machines we have to be careful when putting differing
3009          * types of snoopable memory together to avoid the prefetcher
3010          * crossing memory domains and dying.
3011          */
3012         if (HAS_LLC(dev))
3013                 return true;
3014
3015         if (!drm_mm_node_allocated(gtt_space))
3016                 return true;
3017
3018         if (list_empty(&gtt_space->node_list))
3019                 return true;
3020
3021         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3022         if (other->allocated && !other->hole_follows && other->color != cache_level)
3023                 return false;
3024
3025         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3026         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3027                 return false;
3028
3029         return true;
3030 }
3031
3032 static void i915_gem_verify_gtt(struct drm_device *dev)
3033 {
3034 #if WATCH_GTT
3035         struct drm_i915_private *dev_priv = dev->dev_private;
3036         struct drm_i915_gem_object *obj;
3037         int err = 0;
3038
3039         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3040                 if (obj->gtt_space == NULL) {
3041                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3042                         err++;
3043                         continue;
3044                 }
3045
3046                 if (obj->cache_level != obj->gtt_space->color) {
3047                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3048                                i915_gem_obj_ggtt_offset(obj),
3049                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3050                                obj->cache_level,
3051                                obj->gtt_space->color);
3052                         err++;
3053                         continue;
3054                 }
3055
3056                 if (!i915_gem_valid_gtt_space(dev,
3057                                               obj->gtt_space,
3058                                               obj->cache_level)) {
3059                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3060                                i915_gem_obj_ggtt_offset(obj),
3061                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3062                                obj->cache_level);
3063                         err++;
3064                         continue;
3065                 }
3066         }
3067
3068         WARN_ON(err);
3069 #endif
3070 }
3071
3072 /**
3073  * Finds free space in the GTT aperture and binds the object there.
3074  */
3075 static int
3076 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3077                             unsigned alignment,
3078                             bool map_and_fenceable,
3079                             bool nonblocking)
3080 {
3081         struct drm_device *dev = obj->base.dev;
3082         drm_i915_private_t *dev_priv = dev->dev_private;
3083         struct i915_address_space *vm = &dev_priv->gtt.base;
3084         u32 size, fence_size, fence_alignment, unfenced_alignment;
3085         bool mappable, fenceable;
3086         size_t gtt_max = map_and_fenceable ?
3087                 dev_priv->gtt.mappable_end : dev_priv->gtt.base.total;
3088         struct i915_vma *vma;
3089         int ret;
3090
3091         if (WARN_ON(!list_empty(&obj->vma_list)))
3092                 return -EBUSY;
3093
3094         fence_size = i915_gem_get_gtt_size(dev,
3095                                            obj->base.size,
3096                                            obj->tiling_mode);
3097         fence_alignment = i915_gem_get_gtt_alignment(dev,
3098                                                      obj->base.size,
3099                                                      obj->tiling_mode, true);
3100         unfenced_alignment =
3101                 i915_gem_get_gtt_alignment(dev,
3102                                                     obj->base.size,
3103                                                     obj->tiling_mode, false);
3104
3105         if (alignment == 0)
3106                 alignment = map_and_fenceable ? fence_alignment :
3107                                                 unfenced_alignment;
3108         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3109                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3110                 return -EINVAL;
3111         }
3112
3113         size = map_and_fenceable ? fence_size : obj->base.size;
3114
3115         /* If the object is bigger than the entire aperture, reject it early
3116          * before evicting everything in a vain attempt to find space.
3117          */
3118         if (obj->base.size > gtt_max) {
3119                 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3120                           obj->base.size,
3121                           map_and_fenceable ? "mappable" : "total",
3122                           gtt_max);
3123                 return -E2BIG;
3124         }
3125
3126         ret = i915_gem_object_get_pages(obj);
3127         if (ret)
3128                 return ret;
3129
3130         i915_gem_object_pin_pages(obj);
3131
3132         vma = i915_gem_vma_create(obj, &dev_priv->gtt.base);
3133         if (IS_ERR(vma)) {
3134                 ret = PTR_ERR(vma);
3135                 goto err_unpin;
3136         }
3137
3138 search_free:
3139         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
3140                                                   &vma->node,
3141                                                   size, alignment,
3142                                                   obj->cache_level, 0, gtt_max);
3143         if (ret) {
3144                 ret = i915_gem_evict_something(dev, size, alignment,
3145                                                obj->cache_level,
3146                                                map_and_fenceable,
3147                                                nonblocking);
3148                 if (ret == 0)
3149                         goto search_free;
3150
3151                 goto err_free_vma;
3152         }
3153         if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3154                                               obj->cache_level))) {
3155                 ret = -EINVAL;
3156                 goto err_remove_node;
3157         }
3158
3159         ret = i915_gem_gtt_prepare_object(obj);
3160         if (ret)
3161                 goto err_remove_node;
3162
3163         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3164         list_add_tail(&obj->mm_list, &vm->inactive_list);
3165         list_add(&vma->vma_link, &obj->vma_list);
3166
3167         fenceable =
3168                 i915_gem_obj_ggtt_size(obj) == fence_size &&
3169                 (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0;
3170
3171         mappable = i915_gem_obj_ggtt_offset(obj) + obj->base.size <=
3172                 dev_priv->gtt.mappable_end;
3173
3174         obj->map_and_fenceable = mappable && fenceable;
3175
3176         trace_i915_gem_object_bind(obj, map_and_fenceable);
3177         i915_gem_verify_gtt(dev);
3178         return 0;
3179
3180 err_remove_node:
3181         drm_mm_remove_node(&vma->node);
3182 err_free_vma:
3183         i915_gem_vma_destroy(vma);
3184 err_unpin:
3185         i915_gem_object_unpin_pages(obj);
3186         return ret;
3187 }
3188
3189 void
3190 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3191 {
3192         /* If we don't have a page list set up, then we're not pinned
3193          * to GPU, and we can ignore the cache flush because it'll happen
3194          * again at bind time.
3195          */
3196         if (obj->pages == NULL)
3197                 return;
3198
3199         /*
3200          * Stolen memory is always coherent with the GPU as it is explicitly
3201          * marked as wc by the system, or the system is cache-coherent.
3202          */
3203         if (obj->stolen)
3204                 return;
3205
3206         /* If the GPU is snooping the contents of the CPU cache,
3207          * we do not need to manually clear the CPU cache lines.  However,
3208          * the caches are only snooped when the render cache is
3209          * flushed/invalidated.  As we always have to emit invalidations
3210          * and flushes when moving into and out of the RENDER domain, correct
3211          * snooping behaviour occurs naturally as the result of our domain
3212          * tracking.
3213          */
3214         if (obj->cache_level != I915_CACHE_NONE)
3215                 return;
3216
3217         trace_i915_gem_object_clflush(obj);
3218
3219         drm_clflush_sg(obj->pages);
3220 }
3221
3222 /** Flushes the GTT write domain for the object if it's dirty. */
3223 static void
3224 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3225 {
3226         uint32_t old_write_domain;
3227
3228         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3229                 return;
3230
3231         /* No actual flushing is required for the GTT write domain.  Writes
3232          * to it immediately go to main memory as far as we know, so there's
3233          * no chipset flush.  It also doesn't land in render cache.
3234          *
3235          * However, we do have to enforce the order so that all writes through
3236          * the GTT land before any writes to the device, such as updates to
3237          * the GATT itself.
3238          */
3239         wmb();
3240
3241         old_write_domain = obj->base.write_domain;
3242         obj->base.write_domain = 0;
3243
3244         trace_i915_gem_object_change_domain(obj,
3245                                             obj->base.read_domains,
3246                                             old_write_domain);
3247 }
3248
3249 /** Flushes the CPU write domain for the object if it's dirty. */
3250 static void
3251 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3252 {
3253         uint32_t old_write_domain;
3254
3255         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3256                 return;
3257
3258         i915_gem_clflush_object(obj);
3259         i915_gem_chipset_flush(obj->base.dev);
3260         old_write_domain = obj->base.write_domain;
3261         obj->base.write_domain = 0;
3262
3263         trace_i915_gem_object_change_domain(obj,
3264                                             obj->base.read_domains,
3265                                             old_write_domain);
3266 }
3267
3268 /**
3269  * Moves a single object to the GTT read, and possibly write domain.
3270  *
3271  * This function returns when the move is complete, including waiting on
3272  * flushes to occur.
3273  */
3274 int
3275 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3276 {
3277         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3278         uint32_t old_write_domain, old_read_domains;
3279         int ret;
3280
3281         /* Not valid to be called on unbound objects. */
3282         if (!i915_gem_obj_ggtt_bound(obj))
3283                 return -EINVAL;
3284
3285         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3286                 return 0;
3287
3288         ret = i915_gem_object_wait_rendering(obj, !write);
3289         if (ret)
3290                 return ret;
3291
3292         i915_gem_object_flush_cpu_write_domain(obj);
3293
3294         /* Serialise direct access to this object with the barriers for
3295          * coherent writes from the GPU, by effectively invalidating the
3296          * GTT domain upon first access.
3297          */
3298         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3299                 mb();
3300
3301         old_write_domain = obj->base.write_domain;
3302         old_read_domains = obj->base.read_domains;
3303
3304         /* It should now be out of any other write domains, and we can update
3305          * the domain values for our changes.
3306          */
3307         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3308         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3309         if (write) {
3310                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3311                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3312                 obj->dirty = 1;
3313         }
3314
3315         trace_i915_gem_object_change_domain(obj,
3316                                             old_read_domains,
3317                                             old_write_domain);
3318
3319         /* And bump the LRU for this access */
3320         if (i915_gem_object_is_inactive(obj))
3321                 list_move_tail(&obj->mm_list,
3322                                &dev_priv->gtt.base.inactive_list);
3323
3324         return 0;
3325 }
3326
3327 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3328                                     enum i915_cache_level cache_level)
3329 {
3330         struct drm_device *dev = obj->base.dev;
3331         drm_i915_private_t *dev_priv = dev->dev_private;
3332         struct i915_vma *vma = __i915_gem_obj_to_vma(obj);
3333         int ret;
3334
3335         if (obj->cache_level == cache_level)
3336                 return 0;
3337
3338         if (obj->pin_count) {
3339                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3340                 return -EBUSY;
3341         }
3342
3343         if (vma && !i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3344                 ret = i915_gem_object_unbind(obj);
3345                 if (ret)
3346                         return ret;
3347         }
3348
3349         if (i915_gem_obj_ggtt_bound(obj)) {
3350                 ret = i915_gem_object_finish_gpu(obj);
3351                 if (ret)
3352                         return ret;
3353
3354                 i915_gem_object_finish_gtt(obj);
3355
3356                 /* Before SandyBridge, you could not use tiling or fence
3357                  * registers with snooped memory, so relinquish any fences
3358                  * currently pointing to our region in the aperture.
3359                  */
3360                 if (INTEL_INFO(dev)->gen < 6) {
3361                         ret = i915_gem_object_put_fence(obj);
3362                         if (ret)
3363                                 return ret;
3364                 }
3365
3366                 if (obj->has_global_gtt_mapping)
3367                         i915_gem_gtt_bind_object(obj, cache_level);
3368                 if (obj->has_aliasing_ppgtt_mapping)
3369                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3370                                                obj, cache_level);
3371
3372                 i915_gem_obj_ggtt_set_color(obj, cache_level);
3373         }
3374
3375         if (cache_level == I915_CACHE_NONE) {
3376                 u32 old_read_domains, old_write_domain;
3377
3378                 /* If we're coming from LLC cached, then we haven't
3379                  * actually been tracking whether the data is in the
3380                  * CPU cache or not, since we only allow one bit set
3381                  * in obj->write_domain and have been skipping the clflushes.
3382                  * Just set it to the CPU cache for now.
3383                  */
3384                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3385                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3386
3387                 old_read_domains = obj->base.read_domains;
3388                 old_write_domain = obj->base.write_domain;
3389
3390                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3391                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3392
3393                 trace_i915_gem_object_change_domain(obj,
3394                                                     old_read_domains,
3395                                                     old_write_domain);
3396         }
3397
3398         obj->cache_level = cache_level;
3399         i915_gem_verify_gtt(dev);
3400         return 0;
3401 }
3402
3403 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3404                                struct drm_file *file)
3405 {
3406         struct drm_i915_gem_caching *args = data;
3407         struct drm_i915_gem_object *obj;
3408         int ret;
3409
3410         ret = i915_mutex_lock_interruptible(dev);
3411         if (ret)
3412                 return ret;
3413
3414         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3415         if (&obj->base == NULL) {
3416                 ret = -ENOENT;
3417                 goto unlock;
3418         }
3419
3420         args->caching = obj->cache_level != I915_CACHE_NONE;
3421
3422         drm_gem_object_unreference(&obj->base);
3423 unlock:
3424         mutex_unlock(&dev->struct_mutex);
3425         return ret;
3426 }
3427
3428 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3429                                struct drm_file *file)
3430 {
3431         struct drm_i915_gem_caching *args = data;
3432         struct drm_i915_gem_object *obj;
3433         enum i915_cache_level level;
3434         int ret;
3435
3436         switch (args->caching) {
3437         case I915_CACHING_NONE:
3438                 level = I915_CACHE_NONE;
3439                 break;
3440         case I915_CACHING_CACHED:
3441                 level = I915_CACHE_LLC;
3442                 break;
3443         default:
3444                 return -EINVAL;
3445         }
3446
3447         ret = i915_mutex_lock_interruptible(dev);
3448         if (ret)
3449                 return ret;
3450
3451         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3452         if (&obj->base == NULL) {
3453                 ret = -ENOENT;
3454                 goto unlock;
3455         }
3456
3457         ret = i915_gem_object_set_cache_level(obj, level);
3458
3459         drm_gem_object_unreference(&obj->base);
3460 unlock:
3461         mutex_unlock(&dev->struct_mutex);
3462         return ret;
3463 }
3464
3465 /*
3466  * Prepare buffer for display plane (scanout, cursors, etc).
3467  * Can be called from an uninterruptible phase (modesetting) and allows
3468  * any flushes to be pipelined (for pageflips).
3469  */
3470 int
3471 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3472                                      u32 alignment,
3473                                      struct intel_ring_buffer *pipelined)
3474 {
3475         u32 old_read_domains, old_write_domain;
3476         int ret;
3477
3478         if (pipelined != obj->ring) {
3479                 ret = i915_gem_object_sync(obj, pipelined);
3480                 if (ret)
3481                         return ret;
3482         }
3483
3484         /* The display engine is not coherent with the LLC cache on gen6.  As
3485          * a result, we make sure that the pinning that is about to occur is
3486          * done with uncached PTEs. This is lowest common denominator for all
3487          * chipsets.
3488          *
3489          * However for gen6+, we could do better by using the GFDT bit instead
3490          * of uncaching, which would allow us to flush all the LLC-cached data
3491          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3492          */
3493         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3494         if (ret)
3495                 return ret;
3496
3497         /* As the user may map the buffer once pinned in the display plane
3498          * (e.g. libkms for the bootup splash), we have to ensure that we
3499          * always use map_and_fenceable for all scanout buffers.
3500          */
3501         ret = i915_gem_object_pin(obj, alignment, true, false);
3502         if (ret)
3503                 return ret;
3504
3505         i915_gem_object_flush_cpu_write_domain(obj);
3506
3507         old_write_domain = obj->base.write_domain;
3508         old_read_domains = obj->base.read_domains;
3509
3510         /* It should now be out of any other write domains, and we can update
3511          * the domain values for our changes.
3512          */
3513         obj->base.write_domain = 0;
3514         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3515
3516         trace_i915_gem_object_change_domain(obj,
3517                                             old_read_domains,
3518                                             old_write_domain);
3519
3520         return 0;
3521 }
3522
3523 int
3524 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3525 {
3526         int ret;
3527
3528         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3529                 return 0;
3530
3531         ret = i915_gem_object_wait_rendering(obj, false);
3532         if (ret)
3533                 return ret;
3534
3535         /* Ensure that we invalidate the GPU's caches and TLBs. */
3536         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3537         return 0;
3538 }
3539
3540 /**
3541  * Moves a single object to the CPU read, and possibly write domain.
3542  *
3543  * This function returns when the move is complete, including waiting on
3544  * flushes to occur.
3545  */
3546 int
3547 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3548 {
3549         uint32_t old_write_domain, old_read_domains;
3550         int ret;
3551
3552         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3553                 return 0;
3554
3555         ret = i915_gem_object_wait_rendering(obj, !write);
3556         if (ret)
3557                 return ret;
3558
3559         i915_gem_object_flush_gtt_write_domain(obj);
3560
3561         old_write_domain = obj->base.write_domain;
3562         old_read_domains = obj->base.read_domains;
3563
3564         /* Flush the CPU cache if it's still invalid. */
3565         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3566                 i915_gem_clflush_object(obj);
3567
3568                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3569         }
3570
3571         /* It should now be out of any other write domains, and we can update
3572          * the domain values for our changes.
3573          */
3574         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3575
3576         /* If we're writing through the CPU, then the GPU read domains will
3577          * need to be invalidated at next use.
3578          */
3579         if (write) {
3580                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3581                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3582         }
3583
3584         trace_i915_gem_object_change_domain(obj,
3585                                             old_read_domains,
3586                                             old_write_domain);
3587
3588         return 0;
3589 }
3590
3591 /* Throttle our rendering by waiting until the ring has completed our requests
3592  * emitted over 20 msec ago.
3593  *
3594  * Note that if we were to use the current jiffies each time around the loop,
3595  * we wouldn't escape the function with any frames outstanding if the time to
3596  * render a frame was over 20ms.
3597  *
3598  * This should get us reasonable parallelism between CPU and GPU but also
3599  * relatively low latency when blocking on a particular request to finish.
3600  */
3601 static int
3602 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3603 {
3604         struct drm_i915_private *dev_priv = dev->dev_private;
3605         struct drm_i915_file_private *file_priv = file->driver_priv;
3606         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3607         struct drm_i915_gem_request *request;
3608         struct intel_ring_buffer *ring = NULL;
3609         unsigned reset_counter;
3610         u32 seqno = 0;
3611         int ret;
3612
3613         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3614         if (ret)
3615                 return ret;
3616
3617         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3618         if (ret)
3619                 return ret;
3620
3621         spin_lock(&file_priv->mm.lock);
3622         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3623                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3624                         break;
3625
3626                 ring = request->ring;
3627                 seqno = request->seqno;
3628         }
3629         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3630         spin_unlock(&file_priv->mm.lock);
3631
3632         if (seqno == 0)
3633                 return 0;
3634
3635         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3636         if (ret == 0)
3637                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3638
3639         return ret;
3640 }
3641
3642 int
3643 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3644                     uint32_t alignment,
3645                     bool map_and_fenceable,
3646                     bool nonblocking)
3647 {
3648         int ret;
3649
3650         if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3651                 return -EBUSY;
3652
3653         if (i915_gem_obj_ggtt_bound(obj)) {
3654                 if ((alignment && i915_gem_obj_ggtt_offset(obj) & (alignment - 1)) ||
3655                     (map_and_fenceable && !obj->map_and_fenceable)) {
3656                         WARN(obj->pin_count,
3657                              "bo is already pinned with incorrect alignment:"
3658                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3659                              " obj->map_and_fenceable=%d\n",
3660                              i915_gem_obj_ggtt_offset(obj), alignment,
3661                              map_and_fenceable,
3662                              obj->map_and_fenceable);
3663                         ret = i915_gem_object_unbind(obj);
3664                         if (ret)
3665                                 return ret;
3666                 }
3667         }
3668
3669         if (!i915_gem_obj_ggtt_bound(obj)) {
3670                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3671
3672                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3673                                                   map_and_fenceable,
3674                                                   nonblocking);
3675                 if (ret)
3676                         return ret;
3677
3678                 if (!dev_priv->mm.aliasing_ppgtt)
3679                         i915_gem_gtt_bind_object(obj, obj->cache_level);
3680         }
3681
3682         if (!obj->has_global_gtt_mapping && map_and_fenceable)
3683                 i915_gem_gtt_bind_object(obj, obj->cache_level);
3684
3685         obj->pin_count++;
3686         obj->pin_mappable |= map_and_fenceable;
3687
3688         return 0;
3689 }
3690
3691 void
3692 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3693 {
3694         BUG_ON(obj->pin_count == 0);
3695         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
3696
3697         if (--obj->pin_count == 0)
3698                 obj->pin_mappable = false;
3699 }
3700
3701 int
3702 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3703                    struct drm_file *file)
3704 {
3705         struct drm_i915_gem_pin *args = data;
3706         struct drm_i915_gem_object *obj;
3707         int ret;
3708
3709         ret = i915_mutex_lock_interruptible(dev);
3710         if (ret)
3711                 return ret;
3712
3713         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3714         if (&obj->base == NULL) {
3715                 ret = -ENOENT;
3716                 goto unlock;
3717         }
3718
3719         if (obj->madv != I915_MADV_WILLNEED) {
3720                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3721                 ret = -EINVAL;
3722                 goto out;
3723         }
3724
3725         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3726                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3727                           args->handle);
3728                 ret = -EINVAL;
3729                 goto out;
3730         }
3731
3732         if (obj->user_pin_count == 0) {
3733                 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3734                 if (ret)
3735                         goto out;
3736         }
3737
3738         obj->user_pin_count++;
3739         obj->pin_filp = file;
3740
3741         /* XXX - flush the CPU caches for pinned objects
3742          * as the X server doesn't manage domains yet
3743          */
3744         i915_gem_object_flush_cpu_write_domain(obj);
3745         args->offset = i915_gem_obj_ggtt_offset(obj);
3746 out:
3747         drm_gem_object_unreference(&obj->base);
3748 unlock:
3749         mutex_unlock(&dev->struct_mutex);
3750         return ret;
3751 }
3752
3753 int
3754 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3755                      struct drm_file *file)
3756 {
3757         struct drm_i915_gem_pin *args = data;
3758         struct drm_i915_gem_object *obj;
3759         int ret;
3760
3761         ret = i915_mutex_lock_interruptible(dev);
3762         if (ret)
3763                 return ret;
3764
3765         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3766         if (&obj->base == NULL) {
3767                 ret = -ENOENT;
3768                 goto unlock;
3769         }
3770
3771         if (obj->pin_filp != file) {
3772                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3773                           args->handle);
3774                 ret = -EINVAL;
3775                 goto out;
3776         }
3777         obj->user_pin_count--;
3778         if (obj->user_pin_count == 0) {
3779                 obj->pin_filp = NULL;
3780                 i915_gem_object_unpin(obj);
3781         }
3782
3783 out:
3784         drm_gem_object_unreference(&obj->base);
3785 unlock:
3786         mutex_unlock(&dev->struct_mutex);
3787         return ret;
3788 }
3789
3790 int
3791 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3792                     struct drm_file *file)
3793 {
3794         struct drm_i915_gem_busy *args = data;
3795         struct drm_i915_gem_object *obj;
3796         int ret;
3797
3798         ret = i915_mutex_lock_interruptible(dev);
3799         if (ret)
3800                 return ret;
3801
3802         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3803         if (&obj->base == NULL) {
3804                 ret = -ENOENT;
3805                 goto unlock;
3806         }
3807
3808         /* Count all active objects as busy, even if they are currently not used
3809          * by the gpu. Users of this interface expect objects to eventually
3810          * become non-busy without any further actions, therefore emit any
3811          * necessary flushes here.
3812          */
3813         ret = i915_gem_object_flush_active(obj);
3814
3815         args->busy = obj->active;
3816         if (obj->ring) {
3817                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3818                 args->busy |= intel_ring_flag(obj->ring) << 16;
3819         }
3820
3821         drm_gem_object_unreference(&obj->base);
3822 unlock:
3823         mutex_unlock(&dev->struct_mutex);
3824         return ret;
3825 }
3826
3827 int
3828 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3829                         struct drm_file *file_priv)
3830 {
3831         return i915_gem_ring_throttle(dev, file_priv);
3832 }
3833
3834 int
3835 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3836                        struct drm_file *file_priv)
3837 {
3838         struct drm_i915_gem_madvise *args = data;
3839         struct drm_i915_gem_object *obj;
3840         int ret;
3841
3842         switch (args->madv) {
3843         case I915_MADV_DONTNEED:
3844         case I915_MADV_WILLNEED:
3845             break;
3846         default:
3847             return -EINVAL;
3848         }
3849
3850         ret = i915_mutex_lock_interruptible(dev);
3851         if (ret)
3852                 return ret;
3853
3854         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3855         if (&obj->base == NULL) {
3856                 ret = -ENOENT;
3857                 goto unlock;
3858         }
3859
3860         if (obj->pin_count) {
3861                 ret = -EINVAL;
3862                 goto out;
3863         }
3864
3865         if (obj->madv != __I915_MADV_PURGED)
3866                 obj->madv = args->madv;
3867
3868         /* if the object is no longer attached, discard its backing storage */
3869         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3870                 i915_gem_object_truncate(obj);
3871
3872         args->retained = obj->madv != __I915_MADV_PURGED;
3873
3874 out:
3875         drm_gem_object_unreference(&obj->base);
3876 unlock:
3877         mutex_unlock(&dev->struct_mutex);
3878         return ret;
3879 }
3880
3881 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3882                           const struct drm_i915_gem_object_ops *ops)
3883 {
3884         INIT_LIST_HEAD(&obj->mm_list);
3885         INIT_LIST_HEAD(&obj->global_list);
3886         INIT_LIST_HEAD(&obj->ring_list);
3887         INIT_LIST_HEAD(&obj->exec_list);
3888         INIT_LIST_HEAD(&obj->vma_list);
3889
3890         obj->ops = ops;
3891
3892         obj->fence_reg = I915_FENCE_REG_NONE;
3893         obj->madv = I915_MADV_WILLNEED;
3894         /* Avoid an unnecessary call to unbind on the first bind. */
3895         obj->map_and_fenceable = true;
3896
3897         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3898 }
3899
3900 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3901         .get_pages = i915_gem_object_get_pages_gtt,
3902         .put_pages = i915_gem_object_put_pages_gtt,
3903 };
3904
3905 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3906                                                   size_t size)
3907 {
3908         struct drm_i915_gem_object *obj;
3909         struct address_space *mapping;
3910         gfp_t mask;
3911
3912         obj = i915_gem_object_alloc(dev);
3913         if (obj == NULL)
3914                 return NULL;
3915
3916         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3917                 i915_gem_object_free(obj);
3918                 return NULL;
3919         }
3920
3921         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3922         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3923                 /* 965gm cannot relocate objects above 4GiB. */
3924                 mask &= ~__GFP_HIGHMEM;
3925                 mask |= __GFP_DMA32;
3926         }
3927
3928         mapping = file_inode(obj->base.filp)->i_mapping;
3929         mapping_set_gfp_mask(mapping, mask);
3930
3931         i915_gem_object_init(obj, &i915_gem_object_ops);
3932
3933         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3934         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3935
3936         if (HAS_LLC(dev)) {
3937                 /* On some devices, we can have the GPU use the LLC (the CPU
3938                  * cache) for about a 10% performance improvement
3939                  * compared to uncached.  Graphics requests other than
3940                  * display scanout are coherent with the CPU in
3941                  * accessing this cache.  This means in this mode we
3942                  * don't need to clflush on the CPU side, and on the
3943                  * GPU side we only need to flush internal caches to
3944                  * get data visible to the CPU.
3945                  *
3946                  * However, we maintain the display planes as UC, and so
3947                  * need to rebind when first used as such.
3948                  */
3949                 obj->cache_level = I915_CACHE_LLC;
3950         } else
3951                 obj->cache_level = I915_CACHE_NONE;
3952
3953         trace_i915_gem_object_create(obj);
3954
3955         return obj;
3956 }
3957
3958 int i915_gem_init_object(struct drm_gem_object *obj)
3959 {
3960         BUG();
3961
3962         return 0;
3963 }
3964
3965 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3966 {
3967         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3968         struct drm_device *dev = obj->base.dev;
3969         drm_i915_private_t *dev_priv = dev->dev_private;
3970
3971         trace_i915_gem_object_destroy(obj);
3972
3973         if (obj->phys_obj)
3974                 i915_gem_detach_phys_object(dev, obj);
3975
3976         obj->pin_count = 0;
3977         if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3978                 bool was_interruptible;
3979
3980                 was_interruptible = dev_priv->mm.interruptible;
3981                 dev_priv->mm.interruptible = false;
3982
3983                 WARN_ON(i915_gem_object_unbind(obj));
3984
3985                 dev_priv->mm.interruptible = was_interruptible;
3986         }
3987
3988         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3989          * before progressing. */
3990         if (obj->stolen)
3991                 i915_gem_object_unpin_pages(obj);
3992
3993         if (WARN_ON(obj->pages_pin_count))
3994                 obj->pages_pin_count = 0;
3995         i915_gem_object_put_pages(obj);
3996         i915_gem_object_free_mmap_offset(obj);
3997         i915_gem_object_release_stolen(obj);
3998
3999         BUG_ON(obj->pages);
4000
4001         if (obj->base.import_attach)
4002                 drm_prime_gem_destroy(&obj->base, NULL);
4003
4004         drm_gem_object_release(&obj->base);
4005         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4006
4007         kfree(obj->bit_17);
4008         i915_gem_object_free(obj);
4009 }
4010
4011 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
4012                                      struct i915_address_space *vm)
4013 {
4014         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4015         if (vma == NULL)
4016                 return ERR_PTR(-ENOMEM);
4017
4018         INIT_LIST_HEAD(&vma->vma_link);
4019         vma->vm = vm;
4020         vma->obj = obj;
4021
4022         return vma;
4023 }
4024
4025 void i915_gem_vma_destroy(struct i915_vma *vma)
4026 {
4027         WARN_ON(vma->node.allocated);
4028         kfree(vma);
4029 }
4030
4031 int
4032 i915_gem_idle(struct drm_device *dev)
4033 {
4034         drm_i915_private_t *dev_priv = dev->dev_private;
4035         int ret;
4036
4037         if (dev_priv->ums.mm_suspended) {
4038                 mutex_unlock(&dev->struct_mutex);
4039                 return 0;
4040         }
4041
4042         ret = i915_gpu_idle(dev);
4043         if (ret) {
4044                 mutex_unlock(&dev->struct_mutex);
4045                 return ret;
4046         }
4047         i915_gem_retire_requests(dev);
4048
4049         /* Under UMS, be paranoid and evict. */
4050         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4051                 i915_gem_evict_everything(dev);
4052
4053         i915_gem_reset_fences(dev);
4054
4055         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4056
4057         i915_kernel_lost_context(dev);
4058         i915_gem_cleanup_ringbuffer(dev);
4059
4060         /* Cancel the retire work handler, which should be idle now. */
4061         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4062
4063         return 0;
4064 }
4065
4066 void i915_gem_l3_remap(struct drm_device *dev)
4067 {
4068         drm_i915_private_t *dev_priv = dev->dev_private;
4069         u32 misccpctl;
4070         int i;
4071
4072         if (!HAS_L3_GPU_CACHE(dev))
4073                 return;
4074
4075         if (!dev_priv->l3_parity.remap_info)
4076                 return;
4077
4078         misccpctl = I915_READ(GEN7_MISCCPCTL);
4079         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4080         POSTING_READ(GEN7_MISCCPCTL);
4081
4082         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4083                 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4084                 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4085                         DRM_DEBUG("0x%x was already programmed to %x\n",
4086                                   GEN7_L3LOG_BASE + i, remap);
4087                 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4088                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
4089                 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4090         }
4091
4092         /* Make sure all the writes land before disabling dop clock gating */
4093         POSTING_READ(GEN7_L3LOG_BASE);
4094
4095         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4096 }
4097
4098 void i915_gem_init_swizzling(struct drm_device *dev)
4099 {
4100         drm_i915_private_t *dev_priv = dev->dev_private;
4101
4102         if (INTEL_INFO(dev)->gen < 5 ||
4103             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4104                 return;
4105
4106         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4107                                  DISP_TILE_SURFACE_SWIZZLING);
4108
4109         if (IS_GEN5(dev))
4110                 return;
4111
4112         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4113         if (IS_GEN6(dev))
4114                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4115         else if (IS_GEN7(dev))
4116                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4117         else
4118                 BUG();
4119 }
4120
4121 static bool
4122 intel_enable_blt(struct drm_device *dev)
4123 {
4124         if (!HAS_BLT(dev))
4125                 return false;
4126
4127         /* The blitter was dysfunctional on early prototypes */
4128         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4129                 DRM_INFO("BLT not supported on this pre-production hardware;"
4130                          " graphics performance will be degraded.\n");
4131                 return false;
4132         }
4133
4134         return true;
4135 }
4136
4137 static int i915_gem_init_rings(struct drm_device *dev)
4138 {
4139         struct drm_i915_private *dev_priv = dev->dev_private;
4140         int ret;
4141
4142         ret = intel_init_render_ring_buffer(dev);
4143         if (ret)
4144                 return ret;
4145
4146         if (HAS_BSD(dev)) {
4147                 ret = intel_init_bsd_ring_buffer(dev);
4148                 if (ret)
4149                         goto cleanup_render_ring;
4150         }
4151
4152         if (intel_enable_blt(dev)) {
4153                 ret = intel_init_blt_ring_buffer(dev);
4154                 if (ret)
4155                         goto cleanup_bsd_ring;
4156         }
4157
4158         if (HAS_VEBOX(dev)) {
4159                 ret = intel_init_vebox_ring_buffer(dev);
4160                 if (ret)
4161                         goto cleanup_blt_ring;
4162         }
4163
4164
4165         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4166         if (ret)
4167                 goto cleanup_vebox_ring;
4168
4169         return 0;
4170
4171 cleanup_vebox_ring:
4172         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4173 cleanup_blt_ring:
4174         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4175 cleanup_bsd_ring:
4176         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4177 cleanup_render_ring:
4178         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4179
4180         return ret;
4181 }
4182
4183 int
4184 i915_gem_init_hw(struct drm_device *dev)
4185 {
4186         drm_i915_private_t *dev_priv = dev->dev_private;
4187         int ret;
4188
4189         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4190                 return -EIO;
4191
4192         if (dev_priv->ellc_size)
4193                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4194
4195         if (HAS_PCH_NOP(dev)) {
4196                 u32 temp = I915_READ(GEN7_MSG_CTL);
4197                 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4198                 I915_WRITE(GEN7_MSG_CTL, temp);
4199         }
4200
4201         i915_gem_l3_remap(dev);
4202
4203         i915_gem_init_swizzling(dev);
4204
4205         ret = i915_gem_init_rings(dev);
4206         if (ret)
4207                 return ret;
4208
4209         /*
4210          * XXX: There was some w/a described somewhere suggesting loading
4211          * contexts before PPGTT.
4212          */
4213         i915_gem_context_init(dev);
4214         if (dev_priv->mm.aliasing_ppgtt) {
4215                 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4216                 if (ret) {
4217                         i915_gem_cleanup_aliasing_ppgtt(dev);
4218                         DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4219                 }
4220         }
4221
4222         return 0;
4223 }
4224
4225 int i915_gem_init(struct drm_device *dev)
4226 {
4227         struct drm_i915_private *dev_priv = dev->dev_private;
4228         int ret;
4229
4230         mutex_lock(&dev->struct_mutex);
4231
4232         if (IS_VALLEYVIEW(dev)) {
4233                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4234                 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4235                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4236                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4237         }
4238
4239         i915_gem_init_global_gtt(dev);
4240
4241         ret = i915_gem_init_hw(dev);
4242         mutex_unlock(&dev->struct_mutex);
4243         if (ret) {
4244                 i915_gem_cleanup_aliasing_ppgtt(dev);
4245                 return ret;
4246         }
4247
4248         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4249         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4250                 dev_priv->dri1.allow_batchbuffer = 1;
4251         return 0;
4252 }
4253
4254 void
4255 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4256 {
4257         drm_i915_private_t *dev_priv = dev->dev_private;
4258         struct intel_ring_buffer *ring;
4259         int i;
4260
4261         for_each_ring(ring, dev_priv, i)
4262                 intel_cleanup_ring_buffer(ring);
4263 }
4264
4265 int
4266 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4267                        struct drm_file *file_priv)
4268 {
4269         struct drm_i915_private *dev_priv = dev->dev_private;
4270         int ret;
4271
4272         if (drm_core_check_feature(dev, DRIVER_MODESET))
4273                 return 0;
4274
4275         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4276                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4277                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4278         }
4279
4280         mutex_lock(&dev->struct_mutex);
4281         dev_priv->ums.mm_suspended = 0;
4282
4283         ret = i915_gem_init_hw(dev);
4284         if (ret != 0) {
4285                 mutex_unlock(&dev->struct_mutex);
4286                 return ret;
4287         }
4288
4289         BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4290         mutex_unlock(&dev->struct_mutex);
4291
4292         ret = drm_irq_install(dev);
4293         if (ret)
4294                 goto cleanup_ringbuffer;
4295
4296         return 0;
4297
4298 cleanup_ringbuffer:
4299         mutex_lock(&dev->struct_mutex);
4300         i915_gem_cleanup_ringbuffer(dev);
4301         dev_priv->ums.mm_suspended = 1;
4302         mutex_unlock(&dev->struct_mutex);
4303
4304         return ret;
4305 }
4306
4307 int
4308 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4309                        struct drm_file *file_priv)
4310 {
4311         struct drm_i915_private *dev_priv = dev->dev_private;
4312         int ret;
4313
4314         if (drm_core_check_feature(dev, DRIVER_MODESET))
4315                 return 0;
4316
4317         drm_irq_uninstall(dev);
4318
4319         mutex_lock(&dev->struct_mutex);
4320         ret =  i915_gem_idle(dev);
4321
4322         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4323          * We need to replace this with a semaphore, or something.
4324          * And not confound ums.mm_suspended!
4325          */
4326         if (ret != 0)
4327                 dev_priv->ums.mm_suspended = 1;
4328         mutex_unlock(&dev->struct_mutex);
4329
4330         return ret;
4331 }
4332
4333 void
4334 i915_gem_lastclose(struct drm_device *dev)
4335 {
4336         int ret;
4337
4338         if (drm_core_check_feature(dev, DRIVER_MODESET))
4339                 return;
4340
4341         mutex_lock(&dev->struct_mutex);
4342         ret = i915_gem_idle(dev);
4343         if (ret)
4344                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4345         mutex_unlock(&dev->struct_mutex);
4346 }
4347
4348 static void
4349 init_ring_lists(struct intel_ring_buffer *ring)
4350 {
4351         INIT_LIST_HEAD(&ring->active_list);
4352         INIT_LIST_HEAD(&ring->request_list);
4353 }
4354
4355 void
4356 i915_gem_load(struct drm_device *dev)
4357 {
4358         drm_i915_private_t *dev_priv = dev->dev_private;
4359         int i;
4360
4361         dev_priv->slab =
4362                 kmem_cache_create("i915_gem_object",
4363                                   sizeof(struct drm_i915_gem_object), 0,
4364                                   SLAB_HWCACHE_ALIGN,
4365                                   NULL);
4366
4367         INIT_LIST_HEAD(&dev_priv->gtt.base.active_list);
4368         INIT_LIST_HEAD(&dev_priv->gtt.base.inactive_list);
4369         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4370         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4371         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4372         for (i = 0; i < I915_NUM_RINGS; i++)
4373                 init_ring_lists(&dev_priv->ring[i]);
4374         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4375                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4376         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4377                           i915_gem_retire_work_handler);
4378         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4379
4380         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4381         if (IS_GEN3(dev)) {
4382                 I915_WRITE(MI_ARB_STATE,
4383                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4384         }
4385
4386         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4387
4388         /* Old X drivers will take 0-2 for front, back, depth buffers */
4389         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4390                 dev_priv->fence_reg_start = 3;
4391
4392         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4393                 dev_priv->num_fence_regs = 32;
4394         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4395                 dev_priv->num_fence_regs = 16;
4396         else
4397                 dev_priv->num_fence_regs = 8;
4398
4399         /* Initialize fence registers to zero */
4400         i915_gem_reset_fences(dev);
4401
4402         i915_gem_detect_bit_6_swizzle(dev);
4403         init_waitqueue_head(&dev_priv->pending_flip_queue);
4404
4405         dev_priv->mm.interruptible = true;
4406
4407         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4408         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4409         register_shrinker(&dev_priv->mm.inactive_shrinker);
4410 }
4411
4412 /*
4413  * Create a physically contiguous memory object for this object
4414  * e.g. for cursor + overlay regs
4415  */
4416 static int i915_gem_init_phys_object(struct drm_device *dev,
4417                                      int id, int size, int align)
4418 {
4419         drm_i915_private_t *dev_priv = dev->dev_private;
4420         struct drm_i915_gem_phys_object *phys_obj;
4421         int ret;
4422
4423         if (dev_priv->mm.phys_objs[id - 1] || !size)
4424                 return 0;
4425
4426         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4427         if (!phys_obj)
4428                 return -ENOMEM;
4429
4430         phys_obj->id = id;
4431
4432         phys_obj->handle = drm_pci_alloc(dev, size, align);
4433         if (!phys_obj->handle) {
4434                 ret = -ENOMEM;
4435                 goto kfree_obj;
4436         }
4437 #ifdef CONFIG_X86
4438         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4439 #endif
4440
4441         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4442
4443         return 0;
4444 kfree_obj:
4445         kfree(phys_obj);
4446         return ret;
4447 }
4448
4449 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4450 {
4451         drm_i915_private_t *dev_priv = dev->dev_private;
4452         struct drm_i915_gem_phys_object *phys_obj;
4453
4454         if (!dev_priv->mm.phys_objs[id - 1])
4455                 return;
4456
4457         phys_obj = dev_priv->mm.phys_objs[id - 1];
4458         if (phys_obj->cur_obj) {
4459                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4460         }
4461
4462 #ifdef CONFIG_X86
4463         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4464 #endif
4465         drm_pci_free(dev, phys_obj->handle);
4466         kfree(phys_obj);
4467         dev_priv->mm.phys_objs[id - 1] = NULL;
4468 }
4469
4470 void i915_gem_free_all_phys_object(struct drm_device *dev)
4471 {
4472         int i;
4473
4474         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4475                 i915_gem_free_phys_object(dev, i);
4476 }
4477
4478 void i915_gem_detach_phys_object(struct drm_device *dev,
4479                                  struct drm_i915_gem_object *obj)
4480 {
4481         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4482         char *vaddr;
4483         int i;
4484         int page_count;
4485
4486         if (!obj->phys_obj)
4487                 return;
4488         vaddr = obj->phys_obj->handle->vaddr;
4489
4490         page_count = obj->base.size / PAGE_SIZE;
4491         for (i = 0; i < page_count; i++) {
4492                 struct page *page = shmem_read_mapping_page(mapping, i);
4493                 if (!IS_ERR(page)) {
4494                         char *dst = kmap_atomic(page);
4495                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4496                         kunmap_atomic(dst);
4497
4498                         drm_clflush_pages(&page, 1);
4499
4500                         set_page_dirty(page);
4501                         mark_page_accessed(page);
4502                         page_cache_release(page);
4503                 }
4504         }
4505         i915_gem_chipset_flush(dev);
4506
4507         obj->phys_obj->cur_obj = NULL;
4508         obj->phys_obj = NULL;
4509 }
4510
4511 int
4512 i915_gem_attach_phys_object(struct drm_device *dev,
4513                             struct drm_i915_gem_object *obj,
4514                             int id,
4515                             int align)
4516 {
4517         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4518         drm_i915_private_t *dev_priv = dev->dev_private;
4519         int ret = 0;
4520         int page_count;
4521         int i;
4522
4523         if (id > I915_MAX_PHYS_OBJECT)
4524                 return -EINVAL;
4525
4526         if (obj->phys_obj) {
4527                 if (obj->phys_obj->id == id)
4528                         return 0;
4529                 i915_gem_detach_phys_object(dev, obj);
4530         }
4531
4532         /* create a new object */
4533         if (!dev_priv->mm.phys_objs[id - 1]) {
4534                 ret = i915_gem_init_phys_object(dev, id,
4535                                                 obj->base.size, align);
4536                 if (ret) {
4537                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4538                                   id, obj->base.size);
4539                         return ret;
4540                 }
4541         }
4542
4543         /* bind to the object */
4544         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4545         obj->phys_obj->cur_obj = obj;
4546
4547         page_count = obj->base.size / PAGE_SIZE;
4548
4549         for (i = 0; i < page_count; i++) {
4550                 struct page *page;
4551                 char *dst, *src;
4552
4553                 page = shmem_read_mapping_page(mapping, i);
4554                 if (IS_ERR(page))
4555                         return PTR_ERR(page);
4556
4557                 src = kmap_atomic(page);
4558                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4559                 memcpy(dst, src, PAGE_SIZE);
4560                 kunmap_atomic(src);
4561
4562                 mark_page_accessed(page);
4563                 page_cache_release(page);
4564         }
4565
4566         return 0;
4567 }
4568
4569 static int
4570 i915_gem_phys_pwrite(struct drm_device *dev,
4571                      struct drm_i915_gem_object *obj,
4572                      struct drm_i915_gem_pwrite *args,
4573                      struct drm_file *file_priv)
4574 {
4575         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4576         char __user *user_data = to_user_ptr(args->data_ptr);
4577
4578         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4579                 unsigned long unwritten;
4580
4581                 /* The physical object once assigned is fixed for the lifetime
4582                  * of the obj, so we can safely drop the lock and continue
4583                  * to access vaddr.
4584                  */
4585                 mutex_unlock(&dev->struct_mutex);
4586                 unwritten = copy_from_user(vaddr, user_data, args->size);
4587                 mutex_lock(&dev->struct_mutex);
4588                 if (unwritten)
4589                         return -EFAULT;
4590         }
4591
4592         i915_gem_chipset_flush(dev);
4593         return 0;
4594 }
4595
4596 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4597 {
4598         struct drm_i915_file_private *file_priv = file->driver_priv;
4599
4600         /* Clean up our request list when the client is going away, so that
4601          * later retire_requests won't dereference our soon-to-be-gone
4602          * file_priv.
4603          */
4604         spin_lock(&file_priv->mm.lock);
4605         while (!list_empty(&file_priv->mm.request_list)) {
4606                 struct drm_i915_gem_request *request;
4607
4608                 request = list_first_entry(&file_priv->mm.request_list,
4609                                            struct drm_i915_gem_request,
4610                                            client_list);
4611                 list_del(&request->client_list);
4612                 request->file_priv = NULL;
4613         }
4614         spin_unlock(&file_priv->mm.lock);
4615 }
4616
4617 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4618 {
4619         if (!mutex_is_locked(mutex))
4620                 return false;
4621
4622 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4623         return mutex->owner == task;
4624 #else
4625         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4626         return false;
4627 #endif
4628 }
4629
4630 static int
4631 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4632 {
4633         struct drm_i915_private *dev_priv =
4634                 container_of(shrinker,
4635                              struct drm_i915_private,
4636                              mm.inactive_shrinker);
4637         struct drm_device *dev = dev_priv->dev;
4638         struct i915_address_space *vm = &dev_priv->gtt.base;
4639         struct drm_i915_gem_object *obj;
4640         int nr_to_scan = sc->nr_to_scan;
4641         bool unlock = true;
4642         int cnt;
4643
4644         if (!mutex_trylock(&dev->struct_mutex)) {
4645                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4646                         return 0;
4647
4648                 if (dev_priv->mm.shrinker_no_lock_stealing)
4649                         return 0;
4650
4651                 unlock = false;
4652         }
4653
4654         if (nr_to_scan) {
4655                 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4656                 if (nr_to_scan > 0)
4657                         nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4658                                                         false);
4659                 if (nr_to_scan > 0)
4660                         i915_gem_shrink_all(dev_priv);
4661         }
4662
4663         cnt = 0;
4664         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4665                 if (obj->pages_pin_count == 0)
4666                         cnt += obj->base.size >> PAGE_SHIFT;
4667         list_for_each_entry(obj, &vm->inactive_list, global_list)
4668                 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4669                         cnt += obj->base.size >> PAGE_SHIFT;
4670
4671         if (unlock)
4672                 mutex_unlock(&dev->struct_mutex);
4673         return cnt;
4674 }