drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/oom.h>
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  43                                                    bool force);
  44 static __must_check int
  45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  46                                bool readonly);
  47 static void
  48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  57                                              struct shrink_control *sc);
  58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  59                                             struct shrink_control *sc);
  60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  61                                  unsigned long event,
  62                                  void *ptr);
  63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  64
  65 static bool cpu_cache_is_coherent(struct drm_device *dev,
  66                                   enum i915_cache_level level)
  67 {
  68         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  69 }
  70
  71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  72 {
  73         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  74                 return true;
  75
  76         return obj->pin_display;
  77 }
  78
  79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  80 {
  81         if (obj->tiling_mode)
  82                 i915_gem_release_mmap(obj);
  83
  84         /* As we do not have an associated fence register, we will force
  85          * a tiling change if we ever need to acquire one.
  86          */
  87         obj->fence_dirty = false;
  88         obj->fence_reg = I915_FENCE_REG_NONE;
  89 }
  90
  91 /* some bookkeeping */
  92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  93                                   size_t size)
  94 {
  95         spin_lock(&dev_priv->mm.object_stat_lock);
  96         dev_priv->mm.object_count++;
  97         dev_priv->mm.object_memory += size;
  98         spin_unlock(&dev_priv->mm.object_stat_lock);
  99 }
 100
 101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 102                                      size_t size)
 103 {
 104         spin_lock(&dev_priv->mm.object_stat_lock);
 105         dev_priv->mm.object_count--;
 106         dev_priv->mm.object_memory -= size;
 107         spin_unlock(&dev_priv->mm.object_stat_lock);
 108 }
 109
 110 static int
 111 i915_gem_wait_for_error(struct i915_gpu_error *error)
 112 {
 113         int ret;
 114
 115 #define EXIT_COND (!i915_reset_in_progress(error) || \
 116                    i915_terminally_wedged(error))
 117         if (EXIT_COND)
 118                 return 0;
 119
 120         /*
 121          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 122          * userspace. If it takes that long something really bad is going on and
 123          * we should simply try to bail out and fail as gracefully as possible.
 124          */
 125         ret = wait_event_interruptible_timeout(error->reset_queue,
 126                                                EXIT_COND,
 127                                                10*HZ);
 128         if (ret == 0) {
 129                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 130                 return -EIO;
 131         } else if (ret < 0) {
 132                 return ret;
 133         }
 134 #undef EXIT_COND
 135
 136         return 0;
 137 }
 138
 139 int i915_mutex_lock_interruptible(struct drm_device *dev)
 140 {
 141         struct drm_i915_private *dev_priv = dev->dev_private;
 142         int ret;
 143
 144         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 145         if (ret)
 146                 return ret;
 147
 148         ret = mutex_lock_interruptible(&dev->struct_mutex);
 149         if (ret)
 150                 return ret;
 151
 152         WARN_ON(i915_verify_lists(dev));
 153         return 0;
 154 }
 155
 156 static inline bool
 157 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 158 {
 159         return i915_gem_obj_bound_any(obj) && !obj->active;
 160 }
 161
 162 int
 163 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 164                             struct drm_file *file)
 165 {
 166         struct drm_i915_private *dev_priv = dev->dev_private;
 167         struct drm_i915_gem_get_aperture *args = data;
 168         struct drm_i915_gem_object *obj;
 169         size_t pinned;
 170
 171         pinned = 0;
 172         mutex_lock(&dev->struct_mutex);
 173         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 174                 if (i915_gem_obj_is_pinned(obj))
 175                         pinned += i915_gem_obj_ggtt_size(obj);
 176         mutex_unlock(&dev->struct_mutex);
 177
 178         args->aper_size = dev_priv->gtt.base.total;
 179         args->aper_available_size = args->aper_size - pinned;
 180
 181         return 0;
 182 }
 183
 184 static int
 185 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 186 {
 187         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 188         char *vaddr = obj->phys_handle->vaddr;
 189         struct sg_table *st;
 190         struct scatterlist *sg;
 191         int i;
 192
 193         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
 194                 return -EINVAL;
 195
 196         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 197                 struct page *page;
 198                 char *src;
 199
 200                 page = shmem_read_mapping_page(mapping, i);
 201                 if (IS_ERR(page))
 202                         return PTR_ERR(page);
 203
 204                 src = kmap_atomic(page);
 205                 memcpy(vaddr, src, PAGE_SIZE);
 206                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 207                 kunmap_atomic(src);
 208
 209                 page_cache_release(page);
 210                 vaddr += PAGE_SIZE;
 211         }
 212
 213         i915_gem_chipset_flush(obj->base.dev);
 214
 215         st = kmalloc(sizeof(*st), GFP_KERNEL);
 216         if (st == NULL)
 217                 return -ENOMEM;
 218
 219         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 220                 kfree(st);
 221                 return -ENOMEM;
 222         }
 223
 224         sg = st->sgl;
 225         sg->offset = 0;
 226         sg->length = obj->base.size;
 227
 228         sg_dma_address(sg) = obj->phys_handle->busaddr;
 229         sg_dma_len(sg) = obj->base.size;
 230
 231         obj->pages = st;
 232         obj->has_dma_mapping = true;
 233         return 0;
 234 }
 235
 236 static void
 237 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
 238 {
 239         int ret;
 240
 241         BUG_ON(obj->madv == __I915_MADV_PURGED);
 242
 243         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 244         if (ret) {
 245                 /* In the event of a disaster, abandon all caches and
 246                  * hope for the best.
 247                  */
 248                 WARN_ON(ret != -EIO);
 249                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 250         }
 251
 252         if (obj->madv == I915_MADV_DONTNEED)
 253                 obj->dirty = 0;
 254
 255         if (obj->dirty) {
 256                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 257                 char *vaddr = obj->phys_handle->vaddr;
 258                 int i;
 259
 260                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 261                         struct page *page;
 262                         char *dst;
 263
 264                         page = shmem_read_mapping_page(mapping, i);
 265                         if (IS_ERR(page))
 266                                 continue;
 267
 268                         dst = kmap_atomic(page);
 269                         drm_clflush_virt_range(vaddr, PAGE_SIZE);
 270                         memcpy(dst, vaddr, PAGE_SIZE);
 271                         kunmap_atomic(dst);
 272
 273                         set_page_dirty(page);
 274                         if (obj->madv == I915_MADV_WILLNEED)
 275                                 mark_page_accessed(page);
 276                         page_cache_release(page);
 277                         vaddr += PAGE_SIZE;
 278                 }
 279                 obj->dirty = 0;
 280         }
 281
 282         sg_free_table(obj->pages);
 283         kfree(obj->pages);
 284
 285         obj->has_dma_mapping = false;
 286 }
 287
 288 static void
 289 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
 290 {
 291         drm_pci_free(obj->base.dev, obj->phys_handle);
 292 }
 293
 294 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 295         .get_pages = i915_gem_object_get_pages_phys,
 296         .put_pages = i915_gem_object_put_pages_phys,
 297         .release = i915_gem_object_release_phys,
 298 };
 299
 300 static int
 301 drop_pages(struct drm_i915_gem_object *obj)
 302 {
 303         struct i915_vma *vma, *next;
 304         int ret;
 305
 306         drm_gem_object_reference(&obj->base);
 307         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
 308                 if (i915_vma_unbind(vma))
 309                         break;
 310
 311         ret = i915_gem_object_put_pages(obj);
 312         drm_gem_object_unreference(&obj->base);
 313
 314         return ret;
 315 }
 316
 317 int
 318 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 319                             int align)
 320 {
 321         drm_dma_handle_t *phys;
 322         int ret;
 323
 324         if (obj->phys_handle) {
 325                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 326                         return -EBUSY;
 327
 328                 return 0;
 329         }
 330
 331         if (obj->madv != I915_MADV_WILLNEED)
 332                 return -EFAULT;
 333
 334         if (obj->base.filp == NULL)
 335                 return -EINVAL;
 336
 337         ret = drop_pages(obj);
 338         if (ret)
 339                 return ret;
 340
 341         /* create a new object */
 342         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 343         if (!phys)
 344                 return -ENOMEM;
 345
 346         obj->phys_handle = phys;
 347         obj->ops = &i915_gem_phys_ops;
 348
 349         return i915_gem_object_get_pages(obj);
 350 }
 351
 352 static int
 353 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 354                      struct drm_i915_gem_pwrite *args,
 355                      struct drm_file *file_priv)
 356 {
 357         struct drm_device *dev = obj->base.dev;
 358         void *vaddr = obj->phys_handle->vaddr + args->offset;
 359         char __user *user_data = to_user_ptr(args->data_ptr);
 360         int ret;
 361
 362         /* We manually control the domain here and pretend that it
 363          * remains coherent i.e. in the GTT domain, like shmem_pwrite.
 364          */
 365         ret = i915_gem_object_wait_rendering(obj, false);
 366         if (ret)
 367                 return ret;
 368
 369         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 370                 unsigned long unwritten;
 371
 372                 /* The physical object once assigned is fixed for the lifetime
 373                  * of the obj, so we can safely drop the lock and continue
 374                  * to access vaddr.
 375                  */
 376                 mutex_unlock(&dev->struct_mutex);
 377                 unwritten = copy_from_user(vaddr, user_data, args->size);
 378                 mutex_lock(&dev->struct_mutex);
 379                 if (unwritten)
 380                         return -EFAULT;
 381         }
 382
 383         drm_clflush_virt_range(vaddr, args->size);
 384         i915_gem_chipset_flush(dev);
 385         return 0;
 386 }
 387
 388 void *i915_gem_object_alloc(struct drm_device *dev)
 389 {
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 392 }
 393
 394 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 395 {
 396         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 397         kmem_cache_free(dev_priv->slab, obj);
 398 }
 399
 400 static int
 401 i915_gem_create(struct drm_file *file,
 402                 struct drm_device *dev,
 403                 uint64_t size,
 404                 bool dumb,
 405                 uint32_t *handle_p)
 406 {
 407         struct drm_i915_gem_object *obj;
 408         int ret;
 409         u32 handle;
 410
 411         size = roundup(size, PAGE_SIZE);
 412         if (size == 0)
 413                 return -EINVAL;
 414
 415         /* Allocate the new object */
 416         obj = i915_gem_alloc_object(dev, size);
 417         if (obj == NULL)
 418                 return -ENOMEM;
 419
 420         obj->base.dumb = dumb;
 421         ret = drm_gem_handle_create(file, &obj->base, &handle);
 422         /* drop reference from allocate - handle holds it now */
 423         drm_gem_object_unreference_unlocked(&obj->base);
 424         if (ret)
 425                 return ret;
 426
 427         *handle_p = handle;
 428         return 0;
 429 }
 430
 431 int
 432 i915_gem_dumb_create(struct drm_file *file,
 433                      struct drm_device *dev,
 434                      struct drm_mode_create_dumb *args)
 435 {
 436         /* have to work out size/pitch and return them */
 437         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 438         args->size = args->pitch * args->height;
 439         return i915_gem_create(file, dev,
 440                                args->size, true, &args->handle);
 441 }
 442
 443 /**
 444  * Creates a new mm object and returns a handle to it.
 445  */
 446 int
 447 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 448                       struct drm_file *file)
 449 {
 450         struct drm_i915_gem_create *args = data;
 451
 452         return i915_gem_create(file, dev,
 453                                args->size, false, &args->handle);
 454 }
 455
 456 static inline int
 457 __copy_to_user_swizzled(char __user *cpu_vaddr,
 458                         const char *gpu_vaddr, int gpu_offset,
 459                         int length)
 460 {
 461         int ret, cpu_offset = 0;
 462
 463         while (length > 0) {
 464                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 465                 int this_length = min(cacheline_end - gpu_offset, length);
 466                 int swizzled_gpu_offset = gpu_offset ^ 64;
 467
 468                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 469                                      gpu_vaddr + swizzled_gpu_offset,
 470                                      this_length);
 471                 if (ret)
 472                         return ret + length;
 473
 474                 cpu_offset += this_length;
 475                 gpu_offset += this_length;
 476                 length -= this_length;
 477         }
 478
 479         return 0;
 480 }
 481
 482 static inline int
 483 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 484                           const char __user *cpu_vaddr,
 485                           int length)
 486 {
 487         int ret, cpu_offset = 0;
 488
 489         while (length > 0) {
 490                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 491                 int this_length = min(cacheline_end - gpu_offset, length);
 492                 int swizzled_gpu_offset = gpu_offset ^ 64;
 493
 494                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 495                                        cpu_vaddr + cpu_offset,
 496                                        this_length);
 497                 if (ret)
 498                         return ret + length;
 499
 500                 cpu_offset += this_length;
 501                 gpu_offset += this_length;
 502                 length -= this_length;
 503         }
 504
 505         return 0;
 506 }
 507
 508 /*
 509  * Pins the specified object's pages and synchronizes the object with
 510  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 511  * flush the object from the CPU cache.
 512  */
 513 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 514                                     int *needs_clflush)
 515 {
 516         int ret;
 517
 518         *needs_clflush = 0;
 519
 520         if (!obj->base.filp)
 521                 return -EINVAL;
 522
 523         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 524                 /* If we're not in the cpu read domain, set ourself into the gtt
 525                  * read domain and manually flush cachelines (if required). This
 526                  * optimizes for the case when the gpu will dirty the data
 527                  * anyway again before the next pread happens. */
 528                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 529                                                         obj->cache_level);
 530                 ret = i915_gem_object_wait_rendering(obj, true);
 531                 if (ret)
 532                         return ret;
 533
 534                 i915_gem_object_retire(obj);
 535         }
 536
 537         ret = i915_gem_object_get_pages(obj);
 538         if (ret)
 539                 return ret;
 540
 541         i915_gem_object_pin_pages(obj);
 542
 543         return ret;
 544 }
 545
 546 /* Per-page copy function for the shmem pread fastpath.
 547  * Flushes invalid cachelines before reading the target if
 548  * needs_clflush is set. */
 549 static int
 550 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 551                  char __user *user_data,
 552                  bool page_do_bit17_swizzling, bool needs_clflush)
 553 {
 554         char *vaddr;
 555         int ret;
 556
 557         if (unlikely(page_do_bit17_swizzling))
 558                 return -EINVAL;
 559
 560         vaddr = kmap_atomic(page);
 561         if (needs_clflush)
 562                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 563                                        page_length);
 564         ret = __copy_to_user_inatomic(user_data,
 565                                       vaddr + shmem_page_offset,
 566                                       page_length);
 567         kunmap_atomic(vaddr);
 568
 569         return ret ? -EFAULT : 0;
 570 }
 571
 572 static void
 573 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 574                              bool swizzled)
 575 {
 576         if (unlikely(swizzled)) {
 577                 unsigned long start = (unsigned long) addr;
 578                 unsigned long end = (unsigned long) addr + length;
 579
 580                 /* For swizzling simply ensure that we always flush both
 581                  * channels. Lame, but simple and it works. Swizzled
 582                  * pwrite/pread is far from a hotpath - current userspace
 583                  * doesn't use it at all. */
 584                 start = round_down(start, 128);
 585                 end = round_up(end, 128);
 586
 587                 drm_clflush_virt_range((void *)start, end - start);
 588         } else {
 589                 drm_clflush_virt_range(addr, length);
 590         }
 591
 592 }
 593
 594 /* Only difference to the fast-path function is that this can handle bit17
 595  * and uses non-atomic copy and kmap functions. */
 596 static int
 597 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 598                  char __user *user_data,
 599                  bool page_do_bit17_swizzling, bool needs_clflush)
 600 {
 601         char *vaddr;
 602         int ret;
 603
 604         vaddr = kmap(page);
 605         if (needs_clflush)
 606                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 607                                              page_length,
 608                                              page_do_bit17_swizzling);
 609
 610         if (page_do_bit17_swizzling)
 611                 ret = __copy_to_user_swizzled(user_data,
 612                                               vaddr, shmem_page_offset,
 613                                               page_length);
 614         else
 615                 ret = __copy_to_user(user_data,
 616                                      vaddr + shmem_page_offset,
 617                                      page_length);
 618         kunmap(page);
 619
 620         return ret ? - EFAULT : 0;
 621 }
 622
 623 static int
 624 i915_gem_shmem_pread(struct drm_device *dev,
 625                      struct drm_i915_gem_object *obj,
 626                      struct drm_i915_gem_pread *args,
 627                      struct drm_file *file)
 628 {
 629         char __user *user_data;
 630         ssize_t remain;
 631         loff_t offset;
 632         int shmem_page_offset, page_length, ret = 0;
 633         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 634         int prefaulted = 0;
 635         int needs_clflush = 0;
 636         struct sg_page_iter sg_iter;
 637
 638         user_data = to_user_ptr(args->data_ptr);
 639         remain = args->size;
 640
 641         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 642
 643         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 644         if (ret)
 645                 return ret;
 646
 647         offset = args->offset;
 648
 649         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 650                          offset >> PAGE_SHIFT) {
 651                 struct page *page = sg_page_iter_page(&sg_iter);
 652
 653                 if (remain <= 0)
 654                         break;
 655
 656                 /* Operation in this page
 657                  *
 658                  * shmem_page_offset = offset within page in shmem file
 659                  * page_length = bytes to copy for this page
 660                  */
 661                 shmem_page_offset = offset_in_page(offset);
 662                 page_length = remain;
 663                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 664                         page_length = PAGE_SIZE - shmem_page_offset;
 665
 666                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 667                         (page_to_phys(page) & (1 << 17)) != 0;
 668
 669                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 670                                        user_data, page_do_bit17_swizzling,
 671                                        needs_clflush);
 672                 if (ret == 0)
 673                         goto next_page;
 674
 675                 mutex_unlock(&dev->struct_mutex);
 676
 677                 if (likely(!i915.prefault_disable) && !prefaulted) {
 678                         ret = fault_in_multipages_writeable(user_data, remain);
 679                         /* Userspace is tricking us, but we've already clobbered
 680                          * its pages with the prefault and promised to write the
 681                          * data up to the first fault. Hence ignore any errors
 682                          * and just continue. */
 683                         (void)ret;
 684                         prefaulted = 1;
 685                 }
 686
 687                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 688                                        user_data, page_do_bit17_swizzling,
 689                                        needs_clflush);
 690
 691                 mutex_lock(&dev->struct_mutex);
 692
 693                 if (ret)
 694                         goto out;
 695
 696 next_page:
 697                 remain -= page_length;
 698                 user_data += page_length;
 699                 offset += page_length;
 700         }
 701
 702 out:
 703         i915_gem_object_unpin_pages(obj);
 704
 705         return ret;
 706 }
 707
 708 /**
 709  * Reads data from the object referenced by handle.
 710  *
 711  * On error, the contents of *data are undefined.
 712  */
 713 int
 714 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 715                      struct drm_file *file)
 716 {
 717         struct drm_i915_gem_pread *args = data;
 718         struct drm_i915_gem_object *obj;
 719         int ret = 0;
 720
 721         if (args->size == 0)
 722                 return 0;
 723
 724         if (!access_ok(VERIFY_WRITE,
 725                        to_user_ptr(args->data_ptr),
 726                        args->size))
 727                 return -EFAULT;
 728
 729         ret = i915_mutex_lock_interruptible(dev);
 730         if (ret)
 731                 return ret;
 732
 733         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 734         if (&obj->base == NULL) {
 735                 ret = -ENOENT;
 736                 goto unlock;
 737         }
 738
 739         /* Bounds check source.  */
 740         if (args->offset > obj->base.size ||
 741             args->size > obj->base.size - args->offset) {
 742                 ret = -EINVAL;
 743                 goto out;
 744         }
 745
 746         /* prime objects have no backing filp to GEM pread/pwrite
 747          * pages from.
 748          */
 749         if (!obj->base.filp) {
 750                 ret = -EINVAL;
 751                 goto out;
 752         }
 753
 754         trace_i915_gem_object_pread(obj, args->offset, args->size);
 755
 756         ret = i915_gem_shmem_pread(dev, obj, args, file);
 757
 758 out:
 759         drm_gem_object_unreference(&obj->base);
 760 unlock:
 761         mutex_unlock(&dev->struct_mutex);
 762         return ret;
 763 }
 764
 765 /* This is the fast write path which cannot handle
 766  * page faults in the source data
 767  */
 768
 769 static inline int
 770 fast_user_write(struct io_mapping *mapping,
 771                 loff_t page_base, int page_offset,
 772                 char __user *user_data,
 773                 int length)
 774 {
 775         void __iomem *vaddr_atomic;
 776         void *vaddr;
 777         unsigned long unwritten;
 778
 779         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 780         /* We can use the cpu mem copy function because this is X86. */
 781         vaddr = (void __force*)vaddr_atomic + page_offset;
 782         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 783                                                       user_data, length);
 784         io_mapping_unmap_atomic(vaddr_atomic);
 785         return unwritten;
 786 }
 787
 788 /**
 789  * This is the fast pwrite path, where we copy the data directly from the
 790  * user into the GTT, uncached.
 791  */
 792 static int
 793 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 794                          struct drm_i915_gem_object *obj,
 795                          struct drm_i915_gem_pwrite *args,
 796                          struct drm_file *file)
 797 {
 798         struct drm_i915_private *dev_priv = dev->dev_private;
 799         ssize_t remain;
 800         loff_t offset, page_base;
 801         char __user *user_data;
 802         int page_offset, page_length, ret;
 803
 804         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 805         if (ret)
 806                 goto out;
 807
 808         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 809         if (ret)
 810                 goto out_unpin;
 811
 812         ret = i915_gem_object_put_fence(obj);
 813         if (ret)
 814                 goto out_unpin;
 815
 816         user_data = to_user_ptr(args->data_ptr);
 817         remain = args->size;
 818
 819         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 820
 821         while (remain > 0) {
 822                 /* Operation in this page
 823                  *
 824                  * page_base = page offset within aperture
 825                  * page_offset = offset within page
 826                  * page_length = bytes to copy for this page
 827                  */
 828                 page_base = offset & PAGE_MASK;
 829                 page_offset = offset_in_page(offset);
 830                 page_length = remain;
 831                 if ((page_offset + remain) > PAGE_SIZE)
 832                         page_length = PAGE_SIZE - page_offset;
 833
 834                 /* If we get a fault while copying data, then (presumably) our
 835                  * source page isn't available.  Return the error and we'll
 836                  * retry in the slow path.
 837                  */
 838                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 839                                     page_offset, user_data, page_length)) {
 840                         ret = -EFAULT;
 841                         goto out_unpin;
 842                 }
 843
 844                 remain -= page_length;
 845                 user_data += page_length;
 846                 offset += page_length;
 847         }
 848
 849 out_unpin:
 850         i915_gem_object_ggtt_unpin(obj);
 851 out:
 852         return ret;
 853 }
 854
 855 /* Per-page copy function for the shmem pwrite fastpath.
 856  * Flushes invalid cachelines before writing to the target if
 857  * needs_clflush_before is set and flushes out any written cachelines after
 858  * writing if needs_clflush is set. */
 859 static int
 860 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 861                   char __user *user_data,
 862                   bool page_do_bit17_swizzling,
 863                   bool needs_clflush_before,
 864                   bool needs_clflush_after)
 865 {
 866         char *vaddr;
 867         int ret;
 868
 869         if (unlikely(page_do_bit17_swizzling))
 870                 return -EINVAL;
 871
 872         vaddr = kmap_atomic(page);
 873         if (needs_clflush_before)
 874                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 875                                        page_length);
 876         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 877                                         user_data, page_length);
 878         if (needs_clflush_after)
 879                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 880                                        page_length);
 881         kunmap_atomic(vaddr);
 882
 883         return ret ? -EFAULT : 0;
 884 }
 885
 886 /* Only difference to the fast-path function is that this can handle bit17
 887  * and uses non-atomic copy and kmap functions. */
 888 static int
 889 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 890                   char __user *user_data,
 891                   bool page_do_bit17_swizzling,
 892                   bool needs_clflush_before,
 893                   bool needs_clflush_after)
 894 {
 895         char *vaddr;
 896         int ret;
 897
 898         vaddr = kmap(page);
 899         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 900                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 901                                              page_length,
 902                                              page_do_bit17_swizzling);
 903         if (page_do_bit17_swizzling)
 904                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 905                                                 user_data,
 906                                                 page_length);
 907         else
 908                 ret = __copy_from_user(vaddr + shmem_page_offset,
 909                                        user_data,
 910                                        page_length);
 911         if (needs_clflush_after)
 912                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 913                                              page_length,
 914                                              page_do_bit17_swizzling);
 915         kunmap(page);
 916
 917         return ret ? -EFAULT : 0;
 918 }
 919
 920 static int
 921 i915_gem_shmem_pwrite(struct drm_device *dev,
 922                       struct drm_i915_gem_object *obj,
 923                       struct drm_i915_gem_pwrite *args,
 924                       struct drm_file *file)
 925 {
 926         ssize_t remain;
 927         loff_t offset;
 928         char __user *user_data;
 929         int shmem_page_offset, page_length, ret = 0;
 930         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 931         int hit_slowpath = 0;
 932         int needs_clflush_after = 0;
 933         int needs_clflush_before = 0;
 934         struct sg_page_iter sg_iter;
 935
 936         user_data = to_user_ptr(args->data_ptr);
 937         remain = args->size;
 938
 939         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 940
 941         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 942                 /* If we're not in the cpu write domain, set ourself into the gtt
 943                  * write domain and manually flush cachelines (if required). This
 944                  * optimizes for the case when the gpu will use the data
 945                  * right away and we therefore have to clflush anyway. */
 946                 needs_clflush_after = cpu_write_needs_clflush(obj);
 947                 ret = i915_gem_object_wait_rendering(obj, false);
 948                 if (ret)
 949                         return ret;
 950
 951                 i915_gem_object_retire(obj);
 952         }
 953         /* Same trick applies to invalidate partially written cachelines read
 954          * before writing. */
 955         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 956                 needs_clflush_before =
 957                         !cpu_cache_is_coherent(dev, obj->cache_level);
 958
 959         ret = i915_gem_object_get_pages(obj);
 960         if (ret)
 961                 return ret;
 962
 963         i915_gem_object_pin_pages(obj);
 964
 965         offset = args->offset;
 966         obj->dirty = 1;
 967
 968         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 969                          offset >> PAGE_SHIFT) {
 970                 struct page *page = sg_page_iter_page(&sg_iter);
 971                 int partial_cacheline_write;
 972
 973                 if (remain <= 0)
 974                         break;
 975
 976                 /* Operation in this page
 977                  *
 978                  * shmem_page_offset = offset within page in shmem file
 979                  * page_length = bytes to copy for this page
 980                  */
 981                 shmem_page_offset = offset_in_page(offset);
 982
 983                 page_length = remain;
 984                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 985                         page_length = PAGE_SIZE - shmem_page_offset;
 986
 987                 /* If we don't overwrite a cacheline completely we need to be
 988                  * careful to have up-to-date data by first clflushing. Don't
 989                  * overcomplicate things and flush the entire patch. */
 990                 partial_cacheline_write = needs_clflush_before &&
 991                         ((shmem_page_offset | page_length)
 992                                 & (boot_cpu_data.x86_clflush_size - 1));
 993
 994                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 995                         (page_to_phys(page) & (1 << 17)) != 0;
 996
 997                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 998                                         user_data, page_do_bit17_swizzling,
 999                                         partial_cacheline_write,
1000                                         needs_clflush_after);
1001                 if (ret == 0)
1002                         goto next_page;
1003
1004                 hit_slowpath = 1;
1005                 mutex_unlock(&dev->struct_mutex);
1006                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1007                                         user_data, page_do_bit17_swizzling,
1008                                         partial_cacheline_write,
1009                                         needs_clflush_after);
1010
1011                 mutex_lock(&dev->struct_mutex);
1012
1013                 if (ret)
1014                         goto out;
1015
1016 next_page:
1017                 remain -= page_length;
1018                 user_data += page_length;
1019                 offset += page_length;
1020         }
1021
1022 out:
1023         i915_gem_object_unpin_pages(obj);
1024
1025         if (hit_slowpath) {
1026                 /*
1027                  * Fixup: Flush cpu caches in case we didn't flush the dirty
1028                  * cachelines in-line while writing and the object moved
1029                  * out of the cpu write domain while we've dropped the lock.
1030                  */
1031                 if (!needs_clflush_after &&
1032                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1033                         if (i915_gem_clflush_object(obj, obj->pin_display))
1034                                 i915_gem_chipset_flush(dev);
1035                 }
1036         }
1037
1038         if (needs_clflush_after)
1039                 i915_gem_chipset_flush(dev);
1040
1041         return ret;
1042 }
1043
1044 /**
1045  * Writes data to the object referenced by handle.
1046  *
1047  * On error, the contents of the buffer that were to be modified are undefined.
1048  */
1049 int
1050 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1051                       struct drm_file *file)
1052 {
1053         struct drm_i915_private *dev_priv = dev->dev_private;
1054         struct drm_i915_gem_pwrite *args = data;
1055         struct drm_i915_gem_object *obj;
1056         int ret;
1057
1058         if (args->size == 0)
1059                 return 0;
1060
1061         if (!access_ok(VERIFY_READ,
1062                        to_user_ptr(args->data_ptr),
1063                        args->size))
1064                 return -EFAULT;
1065
1066         if (likely(!i915.prefault_disable)) {
1067                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1068                                                    args->size);
1069                 if (ret)
1070                         return -EFAULT;
1071         }
1072
1073         intel_runtime_pm_get(dev_priv);
1074
1075         ret = i915_mutex_lock_interruptible(dev);
1076         if (ret)
1077                 goto put_rpm;
1078
1079         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1080         if (&obj->base == NULL) {
1081                 ret = -ENOENT;
1082                 goto unlock;
1083         }
1084
1085         /* Bounds check destination. */
1086         if (args->offset > obj->base.size ||
1087             args->size > obj->base.size - args->offset) {
1088                 ret = -EINVAL;
1089                 goto out;
1090         }
1091
1092         /* prime objects have no backing filp to GEM pread/pwrite
1093          * pages from.
1094          */
1095         if (!obj->base.filp) {
1096                 ret = -EINVAL;
1097                 goto out;
1098         }
1099
1100         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1101
1102         ret = -EFAULT;
1103         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1104          * it would end up going through the fenced access, and we'll get
1105          * different detiling behavior between reading and writing.
1106          * pread/pwrite currently are reading and writing from the CPU
1107          * perspective, requiring manual detiling by the client.
1108          */
1109         if (obj->tiling_mode == I915_TILING_NONE &&
1110             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1111             cpu_write_needs_clflush(obj)) {
1112                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1113                 /* Note that the gtt paths might fail with non-page-backed user
1114                  * pointers (e.g. gtt mappings when moving data between
1115                  * textures). Fallback to the shmem path in that case. */
1116         }
1117
1118         if (ret == -EFAULT || ret == -ENOSPC) {
1119                 if (obj->phys_handle)
1120                         ret = i915_gem_phys_pwrite(obj, args, file);
1121                 else
1122                         ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1123         }
1124
1125 out:
1126         drm_gem_object_unreference(&obj->base);
1127 unlock:
1128         mutex_unlock(&dev->struct_mutex);
1129 put_rpm:
1130         intel_runtime_pm_put(dev_priv);
1131
1132         return ret;
1133 }
1134
1135 int
1136 i915_gem_check_wedge(struct i915_gpu_error *error,
1137                      bool interruptible)
1138 {
1139         if (i915_reset_in_progress(error)) {
1140                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1141                  * -EIO unconditionally for these. */
1142                 if (!interruptible)
1143                         return -EIO;
1144
1145                 /* Recovery complete, but the reset failed ... */
1146                 if (i915_terminally_wedged(error))
1147                         return -EIO;
1148
1149                 /*
1150                  * Check if GPU Reset is in progress - we need intel_ring_begin
1151                  * to work properly to reinit the hw state while the gpu is
1152                  * still marked as reset-in-progress. Handle this with a flag.
1153                  */
1154                 if (!error->reload_in_reset)
1155                         return -EAGAIN;
1156         }
1157
1158         return 0;
1159 }
1160
1161 /*
1162  * Compare seqno against outstanding lazy request. Emit a request if they are
1163  * equal.
1164  */
1165 int
1166 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1167 {
1168         int ret;
1169
1170         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1171
1172         ret = 0;
1173         if (seqno == ring->outstanding_lazy_seqno)
1174                 ret = i915_add_request(ring, NULL);
1175
1176         return ret;
1177 }
1178
1179 static void fake_irq(unsigned long data)
1180 {
1181         wake_up_process((struct task_struct *)data);
1182 }
1183
1184 static bool missed_irq(struct drm_i915_private *dev_priv,
1185                        struct intel_engine_cs *ring)
1186 {
1187         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1188 }
1189
1190 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1191 {
1192         if (file_priv == NULL)
1193                 return true;
1194
1195         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1196 }
1197
1198 /**
1199  * __i915_wait_seqno - wait until execution of seqno has finished
1200  * @ring: the ring expected to report seqno
1201  * @seqno: duh!
1202  * @reset_counter: reset sequence associated with the given seqno
1203  * @interruptible: do an interruptible wait (normally yes)
1204  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1205  *
1206  * Note: It is of utmost importance that the passed in seqno and reset_counter
1207  * values have been read by the caller in an smp safe manner. Where read-side
1208  * locks are involved, it is sufficient to read the reset_counter before
1209  * unlocking the lock that protects the seqno. For lockless tricks, the
1210  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1211  * inserted.
1212  *
1213  * Returns 0 if the seqno was found within the alloted time. Else returns the
1214  * errno with remaining time filled in timeout argument.
1215  */
1216 int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1217                         unsigned reset_counter,
1218                         bool interruptible,
1219                         s64 *timeout,
1220                         struct drm_i915_file_private *file_priv)
1221 {
1222         struct drm_device *dev = ring->dev;
1223         struct drm_i915_private *dev_priv = dev->dev_private;
1224         const bool irq_test_in_progress =
1225                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1226         DEFINE_WAIT(wait);
1227         unsigned long timeout_expire;
1228         s64 before, now;
1229         int ret;
1230
1231         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1232
1233         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1234                 return 0;
1235
1236         timeout_expire = timeout ?
1237                 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1238
1239         if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1240                 gen6_rps_boost(dev_priv);
1241                 if (file_priv)
1242                         mod_delayed_work(dev_priv->wq,
1243                                          &file_priv->mm.idle_work,
1244                                          msecs_to_jiffies(100));
1245         }
1246
1247         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1248                 return -ENODEV;
1249
1250         /* Record current time in case interrupted by signal, or wedged */
1251         trace_i915_gem_request_wait_begin(ring, seqno);
1252         before = ktime_get_raw_ns();
1253         for (;;) {
1254                 struct timer_list timer;
1255
1256                 prepare_to_wait(&ring->irq_queue, &wait,
1257                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1258
1259                 /* We need to check whether any gpu reset happened in between
1260                  * the caller grabbing the seqno and now ... */
1261                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1262                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1263                          * is truely gone. */
1264                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1265                         if (ret == 0)
1266                                 ret = -EAGAIN;
1267                         break;
1268                 }
1269
1270                 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1271                         ret = 0;
1272                         break;
1273                 }
1274
1275                 if (interruptible && signal_pending(current)) {
1276                         ret = -ERESTARTSYS;
1277                         break;
1278                 }
1279
1280                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1281                         ret = -ETIME;
1282                         break;
1283                 }
1284
1285                 timer.function = NULL;
1286                 if (timeout || missed_irq(dev_priv, ring)) {
1287                         unsigned long expire;
1288
1289                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1290                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1291                         mod_timer(&timer, expire);
1292                 }
1293
1294                 io_schedule();
1295
1296                 if (timer.function) {
1297                         del_singleshot_timer_sync(&timer);
1298                         destroy_timer_on_stack(&timer);
1299                 }
1300         }
1301         now = ktime_get_raw_ns();
1302         trace_i915_gem_request_wait_end(ring, seqno);
1303
1304         if (!irq_test_in_progress)
1305                 ring->irq_put(ring);
1306
1307         finish_wait(&ring->irq_queue, &wait);
1308
1309         if (timeout) {
1310                 s64 tres = *timeout - (now - before);
1311
1312                 *timeout = tres < 0 ? 0 : tres;
1313
1314                 /*
1315                  * Apparently ktime isn't accurate enough and occasionally has a
1316                  * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1317                  * things up to make the test happy. We allow up to 1 jiffy.
1318                  *
1319                  * This is a regrssion from the timespec->ktime conversion.
1320                  */
1321                 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1322                         *timeout = 0;
1323         }
1324
1325         return ret;
1326 }
1327
1328 /**
1329  * Waits for a sequence number to be signaled, and cleans up the
1330  * request and object lists appropriately for that event.
1331  */
1332 int
1333 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1334 {
1335         struct drm_device *dev = ring->dev;
1336         struct drm_i915_private *dev_priv = dev->dev_private;
1337         bool interruptible = dev_priv->mm.interruptible;
1338         unsigned reset_counter;
1339         int ret;
1340
1341         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1342         BUG_ON(seqno == 0);
1343
1344         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1345         if (ret)
1346                 return ret;
1347
1348         ret = i915_gem_check_olr(ring, seqno);
1349         if (ret)
1350                 return ret;
1351
1352         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1353         return __i915_wait_seqno(ring, seqno, reset_counter, interruptible,
1354                                  NULL, NULL);
1355 }
1356
1357 static int
1358 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1359 {
1360         if (!obj->active)
1361                 return 0;
1362
1363         /* Manually manage the write flush as we may have not yet
1364          * retired the buffer.
1365          *
1366          * Note that the last_write_seqno is always the earlier of
1367          * the two (read/write) seqno, so if we haved successfully waited,
1368          * we know we have passed the last write.
1369          */
1370         obj->last_write_seqno = 0;
1371
1372         return 0;
1373 }
1374
1375 /**
1376  * Ensures that all rendering to the object has completed and the object is
1377  * safe to unbind from the GTT or access from the CPU.
1378  */
1379 static __must_check int
1380 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1381                                bool readonly)
1382 {
1383         struct intel_engine_cs *ring = obj->ring;
1384         u32 seqno;
1385         int ret;
1386
1387         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1388         if (seqno == 0)
1389                 return 0;
1390
1391         ret = i915_wait_seqno(ring, seqno);
1392         if (ret)
1393                 return ret;
1394
1395         return i915_gem_object_wait_rendering__tail(obj);
1396 }
1397
1398 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1399  * as the object state may change during this call.
1400  */
1401 static __must_check int
1402 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1403                                             struct drm_i915_file_private *file_priv,
1404                                             bool readonly)
1405 {
1406         struct drm_device *dev = obj->base.dev;
1407         struct drm_i915_private *dev_priv = dev->dev_private;
1408         struct intel_engine_cs *ring = obj->ring;
1409         unsigned reset_counter;
1410         u32 seqno;
1411         int ret;
1412
1413         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1414         BUG_ON(!dev_priv->mm.interruptible);
1415
1416         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1417         if (seqno == 0)
1418                 return 0;
1419
1420         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1421         if (ret)
1422                 return ret;
1423
1424         ret = i915_gem_check_olr(ring, seqno);
1425         if (ret)
1426                 return ret;
1427
1428         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1429         mutex_unlock(&dev->struct_mutex);
1430         ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL,
1431                                 file_priv);
1432         mutex_lock(&dev->struct_mutex);
1433         if (ret)
1434                 return ret;
1435
1436         return i915_gem_object_wait_rendering__tail(obj);
1437 }
1438
1439 /**
1440  * Called when user space prepares to use an object with the CPU, either
1441  * through the mmap ioctl's mapping or a GTT mapping.
1442  */
1443 int
1444 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1445                           struct drm_file *file)
1446 {
1447         struct drm_i915_gem_set_domain *args = data;
1448         struct drm_i915_gem_object *obj;
1449         uint32_t read_domains = args->read_domains;
1450         uint32_t write_domain = args->write_domain;
1451         int ret;
1452
1453         /* Only handle setting domains to types used by the CPU. */
1454         if (write_domain & I915_GEM_GPU_DOMAINS)
1455                 return -EINVAL;
1456
1457         if (read_domains & I915_GEM_GPU_DOMAINS)
1458                 return -EINVAL;
1459
1460         /* Having something in the write domain implies it's in the read
1461          * domain, and only that read domain.  Enforce that in the request.
1462          */
1463         if (write_domain != 0 && read_domains != write_domain)
1464                 return -EINVAL;
1465
1466         ret = i915_mutex_lock_interruptible(dev);
1467         if (ret)
1468                 return ret;
1469
1470         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1471         if (&obj->base == NULL) {
1472                 ret = -ENOENT;
1473                 goto unlock;
1474         }
1475
1476         /* Try to flush the object off the GPU without holding the lock.
1477          * We will repeat the flush holding the lock in the normal manner
1478          * to catch cases where we are gazumped.
1479          */
1480         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1481                                                           file->driver_priv,
1482                                                           !write_domain);
1483         if (ret)
1484                 goto unref;
1485
1486         if (read_domains & I915_GEM_DOMAIN_GTT) {
1487                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1488
1489                 /* Silently promote "you're not bound, there was nothing to do"
1490                  * to success, since the client was just asking us to
1491                  * make sure everything was done.
1492                  */
1493                 if (ret == -EINVAL)
1494                         ret = 0;
1495         } else {
1496                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1497         }
1498
1499 unref:
1500         drm_gem_object_unreference(&obj->base);
1501 unlock:
1502         mutex_unlock(&dev->struct_mutex);
1503         return ret;
1504 }
1505
1506 /**
1507  * Called when user space has done writes to this buffer
1508  */
1509 int
1510 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1511                          struct drm_file *file)
1512 {
1513         struct drm_i915_gem_sw_finish *args = data;
1514         struct drm_i915_gem_object *obj;
1515         int ret = 0;
1516
1517         ret = i915_mutex_lock_interruptible(dev);
1518         if (ret)
1519                 return ret;
1520
1521         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1522         if (&obj->base == NULL) {
1523                 ret = -ENOENT;
1524                 goto unlock;
1525         }
1526
1527         /* Pinned buffers may be scanout, so flush the cache */
1528         if (obj->pin_display)
1529                 i915_gem_object_flush_cpu_write_domain(obj, true);
1530
1531         drm_gem_object_unreference(&obj->base);
1532 unlock:
1533         mutex_unlock(&dev->struct_mutex);
1534         return ret;
1535 }
1536
1537 /**
1538  * Maps the contents of an object, returning the address it is mapped
1539  * into.
1540  *
1541  * While the mapping holds a reference on the contents of the object, it doesn't
1542  * imply a ref on the object itself.
1543  *
1544  * IMPORTANT:
1545  *
1546  * DRM driver writers who look a this function as an example for how to do GEM
1547  * mmap support, please don't implement mmap support like here. The modern way
1548  * to implement DRM mmap support is with an mmap offset ioctl (like
1549  * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1550  * That way debug tooling like valgrind will understand what's going on, hiding
1551  * the mmap call in a driver private ioctl will break that. The i915 driver only
1552  * does cpu mmaps this way because we didn't know better.
1553  */
1554 int
1555 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1556                     struct drm_file *file)
1557 {
1558         struct drm_i915_gem_mmap *args = data;
1559         struct drm_gem_object *obj;
1560         unsigned long addr;
1561
1562         obj = drm_gem_object_lookup(dev, file, args->handle);
1563         if (obj == NULL)
1564                 return -ENOENT;
1565
1566         /* prime objects have no backing filp to GEM mmap
1567          * pages from.
1568          */
1569         if (!obj->filp) {
1570                 drm_gem_object_unreference_unlocked(obj);
1571                 return -EINVAL;
1572         }
1573
1574         addr = vm_mmap(obj->filp, 0, args->size,
1575                        PROT_READ | PROT_WRITE, MAP_SHARED,
1576                        args->offset);
1577         drm_gem_object_unreference_unlocked(obj);
1578         if (IS_ERR((void *)addr))
1579                 return addr;
1580
1581         args->addr_ptr = (uint64_t) addr;
1582
1583         return 0;
1584 }
1585
1586 /**
1587  * i915_gem_fault - fault a page into the GTT
1588  * vma: VMA in question
1589  * vmf: fault info
1590  *
1591  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1592  * from userspace.  The fault handler takes care of binding the object to
1593  * the GTT (if needed), allocating and programming a fence register (again,
1594  * only if needed based on whether the old reg is still valid or the object
1595  * is tiled) and inserting a new PTE into the faulting process.
1596  *
1597  * Note that the faulting process may involve evicting existing objects
1598  * from the GTT and/or fence registers to make room.  So performance may
1599  * suffer if the GTT working set is large or there are few fence registers
1600  * left.
1601  */
1602 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1603 {
1604         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1605         struct drm_device *dev = obj->base.dev;
1606         struct drm_i915_private *dev_priv = dev->dev_private;
1607         pgoff_t page_offset;
1608         unsigned long pfn;
1609         int ret = 0;
1610         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1611
1612         intel_runtime_pm_get(dev_priv);
1613
1614         /* We don't use vmf->pgoff since that has the fake offset */
1615         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1616                 PAGE_SHIFT;
1617
1618         ret = i915_mutex_lock_interruptible(dev);
1619         if (ret)
1620                 goto out;
1621
1622         trace_i915_gem_object_fault(obj, page_offset, true, write);
1623
1624         /* Try to flush the object off the GPU first without holding the lock.
1625          * Upon reacquiring the lock, we will perform our sanity checks and then
1626          * repeat the flush holding the lock in the normal manner to catch cases
1627          * where we are gazumped.
1628          */
1629         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1630         if (ret)
1631                 goto unlock;
1632
1633         /* Access to snoopable pages through the GTT is incoherent. */
1634         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1635                 ret = -EFAULT;
1636                 goto unlock;
1637         }
1638
1639         /* Now bind it into the GTT if needed */
1640         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1641         if (ret)
1642                 goto unlock;
1643
1644         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1645         if (ret)
1646                 goto unpin;
1647
1648         ret = i915_gem_object_get_fence(obj);
1649         if (ret)
1650                 goto unpin;
1651
1652         /* Finally, remap it using the new GTT offset */
1653         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1654         pfn >>= PAGE_SHIFT;
1655
1656         if (!obj->fault_mappable) {
1657                 unsigned long size = min_t(unsigned long,
1658                                            vma->vm_end - vma->vm_start,
1659                                            obj->base.size);
1660                 int i;
1661
1662                 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1663                         ret = vm_insert_pfn(vma,
1664                                             (unsigned long)vma->vm_start + i * PAGE_SIZE,
1665                                             pfn + i);
1666                         if (ret)
1667                                 break;
1668                 }
1669
1670                 obj->fault_mappable = true;
1671         } else
1672                 ret = vm_insert_pfn(vma,
1673                                     (unsigned long)vmf->virtual_address,
1674                                     pfn + page_offset);
1675 unpin:
1676         i915_gem_object_ggtt_unpin(obj);
1677 unlock:
1678         mutex_unlock(&dev->struct_mutex);
1679 out:
1680         switch (ret) {
1681         case -EIO:
1682                 /*
1683                  * We eat errors when the gpu is terminally wedged to avoid
1684                  * userspace unduly crashing (gl has no provisions for mmaps to
1685                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
1686                  * and so needs to be reported.
1687                  */
1688                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1689                         ret = VM_FAULT_SIGBUS;
1690                         break;
1691                 }
1692         case -EAGAIN:
1693                 /*
1694                  * EAGAIN means the gpu is hung and we'll wait for the error
1695                  * handler to reset everything when re-faulting in
1696                  * i915_mutex_lock_interruptible.
1697                  */
1698         case 0:
1699         case -ERESTARTSYS:
1700         case -EINTR:
1701         case -EBUSY:
1702                 /*
1703                  * EBUSY is ok: this just means that another thread
1704                  * already did the job.
1705                  */
1706                 ret = VM_FAULT_NOPAGE;
1707                 break;
1708         case -ENOMEM:
1709                 ret = VM_FAULT_OOM;
1710                 break;
1711         case -ENOSPC:
1712         case -EFAULT:
1713                 ret = VM_FAULT_SIGBUS;
1714                 break;
1715         default:
1716                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1717                 ret = VM_FAULT_SIGBUS;
1718                 break;
1719         }
1720
1721         intel_runtime_pm_put(dev_priv);
1722         return ret;
1723 }
1724
1725 /**
1726  * i915_gem_release_mmap - remove physical page mappings
1727  * @obj: obj in question
1728  *
1729  * Preserve the reservation of the mmapping with the DRM core code, but
1730  * relinquish ownership of the pages back to the system.
1731  *
1732  * It is vital that we remove the page mapping if we have mapped a tiled
1733  * object through the GTT and then lose the fence register due to
1734  * resource pressure. Similarly if the object has been moved out of the
1735  * aperture, than pages mapped into userspace must be revoked. Removing the
1736  * mapping will then trigger a page fault on the next user access, allowing
1737  * fixup by i915_gem_fault().
1738  */
1739 void
1740 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1741 {
1742         if (!obj->fault_mappable)
1743                 return;
1744
1745         drm_vma_node_unmap(&obj->base.vma_node,
1746                            obj->base.dev->anon_inode->i_mapping);
1747         obj->fault_mappable = false;
1748 }
1749
1750 void
1751 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1752 {
1753         struct drm_i915_gem_object *obj;
1754
1755         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1756                 i915_gem_release_mmap(obj);
1757 }
1758
1759 uint32_t
1760 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1761 {
1762         uint32_t gtt_size;
1763
1764         if (INTEL_INFO(dev)->gen >= 4 ||
1765             tiling_mode == I915_TILING_NONE)
1766                 return size;
1767
1768         /* Previous chips need a power-of-two fence region when tiling */
1769         if (INTEL_INFO(dev)->gen == 3)
1770                 gtt_size = 1024*1024;
1771         else
1772                 gtt_size = 512*1024;
1773
1774         while (gtt_size < size)
1775                 gtt_size <<= 1;
1776
1777         return gtt_size;
1778 }
1779
1780 /**
1781  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1782  * @obj: object to check
1783  *
1784  * Return the required GTT alignment for an object, taking into account
1785  * potential fence register mapping.
1786  */
1787 uint32_t
1788 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1789                            int tiling_mode, bool fenced)
1790 {
1791         /*
1792          * Minimum alignment is 4k (GTT page size), but might be greater
1793          * if a fence register is needed for the object.
1794          */
1795         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1796             tiling_mode == I915_TILING_NONE)
1797                 return 4096;
1798
1799         /*
1800          * Previous chips need to be aligned to the size of the smallest
1801          * fence register that can contain the object.
1802          */
1803         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1804 }
1805
1806 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1807 {
1808         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1809         int ret;
1810
1811         if (drm_vma_node_has_offset(&obj->base.vma_node))
1812                 return 0;
1813
1814         dev_priv->mm.shrinker_no_lock_stealing = true;
1815
1816         ret = drm_gem_create_mmap_offset(&obj->base);
1817         if (ret != -ENOSPC)
1818                 goto out;
1819
1820         /* Badly fragmented mmap space? The only way we can recover
1821          * space is by destroying unwanted objects. We can't randomly release
1822          * mmap_offsets as userspace expects them to be persistent for the
1823          * lifetime of the objects. The closest we can is to release the
1824          * offsets on purgeable objects by truncating it and marking it purged,
1825          * which prevents userspace from ever using that object again.
1826          */
1827         i915_gem_shrink(dev_priv,
1828                         obj->base.size >> PAGE_SHIFT,
1829                         I915_SHRINK_BOUND |
1830                         I915_SHRINK_UNBOUND |
1831                         I915_SHRINK_PURGEABLE);
1832         ret = drm_gem_create_mmap_offset(&obj->base);
1833         if (ret != -ENOSPC)
1834                 goto out;
1835
1836         i915_gem_shrink_all(dev_priv);
1837         ret = drm_gem_create_mmap_offset(&obj->base);
1838 out:
1839         dev_priv->mm.shrinker_no_lock_stealing = false;
1840
1841         return ret;
1842 }
1843
1844 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1845 {
1846         drm_gem_free_mmap_offset(&obj->base);
1847 }
1848
1849 static int
1850 i915_gem_mmap_gtt(struct drm_file *file,
1851                   struct drm_device *dev,
1852                   uint32_t handle, bool dumb,
1853                   uint64_t *offset)
1854 {
1855         struct drm_i915_private *dev_priv = dev->dev_private;
1856         struct drm_i915_gem_object *obj;
1857         int ret;
1858
1859         ret = i915_mutex_lock_interruptible(dev);
1860         if (ret)
1861                 return ret;
1862
1863         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1864         if (&obj->base == NULL) {
1865                 ret = -ENOENT;
1866                 goto unlock;
1867         }
1868
1869         /*
1870          * We don't allow dumb mmaps on objects created using another
1871          * interface.
1872          */
1873         WARN_ONCE(dumb && !(obj->base.dumb || obj->base.import_attach),
1874                   "Illegal dumb map of accelerated buffer.\n");
1875
1876         if (obj->base.size > dev_priv->gtt.mappable_end) {
1877                 ret = -E2BIG;
1878                 goto out;
1879         }
1880
1881         if (obj->madv != I915_MADV_WILLNEED) {
1882                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1883                 ret = -EFAULT;
1884                 goto out;
1885         }
1886
1887         ret = i915_gem_object_create_mmap_offset(obj);
1888         if (ret)
1889                 goto out;
1890
1891         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1892
1893 out:
1894         drm_gem_object_unreference(&obj->base);
1895 unlock:
1896         mutex_unlock(&dev->struct_mutex);
1897         return ret;
1898 }
1899
1900 int
1901 i915_gem_dumb_map_offset(struct drm_file *file,
1902                          struct drm_device *dev,
1903                          uint32_t handle,
1904                          uint64_t *offset)
1905 {
1906         return i915_gem_mmap_gtt(file, dev, handle, true, offset);
1907 }
1908
1909 /**
1910  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1911  * @dev: DRM device
1912  * @data: GTT mapping ioctl data
1913  * @file: GEM object info
1914  *
1915  * Simply returns the fake offset to userspace so it can mmap it.
1916  * The mmap call will end up in drm_gem_mmap(), which will set things
1917  * up so we can get faults in the handler above.
1918  *
1919  * The fault handler will take care of binding the object into the GTT
1920  * (since it may have been evicted to make room for something), allocating
1921  * a fence register, and mapping the appropriate aperture address into
1922  * userspace.
1923  */
1924 int
1925 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1926                         struct drm_file *file)
1927 {
1928         struct drm_i915_gem_mmap_gtt *args = data;
1929
1930         return i915_gem_mmap_gtt(file, dev, args->handle, false, &args->offset);
1931 }
1932
1933 static inline int
1934 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1935 {
1936         return obj->madv == I915_MADV_DONTNEED;
1937 }
1938
1939 /* Immediately discard the backing storage */
1940 static void
1941 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1942 {
1943         i915_gem_object_free_mmap_offset(obj);
1944
1945         if (obj->base.filp == NULL)
1946                 return;
1947
1948         /* Our goal here is to return as much of the memory as
1949          * is possible back to the system as we are called from OOM.
1950          * To do this we must instruct the shmfs to drop all of its
1951          * backing pages, *now*.
1952          */
1953         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1954         obj->madv = __I915_MADV_PURGED;
1955 }
1956
1957 /* Try to discard unwanted pages */
1958 static void
1959 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1960 {
1961         struct address_space *mapping;
1962
1963         switch (obj->madv) {
1964         case I915_MADV_DONTNEED:
1965                 i915_gem_object_truncate(obj);
1966         case __I915_MADV_PURGED:
1967                 return;
1968         }
1969
1970         if (obj->base.filp == NULL)
1971                 return;
1972
1973         mapping = file_inode(obj->base.filp)->i_mapping,
1974         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1975 }
1976
1977 static void
1978 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1979 {
1980         struct sg_page_iter sg_iter;
1981         int ret;
1982
1983         BUG_ON(obj->madv == __I915_MADV_PURGED);
1984
1985         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1986         if (ret) {
1987                 /* In the event of a disaster, abandon all caches and
1988                  * hope for the best.
1989                  */
1990                 WARN_ON(ret != -EIO);
1991                 i915_gem_clflush_object(obj, true);
1992                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1993         }
1994
1995         if (i915_gem_object_needs_bit17_swizzle(obj))
1996                 i915_gem_object_save_bit_17_swizzle(obj);
1997
1998         if (obj->madv == I915_MADV_DONTNEED)
1999                 obj->dirty = 0;
2000
2001         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2002                 struct page *page = sg_page_iter_page(&sg_iter);
2003
2004                 if (obj->dirty)
2005                         set_page_dirty(page);
2006
2007                 if (obj->madv == I915_MADV_WILLNEED)
2008                         mark_page_accessed(page);
2009
2010                 page_cache_release(page);
2011         }
2012         obj->dirty = 0;
2013
2014         sg_free_table(obj->pages);
2015         kfree(obj->pages);
2016 }
2017
2018 int
2019 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2020 {
2021         const struct drm_i915_gem_object_ops *ops = obj->ops;
2022
2023         if (obj->pages == NULL)
2024                 return 0;
2025
2026         if (obj->pages_pin_count)
2027                 return -EBUSY;
2028
2029         BUG_ON(i915_gem_obj_bound_any(obj));
2030
2031         /* ->put_pages might need to allocate memory for the bit17 swizzle
2032          * array, hence protect them from being reaped by removing them from gtt
2033          * lists early. */
2034         list_del(&obj->global_list);
2035
2036         ops->put_pages(obj);
2037         obj->pages = NULL;
2038
2039         i915_gem_object_invalidate(obj);
2040
2041         return 0;
2042 }
2043
2044 unsigned long
2045 i915_gem_shrink(struct drm_i915_private *dev_priv,
2046                 long target, unsigned flags)
2047 {
2048         const struct {
2049                 struct list_head *list;
2050                 unsigned int bit;
2051         } phases[] = {
2052                 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2053                 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2054                 { NULL, 0 },
2055         }, *phase;
2056         unsigned long count = 0;
2057
2058         /*
2059          * As we may completely rewrite the (un)bound list whilst unbinding
2060          * (due to retiring requests) we have to strictly process only
2061          * one element of the list at the time, and recheck the list
2062          * on every iteration.
2063          *
2064          * In particular, we must hold a reference whilst removing the
2065          * object as we may end up waiting for and/or retiring the objects.
2066          * This might release the final reference (held by the active list)
2067          * and result in the object being freed from under us. This is
2068          * similar to the precautions the eviction code must take whilst
2069          * removing objects.
2070          *
2071          * Also note that although these lists do not hold a reference to
2072          * the object we can safely grab one here: The final object
2073          * unreferencing and the bound_list are both protected by the
2074          * dev->struct_mutex and so we won't ever be able to observe an
2075          * object on the bound_list with a reference count equals 0.
2076          */
2077         for (phase = phases; phase->list; phase++) {
2078                 struct list_head still_in_list;
2079
2080                 if ((flags & phase->bit) == 0)
2081                         continue;
2082
2083                 INIT_LIST_HEAD(&still_in_list);
2084                 while (count < target && !list_empty(phase->list)) {
2085                         struct drm_i915_gem_object *obj;
2086                         struct i915_vma *vma, *v;
2087
2088                         obj = list_first_entry(phase->list,
2089                                                typeof(*obj), global_list);
2090                         list_move_tail(&obj->global_list, &still_in_list);
2091
2092                         if (flags & I915_SHRINK_PURGEABLE &&
2093                             !i915_gem_object_is_purgeable(obj))
2094                                 continue;
2095
2096                         drm_gem_object_reference(&obj->base);
2097
2098                         /* For the unbound phase, this should be a no-op! */
2099                         list_for_each_entry_safe(vma, v,
2100                                                  &obj->vma_list, vma_link)
2101                                 if (i915_vma_unbind(vma))
2102                                         break;
2103
2104                         if (i915_gem_object_put_pages(obj) == 0)
2105                                 count += obj->base.size >> PAGE_SHIFT;
2106
2107                         drm_gem_object_unreference(&obj->base);
2108                 }
2109                 list_splice(&still_in_list, phase->list);
2110         }
2111
2112         return count;
2113 }
2114
2115 static unsigned long
2116 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2117 {
2118         i915_gem_evict_everything(dev_priv->dev);
2119         return i915_gem_shrink(dev_priv, LONG_MAX,
2120                                I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2121 }
2122
2123 static int
2124 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2125 {
2126         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2127         int page_count, i;
2128         struct address_space *mapping;
2129         struct sg_table *st;
2130         struct scatterlist *sg;
2131         struct sg_page_iter sg_iter;
2132         struct page *page;
2133         unsigned long last_pfn = 0;     /* suppress gcc warning */
2134         gfp_t gfp;
2135
2136         /* Assert that the object is not currently in any GPU domain. As it
2137          * wasn't in the GTT, there shouldn't be any way it could have been in
2138          * a GPU cache
2139          */
2140         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2141         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2142
2143         st = kmalloc(sizeof(*st), GFP_KERNEL);
2144         if (st == NULL)
2145                 return -ENOMEM;
2146
2147         page_count = obj->base.size / PAGE_SIZE;
2148         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2149                 kfree(st);
2150                 return -ENOMEM;
2151         }
2152
2153         /* Get the list of pages out of our struct file.  They'll be pinned
2154          * at this point until we release them.
2155          *
2156          * Fail silently without starting the shrinker
2157          */
2158         mapping = file_inode(obj->base.filp)->i_mapping;
2159         gfp = mapping_gfp_mask(mapping);
2160         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2161         gfp &= ~(__GFP_IO | __GFP_WAIT);
2162         sg = st->sgl;
2163         st->nents = 0;
2164         for (i = 0; i < page_count; i++) {
2165                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2166                 if (IS_ERR(page)) {
2167                         i915_gem_shrink(dev_priv,
2168                                         page_count,
2169                                         I915_SHRINK_BOUND |
2170                                         I915_SHRINK_UNBOUND |
2171                                         I915_SHRINK_PURGEABLE);
2172                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2173                 }
2174                 if (IS_ERR(page)) {
2175                         /* We've tried hard to allocate the memory by reaping
2176                          * our own buffer, now let the real VM do its job and
2177                          * go down in flames if truly OOM.
2178                          */
2179                         i915_gem_shrink_all(dev_priv);
2180                         page = shmem_read_mapping_page(mapping, i);
2181                         if (IS_ERR(page))
2182                                 goto err_pages;
2183                 }
2184 #ifdef CONFIG_SWIOTLB
2185                 if (swiotlb_nr_tbl()) {
2186                         st->nents++;
2187                         sg_set_page(sg, page, PAGE_SIZE, 0);
2188                         sg = sg_next(sg);
2189                         continue;
2190                 }
2191 #endif
2192                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2193                         if (i)
2194                                 sg = sg_next(sg);
2195                         st->nents++;
2196                         sg_set_page(sg, page, PAGE_SIZE, 0);
2197                 } else {
2198                         sg->length += PAGE_SIZE;
2199                 }
2200                 last_pfn = page_to_pfn(page);
2201
2202                 /* Check that the i965g/gm workaround works. */
2203                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2204         }
2205 #ifdef CONFIG_SWIOTLB
2206         if (!swiotlb_nr_tbl())
2207 #endif
2208                 sg_mark_end(sg);
2209         obj->pages = st;
2210
2211         if (i915_gem_object_needs_bit17_swizzle(obj))
2212                 i915_gem_object_do_bit_17_swizzle(obj);
2213
2214         if (obj->tiling_mode != I915_TILING_NONE &&
2215             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2216                 i915_gem_object_pin_pages(obj);
2217
2218         return 0;
2219
2220 err_pages:
2221         sg_mark_end(sg);
2222         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2223                 page_cache_release(sg_page_iter_page(&sg_iter));
2224         sg_free_table(st);
2225         kfree(st);
2226
2227         /* shmemfs first checks if there is enough memory to allocate the page
2228          * and reports ENOSPC should there be insufficient, along with the usual
2229          * ENOMEM for a genuine allocation failure.
2230          *
2231          * We use ENOSPC in our driver to mean that we have run out of aperture
2232          * space and so want to translate the error from shmemfs back to our
2233          * usual understanding of ENOMEM.
2234          */
2235         if (PTR_ERR(page) == -ENOSPC)
2236                 return -ENOMEM;
2237         else
2238                 return PTR_ERR(page);
2239 }
2240
2241 /* Ensure that the associated pages are gathered from the backing storage
2242  * and pinned into our object. i915_gem_object_get_pages() may be called
2243  * multiple times before they are released by a single call to
2244  * i915_gem_object_put_pages() - once the pages are no longer referenced
2245  * either as a result of memory pressure (reaping pages under the shrinker)
2246  * or as the object is itself released.
2247  */
2248 int
2249 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2250 {
2251         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2252         const struct drm_i915_gem_object_ops *ops = obj->ops;
2253         int ret;
2254
2255         if (obj->pages)
2256                 return 0;
2257
2258         if (obj->madv != I915_MADV_WILLNEED) {
2259                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2260                 return -EFAULT;
2261         }
2262
2263         BUG_ON(obj->pages_pin_count);
2264
2265         ret = ops->get_pages(obj);
2266         if (ret)
2267                 return ret;
2268
2269         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2270         return 0;
2271 }
2272
2273 static void
2274 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2275                                struct intel_engine_cs *ring)
2276 {
2277         u32 seqno = intel_ring_get_seqno(ring);
2278
2279         BUG_ON(ring == NULL);
2280         if (obj->ring != ring && obj->last_write_seqno) {
2281                 /* Keep the seqno relative to the current ring */
2282                 obj->last_write_seqno = seqno;
2283         }
2284         obj->ring = ring;
2285
2286         /* Add a reference if we're newly entering the active list. */
2287         if (!obj->active) {
2288                 drm_gem_object_reference(&obj->base);
2289                 obj->active = 1;
2290         }
2291
2292         list_move_tail(&obj->ring_list, &ring->active_list);
2293
2294         obj->last_read_seqno = seqno;
2295 }
2296
2297 void i915_vma_move_to_active(struct i915_vma *vma,
2298                              struct intel_engine_cs *ring)
2299 {
2300         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2301         return i915_gem_object_move_to_active(vma->obj, ring);
2302 }
2303
2304 static void
2305 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2306 {
2307         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2308         struct i915_address_space *vm;
2309         struct i915_vma *vma;
2310
2311         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2312         BUG_ON(!obj->active);
2313
2314         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2315                 vma = i915_gem_obj_to_vma(obj, vm);
2316                 if (vma && !list_empty(&vma->mm_list))
2317                         list_move_tail(&vma->mm_list, &vm->inactive_list);
2318         }
2319
2320         intel_fb_obj_flush(obj, true);
2321
2322         list_del_init(&obj->ring_list);
2323         obj->ring = NULL;
2324
2325         obj->last_read_seqno = 0;
2326         obj->last_write_seqno = 0;
2327         obj->base.write_domain = 0;
2328
2329         obj->last_fenced_seqno = 0;
2330
2331         obj->active = 0;
2332         drm_gem_object_unreference(&obj->base);
2333
2334         WARN_ON(i915_verify_lists(dev));
2335 }
2336
2337 static void
2338 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2339 {
2340         struct intel_engine_cs *ring = obj->ring;
2341
2342         if (ring == NULL)
2343                 return;
2344
2345         if (i915_seqno_passed(ring->get_seqno(ring, true),
2346                               obj->last_read_seqno))
2347                 i915_gem_object_move_to_inactive(obj);
2348 }
2349
2350 static int
2351 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2352 {
2353         struct drm_i915_private *dev_priv = dev->dev_private;
2354         struct intel_engine_cs *ring;
2355         int ret, i, j;
2356
2357         /* Carefully retire all requests without writing to the rings */
2358         for_each_ring(ring, dev_priv, i) {
2359                 ret = intel_ring_idle(ring);
2360                 if (ret)
2361                         return ret;
2362         }
2363         i915_gem_retire_requests(dev);
2364
2365         /* Finally reset hw state */
2366         for_each_ring(ring, dev_priv, i) {
2367                 intel_ring_init_seqno(ring, seqno);
2368
2369                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2370                         ring->semaphore.sync_seqno[j] = 0;
2371         }
2372
2373         return 0;
2374 }
2375
2376 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2377 {
2378         struct drm_i915_private *dev_priv = dev->dev_private;
2379         int ret;
2380
2381         if (seqno == 0)
2382                 return -EINVAL;
2383
2384         /* HWS page needs to be set less than what we
2385          * will inject to ring
2386          */
2387         ret = i915_gem_init_seqno(dev, seqno - 1);
2388         if (ret)
2389                 return ret;
2390
2391         /* Carefully set the last_seqno value so that wrap
2392          * detection still works
2393          */
2394         dev_priv->next_seqno = seqno;
2395         dev_priv->last_seqno = seqno - 1;
2396         if (dev_priv->last_seqno == 0)
2397                 dev_priv->last_seqno--;
2398
2399         return 0;
2400 }
2401
2402 int
2403 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2404 {
2405         struct drm_i915_private *dev_priv = dev->dev_private;
2406
2407         /* reserve 0 for non-seqno */
2408         if (dev_priv->next_seqno == 0) {
2409                 int ret = i915_gem_init_seqno(dev, 0);
2410                 if (ret)
2411                         return ret;
2412
2413                 dev_priv->next_seqno = 1;
2414         }
2415
2416         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2417         return 0;
2418 }
2419
2420 int __i915_add_request(struct intel_engine_cs *ring,
2421                        struct drm_file *file,
2422                        struct drm_i915_gem_object *obj,
2423                        u32 *out_seqno)
2424 {
2425         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2426         struct drm_i915_gem_request *request;
2427         struct intel_ringbuffer *ringbuf;
2428         u32 request_ring_position, request_start;
2429         int ret;
2430
2431         request = ring->preallocated_lazy_request;
2432         if (WARN_ON(request == NULL))
2433                 return -ENOMEM;
2434
2435         if (i915.enable_execlists) {
2436                 struct intel_context *ctx = request->ctx;
2437                 ringbuf = ctx->engine[ring->id].ringbuf;
2438         } else
2439                 ringbuf = ring->buffer;
2440
2441         request_start = intel_ring_get_tail(ringbuf);
2442         /*
2443          * Emit any outstanding flushes - execbuf can fail to emit the flush
2444          * after having emitted the batchbuffer command. Hence we need to fix
2445          * things up similar to emitting the lazy request. The difference here
2446          * is that the flush _must_ happen before the next request, no matter
2447          * what.
2448          */
2449         if (i915.enable_execlists) {
2450                 ret = logical_ring_flush_all_caches(ringbuf);
2451                 if (ret)
2452                         return ret;
2453         } else {
2454                 ret = intel_ring_flush_all_caches(ring);
2455                 if (ret)
2456                         return ret;
2457         }
2458
2459         /* Record the position of the start of the request so that
2460          * should we detect the updated seqno part-way through the
2461          * GPU processing the request, we never over-estimate the
2462          * position of the head.
2463          */
2464         request_ring_position = intel_ring_get_tail(ringbuf);
2465
2466         if (i915.enable_execlists) {
2467                 ret = ring->emit_request(ringbuf);
2468                 if (ret)
2469                         return ret;
2470         } else {
2471                 ret = ring->add_request(ring);
2472                 if (ret)
2473                         return ret;
2474         }
2475
2476         request->seqno = intel_ring_get_seqno(ring);
2477         request->ring = ring;
2478         request->head = request_start;
2479         request->tail = request_ring_position;
2480
2481         /* Whilst this request exists, batch_obj will be on the
2482          * active_list, and so will hold the active reference. Only when this
2483          * request is retired will the the batch_obj be moved onto the
2484          * inactive_list and lose its active reference. Hence we do not need
2485          * to explicitly hold another reference here.
2486          */
2487         request->batch_obj = obj;
2488
2489         if (!i915.enable_execlists) {
2490                 /* Hold a reference to the current context so that we can inspect
2491                  * it later in case a hangcheck error event fires.
2492                  */
2493                 request->ctx = ring->last_context;
2494                 if (request->ctx)
2495                         i915_gem_context_reference(request->ctx);
2496         }
2497
2498         request->emitted_jiffies = jiffies;
2499         list_add_tail(&request->list, &ring->request_list);
2500         request->file_priv = NULL;
2501
2502         if (file) {
2503                 struct drm_i915_file_private *file_priv = file->driver_priv;
2504
2505                 spin_lock(&file_priv->mm.lock);
2506                 request->file_priv = file_priv;
2507                 list_add_tail(&request->client_list,
2508                               &file_priv->mm.request_list);
2509                 spin_unlock(&file_priv->mm.lock);
2510         }
2511
2512         trace_i915_gem_request_add(ring, request->seqno);
2513         ring->outstanding_lazy_seqno = 0;
2514         ring->preallocated_lazy_request = NULL;
2515
2516         i915_queue_hangcheck(ring->dev);
2517
2518         cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2519         queue_delayed_work(dev_priv->wq,
2520                            &dev_priv->mm.retire_work,
2521                            round_jiffies_up_relative(HZ));
2522         intel_mark_busy(dev_priv->dev);
2523
2524         if (out_seqno)
2525                 *out_seqno = request->seqno;
2526         return 0;
2527 }
2528
2529 static inline void
2530 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2531 {
2532         struct drm_i915_file_private *file_priv = request->file_priv;
2533
2534         if (!file_priv)
2535                 return;
2536
2537         spin_lock(&file_priv->mm.lock);
2538         list_del(&request->client_list);
2539         request->file_priv = NULL;
2540         spin_unlock(&file_priv->mm.lock);
2541 }
2542
2543 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2544                                    const struct intel_context *ctx)
2545 {
2546         unsigned long elapsed;
2547
2548         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2549
2550         if (ctx->hang_stats.banned)
2551                 return true;
2552
2553         if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2554                 if (!i915_gem_context_is_default(ctx)) {
2555                         DRM_DEBUG("context hanging too fast, banning!\n");
2556                         return true;
2557                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2558                         if (i915_stop_ring_allow_warn(dev_priv))
2559                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2560                         return true;
2561                 }
2562         }
2563
2564         return false;
2565 }
2566
2567 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2568                                   struct intel_context *ctx,
2569                                   const bool guilty)
2570 {
2571         struct i915_ctx_hang_stats *hs;
2572
2573         if (WARN_ON(!ctx))
2574                 return;
2575
2576         hs = &ctx->hang_stats;
2577
2578         if (guilty) {
2579                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2580                 hs->batch_active++;
2581                 hs->guilty_ts = get_seconds();
2582         } else {
2583                 hs->batch_pending++;
2584         }
2585 }
2586
2587 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2588 {
2589         struct intel_context *ctx = request->ctx;
2590
2591         list_del(&request->list);
2592         i915_gem_request_remove_from_client(request);
2593
2594         if (ctx) {
2595                 if (i915.enable_execlists) {
2596                         struct intel_engine_cs *ring = request->ring;
2597
2598                         if (ctx != ring->default_context)
2599                                 intel_lr_context_unpin(ring, ctx);
2600                 }
2601                 i915_gem_context_unreference(ctx);
2602         }
2603         kfree(request);
2604 }
2605
2606 struct drm_i915_gem_request *
2607 i915_gem_find_active_request(struct intel_engine_cs *ring)
2608 {
2609         struct drm_i915_gem_request *request;
2610         u32 completed_seqno;
2611
2612         completed_seqno = ring->get_seqno(ring, false);
2613
2614         list_for_each_entry(request, &ring->request_list, list) {
2615                 if (i915_seqno_passed(completed_seqno, request->seqno))
2616                         continue;
2617
2618                 return request;
2619         }
2620
2621         return NULL;
2622 }
2623
2624 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2625                                        struct intel_engine_cs *ring)
2626 {
2627         struct drm_i915_gem_request *request;
2628         bool ring_hung;
2629
2630         request = i915_gem_find_active_request(ring);
2631
2632         if (request == NULL)
2633                 return;
2634
2635         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2636
2637         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2638
2639         list_for_each_entry_continue(request, &ring->request_list, list)
2640                 i915_set_reset_status(dev_priv, request->ctx, false);
2641 }
2642
2643 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2644                                         struct intel_engine_cs *ring)
2645 {
2646         while (!list_empty(&ring->active_list)) {
2647                 struct drm_i915_gem_object *obj;
2648
2649                 obj = list_first_entry(&ring->active_list,
2650                                        struct drm_i915_gem_object,
2651                                        ring_list);
2652
2653                 i915_gem_object_move_to_inactive(obj);
2654         }
2655
2656         /*
2657          * Clear the execlists queue up before freeing the requests, as those
2658          * are the ones that keep the context and ringbuffer backing objects
2659          * pinned in place.
2660          */
2661         while (!list_empty(&ring->execlist_queue)) {
2662                 struct intel_ctx_submit_request *submit_req;
2663
2664                 submit_req = list_first_entry(&ring->execlist_queue,
2665                                 struct intel_ctx_submit_request,
2666                                 execlist_link);
2667                 list_del(&submit_req->execlist_link);
2668                 intel_runtime_pm_put(dev_priv);
2669                 i915_gem_context_unreference(submit_req->ctx);
2670                 kfree(submit_req);
2671         }
2672
2673         /*
2674          * We must free the requests after all the corresponding objects have
2675          * been moved off active lists. Which is the same order as the normal
2676          * retire_requests function does. This is important if object hold
2677          * implicit references on things like e.g. ppgtt address spaces through
2678          * the request.
2679          */
2680         while (!list_empty(&ring->request_list)) {
2681                 struct drm_i915_gem_request *request;
2682
2683                 request = list_first_entry(&ring->request_list,
2684                                            struct drm_i915_gem_request,
2685                                            list);
2686
2687                 i915_gem_free_request(request);
2688         }
2689
2690         /* These may not have been flush before the reset, do so now */
2691         kfree(ring->preallocated_lazy_request);
2692         ring->preallocated_lazy_request = NULL;
2693         ring->outstanding_lazy_seqno = 0;
2694 }
2695
2696 void i915_gem_restore_fences(struct drm_device *dev)
2697 {
2698         struct drm_i915_private *dev_priv = dev->dev_private;
2699         int i;
2700
2701         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2702                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2703
2704                 /*
2705                  * Commit delayed tiling changes if we have an object still
2706                  * attached to the fence, otherwise just clear the fence.
2707                  */
2708                 if (reg->obj) {
2709                         i915_gem_object_update_fence(reg->obj, reg,
2710                                                      reg->obj->tiling_mode);
2711                 } else {
2712                         i915_gem_write_fence(dev, i, NULL);
2713                 }
2714         }
2715 }
2716
2717 void i915_gem_reset(struct drm_device *dev)
2718 {
2719         struct drm_i915_private *dev_priv = dev->dev_private;
2720         struct intel_engine_cs *ring;
2721         int i;
2722
2723         /*
2724          * Before we free the objects from the requests, we need to inspect
2725          * them for finding the guilty party. As the requests only borrow
2726          * their reference to the objects, the inspection must be done first.
2727          */
2728         for_each_ring(ring, dev_priv, i)
2729                 i915_gem_reset_ring_status(dev_priv, ring);
2730
2731         for_each_ring(ring, dev_priv, i)
2732                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2733
2734         i915_gem_context_reset(dev);
2735
2736         i915_gem_restore_fences(dev);
2737 }
2738
2739 /**
2740  * This function clears the request list as sequence numbers are passed.
2741  */
2742 void
2743 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2744 {
2745         uint32_t seqno;
2746
2747         if (list_empty(&ring->request_list))
2748                 return;
2749
2750         WARN_ON(i915_verify_lists(ring->dev));
2751
2752         seqno = ring->get_seqno(ring, true);
2753
2754         /* Move any buffers on the active list that are no longer referenced
2755          * by the ringbuffer to the flushing/inactive lists as appropriate,
2756          * before we free the context associated with the requests.
2757          */
2758         while (!list_empty(&ring->active_list)) {
2759                 struct drm_i915_gem_object *obj;
2760
2761                 obj = list_first_entry(&ring->active_list,
2762                                       struct drm_i915_gem_object,
2763                                       ring_list);
2764
2765                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2766                         break;
2767
2768                 i915_gem_object_move_to_inactive(obj);
2769         }
2770
2771
2772         while (!list_empty(&ring->request_list)) {
2773                 struct drm_i915_gem_request *request;
2774                 struct intel_ringbuffer *ringbuf;
2775
2776                 request = list_first_entry(&ring->request_list,
2777                                            struct drm_i915_gem_request,
2778                                            list);
2779
2780                 if (!i915_seqno_passed(seqno, request->seqno))
2781                         break;
2782
2783                 trace_i915_gem_request_retire(ring, request->seqno);
2784
2785                 /* This is one of the few common intersection points
2786                  * between legacy ringbuffer submission and execlists:
2787                  * we need to tell them apart in order to find the correct
2788                  * ringbuffer to which the request belongs to.
2789                  */
2790                 if (i915.enable_execlists) {
2791                         struct intel_context *ctx = request->ctx;
2792                         ringbuf = ctx->engine[ring->id].ringbuf;
2793                 } else
2794                         ringbuf = ring->buffer;
2795
2796                 /* We know the GPU must have read the request to have
2797                  * sent us the seqno + interrupt, so use the position
2798                  * of tail of the request to update the last known position
2799                  * of the GPU head.
2800                  */
2801                 ringbuf->last_retired_head = request->tail;
2802
2803                 i915_gem_free_request(request);
2804         }
2805
2806         if (unlikely(ring->trace_irq_seqno &&
2807                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2808                 ring->irq_put(ring);
2809                 ring->trace_irq_seqno = 0;
2810         }
2811
2812         WARN_ON(i915_verify_lists(ring->dev));
2813 }
2814
2815 bool
2816 i915_gem_retire_requests(struct drm_device *dev)
2817 {
2818         struct drm_i915_private *dev_priv = dev->dev_private;
2819         struct intel_engine_cs *ring;
2820         bool idle = true;
2821         int i;
2822
2823         for_each_ring(ring, dev_priv, i) {
2824                 i915_gem_retire_requests_ring(ring);
2825                 idle &= list_empty(&ring->request_list);
2826                 if (i915.enable_execlists) {
2827                         unsigned long flags;
2828
2829                         spin_lock_irqsave(&ring->execlist_lock, flags);
2830                         idle &= list_empty(&ring->execlist_queue);
2831                         spin_unlock_irqrestore(&ring->execlist_lock, flags);
2832
2833                         intel_execlists_retire_requests(ring);
2834                 }
2835         }
2836
2837         if (idle)
2838                 mod_delayed_work(dev_priv->wq,
2839                                    &dev_priv->mm.idle_work,
2840                                    msecs_to_jiffies(100));
2841
2842         return idle;
2843 }
2844
2845 static void
2846 i915_gem_retire_work_handler(struct work_struct *work)
2847 {
2848         struct drm_i915_private *dev_priv =
2849                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2850         struct drm_device *dev = dev_priv->dev;
2851         bool idle;
2852
2853         /* Come back later if the device is busy... */
2854         idle = false;
2855         if (mutex_trylock(&dev->struct_mutex)) {
2856                 idle = i915_gem_retire_requests(dev);
2857                 mutex_unlock(&dev->struct_mutex);
2858         }
2859         if (!idle)
2860                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2861                                    round_jiffies_up_relative(HZ));
2862 }
2863
2864 static void
2865 i915_gem_idle_work_handler(struct work_struct *work)
2866 {
2867         struct drm_i915_private *dev_priv =
2868                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2869
2870         intel_mark_idle(dev_priv->dev);
2871 }
2872
2873 /**
2874  * Ensures that an object will eventually get non-busy by flushing any required
2875  * write domains, emitting any outstanding lazy request and retiring and
2876  * completed requests.
2877  */
2878 static int
2879 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2880 {
2881         int ret;
2882
2883         if (obj->active) {
2884                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2885                 if (ret)
2886                         return ret;
2887
2888                 i915_gem_retire_requests_ring(obj->ring);
2889         }
2890
2891         return 0;
2892 }
2893
2894 /**
2895  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2896  * @DRM_IOCTL_ARGS: standard ioctl arguments
2897  *
2898  * Returns 0 if successful, else an error is returned with the remaining time in
2899  * the timeout parameter.
2900  *  -ETIME: object is still busy after timeout
2901  *  -ERESTARTSYS: signal interrupted the wait
2902  *  -ENONENT: object doesn't exist
2903  * Also possible, but rare:
2904  *  -EAGAIN: GPU wedged
2905  *  -ENOMEM: damn
2906  *  -ENODEV: Internal IRQ fail
2907  *  -E?: The add request failed
2908  *
2909  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2910  * non-zero timeout parameter the wait ioctl will wait for the given number of
2911  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2912  * without holding struct_mutex the object may become re-busied before this
2913  * function completes. A similar but shorter * race condition exists in the busy
2914  * ioctl
2915  */
2916 int
2917 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2918 {
2919         struct drm_i915_private *dev_priv = dev->dev_private;
2920         struct drm_i915_gem_wait *args = data;
2921         struct drm_i915_gem_object *obj;
2922         struct intel_engine_cs *ring = NULL;
2923         unsigned reset_counter;
2924         u32 seqno = 0;
2925         int ret = 0;
2926
2927         if (args->flags != 0)
2928                 return -EINVAL;
2929
2930         ret = i915_mutex_lock_interruptible(dev);
2931         if (ret)
2932                 return ret;
2933
2934         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2935         if (&obj->base == NULL) {
2936                 mutex_unlock(&dev->struct_mutex);
2937                 return -ENOENT;
2938         }
2939
2940         /* Need to make sure the object gets inactive eventually. */
2941         ret = i915_gem_object_flush_active(obj);
2942         if (ret)
2943                 goto out;
2944
2945         if (obj->active) {
2946                 seqno = obj->last_read_seqno;
2947                 ring = obj->ring;
2948         }
2949
2950         if (seqno == 0)
2951                  goto out;
2952
2953         /* Do this after OLR check to make sure we make forward progress polling
2954          * on this IOCTL with a timeout <=0 (like busy ioctl)
2955          */
2956         if (args->timeout_ns <= 0) {
2957                 ret = -ETIME;
2958                 goto out;
2959         }
2960
2961         drm_gem_object_unreference(&obj->base);
2962         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2963         mutex_unlock(&dev->struct_mutex);
2964
2965         return __i915_wait_seqno(ring, seqno, reset_counter, true,
2966                                  &args->timeout_ns, file->driver_priv);
2967
2968 out:
2969         drm_gem_object_unreference(&obj->base);
2970         mutex_unlock(&dev->struct_mutex);
2971         return ret;
2972 }
2973
2974 /**
2975  * i915_gem_object_sync - sync an object to a ring.
2976  *
2977  * @obj: object which may be in use on another ring.
2978  * @to: ring we wish to use the object on. May be NULL.
2979  *
2980  * This code is meant to abstract object synchronization with the GPU.
2981  * Calling with NULL implies synchronizing the object with the CPU
2982  * rather than a particular GPU ring.
2983  *
2984  * Returns 0 if successful, else propagates up the lower layer error.
2985  */
2986 int
2987 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2988                      struct intel_engine_cs *to)
2989 {
2990         struct intel_engine_cs *from = obj->ring;
2991         u32 seqno;
2992         int ret, idx;
2993
2994         if (from == NULL || to == from)
2995                 return 0;
2996
2997         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2998                 return i915_gem_object_wait_rendering(obj, false);
2999
3000         idx = intel_ring_sync_index(from, to);
3001
3002         seqno = obj->last_read_seqno;
3003         /* Optimization: Avoid semaphore sync when we are sure we already
3004          * waited for an object with higher seqno */
3005         if (seqno <= from->semaphore.sync_seqno[idx])
3006                 return 0;
3007
3008         ret = i915_gem_check_olr(obj->ring, seqno);
3009         if (ret)
3010                 return ret;
3011
3012         trace_i915_gem_ring_sync_to(from, to, seqno);
3013         ret = to->semaphore.sync_to(to, from, seqno);
3014         if (!ret)
3015                 /* We use last_read_seqno because sync_to()
3016                  * might have just caused seqno wrap under
3017                  * the radar.
3018                  */
3019                 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
3020
3021         return ret;
3022 }
3023
3024 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3025 {
3026         u32 old_write_domain, old_read_domains;
3027
3028         /* Force a pagefault for domain tracking on next user access */
3029         i915_gem_release_mmap(obj);
3030
3031         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3032                 return;
3033
3034         /* Wait for any direct GTT access to complete */
3035         mb();
3036
3037         old_read_domains = obj->base.read_domains;
3038         old_write_domain = obj->base.write_domain;
3039
3040         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3041         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3042
3043         trace_i915_gem_object_change_domain(obj,
3044                                             old_read_domains,
3045                                             old_write_domain);
3046 }
3047
3048 int i915_vma_unbind(struct i915_vma *vma)
3049 {
3050         struct drm_i915_gem_object *obj = vma->obj;
3051         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3052         int ret;
3053
3054         if (list_empty(&vma->vma_link))
3055                 return 0;
3056
3057         if (!drm_mm_node_allocated(&vma->node)) {
3058                 i915_gem_vma_destroy(vma);
3059                 return 0;
3060         }
3061
3062         if (vma->pin_count)
3063                 return -EBUSY;
3064
3065         BUG_ON(obj->pages == NULL);
3066
3067         ret = i915_gem_object_finish_gpu(obj);
3068         if (ret)
3069                 return ret;
3070         /* Continue on if we fail due to EIO, the GPU is hung so we
3071          * should be safe and we need to cleanup or else we might
3072          * cause memory corruption through use-after-free.
3073          */
3074
3075         /* Throw away the active reference before moving to the unbound list */
3076         i915_gem_object_retire(obj);
3077
3078         if (i915_is_ggtt(vma->vm)) {
3079                 i915_gem_object_finish_gtt(obj);
3080
3081                 /* release the fence reg _after_ flushing */
3082                 ret = i915_gem_object_put_fence(obj);
3083                 if (ret)
3084                         return ret;
3085         }
3086
3087         trace_i915_vma_unbind(vma);
3088
3089         vma->unbind_vma(vma);
3090
3091         list_del_init(&vma->mm_list);
3092         if (i915_is_ggtt(vma->vm))
3093                 obj->map_and_fenceable = false;
3094
3095         drm_mm_remove_node(&vma->node);
3096         i915_gem_vma_destroy(vma);
3097
3098         /* Since the unbound list is global, only move to that list if
3099          * no more VMAs exist. */
3100         if (list_empty(&obj->vma_list)) {
3101                 i915_gem_gtt_finish_object(obj);
3102                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3103         }
3104
3105         /* And finally now the object is completely decoupled from this vma,
3106          * we can drop its hold on the backing storage and allow it to be
3107          * reaped by the shrinker.
3108          */
3109         i915_gem_object_unpin_pages(obj);
3110
3111         return 0;
3112 }
3113
3114 int i915_gpu_idle(struct drm_device *dev)
3115 {
3116         struct drm_i915_private *dev_priv = dev->dev_private;
3117         struct intel_engine_cs *ring;
3118         int ret, i;
3119
3120         /* Flush everything onto the inactive list. */
3121         for_each_ring(ring, dev_priv, i) {
3122                 if (!i915.enable_execlists) {
3123                         ret = i915_switch_context(ring, ring->default_context);
3124                         if (ret)
3125                                 return ret;
3126                 }
3127
3128                 ret = intel_ring_idle(ring);
3129                 if (ret)
3130                         return ret;
3131         }
3132
3133         return 0;
3134 }
3135
3136 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3137                                  struct drm_i915_gem_object *obj)
3138 {
3139         struct drm_i915_private *dev_priv = dev->dev_private;
3140         int fence_reg;
3141         int fence_pitch_shift;
3142
3143         if (INTEL_INFO(dev)->gen >= 6) {
3144                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3145                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3146         } else {
3147                 fence_reg = FENCE_REG_965_0;
3148                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3149         }
3150
3151         fence_reg += reg * 8;
3152
3153         /* To w/a incoherency with non-atomic 64-bit register updates,
3154          * we split the 64-bit update into two 32-bit writes. In order
3155          * for a partial fence not to be evaluated between writes, we
3156          * precede the update with write to turn off the fence register,
3157          * and only enable the fence as the last step.
3158          *
3159          * For extra levels of paranoia, we make sure each step lands
3160          * before applying the next step.
3161          */
3162         I915_WRITE(fence_reg, 0);
3163         POSTING_READ(fence_reg);
3164
3165         if (obj) {
3166                 u32 size = i915_gem_obj_ggtt_size(obj);
3167                 uint64_t val;
3168
3169                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3170                                  0xfffff000) << 32;
3171                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3172                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3173                 if (obj->tiling_mode == I915_TILING_Y)
3174                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3175                 val |= I965_FENCE_REG_VALID;
3176
3177                 I915_WRITE(fence_reg + 4, val >> 32);
3178                 POSTING_READ(fence_reg + 4);
3179
3180                 I915_WRITE(fence_reg + 0, val);
3181                 POSTING_READ(fence_reg);
3182         } else {
3183                 I915_WRITE(fence_reg + 4, 0);
3184                 POSTING_READ(fence_reg + 4);
3185         }
3186 }
3187
3188 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3189                                  struct drm_i915_gem_object *obj)
3190 {
3191         struct drm_i915_private *dev_priv = dev->dev_private;
3192         u32 val;
3193
3194         if (obj) {
3195                 u32 size = i915_gem_obj_ggtt_size(obj);
3196                 int pitch_val;
3197                 int tile_width;
3198
3199                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3200                      (size & -size) != size ||
3201                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3202                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3203                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3204
3205                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3206                         tile_width = 128;
3207                 else
3208                         tile_width = 512;
3209
3210                 /* Note: pitch better be a power of two tile widths */
3211                 pitch_val = obj->stride / tile_width;
3212                 pitch_val = ffs(pitch_val) - 1;
3213
3214                 val = i915_gem_obj_ggtt_offset(obj);
3215                 if (obj->tiling_mode == I915_TILING_Y)
3216                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3217                 val |= I915_FENCE_SIZE_BITS(size);
3218                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3219                 val |= I830_FENCE_REG_VALID;
3220         } else
3221                 val = 0;
3222
3223         if (reg < 8)
3224                 reg = FENCE_REG_830_0 + reg * 4;
3225         else
3226                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3227
3228         I915_WRITE(reg, val);
3229         POSTING_READ(reg);
3230 }
3231
3232 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3233                                 struct drm_i915_gem_object *obj)
3234 {
3235         struct drm_i915_private *dev_priv = dev->dev_private;
3236         uint32_t val;
3237
3238         if (obj) {
3239                 u32 size = i915_gem_obj_ggtt_size(obj);
3240                 uint32_t pitch_val;
3241
3242                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3243                      (size & -size) != size ||
3244                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3245                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3246                      i915_gem_obj_ggtt_offset(obj), size);
3247
3248                 pitch_val = obj->stride / 128;
3249                 pitch_val = ffs(pitch_val) - 1;
3250
3251                 val = i915_gem_obj_ggtt_offset(obj);
3252                 if (obj->tiling_mode == I915_TILING_Y)
3253                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3254                 val |= I830_FENCE_SIZE_BITS(size);
3255                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3256                 val |= I830_FENCE_REG_VALID;
3257         } else
3258                 val = 0;
3259
3260         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3261         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3262 }
3263
3264 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3265 {
3266         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3267 }
3268
3269 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3270                                  struct drm_i915_gem_object *obj)
3271 {
3272         struct drm_i915_private *dev_priv = dev->dev_private;
3273
3274         /* Ensure that all CPU reads are completed before installing a fence
3275          * and all writes before removing the fence.
3276          */
3277         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3278                 mb();
3279
3280         WARN(obj && (!obj->stride || !obj->tiling_mode),
3281              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3282              obj->stride, obj->tiling_mode);
3283
3284         switch (INTEL_INFO(dev)->gen) {
3285         case 9:
3286         case 8:
3287         case 7:
3288         case 6:
3289         case 5:
3290         case 4: i965_write_fence_reg(dev, reg, obj); break;
3291         case 3: i915_write_fence_reg(dev, reg, obj); break;
3292         case 2: i830_write_fence_reg(dev, reg, obj); break;
3293         default: BUG();
3294         }
3295
3296         /* And similarly be paranoid that no direct access to this region
3297          * is reordered to before the fence is installed.
3298          */
3299         if (i915_gem_object_needs_mb(obj))
3300                 mb();
3301 }
3302
3303 static inline int fence_number(struct drm_i915_private *dev_priv,
3304                                struct drm_i915_fence_reg *fence)
3305 {
3306         return fence - dev_priv->fence_regs;
3307 }
3308
3309 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3310                                          struct drm_i915_fence_reg *fence,
3311                                          bool enable)
3312 {
3313         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3314         int reg = fence_number(dev_priv, fence);
3315
3316         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3317
3318         if (enable) {
3319                 obj->fence_reg = reg;
3320                 fence->obj = obj;
3321                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3322         } else {
3323                 obj->fence_reg = I915_FENCE_REG_NONE;
3324                 fence->obj = NULL;
3325                 list_del_init(&fence->lru_list);
3326         }
3327         obj->fence_dirty = false;
3328 }
3329
3330 static int
3331 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3332 {
3333         if (obj->last_fenced_seqno) {
3334                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3335                 if (ret)
3336                         return ret;
3337
3338                 obj->last_fenced_seqno = 0;
3339         }
3340
3341         return 0;
3342 }
3343
3344 int
3345 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3346 {
3347         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3348         struct drm_i915_fence_reg *fence;
3349         int ret;
3350
3351         ret = i915_gem_object_wait_fence(obj);
3352         if (ret)
3353                 return ret;
3354
3355         if (obj->fence_reg == I915_FENCE_REG_NONE)
3356                 return 0;
3357
3358         fence = &dev_priv->fence_regs[obj->fence_reg];
3359
3360         if (WARN_ON(fence->pin_count))
3361                 return -EBUSY;
3362
3363         i915_gem_object_fence_lost(obj);
3364         i915_gem_object_update_fence(obj, fence, false);
3365
3366         return 0;
3367 }
3368
3369 static struct drm_i915_fence_reg *
3370 i915_find_fence_reg(struct drm_device *dev)
3371 {
3372         struct drm_i915_private *dev_priv = dev->dev_private;
3373         struct drm_i915_fence_reg *reg, *avail;
3374         int i;
3375
3376         /* First try to find a free reg */
3377         avail = NULL;
3378         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3379                 reg = &dev_priv->fence_regs[i];
3380                 if (!reg->obj)
3381                         return reg;
3382
3383                 if (!reg->pin_count)
3384                         avail = reg;
3385         }
3386
3387         if (avail == NULL)
3388                 goto deadlock;
3389
3390         /* None available, try to steal one or wait for a user to finish */
3391         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3392                 if (reg->pin_count)
3393                         continue;
3394
3395                 return reg;
3396         }
3397
3398 deadlock:
3399         /* Wait for completion of pending flips which consume fences */
3400         if (intel_has_pending_fb_unpin(dev))
3401                 return ERR_PTR(-EAGAIN);
3402
3403         return ERR_PTR(-EDEADLK);
3404 }
3405
3406 /**
3407  * i915_gem_object_get_fence - set up fencing for an object
3408  * @obj: object to map through a fence reg
3409  *
3410  * When mapping objects through the GTT, userspace wants to be able to write
3411  * to them without having to worry about swizzling if the object is tiled.
3412  * This function walks the fence regs looking for a free one for @obj,
3413  * stealing one if it can't find any.
3414  *
3415  * It then sets up the reg based on the object's properties: address, pitch
3416  * and tiling format.
3417  *
3418  * For an untiled surface, this removes any existing fence.
3419  */
3420 int
3421 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3422 {
3423         struct drm_device *dev = obj->base.dev;
3424         struct drm_i915_private *dev_priv = dev->dev_private;
3425         bool enable = obj->tiling_mode != I915_TILING_NONE;
3426         struct drm_i915_fence_reg *reg;
3427         int ret;
3428
3429         /* Have we updated the tiling parameters upon the object and so
3430          * will need to serialise the write to the associated fence register?
3431          */
3432         if (obj->fence_dirty) {
3433                 ret = i915_gem_object_wait_fence(obj);
3434                 if (ret)
3435                         return ret;
3436         }
3437
3438         /* Just update our place in the LRU if our fence is getting reused. */
3439         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3440                 reg = &dev_priv->fence_regs[obj->fence_reg];
3441                 if (!obj->fence_dirty) {
3442                         list_move_tail(&reg->lru_list,
3443                                        &dev_priv->mm.fence_list);
3444                         return 0;
3445                 }
3446         } else if (enable) {
3447                 if (WARN_ON(!obj->map_and_fenceable))
3448                         return -EINVAL;
3449
3450                 reg = i915_find_fence_reg(dev);
3451                 if (IS_ERR(reg))
3452                         return PTR_ERR(reg);
3453
3454                 if (reg->obj) {
3455                         struct drm_i915_gem_object *old = reg->obj;
3456
3457                         ret = i915_gem_object_wait_fence(old);
3458                         if (ret)
3459                                 return ret;
3460
3461                         i915_gem_object_fence_lost(old);
3462                 }
3463         } else
3464                 return 0;
3465
3466         i915_gem_object_update_fence(obj, reg, enable);
3467
3468         return 0;
3469 }
3470
3471 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3472                                      unsigned long cache_level)
3473 {
3474         struct drm_mm_node *gtt_space = &vma->node;
3475         struct drm_mm_node *other;
3476
3477         /*
3478          * On some machines we have to be careful when putting differing types
3479          * of snoopable memory together to avoid the prefetcher crossing memory
3480          * domains and dying. During vm initialisation, we decide whether or not
3481          * these constraints apply and set the drm_mm.color_adjust
3482          * appropriately.
3483          */
3484         if (vma->vm->mm.color_adjust == NULL)
3485                 return true;
3486
3487         if (!drm_mm_node_allocated(gtt_space))
3488                 return true;
3489
3490         if (list_empty(&gtt_space->node_list))
3491                 return true;
3492
3493         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3494         if (other->allocated && !other->hole_follows && other->color != cache_level)
3495                 return false;
3496
3497         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3498         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3499                 return false;
3500
3501         return true;
3502 }
3503
3504 /**
3505  * Finds free space in the GTT aperture and binds the object there.
3506  */
3507 static struct i915_vma *
3508 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3509                            struct i915_address_space *vm,
3510                            unsigned alignment,
3511                            uint64_t flags)
3512 {
3513         struct drm_device *dev = obj->base.dev;
3514         struct drm_i915_private *dev_priv = dev->dev_private;
3515         u32 size, fence_size, fence_alignment, unfenced_alignment;
3516         unsigned long start =
3517                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3518         unsigned long end =
3519                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3520         struct i915_vma *vma;
3521         int ret;
3522
3523         fence_size = i915_gem_get_gtt_size(dev,
3524                                            obj->base.size,
3525                                            obj->tiling_mode);
3526         fence_alignment = i915_gem_get_gtt_alignment(dev,
3527                                                      obj->base.size,
3528                                                      obj->tiling_mode, true);
3529         unfenced_alignment =
3530                 i915_gem_get_gtt_alignment(dev,
3531                                            obj->base.size,
3532                                            obj->tiling_mode, false);
3533
3534         if (alignment == 0)
3535                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3536                                                 unfenced_alignment;
3537         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3538                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3539                 return ERR_PTR(-EINVAL);
3540         }
3541
3542         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3543
3544         /* If the object is bigger than the entire aperture, reject it early
3545          * before evicting everything in a vain attempt to find space.
3546          */
3547         if (obj->base.size > end) {
3548                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3549                           obj->base.size,
3550                           flags & PIN_MAPPABLE ? "mappable" : "total",
3551                           end);
3552                 return ERR_PTR(-E2BIG);
3553         }
3554
3555         ret = i915_gem_object_get_pages(obj);
3556         if (ret)
3557                 return ERR_PTR(ret);
3558
3559         i915_gem_object_pin_pages(obj);
3560
3561         vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3562         if (IS_ERR(vma))
3563                 goto err_unpin;
3564
3565 search_free:
3566         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3567                                                   size, alignment,
3568                                                   obj->cache_level,
3569                                                   start, end,
3570                                                   DRM_MM_SEARCH_DEFAULT,
3571                                                   DRM_MM_CREATE_DEFAULT);
3572         if (ret) {
3573                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3574                                                obj->cache_level,
3575                                                start, end,
3576                                                flags);
3577                 if (ret == 0)
3578                         goto search_free;
3579
3580                 goto err_free_vma;
3581         }
3582         if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3583                 ret = -EINVAL;
3584                 goto err_remove_node;
3585         }
3586
3587         ret = i915_gem_gtt_prepare_object(obj);
3588         if (ret)
3589                 goto err_remove_node;
3590
3591         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3592         list_add_tail(&vma->mm_list, &vm->inactive_list);
3593
3594         trace_i915_vma_bind(vma, flags);
3595         vma->bind_vma(vma, obj->cache_level,
3596                       flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3597
3598         return vma;
3599
3600 err_remove_node:
3601         drm_mm_remove_node(&vma->node);
3602 err_free_vma:
3603         i915_gem_vma_destroy(vma);
3604         vma = ERR_PTR(ret);
3605 err_unpin:
3606         i915_gem_object_unpin_pages(obj);
3607         return vma;
3608 }
3609
3610 bool
3611 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3612                         bool force)
3613 {
3614         /* If we don't have a page list set up, then we're not pinned
3615          * to GPU, and we can ignore the cache flush because it'll happen
3616          * again at bind time.
3617          */
3618         if (obj->pages == NULL)
3619                 return false;
3620
3621         /*
3622          * Stolen memory is always coherent with the GPU as it is explicitly
3623          * marked as wc by the system, or the system is cache-coherent.
3624          */
3625         if (obj->stolen || obj->phys_handle)
3626                 return false;
3627
3628         /* If the GPU is snooping the contents of the CPU cache,
3629          * we do not need to manually clear the CPU cache lines.  However,
3630          * the caches are only snooped when the render cache is
3631          * flushed/invalidated.  As we always have to emit invalidations
3632          * and flushes when moving into and out of the RENDER domain, correct
3633          * snooping behaviour occurs naturally as the result of our domain
3634          * tracking.
3635          */
3636         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3637                 return false;
3638
3639         trace_i915_gem_object_clflush(obj);
3640         drm_clflush_sg(obj->pages);
3641
3642         return true;
3643 }
3644
3645 /** Flushes the GTT write domain for the object if it's dirty. */
3646 static void
3647 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3648 {
3649         uint32_t old_write_domain;
3650
3651         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3652                 return;
3653
3654         /* No actual flushing is required for the GTT write domain.  Writes
3655          * to it immediately go to main memory as far as we know, so there's
3656          * no chipset flush.  It also doesn't land in render cache.
3657          *
3658          * However, we do have to enforce the order so that all writes through
3659          * the GTT land before any writes to the device, such as updates to
3660          * the GATT itself.
3661          */
3662         wmb();
3663
3664         old_write_domain = obj->base.write_domain;
3665         obj->base.write_domain = 0;
3666
3667         intel_fb_obj_flush(obj, false);
3668
3669         trace_i915_gem_object_change_domain(obj,
3670                                             obj->base.read_domains,
3671                                             old_write_domain);
3672 }
3673
3674 /** Flushes the CPU write domain for the object if it's dirty. */
3675 static void
3676 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3677                                        bool force)
3678 {
3679         uint32_t old_write_domain;
3680
3681         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3682                 return;
3683
3684         if (i915_gem_clflush_object(obj, force))
3685                 i915_gem_chipset_flush(obj->base.dev);
3686
3687         old_write_domain = obj->base.write_domain;
3688         obj->base.write_domain = 0;
3689
3690         intel_fb_obj_flush(obj, false);
3691
3692         trace_i915_gem_object_change_domain(obj,
3693                                             obj->base.read_domains,
3694                                             old_write_domain);
3695 }
3696
3697 /**
3698  * Moves a single object to the GTT read, and possibly write domain.
3699  *
3700  * This function returns when the move is complete, including waiting on
3701  * flushes to occur.
3702  */
3703 int
3704 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3705 {
3706         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3707         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3708         uint32_t old_write_domain, old_read_domains;
3709         int ret;
3710
3711         /* Not valid to be called on unbound objects. */
3712         if (vma == NULL)
3713                 return -EINVAL;
3714
3715         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3716                 return 0;
3717
3718         ret = i915_gem_object_wait_rendering(obj, !write);
3719         if (ret)
3720                 return ret;
3721
3722         i915_gem_object_retire(obj);
3723         i915_gem_object_flush_cpu_write_domain(obj, false);
3724
3725         /* Serialise direct access to this object with the barriers for
3726          * coherent writes from the GPU, by effectively invalidating the
3727          * GTT domain upon first access.
3728          */
3729         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3730                 mb();
3731
3732         old_write_domain = obj->base.write_domain;
3733         old_read_domains = obj->base.read_domains;
3734
3735         /* It should now be out of any other write domains, and we can update
3736          * the domain values for our changes.
3737          */
3738         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3739         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3740         if (write) {
3741                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3742                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3743                 obj->dirty = 1;
3744         }
3745
3746         if (write)
3747                 intel_fb_obj_invalidate(obj, NULL);
3748
3749         trace_i915_gem_object_change_domain(obj,
3750                                             old_read_domains,
3751                                             old_write_domain);
3752
3753         /* And bump the LRU for this access */
3754         if (i915_gem_object_is_inactive(obj))
3755                 list_move_tail(&vma->mm_list,
3756                                &dev_priv->gtt.base.inactive_list);
3757
3758         return 0;
3759 }
3760
3761 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3762                                     enum i915_cache_level cache_level)
3763 {
3764         struct drm_device *dev = obj->base.dev;
3765         struct i915_vma *vma, *next;
3766         int ret;
3767
3768         if (obj->cache_level == cache_level)
3769                 return 0;
3770
3771         if (i915_gem_obj_is_pinned(obj)) {
3772                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3773                 return -EBUSY;
3774         }
3775
3776         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3777                 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3778                         ret = i915_vma_unbind(vma);
3779                         if (ret)
3780                                 return ret;
3781                 }
3782         }
3783
3784         if (i915_gem_obj_bound_any(obj)) {
3785                 ret = i915_gem_object_finish_gpu(obj);
3786                 if (ret)
3787                         return ret;
3788
3789                 i915_gem_object_finish_gtt(obj);
3790
3791                 /* Before SandyBridge, you could not use tiling or fence
3792                  * registers with snooped memory, so relinquish any fences
3793                  * currently pointing to our region in the aperture.
3794                  */
3795                 if (INTEL_INFO(dev)->gen < 6) {
3796                         ret = i915_gem_object_put_fence(obj);
3797                         if (ret)
3798                                 return ret;
3799                 }
3800
3801                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3802                         if (drm_mm_node_allocated(&vma->node))
3803                                 vma->bind_vma(vma, cache_level,
3804                                                 vma->bound & GLOBAL_BIND);
3805         }
3806
3807         list_for_each_entry(vma, &obj->vma_list, vma_link)
3808                 vma->node.color = cache_level;
3809         obj->cache_level = cache_level;
3810
3811         if (cpu_write_needs_clflush(obj)) {
3812                 u32 old_read_domains, old_write_domain;
3813
3814                 /* If we're coming from LLC cached, then we haven't
3815                  * actually been tracking whether the data is in the
3816                  * CPU cache or not, since we only allow one bit set
3817                  * in obj->write_domain and have been skipping the clflushes.
3818                  * Just set it to the CPU cache for now.
3819                  */
3820                 i915_gem_object_retire(obj);
3821                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3822
3823                 old_read_domains = obj->base.read_domains;
3824                 old_write_domain = obj->base.write_domain;
3825
3826                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3827                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3828
3829                 trace_i915_gem_object_change_domain(obj,
3830                                                     old_read_domains,
3831                                                     old_write_domain);
3832         }
3833
3834         return 0;
3835 }
3836
3837 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3838                                struct drm_file *file)
3839 {
3840         struct drm_i915_gem_caching *args = data;
3841         struct drm_i915_gem_object *obj;
3842         int ret;
3843
3844         ret = i915_mutex_lock_interruptible(dev);
3845         if (ret)
3846                 return ret;
3847
3848         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3849         if (&obj->base == NULL) {
3850                 ret = -ENOENT;
3851                 goto unlock;
3852         }
3853
3854         switch (obj->cache_level) {
3855         case I915_CACHE_LLC:
3856         case I915_CACHE_L3_LLC:
3857                 args->caching = I915_CACHING_CACHED;
3858                 break;
3859
3860         case I915_CACHE_WT:
3861                 args->caching = I915_CACHING_DISPLAY;
3862                 break;
3863
3864         default:
3865                 args->caching = I915_CACHING_NONE;
3866                 break;
3867         }
3868
3869         drm_gem_object_unreference(&obj->base);
3870 unlock:
3871         mutex_unlock(&dev->struct_mutex);
3872         return ret;
3873 }
3874
3875 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3876                                struct drm_file *file)
3877 {
3878         struct drm_i915_gem_caching *args = data;
3879         struct drm_i915_gem_object *obj;
3880         enum i915_cache_level level;
3881         int ret;
3882
3883         switch (args->caching) {
3884         case I915_CACHING_NONE:
3885                 level = I915_CACHE_NONE;
3886                 break;
3887         case I915_CACHING_CACHED:
3888                 level = I915_CACHE_LLC;
3889                 break;
3890         case I915_CACHING_DISPLAY:
3891                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3892                 break;
3893         default:
3894                 return -EINVAL;
3895         }
3896
3897         ret = i915_mutex_lock_interruptible(dev);
3898         if (ret)
3899                 return ret;
3900
3901         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3902         if (&obj->base == NULL) {
3903                 ret = -ENOENT;
3904                 goto unlock;
3905         }
3906
3907         ret = i915_gem_object_set_cache_level(obj, level);
3908
3909         drm_gem_object_unreference(&obj->base);
3910 unlock:
3911         mutex_unlock(&dev->struct_mutex);
3912         return ret;
3913 }
3914
3915 static bool is_pin_display(struct drm_i915_gem_object *obj)
3916 {
3917         struct i915_vma *vma;
3918
3919         vma = i915_gem_obj_to_ggtt(obj);
3920         if (!vma)
3921                 return false;
3922
3923         /* There are 3 sources that pin objects:
3924          *   1. The display engine (scanouts, sprites, cursors);
3925          *   2. Reservations for execbuffer;
3926          *   3. The user.
3927          *
3928          * We can ignore reservations as we hold the struct_mutex and
3929          * are only called outside of the reservation path.  The user
3930          * can only increment pin_count once, and so if after
3931          * subtracting the potential reference by the user, any pin_count
3932          * remains, it must be due to another use by the display engine.
3933          */
3934         return vma->pin_count - !!obj->user_pin_count;
3935 }
3936
3937 /*
3938  * Prepare buffer for display plane (scanout, cursors, etc).
3939  * Can be called from an uninterruptible phase (modesetting) and allows
3940  * any flushes to be pipelined (for pageflips).
3941  */
3942 int
3943 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3944                                      u32 alignment,
3945                                      struct intel_engine_cs *pipelined)
3946 {
3947         u32 old_read_domains, old_write_domain;
3948         bool was_pin_display;
3949         int ret;
3950
3951         if (pipelined != obj->ring) {
3952                 ret = i915_gem_object_sync(obj, pipelined);
3953                 if (ret)
3954                         return ret;
3955         }
3956
3957         /* Mark the pin_display early so that we account for the
3958          * display coherency whilst setting up the cache domains.
3959          */
3960         was_pin_display = obj->pin_display;
3961         obj->pin_display = true;
3962
3963         /* The display engine is not coherent with the LLC cache on gen6.  As
3964          * a result, we make sure that the pinning that is about to occur is
3965          * done with uncached PTEs. This is lowest common denominator for all
3966          * chipsets.
3967          *
3968          * However for gen6+, we could do better by using the GFDT bit instead
3969          * of uncaching, which would allow us to flush all the LLC-cached data
3970          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3971          */
3972         ret = i915_gem_object_set_cache_level(obj,
3973                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3974         if (ret)
3975                 goto err_unpin_display;
3976
3977         /* As the user may map the buffer once pinned in the display plane
3978          * (e.g. libkms for the bootup splash), we have to ensure that we
3979          * always use map_and_fenceable for all scanout buffers.
3980          */
3981         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3982         if (ret)
3983                 goto err_unpin_display;
3984
3985         i915_gem_object_flush_cpu_write_domain(obj, true);
3986
3987         old_write_domain = obj->base.write_domain;
3988         old_read_domains = obj->base.read_domains;
3989
3990         /* It should now be out of any other write domains, and we can update
3991          * the domain values for our changes.
3992          */
3993         obj->base.write_domain = 0;
3994         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3995
3996         trace_i915_gem_object_change_domain(obj,
3997                                             old_read_domains,
3998                                             old_write_domain);
3999
4000         return 0;
4001
4002 err_unpin_display:
4003         WARN_ON(was_pin_display != is_pin_display(obj));
4004         obj->pin_display = was_pin_display;
4005         return ret;
4006 }
4007
4008 void
4009 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
4010 {
4011         i915_gem_object_ggtt_unpin(obj);
4012         obj->pin_display = is_pin_display(obj);
4013 }
4014
4015 int
4016 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4017 {
4018         int ret;
4019
4020         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4021                 return 0;
4022
4023         ret = i915_gem_object_wait_rendering(obj, false);
4024         if (ret)
4025                 return ret;
4026
4027         /* Ensure that we invalidate the GPU's caches and TLBs. */
4028         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4029         return 0;
4030 }
4031
4032 /**
4033  * Moves a single object to the CPU read, and possibly write domain.
4034  *
4035  * This function returns when the move is complete, including waiting on
4036  * flushes to occur.
4037  */
4038 int
4039 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4040 {
4041         uint32_t old_write_domain, old_read_domains;
4042         int ret;
4043
4044         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4045                 return 0;
4046
4047         ret = i915_gem_object_wait_rendering(obj, !write);
4048         if (ret)
4049                 return ret;
4050
4051         i915_gem_object_retire(obj);
4052         i915_gem_object_flush_gtt_write_domain(obj);
4053
4054         old_write_domain = obj->base.write_domain;
4055         old_read_domains = obj->base.read_domains;
4056
4057         /* Flush the CPU cache if it's still invalid. */
4058         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4059                 i915_gem_clflush_object(obj, false);
4060
4061                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4062         }
4063
4064         /* It should now be out of any other write domains, and we can update
4065          * the domain values for our changes.
4066          */
4067         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4068
4069         /* If we're writing through the CPU, then the GPU read domains will
4070          * need to be invalidated at next use.
4071          */
4072         if (write) {
4073                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4074                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4075         }
4076
4077         if (write)
4078                 intel_fb_obj_invalidate(obj, NULL);
4079
4080         trace_i915_gem_object_change_domain(obj,
4081                                             old_read_domains,
4082                                             old_write_domain);
4083
4084         return 0;
4085 }
4086
4087 /* Throttle our rendering by waiting until the ring has completed our requests
4088  * emitted over 20 msec ago.
4089  *
4090  * Note that if we were to use the current jiffies each time around the loop,
4091  * we wouldn't escape the function with any frames outstanding if the time to
4092  * render a frame was over 20ms.
4093  *
4094  * This should get us reasonable parallelism between CPU and GPU but also
4095  * relatively low latency when blocking on a particular request to finish.
4096  */
4097 static int
4098 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4099 {
4100         struct drm_i915_private *dev_priv = dev->dev_private;
4101         struct drm_i915_file_private *file_priv = file->driver_priv;
4102         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4103         struct drm_i915_gem_request *request;
4104         struct intel_engine_cs *ring = NULL;
4105         unsigned reset_counter;
4106         u32 seqno = 0;
4107         int ret;
4108
4109         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4110         if (ret)
4111                 return ret;
4112
4113         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4114         if (ret)
4115                 return ret;
4116
4117         spin_lock(&file_priv->mm.lock);
4118         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4119                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4120                         break;
4121
4122                 ring = request->ring;
4123                 seqno = request->seqno;
4124         }
4125         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4126         spin_unlock(&file_priv->mm.lock);
4127
4128         if (seqno == 0)
4129                 return 0;
4130
4131         ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4132         if (ret == 0)
4133                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4134
4135         return ret;
4136 }
4137
4138 static bool
4139 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4140 {
4141         struct drm_i915_gem_object *obj = vma->obj;
4142
4143         if (alignment &&
4144             vma->node.start & (alignment - 1))
4145                 return true;
4146
4147         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4148                 return true;
4149
4150         if (flags & PIN_OFFSET_BIAS &&
4151             vma->node.start < (flags & PIN_OFFSET_MASK))
4152                 return true;
4153
4154         return false;
4155 }
4156
4157 int
4158 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4159                     struct i915_address_space *vm,
4160                     uint32_t alignment,
4161                     uint64_t flags)
4162 {
4163         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4164         struct i915_vma *vma;
4165         unsigned bound;
4166         int ret;
4167
4168         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4169                 return -ENODEV;
4170
4171         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4172                 return -EINVAL;
4173
4174         if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4175                 return -EINVAL;
4176
4177         vma = i915_gem_obj_to_vma(obj, vm);
4178         if (vma) {
4179                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4180                         return -EBUSY;
4181
4182                 if (i915_vma_misplaced(vma, alignment, flags)) {
4183                         WARN(vma->pin_count,
4184                              "bo is already pinned with incorrect alignment:"
4185                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4186                              " obj->map_and_fenceable=%d\n",
4187                              i915_gem_obj_offset(obj, vm), alignment,
4188                              !!(flags & PIN_MAPPABLE),
4189                              obj->map_and_fenceable);
4190                         ret = i915_vma_unbind(vma);
4191                         if (ret)
4192                                 return ret;
4193
4194                         vma = NULL;
4195                 }
4196         }
4197
4198         bound = vma ? vma->bound : 0;
4199         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4200                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4201                 if (IS_ERR(vma))
4202                         return PTR_ERR(vma);
4203         }
4204
4205         if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND))
4206                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4207
4208         if ((bound ^ vma->bound) & GLOBAL_BIND) {
4209                 bool mappable, fenceable;
4210                 u32 fence_size, fence_alignment;
4211
4212                 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4213                                                    obj->base.size,
4214                                                    obj->tiling_mode);
4215                 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4216                                                              obj->base.size,
4217                                                              obj->tiling_mode,
4218                                                              true);
4219
4220                 fenceable = (vma->node.size == fence_size &&
4221                              (vma->node.start & (fence_alignment - 1)) == 0);
4222
4223                 mappable = (vma->node.start + obj->base.size <=
4224                             dev_priv->gtt.mappable_end);
4225
4226                 obj->map_and_fenceable = mappable && fenceable;
4227         }
4228
4229         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4230
4231         vma->pin_count++;
4232         if (flags & PIN_MAPPABLE)
4233                 obj->pin_mappable |= true;
4234
4235         return 0;
4236 }
4237
4238 void
4239 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4240 {
4241         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4242
4243         BUG_ON(!vma);
4244         BUG_ON(vma->pin_count == 0);
4245         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4246
4247         if (--vma->pin_count == 0)
4248                 obj->pin_mappable = false;
4249 }
4250
4251 bool
4252 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4253 {
4254         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4255                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4256                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4257
4258                 WARN_ON(!ggtt_vma ||
4259                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4260                         ggtt_vma->pin_count);
4261                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4262                 return true;
4263         } else
4264                 return false;
4265 }
4266
4267 void
4268 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4269 {
4270         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4271                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4272                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4273                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4274         }
4275 }
4276
4277 int
4278 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4279                    struct drm_file *file)
4280 {
4281         struct drm_i915_gem_pin *args = data;
4282         struct drm_i915_gem_object *obj;
4283         int ret;
4284
4285         if (drm_core_check_feature(dev, DRIVER_MODESET))
4286                 return -ENODEV;
4287
4288         ret = i915_mutex_lock_interruptible(dev);
4289         if (ret)
4290                 return ret;
4291
4292         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4293         if (&obj->base == NULL) {
4294                 ret = -ENOENT;
4295                 goto unlock;
4296         }
4297
4298         if (obj->madv != I915_MADV_WILLNEED) {
4299                 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4300                 ret = -EFAULT;
4301                 goto out;
4302         }
4303
4304         if (obj->pin_filp != NULL && obj->pin_filp != file) {
4305                 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4306                           args->handle);
4307                 ret = -EINVAL;
4308                 goto out;
4309         }
4310
4311         if (obj->user_pin_count == ULONG_MAX) {
4312                 ret = -EBUSY;
4313                 goto out;
4314         }
4315
4316         if (obj->user_pin_count == 0) {
4317                 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4318                 if (ret)
4319                         goto out;
4320         }
4321
4322         obj->user_pin_count++;
4323         obj->pin_filp = file;
4324
4325         args->offset = i915_gem_obj_ggtt_offset(obj);
4326 out:
4327         drm_gem_object_unreference(&obj->base);
4328 unlock:
4329         mutex_unlock(&dev->struct_mutex);
4330         return ret;
4331 }
4332
4333 int
4334 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4335                      struct drm_file *file)
4336 {
4337         struct drm_i915_gem_pin *args = data;
4338         struct drm_i915_gem_object *obj;
4339         int ret;
4340
4341         if (drm_core_check_feature(dev, DRIVER_MODESET))
4342                 return -ENODEV;
4343
4344         ret = i915_mutex_lock_interruptible(dev);
4345         if (ret)
4346                 return ret;
4347
4348         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4349         if (&obj->base == NULL) {
4350                 ret = -ENOENT;
4351                 goto unlock;
4352         }
4353
4354         if (obj->pin_filp != file) {
4355                 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4356                           args->handle);
4357                 ret = -EINVAL;
4358                 goto out;
4359         }
4360         obj->user_pin_count--;
4361         if (obj->user_pin_count == 0) {
4362                 obj->pin_filp = NULL;
4363                 i915_gem_object_ggtt_unpin(obj);
4364         }
4365
4366 out:
4367         drm_gem_object_unreference(&obj->base);
4368 unlock:
4369         mutex_unlock(&dev->struct_mutex);
4370         return ret;
4371 }
4372
4373 int
4374 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4375                     struct drm_file *file)
4376 {
4377         struct drm_i915_gem_busy *args = data;
4378         struct drm_i915_gem_object *obj;
4379         int ret;
4380
4381         ret = i915_mutex_lock_interruptible(dev);
4382         if (ret)
4383                 return ret;
4384
4385         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4386         if (&obj->base == NULL) {
4387                 ret = -ENOENT;
4388                 goto unlock;
4389         }
4390
4391         /* Count all active objects as busy, even if they are currently not used
4392          * by the gpu. Users of this interface expect objects to eventually
4393          * become non-busy without any further actions, therefore emit any
4394          * necessary flushes here.
4395          */
4396         ret = i915_gem_object_flush_active(obj);
4397
4398         args->busy = obj->active;
4399         if (obj->ring) {
4400                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4401                 args->busy |= intel_ring_flag(obj->ring) << 16;
4402         }
4403
4404         drm_gem_object_unreference(&obj->base);
4405 unlock:
4406         mutex_unlock(&dev->struct_mutex);
4407         return ret;
4408 }
4409
4410 int
4411 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4412                         struct drm_file *file_priv)
4413 {
4414         return i915_gem_ring_throttle(dev, file_priv);
4415 }
4416
4417 int
4418 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4419                        struct drm_file *file_priv)
4420 {
4421         struct drm_i915_private *dev_priv = dev->dev_private;
4422         struct drm_i915_gem_madvise *args = data;
4423         struct drm_i915_gem_object *obj;
4424         int ret;
4425
4426         switch (args->madv) {
4427         case I915_MADV_DONTNEED:
4428         case I915_MADV_WILLNEED:
4429             break;
4430         default:
4431             return -EINVAL;
4432         }
4433
4434         ret = i915_mutex_lock_interruptible(dev);
4435         if (ret)
4436                 return ret;
4437
4438         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4439         if (&obj->base == NULL) {
4440                 ret = -ENOENT;
4441                 goto unlock;
4442         }
4443
4444         if (i915_gem_obj_is_pinned(obj)) {
4445                 ret = -EINVAL;
4446                 goto out;
4447         }
4448
4449         if (obj->pages &&
4450             obj->tiling_mode != I915_TILING_NONE &&
4451             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4452                 if (obj->madv == I915_MADV_WILLNEED)
4453                         i915_gem_object_unpin_pages(obj);
4454                 if (args->madv == I915_MADV_WILLNEED)
4455                         i915_gem_object_pin_pages(obj);
4456         }
4457
4458         if (obj->madv != __I915_MADV_PURGED)
4459                 obj->madv = args->madv;
4460
4461         /* if the object is no longer attached, discard its backing storage */
4462         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4463                 i915_gem_object_truncate(obj);
4464
4465         args->retained = obj->madv != __I915_MADV_PURGED;
4466
4467 out:
4468         drm_gem_object_unreference(&obj->base);
4469 unlock:
4470         mutex_unlock(&dev->struct_mutex);
4471         return ret;
4472 }
4473
4474 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4475                           const struct drm_i915_gem_object_ops *ops)
4476 {
4477         INIT_LIST_HEAD(&obj->global_list);
4478         INIT_LIST_HEAD(&obj->ring_list);
4479         INIT_LIST_HEAD(&obj->obj_exec_link);
4480         INIT_LIST_HEAD(&obj->vma_list);
4481
4482         obj->ops = ops;
4483
4484         obj->fence_reg = I915_FENCE_REG_NONE;
4485         obj->madv = I915_MADV_WILLNEED;
4486
4487         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4488 }
4489
4490 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4491         .get_pages = i915_gem_object_get_pages_gtt,
4492         .put_pages = i915_gem_object_put_pages_gtt,
4493 };
4494
4495 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4496                                                   size_t size)
4497 {
4498         struct drm_i915_gem_object *obj;
4499         struct address_space *mapping;
4500         gfp_t mask;
4501
4502         obj = i915_gem_object_alloc(dev);
4503         if (obj == NULL)
4504                 return NULL;
4505
4506         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4507                 i915_gem_object_free(obj);
4508                 return NULL;
4509         }
4510
4511         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4512         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4513                 /* 965gm cannot relocate objects above 4GiB. */
4514                 mask &= ~__GFP_HIGHMEM;
4515                 mask |= __GFP_DMA32;
4516         }
4517
4518         mapping = file_inode(obj->base.filp)->i_mapping;
4519         mapping_set_gfp_mask(mapping, mask);
4520
4521         i915_gem_object_init(obj, &i915_gem_object_ops);
4522
4523         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4524         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4525
4526         if (HAS_LLC(dev)) {
4527                 /* On some devices, we can have the GPU use the LLC (the CPU
4528                  * cache) for about a 10% performance improvement
4529                  * compared to uncached.  Graphics requests other than
4530                  * display scanout are coherent with the CPU in
4531                  * accessing this cache.  This means in this mode we
4532                  * don't need to clflush on the CPU side, and on the
4533                  * GPU side we only need to flush internal caches to
4534                  * get data visible to the CPU.
4535                  *
4536                  * However, we maintain the display planes as UC, and so
4537                  * need to rebind when first used as such.
4538                  */
4539                 obj->cache_level = I915_CACHE_LLC;
4540         } else
4541                 obj->cache_level = I915_CACHE_NONE;
4542
4543         trace_i915_gem_object_create(obj);
4544
4545         return obj;
4546 }
4547
4548 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4549 {
4550         /* If we are the last user of the backing storage (be it shmemfs
4551          * pages or stolen etc), we know that the pages are going to be
4552          * immediately released. In this case, we can then skip copying
4553          * back the contents from the GPU.
4554          */
4555
4556         if (obj->madv != I915_MADV_WILLNEED)
4557                 return false;
4558
4559         if (obj->base.filp == NULL)
4560                 return true;
4561
4562         /* At first glance, this looks racy, but then again so would be
4563          * userspace racing mmap against close. However, the first external
4564          * reference to the filp can only be obtained through the
4565          * i915_gem_mmap_ioctl() which safeguards us against the user
4566          * acquiring such a reference whilst we are in the middle of
4567          * freeing the object.
4568          */
4569         return atomic_long_read(&obj->base.filp->f_count) == 1;
4570 }
4571
4572 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4573 {
4574         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4575         struct drm_device *dev = obj->base.dev;
4576         struct drm_i915_private *dev_priv = dev->dev_private;
4577         struct i915_vma *vma, *next;
4578
4579         intel_runtime_pm_get(dev_priv);
4580
4581         trace_i915_gem_object_destroy(obj);
4582
4583         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4584                 int ret;
4585
4586                 vma->pin_count = 0;
4587                 ret = i915_vma_unbind(vma);
4588                 if (WARN_ON(ret == -ERESTARTSYS)) {
4589                         bool was_interruptible;
4590
4591                         was_interruptible = dev_priv->mm.interruptible;
4592                         dev_priv->mm.interruptible = false;
4593
4594                         WARN_ON(i915_vma_unbind(vma));
4595
4596                         dev_priv->mm.interruptible = was_interruptible;
4597                 }
4598         }
4599
4600         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4601          * before progressing. */
4602         if (obj->stolen)
4603                 i915_gem_object_unpin_pages(obj);
4604
4605         WARN_ON(obj->frontbuffer_bits);
4606
4607         if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4608             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4609             obj->tiling_mode != I915_TILING_NONE)
4610                 i915_gem_object_unpin_pages(obj);
4611
4612         if (WARN_ON(obj->pages_pin_count))
4613                 obj->pages_pin_count = 0;
4614         if (discard_backing_storage(obj))
4615                 obj->madv = I915_MADV_DONTNEED;
4616         i915_gem_object_put_pages(obj);
4617         i915_gem_object_free_mmap_offset(obj);
4618
4619         BUG_ON(obj->pages);
4620
4621         if (obj->base.import_attach)
4622                 drm_prime_gem_destroy(&obj->base, NULL);
4623
4624         if (obj->ops->release)
4625                 obj->ops->release(obj);
4626
4627         drm_gem_object_release(&obj->base);
4628         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4629
4630         kfree(obj->bit_17);
4631         i915_gem_object_free(obj);
4632
4633         intel_runtime_pm_put(dev_priv);
4634 }
4635
4636 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4637                                      struct i915_address_space *vm)
4638 {
4639         struct i915_vma *vma;
4640         list_for_each_entry(vma, &obj->vma_list, vma_link)
4641                 if (vma->vm == vm)
4642                         return vma;
4643
4644         return NULL;
4645 }
4646
4647 void i915_gem_vma_destroy(struct i915_vma *vma)
4648 {
4649         struct i915_address_space *vm = NULL;
4650         WARN_ON(vma->node.allocated);
4651
4652         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4653         if (!list_empty(&vma->exec_list))
4654                 return;
4655
4656         vm = vma->vm;
4657
4658         if (!i915_is_ggtt(vm))
4659                 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4660
4661         list_del(&vma->vma_link);
4662
4663         kfree(vma);
4664 }
4665
4666 static void
4667 i915_gem_stop_ringbuffers(struct drm_device *dev)
4668 {
4669         struct drm_i915_private *dev_priv = dev->dev_private;
4670         struct intel_engine_cs *ring;
4671         int i;
4672
4673         for_each_ring(ring, dev_priv, i)
4674                 dev_priv->gt.stop_ring(ring);
4675 }
4676
4677 int
4678 i915_gem_suspend(struct drm_device *dev)
4679 {
4680         struct drm_i915_private *dev_priv = dev->dev_private;
4681         int ret = 0;
4682
4683         mutex_lock(&dev->struct_mutex);
4684         ret = i915_gpu_idle(dev);
4685         if (ret)
4686                 goto err;
4687
4688         i915_gem_retire_requests(dev);
4689
4690         /* Under UMS, be paranoid and evict. */
4691         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4692                 i915_gem_evict_everything(dev);
4693
4694         i915_gem_stop_ringbuffers(dev);
4695         mutex_unlock(&dev->struct_mutex);
4696
4697         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4698         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4699         flush_delayed_work(&dev_priv->mm.idle_work);
4700
4701         return 0;
4702
4703 err:
4704         mutex_unlock(&dev->struct_mutex);
4705         return ret;
4706 }
4707
4708 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4709 {
4710         struct drm_device *dev = ring->dev;
4711         struct drm_i915_private *dev_priv = dev->dev_private;
4712         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4713         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4714         int i, ret;
4715
4716         if (!HAS_L3_DPF(dev) || !remap_info)
4717                 return 0;
4718
4719         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4720         if (ret)
4721                 return ret;
4722
4723         /*
4724          * Note: We do not worry about the concurrent register cacheline hang
4725          * here because no other code should access these registers other than
4726          * at initialization time.
4727          */
4728         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4729                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4730                 intel_ring_emit(ring, reg_base + i);
4731                 intel_ring_emit(ring, remap_info[i/4]);
4732         }
4733
4734         intel_ring_advance(ring);
4735
4736         return ret;
4737 }
4738
4739 void i915_gem_init_swizzling(struct drm_device *dev)
4740 {
4741         struct drm_i915_private *dev_priv = dev->dev_private;
4742
4743         if (INTEL_INFO(dev)->gen < 5 ||
4744             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4745                 return;
4746
4747         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4748                                  DISP_TILE_SURFACE_SWIZZLING);
4749
4750         if (IS_GEN5(dev))
4751                 return;
4752
4753         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4754         if (IS_GEN6(dev))
4755                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4756         else if (IS_GEN7(dev))
4757                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4758         else if (IS_GEN8(dev))
4759                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4760         else
4761                 BUG();
4762 }
4763
4764 static bool
4765 intel_enable_blt(struct drm_device *dev)
4766 {
4767         if (!HAS_BLT(dev))
4768                 return false;
4769
4770         /* The blitter was dysfunctional on early prototypes */
4771         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4772                 DRM_INFO("BLT not supported on this pre-production hardware;"
4773                          " graphics performance will be degraded.\n");
4774                 return false;
4775         }
4776
4777         return true;
4778 }
4779
4780 static void init_unused_ring(struct drm_device *dev, u32 base)
4781 {
4782         struct drm_i915_private *dev_priv = dev->dev_private;
4783
4784         I915_WRITE(RING_CTL(base), 0);
4785         I915_WRITE(RING_HEAD(base), 0);
4786         I915_WRITE(RING_TAIL(base), 0);
4787         I915_WRITE(RING_START(base), 0);
4788 }
4789
4790 static void init_unused_rings(struct drm_device *dev)
4791 {
4792         if (IS_I830(dev)) {
4793                 init_unused_ring(dev, PRB1_BASE);
4794                 init_unused_ring(dev, SRB0_BASE);
4795                 init_unused_ring(dev, SRB1_BASE);
4796                 init_unused_ring(dev, SRB2_BASE);
4797                 init_unused_ring(dev, SRB3_BASE);
4798         } else if (IS_GEN2(dev)) {
4799                 init_unused_ring(dev, SRB0_BASE);
4800                 init_unused_ring(dev, SRB1_BASE);
4801         } else if (IS_GEN3(dev)) {
4802                 init_unused_ring(dev, PRB1_BASE);
4803                 init_unused_ring(dev, PRB2_BASE);
4804         }
4805 }
4806
4807 int i915_gem_init_rings(struct drm_device *dev)
4808 {
4809         struct drm_i915_private *dev_priv = dev->dev_private;
4810         int ret;
4811
4812         /*
4813          * At least 830 can leave some of the unused rings
4814          * "active" (ie. head != tail) after resume which
4815          * will prevent c3 entry. Makes sure all unused rings
4816          * are totally idle.
4817          */
4818         init_unused_rings(dev);
4819
4820         ret = intel_init_render_ring_buffer(dev);
4821         if (ret)
4822                 return ret;
4823
4824         if (HAS_BSD(dev)) {
4825                 ret = intel_init_bsd_ring_buffer(dev);
4826                 if (ret)
4827                         goto cleanup_render_ring;
4828         }
4829
4830         if (intel_enable_blt(dev)) {
4831                 ret = intel_init_blt_ring_buffer(dev);
4832                 if (ret)
4833                         goto cleanup_bsd_ring;
4834         }
4835
4836         if (HAS_VEBOX(dev)) {
4837                 ret = intel_init_vebox_ring_buffer(dev);
4838                 if (ret)
4839                         goto cleanup_blt_ring;
4840         }
4841
4842         if (HAS_BSD2(dev)) {
4843                 ret = intel_init_bsd2_ring_buffer(dev);
4844                 if (ret)
4845                         goto cleanup_vebox_ring;
4846         }
4847
4848         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4849         if (ret)
4850                 goto cleanup_bsd2_ring;
4851
4852         return 0;
4853
4854 cleanup_bsd2_ring:
4855         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4856 cleanup_vebox_ring:
4857         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4858 cleanup_blt_ring:
4859         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4860 cleanup_bsd_ring:
4861         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4862 cleanup_render_ring:
4863         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4864
4865         return ret;
4866 }
4867
4868 int
4869 i915_gem_init_hw(struct drm_device *dev)
4870 {
4871         struct drm_i915_private *dev_priv = dev->dev_private;
4872         int ret, i;
4873
4874         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4875                 return -EIO;
4876
4877         if (dev_priv->ellc_size)
4878                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4879
4880         if (IS_HASWELL(dev))
4881                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4882                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4883
4884         if (HAS_PCH_NOP(dev)) {
4885                 if (IS_IVYBRIDGE(dev)) {
4886                         u32 temp = I915_READ(GEN7_MSG_CTL);
4887                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4888                         I915_WRITE(GEN7_MSG_CTL, temp);
4889                 } else if (INTEL_INFO(dev)->gen >= 7) {
4890                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4891                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4892                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4893                 }
4894         }
4895
4896         i915_gem_init_swizzling(dev);
4897
4898         ret = dev_priv->gt.init_rings(dev);
4899         if (ret)
4900                 return ret;
4901
4902         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4903                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4904
4905         /*
4906          * XXX: Contexts should only be initialized once. Doing a switch to the
4907          * default context switch however is something we'd like to do after
4908          * reset or thaw (the latter may not actually be necessary for HW, but
4909          * goes with our code better). Context switching requires rings (for
4910          * the do_switch), but before enabling PPGTT. So don't move this.
4911          */
4912         ret = i915_gem_context_enable(dev_priv);
4913         if (ret && ret != -EIO) {
4914                 DRM_ERROR("Context enable failed %d\n", ret);
4915                 i915_gem_cleanup_ringbuffer(dev);
4916
4917                 return ret;
4918         }
4919
4920         ret = i915_ppgtt_init_hw(dev);
4921         if (ret && ret != -EIO) {
4922                 DRM_ERROR("PPGTT enable failed %d\n", ret);
4923                 i915_gem_cleanup_ringbuffer(dev);
4924         }
4925
4926         return ret;
4927 }
4928
4929 int i915_gem_init(struct drm_device *dev)
4930 {
4931         struct drm_i915_private *dev_priv = dev->dev_private;
4932         int ret;
4933
4934         i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4935                         i915.enable_execlists);
4936
4937         mutex_lock(&dev->struct_mutex);
4938
4939         if (IS_VALLEYVIEW(dev)) {
4940                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4941                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4942                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4943                               VLV_GTLC_ALLOWWAKEACK), 10))
4944                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4945         }
4946
4947         if (!i915.enable_execlists) {
4948                 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4949                 dev_priv->gt.init_rings = i915_gem_init_rings;
4950                 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4951                 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4952         } else {
4953                 dev_priv->gt.do_execbuf = intel_execlists_submission;
4954                 dev_priv->gt.init_rings = intel_logical_rings_init;
4955                 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4956                 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4957         }
4958
4959         ret = i915_gem_init_userptr(dev);
4960         if (ret) {
4961                 mutex_unlock(&dev->struct_mutex);
4962                 return ret;
4963         }
4964
4965         i915_gem_init_global_gtt(dev);
4966
4967         ret = i915_gem_context_init(dev);
4968         if (ret) {
4969                 mutex_unlock(&dev->struct_mutex);
4970                 return ret;
4971         }
4972
4973         ret = i915_gem_init_hw(dev);
4974         if (ret == -EIO) {
4975                 /* Allow ring initialisation to fail by marking the GPU as
4976                  * wedged. But we only want to do this where the GPU is angry,
4977                  * for all other failure, such as an allocation failure, bail.
4978                  */
4979                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4980                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4981                 ret = 0;
4982         }
4983         mutex_unlock(&dev->struct_mutex);
4984
4985         return ret;
4986 }
4987
4988 void
4989 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4990 {
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         struct intel_engine_cs *ring;
4993         int i;
4994
4995         for_each_ring(ring, dev_priv, i)
4996                 dev_priv->gt.cleanup_ring(ring);
4997 }
4998
4999 static void
5000 init_ring_lists(struct intel_engine_cs *ring)
5001 {
5002         INIT_LIST_HEAD(&ring->active_list);
5003         INIT_LIST_HEAD(&ring->request_list);
5004 }
5005
5006 void i915_init_vm(struct drm_i915_private *dev_priv,
5007                   struct i915_address_space *vm)
5008 {
5009         if (!i915_is_ggtt(vm))
5010                 drm_mm_init(&vm->mm, vm->start, vm->total);
5011         vm->dev = dev_priv->dev;
5012         INIT_LIST_HEAD(&vm->active_list);
5013         INIT_LIST_HEAD(&vm->inactive_list);
5014         INIT_LIST_HEAD(&vm->global_link);
5015         list_add_tail(&vm->global_link, &dev_priv->vm_list);
5016 }
5017
5018 void
5019 i915_gem_load(struct drm_device *dev)
5020 {
5021         struct drm_i915_private *dev_priv = dev->dev_private;
5022         int i;
5023
5024         dev_priv->slab =
5025                 kmem_cache_create("i915_gem_object",
5026                                   sizeof(struct drm_i915_gem_object), 0,
5027                                   SLAB_HWCACHE_ALIGN,
5028                                   NULL);
5029
5030         INIT_LIST_HEAD(&dev_priv->vm_list);
5031         i915_init_vm(dev_priv, &dev_priv->gtt.base);
5032
5033         INIT_LIST_HEAD(&dev_priv->context_list);
5034         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5035         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5036         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5037         for (i = 0; i < I915_NUM_RINGS; i++)
5038                 init_ring_lists(&dev_priv->ring[i]);
5039         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5040                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5041         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5042                           i915_gem_retire_work_handler);
5043         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5044                           i915_gem_idle_work_handler);
5045         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5046
5047         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5048         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
5049                 I915_WRITE(MI_ARB_STATE,
5050                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5051         }
5052
5053         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5054
5055         /* Old X drivers will take 0-2 for front, back, depth buffers */
5056         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5057                 dev_priv->fence_reg_start = 3;
5058
5059         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5060                 dev_priv->num_fence_regs = 32;
5061         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5062                 dev_priv->num_fence_regs = 16;
5063         else
5064                 dev_priv->num_fence_regs = 8;
5065
5066         /* Initialize fence registers to zero */
5067         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5068         i915_gem_restore_fences(dev);
5069
5070         i915_gem_detect_bit_6_swizzle(dev);
5071         init_waitqueue_head(&dev_priv->pending_flip_queue);
5072
5073         dev_priv->mm.interruptible = true;
5074
5075         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
5076         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
5077         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
5078         register_shrinker(&dev_priv->mm.shrinker);
5079
5080         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
5081         register_oom_notifier(&dev_priv->mm.oom_notifier);
5082
5083         mutex_init(&dev_priv->fb_tracking.lock);
5084 }
5085
5086 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5087 {
5088         struct drm_i915_file_private *file_priv = file->driver_priv;
5089
5090         cancel_delayed_work_sync(&file_priv->mm.idle_work);
5091
5092         /* Clean up our request list when the client is going away, so that
5093          * later retire_requests won't dereference our soon-to-be-gone
5094          * file_priv.
5095          */
5096         spin_lock(&file_priv->mm.lock);
5097         while (!list_empty(&file_priv->mm.request_list)) {
5098                 struct drm_i915_gem_request *request;
5099
5100                 request = list_first_entry(&file_priv->mm.request_list,
5101                                            struct drm_i915_gem_request,
5102                                            client_list);
5103                 list_del(&request->client_list);
5104                 request->file_priv = NULL;
5105         }
5106         spin_unlock(&file_priv->mm.lock);
5107 }
5108
5109 static void
5110 i915_gem_file_idle_work_handler(struct work_struct *work)
5111 {
5112         struct drm_i915_file_private *file_priv =
5113                 container_of(work, typeof(*file_priv), mm.idle_work.work);
5114
5115         atomic_set(&file_priv->rps_wait_boost, false);
5116 }
5117
5118 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5119 {
5120         struct drm_i915_file_private *file_priv;
5121         int ret;
5122
5123         DRM_DEBUG_DRIVER("\n");
5124
5125         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5126         if (!file_priv)
5127                 return -ENOMEM;
5128
5129         file->driver_priv = file_priv;
5130         file_priv->dev_priv = dev->dev_private;
5131         file_priv->file = file;
5132
5133         spin_lock_init(&file_priv->mm.lock);
5134         INIT_LIST_HEAD(&file_priv->mm.request_list);
5135         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5136                           i915_gem_file_idle_work_handler);
5137
5138         ret = i915_gem_context_open(dev, file);
5139         if (ret)
5140                 kfree(file_priv);
5141
5142         return ret;
5143 }
5144
5145 /**
5146  * i915_gem_track_fb - update frontbuffer tracking
5147  * old: current GEM buffer for the frontbuffer slots
5148  * new: new GEM buffer for the frontbuffer slots
5149  * frontbuffer_bits: bitmask of frontbuffer slots
5150  *
5151  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5152  * from @old and setting them in @new. Both @old and @new can be NULL.
5153  */
5154 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5155                        struct drm_i915_gem_object *new,
5156                        unsigned frontbuffer_bits)
5157 {
5158         if (old) {
5159                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5160                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5161                 old->frontbuffer_bits &= ~frontbuffer_bits;
5162         }
5163
5164         if (new) {
5165                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5166                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5167                 new->frontbuffer_bits |= frontbuffer_bits;
5168         }
5169 }
5170
5171 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5172 {
5173         if (!mutex_is_locked(mutex))
5174                 return false;
5175
5176 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5177         return mutex->owner == task;
5178 #else
5179         /* Since UP may be pre-empted, we cannot assume that we own the lock */
5180         return false;
5181 #endif
5182 }
5183
5184 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5185 {
5186         if (!mutex_trylock(&dev->struct_mutex)) {
5187                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5188                         return false;
5189
5190                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5191                         return false;
5192
5193                 *unlock = false;
5194         } else
5195                 *unlock = true;
5196
5197         return true;
5198 }
5199
5200 static int num_vma_bound(struct drm_i915_gem_object *obj)
5201 {
5202         struct i915_vma *vma;
5203         int count = 0;
5204
5205         list_for_each_entry(vma, &obj->vma_list, vma_link)
5206                 if (drm_mm_node_allocated(&vma->node))
5207                         count++;
5208
5209         return count;
5210 }
5211
5212 static unsigned long
5213 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5214 {
5215         struct drm_i915_private *dev_priv =
5216                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5217         struct drm_device *dev = dev_priv->dev;
5218         struct drm_i915_gem_object *obj;
5219         unsigned long count;
5220         bool unlock;
5221
5222         if (!i915_gem_shrinker_lock(dev, &unlock))
5223                 return 0;
5224
5225         count = 0;
5226         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5227                 if (obj->pages_pin_count == 0)
5228                         count += obj->base.size >> PAGE_SHIFT;
5229
5230         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5231                 if (!i915_gem_obj_is_pinned(obj) &&
5232                     obj->pages_pin_count == num_vma_bound(obj))
5233                         count += obj->base.size >> PAGE_SHIFT;
5234         }
5235
5236         if (unlock)
5237                 mutex_unlock(&dev->struct_mutex);
5238
5239         return count;
5240 }
5241
5242 /* All the new VM stuff */
5243 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5244                                   struct i915_address_space *vm)
5245 {
5246         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5247         struct i915_vma *vma;
5248
5249         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5250
5251         list_for_each_entry(vma, &o->vma_list, vma_link) {
5252                 if (vma->vm == vm)
5253                         return vma->node.start;
5254
5255         }
5256         WARN(1, "%s vma for this object not found.\n",
5257              i915_is_ggtt(vm) ? "global" : "ppgtt");
5258         return -1;
5259 }
5260
5261 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5262                         struct i915_address_space *vm)
5263 {
5264         struct i915_vma *vma;
5265
5266         list_for_each_entry(vma, &o->vma_list, vma_link)
5267                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5268                         return true;
5269
5270         return false;
5271 }
5272
5273 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5274 {
5275         struct i915_vma *vma;
5276
5277         list_for_each_entry(vma, &o->vma_list, vma_link)
5278                 if (drm_mm_node_allocated(&vma->node))
5279                         return true;
5280
5281         return false;
5282 }
5283
5284 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5285                                 struct i915_address_space *vm)
5286 {
5287         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5288         struct i915_vma *vma;
5289
5290         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5291
5292         BUG_ON(list_empty(&o->vma_list));
5293
5294         list_for_each_entry(vma, &o->vma_list, vma_link)
5295                 if (vma->vm == vm)
5296                         return vma->node.size;
5297
5298         return 0;
5299 }
5300
5301 static unsigned long
5302 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5303 {
5304         struct drm_i915_private *dev_priv =
5305                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5306         struct drm_device *dev = dev_priv->dev;
5307         unsigned long freed;
5308         bool unlock;
5309
5310         if (!i915_gem_shrinker_lock(dev, &unlock))
5311                 return SHRINK_STOP;
5312
5313         freed = i915_gem_shrink(dev_priv,
5314                                 sc->nr_to_scan,
5315                                 I915_SHRINK_BOUND |
5316                                 I915_SHRINK_UNBOUND |
5317                                 I915_SHRINK_PURGEABLE);
5318         if (freed < sc->nr_to_scan)
5319                 freed += i915_gem_shrink(dev_priv,
5320                                          sc->nr_to_scan - freed,
5321                                          I915_SHRINK_BOUND |
5322                                          I915_SHRINK_UNBOUND);
5323         if (unlock)
5324                 mutex_unlock(&dev->struct_mutex);
5325
5326         return freed;
5327 }
5328
5329 static int
5330 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5331 {
5332         struct drm_i915_private *dev_priv =
5333                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5334         struct drm_device *dev = dev_priv->dev;
5335         struct drm_i915_gem_object *obj;
5336         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5337         unsigned long pinned, bound, unbound, freed_pages;
5338         bool was_interruptible;
5339         bool unlock;
5340
5341         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5342                 schedule_timeout_killable(1);
5343                 if (fatal_signal_pending(current))
5344                         return NOTIFY_DONE;
5345         }
5346         if (timeout == 0) {
5347                 pr_err("Unable to purge GPU memory due lock contention.\n");
5348                 return NOTIFY_DONE;
5349         }
5350
5351         was_interruptible = dev_priv->mm.interruptible;
5352         dev_priv->mm.interruptible = false;
5353
5354         freed_pages = i915_gem_shrink_all(dev_priv);
5355
5356         dev_priv->mm.interruptible = was_interruptible;
5357
5358         /* Because we may be allocating inside our own driver, we cannot
5359          * assert that there are no objects with pinned pages that are not
5360          * being pointed to by hardware.
5361          */
5362         unbound = bound = pinned = 0;
5363         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5364                 if (!obj->base.filp) /* not backed by a freeable object */
5365                         continue;
5366
5367                 if (obj->pages_pin_count)
5368                         pinned += obj->base.size;
5369                 else
5370                         unbound += obj->base.size;
5371         }
5372         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5373                 if (!obj->base.filp)
5374                         continue;
5375
5376                 if (obj->pages_pin_count)
5377                         pinned += obj->base.size;
5378                 else
5379                         bound += obj->base.size;
5380         }
5381
5382         if (unlock)
5383                 mutex_unlock(&dev->struct_mutex);
5384
5385         if (freed_pages || unbound || bound)
5386                 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5387                         freed_pages << PAGE_SHIFT, pinned);
5388         if (unbound || bound)
5389                 pr_err("%lu and %lu bytes still available in the "
5390                        "bound and unbound GPU page lists.\n",
5391                        bound, unbound);
5392
5393         *(unsigned long *)ptr += freed_pages;
5394         return NOTIFY_DONE;
5395 }
5396
5397 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5398 {
5399         struct i915_vma *vma;
5400
5401         vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5402         if (vma->vm != i915_obj_to_ggtt(obj))
5403                 return NULL;
5404
5405         return vma;
5406 }