drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_vgpu.h"
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35 #include <linux/oom.h>
  36 #include <linux/shmem_fs.h>
  37 #include <linux/slab.h>
  38 #include <linux/swap.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-buf.h>
  41
  42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  44 static __must_check int
  45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  46                                bool readonly);
  47 static void
  48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  57                                              struct shrink_control *sc);
  58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  59                                             struct shrink_control *sc);
  60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  61                                  unsigned long event,
  62                                  void *ptr);
  63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  64
  65 static bool cpu_cache_is_coherent(struct drm_device *dev,
  66                                   enum i915_cache_level level)
  67 {
  68         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  69 }
  70
  71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  72 {
  73         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  74                 return true;
  75
  76         return obj->pin_display;
  77 }
  78
  79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  80 {
  81         if (obj->tiling_mode)
  82                 i915_gem_release_mmap(obj);
  83
  84         /* As we do not have an associated fence register, we will force
  85          * a tiling change if we ever need to acquire one.
  86          */
  87         obj->fence_dirty = false;
  88         obj->fence_reg = I915_FENCE_REG_NONE;
  89 }
  90
  91 /* some bookkeeping */
  92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  93                                   size_t size)
  94 {
  95         spin_lock(&dev_priv->mm.object_stat_lock);
  96         dev_priv->mm.object_count++;
  97         dev_priv->mm.object_memory += size;
  98         spin_unlock(&dev_priv->mm.object_stat_lock);
  99 }
 100
 101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 102                                      size_t size)
 103 {
 104         spin_lock(&dev_priv->mm.object_stat_lock);
 105         dev_priv->mm.object_count--;
 106         dev_priv->mm.object_memory -= size;
 107         spin_unlock(&dev_priv->mm.object_stat_lock);
 108 }
 109
 110 static int
 111 i915_gem_wait_for_error(struct i915_gpu_error *error)
 112 {
 113         int ret;
 114
 115 #define EXIT_COND (!i915_reset_in_progress(error) || \
 116                    i915_terminally_wedged(error))
 117         if (EXIT_COND)
 118                 return 0;
 119
 120         /*
 121          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 122          * userspace. If it takes that long something really bad is going on and
 123          * we should simply try to bail out and fail as gracefully as possible.
 124          */
 125         ret = wait_event_interruptible_timeout(error->reset_queue,
 126                                                EXIT_COND,
 127                                                10*HZ);
 128         if (ret == 0) {
 129                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 130                 return -EIO;
 131         } else if (ret < 0) {
 132                 return ret;
 133         }
 134 #undef EXIT_COND
 135
 136         return 0;
 137 }
 138
 139 int i915_mutex_lock_interruptible(struct drm_device *dev)
 140 {
 141         struct drm_i915_private *dev_priv = dev->dev_private;
 142         int ret;
 143
 144         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 145         if (ret)
 146                 return ret;
 147
 148         ret = mutex_lock_interruptible(&dev->struct_mutex);
 149         if (ret)
 150                 return ret;
 151
 152         WARN_ON(i915_verify_lists(dev));
 153         return 0;
 154 }
 155
 156 int
 157 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 158                             struct drm_file *file)
 159 {
 160         struct drm_i915_private *dev_priv = dev->dev_private;
 161         struct drm_i915_gem_get_aperture *args = data;
 162         struct drm_i915_gem_object *obj;
 163         size_t pinned;
 164
 165         pinned = 0;
 166         mutex_lock(&dev->struct_mutex);
 167         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 168                 if (i915_gem_obj_is_pinned(obj))
 169                         pinned += i915_gem_obj_ggtt_size(obj);
 170         mutex_unlock(&dev->struct_mutex);
 171
 172         args->aper_size = dev_priv->gtt.base.total;
 173         args->aper_available_size = args->aper_size - pinned;
 174
 175         return 0;
 176 }
 177
 178 static int
 179 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 180 {
 181         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 182         char *vaddr = obj->phys_handle->vaddr;
 183         struct sg_table *st;
 184         struct scatterlist *sg;
 185         int i;
 186
 187         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
 188                 return -EINVAL;
 189
 190         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 191                 struct page *page;
 192                 char *src;
 193
 194                 page = shmem_read_mapping_page(mapping, i);
 195                 if (IS_ERR(page))
 196                         return PTR_ERR(page);
 197
 198                 src = kmap_atomic(page);
 199                 memcpy(vaddr, src, PAGE_SIZE);
 200                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 201                 kunmap_atomic(src);
 202
 203                 page_cache_release(page);
 204                 vaddr += PAGE_SIZE;
 205         }
 206
 207         i915_gem_chipset_flush(obj->base.dev);
 208
 209         st = kmalloc(sizeof(*st), GFP_KERNEL);
 210         if (st == NULL)
 211                 return -ENOMEM;
 212
 213         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 214                 kfree(st);
 215                 return -ENOMEM;
 216         }
 217
 218         sg = st->sgl;
 219         sg->offset = 0;
 220         sg->length = obj->base.size;
 221
 222         sg_dma_address(sg) = obj->phys_handle->busaddr;
 223         sg_dma_len(sg) = obj->base.size;
 224
 225         obj->pages = st;
 226         obj->has_dma_mapping = true;
 227         return 0;
 228 }
 229
 230 static void
 231 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
 232 {
 233         int ret;
 234
 235         BUG_ON(obj->madv == __I915_MADV_PURGED);
 236
 237         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 238         if (ret) {
 239                 /* In the event of a disaster, abandon all caches and
 240                  * hope for the best.
 241                  */
 242                 WARN_ON(ret != -EIO);
 243                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 244         }
 245
 246         if (obj->madv == I915_MADV_DONTNEED)
 247                 obj->dirty = 0;
 248
 249         if (obj->dirty) {
 250                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 251                 char *vaddr = obj->phys_handle->vaddr;
 252                 int i;
 253
 254                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 255                         struct page *page;
 256                         char *dst;
 257
 258                         page = shmem_read_mapping_page(mapping, i);
 259                         if (IS_ERR(page))
 260                                 continue;
 261
 262                         dst = kmap_atomic(page);
 263                         drm_clflush_virt_range(vaddr, PAGE_SIZE);
 264                         memcpy(dst, vaddr, PAGE_SIZE);
 265                         kunmap_atomic(dst);
 266
 267                         set_page_dirty(page);
 268                         if (obj->madv == I915_MADV_WILLNEED)
 269                                 mark_page_accessed(page);
 270                         page_cache_release(page);
 271                         vaddr += PAGE_SIZE;
 272                 }
 273                 obj->dirty = 0;
 274         }
 275
 276         sg_free_table(obj->pages);
 277         kfree(obj->pages);
 278
 279         obj->has_dma_mapping = false;
 280 }
 281
 282 static void
 283 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
 284 {
 285         drm_pci_free(obj->base.dev, obj->phys_handle);
 286 }
 287
 288 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 289         .get_pages = i915_gem_object_get_pages_phys,
 290         .put_pages = i915_gem_object_put_pages_phys,
 291         .release = i915_gem_object_release_phys,
 292 };
 293
 294 static int
 295 drop_pages(struct drm_i915_gem_object *obj)
 296 {
 297         struct i915_vma *vma, *next;
 298         int ret;
 299
 300         drm_gem_object_reference(&obj->base);
 301         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
 302                 if (i915_vma_unbind(vma))
 303                         break;
 304
 305         ret = i915_gem_object_put_pages(obj);
 306         drm_gem_object_unreference(&obj->base);
 307
 308         return ret;
 309 }
 310
 311 int
 312 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 313                             int align)
 314 {
 315         drm_dma_handle_t *phys;
 316         int ret;
 317
 318         if (obj->phys_handle) {
 319                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 320                         return -EBUSY;
 321
 322                 return 0;
 323         }
 324
 325         if (obj->madv != I915_MADV_WILLNEED)
 326                 return -EFAULT;
 327
 328         if (obj->base.filp == NULL)
 329                 return -EINVAL;
 330
 331         ret = drop_pages(obj);
 332         if (ret)
 333                 return ret;
 334
 335         /* create a new object */
 336         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 337         if (!phys)
 338                 return -ENOMEM;
 339
 340         obj->phys_handle = phys;
 341         obj->ops = &i915_gem_phys_ops;
 342
 343         return i915_gem_object_get_pages(obj);
 344 }
 345
 346 static int
 347 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 348                      struct drm_i915_gem_pwrite *args,
 349                      struct drm_file *file_priv)
 350 {
 351         struct drm_device *dev = obj->base.dev;
 352         void *vaddr = obj->phys_handle->vaddr + args->offset;
 353         char __user *user_data = to_user_ptr(args->data_ptr);
 354         int ret;
 355
 356         /* We manually control the domain here and pretend that it
 357          * remains coherent i.e. in the GTT domain, like shmem_pwrite.
 358          */
 359         ret = i915_gem_object_wait_rendering(obj, false);
 360         if (ret)
 361                 return ret;
 362
 363         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 364                 unsigned long unwritten;
 365
 366                 /* The physical object once assigned is fixed for the lifetime
 367                  * of the obj, so we can safely drop the lock and continue
 368                  * to access vaddr.
 369                  */
 370                 mutex_unlock(&dev->struct_mutex);
 371                 unwritten = copy_from_user(vaddr, user_data, args->size);
 372                 mutex_lock(&dev->struct_mutex);
 373                 if (unwritten)
 374                         return -EFAULT;
 375         }
 376
 377         drm_clflush_virt_range(vaddr, args->size);
 378         i915_gem_chipset_flush(dev);
 379         return 0;
 380 }
 381
 382 void *i915_gem_object_alloc(struct drm_device *dev)
 383 {
 384         struct drm_i915_private *dev_priv = dev->dev_private;
 385         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 386 }
 387
 388 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 389 {
 390         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 391         kmem_cache_free(dev_priv->slab, obj);
 392 }
 393
 394 static int
 395 i915_gem_create(struct drm_file *file,
 396                 struct drm_device *dev,
 397                 uint64_t size,
 398                 uint32_t *handle_p)
 399 {
 400         struct drm_i915_gem_object *obj;
 401         int ret;
 402         u32 handle;
 403
 404         size = roundup(size, PAGE_SIZE);
 405         if (size == 0)
 406                 return -EINVAL;
 407
 408         /* Allocate the new object */
 409         obj = i915_gem_alloc_object(dev, size);
 410         if (obj == NULL)
 411                 return -ENOMEM;
 412
 413         ret = drm_gem_handle_create(file, &obj->base, &handle);
 414         /* drop reference from allocate - handle holds it now */
 415         drm_gem_object_unreference_unlocked(&obj->base);
 416         if (ret)
 417                 return ret;
 418
 419         *handle_p = handle;
 420         return 0;
 421 }
 422
 423 int
 424 i915_gem_dumb_create(struct drm_file *file,
 425                      struct drm_device *dev,
 426                      struct drm_mode_create_dumb *args)
 427 {
 428         /* have to work out size/pitch and return them */
 429         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 430         args->size = args->pitch * args->height;
 431         return i915_gem_create(file, dev,
 432                                args->size, &args->handle);
 433 }
 434
 435 /**
 436  * Creates a new mm object and returns a handle to it.
 437  */
 438 int
 439 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 440                       struct drm_file *file)
 441 {
 442         struct drm_i915_gem_create *args = data;
 443
 444         return i915_gem_create(file, dev,
 445                                args->size, &args->handle);
 446 }
 447
 448 static inline int
 449 __copy_to_user_swizzled(char __user *cpu_vaddr,
 450                         const char *gpu_vaddr, int gpu_offset,
 451                         int length)
 452 {
 453         int ret, cpu_offset = 0;
 454
 455         while (length > 0) {
 456                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 457                 int this_length = min(cacheline_end - gpu_offset, length);
 458                 int swizzled_gpu_offset = gpu_offset ^ 64;
 459
 460                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 461                                      gpu_vaddr + swizzled_gpu_offset,
 462                                      this_length);
 463                 if (ret)
 464                         return ret + length;
 465
 466                 cpu_offset += this_length;
 467                 gpu_offset += this_length;
 468                 length -= this_length;
 469         }
 470
 471         return 0;
 472 }
 473
 474 static inline int
 475 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 476                           const char __user *cpu_vaddr,
 477                           int length)
 478 {
 479         int ret, cpu_offset = 0;
 480
 481         while (length > 0) {
 482                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 483                 int this_length = min(cacheline_end - gpu_offset, length);
 484                 int swizzled_gpu_offset = gpu_offset ^ 64;
 485
 486                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 487                                        cpu_vaddr + cpu_offset,
 488                                        this_length);
 489                 if (ret)
 490                         return ret + length;
 491
 492                 cpu_offset += this_length;
 493                 gpu_offset += this_length;
 494                 length -= this_length;
 495         }
 496
 497         return 0;
 498 }
 499
 500 /*
 501  * Pins the specified object's pages and synchronizes the object with
 502  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 503  * flush the object from the CPU cache.
 504  */
 505 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 506                                     int *needs_clflush)
 507 {
 508         int ret;
 509
 510         *needs_clflush = 0;
 511
 512         if (!obj->base.filp)
 513                 return -EINVAL;
 514
 515         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 516                 /* If we're not in the cpu read domain, set ourself into the gtt
 517                  * read domain and manually flush cachelines (if required). This
 518                  * optimizes for the case when the gpu will dirty the data
 519                  * anyway again before the next pread happens. */
 520                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 521                                                         obj->cache_level);
 522                 ret = i915_gem_object_wait_rendering(obj, true);
 523                 if (ret)
 524                         return ret;
 525
 526                 i915_gem_object_retire(obj);
 527         }
 528
 529         ret = i915_gem_object_get_pages(obj);
 530         if (ret)
 531                 return ret;
 532
 533         i915_gem_object_pin_pages(obj);
 534
 535         return ret;
 536 }
 537
 538 /* Per-page copy function for the shmem pread fastpath.
 539  * Flushes invalid cachelines before reading the target if
 540  * needs_clflush is set. */
 541 static int
 542 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 543                  char __user *user_data,
 544                  bool page_do_bit17_swizzling, bool needs_clflush)
 545 {
 546         char *vaddr;
 547         int ret;
 548
 549         if (unlikely(page_do_bit17_swizzling))
 550                 return -EINVAL;
 551
 552         vaddr = kmap_atomic(page);
 553         if (needs_clflush)
 554                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 555                                        page_length);
 556         ret = __copy_to_user_inatomic(user_data,
 557                                       vaddr + shmem_page_offset,
 558                                       page_length);
 559         kunmap_atomic(vaddr);
 560
 561         return ret ? -EFAULT : 0;
 562 }
 563
 564 static void
 565 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 566                              bool swizzled)
 567 {
 568         if (unlikely(swizzled)) {
 569                 unsigned long start = (unsigned long) addr;
 570                 unsigned long end = (unsigned long) addr + length;
 571
 572                 /* For swizzling simply ensure that we always flush both
 573                  * channels. Lame, but simple and it works. Swizzled
 574                  * pwrite/pread is far from a hotpath - current userspace
 575                  * doesn't use it at all. */
 576                 start = round_down(start, 128);
 577                 end = round_up(end, 128);
 578
 579                 drm_clflush_virt_range((void *)start, end - start);
 580         } else {
 581                 drm_clflush_virt_range(addr, length);
 582         }
 583
 584 }
 585
 586 /* Only difference to the fast-path function is that this can handle bit17
 587  * and uses non-atomic copy and kmap functions. */
 588 static int
 589 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 590                  char __user *user_data,
 591                  bool page_do_bit17_swizzling, bool needs_clflush)
 592 {
 593         char *vaddr;
 594         int ret;
 595
 596         vaddr = kmap(page);
 597         if (needs_clflush)
 598                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 599                                              page_length,
 600                                              page_do_bit17_swizzling);
 601
 602         if (page_do_bit17_swizzling)
 603                 ret = __copy_to_user_swizzled(user_data,
 604                                               vaddr, shmem_page_offset,
 605                                               page_length);
 606         else
 607                 ret = __copy_to_user(user_data,
 608                                      vaddr + shmem_page_offset,
 609                                      page_length);
 610         kunmap(page);
 611
 612         return ret ? - EFAULT : 0;
 613 }
 614
 615 static int
 616 i915_gem_shmem_pread(struct drm_device *dev,
 617                      struct drm_i915_gem_object *obj,
 618                      struct drm_i915_gem_pread *args,
 619                      struct drm_file *file)
 620 {
 621         char __user *user_data;
 622         ssize_t remain;
 623         loff_t offset;
 624         int shmem_page_offset, page_length, ret = 0;
 625         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 626         int prefaulted = 0;
 627         int needs_clflush = 0;
 628         struct sg_page_iter sg_iter;
 629
 630         user_data = to_user_ptr(args->data_ptr);
 631         remain = args->size;
 632
 633         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 634
 635         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 636         if (ret)
 637                 return ret;
 638
 639         offset = args->offset;
 640
 641         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 642                          offset >> PAGE_SHIFT) {
 643                 struct page *page = sg_page_iter_page(&sg_iter);
 644
 645                 if (remain <= 0)
 646                         break;
 647
 648                 /* Operation in this page
 649                  *
 650                  * shmem_page_offset = offset within page in shmem file
 651                  * page_length = bytes to copy for this page
 652                  */
 653                 shmem_page_offset = offset_in_page(offset);
 654                 page_length = remain;
 655                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 656                         page_length = PAGE_SIZE - shmem_page_offset;
 657
 658                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 659                         (page_to_phys(page) & (1 << 17)) != 0;
 660
 661                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 662                                        user_data, page_do_bit17_swizzling,
 663                                        needs_clflush);
 664                 if (ret == 0)
 665                         goto next_page;
 666
 667                 mutex_unlock(&dev->struct_mutex);
 668
 669                 if (likely(!i915.prefault_disable) && !prefaulted) {
 670                         ret = fault_in_multipages_writeable(user_data, remain);
 671                         /* Userspace is tricking us, but we've already clobbered
 672                          * its pages with the prefault and promised to write the
 673                          * data up to the first fault. Hence ignore any errors
 674                          * and just continue. */
 675                         (void)ret;
 676                         prefaulted = 1;
 677                 }
 678
 679                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 680                                        user_data, page_do_bit17_swizzling,
 681                                        needs_clflush);
 682
 683                 mutex_lock(&dev->struct_mutex);
 684
 685                 if (ret)
 686                         goto out;
 687
 688 next_page:
 689                 remain -= page_length;
 690                 user_data += page_length;
 691                 offset += page_length;
 692         }
 693
 694 out:
 695         i915_gem_object_unpin_pages(obj);
 696
 697         return ret;
 698 }
 699
 700 /**
 701  * Reads data from the object referenced by handle.
 702  *
 703  * On error, the contents of *data are undefined.
 704  */
 705 int
 706 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 707                      struct drm_file *file)
 708 {
 709         struct drm_i915_gem_pread *args = data;
 710         struct drm_i915_gem_object *obj;
 711         int ret = 0;
 712
 713         if (args->size == 0)
 714                 return 0;
 715
 716         if (!access_ok(VERIFY_WRITE,
 717                        to_user_ptr(args->data_ptr),
 718                        args->size))
 719                 return -EFAULT;
 720
 721         ret = i915_mutex_lock_interruptible(dev);
 722         if (ret)
 723                 return ret;
 724
 725         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 726         if (&obj->base == NULL) {
 727                 ret = -ENOENT;
 728                 goto unlock;
 729         }
 730
 731         /* Bounds check source.  */
 732         if (args->offset > obj->base.size ||
 733             args->size > obj->base.size - args->offset) {
 734                 ret = -EINVAL;
 735                 goto out;
 736         }
 737
 738         /* prime objects have no backing filp to GEM pread/pwrite
 739          * pages from.
 740          */
 741         if (!obj->base.filp) {
 742                 ret = -EINVAL;
 743                 goto out;
 744         }
 745
 746         trace_i915_gem_object_pread(obj, args->offset, args->size);
 747
 748         ret = i915_gem_shmem_pread(dev, obj, args, file);
 749
 750 out:
 751         drm_gem_object_unreference(&obj->base);
 752 unlock:
 753         mutex_unlock(&dev->struct_mutex);
 754         return ret;
 755 }
 756
 757 /* This is the fast write path which cannot handle
 758  * page faults in the source data
 759  */
 760
 761 static inline int
 762 fast_user_write(struct io_mapping *mapping,
 763                 loff_t page_base, int page_offset,
 764                 char __user *user_data,
 765                 int length)
 766 {
 767         void __iomem *vaddr_atomic;
 768         void *vaddr;
 769         unsigned long unwritten;
 770
 771         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 772         /* We can use the cpu mem copy function because this is X86. */
 773         vaddr = (void __force*)vaddr_atomic + page_offset;
 774         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 775                                                       user_data, length);
 776         io_mapping_unmap_atomic(vaddr_atomic);
 777         return unwritten;
 778 }
 779
 780 /**
 781  * This is the fast pwrite path, where we copy the data directly from the
 782  * user into the GTT, uncached.
 783  */
 784 static int
 785 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 786                          struct drm_i915_gem_object *obj,
 787                          struct drm_i915_gem_pwrite *args,
 788                          struct drm_file *file)
 789 {
 790         struct drm_i915_private *dev_priv = dev->dev_private;
 791         ssize_t remain;
 792         loff_t offset, page_base;
 793         char __user *user_data;
 794         int page_offset, page_length, ret;
 795
 796         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 797         if (ret)
 798                 goto out;
 799
 800         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 801         if (ret)
 802                 goto out_unpin;
 803
 804         ret = i915_gem_object_put_fence(obj);
 805         if (ret)
 806                 goto out_unpin;
 807
 808         user_data = to_user_ptr(args->data_ptr);
 809         remain = args->size;
 810
 811         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 812
 813         while (remain > 0) {
 814                 /* Operation in this page
 815                  *
 816                  * page_base = page offset within aperture
 817                  * page_offset = offset within page
 818                  * page_length = bytes to copy for this page
 819                  */
 820                 page_base = offset & PAGE_MASK;
 821                 page_offset = offset_in_page(offset);
 822                 page_length = remain;
 823                 if ((page_offset + remain) > PAGE_SIZE)
 824                         page_length = PAGE_SIZE - page_offset;
 825
 826                 /* If we get a fault while copying data, then (presumably) our
 827                  * source page isn't available.  Return the error and we'll
 828                  * retry in the slow path.
 829                  */
 830                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 831                                     page_offset, user_data, page_length)) {
 832                         ret = -EFAULT;
 833                         goto out_unpin;
 834                 }
 835
 836                 remain -= page_length;
 837                 user_data += page_length;
 838                 offset += page_length;
 839         }
 840
 841 out_unpin:
 842         i915_gem_object_ggtt_unpin(obj);
 843 out:
 844         return ret;
 845 }
 846
 847 /* Per-page copy function for the shmem pwrite fastpath.
 848  * Flushes invalid cachelines before writing to the target if
 849  * needs_clflush_before is set and flushes out any written cachelines after
 850  * writing if needs_clflush is set. */
 851 static int
 852 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 853                   char __user *user_data,
 854                   bool page_do_bit17_swizzling,
 855                   bool needs_clflush_before,
 856                   bool needs_clflush_after)
 857 {
 858         char *vaddr;
 859         int ret;
 860
 861         if (unlikely(page_do_bit17_swizzling))
 862                 return -EINVAL;
 863
 864         vaddr = kmap_atomic(page);
 865         if (needs_clflush_before)
 866                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 867                                        page_length);
 868         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 869                                         user_data, page_length);
 870         if (needs_clflush_after)
 871                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 872                                        page_length);
 873         kunmap_atomic(vaddr);
 874
 875         return ret ? -EFAULT : 0;
 876 }
 877
 878 /* Only difference to the fast-path function is that this can handle bit17
 879  * and uses non-atomic copy and kmap functions. */
 880 static int
 881 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 882                   char __user *user_data,
 883                   bool page_do_bit17_swizzling,
 884                   bool needs_clflush_before,
 885                   bool needs_clflush_after)
 886 {
 887         char *vaddr;
 888         int ret;
 889
 890         vaddr = kmap(page);
 891         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 892                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 893                                              page_length,
 894                                              page_do_bit17_swizzling);
 895         if (page_do_bit17_swizzling)
 896                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 897                                                 user_data,
 898                                                 page_length);
 899         else
 900                 ret = __copy_from_user(vaddr + shmem_page_offset,
 901                                        user_data,
 902                                        page_length);
 903         if (needs_clflush_after)
 904                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 905                                              page_length,
 906                                              page_do_bit17_swizzling);
 907         kunmap(page);
 908
 909         return ret ? -EFAULT : 0;
 910 }
 911
 912 static int
 913 i915_gem_shmem_pwrite(struct drm_device *dev,
 914                       struct drm_i915_gem_object *obj,
 915                       struct drm_i915_gem_pwrite *args,
 916                       struct drm_file *file)
 917 {
 918         ssize_t remain;
 919         loff_t offset;
 920         char __user *user_data;
 921         int shmem_page_offset, page_length, ret = 0;
 922         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 923         int hit_slowpath = 0;
 924         int needs_clflush_after = 0;
 925         int needs_clflush_before = 0;
 926         struct sg_page_iter sg_iter;
 927
 928         user_data = to_user_ptr(args->data_ptr);
 929         remain = args->size;
 930
 931         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 932
 933         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 934                 /* If we're not in the cpu write domain, set ourself into the gtt
 935                  * write domain and manually flush cachelines (if required). This
 936                  * optimizes for the case when the gpu will use the data
 937                  * right away and we therefore have to clflush anyway. */
 938                 needs_clflush_after = cpu_write_needs_clflush(obj);
 939                 ret = i915_gem_object_wait_rendering(obj, false);
 940                 if (ret)
 941                         return ret;
 942
 943                 i915_gem_object_retire(obj);
 944         }
 945         /* Same trick applies to invalidate partially written cachelines read
 946          * before writing. */
 947         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 948                 needs_clflush_before =
 949                         !cpu_cache_is_coherent(dev, obj->cache_level);
 950
 951         ret = i915_gem_object_get_pages(obj);
 952         if (ret)
 953                 return ret;
 954
 955         i915_gem_object_pin_pages(obj);
 956
 957         offset = args->offset;
 958         obj->dirty = 1;
 959
 960         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 961                          offset >> PAGE_SHIFT) {
 962                 struct page *page = sg_page_iter_page(&sg_iter);
 963                 int partial_cacheline_write;
 964
 965                 if (remain <= 0)
 966                         break;
 967
 968                 /* Operation in this page
 969                  *
 970                  * shmem_page_offset = offset within page in shmem file
 971                  * page_length = bytes to copy for this page
 972                  */
 973                 shmem_page_offset = offset_in_page(offset);
 974
 975                 page_length = remain;
 976                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 977                         page_length = PAGE_SIZE - shmem_page_offset;
 978
 979                 /* If we don't overwrite a cacheline completely we need to be
 980                  * careful to have up-to-date data by first clflushing. Don't
 981                  * overcomplicate things and flush the entire patch. */
 982                 partial_cacheline_write = needs_clflush_before &&
 983                         ((shmem_page_offset | page_length)
 984                                 & (boot_cpu_data.x86_clflush_size - 1));
 985
 986                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 987                         (page_to_phys(page) & (1 << 17)) != 0;
 988
 989                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 990                                         user_data, page_do_bit17_swizzling,
 991                                         partial_cacheline_write,
 992                                         needs_clflush_after);
 993                 if (ret == 0)
 994                         goto next_page;
 995
 996                 hit_slowpath = 1;
 997                 mutex_unlock(&dev->struct_mutex);
 998                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 999                                         user_data, page_do_bit17_swizzling,
1000                                         partial_cacheline_write,
1001                                         needs_clflush_after);
1002
1003                 mutex_lock(&dev->struct_mutex);
1004
1005                 if (ret)
1006                         goto out;
1007
1008 next_page:
1009                 remain -= page_length;
1010                 user_data += page_length;
1011                 offset += page_length;
1012         }
1013
1014 out:
1015         i915_gem_object_unpin_pages(obj);
1016
1017         if (hit_slowpath) {
1018                 /*
1019                  * Fixup: Flush cpu caches in case we didn't flush the dirty
1020                  * cachelines in-line while writing and the object moved
1021                  * out of the cpu write domain while we've dropped the lock.
1022                  */
1023                 if (!needs_clflush_after &&
1024                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1025                         if (i915_gem_clflush_object(obj, obj->pin_display))
1026                                 i915_gem_chipset_flush(dev);
1027                 }
1028         }
1029
1030         if (needs_clflush_after)
1031                 i915_gem_chipset_flush(dev);
1032
1033         return ret;
1034 }
1035
1036 /**
1037  * Writes data to the object referenced by handle.
1038  *
1039  * On error, the contents of the buffer that were to be modified are undefined.
1040  */
1041 int
1042 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1043                       struct drm_file *file)
1044 {
1045         struct drm_i915_private *dev_priv = dev->dev_private;
1046         struct drm_i915_gem_pwrite *args = data;
1047         struct drm_i915_gem_object *obj;
1048         int ret;
1049
1050         if (args->size == 0)
1051                 return 0;
1052
1053         if (!access_ok(VERIFY_READ,
1054                        to_user_ptr(args->data_ptr),
1055                        args->size))
1056                 return -EFAULT;
1057
1058         if (likely(!i915.prefault_disable)) {
1059                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1060                                                    args->size);
1061                 if (ret)
1062                         return -EFAULT;
1063         }
1064
1065         intel_runtime_pm_get(dev_priv);
1066
1067         ret = i915_mutex_lock_interruptible(dev);
1068         if (ret)
1069                 goto put_rpm;
1070
1071         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1072         if (&obj->base == NULL) {
1073                 ret = -ENOENT;
1074                 goto unlock;
1075         }
1076
1077         /* Bounds check destination. */
1078         if (args->offset > obj->base.size ||
1079             args->size > obj->base.size - args->offset) {
1080                 ret = -EINVAL;
1081                 goto out;
1082         }
1083
1084         /* prime objects have no backing filp to GEM pread/pwrite
1085          * pages from.
1086          */
1087         if (!obj->base.filp) {
1088                 ret = -EINVAL;
1089                 goto out;
1090         }
1091
1092         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1093
1094         ret = -EFAULT;
1095         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1096          * it would end up going through the fenced access, and we'll get
1097          * different detiling behavior between reading and writing.
1098          * pread/pwrite currently are reading and writing from the CPU
1099          * perspective, requiring manual detiling by the client.
1100          */
1101         if (obj->tiling_mode == I915_TILING_NONE &&
1102             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1103             cpu_write_needs_clflush(obj)) {
1104                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1105                 /* Note that the gtt paths might fail with non-page-backed user
1106                  * pointers (e.g. gtt mappings when moving data between
1107                  * textures). Fallback to the shmem path in that case. */
1108         }
1109
1110         if (ret == -EFAULT || ret == -ENOSPC) {
1111                 if (obj->phys_handle)
1112                         ret = i915_gem_phys_pwrite(obj, args, file);
1113                 else
1114                         ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1115         }
1116
1117 out:
1118         drm_gem_object_unreference(&obj->base);
1119 unlock:
1120         mutex_unlock(&dev->struct_mutex);
1121 put_rpm:
1122         intel_runtime_pm_put(dev_priv);
1123
1124         return ret;
1125 }
1126
1127 int
1128 i915_gem_check_wedge(struct i915_gpu_error *error,
1129                      bool interruptible)
1130 {
1131         if (i915_reset_in_progress(error)) {
1132                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1133                  * -EIO unconditionally for these. */
1134                 if (!interruptible)
1135                         return -EIO;
1136
1137                 /* Recovery complete, but the reset failed ... */
1138                 if (i915_terminally_wedged(error))
1139                         return -EIO;
1140
1141                 /*
1142                  * Check if GPU Reset is in progress - we need intel_ring_begin
1143                  * to work properly to reinit the hw state while the gpu is
1144                  * still marked as reset-in-progress. Handle this with a flag.
1145                  */
1146                 if (!error->reload_in_reset)
1147                         return -EAGAIN;
1148         }
1149
1150         return 0;
1151 }
1152
1153 /*
1154  * Compare arbitrary request against outstanding lazy request. Emit on match.
1155  */
1156 int
1157 i915_gem_check_olr(struct drm_i915_gem_request *req)
1158 {
1159         int ret;
1160
1161         WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1162
1163         ret = 0;
1164         if (req == req->ring->outstanding_lazy_request)
1165                 ret = i915_add_request(req->ring);
1166
1167         return ret;
1168 }
1169
1170 static void fake_irq(unsigned long data)
1171 {
1172         wake_up_process((struct task_struct *)data);
1173 }
1174
1175 static bool missed_irq(struct drm_i915_private *dev_priv,
1176                        struct intel_engine_cs *ring)
1177 {
1178         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1179 }
1180
1181 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1182 {
1183         if (file_priv == NULL)
1184                 return true;
1185
1186         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1187 }
1188
1189 /**
1190  * __i915_wait_request - wait until execution of request has finished
1191  * @req: duh!
1192  * @reset_counter: reset sequence associated with the given request
1193  * @interruptible: do an interruptible wait (normally yes)
1194  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1195  *
1196  * Note: It is of utmost importance that the passed in seqno and reset_counter
1197  * values have been read by the caller in an smp safe manner. Where read-side
1198  * locks are involved, it is sufficient to read the reset_counter before
1199  * unlocking the lock that protects the seqno. For lockless tricks, the
1200  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1201  * inserted.
1202  *
1203  * Returns 0 if the request was found within the alloted time. Else returns the
1204  * errno with remaining time filled in timeout argument.
1205  */
1206 int __i915_wait_request(struct drm_i915_gem_request *req,
1207                         unsigned reset_counter,
1208                         bool interruptible,
1209                         s64 *timeout,
1210                         struct drm_i915_file_private *file_priv)
1211 {
1212         struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1213         struct drm_device *dev = ring->dev;
1214         struct drm_i915_private *dev_priv = dev->dev_private;
1215         const bool irq_test_in_progress =
1216                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1217         DEFINE_WAIT(wait);
1218         unsigned long timeout_expire;
1219         s64 before, now;
1220         int ret;
1221
1222         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1223
1224         if (i915_gem_request_completed(req, true))
1225                 return 0;
1226
1227         timeout_expire = timeout ?
1228                 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1229
1230         if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1231                 gen6_rps_boost(dev_priv);
1232                 if (file_priv)
1233                         mod_delayed_work(dev_priv->wq,
1234                                          &file_priv->mm.idle_work,
1235                                          msecs_to_jiffies(100));
1236         }
1237
1238         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1239                 return -ENODEV;
1240
1241         /* Record current time in case interrupted by signal, or wedged */
1242         trace_i915_gem_request_wait_begin(req);
1243         before = ktime_get_raw_ns();
1244         for (;;) {
1245                 struct timer_list timer;
1246
1247                 prepare_to_wait(&ring->irq_queue, &wait,
1248                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1249
1250                 /* We need to check whether any gpu reset happened in between
1251                  * the caller grabbing the seqno and now ... */
1252                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1253                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1254                          * is truely gone. */
1255                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1256                         if (ret == 0)
1257                                 ret = -EAGAIN;
1258                         break;
1259                 }
1260
1261                 if (i915_gem_request_completed(req, false)) {
1262                         ret = 0;
1263                         break;
1264                 }
1265
1266                 if (interruptible && signal_pending(current)) {
1267                         ret = -ERESTARTSYS;
1268                         break;
1269                 }
1270
1271                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1272                         ret = -ETIME;
1273                         break;
1274                 }
1275
1276                 timer.function = NULL;
1277                 if (timeout || missed_irq(dev_priv, ring)) {
1278                         unsigned long expire;
1279
1280                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1281                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1282                         mod_timer(&timer, expire);
1283                 }
1284
1285                 io_schedule();
1286
1287                 if (timer.function) {
1288                         del_singleshot_timer_sync(&timer);
1289                         destroy_timer_on_stack(&timer);
1290                 }
1291         }
1292         now = ktime_get_raw_ns();
1293         trace_i915_gem_request_wait_end(req);
1294
1295         if (!irq_test_in_progress)
1296                 ring->irq_put(ring);
1297
1298         finish_wait(&ring->irq_queue, &wait);
1299
1300         if (timeout) {
1301                 s64 tres = *timeout - (now - before);
1302
1303                 *timeout = tres < 0 ? 0 : tres;
1304
1305                 /*
1306                  * Apparently ktime isn't accurate enough and occasionally has a
1307                  * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1308                  * things up to make the test happy. We allow up to 1 jiffy.
1309                  *
1310                  * This is a regrssion from the timespec->ktime conversion.
1311                  */
1312                 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1313                         *timeout = 0;
1314         }
1315
1316         return ret;
1317 }
1318
1319 /**
1320  * Waits for a request to be signaled, and cleans up the
1321  * request and object lists appropriately for that event.
1322  */
1323 int
1324 i915_wait_request(struct drm_i915_gem_request *req)
1325 {
1326         struct drm_device *dev;
1327         struct drm_i915_private *dev_priv;
1328         bool interruptible;
1329         unsigned reset_counter;
1330         int ret;
1331
1332         BUG_ON(req == NULL);
1333
1334         dev = req->ring->dev;
1335         dev_priv = dev->dev_private;
1336         interruptible = dev_priv->mm.interruptible;
1337
1338         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1339
1340         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1341         if (ret)
1342                 return ret;
1343
1344         ret = i915_gem_check_olr(req);
1345         if (ret)
1346                 return ret;
1347
1348         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1349         i915_gem_request_reference(req);
1350         ret = __i915_wait_request(req, reset_counter,
1351                                   interruptible, NULL, NULL);
1352         i915_gem_request_unreference(req);
1353         return ret;
1354 }
1355
1356 static int
1357 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1358 {
1359         if (!obj->active)
1360                 return 0;
1361
1362         /* Manually manage the write flush as we may have not yet
1363          * retired the buffer.
1364          *
1365          * Note that the last_write_req is always the earlier of
1366          * the two (read/write) requests, so if we haved successfully waited,
1367          * we know we have passed the last write.
1368          */
1369         i915_gem_request_assign(&obj->last_write_req, NULL);
1370
1371         return 0;
1372 }
1373
1374 /**
1375  * Ensures that all rendering to the object has completed and the object is
1376  * safe to unbind from the GTT or access from the CPU.
1377  */
1378 static __must_check int
1379 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1380                                bool readonly)
1381 {
1382         struct drm_i915_gem_request *req;
1383         int ret;
1384
1385         req = readonly ? obj->last_write_req : obj->last_read_req;
1386         if (!req)
1387                 return 0;
1388
1389         ret = i915_wait_request(req);
1390         if (ret)
1391                 return ret;
1392
1393         return i915_gem_object_wait_rendering__tail(obj);
1394 }
1395
1396 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1397  * as the object state may change during this call.
1398  */
1399 static __must_check int
1400 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1401                                             struct drm_i915_file_private *file_priv,
1402                                             bool readonly)
1403 {
1404         struct drm_i915_gem_request *req;
1405         struct drm_device *dev = obj->base.dev;
1406         struct drm_i915_private *dev_priv = dev->dev_private;
1407         unsigned reset_counter;
1408         int ret;
1409
1410         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1411         BUG_ON(!dev_priv->mm.interruptible);
1412
1413         req = readonly ? obj->last_write_req : obj->last_read_req;
1414         if (!req)
1415                 return 0;
1416
1417         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1418         if (ret)
1419                 return ret;
1420
1421         ret = i915_gem_check_olr(req);
1422         if (ret)
1423                 return ret;
1424
1425         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1426         i915_gem_request_reference(req);
1427         mutex_unlock(&dev->struct_mutex);
1428         ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
1429         mutex_lock(&dev->struct_mutex);
1430         i915_gem_request_unreference(req);
1431         if (ret)
1432                 return ret;
1433
1434         return i915_gem_object_wait_rendering__tail(obj);
1435 }
1436
1437 /**
1438  * Called when user space prepares to use an object with the CPU, either
1439  * through the mmap ioctl's mapping or a GTT mapping.
1440  */
1441 int
1442 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1443                           struct drm_file *file)
1444 {
1445         struct drm_i915_gem_set_domain *args = data;
1446         struct drm_i915_gem_object *obj;
1447         uint32_t read_domains = args->read_domains;
1448         uint32_t write_domain = args->write_domain;
1449         int ret;
1450
1451         /* Only handle setting domains to types used by the CPU. */
1452         if (write_domain & I915_GEM_GPU_DOMAINS)
1453                 return -EINVAL;
1454
1455         if (read_domains & I915_GEM_GPU_DOMAINS)
1456                 return -EINVAL;
1457
1458         /* Having something in the write domain implies it's in the read
1459          * domain, and only that read domain.  Enforce that in the request.
1460          */
1461         if (write_domain != 0 && read_domains != write_domain)
1462                 return -EINVAL;
1463
1464         ret = i915_mutex_lock_interruptible(dev);
1465         if (ret)
1466                 return ret;
1467
1468         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1469         if (&obj->base == NULL) {
1470                 ret = -ENOENT;
1471                 goto unlock;
1472         }
1473
1474         /* Try to flush the object off the GPU without holding the lock.
1475          * We will repeat the flush holding the lock in the normal manner
1476          * to catch cases where we are gazumped.
1477          */
1478         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1479                                                           file->driver_priv,
1480                                                           !write_domain);
1481         if (ret)
1482                 goto unref;
1483
1484         if (read_domains & I915_GEM_DOMAIN_GTT)
1485                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1486         else
1487                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1488
1489 unref:
1490         drm_gem_object_unreference(&obj->base);
1491 unlock:
1492         mutex_unlock(&dev->struct_mutex);
1493         return ret;
1494 }
1495
1496 /**
1497  * Called when user space has done writes to this buffer
1498  */
1499 int
1500 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1501                          struct drm_file *file)
1502 {
1503         struct drm_i915_gem_sw_finish *args = data;
1504         struct drm_i915_gem_object *obj;
1505         int ret = 0;
1506
1507         ret = i915_mutex_lock_interruptible(dev);
1508         if (ret)
1509                 return ret;
1510
1511         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1512         if (&obj->base == NULL) {
1513                 ret = -ENOENT;
1514                 goto unlock;
1515         }
1516
1517         /* Pinned buffers may be scanout, so flush the cache */
1518         if (obj->pin_display)
1519                 i915_gem_object_flush_cpu_write_domain(obj);
1520
1521         drm_gem_object_unreference(&obj->base);
1522 unlock:
1523         mutex_unlock(&dev->struct_mutex);
1524         return ret;
1525 }
1526
1527 /**
1528  * Maps the contents of an object, returning the address it is mapped
1529  * into.
1530  *
1531  * While the mapping holds a reference on the contents of the object, it doesn't
1532  * imply a ref on the object itself.
1533  *
1534  * IMPORTANT:
1535  *
1536  * DRM driver writers who look a this function as an example for how to do GEM
1537  * mmap support, please don't implement mmap support like here. The modern way
1538  * to implement DRM mmap support is with an mmap offset ioctl (like
1539  * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1540  * That way debug tooling like valgrind will understand what's going on, hiding
1541  * the mmap call in a driver private ioctl will break that. The i915 driver only
1542  * does cpu mmaps this way because we didn't know better.
1543  */
1544 int
1545 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1546                     struct drm_file *file)
1547 {
1548         struct drm_i915_gem_mmap *args = data;
1549         struct drm_gem_object *obj;
1550         unsigned long addr;
1551
1552         if (args->flags & ~(I915_MMAP_WC))
1553                 return -EINVAL;
1554
1555         if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1556                 return -ENODEV;
1557
1558         obj = drm_gem_object_lookup(dev, file, args->handle);
1559         if (obj == NULL)
1560                 return -ENOENT;
1561
1562         /* prime objects have no backing filp to GEM mmap
1563          * pages from.
1564          */
1565         if (!obj->filp) {
1566                 drm_gem_object_unreference_unlocked(obj);
1567                 return -EINVAL;
1568         }
1569
1570         addr = vm_mmap(obj->filp, 0, args->size,
1571                        PROT_READ | PROT_WRITE, MAP_SHARED,
1572                        args->offset);
1573         if (args->flags & I915_MMAP_WC) {
1574                 struct mm_struct *mm = current->mm;
1575                 struct vm_area_struct *vma;
1576
1577                 down_write(&mm->mmap_sem);
1578                 vma = find_vma(mm, addr);
1579                 if (vma)
1580                         vma->vm_page_prot =
1581                                 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1582                 else
1583                         addr = -ENOMEM;
1584                 up_write(&mm->mmap_sem);
1585         }
1586         drm_gem_object_unreference_unlocked(obj);
1587         if (IS_ERR((void *)addr))
1588                 return addr;
1589
1590         args->addr_ptr = (uint64_t) addr;
1591
1592         return 0;
1593 }
1594
1595 /**
1596  * i915_gem_fault - fault a page into the GTT
1597  * vma: VMA in question
1598  * vmf: fault info
1599  *
1600  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1601  * from userspace.  The fault handler takes care of binding the object to
1602  * the GTT (if needed), allocating and programming a fence register (again,
1603  * only if needed based on whether the old reg is still valid or the object
1604  * is tiled) and inserting a new PTE into the faulting process.
1605  *
1606  * Note that the faulting process may involve evicting existing objects
1607  * from the GTT and/or fence registers to make room.  So performance may
1608  * suffer if the GTT working set is large or there are few fence registers
1609  * left.
1610  */
1611 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1612 {
1613         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1614         struct drm_device *dev = obj->base.dev;
1615         struct drm_i915_private *dev_priv = dev->dev_private;
1616         pgoff_t page_offset;
1617         unsigned long pfn;
1618         int ret = 0;
1619         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1620
1621         intel_runtime_pm_get(dev_priv);
1622
1623         /* We don't use vmf->pgoff since that has the fake offset */
1624         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1625                 PAGE_SHIFT;
1626
1627         ret = i915_mutex_lock_interruptible(dev);
1628         if (ret)
1629                 goto out;
1630
1631         trace_i915_gem_object_fault(obj, page_offset, true, write);
1632
1633         /* Try to flush the object off the GPU first without holding the lock.
1634          * Upon reacquiring the lock, we will perform our sanity checks and then
1635          * repeat the flush holding the lock in the normal manner to catch cases
1636          * where we are gazumped.
1637          */
1638         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1639         if (ret)
1640                 goto unlock;
1641
1642         /* Access to snoopable pages through the GTT is incoherent. */
1643         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1644                 ret = -EFAULT;
1645                 goto unlock;
1646         }
1647
1648         /* Now bind it into the GTT if needed */
1649         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1650         if (ret)
1651                 goto unlock;
1652
1653         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1654         if (ret)
1655                 goto unpin;
1656
1657         ret = i915_gem_object_get_fence(obj);
1658         if (ret)
1659                 goto unpin;
1660
1661         /* Finally, remap it using the new GTT offset */
1662         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1663         pfn >>= PAGE_SHIFT;
1664
1665         if (!obj->fault_mappable) {
1666                 unsigned long size = min_t(unsigned long,
1667                                            vma->vm_end - vma->vm_start,
1668                                            obj->base.size);
1669                 int i;
1670
1671                 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1672                         ret = vm_insert_pfn(vma,
1673                                             (unsigned long)vma->vm_start + i * PAGE_SIZE,
1674                                             pfn + i);
1675                         if (ret)
1676                                 break;
1677                 }
1678
1679                 obj->fault_mappable = true;
1680         } else
1681                 ret = vm_insert_pfn(vma,
1682                                     (unsigned long)vmf->virtual_address,
1683                                     pfn + page_offset);
1684 unpin:
1685         i915_gem_object_ggtt_unpin(obj);
1686 unlock:
1687         mutex_unlock(&dev->struct_mutex);
1688 out:
1689         switch (ret) {
1690         case -EIO:
1691                 /*
1692                  * We eat errors when the gpu is terminally wedged to avoid
1693                  * userspace unduly crashing (gl has no provisions for mmaps to
1694                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
1695                  * and so needs to be reported.
1696                  */
1697                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1698                         ret = VM_FAULT_SIGBUS;
1699                         break;
1700                 }
1701         case -EAGAIN:
1702                 /*
1703                  * EAGAIN means the gpu is hung and we'll wait for the error
1704                  * handler to reset everything when re-faulting in
1705                  * i915_mutex_lock_interruptible.
1706                  */
1707         case 0:
1708         case -ERESTARTSYS:
1709         case -EINTR:
1710         case -EBUSY:
1711                 /*
1712                  * EBUSY is ok: this just means that another thread
1713                  * already did the job.
1714                  */
1715                 ret = VM_FAULT_NOPAGE;
1716                 break;
1717         case -ENOMEM:
1718                 ret = VM_FAULT_OOM;
1719                 break;
1720         case -ENOSPC:
1721         case -EFAULT:
1722                 ret = VM_FAULT_SIGBUS;
1723                 break;
1724         default:
1725                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1726                 ret = VM_FAULT_SIGBUS;
1727                 break;
1728         }
1729
1730         intel_runtime_pm_put(dev_priv);
1731         return ret;
1732 }
1733
1734 /**
1735  * i915_gem_release_mmap - remove physical page mappings
1736  * @obj: obj in question
1737  *
1738  * Preserve the reservation of the mmapping with the DRM core code, but
1739  * relinquish ownership of the pages back to the system.
1740  *
1741  * It is vital that we remove the page mapping if we have mapped a tiled
1742  * object through the GTT and then lose the fence register due to
1743  * resource pressure. Similarly if the object has been moved out of the
1744  * aperture, than pages mapped into userspace must be revoked. Removing the
1745  * mapping will then trigger a page fault on the next user access, allowing
1746  * fixup by i915_gem_fault().
1747  */
1748 void
1749 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1750 {
1751         if (!obj->fault_mappable)
1752                 return;
1753
1754         drm_vma_node_unmap(&obj->base.vma_node,
1755                            obj->base.dev->anon_inode->i_mapping);
1756         obj->fault_mappable = false;
1757 }
1758
1759 void
1760 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1761 {
1762         struct drm_i915_gem_object *obj;
1763
1764         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1765                 i915_gem_release_mmap(obj);
1766 }
1767
1768 uint32_t
1769 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1770 {
1771         uint32_t gtt_size;
1772
1773         if (INTEL_INFO(dev)->gen >= 4 ||
1774             tiling_mode == I915_TILING_NONE)
1775                 return size;
1776
1777         /* Previous chips need a power-of-two fence region when tiling */
1778         if (INTEL_INFO(dev)->gen == 3)
1779                 gtt_size = 1024*1024;
1780         else
1781                 gtt_size = 512*1024;
1782
1783         while (gtt_size < size)
1784                 gtt_size <<= 1;
1785
1786         return gtt_size;
1787 }
1788
1789 /**
1790  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1791  * @obj: object to check
1792  *
1793  * Return the required GTT alignment for an object, taking into account
1794  * potential fence register mapping.
1795  */
1796 uint32_t
1797 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1798                            int tiling_mode, bool fenced)
1799 {
1800         /*
1801          * Minimum alignment is 4k (GTT page size), but might be greater
1802          * if a fence register is needed for the object.
1803          */
1804         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1805             tiling_mode == I915_TILING_NONE)
1806                 return 4096;
1807
1808         /*
1809          * Previous chips need to be aligned to the size of the smallest
1810          * fence register that can contain the object.
1811          */
1812         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1813 }
1814
1815 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1816 {
1817         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1818         int ret;
1819
1820         if (drm_vma_node_has_offset(&obj->base.vma_node))
1821                 return 0;
1822
1823         dev_priv->mm.shrinker_no_lock_stealing = true;
1824
1825         ret = drm_gem_create_mmap_offset(&obj->base);
1826         if (ret != -ENOSPC)
1827                 goto out;
1828
1829         /* Badly fragmented mmap space? The only way we can recover
1830          * space is by destroying unwanted objects. We can't randomly release
1831          * mmap_offsets as userspace expects them to be persistent for the
1832          * lifetime of the objects. The closest we can is to release the
1833          * offsets on purgeable objects by truncating it and marking it purged,
1834          * which prevents userspace from ever using that object again.
1835          */
1836         i915_gem_shrink(dev_priv,
1837                         obj->base.size >> PAGE_SHIFT,
1838                         I915_SHRINK_BOUND |
1839                         I915_SHRINK_UNBOUND |
1840                         I915_SHRINK_PURGEABLE);
1841         ret = drm_gem_create_mmap_offset(&obj->base);
1842         if (ret != -ENOSPC)
1843                 goto out;
1844
1845         i915_gem_shrink_all(dev_priv);
1846         ret = drm_gem_create_mmap_offset(&obj->base);
1847 out:
1848         dev_priv->mm.shrinker_no_lock_stealing = false;
1849
1850         return ret;
1851 }
1852
1853 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1854 {
1855         drm_gem_free_mmap_offset(&obj->base);
1856 }
1857
1858 int
1859 i915_gem_mmap_gtt(struct drm_file *file,
1860                   struct drm_device *dev,
1861                   uint32_t handle,
1862                   uint64_t *offset)
1863 {
1864         struct drm_i915_private *dev_priv = dev->dev_private;
1865         struct drm_i915_gem_object *obj;
1866         int ret;
1867
1868         ret = i915_mutex_lock_interruptible(dev);
1869         if (ret)
1870                 return ret;
1871
1872         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1873         if (&obj->base == NULL) {
1874                 ret = -ENOENT;
1875                 goto unlock;
1876         }
1877
1878         if (obj->base.size > dev_priv->gtt.mappable_end) {
1879                 ret = -E2BIG;
1880                 goto out;
1881         }
1882
1883         if (obj->madv != I915_MADV_WILLNEED) {
1884                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1885                 ret = -EFAULT;
1886                 goto out;
1887         }
1888
1889         ret = i915_gem_object_create_mmap_offset(obj);
1890         if (ret)
1891                 goto out;
1892
1893         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1894
1895 out:
1896         drm_gem_object_unreference(&obj->base);
1897 unlock:
1898         mutex_unlock(&dev->struct_mutex);
1899         return ret;
1900 }
1901
1902 /**
1903  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1904  * @dev: DRM device
1905  * @data: GTT mapping ioctl data
1906  * @file: GEM object info
1907  *
1908  * Simply returns the fake offset to userspace so it can mmap it.
1909  * The mmap call will end up in drm_gem_mmap(), which will set things
1910  * up so we can get faults in the handler above.
1911  *
1912  * The fault handler will take care of binding the object into the GTT
1913  * (since it may have been evicted to make room for something), allocating
1914  * a fence register, and mapping the appropriate aperture address into
1915  * userspace.
1916  */
1917 int
1918 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1919                         struct drm_file *file)
1920 {
1921         struct drm_i915_gem_mmap_gtt *args = data;
1922
1923         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1924 }
1925
1926 static inline int
1927 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1928 {
1929         return obj->madv == I915_MADV_DONTNEED;
1930 }
1931
1932 /* Immediately discard the backing storage */
1933 static void
1934 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1935 {
1936         i915_gem_object_free_mmap_offset(obj);
1937
1938         if (obj->base.filp == NULL)
1939                 return;
1940
1941         /* Our goal here is to return as much of the memory as
1942          * is possible back to the system as we are called from OOM.
1943          * To do this we must instruct the shmfs to drop all of its
1944          * backing pages, *now*.
1945          */
1946         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1947         obj->madv = __I915_MADV_PURGED;
1948 }
1949
1950 /* Try to discard unwanted pages */
1951 static void
1952 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1953 {
1954         struct address_space *mapping;
1955
1956         switch (obj->madv) {
1957         case I915_MADV_DONTNEED:
1958                 i915_gem_object_truncate(obj);
1959         case __I915_MADV_PURGED:
1960                 return;
1961         }
1962
1963         if (obj->base.filp == NULL)
1964                 return;
1965
1966         mapping = file_inode(obj->base.filp)->i_mapping,
1967         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1968 }
1969
1970 static void
1971 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1972 {
1973         struct sg_page_iter sg_iter;
1974         int ret;
1975
1976         BUG_ON(obj->madv == __I915_MADV_PURGED);
1977
1978         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1979         if (ret) {
1980                 /* In the event of a disaster, abandon all caches and
1981                  * hope for the best.
1982                  */
1983                 WARN_ON(ret != -EIO);
1984                 i915_gem_clflush_object(obj, true);
1985                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1986         }
1987
1988         if (i915_gem_object_needs_bit17_swizzle(obj))
1989                 i915_gem_object_save_bit_17_swizzle(obj);
1990
1991         if (obj->madv == I915_MADV_DONTNEED)
1992                 obj->dirty = 0;
1993
1994         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1995                 struct page *page = sg_page_iter_page(&sg_iter);
1996
1997                 if (obj->dirty)
1998                         set_page_dirty(page);
1999
2000                 if (obj->madv == I915_MADV_WILLNEED)
2001                         mark_page_accessed(page);
2002
2003                 page_cache_release(page);
2004         }
2005         obj->dirty = 0;
2006
2007         sg_free_table(obj->pages);
2008         kfree(obj->pages);
2009 }
2010
2011 int
2012 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2013 {
2014         const struct drm_i915_gem_object_ops *ops = obj->ops;
2015
2016         if (obj->pages == NULL)
2017                 return 0;
2018
2019         if (obj->pages_pin_count)
2020                 return -EBUSY;
2021
2022         BUG_ON(i915_gem_obj_bound_any(obj));
2023
2024         /* ->put_pages might need to allocate memory for the bit17 swizzle
2025          * array, hence protect them from being reaped by removing them from gtt
2026          * lists early. */
2027         list_del(&obj->global_list);
2028
2029         ops->put_pages(obj);
2030         obj->pages = NULL;
2031
2032         i915_gem_object_invalidate(obj);
2033
2034         return 0;
2035 }
2036
2037 unsigned long
2038 i915_gem_shrink(struct drm_i915_private *dev_priv,
2039                 long target, unsigned flags)
2040 {
2041         const struct {
2042                 struct list_head *list;
2043                 unsigned int bit;
2044         } phases[] = {
2045                 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2046                 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2047                 { NULL, 0 },
2048         }, *phase;
2049         unsigned long count = 0;
2050
2051         /*
2052          * As we may completely rewrite the (un)bound list whilst unbinding
2053          * (due to retiring requests) we have to strictly process only
2054          * one element of the list at the time, and recheck the list
2055          * on every iteration.
2056          *
2057          * In particular, we must hold a reference whilst removing the
2058          * object as we may end up waiting for and/or retiring the objects.
2059          * This might release the final reference (held by the active list)
2060          * and result in the object being freed from under us. This is
2061          * similar to the precautions the eviction code must take whilst
2062          * removing objects.
2063          *
2064          * Also note that although these lists do not hold a reference to
2065          * the object we can safely grab one here: The final object
2066          * unreferencing and the bound_list are both protected by the
2067          * dev->struct_mutex and so we won't ever be able to observe an
2068          * object on the bound_list with a reference count equals 0.
2069          */
2070         for (phase = phases; phase->list; phase++) {
2071                 struct list_head still_in_list;
2072
2073                 if ((flags & phase->bit) == 0)
2074                         continue;
2075
2076                 INIT_LIST_HEAD(&still_in_list);
2077                 while (count < target && !list_empty(phase->list)) {
2078                         struct drm_i915_gem_object *obj;
2079                         struct i915_vma *vma, *v;
2080
2081                         obj = list_first_entry(phase->list,
2082                                                typeof(*obj), global_list);
2083                         list_move_tail(&obj->global_list, &still_in_list);
2084
2085                         if (flags & I915_SHRINK_PURGEABLE &&
2086                             !i915_gem_object_is_purgeable(obj))
2087                                 continue;
2088
2089                         drm_gem_object_reference(&obj->base);
2090
2091                         /* For the unbound phase, this should be a no-op! */
2092                         list_for_each_entry_safe(vma, v,
2093                                                  &obj->vma_list, vma_link)
2094                                 if (i915_vma_unbind(vma))
2095                                         break;
2096
2097                         if (i915_gem_object_put_pages(obj) == 0)
2098                                 count += obj->base.size >> PAGE_SHIFT;
2099
2100                         drm_gem_object_unreference(&obj->base);
2101                 }
2102                 list_splice(&still_in_list, phase->list);
2103         }
2104
2105         return count;
2106 }
2107
2108 static unsigned long
2109 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2110 {
2111         i915_gem_evict_everything(dev_priv->dev);
2112         return i915_gem_shrink(dev_priv, LONG_MAX,
2113                                I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2114 }
2115
2116 static int
2117 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2118 {
2119         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2120         int page_count, i;
2121         struct address_space *mapping;
2122         struct sg_table *st;
2123         struct scatterlist *sg;
2124         struct sg_page_iter sg_iter;
2125         struct page *page;
2126         unsigned long last_pfn = 0;     /* suppress gcc warning */
2127         gfp_t gfp;
2128
2129         /* Assert that the object is not currently in any GPU domain. As it
2130          * wasn't in the GTT, there shouldn't be any way it could have been in
2131          * a GPU cache
2132          */
2133         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2134         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2135
2136         st = kmalloc(sizeof(*st), GFP_KERNEL);
2137         if (st == NULL)
2138                 return -ENOMEM;
2139
2140         page_count = obj->base.size / PAGE_SIZE;
2141         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2142                 kfree(st);
2143                 return -ENOMEM;
2144         }
2145
2146         /* Get the list of pages out of our struct file.  They'll be pinned
2147          * at this point until we release them.
2148          *
2149          * Fail silently without starting the shrinker
2150          */
2151         mapping = file_inode(obj->base.filp)->i_mapping;
2152         gfp = mapping_gfp_mask(mapping);
2153         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2154         gfp &= ~(__GFP_IO | __GFP_WAIT);
2155         sg = st->sgl;
2156         st->nents = 0;
2157         for (i = 0; i < page_count; i++) {
2158                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2159                 if (IS_ERR(page)) {
2160                         i915_gem_shrink(dev_priv,
2161                                         page_count,
2162                                         I915_SHRINK_BOUND |
2163                                         I915_SHRINK_UNBOUND |
2164                                         I915_SHRINK_PURGEABLE);
2165                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2166                 }
2167                 if (IS_ERR(page)) {
2168                         /* We've tried hard to allocate the memory by reaping
2169                          * our own buffer, now let the real VM do its job and
2170                          * go down in flames if truly OOM.
2171                          */
2172                         i915_gem_shrink_all(dev_priv);
2173                         page = shmem_read_mapping_page(mapping, i);
2174                         if (IS_ERR(page))
2175                                 goto err_pages;
2176                 }
2177 #ifdef CONFIG_SWIOTLB
2178                 if (swiotlb_nr_tbl()) {
2179                         st->nents++;
2180                         sg_set_page(sg, page, PAGE_SIZE, 0);
2181                         sg = sg_next(sg);
2182                         continue;
2183                 }
2184 #endif
2185                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2186                         if (i)
2187                                 sg = sg_next(sg);
2188                         st->nents++;
2189                         sg_set_page(sg, page, PAGE_SIZE, 0);
2190                 } else {
2191                         sg->length += PAGE_SIZE;
2192                 }
2193                 last_pfn = page_to_pfn(page);
2194
2195                 /* Check that the i965g/gm workaround works. */
2196                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2197         }
2198 #ifdef CONFIG_SWIOTLB
2199         if (!swiotlb_nr_tbl())
2200 #endif
2201                 sg_mark_end(sg);
2202         obj->pages = st;
2203
2204         if (i915_gem_object_needs_bit17_swizzle(obj))
2205                 i915_gem_object_do_bit_17_swizzle(obj);
2206
2207         if (obj->tiling_mode != I915_TILING_NONE &&
2208             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2209                 i915_gem_object_pin_pages(obj);
2210
2211         return 0;
2212
2213 err_pages:
2214         sg_mark_end(sg);
2215         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2216                 page_cache_release(sg_page_iter_page(&sg_iter));
2217         sg_free_table(st);
2218         kfree(st);
2219
2220         /* shmemfs first checks if there is enough memory to allocate the page
2221          * and reports ENOSPC should there be insufficient, along with the usual
2222          * ENOMEM for a genuine allocation failure.
2223          *
2224          * We use ENOSPC in our driver to mean that we have run out of aperture
2225          * space and so want to translate the error from shmemfs back to our
2226          * usual understanding of ENOMEM.
2227          */
2228         if (PTR_ERR(page) == -ENOSPC)
2229                 return -ENOMEM;
2230         else
2231                 return PTR_ERR(page);
2232 }
2233
2234 /* Ensure that the associated pages are gathered from the backing storage
2235  * and pinned into our object. i915_gem_object_get_pages() may be called
2236  * multiple times before they are released by a single call to
2237  * i915_gem_object_put_pages() - once the pages are no longer referenced
2238  * either as a result of memory pressure (reaping pages under the shrinker)
2239  * or as the object is itself released.
2240  */
2241 int
2242 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2243 {
2244         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2245         const struct drm_i915_gem_object_ops *ops = obj->ops;
2246         int ret;
2247
2248         if (obj->pages)
2249                 return 0;
2250
2251         if (obj->madv != I915_MADV_WILLNEED) {
2252                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2253                 return -EFAULT;
2254         }
2255
2256         BUG_ON(obj->pages_pin_count);
2257
2258         ret = ops->get_pages(obj);
2259         if (ret)
2260                 return ret;
2261
2262         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2263         return 0;
2264 }
2265
2266 static void
2267 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2268                                struct intel_engine_cs *ring)
2269 {
2270         struct drm_i915_gem_request *req;
2271         struct intel_engine_cs *old_ring;
2272
2273         BUG_ON(ring == NULL);
2274
2275         req = intel_ring_get_request(ring);
2276         old_ring = i915_gem_request_get_ring(obj->last_read_req);
2277
2278         if (old_ring != ring && obj->last_write_req) {
2279                 /* Keep the request relative to the current ring */
2280                 i915_gem_request_assign(&obj->last_write_req, req);
2281         }
2282
2283         /* Add a reference if we're newly entering the active list. */
2284         if (!obj->active) {
2285                 drm_gem_object_reference(&obj->base);
2286                 obj->active = 1;
2287         }
2288
2289         list_move_tail(&obj->ring_list, &ring->active_list);
2290
2291         i915_gem_request_assign(&obj->last_read_req, req);
2292 }
2293
2294 void i915_vma_move_to_active(struct i915_vma *vma,
2295                              struct intel_engine_cs *ring)
2296 {
2297         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2298         return i915_gem_object_move_to_active(vma->obj, ring);
2299 }
2300
2301 static void
2302 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2303 {
2304         struct i915_vma *vma;
2305
2306         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2307         BUG_ON(!obj->active);
2308
2309         list_for_each_entry(vma, &obj->vma_list, vma_link) {
2310                 if (!list_empty(&vma->mm_list))
2311                         list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2312         }
2313
2314         intel_fb_obj_flush(obj, true);
2315
2316         list_del_init(&obj->ring_list);
2317
2318         i915_gem_request_assign(&obj->last_read_req, NULL);
2319         i915_gem_request_assign(&obj->last_write_req, NULL);
2320         obj->base.write_domain = 0;
2321
2322         i915_gem_request_assign(&obj->last_fenced_req, NULL);
2323
2324         obj->active = 0;
2325         drm_gem_object_unreference(&obj->base);
2326
2327         WARN_ON(i915_verify_lists(dev));
2328 }
2329
2330 static void
2331 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2332 {
2333         if (obj->last_read_req == NULL)
2334                 return;
2335
2336         if (i915_gem_request_completed(obj->last_read_req, true))
2337                 i915_gem_object_move_to_inactive(obj);
2338 }
2339
2340 static int
2341 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2342 {
2343         struct drm_i915_private *dev_priv = dev->dev_private;
2344         struct intel_engine_cs *ring;
2345         int ret, i, j;
2346
2347         /* Carefully retire all requests without writing to the rings */
2348         for_each_ring(ring, dev_priv, i) {
2349                 ret = intel_ring_idle(ring);
2350                 if (ret)
2351                         return ret;
2352         }
2353         i915_gem_retire_requests(dev);
2354
2355         /* Finally reset hw state */
2356         for_each_ring(ring, dev_priv, i) {
2357                 intel_ring_init_seqno(ring, seqno);
2358
2359                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2360                         ring->semaphore.sync_seqno[j] = 0;
2361         }
2362
2363         return 0;
2364 }
2365
2366 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2367 {
2368         struct drm_i915_private *dev_priv = dev->dev_private;
2369         int ret;
2370
2371         if (seqno == 0)
2372                 return -EINVAL;
2373
2374         /* HWS page needs to be set less than what we
2375          * will inject to ring
2376          */
2377         ret = i915_gem_init_seqno(dev, seqno - 1);
2378         if (ret)
2379                 return ret;
2380
2381         /* Carefully set the last_seqno value so that wrap
2382          * detection still works
2383          */
2384         dev_priv->next_seqno = seqno;
2385         dev_priv->last_seqno = seqno - 1;
2386         if (dev_priv->last_seqno == 0)
2387                 dev_priv->last_seqno--;
2388
2389         return 0;
2390 }
2391
2392 int
2393 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2394 {
2395         struct drm_i915_private *dev_priv = dev->dev_private;
2396
2397         /* reserve 0 for non-seqno */
2398         if (dev_priv->next_seqno == 0) {
2399                 int ret = i915_gem_init_seqno(dev, 0);
2400                 if (ret)
2401                         return ret;
2402
2403                 dev_priv->next_seqno = 1;
2404         }
2405
2406         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2407         return 0;
2408 }
2409
2410 int __i915_add_request(struct intel_engine_cs *ring,
2411                        struct drm_file *file,
2412                        struct drm_i915_gem_object *obj)
2413 {
2414         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2415         struct drm_i915_gem_request *request;
2416         struct intel_ringbuffer *ringbuf;
2417         u32 request_start;
2418         int ret;
2419
2420         request = ring->outstanding_lazy_request;
2421         if (WARN_ON(request == NULL))
2422                 return -ENOMEM;
2423
2424         if (i915.enable_execlists) {
2425                 ringbuf = request->ctx->engine[ring->id].ringbuf;
2426         } else
2427                 ringbuf = ring->buffer;
2428
2429         request_start = intel_ring_get_tail(ringbuf);
2430         /*
2431          * Emit any outstanding flushes - execbuf can fail to emit the flush
2432          * after having emitted the batchbuffer command. Hence we need to fix
2433          * things up similar to emitting the lazy request. The difference here
2434          * is that the flush _must_ happen before the next request, no matter
2435          * what.
2436          */
2437         if (i915.enable_execlists) {
2438                 ret = logical_ring_flush_all_caches(ringbuf, request->ctx);
2439                 if (ret)
2440                         return ret;
2441         } else {
2442                 ret = intel_ring_flush_all_caches(ring);
2443                 if (ret)
2444                         return ret;
2445         }
2446
2447         /* Record the position of the start of the request so that
2448          * should we detect the updated seqno part-way through the
2449          * GPU processing the request, we never over-estimate the
2450          * position of the head.
2451          */
2452         request->postfix = intel_ring_get_tail(ringbuf);
2453
2454         if (i915.enable_execlists) {
2455                 ret = ring->emit_request(ringbuf, request);
2456                 if (ret)
2457                         return ret;
2458         } else {
2459                 ret = ring->add_request(ring);
2460                 if (ret)
2461                         return ret;
2462         }
2463
2464         request->head = request_start;
2465         request->tail = intel_ring_get_tail(ringbuf);
2466
2467         /* Whilst this request exists, batch_obj will be on the
2468          * active_list, and so will hold the active reference. Only when this
2469          * request is retired will the the batch_obj be moved onto the
2470          * inactive_list and lose its active reference. Hence we do not need
2471          * to explicitly hold another reference here.
2472          */
2473         request->batch_obj = obj;
2474
2475         if (!i915.enable_execlists) {
2476                 /* Hold a reference to the current context so that we can inspect
2477                  * it later in case a hangcheck error event fires.
2478                  */
2479                 request->ctx = ring->last_context;
2480                 if (request->ctx)
2481                         i915_gem_context_reference(request->ctx);
2482         }
2483
2484         request->emitted_jiffies = jiffies;
2485         list_add_tail(&request->list, &ring->request_list);
2486         request->file_priv = NULL;
2487
2488         if (file) {
2489                 struct drm_i915_file_private *file_priv = file->driver_priv;
2490
2491                 spin_lock(&file_priv->mm.lock);
2492                 request->file_priv = file_priv;
2493                 list_add_tail(&request->client_list,
2494                               &file_priv->mm.request_list);
2495                 spin_unlock(&file_priv->mm.lock);
2496
2497                 request->pid = get_pid(task_pid(current));
2498         }
2499
2500         trace_i915_gem_request_add(request);
2501         ring->outstanding_lazy_request = NULL;
2502
2503         i915_queue_hangcheck(ring->dev);
2504
2505         cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2506         queue_delayed_work(dev_priv->wq,
2507                            &dev_priv->mm.retire_work,
2508                            round_jiffies_up_relative(HZ));
2509         intel_mark_busy(dev_priv->dev);
2510
2511         return 0;
2512 }
2513
2514 static inline void
2515 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2516 {
2517         struct drm_i915_file_private *file_priv = request->file_priv;
2518
2519         if (!file_priv)
2520                 return;
2521
2522         spin_lock(&file_priv->mm.lock);
2523         list_del(&request->client_list);
2524         request->file_priv = NULL;
2525         spin_unlock(&file_priv->mm.lock);
2526 }
2527
2528 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2529                                    const struct intel_context *ctx)
2530 {
2531         unsigned long elapsed;
2532
2533         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2534
2535         if (ctx->hang_stats.banned)
2536                 return true;
2537
2538         if (ctx->hang_stats.ban_period_seconds &&
2539             elapsed <= ctx->hang_stats.ban_period_seconds) {
2540                 if (!i915_gem_context_is_default(ctx)) {
2541                         DRM_DEBUG("context hanging too fast, banning!\n");
2542                         return true;
2543                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2544                         if (i915_stop_ring_allow_warn(dev_priv))
2545                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2546                         return true;
2547                 }
2548         }
2549
2550         return false;
2551 }
2552
2553 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2554                                   struct intel_context *ctx,
2555                                   const bool guilty)
2556 {
2557         struct i915_ctx_hang_stats *hs;
2558
2559         if (WARN_ON(!ctx))
2560                 return;
2561
2562         hs = &ctx->hang_stats;
2563
2564         if (guilty) {
2565                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2566                 hs->batch_active++;
2567                 hs->guilty_ts = get_seconds();
2568         } else {
2569                 hs->batch_pending++;
2570         }
2571 }
2572
2573 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2574 {
2575         list_del(&request->list);
2576         i915_gem_request_remove_from_client(request);
2577
2578         put_pid(request->pid);
2579
2580         i915_gem_request_unreference(request);
2581 }
2582
2583 void i915_gem_request_free(struct kref *req_ref)
2584 {
2585         struct drm_i915_gem_request *req = container_of(req_ref,
2586                                                  typeof(*req), ref);
2587         struct intel_context *ctx = req->ctx;
2588
2589         if (ctx) {
2590                 if (i915.enable_execlists) {
2591                         struct intel_engine_cs *ring = req->ring;
2592
2593                         if (ctx != ring->default_context)
2594                                 intel_lr_context_unpin(ring, ctx);
2595                 }
2596
2597                 i915_gem_context_unreference(ctx);
2598         }
2599
2600         kfree(req);
2601 }
2602
2603 struct drm_i915_gem_request *
2604 i915_gem_find_active_request(struct intel_engine_cs *ring)
2605 {
2606         struct drm_i915_gem_request *request;
2607
2608         list_for_each_entry(request, &ring->request_list, list) {
2609                 if (i915_gem_request_completed(request, false))
2610                         continue;
2611
2612                 return request;
2613         }
2614
2615         return NULL;
2616 }
2617
2618 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2619                                        struct intel_engine_cs *ring)
2620 {
2621         struct drm_i915_gem_request *request;
2622         bool ring_hung;
2623
2624         request = i915_gem_find_active_request(ring);
2625
2626         if (request == NULL)
2627                 return;
2628
2629         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2630
2631         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2632
2633         list_for_each_entry_continue(request, &ring->request_list, list)
2634                 i915_set_reset_status(dev_priv, request->ctx, false);
2635 }
2636
2637 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2638                                         struct intel_engine_cs *ring)
2639 {
2640         while (!list_empty(&ring->active_list)) {
2641                 struct drm_i915_gem_object *obj;
2642
2643                 obj = list_first_entry(&ring->active_list,
2644                                        struct drm_i915_gem_object,
2645                                        ring_list);
2646
2647                 i915_gem_object_move_to_inactive(obj);
2648         }
2649
2650         /*
2651          * Clear the execlists queue up before freeing the requests, as those
2652          * are the ones that keep the context and ringbuffer backing objects
2653          * pinned in place.
2654          */
2655         while (!list_empty(&ring->execlist_queue)) {
2656                 struct drm_i915_gem_request *submit_req;
2657
2658                 submit_req = list_first_entry(&ring->execlist_queue,
2659                                 struct drm_i915_gem_request,
2660                                 execlist_link);
2661                 list_del(&submit_req->execlist_link);
2662                 intel_runtime_pm_put(dev_priv);
2663
2664                 if (submit_req->ctx != ring->default_context)
2665                         intel_lr_context_unpin(ring, submit_req->ctx);
2666
2667                 i915_gem_context_unreference(submit_req->ctx);
2668                 kfree(submit_req);
2669         }
2670
2671         /*
2672          * We must free the requests after all the corresponding objects have
2673          * been moved off active lists. Which is the same order as the normal
2674          * retire_requests function does. This is important if object hold
2675          * implicit references on things like e.g. ppgtt address spaces through
2676          * the request.
2677          */
2678         while (!list_empty(&ring->request_list)) {
2679                 struct drm_i915_gem_request *request;
2680
2681                 request = list_first_entry(&ring->request_list,
2682                                            struct drm_i915_gem_request,
2683                                            list);
2684
2685                 i915_gem_free_request(request);
2686         }
2687
2688         /* This may not have been flushed before the reset, so clean it now */
2689         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2690 }
2691
2692 void i915_gem_restore_fences(struct drm_device *dev)
2693 {
2694         struct drm_i915_private *dev_priv = dev->dev_private;
2695         int i;
2696
2697         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2698                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2699
2700                 /*
2701                  * Commit delayed tiling changes if we have an object still
2702                  * attached to the fence, otherwise just clear the fence.
2703                  */
2704                 if (reg->obj) {
2705                         i915_gem_object_update_fence(reg->obj, reg,
2706                                                      reg->obj->tiling_mode);
2707                 } else {
2708                         i915_gem_write_fence(dev, i, NULL);
2709                 }
2710         }
2711 }
2712
2713 void i915_gem_reset(struct drm_device *dev)
2714 {
2715         struct drm_i915_private *dev_priv = dev->dev_private;
2716         struct intel_engine_cs *ring;
2717         int i;
2718
2719         /*
2720          * Before we free the objects from the requests, we need to inspect
2721          * them for finding the guilty party. As the requests only borrow
2722          * their reference to the objects, the inspection must be done first.
2723          */
2724         for_each_ring(ring, dev_priv, i)
2725                 i915_gem_reset_ring_status(dev_priv, ring);
2726
2727         for_each_ring(ring, dev_priv, i)
2728                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2729
2730         i915_gem_context_reset(dev);
2731
2732         i915_gem_restore_fences(dev);
2733 }
2734
2735 /**
2736  * This function clears the request list as sequence numbers are passed.
2737  */
2738 void
2739 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2740 {
2741         if (list_empty(&ring->request_list))
2742                 return;
2743
2744         WARN_ON(i915_verify_lists(ring->dev));
2745
2746         /* Move any buffers on the active list that are no longer referenced
2747          * by the ringbuffer to the flushing/inactive lists as appropriate,
2748          * before we free the context associated with the requests.
2749          */
2750         while (!list_empty(&ring->active_list)) {
2751                 struct drm_i915_gem_object *obj;
2752
2753                 obj = list_first_entry(&ring->active_list,
2754                                       struct drm_i915_gem_object,
2755                                       ring_list);
2756
2757                 if (!i915_gem_request_completed(obj->last_read_req, true))
2758                         break;
2759
2760                 i915_gem_object_move_to_inactive(obj);
2761         }
2762
2763
2764         while (!list_empty(&ring->request_list)) {
2765                 struct drm_i915_gem_request *request;
2766                 struct intel_ringbuffer *ringbuf;
2767
2768                 request = list_first_entry(&ring->request_list,
2769                                            struct drm_i915_gem_request,
2770                                            list);
2771
2772                 if (!i915_gem_request_completed(request, true))
2773                         break;
2774
2775                 trace_i915_gem_request_retire(request);
2776
2777                 /* This is one of the few common intersection points
2778                  * between legacy ringbuffer submission and execlists:
2779                  * we need to tell them apart in order to find the correct
2780                  * ringbuffer to which the request belongs to.
2781                  */
2782                 if (i915.enable_execlists) {
2783                         struct intel_context *ctx = request->ctx;
2784                         ringbuf = ctx->engine[ring->id].ringbuf;
2785                 } else
2786                         ringbuf = ring->buffer;
2787
2788                 /* We know the GPU must have read the request to have
2789                  * sent us the seqno + interrupt, so use the position
2790                  * of tail of the request to update the last known position
2791                  * of the GPU head.
2792                  */
2793                 ringbuf->last_retired_head = request->postfix;
2794
2795                 i915_gem_free_request(request);
2796         }
2797
2798         if (unlikely(ring->trace_irq_req &&
2799                      i915_gem_request_completed(ring->trace_irq_req, true))) {
2800                 ring->irq_put(ring);
2801                 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2802         }
2803
2804         WARN_ON(i915_verify_lists(ring->dev));
2805 }
2806
2807 bool
2808 i915_gem_retire_requests(struct drm_device *dev)
2809 {
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811         struct intel_engine_cs *ring;
2812         bool idle = true;
2813         int i;
2814
2815         for_each_ring(ring, dev_priv, i) {
2816                 i915_gem_retire_requests_ring(ring);
2817                 idle &= list_empty(&ring->request_list);
2818                 if (i915.enable_execlists) {
2819                         unsigned long flags;
2820
2821                         spin_lock_irqsave(&ring->execlist_lock, flags);
2822                         idle &= list_empty(&ring->execlist_queue);
2823                         spin_unlock_irqrestore(&ring->execlist_lock, flags);
2824
2825                         intel_execlists_retire_requests(ring);
2826                 }
2827         }
2828
2829         if (idle)
2830                 mod_delayed_work(dev_priv->wq,
2831                                    &dev_priv->mm.idle_work,
2832                                    msecs_to_jiffies(100));
2833
2834         return idle;
2835 }
2836
2837 static void
2838 i915_gem_retire_work_handler(struct work_struct *work)
2839 {
2840         struct drm_i915_private *dev_priv =
2841                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2842         struct drm_device *dev = dev_priv->dev;
2843         bool idle;
2844
2845         /* Come back later if the device is busy... */
2846         idle = false;
2847         if (mutex_trylock(&dev->struct_mutex)) {
2848                 idle = i915_gem_retire_requests(dev);
2849                 mutex_unlock(&dev->struct_mutex);
2850         }
2851         if (!idle)
2852                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2853                                    round_jiffies_up_relative(HZ));
2854 }
2855
2856 static void
2857 i915_gem_idle_work_handler(struct work_struct *work)
2858 {
2859         struct drm_i915_private *dev_priv =
2860                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2861
2862         intel_mark_idle(dev_priv->dev);
2863 }
2864
2865 /**
2866  * Ensures that an object will eventually get non-busy by flushing any required
2867  * write domains, emitting any outstanding lazy request and retiring and
2868  * completed requests.
2869  */
2870 static int
2871 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2872 {
2873         struct intel_engine_cs *ring;
2874         int ret;
2875
2876         if (obj->active) {
2877                 ring = i915_gem_request_get_ring(obj->last_read_req);
2878
2879                 ret = i915_gem_check_olr(obj->last_read_req);
2880                 if (ret)
2881                         return ret;
2882
2883                 i915_gem_retire_requests_ring(ring);
2884         }
2885
2886         return 0;
2887 }
2888
2889 /**
2890  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2891  * @DRM_IOCTL_ARGS: standard ioctl arguments
2892  *
2893  * Returns 0 if successful, else an error is returned with the remaining time in
2894  * the timeout parameter.
2895  *  -ETIME: object is still busy after timeout
2896  *  -ERESTARTSYS: signal interrupted the wait
2897  *  -ENONENT: object doesn't exist
2898  * Also possible, but rare:
2899  *  -EAGAIN: GPU wedged
2900  *  -ENOMEM: damn
2901  *  -ENODEV: Internal IRQ fail
2902  *  -E?: The add request failed
2903  *
2904  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2905  * non-zero timeout parameter the wait ioctl will wait for the given number of
2906  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2907  * without holding struct_mutex the object may become re-busied before this
2908  * function completes. A similar but shorter * race condition exists in the busy
2909  * ioctl
2910  */
2911 int
2912 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2913 {
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915         struct drm_i915_gem_wait *args = data;
2916         struct drm_i915_gem_object *obj;
2917         struct drm_i915_gem_request *req;
2918         unsigned reset_counter;
2919         int ret = 0;
2920
2921         if (args->flags != 0)
2922                 return -EINVAL;
2923
2924         ret = i915_mutex_lock_interruptible(dev);
2925         if (ret)
2926                 return ret;
2927
2928         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2929         if (&obj->base == NULL) {
2930                 mutex_unlock(&dev->struct_mutex);
2931                 return -ENOENT;
2932         }
2933
2934         /* Need to make sure the object gets inactive eventually. */
2935         ret = i915_gem_object_flush_active(obj);
2936         if (ret)
2937                 goto out;
2938
2939         if (!obj->active || !obj->last_read_req)
2940                 goto out;
2941
2942         req = obj->last_read_req;
2943
2944         /* Do this after OLR check to make sure we make forward progress polling
2945          * on this IOCTL with a timeout <=0 (like busy ioctl)
2946          */
2947         if (args->timeout_ns <= 0) {
2948                 ret = -ETIME;
2949                 goto out;
2950         }
2951
2952         drm_gem_object_unreference(&obj->base);
2953         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2954         i915_gem_request_reference(req);
2955         mutex_unlock(&dev->struct_mutex);
2956
2957         ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns,
2958                                   file->driver_priv);
2959         mutex_lock(&dev->struct_mutex);
2960         i915_gem_request_unreference(req);
2961         mutex_unlock(&dev->struct_mutex);
2962         return ret;
2963
2964 out:
2965         drm_gem_object_unreference(&obj->base);
2966         mutex_unlock(&dev->struct_mutex);
2967         return ret;
2968 }
2969
2970 /**
2971  * i915_gem_object_sync - sync an object to a ring.
2972  *
2973  * @obj: object which may be in use on another ring.
2974  * @to: ring we wish to use the object on. May be NULL.
2975  *
2976  * This code is meant to abstract object synchronization with the GPU.
2977  * Calling with NULL implies synchronizing the object with the CPU
2978  * rather than a particular GPU ring.
2979  *
2980  * Returns 0 if successful, else propagates up the lower layer error.
2981  */
2982 int
2983 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2984                      struct intel_engine_cs *to)
2985 {
2986         struct intel_engine_cs *from;
2987         u32 seqno;
2988         int ret, idx;
2989
2990         from = i915_gem_request_get_ring(obj->last_read_req);
2991
2992         if (from == NULL || to == from)
2993                 return 0;
2994
2995         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2996                 return i915_gem_object_wait_rendering(obj, false);
2997
2998         idx = intel_ring_sync_index(from, to);
2999
3000         seqno = i915_gem_request_get_seqno(obj->last_read_req);
3001         /* Optimization: Avoid semaphore sync when we are sure we already
3002          * waited for an object with higher seqno */
3003         if (seqno <= from->semaphore.sync_seqno[idx])
3004                 return 0;
3005
3006         ret = i915_gem_check_olr(obj->last_read_req);
3007         if (ret)
3008                 return ret;
3009
3010         trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
3011         ret = to->semaphore.sync_to(to, from, seqno);
3012         if (!ret)
3013                 /* We use last_read_req because sync_to()
3014                  * might have just caused seqno wrap under
3015                  * the radar.
3016                  */
3017                 from->semaphore.sync_seqno[idx] =
3018                                 i915_gem_request_get_seqno(obj->last_read_req);
3019
3020         return ret;
3021 }
3022
3023 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3024 {
3025         u32 old_write_domain, old_read_domains;
3026
3027         /* Force a pagefault for domain tracking on next user access */
3028         i915_gem_release_mmap(obj);
3029
3030         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3031                 return;
3032
3033         /* Wait for any direct GTT access to complete */
3034         mb();
3035
3036         old_read_domains = obj->base.read_domains;
3037         old_write_domain = obj->base.write_domain;
3038
3039         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3040         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3041
3042         trace_i915_gem_object_change_domain(obj,
3043                                             old_read_domains,
3044                                             old_write_domain);
3045 }
3046
3047 int i915_vma_unbind(struct i915_vma *vma)
3048 {
3049         struct drm_i915_gem_object *obj = vma->obj;
3050         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3051         int ret;
3052
3053         if (list_empty(&vma->vma_link))
3054                 return 0;
3055
3056         if (!drm_mm_node_allocated(&vma->node)) {
3057                 i915_gem_vma_destroy(vma);
3058                 return 0;
3059         }
3060
3061         if (vma->pin_count)
3062                 return -EBUSY;
3063
3064         BUG_ON(obj->pages == NULL);
3065
3066         ret = i915_gem_object_finish_gpu(obj);
3067         if (ret)
3068                 return ret;
3069         /* Continue on if we fail due to EIO, the GPU is hung so we
3070          * should be safe and we need to cleanup or else we might
3071          * cause memory corruption through use-after-free.
3072          */
3073
3074         if (i915_is_ggtt(vma->vm) &&
3075             vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3076                 i915_gem_object_finish_gtt(obj);
3077
3078                 /* release the fence reg _after_ flushing */
3079                 ret = i915_gem_object_put_fence(obj);
3080                 if (ret)
3081                         return ret;
3082         }
3083
3084         trace_i915_vma_unbind(vma);
3085
3086         vma->unbind_vma(vma);
3087
3088         list_del_init(&vma->mm_list);
3089         if (i915_is_ggtt(vma->vm)) {
3090                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3091                         obj->map_and_fenceable = false;
3092                 } else if (vma->ggtt_view.pages) {
3093                         sg_free_table(vma->ggtt_view.pages);
3094                         kfree(vma->ggtt_view.pages);
3095                         vma->ggtt_view.pages = NULL;
3096                 }
3097         }
3098
3099         drm_mm_remove_node(&vma->node);
3100         i915_gem_vma_destroy(vma);
3101
3102         /* Since the unbound list is global, only move to that list if
3103          * no more VMAs exist. */
3104         if (list_empty(&obj->vma_list)) {
3105                 /* Throw away the active reference before
3106                  * moving to the unbound list. */
3107                 i915_gem_object_retire(obj);
3108
3109                 i915_gem_gtt_finish_object(obj);
3110                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3111         }
3112
3113         /* And finally now the object is completely decoupled from this vma,
3114          * we can drop its hold on the backing storage and allow it to be
3115          * reaped by the shrinker.
3116          */
3117         i915_gem_object_unpin_pages(obj);
3118
3119         return 0;
3120 }
3121
3122 int i915_gpu_idle(struct drm_device *dev)
3123 {
3124         struct drm_i915_private *dev_priv = dev->dev_private;
3125         struct intel_engine_cs *ring;
3126         int ret, i;
3127
3128         /* Flush everything onto the inactive list. */
3129         for_each_ring(ring, dev_priv, i) {
3130                 if (!i915.enable_execlists) {
3131                         ret = i915_switch_context(ring, ring->default_context);
3132                         if (ret)
3133                                 return ret;
3134                 }
3135
3136                 ret = intel_ring_idle(ring);
3137                 if (ret)
3138                         return ret;
3139         }
3140
3141         return 0;
3142 }
3143
3144 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3145                                  struct drm_i915_gem_object *obj)
3146 {
3147         struct drm_i915_private *dev_priv = dev->dev_private;
3148         int fence_reg;
3149         int fence_pitch_shift;
3150
3151         if (INTEL_INFO(dev)->gen >= 6) {
3152                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3153                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3154         } else {
3155                 fence_reg = FENCE_REG_965_0;
3156                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3157         }
3158
3159         fence_reg += reg * 8;
3160
3161         /* To w/a incoherency with non-atomic 64-bit register updates,
3162          * we split the 64-bit update into two 32-bit writes. In order
3163          * for a partial fence not to be evaluated between writes, we
3164          * precede the update with write to turn off the fence register,
3165          * and only enable the fence as the last step.
3166          *
3167          * For extra levels of paranoia, we make sure each step lands
3168          * before applying the next step.
3169          */
3170         I915_WRITE(fence_reg, 0);
3171         POSTING_READ(fence_reg);
3172
3173         if (obj) {
3174                 u32 size = i915_gem_obj_ggtt_size(obj);
3175                 uint64_t val;
3176
3177                 /* Adjust fence size to match tiled area */
3178                 if (obj->tiling_mode != I915_TILING_NONE) {
3179                         uint32_t row_size = obj->stride *
3180                                 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
3181                         size = (size / row_size) * row_size;
3182                 }
3183
3184                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3185                                  0xfffff000) << 32;
3186                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3187                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3188                 if (obj->tiling_mode == I915_TILING_Y)
3189                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3190                 val |= I965_FENCE_REG_VALID;
3191
3192                 I915_WRITE(fence_reg + 4, val >> 32);
3193                 POSTING_READ(fence_reg + 4);
3194
3195                 I915_WRITE(fence_reg + 0, val);
3196                 POSTING_READ(fence_reg);
3197         } else {
3198                 I915_WRITE(fence_reg + 4, 0);
3199                 POSTING_READ(fence_reg + 4);
3200         }
3201 }
3202
3203 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3204                                  struct drm_i915_gem_object *obj)
3205 {
3206         struct drm_i915_private *dev_priv = dev->dev_private;
3207         u32 val;
3208
3209         if (obj) {
3210                 u32 size = i915_gem_obj_ggtt_size(obj);
3211                 int pitch_val;
3212                 int tile_width;
3213
3214                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3215                      (size & -size) != size ||
3216                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3217                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3218                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3219
3220                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3221                         tile_width = 128;
3222                 else
3223                         tile_width = 512;
3224
3225                 /* Note: pitch better be a power of two tile widths */
3226                 pitch_val = obj->stride / tile_width;
3227                 pitch_val = ffs(pitch_val) - 1;
3228
3229                 val = i915_gem_obj_ggtt_offset(obj);
3230                 if (obj->tiling_mode == I915_TILING_Y)
3231                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3232                 val |= I915_FENCE_SIZE_BITS(size);
3233                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3234                 val |= I830_FENCE_REG_VALID;
3235         } else
3236                 val = 0;
3237
3238         if (reg < 8)
3239                 reg = FENCE_REG_830_0 + reg * 4;
3240         else
3241                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3242
3243         I915_WRITE(reg, val);
3244         POSTING_READ(reg);
3245 }
3246
3247 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3248                                 struct drm_i915_gem_object *obj)
3249 {
3250         struct drm_i915_private *dev_priv = dev->dev_private;
3251         uint32_t val;
3252
3253         if (obj) {
3254                 u32 size = i915_gem_obj_ggtt_size(obj);
3255                 uint32_t pitch_val;
3256
3257                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3258                      (size & -size) != size ||
3259                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3260                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3261                      i915_gem_obj_ggtt_offset(obj), size);
3262
3263                 pitch_val = obj->stride / 128;
3264                 pitch_val = ffs(pitch_val) - 1;
3265
3266                 val = i915_gem_obj_ggtt_offset(obj);
3267                 if (obj->tiling_mode == I915_TILING_Y)
3268                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3269                 val |= I830_FENCE_SIZE_BITS(size);
3270                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3271                 val |= I830_FENCE_REG_VALID;
3272         } else
3273                 val = 0;
3274
3275         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3276         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3277 }
3278
3279 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3280 {
3281         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3282 }
3283
3284 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3285                                  struct drm_i915_gem_object *obj)
3286 {
3287         struct drm_i915_private *dev_priv = dev->dev_private;
3288
3289         /* Ensure that all CPU reads are completed before installing a fence
3290          * and all writes before removing the fence.
3291          */
3292         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3293                 mb();
3294
3295         WARN(obj && (!obj->stride || !obj->tiling_mode),
3296              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3297              obj->stride, obj->tiling_mode);
3298
3299         if (IS_GEN2(dev))
3300                 i830_write_fence_reg(dev, reg, obj);
3301         else if (IS_GEN3(dev))
3302                 i915_write_fence_reg(dev, reg, obj);
3303         else if (INTEL_INFO(dev)->gen >= 4)
3304                 i965_write_fence_reg(dev, reg, obj);
3305
3306         /* And similarly be paranoid that no direct access to this region
3307          * is reordered to before the fence is installed.
3308          */
3309         if (i915_gem_object_needs_mb(obj))
3310                 mb();
3311 }
3312
3313 static inline int fence_number(struct drm_i915_private *dev_priv,
3314                                struct drm_i915_fence_reg *fence)
3315 {
3316         return fence - dev_priv->fence_regs;
3317 }
3318
3319 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3320                                          struct drm_i915_fence_reg *fence,
3321                                          bool enable)
3322 {
3323         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3324         int reg = fence_number(dev_priv, fence);
3325
3326         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3327
3328         if (enable) {
3329                 obj->fence_reg = reg;
3330                 fence->obj = obj;
3331                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3332         } else {
3333                 obj->fence_reg = I915_FENCE_REG_NONE;
3334                 fence->obj = NULL;
3335                 list_del_init(&fence->lru_list);
3336         }
3337         obj->fence_dirty = false;
3338 }
3339
3340 static int
3341 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3342 {
3343         if (obj->last_fenced_req) {
3344                 int ret = i915_wait_request(obj->last_fenced_req);
3345                 if (ret)
3346                         return ret;
3347
3348                 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3349         }
3350
3351         return 0;
3352 }
3353
3354 int
3355 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3356 {
3357         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3358         struct drm_i915_fence_reg *fence;
3359         int ret;
3360
3361         ret = i915_gem_object_wait_fence(obj);
3362         if (ret)
3363                 return ret;
3364
3365         if (obj->fence_reg == I915_FENCE_REG_NONE)
3366                 return 0;
3367
3368         fence = &dev_priv->fence_regs[obj->fence_reg];
3369
3370         if (WARN_ON(fence->pin_count))
3371                 return -EBUSY;
3372
3373         i915_gem_object_fence_lost(obj);
3374         i915_gem_object_update_fence(obj, fence, false);
3375
3376         return 0;
3377 }
3378
3379 static struct drm_i915_fence_reg *
3380 i915_find_fence_reg(struct drm_device *dev)
3381 {
3382         struct drm_i915_private *dev_priv = dev->dev_private;
3383         struct drm_i915_fence_reg *reg, *avail;
3384         int i;
3385
3386         /* First try to find a free reg */
3387         avail = NULL;
3388         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3389                 reg = &dev_priv->fence_regs[i];
3390                 if (!reg->obj)
3391                         return reg;
3392
3393                 if (!reg->pin_count)
3394                         avail = reg;
3395         }
3396
3397         if (avail == NULL)
3398                 goto deadlock;
3399
3400         /* None available, try to steal one or wait for a user to finish */
3401         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3402                 if (reg->pin_count)
3403                         continue;
3404
3405                 return reg;
3406         }
3407
3408 deadlock:
3409         /* Wait for completion of pending flips which consume fences */
3410         if (intel_has_pending_fb_unpin(dev))
3411                 return ERR_PTR(-EAGAIN);
3412
3413         return ERR_PTR(-EDEADLK);
3414 }
3415
3416 /**
3417  * i915_gem_object_get_fence - set up fencing for an object
3418  * @obj: object to map through a fence reg
3419  *
3420  * When mapping objects through the GTT, userspace wants to be able to write
3421  * to them without having to worry about swizzling if the object is tiled.
3422  * This function walks the fence regs looking for a free one for @obj,
3423  * stealing one if it can't find any.
3424  *
3425  * It then sets up the reg based on the object's properties: address, pitch
3426  * and tiling format.
3427  *
3428  * For an untiled surface, this removes any existing fence.
3429  */
3430 int
3431 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3432 {
3433         struct drm_device *dev = obj->base.dev;
3434         struct drm_i915_private *dev_priv = dev->dev_private;
3435         bool enable = obj->tiling_mode != I915_TILING_NONE;
3436         struct drm_i915_fence_reg *reg;
3437         int ret;
3438
3439         /* Have we updated the tiling parameters upon the object and so
3440          * will need to serialise the write to the associated fence register?
3441          */
3442         if (obj->fence_dirty) {
3443                 ret = i915_gem_object_wait_fence(obj);
3444                 if (ret)
3445                         return ret;
3446         }
3447
3448         /* Just update our place in the LRU if our fence is getting reused. */
3449         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3450                 reg = &dev_priv->fence_regs[obj->fence_reg];
3451                 if (!obj->fence_dirty) {
3452                         list_move_tail(&reg->lru_list,
3453                                        &dev_priv->mm.fence_list);
3454                         return 0;
3455                 }
3456         } else if (enable) {
3457                 if (WARN_ON(!obj->map_and_fenceable))
3458                         return -EINVAL;
3459
3460                 reg = i915_find_fence_reg(dev);
3461                 if (IS_ERR(reg))
3462                         return PTR_ERR(reg);
3463
3464                 if (reg->obj) {
3465                         struct drm_i915_gem_object *old = reg->obj;
3466
3467                         ret = i915_gem_object_wait_fence(old);
3468                         if (ret)
3469                                 return ret;
3470
3471                         i915_gem_object_fence_lost(old);
3472                 }
3473         } else
3474                 return 0;
3475
3476         i915_gem_object_update_fence(obj, reg, enable);
3477
3478         return 0;
3479 }
3480
3481 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3482                                      unsigned long cache_level)
3483 {
3484         struct drm_mm_node *gtt_space = &vma->node;
3485         struct drm_mm_node *other;
3486
3487         /*
3488          * On some machines we have to be careful when putting differing types
3489          * of snoopable memory together to avoid the prefetcher crossing memory
3490          * domains and dying. During vm initialisation, we decide whether or not
3491          * these constraints apply and set the drm_mm.color_adjust
3492          * appropriately.
3493          */
3494         if (vma->vm->mm.color_adjust == NULL)
3495                 return true;
3496
3497         if (!drm_mm_node_allocated(gtt_space))
3498                 return true;
3499
3500         if (list_empty(&gtt_space->node_list))
3501                 return true;
3502
3503         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3504         if (other->allocated && !other->hole_follows && other->color != cache_level)
3505                 return false;
3506
3507         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3508         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3509                 return false;
3510
3511         return true;
3512 }
3513
3514 /**
3515  * Finds free space in the GTT aperture and binds the object there.
3516  */
3517 static struct i915_vma *
3518 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3519                            struct i915_address_space *vm,
3520                            unsigned alignment,
3521                            uint64_t flags,
3522                            const struct i915_ggtt_view *view)
3523 {
3524         struct drm_device *dev = obj->base.dev;
3525         struct drm_i915_private *dev_priv = dev->dev_private;
3526         u32 size, fence_size, fence_alignment, unfenced_alignment;
3527         unsigned long start =
3528                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3529         unsigned long end =
3530                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3531         struct i915_vma *vma;
3532         int ret;
3533
3534         fence_size = i915_gem_get_gtt_size(dev,
3535                                            obj->base.size,
3536                                            obj->tiling_mode);
3537         fence_alignment = i915_gem_get_gtt_alignment(dev,
3538                                                      obj->base.size,
3539                                                      obj->tiling_mode, true);
3540         unfenced_alignment =
3541                 i915_gem_get_gtt_alignment(dev,
3542                                            obj->base.size,
3543                                            obj->tiling_mode, false);
3544
3545         if (alignment == 0)
3546                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3547                                                 unfenced_alignment;
3548         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3549                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3550                 return ERR_PTR(-EINVAL);
3551         }
3552
3553         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3554
3555         /* If the object is bigger than the entire aperture, reject it early
3556          * before evicting everything in a vain attempt to find space.
3557          */
3558         if (obj->base.size > end) {
3559                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3560                           obj->base.size,
3561                           flags & PIN_MAPPABLE ? "mappable" : "total",
3562                           end);
3563                 return ERR_PTR(-E2BIG);
3564         }
3565
3566         ret = i915_gem_object_get_pages(obj);
3567         if (ret)
3568                 return ERR_PTR(ret);
3569
3570         i915_gem_object_pin_pages(obj);
3571
3572         vma = i915_gem_obj_lookup_or_create_vma_view(obj, vm, view);
3573         if (IS_ERR(vma))
3574                 goto err_unpin;
3575
3576 search_free:
3577         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3578                                                   size, alignment,
3579                                                   obj->cache_level,
3580                                                   start, end,
3581                                                   DRM_MM_SEARCH_DEFAULT,
3582                                                   DRM_MM_CREATE_DEFAULT);
3583         if (ret) {
3584                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3585                                                obj->cache_level,
3586                                                start, end,
3587                                                flags);
3588                 if (ret == 0)
3589                         goto search_free;
3590
3591                 goto err_free_vma;
3592         }
3593         if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3594                 ret = -EINVAL;
3595                 goto err_remove_node;
3596         }
3597
3598         ret = i915_gem_gtt_prepare_object(obj);
3599         if (ret)
3600                 goto err_remove_node;
3601
3602         trace_i915_vma_bind(vma, flags);
3603         ret = i915_vma_bind(vma, obj->cache_level,
3604                             flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3605         if (ret)
3606                 goto err_finish_gtt;
3607
3608         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3609         list_add_tail(&vma->mm_list, &vm->inactive_list);
3610
3611         return vma;
3612
3613 err_finish_gtt:
3614         i915_gem_gtt_finish_object(obj);
3615 err_remove_node:
3616         drm_mm_remove_node(&vma->node);
3617 err_free_vma:
3618         i915_gem_vma_destroy(vma);
3619         vma = ERR_PTR(ret);
3620 err_unpin:
3621         i915_gem_object_unpin_pages(obj);
3622         return vma;
3623 }
3624
3625 bool
3626 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3627                         bool force)
3628 {
3629         /* If we don't have a page list set up, then we're not pinned
3630          * to GPU, and we can ignore the cache flush because it'll happen
3631          * again at bind time.
3632          */
3633         if (obj->pages == NULL)
3634                 return false;
3635
3636         /*
3637          * Stolen memory is always coherent with the GPU as it is explicitly
3638          * marked as wc by the system, or the system is cache-coherent.
3639          */
3640         if (obj->stolen || obj->phys_handle)
3641                 return false;
3642
3643         /* If the GPU is snooping the contents of the CPU cache,
3644          * we do not need to manually clear the CPU cache lines.  However,
3645          * the caches are only snooped when the render cache is
3646          * flushed/invalidated.  As we always have to emit invalidations
3647          * and flushes when moving into and out of the RENDER domain, correct
3648          * snooping behaviour occurs naturally as the result of our domain
3649          * tracking.
3650          */
3651         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3652                 obj->cache_dirty = true;
3653                 return false;
3654         }
3655
3656         trace_i915_gem_object_clflush(obj);
3657         drm_clflush_sg(obj->pages);
3658         obj->cache_dirty = false;
3659
3660         return true;
3661 }
3662
3663 /** Flushes the GTT write domain for the object if it's dirty. */
3664 static void
3665 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3666 {
3667         uint32_t old_write_domain;
3668
3669         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3670                 return;
3671
3672         /* No actual flushing is required for the GTT write domain.  Writes
3673          * to it immediately go to main memory as far as we know, so there's
3674          * no chipset flush.  It also doesn't land in render cache.
3675          *
3676          * However, we do have to enforce the order so that all writes through
3677          * the GTT land before any writes to the device, such as updates to
3678          * the GATT itself.
3679          */
3680         wmb();
3681
3682         old_write_domain = obj->base.write_domain;
3683         obj->base.write_domain = 0;
3684
3685         intel_fb_obj_flush(obj, false);
3686
3687         trace_i915_gem_object_change_domain(obj,
3688                                             obj->base.read_domains,
3689                                             old_write_domain);
3690 }
3691
3692 /** Flushes the CPU write domain for the object if it's dirty. */
3693 static void
3694 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3695 {
3696         uint32_t old_write_domain;
3697
3698         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3699                 return;
3700
3701         if (i915_gem_clflush_object(obj, obj->pin_display))
3702                 i915_gem_chipset_flush(obj->base.dev);
3703
3704         old_write_domain = obj->base.write_domain;
3705         obj->base.write_domain = 0;
3706
3707         intel_fb_obj_flush(obj, false);
3708
3709         trace_i915_gem_object_change_domain(obj,
3710                                             obj->base.read_domains,
3711                                             old_write_domain);
3712 }
3713
3714 /**
3715  * Moves a single object to the GTT read, and possibly write domain.
3716  *
3717  * This function returns when the move is complete, including waiting on
3718  * flushes to occur.
3719  */
3720 int
3721 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3722 {
3723         uint32_t old_write_domain, old_read_domains;
3724         struct i915_vma *vma;
3725         int ret;
3726
3727         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3728                 return 0;
3729
3730         ret = i915_gem_object_wait_rendering(obj, !write);
3731         if (ret)
3732                 return ret;
3733
3734         i915_gem_object_retire(obj);
3735
3736         /* Flush and acquire obj->pages so that we are coherent through
3737          * direct access in memory with previous cached writes through
3738          * shmemfs and that our cache domain tracking remains valid.
3739          * For example, if the obj->filp was moved to swap without us
3740          * being notified and releasing the pages, we would mistakenly
3741          * continue to assume that the obj remained out of the CPU cached
3742          * domain.
3743          */
3744         ret = i915_gem_object_get_pages(obj);
3745         if (ret)
3746                 return ret;
3747
3748         i915_gem_object_flush_cpu_write_domain(obj);
3749
3750         /* Serialise direct access to this object with the barriers for
3751          * coherent writes from the GPU, by effectively invalidating the
3752          * GTT domain upon first access.
3753          */
3754         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3755                 mb();
3756
3757         old_write_domain = obj->base.write_domain;
3758         old_read_domains = obj->base.read_domains;
3759
3760         /* It should now be out of any other write domains, and we can update
3761          * the domain values for our changes.
3762          */
3763         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3764         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3765         if (write) {
3766                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3767                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3768                 obj->dirty = 1;
3769         }
3770
3771         if (write)
3772                 intel_fb_obj_invalidate(obj, NULL);
3773
3774         trace_i915_gem_object_change_domain(obj,
3775                                             old_read_domains,
3776                                             old_write_domain);
3777
3778         /* And bump the LRU for this access */
3779         vma = i915_gem_obj_to_ggtt(obj);
3780         if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3781                 list_move_tail(&vma->mm_list,
3782                                &to_i915(obj->base.dev)->gtt.base.inactive_list);
3783
3784         return 0;
3785 }
3786
3787 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3788                                     enum i915_cache_level cache_level)
3789 {
3790         struct drm_device *dev = obj->base.dev;
3791         struct i915_vma *vma, *next;
3792         int ret;
3793
3794         if (obj->cache_level == cache_level)
3795                 return 0;
3796
3797         if (i915_gem_obj_is_pinned(obj)) {
3798                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3799                 return -EBUSY;
3800         }
3801
3802         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3803                 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3804                         ret = i915_vma_unbind(vma);
3805                         if (ret)
3806                                 return ret;
3807                 }
3808         }
3809
3810         if (i915_gem_obj_bound_any(obj)) {
3811                 ret = i915_gem_object_finish_gpu(obj);
3812                 if (ret)
3813                         return ret;
3814
3815                 i915_gem_object_finish_gtt(obj);
3816
3817                 /* Before SandyBridge, you could not use tiling or fence
3818                  * registers with snooped memory, so relinquish any fences
3819                  * currently pointing to our region in the aperture.
3820                  */
3821                 if (INTEL_INFO(dev)->gen < 6) {
3822                         ret = i915_gem_object_put_fence(obj);
3823                         if (ret)
3824                                 return ret;
3825                 }
3826
3827                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3828                         if (drm_mm_node_allocated(&vma->node)) {
3829                                 ret = i915_vma_bind(vma, cache_level,
3830                                                     vma->bound & GLOBAL_BIND);
3831                                 if (ret)
3832                                         return ret;
3833                         }
3834         }
3835
3836         list_for_each_entry(vma, &obj->vma_list, vma_link)
3837                 vma->node.color = cache_level;
3838         obj->cache_level = cache_level;
3839
3840         if (obj->cache_dirty &&
3841             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3842             cpu_write_needs_clflush(obj)) {
3843                 if (i915_gem_clflush_object(obj, true))
3844                         i915_gem_chipset_flush(obj->base.dev);
3845         }
3846
3847         return 0;
3848 }
3849
3850 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3851                                struct drm_file *file)
3852 {
3853         struct drm_i915_gem_caching *args = data;
3854         struct drm_i915_gem_object *obj;
3855         int ret;
3856
3857         ret = i915_mutex_lock_interruptible(dev);
3858         if (ret)
3859                 return ret;
3860
3861         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3862         if (&obj->base == NULL) {
3863                 ret = -ENOENT;
3864                 goto unlock;
3865         }
3866
3867         switch (obj->cache_level) {
3868         case I915_CACHE_LLC:
3869         case I915_CACHE_L3_LLC:
3870                 args->caching = I915_CACHING_CACHED;
3871                 break;
3872
3873         case I915_CACHE_WT:
3874                 args->caching = I915_CACHING_DISPLAY;
3875                 break;
3876
3877         default:
3878                 args->caching = I915_CACHING_NONE;
3879                 break;
3880         }
3881
3882         drm_gem_object_unreference(&obj->base);
3883 unlock:
3884         mutex_unlock(&dev->struct_mutex);
3885         return ret;
3886 }
3887
3888 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3889                                struct drm_file *file)
3890 {
3891         struct drm_i915_gem_caching *args = data;
3892         struct drm_i915_gem_object *obj;
3893         enum i915_cache_level level;
3894         int ret;
3895
3896         switch (args->caching) {
3897         case I915_CACHING_NONE:
3898                 level = I915_CACHE_NONE;
3899                 break;
3900         case I915_CACHING_CACHED:
3901                 level = I915_CACHE_LLC;
3902                 break;
3903         case I915_CACHING_DISPLAY:
3904                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3905                 break;
3906         default:
3907                 return -EINVAL;
3908         }
3909
3910         ret = i915_mutex_lock_interruptible(dev);
3911         if (ret)
3912                 return ret;
3913
3914         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3915         if (&obj->base == NULL) {
3916                 ret = -ENOENT;
3917                 goto unlock;
3918         }
3919
3920         ret = i915_gem_object_set_cache_level(obj, level);
3921
3922         drm_gem_object_unreference(&obj->base);
3923 unlock:
3924         mutex_unlock(&dev->struct_mutex);
3925         return ret;
3926 }
3927
3928 static bool is_pin_display(struct drm_i915_gem_object *obj)
3929 {
3930         struct i915_vma *vma;
3931
3932         vma = i915_gem_obj_to_ggtt(obj);
3933         if (!vma)
3934                 return false;
3935
3936         /* There are 2 sources that pin objects:
3937          *   1. The display engine (scanouts, sprites, cursors);
3938          *   2. Reservations for execbuffer;
3939          *
3940          * We can ignore reservations as we hold the struct_mutex and
3941          * are only called outside of the reservation path.
3942          */
3943         return vma->pin_count;
3944 }
3945
3946 /*
3947  * Prepare buffer for display plane (scanout, cursors, etc).
3948  * Can be called from an uninterruptible phase (modesetting) and allows
3949  * any flushes to be pipelined (for pageflips).
3950  */
3951 int
3952 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3953                                      u32 alignment,
3954                                      struct intel_engine_cs *pipelined)
3955 {
3956         u32 old_read_domains, old_write_domain;
3957         bool was_pin_display;
3958         int ret;
3959
3960         if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) {
3961                 ret = i915_gem_object_sync(obj, pipelined);
3962                 if (ret)
3963                         return ret;
3964         }
3965
3966         /* Mark the pin_display early so that we account for the
3967          * display coherency whilst setting up the cache domains.
3968          */
3969         was_pin_display = obj->pin_display;
3970         obj->pin_display = true;
3971
3972         /* The display engine is not coherent with the LLC cache on gen6.  As
3973          * a result, we make sure that the pinning that is about to occur is
3974          * done with uncached PTEs. This is lowest common denominator for all
3975          * chipsets.
3976          *
3977          * However for gen6+, we could do better by using the GFDT bit instead
3978          * of uncaching, which would allow us to flush all the LLC-cached data
3979          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3980          */
3981         ret = i915_gem_object_set_cache_level(obj,
3982                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3983         if (ret)
3984                 goto err_unpin_display;
3985
3986         /* As the user may map the buffer once pinned in the display plane
3987          * (e.g. libkms for the bootup splash), we have to ensure that we
3988          * always use map_and_fenceable for all scanout buffers.
3989          */
3990         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3991         if (ret)
3992                 goto err_unpin_display;
3993
3994         i915_gem_object_flush_cpu_write_domain(obj);
3995
3996         old_write_domain = obj->base.write_domain;
3997         old_read_domains = obj->base.read_domains;
3998
3999         /* It should now be out of any other write domains, and we can update
4000          * the domain values for our changes.
4001          */
4002         obj->base.write_domain = 0;
4003         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4004
4005         trace_i915_gem_object_change_domain(obj,
4006                                             old_read_domains,
4007                                             old_write_domain);
4008
4009         return 0;
4010
4011 err_unpin_display:
4012         WARN_ON(was_pin_display != is_pin_display(obj));
4013         obj->pin_display = was_pin_display;
4014         return ret;
4015 }
4016
4017 void
4018 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
4019 {
4020         i915_gem_object_ggtt_unpin(obj);
4021         obj->pin_display = is_pin_display(obj);
4022 }
4023
4024 int
4025 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4026 {
4027         int ret;
4028
4029         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4030                 return 0;
4031
4032         ret = i915_gem_object_wait_rendering(obj, false);
4033         if (ret)
4034                 return ret;
4035
4036         /* Ensure that we invalidate the GPU's caches and TLBs. */
4037         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4038         return 0;
4039 }
4040
4041 /**
4042  * Moves a single object to the CPU read, and possibly write domain.
4043  *
4044  * This function returns when the move is complete, including waiting on
4045  * flushes to occur.
4046  */
4047 int
4048 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4049 {
4050         uint32_t old_write_domain, old_read_domains;
4051         int ret;
4052
4053         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4054                 return 0;
4055
4056         ret = i915_gem_object_wait_rendering(obj, !write);
4057         if (ret)
4058                 return ret;
4059
4060         i915_gem_object_retire(obj);
4061         i915_gem_object_flush_gtt_write_domain(obj);
4062
4063         old_write_domain = obj->base.write_domain;
4064         old_read_domains = obj->base.read_domains;
4065
4066         /* Flush the CPU cache if it's still invalid. */
4067         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4068                 i915_gem_clflush_object(obj, false);
4069
4070                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4071         }
4072
4073         /* It should now be out of any other write domains, and we can update
4074          * the domain values for our changes.
4075          */
4076         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4077
4078         /* If we're writing through the CPU, then the GPU read domains will
4079          * need to be invalidated at next use.
4080          */
4081         if (write) {
4082                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4083                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4084         }
4085
4086         if (write)
4087                 intel_fb_obj_invalidate(obj, NULL);
4088
4089         trace_i915_gem_object_change_domain(obj,
4090                                             old_read_domains,
4091                                             old_write_domain);
4092
4093         return 0;
4094 }
4095
4096 /* Throttle our rendering by waiting until the ring has completed our requests
4097  * emitted over 20 msec ago.
4098  *
4099  * Note that if we were to use the current jiffies each time around the loop,
4100  * we wouldn't escape the function with any frames outstanding if the time to
4101  * render a frame was over 20ms.
4102  *
4103  * This should get us reasonable parallelism between CPU and GPU but also
4104  * relatively low latency when blocking on a particular request to finish.
4105  */
4106 static int
4107 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4108 {
4109         struct drm_i915_private *dev_priv = dev->dev_private;
4110         struct drm_i915_file_private *file_priv = file->driver_priv;
4111         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4112         struct drm_i915_gem_request *request, *target = NULL;
4113         unsigned reset_counter;
4114         int ret;
4115
4116         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4117         if (ret)
4118                 return ret;
4119
4120         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4121         if (ret)
4122                 return ret;
4123
4124         spin_lock(&file_priv->mm.lock);
4125         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4126                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4127                         break;
4128
4129                 target = request;
4130         }
4131         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4132         if (target)
4133                 i915_gem_request_reference(target);
4134         spin_unlock(&file_priv->mm.lock);
4135
4136         if (target == NULL)
4137                 return 0;
4138
4139         ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4140         if (ret == 0)
4141                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4142
4143         mutex_lock(&dev->struct_mutex);
4144         i915_gem_request_unreference(target);
4145         mutex_unlock(&dev->struct_mutex);
4146
4147         return ret;
4148 }
4149
4150 static bool
4151 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4152 {
4153         struct drm_i915_gem_object *obj = vma->obj;
4154
4155         if (alignment &&
4156             vma->node.start & (alignment - 1))
4157                 return true;
4158
4159         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4160                 return true;
4161
4162         if (flags & PIN_OFFSET_BIAS &&
4163             vma->node.start < (flags & PIN_OFFSET_MASK))
4164                 return true;
4165
4166         return false;
4167 }
4168
4169 int
4170 i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
4171                          struct i915_address_space *vm,
4172                          uint32_t alignment,
4173                          uint64_t flags,
4174                          const struct i915_ggtt_view *view)
4175 {
4176         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4177         struct i915_vma *vma;
4178         unsigned bound;
4179         int ret;
4180
4181         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4182                 return -ENODEV;
4183
4184         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4185                 return -EINVAL;
4186
4187         if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4188                 return -EINVAL;
4189
4190         vma = i915_gem_obj_to_vma_view(obj, vm, view);
4191         if (vma) {
4192                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4193                         return -EBUSY;
4194
4195                 if (i915_vma_misplaced(vma, alignment, flags)) {
4196                         WARN(vma->pin_count,
4197                              "bo is already pinned with incorrect alignment:"
4198                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4199                              " obj->map_and_fenceable=%d\n",
4200                              i915_gem_obj_offset_view(obj, vm, view->type),
4201                              alignment,
4202                              !!(flags & PIN_MAPPABLE),
4203                              obj->map_and_fenceable);
4204                         ret = i915_vma_unbind(vma);
4205                         if (ret)
4206                                 return ret;
4207
4208                         vma = NULL;
4209                 }
4210         }
4211
4212         bound = vma ? vma->bound : 0;
4213         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4214                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment,
4215                                                  flags, view);
4216                 if (IS_ERR(vma))
4217                         return PTR_ERR(vma);
4218         }
4219
4220         if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) {
4221                 ret = i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND);
4222                 if (ret)
4223                         return ret;
4224         }
4225
4226         if ((bound ^ vma->bound) & GLOBAL_BIND) {
4227                 bool mappable, fenceable;
4228                 u32 fence_size, fence_alignment;
4229
4230                 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4231                                                    obj->base.size,
4232                                                    obj->tiling_mode);
4233                 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4234                                                              obj->base.size,
4235                                                              obj->tiling_mode,
4236                                                              true);
4237
4238                 fenceable = (vma->node.size == fence_size &&
4239                              (vma->node.start & (fence_alignment - 1)) == 0);
4240
4241                 mappable = (vma->node.start + obj->base.size <=
4242                             dev_priv->gtt.mappable_end);
4243
4244                 obj->map_and_fenceable = mappable && fenceable;
4245         }
4246
4247         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4248
4249         vma->pin_count++;
4250         if (flags & PIN_MAPPABLE)
4251                 obj->pin_mappable |= true;
4252
4253         return 0;
4254 }
4255
4256 void
4257 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4258 {
4259         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4260
4261         BUG_ON(!vma);
4262         BUG_ON(vma->pin_count == 0);
4263         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4264
4265         if (--vma->pin_count == 0)
4266                 obj->pin_mappable = false;
4267 }
4268
4269 bool
4270 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4271 {
4272         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4273                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4274                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4275
4276                 WARN_ON(!ggtt_vma ||
4277                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4278                         ggtt_vma->pin_count);
4279                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4280                 return true;
4281         } else
4282                 return false;
4283 }
4284
4285 void
4286 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4287 {
4288         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4289                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4290                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4291                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4292         }
4293 }
4294
4295 int
4296 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4297                     struct drm_file *file)
4298 {
4299         struct drm_i915_gem_busy *args = data;
4300         struct drm_i915_gem_object *obj;
4301         int ret;
4302
4303         ret = i915_mutex_lock_interruptible(dev);
4304         if (ret)
4305                 return ret;
4306
4307         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4308         if (&obj->base == NULL) {
4309                 ret = -ENOENT;
4310                 goto unlock;
4311         }
4312
4313         /* Count all active objects as busy, even if they are currently not used
4314          * by the gpu. Users of this interface expect objects to eventually
4315          * become non-busy without any further actions, therefore emit any
4316          * necessary flushes here.
4317          */
4318         ret = i915_gem_object_flush_active(obj);
4319
4320         args->busy = obj->active;
4321         if (obj->last_read_req) {
4322                 struct intel_engine_cs *ring;
4323                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4324                 ring = i915_gem_request_get_ring(obj->last_read_req);
4325                 args->busy |= intel_ring_flag(ring) << 16;
4326         }
4327
4328         drm_gem_object_unreference(&obj->base);
4329 unlock:
4330         mutex_unlock(&dev->struct_mutex);
4331         return ret;
4332 }
4333
4334 int
4335 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4336                         struct drm_file *file_priv)
4337 {
4338         return i915_gem_ring_throttle(dev, file_priv);
4339 }
4340
4341 int
4342 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4343                        struct drm_file *file_priv)
4344 {
4345         struct drm_i915_private *dev_priv = dev->dev_private;
4346         struct drm_i915_gem_madvise *args = data;
4347         struct drm_i915_gem_object *obj;
4348         int ret;
4349
4350         switch (args->madv) {
4351         case I915_MADV_DONTNEED:
4352         case I915_MADV_WILLNEED:
4353             break;
4354         default:
4355             return -EINVAL;
4356         }
4357
4358         ret = i915_mutex_lock_interruptible(dev);
4359         if (ret)
4360                 return ret;
4361
4362         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4363         if (&obj->base == NULL) {
4364                 ret = -ENOENT;
4365                 goto unlock;
4366         }
4367
4368         if (i915_gem_obj_is_pinned(obj)) {
4369                 ret = -EINVAL;
4370                 goto out;
4371         }
4372
4373         if (obj->pages &&
4374             obj->tiling_mode != I915_TILING_NONE &&
4375             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4376                 if (obj->madv == I915_MADV_WILLNEED)
4377                         i915_gem_object_unpin_pages(obj);
4378                 if (args->madv == I915_MADV_WILLNEED)
4379                         i915_gem_object_pin_pages(obj);
4380         }
4381
4382         if (obj->madv != __I915_MADV_PURGED)
4383                 obj->madv = args->madv;
4384
4385         /* if the object is no longer attached, discard its backing storage */
4386         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4387                 i915_gem_object_truncate(obj);
4388
4389         args->retained = obj->madv != __I915_MADV_PURGED;
4390
4391 out:
4392         drm_gem_object_unreference(&obj->base);
4393 unlock:
4394         mutex_unlock(&dev->struct_mutex);
4395         return ret;
4396 }
4397
4398 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4399                           const struct drm_i915_gem_object_ops *ops)
4400 {
4401         INIT_LIST_HEAD(&obj->global_list);
4402         INIT_LIST_HEAD(&obj->ring_list);
4403         INIT_LIST_HEAD(&obj->obj_exec_link);
4404         INIT_LIST_HEAD(&obj->vma_list);
4405         INIT_LIST_HEAD(&obj->batch_pool_list);
4406
4407         obj->ops = ops;
4408
4409         obj->fence_reg = I915_FENCE_REG_NONE;
4410         obj->madv = I915_MADV_WILLNEED;
4411
4412         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4413 }
4414
4415 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4416         .get_pages = i915_gem_object_get_pages_gtt,
4417         .put_pages = i915_gem_object_put_pages_gtt,
4418 };
4419
4420 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4421                                                   size_t size)
4422 {
4423         struct drm_i915_gem_object *obj;
4424         struct address_space *mapping;
4425         gfp_t mask;
4426
4427         obj = i915_gem_object_alloc(dev);
4428         if (obj == NULL)
4429                 return NULL;
4430
4431         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4432                 i915_gem_object_free(obj);
4433                 return NULL;
4434         }
4435
4436         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4437         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4438                 /* 965gm cannot relocate objects above 4GiB. */
4439                 mask &= ~__GFP_HIGHMEM;
4440                 mask |= __GFP_DMA32;
4441         }
4442
4443         mapping = file_inode(obj->base.filp)->i_mapping;
4444         mapping_set_gfp_mask(mapping, mask);
4445
4446         i915_gem_object_init(obj, &i915_gem_object_ops);
4447
4448         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4449         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4450
4451         if (HAS_LLC(dev)) {
4452                 /* On some devices, we can have the GPU use the LLC (the CPU
4453                  * cache) for about a 10% performance improvement
4454                  * compared to uncached.  Graphics requests other than
4455                  * display scanout are coherent with the CPU in
4456                  * accessing this cache.  This means in this mode we
4457                  * don't need to clflush on the CPU side, and on the
4458                  * GPU side we only need to flush internal caches to
4459                  * get data visible to the CPU.
4460                  *
4461                  * However, we maintain the display planes as UC, and so
4462                  * need to rebind when first used as such.
4463                  */
4464                 obj->cache_level = I915_CACHE_LLC;
4465         } else
4466                 obj->cache_level = I915_CACHE_NONE;
4467
4468         trace_i915_gem_object_create(obj);
4469
4470         return obj;
4471 }
4472
4473 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4474 {
4475         /* If we are the last user of the backing storage (be it shmemfs
4476          * pages or stolen etc), we know that the pages are going to be
4477          * immediately released. In this case, we can then skip copying
4478          * back the contents from the GPU.
4479          */
4480
4481         if (obj->madv != I915_MADV_WILLNEED)
4482                 return false;
4483
4484         if (obj->base.filp == NULL)
4485                 return true;
4486
4487         /* At first glance, this looks racy, but then again so would be
4488          * userspace racing mmap against close. However, the first external
4489          * reference to the filp can only be obtained through the
4490          * i915_gem_mmap_ioctl() which safeguards us against the user
4491          * acquiring such a reference whilst we are in the middle of
4492          * freeing the object.
4493          */
4494         return atomic_long_read(&obj->base.filp->f_count) == 1;
4495 }
4496
4497 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4498 {
4499         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4500         struct drm_device *dev = obj->base.dev;
4501         struct drm_i915_private *dev_priv = dev->dev_private;
4502         struct i915_vma *vma, *next;
4503
4504         intel_runtime_pm_get(dev_priv);
4505
4506         trace_i915_gem_object_destroy(obj);
4507
4508         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4509                 int ret;
4510
4511                 vma->pin_count = 0;
4512                 ret = i915_vma_unbind(vma);
4513                 if (WARN_ON(ret == -ERESTARTSYS)) {
4514                         bool was_interruptible;
4515
4516                         was_interruptible = dev_priv->mm.interruptible;
4517                         dev_priv->mm.interruptible = false;
4518
4519                         WARN_ON(i915_vma_unbind(vma));
4520
4521                         dev_priv->mm.interruptible = was_interruptible;
4522                 }
4523         }
4524
4525         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4526          * before progressing. */
4527         if (obj->stolen)
4528                 i915_gem_object_unpin_pages(obj);
4529
4530         WARN_ON(obj->frontbuffer_bits);
4531
4532         if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4533             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4534             obj->tiling_mode != I915_TILING_NONE)
4535                 i915_gem_object_unpin_pages(obj);
4536
4537         if (WARN_ON(obj->pages_pin_count))
4538                 obj->pages_pin_count = 0;
4539         if (discard_backing_storage(obj))
4540                 obj->madv = I915_MADV_DONTNEED;
4541         i915_gem_object_put_pages(obj);
4542         i915_gem_object_free_mmap_offset(obj);
4543
4544         BUG_ON(obj->pages);
4545
4546         if (obj->base.import_attach)
4547                 drm_prime_gem_destroy(&obj->base, NULL);
4548
4549         if (obj->ops->release)
4550                 obj->ops->release(obj);
4551
4552         drm_gem_object_release(&obj->base);
4553         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4554
4555         kfree(obj->bit_17);
4556         i915_gem_object_free(obj);
4557
4558         intel_runtime_pm_put(dev_priv);
4559 }
4560
4561 struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj,
4562                                           struct i915_address_space *vm,
4563                                           const struct i915_ggtt_view *view)
4564 {
4565         struct i915_vma *vma;
4566         list_for_each_entry(vma, &obj->vma_list, vma_link)
4567                 if (vma->vm == vm && vma->ggtt_view.type == view->type)
4568                         return vma;
4569
4570         return NULL;
4571 }
4572
4573 void i915_gem_vma_destroy(struct i915_vma *vma)
4574 {
4575         struct i915_address_space *vm = NULL;
4576         WARN_ON(vma->node.allocated);
4577
4578         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4579         if (!list_empty(&vma->exec_list))
4580                 return;
4581
4582         vm = vma->vm;
4583
4584         if (!i915_is_ggtt(vm))
4585                 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4586
4587         list_del(&vma->vma_link);
4588
4589         kfree(vma);
4590 }
4591
4592 static void
4593 i915_gem_stop_ringbuffers(struct drm_device *dev)
4594 {
4595         struct drm_i915_private *dev_priv = dev->dev_private;
4596         struct intel_engine_cs *ring;
4597         int i;
4598
4599         for_each_ring(ring, dev_priv, i)
4600                 dev_priv->gt.stop_ring(ring);
4601 }
4602
4603 int
4604 i915_gem_suspend(struct drm_device *dev)
4605 {
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         int ret = 0;
4608
4609         mutex_lock(&dev->struct_mutex);
4610         ret = i915_gpu_idle(dev);
4611         if (ret)
4612                 goto err;
4613
4614         i915_gem_retire_requests(dev);
4615
4616         /* Under UMS, be paranoid and evict. */
4617         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4618                 i915_gem_evict_everything(dev);
4619
4620         i915_gem_stop_ringbuffers(dev);
4621         mutex_unlock(&dev->struct_mutex);
4622
4623         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4624         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4625         flush_delayed_work(&dev_priv->mm.idle_work);
4626
4627         /* Assert that we sucessfully flushed all the work and
4628          * reset the GPU back to its idle, low power state.
4629          */
4630         WARN_ON(dev_priv->mm.busy);
4631
4632         return 0;
4633
4634 err:
4635         mutex_unlock(&dev->struct_mutex);
4636         return ret;
4637 }
4638
4639 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4640 {
4641         struct drm_device *dev = ring->dev;
4642         struct drm_i915_private *dev_priv = dev->dev_private;
4643         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4644         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4645         int i, ret;
4646
4647         if (!HAS_L3_DPF(dev) || !remap_info)
4648                 return 0;
4649
4650         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4651         if (ret)
4652                 return ret;
4653
4654         /*
4655          * Note: We do not worry about the concurrent register cacheline hang
4656          * here because no other code should access these registers other than
4657          * at initialization time.
4658          */
4659         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4660                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4661                 intel_ring_emit(ring, reg_base + i);
4662                 intel_ring_emit(ring, remap_info[i/4]);
4663         }
4664
4665         intel_ring_advance(ring);
4666
4667         return ret;
4668 }
4669
4670 void i915_gem_init_swizzling(struct drm_device *dev)
4671 {
4672         struct drm_i915_private *dev_priv = dev->dev_private;
4673
4674         if (INTEL_INFO(dev)->gen < 5 ||
4675             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4676                 return;
4677
4678         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4679                                  DISP_TILE_SURFACE_SWIZZLING);
4680
4681         if (IS_GEN5(dev))
4682                 return;
4683
4684         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4685         if (IS_GEN6(dev))
4686                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4687         else if (IS_GEN7(dev))
4688                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4689         else if (IS_GEN8(dev))
4690                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4691         else
4692                 BUG();
4693 }
4694
4695 static bool
4696 intel_enable_blt(struct drm_device *dev)
4697 {
4698         if (!HAS_BLT(dev))
4699                 return false;
4700
4701         /* The blitter was dysfunctional on early prototypes */
4702         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4703                 DRM_INFO("BLT not supported on this pre-production hardware;"
4704                          " graphics performance will be degraded.\n");
4705                 return false;
4706         }
4707
4708         return true;
4709 }
4710
4711 static void init_unused_ring(struct drm_device *dev, u32 base)
4712 {
4713         struct drm_i915_private *dev_priv = dev->dev_private;
4714
4715         I915_WRITE(RING_CTL(base), 0);
4716         I915_WRITE(RING_HEAD(base), 0);
4717         I915_WRITE(RING_TAIL(base), 0);
4718         I915_WRITE(RING_START(base), 0);
4719 }
4720
4721 static void init_unused_rings(struct drm_device *dev)
4722 {
4723         if (IS_I830(dev)) {
4724                 init_unused_ring(dev, PRB1_BASE);
4725                 init_unused_ring(dev, SRB0_BASE);
4726                 init_unused_ring(dev, SRB1_BASE);
4727                 init_unused_ring(dev, SRB2_BASE);
4728                 init_unused_ring(dev, SRB3_BASE);
4729         } else if (IS_GEN2(dev)) {
4730                 init_unused_ring(dev, SRB0_BASE);
4731                 init_unused_ring(dev, SRB1_BASE);
4732         } else if (IS_GEN3(dev)) {
4733                 init_unused_ring(dev, PRB1_BASE);
4734                 init_unused_ring(dev, PRB2_BASE);
4735         }
4736 }
4737
4738 int i915_gem_init_rings(struct drm_device *dev)
4739 {
4740         struct drm_i915_private *dev_priv = dev->dev_private;
4741         int ret;
4742
4743         ret = intel_init_render_ring_buffer(dev);
4744         if (ret)
4745                 return ret;
4746
4747         if (HAS_BSD(dev)) {
4748                 ret = intel_init_bsd_ring_buffer(dev);
4749                 if (ret)
4750                         goto cleanup_render_ring;
4751         }
4752
4753         if (intel_enable_blt(dev)) {
4754                 ret = intel_init_blt_ring_buffer(dev);
4755                 if (ret)
4756                         goto cleanup_bsd_ring;
4757         }
4758
4759         if (HAS_VEBOX(dev)) {
4760                 ret = intel_init_vebox_ring_buffer(dev);
4761                 if (ret)
4762                         goto cleanup_blt_ring;
4763         }
4764
4765         if (HAS_BSD2(dev)) {
4766                 ret = intel_init_bsd2_ring_buffer(dev);
4767                 if (ret)
4768                         goto cleanup_vebox_ring;
4769         }
4770
4771         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4772         if (ret)
4773                 goto cleanup_bsd2_ring;
4774
4775         return 0;
4776
4777 cleanup_bsd2_ring:
4778         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4779 cleanup_vebox_ring:
4780         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4781 cleanup_blt_ring:
4782         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4783 cleanup_bsd_ring:
4784         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4785 cleanup_render_ring:
4786         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4787
4788         return ret;
4789 }
4790
4791 int
4792 i915_gem_init_hw(struct drm_device *dev)
4793 {
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795         struct intel_engine_cs *ring;
4796         int ret, i;
4797
4798         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4799                 return -EIO;
4800
4801         if (dev_priv->ellc_size)
4802                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4803
4804         if (IS_HASWELL(dev))
4805                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4806                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4807
4808         if (HAS_PCH_NOP(dev)) {
4809                 if (IS_IVYBRIDGE(dev)) {
4810                         u32 temp = I915_READ(GEN7_MSG_CTL);
4811                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4812                         I915_WRITE(GEN7_MSG_CTL, temp);
4813                 } else if (INTEL_INFO(dev)->gen >= 7) {
4814                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4815                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4816                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4817                 }
4818         }
4819
4820         i915_gem_init_swizzling(dev);
4821
4822         /*
4823          * At least 830 can leave some of the unused rings
4824          * "active" (ie. head != tail) after resume which
4825          * will prevent c3 entry. Makes sure all unused rings
4826          * are totally idle.
4827          */
4828         init_unused_rings(dev);
4829
4830         for_each_ring(ring, dev_priv, i) {
4831                 ret = ring->init_hw(ring);
4832                 if (ret)
4833                         return ret;
4834         }
4835
4836         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4837                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4838
4839         ret = i915_ppgtt_init_hw(dev);
4840         if (ret && ret != -EIO) {
4841                 DRM_ERROR("PPGTT enable failed %d\n", ret);
4842                 i915_gem_cleanup_ringbuffer(dev);
4843         }
4844
4845         ret = i915_gem_context_enable(dev_priv);
4846         if (ret && ret != -EIO) {
4847                 DRM_ERROR("Context enable failed %d\n", ret);
4848                 i915_gem_cleanup_ringbuffer(dev);
4849
4850                 return ret;
4851         }
4852
4853         return ret;
4854 }
4855
4856 int i915_gem_init(struct drm_device *dev)
4857 {
4858         struct drm_i915_private *dev_priv = dev->dev_private;
4859         int ret;
4860
4861         i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4862                         i915.enable_execlists);
4863
4864         mutex_lock(&dev->struct_mutex);
4865
4866         if (IS_VALLEYVIEW(dev)) {
4867                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4868                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4869                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4870                               VLV_GTLC_ALLOWWAKEACK), 10))
4871                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4872         }
4873
4874         if (!i915.enable_execlists) {
4875                 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4876                 dev_priv->gt.init_rings = i915_gem_init_rings;
4877                 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4878                 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4879         } else {
4880                 dev_priv->gt.do_execbuf = intel_execlists_submission;
4881                 dev_priv->gt.init_rings = intel_logical_rings_init;
4882                 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4883                 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4884         }
4885
4886         ret = i915_gem_init_userptr(dev);
4887         if (ret)
4888                 goto out_unlock;
4889
4890         i915_gem_init_global_gtt(dev);
4891
4892         ret = i915_gem_context_init(dev);
4893         if (ret)
4894                 goto out_unlock;
4895
4896         ret = dev_priv->gt.init_rings(dev);
4897         if (ret)
4898                 goto out_unlock;
4899
4900         ret = i915_gem_init_hw(dev);
4901         if (ret == -EIO) {
4902                 /* Allow ring initialisation to fail by marking the GPU as
4903                  * wedged. But we only want to do this where the GPU is angry,
4904                  * for all other failure, such as an allocation failure, bail.
4905                  */
4906                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4907                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4908                 ret = 0;
4909         }
4910
4911 out_unlock:
4912         mutex_unlock(&dev->struct_mutex);
4913
4914         return ret;
4915 }
4916
4917 void
4918 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4919 {
4920         struct drm_i915_private *dev_priv = dev->dev_private;
4921         struct intel_engine_cs *ring;
4922         int i;
4923
4924         for_each_ring(ring, dev_priv, i)
4925                 dev_priv->gt.cleanup_ring(ring);
4926 }
4927
4928 static void
4929 init_ring_lists(struct intel_engine_cs *ring)
4930 {
4931         INIT_LIST_HEAD(&ring->active_list);
4932         INIT_LIST_HEAD(&ring->request_list);
4933 }
4934
4935 void i915_init_vm(struct drm_i915_private *dev_priv,
4936                   struct i915_address_space *vm)
4937 {
4938         if (!i915_is_ggtt(vm))
4939                 drm_mm_init(&vm->mm, vm->start, vm->total);
4940         vm->dev = dev_priv->dev;
4941         INIT_LIST_HEAD(&vm->active_list);
4942         INIT_LIST_HEAD(&vm->inactive_list);
4943         INIT_LIST_HEAD(&vm->global_link);
4944         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4945 }
4946
4947 void
4948 i915_gem_load(struct drm_device *dev)
4949 {
4950         struct drm_i915_private *dev_priv = dev->dev_private;
4951         int i;
4952
4953         dev_priv->slab =
4954                 kmem_cache_create("i915_gem_object",
4955                                   sizeof(struct drm_i915_gem_object), 0,
4956                                   SLAB_HWCACHE_ALIGN,
4957                                   NULL);
4958
4959         INIT_LIST_HEAD(&dev_priv->vm_list);
4960         i915_init_vm(dev_priv, &dev_priv->gtt.base);
4961
4962         INIT_LIST_HEAD(&dev_priv->context_list);
4963         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4964         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4965         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4966         for (i = 0; i < I915_NUM_RINGS; i++)
4967                 init_ring_lists(&dev_priv->ring[i]);
4968         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4969                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4970         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4971                           i915_gem_retire_work_handler);
4972         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4973                           i915_gem_idle_work_handler);
4974         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4975
4976         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4977         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4978                 I915_WRITE(MI_ARB_STATE,
4979                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4980         }
4981
4982         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4983
4984         /* Old X drivers will take 0-2 for front, back, depth buffers */
4985         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4986                 dev_priv->fence_reg_start = 3;
4987
4988         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4989                 dev_priv->num_fence_regs = 32;
4990         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4991                 dev_priv->num_fence_regs = 16;
4992         else
4993                 dev_priv->num_fence_regs = 8;
4994
4995         if (intel_vgpu_active(dev))
4996                 dev_priv->num_fence_regs =
4997                                 I915_READ(vgtif_reg(avail_rs.fence_num));
4998
4999         /* Initialize fence registers to zero */
5000         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5001         i915_gem_restore_fences(dev);
5002
5003         i915_gem_detect_bit_6_swizzle(dev);
5004         init_waitqueue_head(&dev_priv->pending_flip_queue);
5005
5006         dev_priv->mm.interruptible = true;
5007
5008         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
5009         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
5010         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
5011         register_shrinker(&dev_priv->mm.shrinker);
5012
5013         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
5014         register_oom_notifier(&dev_priv->mm.oom_notifier);
5015
5016         i915_gem_batch_pool_init(dev, &dev_priv->mm.batch_pool);
5017
5018         mutex_init(&dev_priv->fb_tracking.lock);
5019 }
5020
5021 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5022 {
5023         struct drm_i915_file_private *file_priv = file->driver_priv;
5024
5025         cancel_delayed_work_sync(&file_priv->mm.idle_work);
5026
5027         /* Clean up our request list when the client is going away, so that
5028          * later retire_requests won't dereference our soon-to-be-gone
5029          * file_priv.
5030          */
5031         spin_lock(&file_priv->mm.lock);
5032         while (!list_empty(&file_priv->mm.request_list)) {
5033                 struct drm_i915_gem_request *request;
5034
5035                 request = list_first_entry(&file_priv->mm.request_list,
5036                                            struct drm_i915_gem_request,
5037                                            client_list);
5038                 list_del(&request->client_list);
5039                 request->file_priv = NULL;
5040         }
5041         spin_unlock(&file_priv->mm.lock);
5042 }
5043
5044 static void
5045 i915_gem_file_idle_work_handler(struct work_struct *work)
5046 {
5047         struct drm_i915_file_private *file_priv =
5048                 container_of(work, typeof(*file_priv), mm.idle_work.work);
5049
5050         atomic_set(&file_priv->rps_wait_boost, false);
5051 }
5052
5053 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5054 {
5055         struct drm_i915_file_private *file_priv;
5056         int ret;
5057
5058         DRM_DEBUG_DRIVER("\n");
5059
5060         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5061         if (!file_priv)
5062                 return -ENOMEM;
5063
5064         file->driver_priv = file_priv;
5065         file_priv->dev_priv = dev->dev_private;
5066         file_priv->file = file;
5067
5068         spin_lock_init(&file_priv->mm.lock);
5069         INIT_LIST_HEAD(&file_priv->mm.request_list);
5070         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5071                           i915_gem_file_idle_work_handler);
5072
5073         ret = i915_gem_context_open(dev, file);
5074         if (ret)
5075                 kfree(file_priv);
5076
5077         return ret;
5078 }
5079
5080 /**
5081  * i915_gem_track_fb - update frontbuffer tracking
5082  * old: current GEM buffer for the frontbuffer slots
5083  * new: new GEM buffer for the frontbuffer slots
5084  * frontbuffer_bits: bitmask of frontbuffer slots
5085  *
5086  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5087  * from @old and setting them in @new. Both @old and @new can be NULL.
5088  */
5089 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5090                        struct drm_i915_gem_object *new,
5091                        unsigned frontbuffer_bits)
5092 {
5093         if (old) {
5094                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5095                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5096                 old->frontbuffer_bits &= ~frontbuffer_bits;
5097         }
5098
5099         if (new) {
5100                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5101                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5102                 new->frontbuffer_bits |= frontbuffer_bits;
5103         }
5104 }
5105
5106 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5107 {
5108         if (!mutex_is_locked(mutex))
5109                 return false;
5110
5111 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5112         return mutex->owner == task;
5113 #else
5114         /* Since UP may be pre-empted, we cannot assume that we own the lock */
5115         return false;
5116 #endif
5117 }
5118
5119 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5120 {
5121         if (!mutex_trylock(&dev->struct_mutex)) {
5122                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5123                         return false;
5124
5125                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5126                         return false;
5127
5128                 *unlock = false;
5129         } else
5130                 *unlock = true;
5131
5132         return true;
5133 }
5134
5135 static int num_vma_bound(struct drm_i915_gem_object *obj)
5136 {
5137         struct i915_vma *vma;
5138         int count = 0;
5139
5140         list_for_each_entry(vma, &obj->vma_list, vma_link)
5141                 if (drm_mm_node_allocated(&vma->node))
5142                         count++;
5143
5144         return count;
5145 }
5146
5147 static unsigned long
5148 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5149 {
5150         struct drm_i915_private *dev_priv =
5151                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5152         struct drm_device *dev = dev_priv->dev;
5153         struct drm_i915_gem_object *obj;
5154         unsigned long count;
5155         bool unlock;
5156
5157         if (!i915_gem_shrinker_lock(dev, &unlock))
5158                 return 0;
5159
5160         count = 0;
5161         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5162                 if (obj->pages_pin_count == 0)
5163                         count += obj->base.size >> PAGE_SHIFT;
5164
5165         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5166                 if (!i915_gem_obj_is_pinned(obj) &&
5167                     obj->pages_pin_count == num_vma_bound(obj))
5168                         count += obj->base.size >> PAGE_SHIFT;
5169         }
5170
5171         if (unlock)
5172                 mutex_unlock(&dev->struct_mutex);
5173
5174         return count;
5175 }
5176
5177 /* All the new VM stuff */
5178 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o,
5179                                        struct i915_address_space *vm,
5180                                        enum i915_ggtt_view_type view)
5181 {
5182         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5183         struct i915_vma *vma;
5184
5185         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5186
5187         list_for_each_entry(vma, &o->vma_list, vma_link) {
5188                 if (vma->vm == vm && vma->ggtt_view.type == view)
5189                         return vma->node.start;
5190
5191         }
5192         WARN(1, "%s vma for this object not found.\n",
5193              i915_is_ggtt(vm) ? "global" : "ppgtt");
5194         return -1;
5195 }
5196
5197 bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o,
5198                              struct i915_address_space *vm,
5199                              enum i915_ggtt_view_type view)
5200 {
5201         struct i915_vma *vma;
5202
5203         list_for_each_entry(vma, &o->vma_list, vma_link)
5204                 if (vma->vm == vm &&
5205                     vma->ggtt_view.type == view &&
5206                     drm_mm_node_allocated(&vma->node))
5207                         return true;
5208
5209         return false;
5210 }
5211
5212 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5213 {
5214         struct i915_vma *vma;
5215
5216         list_for_each_entry(vma, &o->vma_list, vma_link)
5217                 if (drm_mm_node_allocated(&vma->node))
5218                         return true;
5219
5220         return false;
5221 }
5222
5223 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5224                                 struct i915_address_space *vm)
5225 {
5226         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5227         struct i915_vma *vma;
5228
5229         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5230
5231         BUG_ON(list_empty(&o->vma_list));
5232
5233         list_for_each_entry(vma, &o->vma_list, vma_link)
5234                 if (vma->vm == vm)
5235                         return vma->node.size;
5236
5237         return 0;
5238 }
5239
5240 static unsigned long
5241 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5242 {
5243         struct drm_i915_private *dev_priv =
5244                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5245         struct drm_device *dev = dev_priv->dev;
5246         unsigned long freed;
5247         bool unlock;
5248
5249         if (!i915_gem_shrinker_lock(dev, &unlock))
5250                 return SHRINK_STOP;
5251
5252         freed = i915_gem_shrink(dev_priv,
5253                                 sc->nr_to_scan,
5254                                 I915_SHRINK_BOUND |
5255                                 I915_SHRINK_UNBOUND |
5256                                 I915_SHRINK_PURGEABLE);
5257         if (freed < sc->nr_to_scan)
5258                 freed += i915_gem_shrink(dev_priv,
5259                                          sc->nr_to_scan - freed,
5260                                          I915_SHRINK_BOUND |
5261                                          I915_SHRINK_UNBOUND);
5262         if (unlock)
5263                 mutex_unlock(&dev->struct_mutex);
5264
5265         return freed;
5266 }
5267
5268 static int
5269 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5270 {
5271         struct drm_i915_private *dev_priv =
5272                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5273         struct drm_device *dev = dev_priv->dev;
5274         struct drm_i915_gem_object *obj;
5275         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5276         unsigned long pinned, bound, unbound, freed_pages;
5277         bool was_interruptible;
5278         bool unlock;
5279
5280         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5281                 schedule_timeout_killable(1);
5282                 if (fatal_signal_pending(current))
5283                         return NOTIFY_DONE;
5284         }
5285         if (timeout == 0) {
5286                 pr_err("Unable to purge GPU memory due lock contention.\n");
5287                 return NOTIFY_DONE;
5288         }
5289
5290         was_interruptible = dev_priv->mm.interruptible;
5291         dev_priv->mm.interruptible = false;
5292
5293         freed_pages = i915_gem_shrink_all(dev_priv);
5294
5295         dev_priv->mm.interruptible = was_interruptible;
5296
5297         /* Because we may be allocating inside our own driver, we cannot
5298          * assert that there are no objects with pinned pages that are not
5299          * being pointed to by hardware.
5300          */
5301         unbound = bound = pinned = 0;
5302         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5303                 if (!obj->base.filp) /* not backed by a freeable object */
5304                         continue;
5305
5306                 if (obj->pages_pin_count)
5307                         pinned += obj->base.size;
5308                 else
5309                         unbound += obj->base.size;
5310         }
5311         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5312                 if (!obj->base.filp)
5313                         continue;
5314
5315                 if (obj->pages_pin_count)
5316                         pinned += obj->base.size;
5317                 else
5318                         bound += obj->base.size;
5319         }
5320
5321         if (unlock)
5322                 mutex_unlock(&dev->struct_mutex);
5323
5324         if (freed_pages || unbound || bound)
5325                 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5326                         freed_pages << PAGE_SHIFT, pinned);
5327         if (unbound || bound)
5328                 pr_err("%lu and %lu bytes still available in the "
5329                        "bound and unbound GPU page lists.\n",
5330                        bound, unbound);
5331
5332         *(unsigned long *)ptr += freed_pages;
5333         return NOTIFY_DONE;
5334 }
5335
5336 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5337 {
5338         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
5339         struct i915_vma *vma;
5340
5341         list_for_each_entry(vma, &obj->vma_list, vma_link)
5342                 if (vma->vm == ggtt &&
5343                     vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
5344                         return vma;
5345
5346         return NULL;
5347 }