drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_vgpu.h"
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 #define RQ_BUG_ON(expr)
  42
  43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  45 static void
  46 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
  47 static void
  48 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
  49
  50 static bool cpu_cache_is_coherent(struct drm_device *dev,
  51                                   enum i915_cache_level level)
  52 {
  53         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  54 }
  55
  56 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  57 {
  58         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  59                 return true;
  60
  61         return obj->pin_display;
  62 }
  63
  64 /* some bookkeeping */
  65 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  66                                   size_t size)
  67 {
  68         spin_lock(&dev_priv->mm.object_stat_lock);
  69         dev_priv->mm.object_count++;
  70         dev_priv->mm.object_memory += size;
  71         spin_unlock(&dev_priv->mm.object_stat_lock);
  72 }
  73
  74 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  75                                      size_t size)
  76 {
  77         spin_lock(&dev_priv->mm.object_stat_lock);
  78         dev_priv->mm.object_count--;
  79         dev_priv->mm.object_memory -= size;
  80         spin_unlock(&dev_priv->mm.object_stat_lock);
  81 }
  82
  83 static int
  84 i915_gem_wait_for_error(struct i915_gpu_error *error)
  85 {
  86         int ret;
  87
  88 #define EXIT_COND (!i915_reset_in_progress(error) || \
  89                    i915_terminally_wedged(error))
  90         if (EXIT_COND)
  91                 return 0;
  92
  93         /*
  94          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
  95          * userspace. If it takes that long something really bad is going on and
  96          * we should simply try to bail out and fail as gracefully as possible.
  97          */
  98         ret = wait_event_interruptible_timeout(error->reset_queue,
  99                                                EXIT_COND,
 100                                                10*HZ);
 101         if (ret == 0) {
 102                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 103                 return -EIO;
 104         } else if (ret < 0) {
 105                 return ret;
 106         }
 107 #undef EXIT_COND
 108
 109         return 0;
 110 }
 111
 112 int i915_mutex_lock_interruptible(struct drm_device *dev)
 113 {
 114         struct drm_i915_private *dev_priv = dev->dev_private;
 115         int ret;
 116
 117         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 118         if (ret)
 119                 return ret;
 120
 121         ret = mutex_lock_interruptible(&dev->struct_mutex);
 122         if (ret)
 123                 return ret;
 124
 125         WARN_ON(i915_verify_lists(dev));
 126         return 0;
 127 }
 128
 129 int
 130 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 131                             struct drm_file *file)
 132 {
 133         struct drm_i915_private *dev_priv = to_i915(dev);
 134         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 135         struct drm_i915_gem_get_aperture *args = data;
 136         struct i915_vma *vma;
 137         size_t pinned;
 138
 139         pinned = 0;
 140         mutex_lock(&dev->struct_mutex);
 141         list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
 142                 if (vma->pin_count)
 143                         pinned += vma->node.size;
 144         list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
 145                 if (vma->pin_count)
 146                         pinned += vma->node.size;
 147         mutex_unlock(&dev->struct_mutex);
 148
 149         args->aper_size = ggtt->base.total;
 150         args->aper_available_size = args->aper_size - pinned;
 151
 152         return 0;
 153 }
 154
 155 static int
 156 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 157 {
 158         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 159         char *vaddr = obj->phys_handle->vaddr;
 160         struct sg_table *st;
 161         struct scatterlist *sg;
 162         int i;
 163
 164         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
 165                 return -EINVAL;
 166
 167         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 168                 struct page *page;
 169                 char *src;
 170
 171                 page = shmem_read_mapping_page(mapping, i);
 172                 if (IS_ERR(page))
 173                         return PTR_ERR(page);
 174
 175                 src = kmap_atomic(page);
 176                 memcpy(vaddr, src, PAGE_SIZE);
 177                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 178                 kunmap_atomic(src);
 179
 180                 put_page(page);
 181                 vaddr += PAGE_SIZE;
 182         }
 183
 184         i915_gem_chipset_flush(obj->base.dev);
 185
 186         st = kmalloc(sizeof(*st), GFP_KERNEL);
 187         if (st == NULL)
 188                 return -ENOMEM;
 189
 190         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 191                 kfree(st);
 192                 return -ENOMEM;
 193         }
 194
 195         sg = st->sgl;
 196         sg->offset = 0;
 197         sg->length = obj->base.size;
 198
 199         sg_dma_address(sg) = obj->phys_handle->busaddr;
 200         sg_dma_len(sg) = obj->base.size;
 201
 202         obj->pages = st;
 203         return 0;
 204 }
 205
 206 static void
 207 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
 208 {
 209         int ret;
 210
 211         BUG_ON(obj->madv == __I915_MADV_PURGED);
 212
 213         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 214         if (ret) {
 215                 /* In the event of a disaster, abandon all caches and
 216                  * hope for the best.
 217                  */
 218                 WARN_ON(ret != -EIO);
 219                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 220         }
 221
 222         if (obj->madv == I915_MADV_DONTNEED)
 223                 obj->dirty = 0;
 224
 225         if (obj->dirty) {
 226                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 227                 char *vaddr = obj->phys_handle->vaddr;
 228                 int i;
 229
 230                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 231                         struct page *page;
 232                         char *dst;
 233
 234                         page = shmem_read_mapping_page(mapping, i);
 235                         if (IS_ERR(page))
 236                                 continue;
 237
 238                         dst = kmap_atomic(page);
 239                         drm_clflush_virt_range(vaddr, PAGE_SIZE);
 240                         memcpy(dst, vaddr, PAGE_SIZE);
 241                         kunmap_atomic(dst);
 242
 243                         set_page_dirty(page);
 244                         if (obj->madv == I915_MADV_WILLNEED)
 245                                 mark_page_accessed(page);
 246                         put_page(page);
 247                         vaddr += PAGE_SIZE;
 248                 }
 249                 obj->dirty = 0;
 250         }
 251
 252         sg_free_table(obj->pages);
 253         kfree(obj->pages);
 254 }
 255
 256 static void
 257 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
 258 {
 259         drm_pci_free(obj->base.dev, obj->phys_handle);
 260 }
 261
 262 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 263         .get_pages = i915_gem_object_get_pages_phys,
 264         .put_pages = i915_gem_object_put_pages_phys,
 265         .release = i915_gem_object_release_phys,
 266 };
 267
 268 static int
 269 drop_pages(struct drm_i915_gem_object *obj)
 270 {
 271         struct i915_vma *vma, *next;
 272         int ret;
 273
 274         drm_gem_object_reference(&obj->base);
 275         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link)
 276                 if (i915_vma_unbind(vma))
 277                         break;
 278
 279         ret = i915_gem_object_put_pages(obj);
 280         drm_gem_object_unreference(&obj->base);
 281
 282         return ret;
 283 }
 284
 285 int
 286 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 287                             int align)
 288 {
 289         drm_dma_handle_t *phys;
 290         int ret;
 291
 292         if (obj->phys_handle) {
 293                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 294                         return -EBUSY;
 295
 296                 return 0;
 297         }
 298
 299         if (obj->madv != I915_MADV_WILLNEED)
 300                 return -EFAULT;
 301
 302         if (obj->base.filp == NULL)
 303                 return -EINVAL;
 304
 305         ret = drop_pages(obj);
 306         if (ret)
 307                 return ret;
 308
 309         /* create a new object */
 310         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 311         if (!phys)
 312                 return -ENOMEM;
 313
 314         obj->phys_handle = phys;
 315         obj->ops = &i915_gem_phys_ops;
 316
 317         return i915_gem_object_get_pages(obj);
 318 }
 319
 320 static int
 321 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 322                      struct drm_i915_gem_pwrite *args,
 323                      struct drm_file *file_priv)
 324 {
 325         struct drm_device *dev = obj->base.dev;
 326         void *vaddr = obj->phys_handle->vaddr + args->offset;
 327         char __user *user_data = to_user_ptr(args->data_ptr);
 328         int ret = 0;
 329
 330         /* We manually control the domain here and pretend that it
 331          * remains coherent i.e. in the GTT domain, like shmem_pwrite.
 332          */
 333         ret = i915_gem_object_wait_rendering(obj, false);
 334         if (ret)
 335                 return ret;
 336
 337         intel_fb_obj_invalidate(obj, ORIGIN_CPU);
 338         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 339                 unsigned long unwritten;
 340
 341                 /* The physical object once assigned is fixed for the lifetime
 342                  * of the obj, so we can safely drop the lock and continue
 343                  * to access vaddr.
 344                  */
 345                 mutex_unlock(&dev->struct_mutex);
 346                 unwritten = copy_from_user(vaddr, user_data, args->size);
 347                 mutex_lock(&dev->struct_mutex);
 348                 if (unwritten) {
 349                         ret = -EFAULT;
 350                         goto out;
 351                 }
 352         }
 353
 354         drm_clflush_virt_range(vaddr, args->size);
 355         i915_gem_chipset_flush(dev);
 356
 357 out:
 358         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
 359         return ret;
 360 }
 361
 362 void *i915_gem_object_alloc(struct drm_device *dev)
 363 {
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365         return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
 366 }
 367
 368 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 369 {
 370         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 371         kmem_cache_free(dev_priv->objects, obj);
 372 }
 373
 374 static int
 375 i915_gem_create(struct drm_file *file,
 376                 struct drm_device *dev,
 377                 uint64_t size,
 378                 uint32_t *handle_p)
 379 {
 380         struct drm_i915_gem_object *obj;
 381         int ret;
 382         u32 handle;
 383
 384         size = roundup(size, PAGE_SIZE);
 385         if (size == 0)
 386                 return -EINVAL;
 387
 388         /* Allocate the new object */
 389         obj = i915_gem_alloc_object(dev, size);
 390         if (obj == NULL)
 391                 return -ENOMEM;
 392
 393         ret = drm_gem_handle_create(file, &obj->base, &handle);
 394         /* drop reference from allocate - handle holds it now */
 395         drm_gem_object_unreference_unlocked(&obj->base);
 396         if (ret)
 397                 return ret;
 398
 399         *handle_p = handle;
 400         return 0;
 401 }
 402
 403 int
 404 i915_gem_dumb_create(struct drm_file *file,
 405                      struct drm_device *dev,
 406                      struct drm_mode_create_dumb *args)
 407 {
 408         /* have to work out size/pitch and return them */
 409         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 410         args->size = args->pitch * args->height;
 411         return i915_gem_create(file, dev,
 412                                args->size, &args->handle);
 413 }
 414
 415 /**
 416  * Creates a new mm object and returns a handle to it.
 417  */
 418 int
 419 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 420                       struct drm_file *file)
 421 {
 422         struct drm_i915_gem_create *args = data;
 423
 424         return i915_gem_create(file, dev,
 425                                args->size, &args->handle);
 426 }
 427
 428 static inline int
 429 __copy_to_user_swizzled(char __user *cpu_vaddr,
 430                         const char *gpu_vaddr, int gpu_offset,
 431                         int length)
 432 {
 433         int ret, cpu_offset = 0;
 434
 435         while (length > 0) {
 436                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 437                 int this_length = min(cacheline_end - gpu_offset, length);
 438                 int swizzled_gpu_offset = gpu_offset ^ 64;
 439
 440                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 441                                      gpu_vaddr + swizzled_gpu_offset,
 442                                      this_length);
 443                 if (ret)
 444                         return ret + length;
 445
 446                 cpu_offset += this_length;
 447                 gpu_offset += this_length;
 448                 length -= this_length;
 449         }
 450
 451         return 0;
 452 }
 453
 454 static inline int
 455 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 456                           const char __user *cpu_vaddr,
 457                           int length)
 458 {
 459         int ret, cpu_offset = 0;
 460
 461         while (length > 0) {
 462                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 463                 int this_length = min(cacheline_end - gpu_offset, length);
 464                 int swizzled_gpu_offset = gpu_offset ^ 64;
 465
 466                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 467                                        cpu_vaddr + cpu_offset,
 468                                        this_length);
 469                 if (ret)
 470                         return ret + length;
 471
 472                 cpu_offset += this_length;
 473                 gpu_offset += this_length;
 474                 length -= this_length;
 475         }
 476
 477         return 0;
 478 }
 479
 480 /*
 481  * Pins the specified object's pages and synchronizes the object with
 482  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 483  * flush the object from the CPU cache.
 484  */
 485 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 486                                     int *needs_clflush)
 487 {
 488         int ret;
 489
 490         *needs_clflush = 0;
 491
 492         if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
 493                 return -EINVAL;
 494
 495         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 496                 /* If we're not in the cpu read domain, set ourself into the gtt
 497                  * read domain and manually flush cachelines (if required). This
 498                  * optimizes for the case when the gpu will dirty the data
 499                  * anyway again before the next pread happens. */
 500                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 501                                                         obj->cache_level);
 502                 ret = i915_gem_object_wait_rendering(obj, true);
 503                 if (ret)
 504                         return ret;
 505         }
 506
 507         ret = i915_gem_object_get_pages(obj);
 508         if (ret)
 509                 return ret;
 510
 511         i915_gem_object_pin_pages(obj);
 512
 513         return ret;
 514 }
 515
 516 /* Per-page copy function for the shmem pread fastpath.
 517  * Flushes invalid cachelines before reading the target if
 518  * needs_clflush is set. */
 519 static int
 520 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 521                  char __user *user_data,
 522                  bool page_do_bit17_swizzling, bool needs_clflush)
 523 {
 524         char *vaddr;
 525         int ret;
 526
 527         if (unlikely(page_do_bit17_swizzling))
 528                 return -EINVAL;
 529
 530         vaddr = kmap_atomic(page);
 531         if (needs_clflush)
 532                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 533                                        page_length);
 534         ret = __copy_to_user_inatomic(user_data,
 535                                       vaddr + shmem_page_offset,
 536                                       page_length);
 537         kunmap_atomic(vaddr);
 538
 539         return ret ? -EFAULT : 0;
 540 }
 541
 542 static void
 543 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 544                              bool swizzled)
 545 {
 546         if (unlikely(swizzled)) {
 547                 unsigned long start = (unsigned long) addr;
 548                 unsigned long end = (unsigned long) addr + length;
 549
 550                 /* For swizzling simply ensure that we always flush both
 551                  * channels. Lame, but simple and it works. Swizzled
 552                  * pwrite/pread is far from a hotpath - current userspace
 553                  * doesn't use it at all. */
 554                 start = round_down(start, 128);
 555                 end = round_up(end, 128);
 556
 557                 drm_clflush_virt_range((void *)start, end - start);
 558         } else {
 559                 drm_clflush_virt_range(addr, length);
 560         }
 561
 562 }
 563
 564 /* Only difference to the fast-path function is that this can handle bit17
 565  * and uses non-atomic copy and kmap functions. */
 566 static int
 567 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 568                  char __user *user_data,
 569                  bool page_do_bit17_swizzling, bool needs_clflush)
 570 {
 571         char *vaddr;
 572         int ret;
 573
 574         vaddr = kmap(page);
 575         if (needs_clflush)
 576                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 577                                              page_length,
 578                                              page_do_bit17_swizzling);
 579
 580         if (page_do_bit17_swizzling)
 581                 ret = __copy_to_user_swizzled(user_data,
 582                                               vaddr, shmem_page_offset,
 583                                               page_length);
 584         else
 585                 ret = __copy_to_user(user_data,
 586                                      vaddr + shmem_page_offset,
 587                                      page_length);
 588         kunmap(page);
 589
 590         return ret ? - EFAULT : 0;
 591 }
 592
 593 static int
 594 i915_gem_shmem_pread(struct drm_device *dev,
 595                      struct drm_i915_gem_object *obj,
 596                      struct drm_i915_gem_pread *args,
 597                      struct drm_file *file)
 598 {
 599         char __user *user_data;
 600         ssize_t remain;
 601         loff_t offset;
 602         int shmem_page_offset, page_length, ret = 0;
 603         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 604         int prefaulted = 0;
 605         int needs_clflush = 0;
 606         struct sg_page_iter sg_iter;
 607
 608         user_data = to_user_ptr(args->data_ptr);
 609         remain = args->size;
 610
 611         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 612
 613         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 614         if (ret)
 615                 return ret;
 616
 617         offset = args->offset;
 618
 619         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 620                          offset >> PAGE_SHIFT) {
 621                 struct page *page = sg_page_iter_page(&sg_iter);
 622
 623                 if (remain <= 0)
 624                         break;
 625
 626                 /* Operation in this page
 627                  *
 628                  * shmem_page_offset = offset within page in shmem file
 629                  * page_length = bytes to copy for this page
 630                  */
 631                 shmem_page_offset = offset_in_page(offset);
 632                 page_length = remain;
 633                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 634                         page_length = PAGE_SIZE - shmem_page_offset;
 635
 636                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 637                         (page_to_phys(page) & (1 << 17)) != 0;
 638
 639                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 640                                        user_data, page_do_bit17_swizzling,
 641                                        needs_clflush);
 642                 if (ret == 0)
 643                         goto next_page;
 644
 645                 mutex_unlock(&dev->struct_mutex);
 646
 647                 if (likely(!i915.prefault_disable) && !prefaulted) {
 648                         ret = fault_in_multipages_writeable(user_data, remain);
 649                         /* Userspace is tricking us, but we've already clobbered
 650                          * its pages with the prefault and promised to write the
 651                          * data up to the first fault. Hence ignore any errors
 652                          * and just continue. */
 653                         (void)ret;
 654                         prefaulted = 1;
 655                 }
 656
 657                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 658                                        user_data, page_do_bit17_swizzling,
 659                                        needs_clflush);
 660
 661                 mutex_lock(&dev->struct_mutex);
 662
 663                 if (ret)
 664                         goto out;
 665
 666 next_page:
 667                 remain -= page_length;
 668                 user_data += page_length;
 669                 offset += page_length;
 670         }
 671
 672 out:
 673         i915_gem_object_unpin_pages(obj);
 674
 675         return ret;
 676 }
 677
 678 /**
 679  * Reads data from the object referenced by handle.
 680  *
 681  * On error, the contents of *data are undefined.
 682  */
 683 int
 684 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 685                      struct drm_file *file)
 686 {
 687         struct drm_i915_gem_pread *args = data;
 688         struct drm_i915_gem_object *obj;
 689         int ret = 0;
 690
 691         if (args->size == 0)
 692                 return 0;
 693
 694         if (!access_ok(VERIFY_WRITE,
 695                        to_user_ptr(args->data_ptr),
 696                        args->size))
 697                 return -EFAULT;
 698
 699         ret = i915_mutex_lock_interruptible(dev);
 700         if (ret)
 701                 return ret;
 702
 703         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 704         if (&obj->base == NULL) {
 705                 ret = -ENOENT;
 706                 goto unlock;
 707         }
 708
 709         /* Bounds check source.  */
 710         if (args->offset > obj->base.size ||
 711             args->size > obj->base.size - args->offset) {
 712                 ret = -EINVAL;
 713                 goto out;
 714         }
 715
 716         /* prime objects have no backing filp to GEM pread/pwrite
 717          * pages from.
 718          */
 719         if (!obj->base.filp) {
 720                 ret = -EINVAL;
 721                 goto out;
 722         }
 723
 724         trace_i915_gem_object_pread(obj, args->offset, args->size);
 725
 726         ret = i915_gem_shmem_pread(dev, obj, args, file);
 727
 728 out:
 729         drm_gem_object_unreference(&obj->base);
 730 unlock:
 731         mutex_unlock(&dev->struct_mutex);
 732         return ret;
 733 }
 734
 735 /* This is the fast write path which cannot handle
 736  * page faults in the source data
 737  */
 738
 739 static inline int
 740 fast_user_write(struct io_mapping *mapping,
 741                 loff_t page_base, int page_offset,
 742                 char __user *user_data,
 743                 int length)
 744 {
 745         void __iomem *vaddr_atomic;
 746         void *vaddr;
 747         unsigned long unwritten;
 748
 749         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 750         /* We can use the cpu mem copy function because this is X86. */
 751         vaddr = (void __force*)vaddr_atomic + page_offset;
 752         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 753                                                       user_data, length);
 754         io_mapping_unmap_atomic(vaddr_atomic);
 755         return unwritten;
 756 }
 757
 758 /**
 759  * This is the fast pwrite path, where we copy the data directly from the
 760  * user into the GTT, uncached.
 761  */
 762 static int
 763 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 764                          struct drm_i915_gem_object *obj,
 765                          struct drm_i915_gem_pwrite *args,
 766                          struct drm_file *file)
 767 {
 768         struct drm_i915_private *dev_priv = to_i915(dev);
 769         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 770         ssize_t remain;
 771         loff_t offset, page_base;
 772         char __user *user_data;
 773         int page_offset, page_length, ret;
 774
 775         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 776         if (ret)
 777                 goto out;
 778
 779         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 780         if (ret)
 781                 goto out_unpin;
 782
 783         ret = i915_gem_object_put_fence(obj);
 784         if (ret)
 785                 goto out_unpin;
 786
 787         user_data = to_user_ptr(args->data_ptr);
 788         remain = args->size;
 789
 790         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 791
 792         intel_fb_obj_invalidate(obj, ORIGIN_GTT);
 793
 794         while (remain > 0) {
 795                 /* Operation in this page
 796                  *
 797                  * page_base = page offset within aperture
 798                  * page_offset = offset within page
 799                  * page_length = bytes to copy for this page
 800                  */
 801                 page_base = offset & PAGE_MASK;
 802                 page_offset = offset_in_page(offset);
 803                 page_length = remain;
 804                 if ((page_offset + remain) > PAGE_SIZE)
 805                         page_length = PAGE_SIZE - page_offset;
 806
 807                 /* If we get a fault while copying data, then (presumably) our
 808                  * source page isn't available.  Return the error and we'll
 809                  * retry in the slow path.
 810                  */
 811                 if (fast_user_write(ggtt->mappable, page_base,
 812                                     page_offset, user_data, page_length)) {
 813                         ret = -EFAULT;
 814                         goto out_flush;
 815                 }
 816
 817                 remain -= page_length;
 818                 user_data += page_length;
 819                 offset += page_length;
 820         }
 821
 822 out_flush:
 823         intel_fb_obj_flush(obj, false, ORIGIN_GTT);
 824 out_unpin:
 825         i915_gem_object_ggtt_unpin(obj);
 826 out:
 827         return ret;
 828 }
 829
 830 /* Per-page copy function for the shmem pwrite fastpath.
 831  * Flushes invalid cachelines before writing to the target if
 832  * needs_clflush_before is set and flushes out any written cachelines after
 833  * writing if needs_clflush is set. */
 834 static int
 835 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 836                   char __user *user_data,
 837                   bool page_do_bit17_swizzling,
 838                   bool needs_clflush_before,
 839                   bool needs_clflush_after)
 840 {
 841         char *vaddr;
 842         int ret;
 843
 844         if (unlikely(page_do_bit17_swizzling))
 845                 return -EINVAL;
 846
 847         vaddr = kmap_atomic(page);
 848         if (needs_clflush_before)
 849                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 850                                        page_length);
 851         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 852                                         user_data, page_length);
 853         if (needs_clflush_after)
 854                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 855                                        page_length);
 856         kunmap_atomic(vaddr);
 857
 858         return ret ? -EFAULT : 0;
 859 }
 860
 861 /* Only difference to the fast-path function is that this can handle bit17
 862  * and uses non-atomic copy and kmap functions. */
 863 static int
 864 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 865                   char __user *user_data,
 866                   bool page_do_bit17_swizzling,
 867                   bool needs_clflush_before,
 868                   bool needs_clflush_after)
 869 {
 870         char *vaddr;
 871         int ret;
 872
 873         vaddr = kmap(page);
 874         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 875                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 876                                              page_length,
 877                                              page_do_bit17_swizzling);
 878         if (page_do_bit17_swizzling)
 879                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 880                                                 user_data,
 881                                                 page_length);
 882         else
 883                 ret = __copy_from_user(vaddr + shmem_page_offset,
 884                                        user_data,
 885                                        page_length);
 886         if (needs_clflush_after)
 887                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 888                                              page_length,
 889                                              page_do_bit17_swizzling);
 890         kunmap(page);
 891
 892         return ret ? -EFAULT : 0;
 893 }
 894
 895 static int
 896 i915_gem_shmem_pwrite(struct drm_device *dev,
 897                       struct drm_i915_gem_object *obj,
 898                       struct drm_i915_gem_pwrite *args,
 899                       struct drm_file *file)
 900 {
 901         ssize_t remain;
 902         loff_t offset;
 903         char __user *user_data;
 904         int shmem_page_offset, page_length, ret = 0;
 905         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 906         int hit_slowpath = 0;
 907         int needs_clflush_after = 0;
 908         int needs_clflush_before = 0;
 909         struct sg_page_iter sg_iter;
 910
 911         user_data = to_user_ptr(args->data_ptr);
 912         remain = args->size;
 913
 914         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 915
 916         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 917                 /* If we're not in the cpu write domain, set ourself into the gtt
 918                  * write domain and manually flush cachelines (if required). This
 919                  * optimizes for the case when the gpu will use the data
 920                  * right away and we therefore have to clflush anyway. */
 921                 needs_clflush_after = cpu_write_needs_clflush(obj);
 922                 ret = i915_gem_object_wait_rendering(obj, false);
 923                 if (ret)
 924                         return ret;
 925         }
 926         /* Same trick applies to invalidate partially written cachelines read
 927          * before writing. */
 928         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 929                 needs_clflush_before =
 930                         !cpu_cache_is_coherent(dev, obj->cache_level);
 931
 932         ret = i915_gem_object_get_pages(obj);
 933         if (ret)
 934                 return ret;
 935
 936         intel_fb_obj_invalidate(obj, ORIGIN_CPU);
 937
 938         i915_gem_object_pin_pages(obj);
 939
 940         offset = args->offset;
 941         obj->dirty = 1;
 942
 943         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 944                          offset >> PAGE_SHIFT) {
 945                 struct page *page = sg_page_iter_page(&sg_iter);
 946                 int partial_cacheline_write;
 947
 948                 if (remain <= 0)
 949                         break;
 950
 951                 /* Operation in this page
 952                  *
 953                  * shmem_page_offset = offset within page in shmem file
 954                  * page_length = bytes to copy for this page
 955                  */
 956                 shmem_page_offset = offset_in_page(offset);
 957
 958                 page_length = remain;
 959                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 960                         page_length = PAGE_SIZE - shmem_page_offset;
 961
 962                 /* If we don't overwrite a cacheline completely we need to be
 963                  * careful to have up-to-date data by first clflushing. Don't
 964                  * overcomplicate things and flush the entire patch. */
 965                 partial_cacheline_write = needs_clflush_before &&
 966                         ((shmem_page_offset | page_length)
 967                                 & (boot_cpu_data.x86_clflush_size - 1));
 968
 969                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 970                         (page_to_phys(page) & (1 << 17)) != 0;
 971
 972                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 973                                         user_data, page_do_bit17_swizzling,
 974                                         partial_cacheline_write,
 975                                         needs_clflush_after);
 976                 if (ret == 0)
 977                         goto next_page;
 978
 979                 hit_slowpath = 1;
 980                 mutex_unlock(&dev->struct_mutex);
 981                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 982                                         user_data, page_do_bit17_swizzling,
 983                                         partial_cacheline_write,
 984                                         needs_clflush_after);
 985
 986                 mutex_lock(&dev->struct_mutex);
 987
 988                 if (ret)
 989                         goto out;
 990
 991 next_page:
 992                 remain -= page_length;
 993                 user_data += page_length;
 994                 offset += page_length;
 995         }
 996
 997 out:
 998         i915_gem_object_unpin_pages(obj);
 999
1000         if (hit_slowpath) {
1001                 /*
1002                  * Fixup: Flush cpu caches in case we didn't flush the dirty
1003                  * cachelines in-line while writing and the object moved
1004                  * out of the cpu write domain while we've dropped the lock.
1005                  */
1006                 if (!needs_clflush_after &&
1007                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1008                         if (i915_gem_clflush_object(obj, obj->pin_display))
1009                                 needs_clflush_after = true;
1010                 }
1011         }
1012
1013         if (needs_clflush_after)
1014                 i915_gem_chipset_flush(dev);
1015         else
1016                 obj->cache_dirty = true;
1017
1018         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1019         return ret;
1020 }
1021
1022 /**
1023  * Writes data to the object referenced by handle.
1024  *
1025  * On error, the contents of the buffer that were to be modified are undefined.
1026  */
1027 int
1028 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1029                       struct drm_file *file)
1030 {
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032         struct drm_i915_gem_pwrite *args = data;
1033         struct drm_i915_gem_object *obj;
1034         int ret;
1035
1036         if (args->size == 0)
1037                 return 0;
1038
1039         if (!access_ok(VERIFY_READ,
1040                        to_user_ptr(args->data_ptr),
1041                        args->size))
1042                 return -EFAULT;
1043
1044         if (likely(!i915.prefault_disable)) {
1045                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1046                                                    args->size);
1047                 if (ret)
1048                         return -EFAULT;
1049         }
1050
1051         intel_runtime_pm_get(dev_priv);
1052
1053         ret = i915_mutex_lock_interruptible(dev);
1054         if (ret)
1055                 goto put_rpm;
1056
1057         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1058         if (&obj->base == NULL) {
1059                 ret = -ENOENT;
1060                 goto unlock;
1061         }
1062
1063         /* Bounds check destination. */
1064         if (args->offset > obj->base.size ||
1065             args->size > obj->base.size - args->offset) {
1066                 ret = -EINVAL;
1067                 goto out;
1068         }
1069
1070         /* prime objects have no backing filp to GEM pread/pwrite
1071          * pages from.
1072          */
1073         if (!obj->base.filp) {
1074                 ret = -EINVAL;
1075                 goto out;
1076         }
1077
1078         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1079
1080         ret = -EFAULT;
1081         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1082          * it would end up going through the fenced access, and we'll get
1083          * different detiling behavior between reading and writing.
1084          * pread/pwrite currently are reading and writing from the CPU
1085          * perspective, requiring manual detiling by the client.
1086          */
1087         if (obj->tiling_mode == I915_TILING_NONE &&
1088             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1089             cpu_write_needs_clflush(obj)) {
1090                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1091                 /* Note that the gtt paths might fail with non-page-backed user
1092                  * pointers (e.g. gtt mappings when moving data between
1093                  * textures). Fallback to the shmem path in that case. */
1094         }
1095
1096         if (ret == -EFAULT || ret == -ENOSPC) {
1097                 if (obj->phys_handle)
1098                         ret = i915_gem_phys_pwrite(obj, args, file);
1099                 else
1100                         ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1101         }
1102
1103 out:
1104         drm_gem_object_unreference(&obj->base);
1105 unlock:
1106         mutex_unlock(&dev->struct_mutex);
1107 put_rpm:
1108         intel_runtime_pm_put(dev_priv);
1109
1110         return ret;
1111 }
1112
1113 int
1114 i915_gem_check_wedge(struct i915_gpu_error *error,
1115                      bool interruptible)
1116 {
1117         if (i915_reset_in_progress(error)) {
1118                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1119                  * -EIO unconditionally for these. */
1120                 if (!interruptible)
1121                         return -EIO;
1122
1123                 /* Recovery complete, but the reset failed ... */
1124                 if (i915_terminally_wedged(error))
1125                         return -EIO;
1126
1127                 /*
1128                  * Check if GPU Reset is in progress - we need intel_ring_begin
1129                  * to work properly to reinit the hw state while the gpu is
1130                  * still marked as reset-in-progress. Handle this with a flag.
1131                  */
1132                 if (!error->reload_in_reset)
1133                         return -EAGAIN;
1134         }
1135
1136         return 0;
1137 }
1138
1139 static void fake_irq(unsigned long data)
1140 {
1141         wake_up_process((struct task_struct *)data);
1142 }
1143
1144 static bool missed_irq(struct drm_i915_private *dev_priv,
1145                        struct intel_engine_cs *engine)
1146 {
1147         return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings);
1148 }
1149
1150 static unsigned long local_clock_us(unsigned *cpu)
1151 {
1152         unsigned long t;
1153
1154         /* Cheaply and approximately convert from nanoseconds to microseconds.
1155          * The result and subsequent calculations are also defined in the same
1156          * approximate microseconds units. The principal source of timing
1157          * error here is from the simple truncation.
1158          *
1159          * Note that local_clock() is only defined wrt to the current CPU;
1160          * the comparisons are no longer valid if we switch CPUs. Instead of
1161          * blocking preemption for the entire busywait, we can detect the CPU
1162          * switch and use that as indicator of system load and a reason to
1163          * stop busywaiting, see busywait_stop().
1164          */
1165         *cpu = get_cpu();
1166         t = local_clock() >> 10;
1167         put_cpu();
1168
1169         return t;
1170 }
1171
1172 static bool busywait_stop(unsigned long timeout, unsigned cpu)
1173 {
1174         unsigned this_cpu;
1175
1176         if (time_after(local_clock_us(&this_cpu), timeout))
1177                 return true;
1178
1179         return this_cpu != cpu;
1180 }
1181
1182 static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
1183 {
1184         unsigned long timeout;
1185         unsigned cpu;
1186
1187         /* When waiting for high frequency requests, e.g. during synchronous
1188          * rendering split between the CPU and GPU, the finite amount of time
1189          * required to set up the irq and wait upon it limits the response
1190          * rate. By busywaiting on the request completion for a short while we
1191          * can service the high frequency waits as quick as possible. However,
1192          * if it is a slow request, we want to sleep as quickly as possible.
1193          * The tradeoff between waiting and sleeping is roughly the time it
1194          * takes to sleep on a request, on the order of a microsecond.
1195          */
1196
1197         if (req->engine->irq_refcount)
1198                 return -EBUSY;
1199
1200         /* Only spin if we know the GPU is processing this request */
1201         if (!i915_gem_request_started(req, true))
1202                 return -EAGAIN;
1203
1204         timeout = local_clock_us(&cpu) + 5;
1205         while (!need_resched()) {
1206                 if (i915_gem_request_completed(req, true))
1207                         return 0;
1208
1209                 if (signal_pending_state(state, current))
1210                         break;
1211
1212                 if (busywait_stop(timeout, cpu))
1213                         break;
1214
1215                 cpu_relax_lowlatency();
1216         }
1217
1218         if (i915_gem_request_completed(req, false))
1219                 return 0;
1220
1221         return -EAGAIN;
1222 }
1223
1224 /**
1225  * __i915_wait_request - wait until execution of request has finished
1226  * @req: duh!
1227  * @reset_counter: reset sequence associated with the given request
1228  * @interruptible: do an interruptible wait (normally yes)
1229  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1230  *
1231  * Note: It is of utmost importance that the passed in seqno and reset_counter
1232  * values have been read by the caller in an smp safe manner. Where read-side
1233  * locks are involved, it is sufficient to read the reset_counter before
1234  * unlocking the lock that protects the seqno. For lockless tricks, the
1235  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1236  * inserted.
1237  *
1238  * Returns 0 if the request was found within the alloted time. Else returns the
1239  * errno with remaining time filled in timeout argument.
1240  */
1241 int __i915_wait_request(struct drm_i915_gem_request *req,
1242                         unsigned reset_counter,
1243                         bool interruptible,
1244                         s64 *timeout,
1245                         struct intel_rps_client *rps)
1246 {
1247         struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
1248         struct drm_device *dev = engine->dev;
1249         struct drm_i915_private *dev_priv = dev->dev_private;
1250         const bool irq_test_in_progress =
1251                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine);
1252         int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1253         DEFINE_WAIT(wait);
1254         unsigned long timeout_expire;
1255         s64 before = 0; /* Only to silence a compiler warning. */
1256         int ret;
1257
1258         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1259
1260         if (list_empty(&req->list))
1261                 return 0;
1262
1263         if (i915_gem_request_completed(req, true))
1264                 return 0;
1265
1266         timeout_expire = 0;
1267         if (timeout) {
1268                 if (WARN_ON(*timeout < 0))
1269                         return -EINVAL;
1270
1271                 if (*timeout == 0)
1272                         return -ETIME;
1273
1274                 timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout);
1275
1276                 /*
1277                  * Record current time in case interrupted by signal, or wedged.
1278                  */
1279                 before = ktime_get_raw_ns();
1280         }
1281
1282         if (INTEL_INFO(dev_priv)->gen >= 6)
1283                 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1284
1285         trace_i915_gem_request_wait_begin(req);
1286
1287         /* Optimistic spin for the next jiffie before touching IRQs */
1288         ret = __i915_spin_request(req, state);
1289         if (ret == 0)
1290                 goto out;
1291
1292         if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) {
1293                 ret = -ENODEV;
1294                 goto out;
1295         }
1296
1297         for (;;) {
1298                 struct timer_list timer;
1299
1300                 prepare_to_wait(&engine->irq_queue, &wait, state);
1301
1302                 /* We need to check whether any gpu reset happened in between
1303                  * the caller grabbing the seqno and now ... */
1304                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1305                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1306                          * is truely gone. */
1307                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1308                         if (ret == 0)
1309                                 ret = -EAGAIN;
1310                         break;
1311                 }
1312
1313                 if (i915_gem_request_completed(req, false)) {
1314                         ret = 0;
1315                         break;
1316                 }
1317
1318                 if (signal_pending_state(state, current)) {
1319                         ret = -ERESTARTSYS;
1320                         break;
1321                 }
1322
1323                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1324                         ret = -ETIME;
1325                         break;
1326                 }
1327
1328                 timer.function = NULL;
1329                 if (timeout || missed_irq(dev_priv, engine)) {
1330                         unsigned long expire;
1331
1332                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1333                         expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire;
1334                         mod_timer(&timer, expire);
1335                 }
1336
1337                 io_schedule();
1338
1339                 if (timer.function) {
1340                         del_singleshot_timer_sync(&timer);
1341                         destroy_timer_on_stack(&timer);
1342                 }
1343         }
1344         if (!irq_test_in_progress)
1345                 engine->irq_put(engine);
1346
1347         finish_wait(&engine->irq_queue, &wait);
1348
1349 out:
1350         trace_i915_gem_request_wait_end(req);
1351
1352         if (timeout) {
1353                 s64 tres = *timeout - (ktime_get_raw_ns() - before);
1354
1355                 *timeout = tres < 0 ? 0 : tres;
1356
1357                 /*
1358                  * Apparently ktime isn't accurate enough and occasionally has a
1359                  * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1360                  * things up to make the test happy. We allow up to 1 jiffy.
1361                  *
1362                  * This is a regrssion from the timespec->ktime conversion.
1363                  */
1364                 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1365                         *timeout = 0;
1366         }
1367
1368         return ret;
1369 }
1370
1371 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1372                                    struct drm_file *file)
1373 {
1374         struct drm_i915_file_private *file_priv;
1375
1376         WARN_ON(!req || !file || req->file_priv);
1377
1378         if (!req || !file)
1379                 return -EINVAL;
1380
1381         if (req->file_priv)
1382                 return -EINVAL;
1383
1384         file_priv = file->driver_priv;
1385
1386         spin_lock(&file_priv->mm.lock);
1387         req->file_priv = file_priv;
1388         list_add_tail(&req->client_list, &file_priv->mm.request_list);
1389         spin_unlock(&file_priv->mm.lock);
1390
1391         req->pid = get_pid(task_pid(current));
1392
1393         return 0;
1394 }
1395
1396 static inline void
1397 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1398 {
1399         struct drm_i915_file_private *file_priv = request->file_priv;
1400
1401         if (!file_priv)
1402                 return;
1403
1404         spin_lock(&file_priv->mm.lock);
1405         list_del(&request->client_list);
1406         request->file_priv = NULL;
1407         spin_unlock(&file_priv->mm.lock);
1408
1409         put_pid(request->pid);
1410         request->pid = NULL;
1411 }
1412
1413 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1414 {
1415         trace_i915_gem_request_retire(request);
1416
1417         /* We know the GPU must have read the request to have
1418          * sent us the seqno + interrupt, so use the position
1419          * of tail of the request to update the last known position
1420          * of the GPU head.
1421          *
1422          * Note this requires that we are always called in request
1423          * completion order.
1424          */
1425         request->ringbuf->last_retired_head = request->postfix;
1426
1427         list_del_init(&request->list);
1428         i915_gem_request_remove_from_client(request);
1429
1430         i915_gem_request_unreference(request);
1431 }
1432
1433 static void
1434 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1435 {
1436         struct intel_engine_cs *engine = req->engine;
1437         struct drm_i915_gem_request *tmp;
1438
1439         lockdep_assert_held(&engine->dev->struct_mutex);
1440
1441         if (list_empty(&req->list))
1442                 return;
1443
1444         do {
1445                 tmp = list_first_entry(&engine->request_list,
1446                                        typeof(*tmp), list);
1447
1448                 i915_gem_request_retire(tmp);
1449         } while (tmp != req);
1450
1451         WARN_ON(i915_verify_lists(engine->dev));
1452 }
1453
1454 /**
1455  * Waits for a request to be signaled, and cleans up the
1456  * request and object lists appropriately for that event.
1457  */
1458 int
1459 i915_wait_request(struct drm_i915_gem_request *req)
1460 {
1461         struct drm_device *dev;
1462         struct drm_i915_private *dev_priv;
1463         bool interruptible;
1464         int ret;
1465
1466         BUG_ON(req == NULL);
1467
1468         dev = req->engine->dev;
1469         dev_priv = dev->dev_private;
1470         interruptible = dev_priv->mm.interruptible;
1471
1472         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1473
1474         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1475         if (ret)
1476                 return ret;
1477
1478         ret = __i915_wait_request(req,
1479                                   atomic_read(&dev_priv->gpu_error.reset_counter),
1480                                   interruptible, NULL, NULL);
1481         if (ret)
1482                 return ret;
1483
1484         __i915_gem_request_retire__upto(req);
1485         return 0;
1486 }
1487
1488 /**
1489  * Ensures that all rendering to the object has completed and the object is
1490  * safe to unbind from the GTT or access from the CPU.
1491  */
1492 int
1493 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1494                                bool readonly)
1495 {
1496         int ret, i;
1497
1498         if (!obj->active)
1499                 return 0;
1500
1501         if (readonly) {
1502                 if (obj->last_write_req != NULL) {
1503                         ret = i915_wait_request(obj->last_write_req);
1504                         if (ret)
1505                                 return ret;
1506
1507                         i = obj->last_write_req->engine->id;
1508                         if (obj->last_read_req[i] == obj->last_write_req)
1509                                 i915_gem_object_retire__read(obj, i);
1510                         else
1511                                 i915_gem_object_retire__write(obj);
1512                 }
1513         } else {
1514                 for (i = 0; i < I915_NUM_ENGINES; i++) {
1515                         if (obj->last_read_req[i] == NULL)
1516                                 continue;
1517
1518                         ret = i915_wait_request(obj->last_read_req[i]);
1519                         if (ret)
1520                                 return ret;
1521
1522                         i915_gem_object_retire__read(obj, i);
1523                 }
1524                 RQ_BUG_ON(obj->active);
1525         }
1526
1527         return 0;
1528 }
1529
1530 static void
1531 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1532                                struct drm_i915_gem_request *req)
1533 {
1534         int ring = req->engine->id;
1535
1536         if (obj->last_read_req[ring] == req)
1537                 i915_gem_object_retire__read(obj, ring);
1538         else if (obj->last_write_req == req)
1539                 i915_gem_object_retire__write(obj);
1540
1541         __i915_gem_request_retire__upto(req);
1542 }
1543
1544 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1545  * as the object state may change during this call.
1546  */
1547 static __must_check int
1548 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1549                                             struct intel_rps_client *rps,
1550                                             bool readonly)
1551 {
1552         struct drm_device *dev = obj->base.dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
1555         unsigned reset_counter;
1556         int ret, i, n = 0;
1557
1558         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1559         BUG_ON(!dev_priv->mm.interruptible);
1560
1561         if (!obj->active)
1562                 return 0;
1563
1564         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1565         if (ret)
1566                 return ret;
1567
1568         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1569
1570         if (readonly) {
1571                 struct drm_i915_gem_request *req;
1572
1573                 req = obj->last_write_req;
1574                 if (req == NULL)
1575                         return 0;
1576
1577                 requests[n++] = i915_gem_request_reference(req);
1578         } else {
1579                 for (i = 0; i < I915_NUM_ENGINES; i++) {
1580                         struct drm_i915_gem_request *req;
1581
1582                         req = obj->last_read_req[i];
1583                         if (req == NULL)
1584                                 continue;
1585
1586                         requests[n++] = i915_gem_request_reference(req);
1587                 }
1588         }
1589
1590         mutex_unlock(&dev->struct_mutex);
1591         for (i = 0; ret == 0 && i < n; i++)
1592                 ret = __i915_wait_request(requests[i], reset_counter, true,
1593                                           NULL, rps);
1594         mutex_lock(&dev->struct_mutex);
1595
1596         for (i = 0; i < n; i++) {
1597                 if (ret == 0)
1598                         i915_gem_object_retire_request(obj, requests[i]);
1599                 i915_gem_request_unreference(requests[i]);
1600         }
1601
1602         return ret;
1603 }
1604
1605 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1606 {
1607         struct drm_i915_file_private *fpriv = file->driver_priv;
1608         return &fpriv->rps;
1609 }
1610
1611 /**
1612  * Called when user space prepares to use an object with the CPU, either
1613  * through the mmap ioctl's mapping or a GTT mapping.
1614  */
1615 int
1616 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1617                           struct drm_file *file)
1618 {
1619         struct drm_i915_gem_set_domain *args = data;
1620         struct drm_i915_gem_object *obj;
1621         uint32_t read_domains = args->read_domains;
1622         uint32_t write_domain = args->write_domain;
1623         int ret;
1624
1625         /* Only handle setting domains to types used by the CPU. */
1626         if (write_domain & I915_GEM_GPU_DOMAINS)
1627                 return -EINVAL;
1628
1629         if (read_domains & I915_GEM_GPU_DOMAINS)
1630                 return -EINVAL;
1631
1632         /* Having something in the write domain implies it's in the read
1633          * domain, and only that read domain.  Enforce that in the request.
1634          */
1635         if (write_domain != 0 && read_domains != write_domain)
1636                 return -EINVAL;
1637
1638         ret = i915_mutex_lock_interruptible(dev);
1639         if (ret)
1640                 return ret;
1641
1642         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1643         if (&obj->base == NULL) {
1644                 ret = -ENOENT;
1645                 goto unlock;
1646         }
1647
1648         /* Try to flush the object off the GPU without holding the lock.
1649          * We will repeat the flush holding the lock in the normal manner
1650          * to catch cases where we are gazumped.
1651          */
1652         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1653                                                           to_rps_client(file),
1654                                                           !write_domain);
1655         if (ret)
1656                 goto unref;
1657
1658         if (read_domains & I915_GEM_DOMAIN_GTT)
1659                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1660         else
1661                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1662
1663         if (write_domain != 0)
1664                 intel_fb_obj_invalidate(obj,
1665                                         write_domain == I915_GEM_DOMAIN_GTT ?
1666                                         ORIGIN_GTT : ORIGIN_CPU);
1667
1668 unref:
1669         drm_gem_object_unreference(&obj->base);
1670 unlock:
1671         mutex_unlock(&dev->struct_mutex);
1672         return ret;
1673 }
1674
1675 /**
1676  * Called when user space has done writes to this buffer
1677  */
1678 int
1679 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1680                          struct drm_file *file)
1681 {
1682         struct drm_i915_gem_sw_finish *args = data;
1683         struct drm_i915_gem_object *obj;
1684         int ret = 0;
1685
1686         ret = i915_mutex_lock_interruptible(dev);
1687         if (ret)
1688                 return ret;
1689
1690         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1691         if (&obj->base == NULL) {
1692                 ret = -ENOENT;
1693                 goto unlock;
1694         }
1695
1696         /* Pinned buffers may be scanout, so flush the cache */
1697         if (obj->pin_display)
1698                 i915_gem_object_flush_cpu_write_domain(obj);
1699
1700         drm_gem_object_unreference(&obj->base);
1701 unlock:
1702         mutex_unlock(&dev->struct_mutex);
1703         return ret;
1704 }
1705
1706 /**
1707  * Maps the contents of an object, returning the address it is mapped
1708  * into.
1709  *
1710  * While the mapping holds a reference on the contents of the object, it doesn't
1711  * imply a ref on the object itself.
1712  *
1713  * IMPORTANT:
1714  *
1715  * DRM driver writers who look a this function as an example for how to do GEM
1716  * mmap support, please don't implement mmap support like here. The modern way
1717  * to implement DRM mmap support is with an mmap offset ioctl (like
1718  * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1719  * That way debug tooling like valgrind will understand what's going on, hiding
1720  * the mmap call in a driver private ioctl will break that. The i915 driver only
1721  * does cpu mmaps this way because we didn't know better.
1722  */
1723 int
1724 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1725                     struct drm_file *file)
1726 {
1727         struct drm_i915_gem_mmap *args = data;
1728         struct drm_gem_object *obj;
1729         unsigned long addr;
1730
1731         if (args->flags & ~(I915_MMAP_WC))
1732                 return -EINVAL;
1733
1734         if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1735                 return -ENODEV;
1736
1737         obj = drm_gem_object_lookup(dev, file, args->handle);
1738         if (obj == NULL)
1739                 return -ENOENT;
1740
1741         /* prime objects have no backing filp to GEM mmap
1742          * pages from.
1743          */
1744         if (!obj->filp) {
1745                 drm_gem_object_unreference_unlocked(obj);
1746                 return -EINVAL;
1747         }
1748
1749         addr = vm_mmap(obj->filp, 0, args->size,
1750                        PROT_READ | PROT_WRITE, MAP_SHARED,
1751                        args->offset);
1752         if (args->flags & I915_MMAP_WC) {
1753                 struct mm_struct *mm = current->mm;
1754                 struct vm_area_struct *vma;
1755
1756                 down_write(&mm->mmap_sem);
1757                 vma = find_vma(mm, addr);
1758                 if (vma)
1759                         vma->vm_page_prot =
1760                                 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1761                 else
1762                         addr = -ENOMEM;
1763                 up_write(&mm->mmap_sem);
1764         }
1765         drm_gem_object_unreference_unlocked(obj);
1766         if (IS_ERR((void *)addr))
1767                 return addr;
1768
1769         args->addr_ptr = (uint64_t) addr;
1770
1771         return 0;
1772 }
1773
1774 /**
1775  * i915_gem_fault - fault a page into the GTT
1776  * @vma: VMA in question
1777  * @vmf: fault info
1778  *
1779  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1780  * from userspace.  The fault handler takes care of binding the object to
1781  * the GTT (if needed), allocating and programming a fence register (again,
1782  * only if needed based on whether the old reg is still valid or the object
1783  * is tiled) and inserting a new PTE into the faulting process.
1784  *
1785  * Note that the faulting process may involve evicting existing objects
1786  * from the GTT and/or fence registers to make room.  So performance may
1787  * suffer if the GTT working set is large or there are few fence registers
1788  * left.
1789  */
1790 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1791 {
1792         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1793         struct drm_device *dev = obj->base.dev;
1794         struct drm_i915_private *dev_priv = to_i915(dev);
1795         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1796         struct i915_ggtt_view view = i915_ggtt_view_normal;
1797         pgoff_t page_offset;
1798         unsigned long pfn;
1799         int ret = 0;
1800         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1801
1802         intel_runtime_pm_get(dev_priv);
1803
1804         /* We don't use vmf->pgoff since that has the fake offset */
1805         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1806                 PAGE_SHIFT;
1807
1808         ret = i915_mutex_lock_interruptible(dev);
1809         if (ret)
1810                 goto out;
1811
1812         trace_i915_gem_object_fault(obj, page_offset, true, write);
1813
1814         /* Try to flush the object off the GPU first without holding the lock.
1815          * Upon reacquiring the lock, we will perform our sanity checks and then
1816          * repeat the flush holding the lock in the normal manner to catch cases
1817          * where we are gazumped.
1818          */
1819         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1820         if (ret)
1821                 goto unlock;
1822
1823         /* Access to snoopable pages through the GTT is incoherent. */
1824         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1825                 ret = -EFAULT;
1826                 goto unlock;
1827         }
1828
1829         /* Use a partial view if the object is bigger than the aperture. */
1830         if (obj->base.size >= ggtt->mappable_end &&
1831             obj->tiling_mode == I915_TILING_NONE) {
1832                 static const unsigned int chunk_size = 256; // 1 MiB
1833
1834                 memset(&view, 0, sizeof(view));
1835                 view.type = I915_GGTT_VIEW_PARTIAL;
1836                 view.params.partial.offset = rounddown(page_offset, chunk_size);
1837                 view.params.partial.size =
1838                         min_t(unsigned int,
1839                               chunk_size,
1840                               (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1841                               view.params.partial.offset);
1842         }
1843
1844         /* Now pin it into the GTT if needed */
1845         ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1846         if (ret)
1847                 goto unlock;
1848
1849         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1850         if (ret)
1851                 goto unpin;
1852
1853         ret = i915_gem_object_get_fence(obj);
1854         if (ret)
1855                 goto unpin;
1856
1857         /* Finally, remap it using the new GTT offset */
1858         pfn = ggtt->mappable_base +
1859                 i915_gem_obj_ggtt_offset_view(obj, &view);
1860         pfn >>= PAGE_SHIFT;
1861
1862         if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1863                 /* Overriding existing pages in partial view does not cause
1864                  * us any trouble as TLBs are still valid because the fault
1865                  * is due to userspace losing part of the mapping or never
1866                  * having accessed it before (at this partials' range).
1867                  */
1868                 unsigned long base = vma->vm_start +
1869                                      (view.params.partial.offset << PAGE_SHIFT);
1870                 unsigned int i;
1871
1872                 for (i = 0; i < view.params.partial.size; i++) {
1873                         ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1874                         if (ret)
1875                                 break;
1876                 }
1877
1878                 obj->fault_mappable = true;
1879         } else {
1880                 if (!obj->fault_mappable) {
1881                         unsigned long size = min_t(unsigned long,
1882                                                    vma->vm_end - vma->vm_start,
1883                                                    obj->base.size);
1884                         int i;
1885
1886                         for (i = 0; i < size >> PAGE_SHIFT; i++) {
1887                                 ret = vm_insert_pfn(vma,
1888                                                     (unsigned long)vma->vm_start + i * PAGE_SIZE,
1889                                                     pfn + i);
1890                                 if (ret)
1891                                         break;
1892                         }
1893
1894                         obj->fault_mappable = true;
1895                 } else
1896                         ret = vm_insert_pfn(vma,
1897                                             (unsigned long)vmf->virtual_address,
1898                                             pfn + page_offset);
1899         }
1900 unpin:
1901         i915_gem_object_ggtt_unpin_view(obj, &view);
1902 unlock:
1903         mutex_unlock(&dev->struct_mutex);
1904 out:
1905         switch (ret) {
1906         case -EIO:
1907                 /*
1908                  * We eat errors when the gpu is terminally wedged to avoid
1909                  * userspace unduly crashing (gl has no provisions for mmaps to
1910                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
1911                  * and so needs to be reported.
1912                  */
1913                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1914                         ret = VM_FAULT_SIGBUS;
1915                         break;
1916                 }
1917         case -EAGAIN:
1918                 /*
1919                  * EAGAIN means the gpu is hung and we'll wait for the error
1920                  * handler to reset everything when re-faulting in
1921                  * i915_mutex_lock_interruptible.
1922                  */
1923         case 0:
1924         case -ERESTARTSYS:
1925         case -EINTR:
1926         case -EBUSY:
1927                 /*
1928                  * EBUSY is ok: this just means that another thread
1929                  * already did the job.
1930                  */
1931                 ret = VM_FAULT_NOPAGE;
1932                 break;
1933         case -ENOMEM:
1934                 ret = VM_FAULT_OOM;
1935                 break;
1936         case -ENOSPC:
1937         case -EFAULT:
1938                 ret = VM_FAULT_SIGBUS;
1939                 break;
1940         default:
1941                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1942                 ret = VM_FAULT_SIGBUS;
1943                 break;
1944         }
1945
1946         intel_runtime_pm_put(dev_priv);
1947         return ret;
1948 }
1949
1950 /**
1951  * i915_gem_release_mmap - remove physical page mappings
1952  * @obj: obj in question
1953  *
1954  * Preserve the reservation of the mmapping with the DRM core code, but
1955  * relinquish ownership of the pages back to the system.
1956  *
1957  * It is vital that we remove the page mapping if we have mapped a tiled
1958  * object through the GTT and then lose the fence register due to
1959  * resource pressure. Similarly if the object has been moved out of the
1960  * aperture, than pages mapped into userspace must be revoked. Removing the
1961  * mapping will then trigger a page fault on the next user access, allowing
1962  * fixup by i915_gem_fault().
1963  */
1964 void
1965 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1966 {
1967         if (!obj->fault_mappable)
1968                 return;
1969
1970         drm_vma_node_unmap(&obj->base.vma_node,
1971                            obj->base.dev->anon_inode->i_mapping);
1972         obj->fault_mappable = false;
1973 }
1974
1975 void
1976 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1977 {
1978         struct drm_i915_gem_object *obj;
1979
1980         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1981                 i915_gem_release_mmap(obj);
1982 }
1983
1984 uint32_t
1985 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1986 {
1987         uint32_t gtt_size;
1988
1989         if (INTEL_INFO(dev)->gen >= 4 ||
1990             tiling_mode == I915_TILING_NONE)
1991                 return size;
1992
1993         /* Previous chips need a power-of-two fence region when tiling */
1994         if (INTEL_INFO(dev)->gen == 3)
1995                 gtt_size = 1024*1024;
1996         else
1997                 gtt_size = 512*1024;
1998
1999         while (gtt_size < size)
2000                 gtt_size <<= 1;
2001
2002         return gtt_size;
2003 }
2004
2005 /**
2006  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2007  * @obj: object to check
2008  *
2009  * Return the required GTT alignment for an object, taking into account
2010  * potential fence register mapping.
2011  */
2012 uint32_t
2013 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2014                            int tiling_mode, bool fenced)
2015 {
2016         /*
2017          * Minimum alignment is 4k (GTT page size), but might be greater
2018          * if a fence register is needed for the object.
2019          */
2020         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
2021             tiling_mode == I915_TILING_NONE)
2022                 return 4096;
2023
2024         /*
2025          * Previous chips need to be aligned to the size of the smallest
2026          * fence register that can contain the object.
2027          */
2028         return i915_gem_get_gtt_size(dev, size, tiling_mode);
2029 }
2030
2031 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2032 {
2033         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2034         int ret;
2035
2036         if (drm_vma_node_has_offset(&obj->base.vma_node))
2037                 return 0;
2038
2039         dev_priv->mm.shrinker_no_lock_stealing = true;
2040
2041         ret = drm_gem_create_mmap_offset(&obj->base);
2042         if (ret != -ENOSPC)
2043                 goto out;
2044
2045         /* Badly fragmented mmap space? The only way we can recover
2046          * space is by destroying unwanted objects. We can't randomly release
2047          * mmap_offsets as userspace expects them to be persistent for the
2048          * lifetime of the objects. The closest we can is to release the
2049          * offsets on purgeable objects by truncating it and marking it purged,
2050          * which prevents userspace from ever using that object again.
2051          */
2052         i915_gem_shrink(dev_priv,
2053                         obj->base.size >> PAGE_SHIFT,
2054                         I915_SHRINK_BOUND |
2055                         I915_SHRINK_UNBOUND |
2056                         I915_SHRINK_PURGEABLE);
2057         ret = drm_gem_create_mmap_offset(&obj->base);
2058         if (ret != -ENOSPC)
2059                 goto out;
2060
2061         i915_gem_shrink_all(dev_priv);
2062         ret = drm_gem_create_mmap_offset(&obj->base);
2063 out:
2064         dev_priv->mm.shrinker_no_lock_stealing = false;
2065
2066         return ret;
2067 }
2068
2069 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2070 {
2071         drm_gem_free_mmap_offset(&obj->base);
2072 }
2073
2074 int
2075 i915_gem_mmap_gtt(struct drm_file *file,
2076                   struct drm_device *dev,
2077                   uint32_t handle,
2078                   uint64_t *offset)
2079 {
2080         struct drm_i915_gem_object *obj;
2081         int ret;
2082
2083         ret = i915_mutex_lock_interruptible(dev);
2084         if (ret)
2085                 return ret;
2086
2087         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2088         if (&obj->base == NULL) {
2089                 ret = -ENOENT;
2090                 goto unlock;
2091         }
2092
2093         if (obj->madv != I915_MADV_WILLNEED) {
2094                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2095                 ret = -EFAULT;
2096                 goto out;
2097         }
2098
2099         ret = i915_gem_object_create_mmap_offset(obj);
2100         if (ret)
2101                 goto out;
2102
2103         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2104
2105 out:
2106         drm_gem_object_unreference(&obj->base);
2107 unlock:
2108         mutex_unlock(&dev->struct_mutex);
2109         return ret;
2110 }
2111
2112 /**
2113  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2114  * @dev: DRM device
2115  * @data: GTT mapping ioctl data
2116  * @file: GEM object info
2117  *
2118  * Simply returns the fake offset to userspace so it can mmap it.
2119  * The mmap call will end up in drm_gem_mmap(), which will set things
2120  * up so we can get faults in the handler above.
2121  *
2122  * The fault handler will take care of binding the object into the GTT
2123  * (since it may have been evicted to make room for something), allocating
2124  * a fence register, and mapping the appropriate aperture address into
2125  * userspace.
2126  */
2127 int
2128 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2129                         struct drm_file *file)
2130 {
2131         struct drm_i915_gem_mmap_gtt *args = data;
2132
2133         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2134 }
2135
2136 /* Immediately discard the backing storage */
2137 static void
2138 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2139 {
2140         i915_gem_object_free_mmap_offset(obj);
2141
2142         if (obj->base.filp == NULL)
2143                 return;
2144
2145         /* Our goal here is to return as much of the memory as
2146          * is possible back to the system as we are called from OOM.
2147          * To do this we must instruct the shmfs to drop all of its
2148          * backing pages, *now*.
2149          */
2150         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2151         obj->madv = __I915_MADV_PURGED;
2152 }
2153
2154 /* Try to discard unwanted pages */
2155 static void
2156 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2157 {
2158         struct address_space *mapping;
2159
2160         switch (obj->madv) {
2161         case I915_MADV_DONTNEED:
2162                 i915_gem_object_truncate(obj);
2163         case __I915_MADV_PURGED:
2164                 return;
2165         }
2166
2167         if (obj->base.filp == NULL)
2168                 return;
2169
2170         mapping = file_inode(obj->base.filp)->i_mapping,
2171         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2172 }
2173
2174 static void
2175 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2176 {
2177         struct sg_page_iter sg_iter;
2178         int ret;
2179
2180         BUG_ON(obj->madv == __I915_MADV_PURGED);
2181
2182         ret = i915_gem_object_set_to_cpu_domain(obj, true);
2183         if (ret) {
2184                 /* In the event of a disaster, abandon all caches and
2185                  * hope for the best.
2186                  */
2187                 WARN_ON(ret != -EIO);
2188                 i915_gem_clflush_object(obj, true);
2189                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2190         }
2191
2192         i915_gem_gtt_finish_object(obj);
2193
2194         if (i915_gem_object_needs_bit17_swizzle(obj))
2195                 i915_gem_object_save_bit_17_swizzle(obj);
2196
2197         if (obj->madv == I915_MADV_DONTNEED)
2198                 obj->dirty = 0;
2199
2200         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2201                 struct page *page = sg_page_iter_page(&sg_iter);
2202
2203                 if (obj->dirty)
2204                         set_page_dirty(page);
2205
2206                 if (obj->madv == I915_MADV_WILLNEED)
2207                         mark_page_accessed(page);
2208
2209                 put_page(page);
2210         }
2211         obj->dirty = 0;
2212
2213         sg_free_table(obj->pages);
2214         kfree(obj->pages);
2215 }
2216
2217 int
2218 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2219 {
2220         const struct drm_i915_gem_object_ops *ops = obj->ops;
2221
2222         if (obj->pages == NULL)
2223                 return 0;
2224
2225         if (obj->pages_pin_count)
2226                 return -EBUSY;
2227
2228         BUG_ON(i915_gem_obj_bound_any(obj));
2229
2230         /* ->put_pages might need to allocate memory for the bit17 swizzle
2231          * array, hence protect them from being reaped by removing them from gtt
2232          * lists early. */
2233         list_del(&obj->global_list);
2234
2235         if (obj->mapping) {
2236                 if (is_vmalloc_addr(obj->mapping))
2237                         vunmap(obj->mapping);
2238                 else
2239                         kunmap(kmap_to_page(obj->mapping));
2240                 obj->mapping = NULL;
2241         }
2242
2243         ops->put_pages(obj);
2244         obj->pages = NULL;
2245
2246         i915_gem_object_invalidate(obj);
2247
2248         return 0;
2249 }
2250
2251 static int
2252 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2253 {
2254         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2255         int page_count, i;
2256         struct address_space *mapping;
2257         struct sg_table *st;
2258         struct scatterlist *sg;
2259         struct sg_page_iter sg_iter;
2260         struct page *page;
2261         unsigned long last_pfn = 0;     /* suppress gcc warning */
2262         int ret;
2263         gfp_t gfp;
2264
2265         /* Assert that the object is not currently in any GPU domain. As it
2266          * wasn't in the GTT, there shouldn't be any way it could have been in
2267          * a GPU cache
2268          */
2269         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2270         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2271
2272         st = kmalloc(sizeof(*st), GFP_KERNEL);
2273         if (st == NULL)
2274                 return -ENOMEM;
2275
2276         page_count = obj->base.size / PAGE_SIZE;
2277         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2278                 kfree(st);
2279                 return -ENOMEM;
2280         }
2281
2282         /* Get the list of pages out of our struct file.  They'll be pinned
2283          * at this point until we release them.
2284          *
2285          * Fail silently without starting the shrinker
2286          */
2287         mapping = file_inode(obj->base.filp)->i_mapping;
2288         gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2289         gfp |= __GFP_NORETRY | __GFP_NOWARN;
2290         sg = st->sgl;
2291         st->nents = 0;
2292         for (i = 0; i < page_count; i++) {
2293                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2294                 if (IS_ERR(page)) {
2295                         i915_gem_shrink(dev_priv,
2296                                         page_count,
2297                                         I915_SHRINK_BOUND |
2298                                         I915_SHRINK_UNBOUND |
2299                                         I915_SHRINK_PURGEABLE);
2300                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2301                 }
2302                 if (IS_ERR(page)) {
2303                         /* We've tried hard to allocate the memory by reaping
2304                          * our own buffer, now let the real VM do its job and
2305                          * go down in flames if truly OOM.
2306                          */
2307                         i915_gem_shrink_all(dev_priv);
2308                         page = shmem_read_mapping_page(mapping, i);
2309                         if (IS_ERR(page)) {
2310                                 ret = PTR_ERR(page);
2311                                 goto err_pages;
2312                         }
2313                 }
2314 #ifdef CONFIG_SWIOTLB
2315                 if (swiotlb_nr_tbl()) {
2316                         st->nents++;
2317                         sg_set_page(sg, page, PAGE_SIZE, 0);
2318                         sg = sg_next(sg);
2319                         continue;
2320                 }
2321 #endif
2322                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2323                         if (i)
2324                                 sg = sg_next(sg);
2325                         st->nents++;
2326                         sg_set_page(sg, page, PAGE_SIZE, 0);
2327                 } else {
2328                         sg->length += PAGE_SIZE;
2329                 }
2330                 last_pfn = page_to_pfn(page);
2331
2332                 /* Check that the i965g/gm workaround works. */
2333                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2334         }
2335 #ifdef CONFIG_SWIOTLB
2336         if (!swiotlb_nr_tbl())
2337 #endif
2338                 sg_mark_end(sg);
2339         obj->pages = st;
2340
2341         ret = i915_gem_gtt_prepare_object(obj);
2342         if (ret)
2343                 goto err_pages;
2344
2345         if (i915_gem_object_needs_bit17_swizzle(obj))
2346                 i915_gem_object_do_bit_17_swizzle(obj);
2347
2348         if (obj->tiling_mode != I915_TILING_NONE &&
2349             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2350                 i915_gem_object_pin_pages(obj);
2351
2352         return 0;
2353
2354 err_pages:
2355         sg_mark_end(sg);
2356         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2357                 put_page(sg_page_iter_page(&sg_iter));
2358         sg_free_table(st);
2359         kfree(st);
2360
2361         /* shmemfs first checks if there is enough memory to allocate the page
2362          * and reports ENOSPC should there be insufficient, along with the usual
2363          * ENOMEM for a genuine allocation failure.
2364          *
2365          * We use ENOSPC in our driver to mean that we have run out of aperture
2366          * space and so want to translate the error from shmemfs back to our
2367          * usual understanding of ENOMEM.
2368          */
2369         if (ret == -ENOSPC)
2370                 ret = -ENOMEM;
2371
2372         return ret;
2373 }
2374
2375 /* Ensure that the associated pages are gathered from the backing storage
2376  * and pinned into our object. i915_gem_object_get_pages() may be called
2377  * multiple times before they are released by a single call to
2378  * i915_gem_object_put_pages() - once the pages are no longer referenced
2379  * either as a result of memory pressure (reaping pages under the shrinker)
2380  * or as the object is itself released.
2381  */
2382 int
2383 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2384 {
2385         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2386         const struct drm_i915_gem_object_ops *ops = obj->ops;
2387         int ret;
2388
2389         if (obj->pages)
2390                 return 0;
2391
2392         if (obj->madv != I915_MADV_WILLNEED) {
2393                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2394                 return -EFAULT;
2395         }
2396
2397         BUG_ON(obj->pages_pin_count);
2398
2399         ret = ops->get_pages(obj);
2400         if (ret)
2401                 return ret;
2402
2403         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2404
2405         obj->get_page.sg = obj->pages->sgl;
2406         obj->get_page.last = 0;
2407
2408         return 0;
2409 }
2410
2411 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj)
2412 {
2413         int ret;
2414
2415         lockdep_assert_held(&obj->base.dev->struct_mutex);
2416
2417         ret = i915_gem_object_get_pages(obj);
2418         if (ret)
2419                 return ERR_PTR(ret);
2420
2421         i915_gem_object_pin_pages(obj);
2422
2423         if (obj->mapping == NULL) {
2424                 struct page **pages;
2425
2426                 pages = NULL;
2427                 if (obj->base.size == PAGE_SIZE)
2428                         obj->mapping = kmap(sg_page(obj->pages->sgl));
2429                 else
2430                         pages = drm_malloc_gfp(obj->base.size >> PAGE_SHIFT,
2431                                                sizeof(*pages),
2432                                                GFP_TEMPORARY);
2433                 if (pages != NULL) {
2434                         struct sg_page_iter sg_iter;
2435                         int n;
2436
2437                         n = 0;
2438                         for_each_sg_page(obj->pages->sgl, &sg_iter,
2439                                          obj->pages->nents, 0)
2440                                 pages[n++] = sg_page_iter_page(&sg_iter);
2441
2442                         obj->mapping = vmap(pages, n, 0, PAGE_KERNEL);
2443                         drm_free_large(pages);
2444                 }
2445                 if (obj->mapping == NULL) {
2446                         i915_gem_object_unpin_pages(obj);
2447                         return ERR_PTR(-ENOMEM);
2448                 }
2449         }
2450
2451         return obj->mapping;
2452 }
2453
2454 void i915_vma_move_to_active(struct i915_vma *vma,
2455                              struct drm_i915_gem_request *req)
2456 {
2457         struct drm_i915_gem_object *obj = vma->obj;
2458         struct intel_engine_cs *engine;
2459
2460         engine = i915_gem_request_get_engine(req);
2461
2462         /* Add a reference if we're newly entering the active list. */
2463         if (obj->active == 0)
2464                 drm_gem_object_reference(&obj->base);
2465         obj->active |= intel_engine_flag(engine);
2466
2467         list_move_tail(&obj->engine_list[engine->id], &engine->active_list);
2468         i915_gem_request_assign(&obj->last_read_req[engine->id], req);
2469
2470         list_move_tail(&vma->vm_link, &vma->vm->active_list);
2471 }
2472
2473 static void
2474 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2475 {
2476         RQ_BUG_ON(obj->last_write_req == NULL);
2477         RQ_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine)));
2478
2479         i915_gem_request_assign(&obj->last_write_req, NULL);
2480         intel_fb_obj_flush(obj, true, ORIGIN_CS);
2481 }
2482
2483 static void
2484 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2485 {
2486         struct i915_vma *vma;
2487
2488         RQ_BUG_ON(obj->last_read_req[ring] == NULL);
2489         RQ_BUG_ON(!(obj->active & (1 << ring)));
2490
2491         list_del_init(&obj->engine_list[ring]);
2492         i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2493
2494         if (obj->last_write_req && obj->last_write_req->engine->id == ring)
2495                 i915_gem_object_retire__write(obj);
2496
2497         obj->active &= ~(1 << ring);
2498         if (obj->active)
2499                 return;
2500
2501         /* Bump our place on the bound list to keep it roughly in LRU order
2502          * so that we don't steal from recently used but inactive objects
2503          * (unless we are forced to ofc!)
2504          */
2505         list_move_tail(&obj->global_list,
2506                        &to_i915(obj->base.dev)->mm.bound_list);
2507
2508         list_for_each_entry(vma, &obj->vma_list, obj_link) {
2509                 if (!list_empty(&vma->vm_link))
2510                         list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
2511         }
2512
2513         i915_gem_request_assign(&obj->last_fenced_req, NULL);
2514         drm_gem_object_unreference(&obj->base);
2515 }
2516
2517 static int
2518 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2519 {
2520         struct drm_i915_private *dev_priv = dev->dev_private;
2521         struct intel_engine_cs *engine;
2522         int ret;
2523
2524         /* Carefully retire all requests without writing to the rings */
2525         for_each_engine(engine, dev_priv) {
2526                 ret = intel_engine_idle(engine);
2527                 if (ret)
2528                         return ret;
2529         }
2530         i915_gem_retire_requests(dev);
2531
2532         /* Finally reset hw state */
2533         for_each_engine(engine, dev_priv)
2534                 intel_ring_init_seqno(engine, seqno);
2535
2536         return 0;
2537 }
2538
2539 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2540 {
2541         struct drm_i915_private *dev_priv = dev->dev_private;
2542         int ret;
2543
2544         if (seqno == 0)
2545                 return -EINVAL;
2546
2547         /* HWS page needs to be set less than what we
2548          * will inject to ring
2549          */
2550         ret = i915_gem_init_seqno(dev, seqno - 1);
2551         if (ret)
2552                 return ret;
2553
2554         /* Carefully set the last_seqno value so that wrap
2555          * detection still works
2556          */
2557         dev_priv->next_seqno = seqno;
2558         dev_priv->last_seqno = seqno - 1;
2559         if (dev_priv->last_seqno == 0)
2560                 dev_priv->last_seqno--;
2561
2562         return 0;
2563 }
2564
2565 int
2566 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2567 {
2568         struct drm_i915_private *dev_priv = dev->dev_private;
2569
2570         /* reserve 0 for non-seqno */
2571         if (dev_priv->next_seqno == 0) {
2572                 int ret = i915_gem_init_seqno(dev, 0);
2573                 if (ret)
2574                         return ret;
2575
2576                 dev_priv->next_seqno = 1;
2577         }
2578
2579         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2580         return 0;
2581 }
2582
2583 /*
2584  * NB: This function is not allowed to fail. Doing so would mean the the
2585  * request is not being tracked for completion but the work itself is
2586  * going to happen on the hardware. This would be a Bad Thing(tm).
2587  */
2588 void __i915_add_request(struct drm_i915_gem_request *request,
2589                         struct drm_i915_gem_object *obj,
2590                         bool flush_caches)
2591 {
2592         struct intel_engine_cs *engine;
2593         struct drm_i915_private *dev_priv;
2594         struct intel_ringbuffer *ringbuf;
2595         u32 request_start;
2596         int ret;
2597
2598         if (WARN_ON(request == NULL))
2599                 return;
2600
2601         engine = request->engine;
2602         dev_priv = request->i915;
2603         ringbuf = request->ringbuf;
2604
2605         /*
2606          * To ensure that this call will not fail, space for its emissions
2607          * should already have been reserved in the ring buffer. Let the ring
2608          * know that it is time to use that space up.
2609          */
2610         intel_ring_reserved_space_use(ringbuf);
2611
2612         request_start = intel_ring_get_tail(ringbuf);
2613         /*
2614          * Emit any outstanding flushes - execbuf can fail to emit the flush
2615          * after having emitted the batchbuffer command. Hence we need to fix
2616          * things up similar to emitting the lazy request. The difference here
2617          * is that the flush _must_ happen before the next request, no matter
2618          * what.
2619          */
2620         if (flush_caches) {
2621                 if (i915.enable_execlists)
2622                         ret = logical_ring_flush_all_caches(request);
2623                 else
2624                         ret = intel_ring_flush_all_caches(request);
2625                 /* Not allowed to fail! */
2626                 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2627         }
2628
2629         trace_i915_gem_request_add(request);
2630
2631         request->head = request_start;
2632
2633         /* Whilst this request exists, batch_obj will be on the
2634          * active_list, and so will hold the active reference. Only when this
2635          * request is retired will the the batch_obj be moved onto the
2636          * inactive_list and lose its active reference. Hence we do not need
2637          * to explicitly hold another reference here.
2638          */
2639         request->batch_obj = obj;
2640
2641         /* Seal the request and mark it as pending execution. Note that
2642          * we may inspect this state, without holding any locks, during
2643          * hangcheck. Hence we apply the barrier to ensure that we do not
2644          * see a more recent value in the hws than we are tracking.
2645          */
2646         request->emitted_jiffies = jiffies;
2647         request->previous_seqno = engine->last_submitted_seqno;
2648         smp_store_mb(engine->last_submitted_seqno, request->seqno);
2649         list_add_tail(&request->list, &engine->request_list);
2650
2651         /* Record the position of the start of the request so that
2652          * should we detect the updated seqno part-way through the
2653          * GPU processing the request, we never over-estimate the
2654          * position of the head.
2655          */
2656         request->postfix = intel_ring_get_tail(ringbuf);
2657
2658         if (i915.enable_execlists)
2659                 ret = engine->emit_request(request);
2660         else {
2661                 ret = engine->add_request(request);
2662
2663                 request->tail = intel_ring_get_tail(ringbuf);
2664         }
2665         /* Not allowed to fail! */
2666         WARN(ret, "emit|add_request failed: %d!\n", ret);
2667
2668         i915_queue_hangcheck(engine->dev);
2669
2670         queue_delayed_work(dev_priv->wq,
2671                            &dev_priv->mm.retire_work,
2672                            round_jiffies_up_relative(HZ));
2673         intel_mark_busy(dev_priv->dev);
2674
2675         /* Sanity check that the reserved size was large enough. */
2676         intel_ring_reserved_space_end(ringbuf);
2677 }
2678
2679 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2680                                    const struct intel_context *ctx)
2681 {
2682         unsigned long elapsed;
2683
2684         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2685
2686         if (ctx->hang_stats.banned)
2687                 return true;
2688
2689         if (ctx->hang_stats.ban_period_seconds &&
2690             elapsed <= ctx->hang_stats.ban_period_seconds) {
2691                 if (!i915_gem_context_is_default(ctx)) {
2692                         DRM_DEBUG("context hanging too fast, banning!\n");
2693                         return true;
2694                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2695                         if (i915_stop_ring_allow_warn(dev_priv))
2696                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2697                         return true;
2698                 }
2699         }
2700
2701         return false;
2702 }
2703
2704 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2705                                   struct intel_context *ctx,
2706                                   const bool guilty)
2707 {
2708         struct i915_ctx_hang_stats *hs;
2709
2710         if (WARN_ON(!ctx))
2711                 return;
2712
2713         hs = &ctx->hang_stats;
2714
2715         if (guilty) {
2716                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2717                 hs->batch_active++;
2718                 hs->guilty_ts = get_seconds();
2719         } else {
2720                 hs->batch_pending++;
2721         }
2722 }
2723
2724 void i915_gem_request_free(struct kref *req_ref)
2725 {
2726         struct drm_i915_gem_request *req = container_of(req_ref,
2727                                                  typeof(*req), ref);
2728         struct intel_context *ctx = req->ctx;
2729
2730         if (req->file_priv)
2731                 i915_gem_request_remove_from_client(req);
2732
2733         if (ctx) {
2734                 if (i915.enable_execlists && ctx != req->i915->kernel_context)
2735                         intel_lr_context_unpin(ctx, req->engine);
2736
2737                 i915_gem_context_unreference(ctx);
2738         }
2739
2740         kmem_cache_free(req->i915->requests, req);
2741 }
2742
2743 static inline int
2744 __i915_gem_request_alloc(struct intel_engine_cs *engine,
2745                          struct intel_context *ctx,
2746                          struct drm_i915_gem_request **req_out)
2747 {
2748         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2749         struct drm_i915_gem_request *req;
2750         int ret;
2751
2752         if (!req_out)
2753                 return -EINVAL;
2754
2755         *req_out = NULL;
2756
2757         req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2758         if (req == NULL)
2759                 return -ENOMEM;
2760
2761         ret = i915_gem_get_seqno(engine->dev, &req->seqno);
2762         if (ret)
2763                 goto err;
2764
2765         kref_init(&req->ref);
2766         req->i915 = dev_priv;
2767         req->engine = engine;
2768         req->ctx  = ctx;
2769         i915_gem_context_reference(req->ctx);
2770
2771         if (i915.enable_execlists)
2772                 ret = intel_logical_ring_alloc_request_extras(req);
2773         else
2774                 ret = intel_ring_alloc_request_extras(req);
2775         if (ret) {
2776                 i915_gem_context_unreference(req->ctx);
2777                 goto err;
2778         }
2779
2780         /*
2781          * Reserve space in the ring buffer for all the commands required to
2782          * eventually emit this request. This is to guarantee that the
2783          * i915_add_request() call can't fail. Note that the reserve may need
2784          * to be redone if the request is not actually submitted straight
2785          * away, e.g. because a GPU scheduler has deferred it.
2786          */
2787         if (i915.enable_execlists)
2788                 ret = intel_logical_ring_reserve_space(req);
2789         else
2790                 ret = intel_ring_reserve_space(req);
2791         if (ret) {
2792                 /*
2793                  * At this point, the request is fully allocated even if not
2794                  * fully prepared. Thus it can be cleaned up using the proper
2795                  * free code.
2796                  */
2797                 i915_gem_request_cancel(req);
2798                 return ret;
2799         }
2800
2801         *req_out = req;
2802         return 0;
2803
2804 err:
2805         kmem_cache_free(dev_priv->requests, req);
2806         return ret;
2807 }
2808
2809 /**
2810  * i915_gem_request_alloc - allocate a request structure
2811  *
2812  * @engine: engine that we wish to issue the request on.
2813  * @ctx: context that the request will be associated with.
2814  *       This can be NULL if the request is not directly related to
2815  *       any specific user context, in which case this function will
2816  *       choose an appropriate context to use.
2817  *
2818  * Returns a pointer to the allocated request if successful,
2819  * or an error code if not.
2820  */
2821 struct drm_i915_gem_request *
2822 i915_gem_request_alloc(struct intel_engine_cs *engine,
2823                        struct intel_context *ctx)
2824 {
2825         struct drm_i915_gem_request *req;
2826         int err;
2827
2828         if (ctx == NULL)
2829                 ctx = to_i915(engine->dev)->kernel_context;
2830         err = __i915_gem_request_alloc(engine, ctx, &req);
2831         return err ? ERR_PTR(err) : req;
2832 }
2833
2834 void i915_gem_request_cancel(struct drm_i915_gem_request *req)
2835 {
2836         intel_ring_reserved_space_cancel(req->ringbuf);
2837
2838         i915_gem_request_unreference(req);
2839 }
2840
2841 struct drm_i915_gem_request *
2842 i915_gem_find_active_request(struct intel_engine_cs *engine)
2843 {
2844         struct drm_i915_gem_request *request;
2845
2846         list_for_each_entry(request, &engine->request_list, list) {
2847                 if (i915_gem_request_completed(request, false))
2848                         continue;
2849
2850                 return request;
2851         }
2852
2853         return NULL;
2854 }
2855
2856 static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv,
2857                                        struct intel_engine_cs *engine)
2858 {
2859         struct drm_i915_gem_request *request;
2860         bool ring_hung;
2861
2862         request = i915_gem_find_active_request(engine);
2863
2864         if (request == NULL)
2865                 return;
2866
2867         ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2868
2869         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2870
2871         list_for_each_entry_continue(request, &engine->request_list, list)
2872                 i915_set_reset_status(dev_priv, request->ctx, false);
2873 }
2874
2875 static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv,
2876                                         struct intel_engine_cs *engine)
2877 {
2878         struct intel_ringbuffer *buffer;
2879
2880         while (!list_empty(&engine->active_list)) {
2881                 struct drm_i915_gem_object *obj;
2882
2883                 obj = list_first_entry(&engine->active_list,
2884                                        struct drm_i915_gem_object,
2885                                        engine_list[engine->id]);
2886
2887                 i915_gem_object_retire__read(obj, engine->id);
2888         }
2889
2890         /*
2891          * Clear the execlists queue up before freeing the requests, as those
2892          * are the ones that keep the context and ringbuffer backing objects
2893          * pinned in place.
2894          */
2895
2896         if (i915.enable_execlists) {
2897                 /* Ensure irq handler finishes or is cancelled. */
2898                 tasklet_kill(&engine->irq_tasklet);
2899
2900                 spin_lock_bh(&engine->execlist_lock);
2901                 /* list_splice_tail_init checks for empty lists */
2902                 list_splice_tail_init(&engine->execlist_queue,
2903                                       &engine->execlist_retired_req_list);
2904                 spin_unlock_bh(&engine->execlist_lock);
2905
2906                 intel_execlists_retire_requests(engine);
2907         }
2908
2909         /*
2910          * We must free the requests after all the corresponding objects have
2911          * been moved off active lists. Which is the same order as the normal
2912          * retire_requests function does. This is important if object hold
2913          * implicit references on things like e.g. ppgtt address spaces through
2914          * the request.
2915          */
2916         while (!list_empty(&engine->request_list)) {
2917                 struct drm_i915_gem_request *request;
2918
2919                 request = list_first_entry(&engine->request_list,
2920                                            struct drm_i915_gem_request,
2921                                            list);
2922
2923                 i915_gem_request_retire(request);
2924         }
2925
2926         /* Having flushed all requests from all queues, we know that all
2927          * ringbuffers must now be empty. However, since we do not reclaim
2928          * all space when retiring the request (to prevent HEADs colliding
2929          * with rapid ringbuffer wraparound) the amount of available space
2930          * upon reset is less than when we start. Do one more pass over
2931          * all the ringbuffers to reset last_retired_head.
2932          */
2933         list_for_each_entry(buffer, &engine->buffers, link) {
2934                 buffer->last_retired_head = buffer->tail;
2935                 intel_ring_update_space(buffer);
2936         }
2937
2938         intel_ring_init_seqno(engine, engine->last_submitted_seqno);
2939 }
2940
2941 void i915_gem_reset(struct drm_device *dev)
2942 {
2943         struct drm_i915_private *dev_priv = dev->dev_private;
2944         struct intel_engine_cs *engine;
2945
2946         /*
2947          * Before we free the objects from the requests, we need to inspect
2948          * them for finding the guilty party. As the requests only borrow
2949          * their reference to the objects, the inspection must be done first.
2950          */
2951         for_each_engine(engine, dev_priv)
2952                 i915_gem_reset_engine_status(dev_priv, engine);
2953
2954         for_each_engine(engine, dev_priv)
2955                 i915_gem_reset_engine_cleanup(dev_priv, engine);
2956
2957         i915_gem_context_reset(dev);
2958
2959         i915_gem_restore_fences(dev);
2960
2961         WARN_ON(i915_verify_lists(dev));
2962 }
2963
2964 /**
2965  * This function clears the request list as sequence numbers are passed.
2966  */
2967 void
2968 i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
2969 {
2970         WARN_ON(i915_verify_lists(engine->dev));
2971
2972         /* Retire requests first as we use it above for the early return.
2973          * If we retire requests last, we may use a later seqno and so clear
2974          * the requests lists without clearing the active list, leading to
2975          * confusion.
2976          */
2977         while (!list_empty(&engine->request_list)) {
2978                 struct drm_i915_gem_request *request;
2979
2980                 request = list_first_entry(&engine->request_list,
2981                                            struct drm_i915_gem_request,
2982                                            list);
2983
2984                 if (!i915_gem_request_completed(request, true))
2985                         break;
2986
2987                 i915_gem_request_retire(request);
2988         }
2989
2990         /* Move any buffers on the active list that are no longer referenced
2991          * by the ringbuffer to the flushing/inactive lists as appropriate,
2992          * before we free the context associated with the requests.
2993          */
2994         while (!list_empty(&engine->active_list)) {
2995                 struct drm_i915_gem_object *obj;
2996
2997                 obj = list_first_entry(&engine->active_list,
2998                                        struct drm_i915_gem_object,
2999                                        engine_list[engine->id]);
3000
3001                 if (!list_empty(&obj->last_read_req[engine->id]->list))
3002                         break;
3003
3004                 i915_gem_object_retire__read(obj, engine->id);
3005         }
3006
3007         if (unlikely(engine->trace_irq_req &&
3008                      i915_gem_request_completed(engine->trace_irq_req, true))) {
3009                 engine->irq_put(engine);
3010                 i915_gem_request_assign(&engine->trace_irq_req, NULL);
3011         }
3012
3013         WARN_ON(i915_verify_lists(engine->dev));
3014 }
3015
3016 bool
3017 i915_gem_retire_requests(struct drm_device *dev)
3018 {
3019         struct drm_i915_private *dev_priv = dev->dev_private;
3020         struct intel_engine_cs *engine;
3021         bool idle = true;
3022
3023         for_each_engine(engine, dev_priv) {
3024                 i915_gem_retire_requests_ring(engine);
3025                 idle &= list_empty(&engine->request_list);
3026                 if (i915.enable_execlists) {
3027                         spin_lock_bh(&engine->execlist_lock);
3028                         idle &= list_empty(&engine->execlist_queue);
3029                         spin_unlock_bh(&engine->execlist_lock);
3030
3031                         intel_execlists_retire_requests(engine);
3032                 }
3033         }
3034
3035         if (idle)
3036                 mod_delayed_work(dev_priv->wq,
3037                                    &dev_priv->mm.idle_work,
3038                                    msecs_to_jiffies(100));
3039
3040         return idle;
3041 }
3042
3043 static void
3044 i915_gem_retire_work_handler(struct work_struct *work)
3045 {
3046         struct drm_i915_private *dev_priv =
3047                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
3048         struct drm_device *dev = dev_priv->dev;
3049         bool idle;
3050
3051         /* Come back later if the device is busy... */
3052         idle = false;
3053         if (mutex_trylock(&dev->struct_mutex)) {
3054                 idle = i915_gem_retire_requests(dev);
3055                 mutex_unlock(&dev->struct_mutex);
3056         }
3057         if (!idle)
3058                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
3059                                    round_jiffies_up_relative(HZ));
3060 }
3061
3062 static void
3063 i915_gem_idle_work_handler(struct work_struct *work)
3064 {
3065         struct drm_i915_private *dev_priv =
3066                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
3067         struct drm_device *dev = dev_priv->dev;
3068         struct intel_engine_cs *engine;
3069
3070         for_each_engine(engine, dev_priv)
3071                 if (!list_empty(&engine->request_list))
3072                         return;
3073
3074         /* we probably should sync with hangcheck here, using cancel_work_sync.
3075          * Also locking seems to be fubar here, engine->request_list is protected
3076          * by dev->struct_mutex. */
3077
3078         intel_mark_idle(dev);
3079
3080         if (mutex_trylock(&dev->struct_mutex)) {
3081                 for_each_engine(engine, dev_priv)
3082                         i915_gem_batch_pool_fini(&engine->batch_pool);
3083
3084                 mutex_unlock(&dev->struct_mutex);
3085         }
3086 }
3087
3088 /**
3089  * Ensures that an object will eventually get non-busy by flushing any required
3090  * write domains, emitting any outstanding lazy request and retiring and
3091  * completed requests.
3092  */
3093 static int
3094 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
3095 {
3096         int i;
3097
3098         if (!obj->active)
3099                 return 0;
3100
3101         for (i = 0; i < I915_NUM_ENGINES; i++) {
3102                 struct drm_i915_gem_request *req;
3103
3104                 req = obj->last_read_req[i];
3105                 if (req == NULL)
3106                         continue;
3107
3108                 if (list_empty(&req->list))
3109                         goto retire;
3110
3111                 if (i915_gem_request_completed(req, true)) {
3112                         __i915_gem_request_retire__upto(req);
3113 retire:
3114                         i915_gem_object_retire__read(obj, i);
3115                 }
3116         }
3117
3118         return 0;
3119 }
3120
3121 /**
3122  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3123  * @DRM_IOCTL_ARGS: standard ioctl arguments
3124  *
3125  * Returns 0 if successful, else an error is returned with the remaining time in
3126  * the timeout parameter.
3127  *  -ETIME: object is still busy after timeout
3128  *  -ERESTARTSYS: signal interrupted the wait
3129  *  -ENONENT: object doesn't exist
3130  * Also possible, but rare:
3131  *  -EAGAIN: GPU wedged
3132  *  -ENOMEM: damn
3133  *  -ENODEV: Internal IRQ fail
3134  *  -E?: The add request failed
3135  *
3136  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3137  * non-zero timeout parameter the wait ioctl will wait for the given number of
3138  * nanoseconds on an object becoming unbusy. Since the wait itself does so
3139  * without holding struct_mutex the object may become re-busied before this
3140  * function completes. A similar but shorter * race condition exists in the busy
3141  * ioctl
3142  */
3143 int
3144 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3145 {
3146         struct drm_i915_private *dev_priv = dev->dev_private;
3147         struct drm_i915_gem_wait *args = data;
3148         struct drm_i915_gem_object *obj;
3149         struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3150         unsigned reset_counter;
3151         int i, n = 0;
3152         int ret;
3153
3154         if (args->flags != 0)
3155                 return -EINVAL;
3156
3157         ret = i915_mutex_lock_interruptible(dev);
3158         if (ret)
3159                 return ret;
3160
3161         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3162         if (&obj->base == NULL) {
3163                 mutex_unlock(&dev->struct_mutex);
3164                 return -ENOENT;
3165         }
3166
3167         /* Need to make sure the object gets inactive eventually. */
3168         ret = i915_gem_object_flush_active(obj);
3169         if (ret)
3170                 goto out;
3171
3172         if (!obj->active)
3173                 goto out;
3174
3175         /* Do this after OLR check to make sure we make forward progress polling
3176          * on this IOCTL with a timeout == 0 (like busy ioctl)
3177          */
3178         if (args->timeout_ns == 0) {
3179                 ret = -ETIME;
3180                 goto out;
3181         }
3182
3183         drm_gem_object_unreference(&obj->base);
3184         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3185
3186         for (i = 0; i < I915_NUM_ENGINES; i++) {
3187                 if (obj->last_read_req[i] == NULL)
3188                         continue;
3189
3190                 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3191         }
3192
3193         mutex_unlock(&dev->struct_mutex);
3194
3195         for (i = 0; i < n; i++) {
3196                 if (ret == 0)
3197                         ret = __i915_wait_request(req[i], reset_counter, true,
3198                                                   args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3199                                                   to_rps_client(file));
3200                 i915_gem_request_unreference__unlocked(req[i]);
3201         }
3202         return ret;
3203
3204 out:
3205         drm_gem_object_unreference(&obj->base);
3206         mutex_unlock(&dev->struct_mutex);
3207         return ret;
3208 }
3209
3210 static int
3211 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3212                        struct intel_engine_cs *to,
3213                        struct drm_i915_gem_request *from_req,
3214                        struct drm_i915_gem_request **to_req)
3215 {
3216         struct intel_engine_cs *from;
3217         int ret;
3218
3219         from = i915_gem_request_get_engine(from_req);
3220         if (to == from)
3221                 return 0;
3222
3223         if (i915_gem_request_completed(from_req, true))
3224                 return 0;
3225
3226         if (!i915_semaphore_is_enabled(obj->base.dev)) {
3227                 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3228                 ret = __i915_wait_request(from_req,
3229                                           atomic_read(&i915->gpu_error.reset_counter),
3230                                           i915->mm.interruptible,
3231                                           NULL,
3232                                           &i915->rps.semaphores);
3233                 if (ret)
3234                         return ret;
3235
3236                 i915_gem_object_retire_request(obj, from_req);
3237         } else {
3238                 int idx = intel_ring_sync_index(from, to);
3239                 u32 seqno = i915_gem_request_get_seqno(from_req);
3240
3241                 WARN_ON(!to_req);
3242
3243                 if (seqno <= from->semaphore.sync_seqno[idx])
3244                         return 0;
3245
3246                 if (*to_req == NULL) {
3247                         struct drm_i915_gem_request *req;
3248
3249                         req = i915_gem_request_alloc(to, NULL);
3250                         if (IS_ERR(req))
3251                                 return PTR_ERR(req);
3252
3253                         *to_req = req;
3254                 }
3255
3256                 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3257                 ret = to->semaphore.sync_to(*to_req, from, seqno);
3258                 if (ret)
3259                         return ret;
3260
3261                 /* We use last_read_req because sync_to()
3262                  * might have just caused seqno wrap under
3263                  * the radar.
3264                  */
3265                 from->semaphore.sync_seqno[idx] =
3266                         i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3267         }
3268
3269         return 0;
3270 }
3271
3272 /**
3273  * i915_gem_object_sync - sync an object to a ring.
3274  *
3275  * @obj: object which may be in use on another ring.
3276  * @to: ring we wish to use the object on. May be NULL.
3277  * @to_req: request we wish to use the object for. See below.
3278  *          This will be allocated and returned if a request is
3279  *          required but not passed in.
3280  *
3281  * This code is meant to abstract object synchronization with the GPU.
3282  * Calling with NULL implies synchronizing the object with the CPU
3283  * rather than a particular GPU ring. Conceptually we serialise writes
3284  * between engines inside the GPU. We only allow one engine to write
3285  * into a buffer at any time, but multiple readers. To ensure each has
3286  * a coherent view of memory, we must:
3287  *
3288  * - If there is an outstanding write request to the object, the new
3289  *   request must wait for it to complete (either CPU or in hw, requests
3290  *   on the same ring will be naturally ordered).
3291  *
3292  * - If we are a write request (pending_write_domain is set), the new
3293  *   request must wait for outstanding read requests to complete.
3294  *
3295  * For CPU synchronisation (NULL to) no request is required. For syncing with
3296  * rings to_req must be non-NULL. However, a request does not have to be
3297  * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3298  * request will be allocated automatically and returned through *to_req. Note
3299  * that it is not guaranteed that commands will be emitted (because the system
3300  * might already be idle). Hence there is no need to create a request that
3301  * might never have any work submitted. Note further that if a request is
3302  * returned in *to_req, it is the responsibility of the caller to submit
3303  * that request (after potentially adding more work to it).
3304  *
3305  * Returns 0 if successful, else propagates up the lower layer error.
3306  */
3307 int
3308 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3309                      struct intel_engine_cs *to,
3310                      struct drm_i915_gem_request **to_req)
3311 {
3312         const bool readonly = obj->base.pending_write_domain == 0;
3313         struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3314         int ret, i, n;
3315
3316         if (!obj->active)
3317                 return 0;
3318
3319         if (to == NULL)
3320                 return i915_gem_object_wait_rendering(obj, readonly);
3321
3322         n = 0;
3323         if (readonly) {
3324                 if (obj->last_write_req)
3325                         req[n++] = obj->last_write_req;
3326         } else {
3327                 for (i = 0; i < I915_NUM_ENGINES; i++)
3328                         if (obj->last_read_req[i])
3329                                 req[n++] = obj->last_read_req[i];
3330         }
3331         for (i = 0; i < n; i++) {
3332                 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3333                 if (ret)
3334                         return ret;
3335         }
3336
3337         return 0;
3338 }
3339
3340 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3341 {
3342         u32 old_write_domain, old_read_domains;
3343
3344         /* Force a pagefault for domain tracking on next user access */
3345         i915_gem_release_mmap(obj);
3346
3347         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3348                 return;
3349
3350         /* Wait for any direct GTT access to complete */
3351         mb();
3352
3353         old_read_domains = obj->base.read_domains;
3354         old_write_domain = obj->base.write_domain;
3355
3356         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3357         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3358
3359         trace_i915_gem_object_change_domain(obj,
3360                                             old_read_domains,
3361                                             old_write_domain);
3362 }
3363
3364 static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
3365 {
3366         struct drm_i915_gem_object *obj = vma->obj;
3367         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3368         int ret;
3369
3370         if (list_empty(&vma->obj_link))
3371                 return 0;
3372
3373         if (!drm_mm_node_allocated(&vma->node)) {
3374                 i915_gem_vma_destroy(vma);
3375                 return 0;
3376         }
3377
3378         if (vma->pin_count)
3379                 return -EBUSY;
3380
3381         BUG_ON(obj->pages == NULL);
3382
3383         if (wait) {
3384                 ret = i915_gem_object_wait_rendering(obj, false);
3385                 if (ret)
3386                         return ret;
3387         }
3388
3389         if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3390                 i915_gem_object_finish_gtt(obj);
3391
3392                 /* release the fence reg _after_ flushing */
3393                 ret = i915_gem_object_put_fence(obj);
3394                 if (ret)
3395                         return ret;
3396         }
3397
3398         trace_i915_vma_unbind(vma);
3399
3400         vma->vm->unbind_vma(vma);
3401         vma->bound = 0;
3402
3403         list_del_init(&vma->vm_link);
3404         if (vma->is_ggtt) {
3405                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3406                         obj->map_and_fenceable = false;
3407                 } else if (vma->ggtt_view.pages) {
3408                         sg_free_table(vma->ggtt_view.pages);
3409                         kfree(vma->ggtt_view.pages);
3410                 }
3411                 vma->ggtt_view.pages = NULL;
3412         }
3413
3414         drm_mm_remove_node(&vma->node);
3415         i915_gem_vma_destroy(vma);
3416
3417         /* Since the unbound list is global, only move to that list if
3418          * no more VMAs exist. */
3419         if (list_empty(&obj->vma_list))
3420                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3421
3422         /* And finally now the object is completely decoupled from this vma,
3423          * we can drop its hold on the backing storage and allow it to be
3424          * reaped by the shrinker.
3425          */
3426         i915_gem_object_unpin_pages(obj);
3427
3428         return 0;
3429 }
3430
3431 int i915_vma_unbind(struct i915_vma *vma)
3432 {
3433         return __i915_vma_unbind(vma, true);
3434 }
3435
3436 int __i915_vma_unbind_no_wait(struct i915_vma *vma)
3437 {
3438         return __i915_vma_unbind(vma, false);
3439 }
3440
3441 int i915_gpu_idle(struct drm_device *dev)
3442 {
3443         struct drm_i915_private *dev_priv = dev->dev_private;
3444         struct intel_engine_cs *engine;
3445         int ret;
3446
3447         /* Flush everything onto the inactive list. */
3448         for_each_engine(engine, dev_priv) {
3449                 if (!i915.enable_execlists) {
3450                         struct drm_i915_gem_request *req;
3451
3452                         req = i915_gem_request_alloc(engine, NULL);
3453                         if (IS_ERR(req))
3454                                 return PTR_ERR(req);
3455
3456                         ret = i915_switch_context(req);
3457                         if (ret) {
3458                                 i915_gem_request_cancel(req);
3459                                 return ret;
3460                         }
3461
3462                         i915_add_request_no_flush(req);
3463                 }
3464
3465                 ret = intel_engine_idle(engine);
3466                 if (ret)
3467                         return ret;
3468         }
3469
3470         WARN_ON(i915_verify_lists(dev));
3471         return 0;
3472 }
3473
3474 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3475                                      unsigned long cache_level)
3476 {
3477         struct drm_mm_node *gtt_space = &vma->node;
3478         struct drm_mm_node *other;
3479
3480         /*
3481          * On some machines we have to be careful when putting differing types
3482          * of snoopable memory together to avoid the prefetcher crossing memory
3483          * domains and dying. During vm initialisation, we decide whether or not
3484          * these constraints apply and set the drm_mm.color_adjust
3485          * appropriately.
3486          */
3487         if (vma->vm->mm.color_adjust == NULL)
3488                 return true;
3489
3490         if (!drm_mm_node_allocated(gtt_space))
3491                 return true;
3492
3493         if (list_empty(&gtt_space->node_list))
3494                 return true;
3495
3496         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3497         if (other->allocated && !other->hole_follows && other->color != cache_level)
3498                 return false;
3499
3500         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3501         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3502                 return false;
3503
3504         return true;
3505 }
3506
3507 /**
3508  * Finds free space in the GTT aperture and binds the object or a view of it
3509  * there.
3510  */
3511 static struct i915_vma *
3512 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3513                            struct i915_address_space *vm,
3514                            const struct i915_ggtt_view *ggtt_view,
3515                            unsigned alignment,
3516                            uint64_t flags)
3517 {
3518         struct drm_device *dev = obj->base.dev;
3519         struct drm_i915_private *dev_priv = to_i915(dev);
3520         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3521         u32 fence_alignment, unfenced_alignment;
3522         u32 search_flag, alloc_flag;
3523         u64 start, end;
3524         u64 size, fence_size;
3525         struct i915_vma *vma;
3526         int ret;
3527
3528         if (i915_is_ggtt(vm)) {
3529                 u32 view_size;
3530
3531                 if (WARN_ON(!ggtt_view))
3532                         return ERR_PTR(-EINVAL);
3533
3534                 view_size = i915_ggtt_view_size(obj, ggtt_view);
3535
3536                 fence_size = i915_gem_get_gtt_size(dev,
3537                                                    view_size,
3538                                                    obj->tiling_mode);
3539                 fence_alignment = i915_gem_get_gtt_alignment(dev,
3540                                                              view_size,
3541                                                              obj->tiling_mode,
3542                                                              true);
3543                 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3544                                                                 view_size,
3545                                                                 obj->tiling_mode,
3546                                                                 false);
3547                 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3548         } else {
3549                 fence_size = i915_gem_get_gtt_size(dev,
3550                                                    obj->base.size,
3551                                                    obj->tiling_mode);
3552                 fence_alignment = i915_gem_get_gtt_alignment(dev,
3553                                                              obj->base.size,
3554                                                              obj->tiling_mode,
3555                                                              true);
3556                 unfenced_alignment =
3557                         i915_gem_get_gtt_alignment(dev,
3558                                                    obj->base.size,
3559                                                    obj->tiling_mode,
3560                                                    false);
3561                 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3562         }
3563
3564         start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3565         end = vm->total;
3566         if (flags & PIN_MAPPABLE)
3567                 end = min_t(u64, end, ggtt->mappable_end);
3568         if (flags & PIN_ZONE_4G)
3569                 end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE);
3570
3571         if (alignment == 0)
3572                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3573                                                 unfenced_alignment;
3574         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3575                 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3576                           ggtt_view ? ggtt_view->type : 0,
3577                           alignment);
3578                 return ERR_PTR(-EINVAL);
3579         }
3580
3581         /* If binding the object/GGTT view requires more space than the entire
3582          * aperture has, reject it early before evicting everything in a vain
3583          * attempt to find space.
3584          */
3585         if (size > end) {
3586                 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3587                           ggtt_view ? ggtt_view->type : 0,
3588                           size,
3589                           flags & PIN_MAPPABLE ? "mappable" : "total",
3590                           end);
3591                 return ERR_PTR(-E2BIG);
3592         }
3593
3594         ret = i915_gem_object_get_pages(obj);
3595         if (ret)
3596                 return ERR_PTR(ret);
3597
3598         i915_gem_object_pin_pages(obj);
3599
3600         vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3601                           i915_gem_obj_lookup_or_create_vma(obj, vm);
3602
3603         if (IS_ERR(vma))
3604                 goto err_unpin;
3605
3606         if (flags & PIN_OFFSET_FIXED) {
3607                 uint64_t offset = flags & PIN_OFFSET_MASK;
3608
3609                 if (offset & (alignment - 1) || offset + size > end) {
3610                         ret = -EINVAL;
3611                         goto err_free_vma;
3612                 }
3613                 vma->node.start = offset;
3614                 vma->node.size = size;
3615                 vma->node.color = obj->cache_level;
3616                 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3617                 if (ret) {
3618                         ret = i915_gem_evict_for_vma(vma);
3619                         if (ret == 0)
3620                                 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3621                 }
3622                 if (ret)
3623                         goto err_free_vma;
3624         } else {
3625                 if (flags & PIN_HIGH) {
3626                         search_flag = DRM_MM_SEARCH_BELOW;
3627                         alloc_flag = DRM_MM_CREATE_TOP;
3628                 } else {
3629                         search_flag = DRM_MM_SEARCH_DEFAULT;
3630                         alloc_flag = DRM_MM_CREATE_DEFAULT;
3631                 }
3632
3633 search_free:
3634                 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3635                                                           size, alignment,
3636                                                           obj->cache_level,
3637                                                           start, end,
3638                                                           search_flag,
3639                                                           alloc_flag);
3640                 if (ret) {
3641                         ret = i915_gem_evict_something(dev, vm, size, alignment,
3642                                                        obj->cache_level,
3643                                                        start, end,
3644                                                        flags);
3645                         if (ret == 0)
3646                                 goto search_free;
3647
3648                         goto err_free_vma;
3649                 }
3650         }
3651         if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3652                 ret = -EINVAL;
3653                 goto err_remove_node;
3654         }
3655
3656         trace_i915_vma_bind(vma, flags);
3657         ret = i915_vma_bind(vma, obj->cache_level, flags);
3658         if (ret)
3659                 goto err_remove_node;
3660
3661         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3662         list_add_tail(&vma->vm_link, &vm->inactive_list);
3663
3664         return vma;
3665
3666 err_remove_node:
3667         drm_mm_remove_node(&vma->node);
3668 err_free_vma:
3669         i915_gem_vma_destroy(vma);
3670         vma = ERR_PTR(ret);
3671 err_unpin:
3672         i915_gem_object_unpin_pages(obj);
3673         return vma;
3674 }
3675
3676 bool
3677 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3678                         bool force)
3679 {
3680         /* If we don't have a page list set up, then we're not pinned
3681          * to GPU, and we can ignore the cache flush because it'll happen
3682          * again at bind time.
3683          */
3684         if (obj->pages == NULL)
3685                 return false;
3686
3687         /*
3688          * Stolen memory is always coherent with the GPU as it is explicitly
3689          * marked as wc by the system, or the system is cache-coherent.
3690          */
3691         if (obj->stolen || obj->phys_handle)
3692                 return false;
3693
3694         /* If the GPU is snooping the contents of the CPU cache,
3695          * we do not need to manually clear the CPU cache lines.  However,
3696          * the caches are only snooped when the render cache is
3697          * flushed/invalidated.  As we always have to emit invalidations
3698          * and flushes when moving into and out of the RENDER domain, correct
3699          * snooping behaviour occurs naturally as the result of our domain
3700          * tracking.
3701          */
3702         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3703                 obj->cache_dirty = true;
3704                 return false;
3705         }
3706
3707         trace_i915_gem_object_clflush(obj);
3708         drm_clflush_sg(obj->pages);
3709         obj->cache_dirty = false;
3710
3711         return true;
3712 }
3713
3714 /** Flushes the GTT write domain for the object if it's dirty. */
3715 static void
3716 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3717 {
3718         uint32_t old_write_domain;
3719
3720         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3721                 return;
3722
3723         /* No actual flushing is required for the GTT write domain.  Writes
3724          * to it immediately go to main memory as far as we know, so there's
3725          * no chipset flush.  It also doesn't land in render cache.
3726          *
3727          * However, we do have to enforce the order so that all writes through
3728          * the GTT land before any writes to the device, such as updates to
3729          * the GATT itself.
3730          */
3731         wmb();
3732
3733         old_write_domain = obj->base.write_domain;
3734         obj->base.write_domain = 0;
3735
3736         intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3737
3738         trace_i915_gem_object_change_domain(obj,
3739                                             obj->base.read_domains,
3740                                             old_write_domain);
3741 }
3742
3743 /** Flushes the CPU write domain for the object if it's dirty. */
3744 static void
3745 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3746 {
3747         uint32_t old_write_domain;
3748
3749         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3750                 return;
3751
3752         if (i915_gem_clflush_object(obj, obj->pin_display))
3753                 i915_gem_chipset_flush(obj->base.dev);
3754
3755         old_write_domain = obj->base.write_domain;
3756         obj->base.write_domain = 0;
3757
3758         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3759
3760         trace_i915_gem_object_change_domain(obj,
3761                                             obj->base.read_domains,
3762                                             old_write_domain);
3763 }
3764
3765 /**
3766  * Moves a single object to the GTT read, and possibly write domain.
3767  *
3768  * This function returns when the move is complete, including waiting on
3769  * flushes to occur.
3770  */
3771 int
3772 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3773 {
3774         struct drm_device *dev = obj->base.dev;
3775         struct drm_i915_private *dev_priv = to_i915(dev);
3776         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3777         uint32_t old_write_domain, old_read_domains;
3778         struct i915_vma *vma;
3779         int ret;
3780
3781         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3782                 return 0;
3783
3784         ret = i915_gem_object_wait_rendering(obj, !write);
3785         if (ret)
3786                 return ret;
3787
3788         /* Flush and acquire obj->pages so that we are coherent through
3789          * direct access in memory with previous cached writes through
3790          * shmemfs and that our cache domain tracking remains valid.
3791          * For example, if the obj->filp was moved to swap without us
3792          * being notified and releasing the pages, we would mistakenly
3793          * continue to assume that the obj remained out of the CPU cached
3794          * domain.
3795          */
3796         ret = i915_gem_object_get_pages(obj);
3797         if (ret)
3798                 return ret;
3799
3800         i915_gem_object_flush_cpu_write_domain(obj);
3801
3802         /* Serialise direct access to this object with the barriers for
3803          * coherent writes from the GPU, by effectively invalidating the
3804          * GTT domain upon first access.
3805          */
3806         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3807                 mb();
3808
3809         old_write_domain = obj->base.write_domain;
3810         old_read_domains = obj->base.read_domains;
3811
3812         /* It should now be out of any other write domains, and we can update
3813          * the domain values for our changes.
3814          */
3815         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3816         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3817         if (write) {
3818                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3819                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3820                 obj->dirty = 1;
3821         }
3822
3823         trace_i915_gem_object_change_domain(obj,
3824                                             old_read_domains,
3825                                             old_write_domain);
3826
3827         /* And bump the LRU for this access */
3828         vma = i915_gem_obj_to_ggtt(obj);
3829         if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3830                 list_move_tail(&vma->vm_link,
3831                                &ggtt->base.inactive_list);
3832
3833         return 0;
3834 }
3835
3836 /**
3837  * Changes the cache-level of an object across all VMA.
3838  *
3839  * After this function returns, the object will be in the new cache-level
3840  * across all GTT and the contents of the backing storage will be coherent,
3841  * with respect to the new cache-level. In order to keep the backing storage
3842  * coherent for all users, we only allow a single cache level to be set
3843  * globally on the object and prevent it from being changed whilst the
3844  * hardware is reading from the object. That is if the object is currently
3845  * on the scanout it will be set to uncached (or equivalent display
3846  * cache coherency) and all non-MOCS GPU access will also be uncached so
3847  * that all direct access to the scanout remains coherent.
3848  */
3849 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3850                                     enum i915_cache_level cache_level)
3851 {
3852         struct drm_device *dev = obj->base.dev;
3853         struct i915_vma *vma, *next;
3854         bool bound = false;
3855         int ret = 0;
3856
3857         if (obj->cache_level == cache_level)
3858                 goto out;
3859
3860         /* Inspect the list of currently bound VMA and unbind any that would
3861          * be invalid given the new cache-level. This is principally to
3862          * catch the issue of the CS prefetch crossing page boundaries and
3863          * reading an invalid PTE on older architectures.
3864          */
3865         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
3866                 if (!drm_mm_node_allocated(&vma->node))
3867                         continue;
3868
3869                 if (vma->pin_count) {
3870                         DRM_DEBUG("can not change the cache level of pinned objects\n");
3871                         return -EBUSY;
3872                 }
3873
3874                 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3875                         ret = i915_vma_unbind(vma);
3876                         if (ret)
3877                                 return ret;
3878                 } else
3879                         bound = true;
3880         }
3881
3882         /* We can reuse the existing drm_mm nodes but need to change the
3883          * cache-level on the PTE. We could simply unbind them all and
3884          * rebind with the correct cache-level on next use. However since
3885          * we already have a valid slot, dma mapping, pages etc, we may as
3886          * rewrite the PTE in the belief that doing so tramples upon less
3887          * state and so involves less work.
3888          */
3889         if (bound) {
3890                 /* Before we change the PTE, the GPU must not be accessing it.
3891                  * If we wait upon the object, we know that all the bound
3892                  * VMA are no longer active.
3893                  */
3894                 ret = i915_gem_object_wait_rendering(obj, false);
3895                 if (ret)
3896                         return ret;
3897
3898                 if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
3899                         /* Access to snoopable pages through the GTT is
3900                          * incoherent and on some machines causes a hard
3901                          * lockup. Relinquish the CPU mmaping to force
3902                          * userspace to refault in the pages and we can
3903                          * then double check if the GTT mapping is still
3904                          * valid for that pointer access.
3905                          */
3906                         i915_gem_release_mmap(obj);
3907
3908                         /* As we no longer need a fence for GTT access,
3909                          * we can relinquish it now (and so prevent having
3910                          * to steal a fence from someone else on the next
3911                          * fence request). Note GPU activity would have
3912                          * dropped the fence as all snoopable access is
3913                          * supposed to be linear.
3914                          */
3915                         ret = i915_gem_object_put_fence(obj);
3916                         if (ret)
3917                                 return ret;
3918                 } else {
3919                         /* We either have incoherent backing store and
3920                          * so no GTT access or the architecture is fully
3921                          * coherent. In such cases, existing GTT mmaps
3922                          * ignore the cache bit in the PTE and we can
3923                          * rewrite it without confusing the GPU or having
3924                          * to force userspace to fault back in its mmaps.
3925                          */
3926                 }
3927
3928                 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3929                         if (!drm_mm_node_allocated(&vma->node))
3930                                 continue;
3931
3932                         ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3933                         if (ret)
3934                                 return ret;
3935                 }
3936         }
3937
3938         list_for_each_entry(vma, &obj->vma_list, obj_link)
3939                 vma->node.color = cache_level;
3940         obj->cache_level = cache_level;
3941
3942 out:
3943         /* Flush the dirty CPU caches to the backing storage so that the
3944          * object is now coherent at its new cache level (with respect
3945          * to the access domain).
3946          */
3947         if (obj->cache_dirty &&
3948             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3949             cpu_write_needs_clflush(obj)) {
3950                 if (i915_gem_clflush_object(obj, true))
3951                         i915_gem_chipset_flush(obj->base.dev);
3952         }
3953
3954         return 0;
3955 }
3956
3957 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3958                                struct drm_file *file)
3959 {
3960         struct drm_i915_gem_caching *args = data;
3961         struct drm_i915_gem_object *obj;
3962
3963         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3964         if (&obj->base == NULL)
3965                 return -ENOENT;
3966
3967         switch (obj->cache_level) {
3968         case I915_CACHE_LLC:
3969         case I915_CACHE_L3_LLC:
3970                 args->caching = I915_CACHING_CACHED;
3971                 break;
3972
3973         case I915_CACHE_WT:
3974                 args->caching = I915_CACHING_DISPLAY;
3975                 break;
3976
3977         default:
3978                 args->caching = I915_CACHING_NONE;
3979                 break;
3980         }
3981
3982         drm_gem_object_unreference_unlocked(&obj->base);
3983         return 0;
3984 }
3985
3986 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3987                                struct drm_file *file)
3988 {
3989         struct drm_i915_private *dev_priv = dev->dev_private;
3990         struct drm_i915_gem_caching *args = data;
3991         struct drm_i915_gem_object *obj;
3992         enum i915_cache_level level;
3993         int ret;
3994
3995         switch (args->caching) {
3996         case I915_CACHING_NONE:
3997                 level = I915_CACHE_NONE;
3998                 break;
3999         case I915_CACHING_CACHED:
4000                 /*
4001                  * Due to a HW issue on BXT A stepping, GPU stores via a
4002                  * snooped mapping may leave stale data in a corresponding CPU
4003                  * cacheline, whereas normally such cachelines would get
4004                  * invalidated.
4005                  */
4006                 if (!HAS_LLC(dev) && !HAS_SNOOP(dev))
4007                         return -ENODEV;
4008
4009                 level = I915_CACHE_LLC;
4010                 break;
4011         case I915_CACHING_DISPLAY:
4012                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
4013                 break;
4014         default:
4015                 return -EINVAL;
4016         }
4017
4018         intel_runtime_pm_get(dev_priv);
4019
4020         ret = i915_mutex_lock_interruptible(dev);
4021         if (ret)
4022                 goto rpm_put;
4023
4024         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4025         if (&obj->base == NULL) {
4026                 ret = -ENOENT;
4027                 goto unlock;
4028         }
4029
4030         ret = i915_gem_object_set_cache_level(obj, level);
4031
4032         drm_gem_object_unreference(&obj->base);
4033 unlock:
4034         mutex_unlock(&dev->struct_mutex);
4035 rpm_put:
4036         intel_runtime_pm_put(dev_priv);
4037
4038         return ret;
4039 }
4040
4041 /*
4042  * Prepare buffer for display plane (scanout, cursors, etc).
4043  * Can be called from an uninterruptible phase (modesetting) and allows
4044  * any flushes to be pipelined (for pageflips).
4045  */
4046 int
4047 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4048                                      u32 alignment,
4049                                      const struct i915_ggtt_view *view)
4050 {
4051         u32 old_read_domains, old_write_domain;
4052         int ret;
4053
4054         /* Mark the pin_display early so that we account for the
4055          * display coherency whilst setting up the cache domains.
4056          */
4057         obj->pin_display++;
4058
4059         /* The display engine is not coherent with the LLC cache on gen6.  As
4060          * a result, we make sure that the pinning that is about to occur is
4061          * done with uncached PTEs. This is lowest common denominator for all
4062          * chipsets.
4063          *
4064          * However for gen6+, we could do better by using the GFDT bit instead
4065          * of uncaching, which would allow us to flush all the LLC-cached data
4066          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4067          */
4068         ret = i915_gem_object_set_cache_level(obj,
4069                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4070         if (ret)
4071                 goto err_unpin_display;
4072
4073         /* As the user may map the buffer once pinned in the display plane
4074          * (e.g. libkms for the bootup splash), we have to ensure that we
4075          * always use map_and_fenceable for all scanout buffers.
4076          */
4077         ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4078                                        view->type == I915_GGTT_VIEW_NORMAL ?
4079                                        PIN_MAPPABLE : 0);
4080         if (ret)
4081                 goto err_unpin_display;
4082
4083         i915_gem_object_flush_cpu_write_domain(obj);
4084
4085         old_write_domain = obj->base.write_domain;
4086         old_read_domains = obj->base.read_domains;
4087
4088         /* It should now be out of any other write domains, and we can update
4089          * the domain values for our changes.
4090          */
4091         obj->base.write_domain = 0;
4092         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4093
4094         trace_i915_gem_object_change_domain(obj,
4095                                             old_read_domains,
4096                                             old_write_domain);
4097
4098         return 0;
4099
4100 err_unpin_display:
4101         obj->pin_display--;
4102         return ret;
4103 }
4104
4105 void
4106 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4107                                          const struct i915_ggtt_view *view)
4108 {
4109         if (WARN_ON(obj->pin_display == 0))
4110                 return;
4111
4112         i915_gem_object_ggtt_unpin_view(obj, view);
4113
4114         obj->pin_display--;
4115 }
4116
4117 /**
4118  * Moves a single object to the CPU read, and possibly write domain.
4119  *
4120  * This function returns when the move is complete, including waiting on
4121  * flushes to occur.
4122  */
4123 int
4124 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4125 {
4126         uint32_t old_write_domain, old_read_domains;
4127         int ret;
4128
4129         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4130                 return 0;
4131
4132         ret = i915_gem_object_wait_rendering(obj, !write);
4133         if (ret)
4134                 return ret;
4135
4136         i915_gem_object_flush_gtt_write_domain(obj);
4137
4138         old_write_domain = obj->base.write_domain;
4139         old_read_domains = obj->base.read_domains;
4140
4141         /* Flush the CPU cache if it's still invalid. */
4142         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4143                 i915_gem_clflush_object(obj, false);
4144
4145                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4146         }
4147
4148         /* It should now be out of any other write domains, and we can update
4149          * the domain values for our changes.
4150          */
4151         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4152
4153         /* If we're writing through the CPU, then the GPU read domains will
4154          * need to be invalidated at next use.
4155          */
4156         if (write) {
4157                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4158                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4159         }
4160
4161         trace_i915_gem_object_change_domain(obj,
4162                                             old_read_domains,
4163                                             old_write_domain);
4164
4165         return 0;
4166 }
4167
4168 /* Throttle our rendering by waiting until the ring has completed our requests
4169  * emitted over 20 msec ago.
4170  *
4171  * Note that if we were to use the current jiffies each time around the loop,
4172  * we wouldn't escape the function with any frames outstanding if the time to
4173  * render a frame was over 20ms.
4174  *
4175  * This should get us reasonable parallelism between CPU and GPU but also
4176  * relatively low latency when blocking on a particular request to finish.
4177  */
4178 static int
4179 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4180 {
4181         struct drm_i915_private *dev_priv = dev->dev_private;
4182         struct drm_i915_file_private *file_priv = file->driver_priv;
4183         unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4184         struct drm_i915_gem_request *request, *target = NULL;
4185         unsigned reset_counter;
4186         int ret;
4187
4188         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4189         if (ret)
4190                 return ret;
4191
4192         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4193         if (ret)
4194                 return ret;
4195
4196         spin_lock(&file_priv->mm.lock);
4197         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4198                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4199                         break;
4200
4201                 /*
4202                  * Note that the request might not have been submitted yet.
4203                  * In which case emitted_jiffies will be zero.
4204                  */
4205                 if (!request->emitted_jiffies)
4206                         continue;
4207
4208                 target = request;
4209         }
4210         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4211         if (target)
4212                 i915_gem_request_reference(target);
4213         spin_unlock(&file_priv->mm.lock);
4214
4215         if (target == NULL)
4216                 return 0;
4217
4218         ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4219         if (ret == 0)
4220                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4221
4222         i915_gem_request_unreference__unlocked(target);
4223
4224         return ret;
4225 }
4226
4227 static bool
4228 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4229 {
4230         struct drm_i915_gem_object *obj = vma->obj;
4231
4232         if (alignment &&
4233             vma->node.start & (alignment - 1))
4234                 return true;
4235
4236         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4237                 return true;
4238
4239         if (flags & PIN_OFFSET_BIAS &&
4240             vma->node.start < (flags & PIN_OFFSET_MASK))
4241                 return true;
4242
4243         if (flags & PIN_OFFSET_FIXED &&
4244             vma->node.start != (flags & PIN_OFFSET_MASK))
4245                 return true;
4246
4247         return false;
4248 }
4249
4250 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
4251 {
4252         struct drm_i915_gem_object *obj = vma->obj;
4253         bool mappable, fenceable;
4254         u32 fence_size, fence_alignment;
4255
4256         fence_size = i915_gem_get_gtt_size(obj->base.dev,
4257                                            obj->base.size,
4258                                            obj->tiling_mode);
4259         fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4260                                                      obj->base.size,
4261                                                      obj->tiling_mode,
4262                                                      true);
4263
4264         fenceable = (vma->node.size == fence_size &&
4265                      (vma->node.start & (fence_alignment - 1)) == 0);
4266
4267         mappable = (vma->node.start + fence_size <=
4268                     to_i915(obj->base.dev)->ggtt.mappable_end);
4269
4270         obj->map_and_fenceable = mappable && fenceable;
4271 }
4272
4273 static int
4274 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4275                        struct i915_address_space *vm,
4276                        const struct i915_ggtt_view *ggtt_view,
4277                        uint32_t alignment,
4278                        uint64_t flags)
4279 {
4280         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4281         struct i915_vma *vma;
4282         unsigned bound;
4283         int ret;
4284
4285         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4286                 return -ENODEV;
4287
4288         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4289                 return -EINVAL;
4290
4291         if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4292                 return -EINVAL;
4293
4294         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4295                 return -EINVAL;
4296
4297         vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4298                           i915_gem_obj_to_vma(obj, vm);
4299
4300         if (vma) {
4301                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4302                         return -EBUSY;
4303
4304                 if (i915_vma_misplaced(vma, alignment, flags)) {
4305                         WARN(vma->pin_count,
4306                              "bo is already pinned in %s with incorrect alignment:"
4307                              " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4308                              " obj->map_and_fenceable=%d\n",
4309                              ggtt_view ? "ggtt" : "ppgtt",
4310                              upper_32_bits(vma->node.start),
4311                              lower_32_bits(vma->node.start),
4312                              alignment,
4313                              !!(flags & PIN_MAPPABLE),
4314                              obj->map_and_fenceable);
4315                         ret = i915_vma_unbind(vma);
4316                         if (ret)
4317                                 return ret;
4318
4319                         vma = NULL;
4320                 }
4321         }
4322
4323         bound = vma ? vma->bound : 0;
4324         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4325                 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4326                                                  flags);
4327                 if (IS_ERR(vma))
4328                         return PTR_ERR(vma);
4329         } else {
4330                 ret = i915_vma_bind(vma, obj->cache_level, flags);
4331                 if (ret)
4332                         return ret;
4333         }
4334
4335         if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4336             (bound ^ vma->bound) & GLOBAL_BIND) {
4337                 __i915_vma_set_map_and_fenceable(vma);
4338                 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4339         }
4340
4341         vma->pin_count++;
4342         return 0;
4343 }
4344
4345 int
4346 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4347                     struct i915_address_space *vm,
4348                     uint32_t alignment,
4349                     uint64_t flags)
4350 {
4351         return i915_gem_object_do_pin(obj, vm,
4352                                       i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4353                                       alignment, flags);
4354 }
4355
4356 int
4357 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4358                          const struct i915_ggtt_view *view,
4359                          uint32_t alignment,
4360                          uint64_t flags)
4361 {
4362         struct drm_device *dev = obj->base.dev;
4363         struct drm_i915_private *dev_priv = to_i915(dev);
4364         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4365
4366         BUG_ON(!view);
4367
4368         return i915_gem_object_do_pin(obj, &ggtt->base, view,
4369                                       alignment, flags | PIN_GLOBAL);
4370 }
4371
4372 void
4373 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4374                                 const struct i915_ggtt_view *view)
4375 {
4376         struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4377
4378         BUG_ON(!vma);
4379         WARN_ON(vma->pin_count == 0);
4380         WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4381
4382         --vma->pin_count;
4383 }
4384
4385 int
4386 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4387                     struct drm_file *file)
4388 {
4389         struct drm_i915_gem_busy *args = data;
4390         struct drm_i915_gem_object *obj;
4391         int ret;
4392
4393         ret = i915_mutex_lock_interruptible(dev);
4394         if (ret)
4395                 return ret;
4396
4397         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4398         if (&obj->base == NULL) {
4399                 ret = -ENOENT;
4400                 goto unlock;
4401         }
4402
4403         /* Count all active objects as busy, even if they are currently not used
4404          * by the gpu. Users of this interface expect objects to eventually
4405          * become non-busy without any further actions, therefore emit any
4406          * necessary flushes here.
4407          */
4408         ret = i915_gem_object_flush_active(obj);
4409         if (ret)
4410                 goto unref;
4411
4412         args->busy = 0;
4413         if (obj->active) {
4414                 int i;
4415
4416                 for (i = 0; i < I915_NUM_ENGINES; i++) {
4417                         struct drm_i915_gem_request *req;
4418
4419                         req = obj->last_read_req[i];
4420                         if (req)
4421                                 args->busy |= 1 << (16 + req->engine->exec_id);
4422                 }
4423                 if (obj->last_write_req)
4424                         args->busy |= obj->last_write_req->engine->exec_id;
4425         }
4426
4427 unref:
4428         drm_gem_object_unreference(&obj->base);
4429 unlock:
4430         mutex_unlock(&dev->struct_mutex);
4431         return ret;
4432 }
4433
4434 int
4435 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4436                         struct drm_file *file_priv)
4437 {
4438         return i915_gem_ring_throttle(dev, file_priv);
4439 }
4440
4441 int
4442 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4443                        struct drm_file *file_priv)
4444 {
4445         struct drm_i915_private *dev_priv = dev->dev_private;
4446         struct drm_i915_gem_madvise *args = data;
4447         struct drm_i915_gem_object *obj;
4448         int ret;
4449
4450         switch (args->madv) {
4451         case I915_MADV_DONTNEED:
4452         case I915_MADV_WILLNEED:
4453             break;
4454         default:
4455             return -EINVAL;
4456         }
4457
4458         ret = i915_mutex_lock_interruptible(dev);
4459         if (ret)
4460                 return ret;
4461
4462         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4463         if (&obj->base == NULL) {
4464                 ret = -ENOENT;
4465                 goto unlock;
4466         }
4467
4468         if (i915_gem_obj_is_pinned(obj)) {
4469                 ret = -EINVAL;
4470                 goto out;
4471         }
4472
4473         if (obj->pages &&
4474             obj->tiling_mode != I915_TILING_NONE &&
4475             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4476                 if (obj->madv == I915_MADV_WILLNEED)
4477                         i915_gem_object_unpin_pages(obj);
4478                 if (args->madv == I915_MADV_WILLNEED)
4479                         i915_gem_object_pin_pages(obj);
4480         }
4481
4482         if (obj->madv != __I915_MADV_PURGED)
4483                 obj->madv = args->madv;
4484
4485         /* if the object is no longer attached, discard its backing storage */
4486         if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4487                 i915_gem_object_truncate(obj);
4488
4489         args->retained = obj->madv != __I915_MADV_PURGED;
4490
4491 out:
4492         drm_gem_object_unreference(&obj->base);
4493 unlock:
4494         mutex_unlock(&dev->struct_mutex);
4495         return ret;
4496 }
4497
4498 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4499                           const struct drm_i915_gem_object_ops *ops)
4500 {
4501         int i;
4502
4503         INIT_LIST_HEAD(&obj->global_list);
4504         for (i = 0; i < I915_NUM_ENGINES; i++)
4505                 INIT_LIST_HEAD(&obj->engine_list[i]);
4506         INIT_LIST_HEAD(&obj->obj_exec_link);
4507         INIT_LIST_HEAD(&obj->vma_list);
4508         INIT_LIST_HEAD(&obj->batch_pool_link);
4509
4510         obj->ops = ops;
4511
4512         obj->fence_reg = I915_FENCE_REG_NONE;
4513         obj->madv = I915_MADV_WILLNEED;
4514
4515         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4516 }
4517
4518 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4519         .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE,
4520         .get_pages = i915_gem_object_get_pages_gtt,
4521         .put_pages = i915_gem_object_put_pages_gtt,
4522 };
4523
4524 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4525                                                   size_t size)
4526 {
4527         struct drm_i915_gem_object *obj;
4528         struct address_space *mapping;
4529         gfp_t mask;
4530
4531         obj = i915_gem_object_alloc(dev);
4532         if (obj == NULL)
4533                 return NULL;
4534
4535         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4536                 i915_gem_object_free(obj);
4537                 return NULL;
4538         }
4539
4540         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4541         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4542                 /* 965gm cannot relocate objects above 4GiB. */
4543                 mask &= ~__GFP_HIGHMEM;
4544                 mask |= __GFP_DMA32;
4545         }
4546
4547         mapping = file_inode(obj->base.filp)->i_mapping;
4548         mapping_set_gfp_mask(mapping, mask);
4549
4550         i915_gem_object_init(obj, &i915_gem_object_ops);
4551
4552         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4553         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4554
4555         if (HAS_LLC(dev)) {
4556                 /* On some devices, we can have the GPU use the LLC (the CPU
4557                  * cache) for about a 10% performance improvement
4558                  * compared to uncached.  Graphics requests other than
4559                  * display scanout are coherent with the CPU in
4560                  * accessing this cache.  This means in this mode we
4561                  * don't need to clflush on the CPU side, and on the
4562                  * GPU side we only need to flush internal caches to
4563                  * get data visible to the CPU.
4564                  *
4565                  * However, we maintain the display planes as UC, and so
4566                  * need to rebind when first used as such.
4567                  */
4568                 obj->cache_level = I915_CACHE_LLC;
4569         } else
4570                 obj->cache_level = I915_CACHE_NONE;
4571
4572         trace_i915_gem_object_create(obj);
4573
4574         return obj;
4575 }
4576
4577 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4578 {
4579         /* If we are the last user of the backing storage (be it shmemfs
4580          * pages or stolen etc), we know that the pages are going to be
4581          * immediately released. In this case, we can then skip copying
4582          * back the contents from the GPU.
4583          */
4584
4585         if (obj->madv != I915_MADV_WILLNEED)
4586                 return false;
4587
4588         if (obj->base.filp == NULL)
4589                 return true;
4590
4591         /* At first glance, this looks racy, but then again so would be
4592          * userspace racing mmap against close. However, the first external
4593          * reference to the filp can only be obtained through the
4594          * i915_gem_mmap_ioctl() which safeguards us against the user
4595          * acquiring such a reference whilst we are in the middle of
4596          * freeing the object.
4597          */
4598         return atomic_long_read(&obj->base.filp->f_count) == 1;
4599 }
4600
4601 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4602 {
4603         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4604         struct drm_device *dev = obj->base.dev;
4605         struct drm_i915_private *dev_priv = dev->dev_private;
4606         struct i915_vma *vma, *next;
4607
4608         intel_runtime_pm_get(dev_priv);
4609
4610         trace_i915_gem_object_destroy(obj);
4611
4612         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
4613                 int ret;
4614
4615                 vma->pin_count = 0;
4616                 ret = i915_vma_unbind(vma);
4617                 if (WARN_ON(ret == -ERESTARTSYS)) {
4618                         bool was_interruptible;
4619
4620                         was_interruptible = dev_priv->mm.interruptible;
4621                         dev_priv->mm.interruptible = false;
4622
4623                         WARN_ON(i915_vma_unbind(vma));
4624
4625                         dev_priv->mm.interruptible = was_interruptible;
4626                 }
4627         }
4628
4629         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4630          * before progressing. */
4631         if (obj->stolen)
4632                 i915_gem_object_unpin_pages(obj);
4633
4634         WARN_ON(obj->frontbuffer_bits);
4635
4636         if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4637             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4638             obj->tiling_mode != I915_TILING_NONE)
4639                 i915_gem_object_unpin_pages(obj);
4640
4641         if (WARN_ON(obj->pages_pin_count))
4642                 obj->pages_pin_count = 0;
4643         if (discard_backing_storage(obj))
4644                 obj->madv = I915_MADV_DONTNEED;
4645         i915_gem_object_put_pages(obj);
4646         i915_gem_object_free_mmap_offset(obj);
4647
4648         BUG_ON(obj->pages);
4649
4650         if (obj->base.import_attach)
4651                 drm_prime_gem_destroy(&obj->base, NULL);
4652
4653         if (obj->ops->release)
4654                 obj->ops->release(obj);
4655
4656         drm_gem_object_release(&obj->base);
4657         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4658
4659         kfree(obj->bit_17);
4660         i915_gem_object_free(obj);
4661
4662         intel_runtime_pm_put(dev_priv);
4663 }
4664
4665 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4666                                      struct i915_address_space *vm)
4667 {
4668         struct i915_vma *vma;
4669         list_for_each_entry(vma, &obj->vma_list, obj_link) {
4670                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL &&
4671                     vma->vm == vm)
4672                         return vma;
4673         }
4674         return NULL;
4675 }
4676
4677 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4678                                            const struct i915_ggtt_view *view)
4679 {
4680         struct drm_device *dev = obj->base.dev;
4681         struct drm_i915_private *dev_priv = to_i915(dev);
4682         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4683         struct i915_vma *vma;
4684
4685         BUG_ON(!view);
4686
4687         list_for_each_entry(vma, &obj->vma_list, obj_link)
4688                 if (vma->vm == &ggtt->base &&
4689                     i915_ggtt_view_equal(&vma->ggtt_view, view))
4690                         return vma;
4691         return NULL;
4692 }
4693
4694 void i915_gem_vma_destroy(struct i915_vma *vma)
4695 {
4696         WARN_ON(vma->node.allocated);
4697
4698         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4699         if (!list_empty(&vma->exec_list))
4700                 return;
4701
4702         if (!vma->is_ggtt)
4703                 i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
4704
4705         list_del(&vma->obj_link);
4706
4707         kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4708 }
4709
4710 static void
4711 i915_gem_stop_engines(struct drm_device *dev)
4712 {
4713         struct drm_i915_private *dev_priv = dev->dev_private;
4714         struct intel_engine_cs *engine;
4715
4716         for_each_engine(engine, dev_priv)
4717                 dev_priv->gt.stop_engine(engine);
4718 }
4719
4720 int
4721 i915_gem_suspend(struct drm_device *dev)
4722 {
4723         struct drm_i915_private *dev_priv = dev->dev_private;
4724         int ret = 0;
4725
4726         mutex_lock(&dev->struct_mutex);
4727         ret = i915_gpu_idle(dev);
4728         if (ret)
4729                 goto err;
4730
4731         i915_gem_retire_requests(dev);
4732
4733         i915_gem_stop_engines(dev);
4734         mutex_unlock(&dev->struct_mutex);
4735
4736         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4737         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4738         flush_delayed_work(&dev_priv->mm.idle_work);
4739
4740         /* Assert that we sucessfully flushed all the work and
4741          * reset the GPU back to its idle, low power state.
4742          */
4743         WARN_ON(dev_priv->mm.busy);
4744
4745         return 0;
4746
4747 err:
4748         mutex_unlock(&dev->struct_mutex);
4749         return ret;
4750 }
4751
4752 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
4753 {
4754         struct intel_engine_cs *engine = req->engine;
4755         struct drm_device *dev = engine->dev;
4756         struct drm_i915_private *dev_priv = dev->dev_private;
4757         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4758         int i, ret;
4759
4760         if (!HAS_L3_DPF(dev) || !remap_info)
4761                 return 0;
4762
4763         ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
4764         if (ret)
4765                 return ret;
4766
4767         /*
4768          * Note: We do not worry about the concurrent register cacheline hang
4769          * here because no other code should access these registers other than
4770          * at initialization time.
4771          */
4772         for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) {
4773                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
4774                 intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i));
4775                 intel_ring_emit(engine, remap_info[i]);
4776         }
4777
4778         intel_ring_advance(engine);
4779
4780         return ret;
4781 }
4782
4783 void i915_gem_init_swizzling(struct drm_device *dev)
4784 {
4785         struct drm_i915_private *dev_priv = dev->dev_private;
4786
4787         if (INTEL_INFO(dev)->gen < 5 ||
4788             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4789                 return;
4790
4791         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4792                                  DISP_TILE_SURFACE_SWIZZLING);
4793
4794         if (IS_GEN5(dev))
4795                 return;
4796
4797         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4798         if (IS_GEN6(dev))
4799                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4800         else if (IS_GEN7(dev))
4801                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4802         else if (IS_GEN8(dev))
4803                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4804         else
4805                 BUG();
4806 }
4807
4808 static void init_unused_ring(struct drm_device *dev, u32 base)
4809 {
4810         struct drm_i915_private *dev_priv = dev->dev_private;
4811
4812         I915_WRITE(RING_CTL(base), 0);
4813         I915_WRITE(RING_HEAD(base), 0);
4814         I915_WRITE(RING_TAIL(base), 0);
4815         I915_WRITE(RING_START(base), 0);
4816 }
4817
4818 static void init_unused_rings(struct drm_device *dev)
4819 {
4820         if (IS_I830(dev)) {
4821                 init_unused_ring(dev, PRB1_BASE);
4822                 init_unused_ring(dev, SRB0_BASE);
4823                 init_unused_ring(dev, SRB1_BASE);
4824                 init_unused_ring(dev, SRB2_BASE);
4825                 init_unused_ring(dev, SRB3_BASE);
4826         } else if (IS_GEN2(dev)) {
4827                 init_unused_ring(dev, SRB0_BASE);
4828                 init_unused_ring(dev, SRB1_BASE);
4829         } else if (IS_GEN3(dev)) {
4830                 init_unused_ring(dev, PRB1_BASE);
4831                 init_unused_ring(dev, PRB2_BASE);
4832         }
4833 }
4834
4835 int i915_gem_init_engines(struct drm_device *dev)
4836 {
4837         struct drm_i915_private *dev_priv = dev->dev_private;
4838         int ret;
4839
4840         ret = intel_init_render_ring_buffer(dev);
4841         if (ret)
4842                 return ret;
4843
4844         if (HAS_BSD(dev)) {
4845                 ret = intel_init_bsd_ring_buffer(dev);
4846                 if (ret)
4847                         goto cleanup_render_ring;
4848         }
4849
4850         if (HAS_BLT(dev)) {
4851                 ret = intel_init_blt_ring_buffer(dev);
4852                 if (ret)
4853                         goto cleanup_bsd_ring;
4854         }
4855
4856         if (HAS_VEBOX(dev)) {
4857                 ret = intel_init_vebox_ring_buffer(dev);
4858                 if (ret)
4859                         goto cleanup_blt_ring;
4860         }
4861
4862         if (HAS_BSD2(dev)) {
4863                 ret = intel_init_bsd2_ring_buffer(dev);
4864                 if (ret)
4865                         goto cleanup_vebox_ring;
4866         }
4867
4868         return 0;
4869
4870 cleanup_vebox_ring:
4871         intel_cleanup_engine(&dev_priv->engine[VECS]);
4872 cleanup_blt_ring:
4873         intel_cleanup_engine(&dev_priv->engine[BCS]);
4874 cleanup_bsd_ring:
4875         intel_cleanup_engine(&dev_priv->engine[VCS]);
4876 cleanup_render_ring:
4877         intel_cleanup_engine(&dev_priv->engine[RCS]);
4878
4879         return ret;
4880 }
4881
4882 int
4883 i915_gem_init_hw(struct drm_device *dev)
4884 {
4885         struct drm_i915_private *dev_priv = dev->dev_private;
4886         struct intel_engine_cs *engine;
4887         int ret, j;
4888
4889         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4890                 return -EIO;
4891
4892         /* Double layer security blanket, see i915_gem_init() */
4893         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4894
4895         if (dev_priv->ellc_size)
4896                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4897
4898         if (IS_HASWELL(dev))
4899                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4900                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4901
4902         if (HAS_PCH_NOP(dev)) {
4903                 if (IS_IVYBRIDGE(dev)) {
4904                         u32 temp = I915_READ(GEN7_MSG_CTL);
4905                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4906                         I915_WRITE(GEN7_MSG_CTL, temp);
4907                 } else if (INTEL_INFO(dev)->gen >= 7) {
4908                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4909                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4910                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4911                 }
4912         }
4913
4914         i915_gem_init_swizzling(dev);
4915
4916         /*
4917          * At least 830 can leave some of the unused rings
4918          * "active" (ie. head != tail) after resume which
4919          * will prevent c3 entry. Makes sure all unused rings
4920          * are totally idle.
4921          */
4922         init_unused_rings(dev);
4923
4924         BUG_ON(!dev_priv->kernel_context);
4925
4926         ret = i915_ppgtt_init_hw(dev);
4927         if (ret) {
4928                 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4929                 goto out;
4930         }
4931
4932         /* Need to do basic initialisation of all rings first: */
4933         for_each_engine(engine, dev_priv) {
4934                 ret = engine->init_hw(engine);
4935                 if (ret)
4936                         goto out;
4937         }
4938
4939         /* We can't enable contexts until all firmware is loaded */
4940         if (HAS_GUC_UCODE(dev)) {
4941                 ret = intel_guc_ucode_load(dev);
4942                 if (ret) {
4943                         DRM_ERROR("Failed to initialize GuC, error %d\n", ret);
4944                         ret = -EIO;
4945                         goto out;
4946                 }
4947         }
4948
4949         /*
4950          * Increment the next seqno by 0x100 so we have a visible break
4951          * on re-initialisation
4952          */
4953         ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100);
4954         if (ret)
4955                 goto out;
4956
4957         /* Now it is safe to go back round and do everything else: */
4958         for_each_engine(engine, dev_priv) {
4959                 struct drm_i915_gem_request *req;
4960
4961                 req = i915_gem_request_alloc(engine, NULL);
4962                 if (IS_ERR(req)) {
4963                         ret = PTR_ERR(req);
4964                         i915_gem_cleanup_engines(dev);
4965                         goto out;
4966                 }
4967
4968                 if (engine->id == RCS) {
4969                         for (j = 0; j < NUM_L3_SLICES(dev); j++)
4970                                 i915_gem_l3_remap(req, j);
4971                 }
4972
4973                 ret = i915_ppgtt_init_ring(req);
4974                 if (ret && ret != -EIO) {
4975                         DRM_ERROR("PPGTT enable %s failed %d\n",
4976                                   engine->name, ret);
4977                         i915_gem_request_cancel(req);
4978                         i915_gem_cleanup_engines(dev);
4979                         goto out;
4980                 }
4981
4982                 ret = i915_gem_context_enable(req);
4983                 if (ret && ret != -EIO) {
4984                         DRM_ERROR("Context enable %s failed %d\n",
4985                                   engine->name, ret);
4986                         i915_gem_request_cancel(req);
4987                         i915_gem_cleanup_engines(dev);
4988                         goto out;
4989                 }
4990
4991                 i915_add_request_no_flush(req);
4992         }
4993
4994 out:
4995         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4996         return ret;
4997 }
4998
4999 int i915_gem_init(struct drm_device *dev)
5000 {
5001         struct drm_i915_private *dev_priv = dev->dev_private;
5002         int ret;
5003
5004         i915.enable_execlists = intel_sanitize_enable_execlists(dev,
5005                         i915.enable_execlists);
5006
5007         mutex_lock(&dev->struct_mutex);
5008
5009         if (!i915.enable_execlists) {
5010                 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
5011                 dev_priv->gt.init_engines = i915_gem_init_engines;
5012                 dev_priv->gt.cleanup_engine = intel_cleanup_engine;
5013                 dev_priv->gt.stop_engine = intel_stop_engine;
5014         } else {
5015                 dev_priv->gt.execbuf_submit = intel_execlists_submission;
5016                 dev_priv->gt.init_engines = intel_logical_rings_init;
5017                 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
5018                 dev_priv->gt.stop_engine = intel_logical_ring_stop;
5019         }
5020
5021         /* This is just a security blanket to placate dragons.
5022          * On some systems, we very sporadically observe that the first TLBs
5023          * used by the CS may be stale, despite us poking the TLB reset. If
5024          * we hold the forcewake during initialisation these problems
5025          * just magically go away.
5026          */
5027         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5028
5029         ret = i915_gem_init_userptr(dev);
5030         if (ret)
5031                 goto out_unlock;
5032
5033         i915_gem_init_ggtt(dev);
5034
5035         ret = i915_gem_context_init(dev);
5036         if (ret)
5037                 goto out_unlock;
5038
5039         ret = dev_priv->gt.init_engines(dev);
5040         if (ret)
5041                 goto out_unlock;
5042
5043         ret = i915_gem_init_hw(dev);
5044         if (ret == -EIO) {
5045                 /* Allow ring initialisation to fail by marking the GPU as
5046                  * wedged. But we only want to do this where the GPU is angry,
5047                  * for all other failure, such as an allocation failure, bail.
5048                  */
5049                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5050                 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
5051                 ret = 0;
5052         }
5053
5054 out_unlock:
5055         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5056         mutex_unlock(&dev->struct_mutex);
5057
5058         return ret;
5059 }
5060
5061 void
5062 i915_gem_cleanup_engines(struct drm_device *dev)
5063 {
5064         struct drm_i915_private *dev_priv = dev->dev_private;
5065         struct intel_engine_cs *engine;
5066
5067         for_each_engine(engine, dev_priv)
5068                 dev_priv->gt.cleanup_engine(engine);
5069
5070         if (i915.enable_execlists)
5071                 /*
5072                  * Neither the BIOS, ourselves or any other kernel
5073                  * expects the system to be in execlists mode on startup,
5074                  * so we need to reset the GPU back to legacy mode.
5075                  */
5076                 intel_gpu_reset(dev, ALL_ENGINES);
5077 }
5078
5079 static void
5080 init_engine_lists(struct intel_engine_cs *engine)
5081 {
5082         INIT_LIST_HEAD(&engine->active_list);
5083         INIT_LIST_HEAD(&engine->request_list);
5084 }
5085
5086 void
5087 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
5088 {
5089         struct drm_device *dev = dev_priv->dev;
5090
5091         if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
5092             !IS_CHERRYVIEW(dev_priv))
5093                 dev_priv->num_fence_regs = 32;
5094         else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
5095                  IS_I945GM(dev_priv) || IS_G33(dev_priv))
5096                 dev_priv->num_fence_regs = 16;
5097         else
5098                 dev_priv->num_fence_regs = 8;
5099
5100         if (intel_vgpu_active(dev))
5101                 dev_priv->num_fence_regs =
5102                                 I915_READ(vgtif_reg(avail_rs.fence_num));
5103
5104         /* Initialize fence registers to zero */
5105         i915_gem_restore_fences(dev);
5106
5107         i915_gem_detect_bit_6_swizzle(dev);
5108 }
5109
5110 void
5111 i915_gem_load_init(struct drm_device *dev)
5112 {
5113         struct drm_i915_private *dev_priv = dev->dev_private;
5114         int i;
5115
5116         dev_priv->objects =
5117                 kmem_cache_create("i915_gem_object",
5118                                   sizeof(struct drm_i915_gem_object), 0,
5119                                   SLAB_HWCACHE_ALIGN,
5120                                   NULL);
5121         dev_priv->vmas =
5122                 kmem_cache_create("i915_gem_vma",
5123                                   sizeof(struct i915_vma), 0,
5124                                   SLAB_HWCACHE_ALIGN,
5125                                   NULL);
5126         dev_priv->requests =
5127                 kmem_cache_create("i915_gem_request",
5128                                   sizeof(struct drm_i915_gem_request), 0,
5129                                   SLAB_HWCACHE_ALIGN,
5130                                   NULL);
5131
5132         INIT_LIST_HEAD(&dev_priv->vm_list);
5133         INIT_LIST_HEAD(&dev_priv->context_list);
5134         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5135         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5136         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5137         for (i = 0; i < I915_NUM_ENGINES; i++)
5138                 init_engine_lists(&dev_priv->engine[i]);
5139         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5140                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5141         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5142                           i915_gem_retire_work_handler);
5143         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5144                           i915_gem_idle_work_handler);
5145         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5146
5147         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5148
5149         /*
5150          * Set initial sequence number for requests.
5151          * Using this number allows the wraparound to happen early,
5152          * catching any obvious problems.
5153          */
5154         dev_priv->next_seqno = ((u32)~0 - 0x1100);
5155         dev_priv->last_seqno = ((u32)~0 - 0x1101);
5156
5157         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5158
5159         init_waitqueue_head(&dev_priv->pending_flip_queue);
5160
5161         dev_priv->mm.interruptible = true;
5162
5163         mutex_init(&dev_priv->fb_tracking.lock);
5164 }
5165
5166 void i915_gem_load_cleanup(struct drm_device *dev)
5167 {
5168         struct drm_i915_private *dev_priv = to_i915(dev);
5169
5170         kmem_cache_destroy(dev_priv->requests);
5171         kmem_cache_destroy(dev_priv->vmas);
5172         kmem_cache_destroy(dev_priv->objects);
5173 }
5174
5175 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5176 {
5177         struct drm_i915_file_private *file_priv = file->driver_priv;
5178
5179         /* Clean up our request list when the client is going away, so that
5180          * later retire_requests won't dereference our soon-to-be-gone
5181          * file_priv.
5182          */
5183         spin_lock(&file_priv->mm.lock);
5184         while (!list_empty(&file_priv->mm.request_list)) {
5185                 struct drm_i915_gem_request *request;
5186
5187                 request = list_first_entry(&file_priv->mm.request_list,
5188                                            struct drm_i915_gem_request,
5189                                            client_list);
5190                 list_del(&request->client_list);
5191                 request->file_priv = NULL;
5192         }
5193         spin_unlock(&file_priv->mm.lock);
5194
5195         if (!list_empty(&file_priv->rps.link)) {
5196                 spin_lock(&to_i915(dev)->rps.client_lock);
5197                 list_del(&file_priv->rps.link);
5198                 spin_unlock(&to_i915(dev)->rps.client_lock);
5199         }
5200 }
5201
5202 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5203 {
5204         struct drm_i915_file_private *file_priv;
5205         int ret;
5206
5207         DRM_DEBUG_DRIVER("\n");
5208
5209         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5210         if (!file_priv)
5211                 return -ENOMEM;
5212
5213         file->driver_priv = file_priv;
5214         file_priv->dev_priv = dev->dev_private;
5215         file_priv->file = file;
5216         INIT_LIST_HEAD(&file_priv->rps.link);
5217
5218         spin_lock_init(&file_priv->mm.lock);
5219         INIT_LIST_HEAD(&file_priv->mm.request_list);
5220
5221         file_priv->bsd_ring = -1;
5222
5223         ret = i915_gem_context_open(dev, file);
5224         if (ret)
5225                 kfree(file_priv);
5226
5227         return ret;
5228 }
5229
5230 /**
5231  * i915_gem_track_fb - update frontbuffer tracking
5232  * @old: current GEM buffer for the frontbuffer slots
5233  * @new: new GEM buffer for the frontbuffer slots
5234  * @frontbuffer_bits: bitmask of frontbuffer slots
5235  *
5236  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5237  * from @old and setting them in @new. Both @old and @new can be NULL.
5238  */
5239 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5240                        struct drm_i915_gem_object *new,
5241                        unsigned frontbuffer_bits)
5242 {
5243         if (old) {
5244                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5245                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5246                 old->frontbuffer_bits &= ~frontbuffer_bits;
5247         }
5248
5249         if (new) {
5250                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5251                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5252                 new->frontbuffer_bits |= frontbuffer_bits;
5253         }
5254 }
5255
5256 /* All the new VM stuff */
5257 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5258                         struct i915_address_space *vm)
5259 {
5260         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5261         struct i915_vma *vma;
5262
5263         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5264
5265         list_for_each_entry(vma, &o->vma_list, obj_link) {
5266                 if (vma->is_ggtt &&
5267                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5268                         continue;
5269                 if (vma->vm == vm)
5270                         return vma->node.start;
5271         }
5272
5273         WARN(1, "%s vma for this object not found.\n",
5274              i915_is_ggtt(vm) ? "global" : "ppgtt");
5275         return -1;
5276 }
5277
5278 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5279                                   const struct i915_ggtt_view *view)
5280 {
5281         struct drm_i915_private *dev_priv = to_i915(o->base.dev);
5282         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5283         struct i915_vma *vma;
5284
5285         list_for_each_entry(vma, &o->vma_list, obj_link)
5286                 if (vma->vm == &ggtt->base &&
5287                     i915_ggtt_view_equal(&vma->ggtt_view, view))
5288                         return vma->node.start;
5289
5290         WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5291         return -1;
5292 }
5293
5294 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5295                         struct i915_address_space *vm)
5296 {
5297         struct i915_vma *vma;
5298
5299         list_for_each_entry(vma, &o->vma_list, obj_link) {
5300                 if (vma->is_ggtt &&
5301                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5302                         continue;
5303                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5304                         return true;
5305         }
5306
5307         return false;
5308 }
5309
5310 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5311                                   const struct i915_ggtt_view *view)
5312 {
5313         struct drm_i915_private *dev_priv = to_i915(o->base.dev);
5314         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5315         struct i915_vma *vma;
5316
5317         list_for_each_entry(vma, &o->vma_list, obj_link)
5318                 if (vma->vm == &ggtt->base &&
5319                     i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5320                     drm_mm_node_allocated(&vma->node))
5321                         return true;
5322
5323         return false;
5324 }
5325
5326 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5327 {
5328         struct i915_vma *vma;
5329
5330         list_for_each_entry(vma, &o->vma_list, obj_link)
5331                 if (drm_mm_node_allocated(&vma->node))
5332                         return true;
5333
5334         return false;
5335 }
5336
5337 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5338                                 struct i915_address_space *vm)
5339 {
5340         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5341         struct i915_vma *vma;
5342
5343         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5344
5345         BUG_ON(list_empty(&o->vma_list));
5346
5347         list_for_each_entry(vma, &o->vma_list, obj_link) {
5348                 if (vma->is_ggtt &&
5349                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5350                         continue;
5351                 if (vma->vm == vm)
5352                         return vma->node.size;
5353         }
5354         return 0;
5355 }
5356
5357 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5358 {
5359         struct i915_vma *vma;
5360         list_for_each_entry(vma, &obj->vma_list, obj_link)
5361                 if (vma->pin_count > 0)
5362                         return true;
5363
5364         return false;
5365 }
5366
5367 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5368 struct page *
5369 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n)
5370 {
5371         struct page *page;
5372
5373         /* Only default objects have per-page dirty tracking */
5374         if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
5375                 return NULL;
5376
5377         page = i915_gem_object_get_page(obj, n);
5378         set_page_dirty(page);
5379         return page;
5380 }
5381
5382 /* Allocate a new GEM object and fill it with the supplied data */
5383 struct drm_i915_gem_object *
5384 i915_gem_object_create_from_data(struct drm_device *dev,
5385                                  const void *data, size_t size)
5386 {
5387         struct drm_i915_gem_object *obj;
5388         struct sg_table *sg;
5389         size_t bytes;
5390         int ret;
5391
5392         obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE));
5393         if (IS_ERR_OR_NULL(obj))
5394                 return obj;
5395
5396         ret = i915_gem_object_set_to_cpu_domain(obj, true);
5397         if (ret)
5398                 goto fail;
5399
5400         ret = i915_gem_object_get_pages(obj);
5401         if (ret)
5402                 goto fail;
5403
5404         i915_gem_object_pin_pages(obj);
5405         sg = obj->pages;
5406         bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
5407         obj->dirty = 1;         /* Backing store is now out of date */
5408         i915_gem_object_unpin_pages(obj);
5409
5410         if (WARN_ON(bytes != size)) {
5411                 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
5412                 ret = -EFAULT;
5413                 goto fail;
5414         }
5415
5416         return obj;
5417
5418 fail:
5419         drm_gem_object_unreference(&obj->base);
5420         return ERR_PTR(ret);
5421 }