drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/oom.h>
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  43                                                    bool force);
  44 static __must_check int
  45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  46                                bool readonly);
  47 static void
  48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  57                                              struct shrink_control *sc);
  58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  59                                             struct shrink_control *sc);
  60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  61                                  unsigned long event,
  62                                  void *ptr);
  63 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  64 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  65
  66 static bool cpu_cache_is_coherent(struct drm_device *dev,
  67                                   enum i915_cache_level level)
  68 {
  69         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  70 }
  71
  72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  73 {
  74         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  75                 return true;
  76
  77         return obj->pin_display;
  78 }
  79
  80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  81 {
  82         if (obj->tiling_mode)
  83                 i915_gem_release_mmap(obj);
  84
  85         /* As we do not have an associated fence register, we will force
  86          * a tiling change if we ever need to acquire one.
  87          */
  88         obj->fence_dirty = false;
  89         obj->fence_reg = I915_FENCE_REG_NONE;
  90 }
  91
  92 /* some bookkeeping */
  93 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  94                                   size_t size)
  95 {
  96         spin_lock(&dev_priv->mm.object_stat_lock);
  97         dev_priv->mm.object_count++;
  98         dev_priv->mm.object_memory += size;
  99         spin_unlock(&dev_priv->mm.object_stat_lock);
 100 }
 101
 102 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 103                                      size_t size)
 104 {
 105         spin_lock(&dev_priv->mm.object_stat_lock);
 106         dev_priv->mm.object_count--;
 107         dev_priv->mm.object_memory -= size;
 108         spin_unlock(&dev_priv->mm.object_stat_lock);
 109 }
 110
 111 static int
 112 i915_gem_wait_for_error(struct i915_gpu_error *error)
 113 {
 114         int ret;
 115
 116 #define EXIT_COND (!i915_reset_in_progress(error) || \
 117                    i915_terminally_wedged(error))
 118         if (EXIT_COND)
 119                 return 0;
 120
 121         /*
 122          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 123          * userspace. If it takes that long something really bad is going on and
 124          * we should simply try to bail out and fail as gracefully as possible.
 125          */
 126         ret = wait_event_interruptible_timeout(error->reset_queue,
 127                                                EXIT_COND,
 128                                                10*HZ);
 129         if (ret == 0) {
 130                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 131                 return -EIO;
 132         } else if (ret < 0) {
 133                 return ret;
 134         }
 135 #undef EXIT_COND
 136
 137         return 0;
 138 }
 139
 140 int i915_mutex_lock_interruptible(struct drm_device *dev)
 141 {
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         int ret;
 144
 145         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 146         if (ret)
 147                 return ret;
 148
 149         ret = mutex_lock_interruptible(&dev->struct_mutex);
 150         if (ret)
 151                 return ret;
 152
 153         WARN_ON(i915_verify_lists(dev));
 154         return 0;
 155 }
 156
 157 static inline bool
 158 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 159 {
 160         return i915_gem_obj_bound_any(obj) && !obj->active;
 161 }
 162
 163 int
 164 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 165                     struct drm_file *file)
 166 {
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         struct drm_i915_gem_init *args = data;
 169
 170         if (drm_core_check_feature(dev, DRIVER_MODESET))
 171                 return -ENODEV;
 172
 173         if (args->gtt_start >= args->gtt_end ||
 174             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 175                 return -EINVAL;
 176
 177         /* GEM with user mode setting was never supported on ilk and later. */
 178         if (INTEL_INFO(dev)->gen >= 5)
 179                 return -ENODEV;
 180
 181         mutex_lock(&dev->struct_mutex);
 182         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 183                                   args->gtt_end);
 184         dev_priv->gtt.mappable_end = args->gtt_end;
 185         mutex_unlock(&dev->struct_mutex);
 186
 187         return 0;
 188 }
 189
 190 int
 191 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 192                             struct drm_file *file)
 193 {
 194         struct drm_i915_private *dev_priv = dev->dev_private;
 195         struct drm_i915_gem_get_aperture *args = data;
 196         struct drm_i915_gem_object *obj;
 197         size_t pinned;
 198
 199         pinned = 0;
 200         mutex_lock(&dev->struct_mutex);
 201         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 202                 if (i915_gem_obj_is_pinned(obj))
 203                         pinned += i915_gem_obj_ggtt_size(obj);
 204         mutex_unlock(&dev->struct_mutex);
 205
 206         args->aper_size = dev_priv->gtt.base.total;
 207         args->aper_available_size = args->aper_size - pinned;
 208
 209         return 0;
 210 }
 211
 212 static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
 213 {
 214         drm_dma_handle_t *phys = obj->phys_handle;
 215
 216         if (!phys)
 217                 return;
 218
 219         if (obj->madv == I915_MADV_WILLNEED) {
 220                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 221                 char *vaddr = phys->vaddr;
 222                 int i;
 223
 224                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 225                         struct page *page = shmem_read_mapping_page(mapping, i);
 226                         if (!IS_ERR(page)) {
 227                                 char *dst = kmap_atomic(page);
 228                                 memcpy(dst, vaddr, PAGE_SIZE);
 229                                 drm_clflush_virt_range(dst, PAGE_SIZE);
 230                                 kunmap_atomic(dst);
 231
 232                                 set_page_dirty(page);
 233                                 mark_page_accessed(page);
 234                                 page_cache_release(page);
 235                         }
 236                         vaddr += PAGE_SIZE;
 237                 }
 238                 i915_gem_chipset_flush(obj->base.dev);
 239         }
 240
 241 #ifdef CONFIG_X86
 242         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 243 #endif
 244         drm_pci_free(obj->base.dev, phys);
 245         obj->phys_handle = NULL;
 246 }
 247
 248 int
 249 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 250                             int align)
 251 {
 252         drm_dma_handle_t *phys;
 253         struct address_space *mapping;
 254         char *vaddr;
 255         int i;
 256
 257         if (obj->phys_handle) {
 258                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 259                         return -EBUSY;
 260
 261                 return 0;
 262         }
 263
 264         if (obj->madv != I915_MADV_WILLNEED)
 265                 return -EFAULT;
 266
 267         if (obj->base.filp == NULL)
 268                 return -EINVAL;
 269
 270         /* create a new object */
 271         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 272         if (!phys)
 273                 return -ENOMEM;
 274
 275         vaddr = phys->vaddr;
 276 #ifdef CONFIG_X86
 277         set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
 278 #endif
 279         mapping = file_inode(obj->base.filp)->i_mapping;
 280         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 281                 struct page *page;
 282                 char *src;
 283
 284                 page = shmem_read_mapping_page(mapping, i);
 285                 if (IS_ERR(page)) {
 286 #ifdef CONFIG_X86
 287                         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 288 #endif
 289                         drm_pci_free(obj->base.dev, phys);
 290                         return PTR_ERR(page);
 291                 }
 292
 293                 src = kmap_atomic(page);
 294                 memcpy(vaddr, src, PAGE_SIZE);
 295                 kunmap_atomic(src);
 296
 297                 mark_page_accessed(page);
 298                 page_cache_release(page);
 299
 300                 vaddr += PAGE_SIZE;
 301         }
 302
 303         obj->phys_handle = phys;
 304         return 0;
 305 }
 306
 307 static int
 308 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 309                      struct drm_i915_gem_pwrite *args,
 310                      struct drm_file *file_priv)
 311 {
 312         struct drm_device *dev = obj->base.dev;
 313         void *vaddr = obj->phys_handle->vaddr + args->offset;
 314         char __user *user_data = to_user_ptr(args->data_ptr);
 315
 316         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 317                 unsigned long unwritten;
 318
 319                 /* The physical object once assigned is fixed for the lifetime
 320                  * of the obj, so we can safely drop the lock and continue
 321                  * to access vaddr.
 322                  */
 323                 mutex_unlock(&dev->struct_mutex);
 324                 unwritten = copy_from_user(vaddr, user_data, args->size);
 325                 mutex_lock(&dev->struct_mutex);
 326                 if (unwritten)
 327                         return -EFAULT;
 328         }
 329
 330         i915_gem_chipset_flush(dev);
 331         return 0;
 332 }
 333
 334 void *i915_gem_object_alloc(struct drm_device *dev)
 335 {
 336         struct drm_i915_private *dev_priv = dev->dev_private;
 337         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 338 }
 339
 340 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 341 {
 342         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 343         kmem_cache_free(dev_priv->slab, obj);
 344 }
 345
 346 static int
 347 i915_gem_create(struct drm_file *file,
 348                 struct drm_device *dev,
 349                 uint64_t size,
 350                 uint32_t *handle_p)
 351 {
 352         struct drm_i915_gem_object *obj;
 353         int ret;
 354         u32 handle;
 355
 356         size = roundup(size, PAGE_SIZE);
 357         if (size == 0)
 358                 return -EINVAL;
 359
 360         /* Allocate the new object */
 361         obj = i915_gem_alloc_object(dev, size);
 362         if (obj == NULL)
 363                 return -ENOMEM;
 364
 365         ret = drm_gem_handle_create(file, &obj->base, &handle);
 366         /* drop reference from allocate - handle holds it now */
 367         drm_gem_object_unreference_unlocked(&obj->base);
 368         if (ret)
 369                 return ret;
 370
 371         *handle_p = handle;
 372         return 0;
 373 }
 374
 375 int
 376 i915_gem_dumb_create(struct drm_file *file,
 377                      struct drm_device *dev,
 378                      struct drm_mode_create_dumb *args)
 379 {
 380         /* have to work out size/pitch and return them */
 381         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 382         args->size = args->pitch * args->height;
 383         return i915_gem_create(file, dev,
 384                                args->size, &args->handle);
 385 }
 386
 387 /**
 388  * Creates a new mm object and returns a handle to it.
 389  */
 390 int
 391 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 392                       struct drm_file *file)
 393 {
 394         struct drm_i915_gem_create *args = data;
 395
 396         return i915_gem_create(file, dev,
 397                                args->size, &args->handle);
 398 }
 399
 400 static inline int
 401 __copy_to_user_swizzled(char __user *cpu_vaddr,
 402                         const char *gpu_vaddr, int gpu_offset,
 403                         int length)
 404 {
 405         int ret, cpu_offset = 0;
 406
 407         while (length > 0) {
 408                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 409                 int this_length = min(cacheline_end - gpu_offset, length);
 410                 int swizzled_gpu_offset = gpu_offset ^ 64;
 411
 412                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 413                                      gpu_vaddr + swizzled_gpu_offset,
 414                                      this_length);
 415                 if (ret)
 416                         return ret + length;
 417
 418                 cpu_offset += this_length;
 419                 gpu_offset += this_length;
 420                 length -= this_length;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static inline int
 427 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 428                           const char __user *cpu_vaddr,
 429                           int length)
 430 {
 431         int ret, cpu_offset = 0;
 432
 433         while (length > 0) {
 434                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 435                 int this_length = min(cacheline_end - gpu_offset, length);
 436                 int swizzled_gpu_offset = gpu_offset ^ 64;
 437
 438                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 439                                        cpu_vaddr + cpu_offset,
 440                                        this_length);
 441                 if (ret)
 442                         return ret + length;
 443
 444                 cpu_offset += this_length;
 445                 gpu_offset += this_length;
 446                 length -= this_length;
 447         }
 448
 449         return 0;
 450 }
 451
 452 /*
 453  * Pins the specified object's pages and synchronizes the object with
 454  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 455  * flush the object from the CPU cache.
 456  */
 457 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 458                                     int *needs_clflush)
 459 {
 460         int ret;
 461
 462         *needs_clflush = 0;
 463
 464         if (!obj->base.filp)
 465                 return -EINVAL;
 466
 467         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 468                 /* If we're not in the cpu read domain, set ourself into the gtt
 469                  * read domain and manually flush cachelines (if required). This
 470                  * optimizes for the case when the gpu will dirty the data
 471                  * anyway again before the next pread happens. */
 472                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 473                                                         obj->cache_level);
 474                 ret = i915_gem_object_wait_rendering(obj, true);
 475                 if (ret)
 476                         return ret;
 477
 478                 i915_gem_object_retire(obj);
 479         }
 480
 481         ret = i915_gem_object_get_pages(obj);
 482         if (ret)
 483                 return ret;
 484
 485         i915_gem_object_pin_pages(obj);
 486
 487         return ret;
 488 }
 489
 490 /* Per-page copy function for the shmem pread fastpath.
 491  * Flushes invalid cachelines before reading the target if
 492  * needs_clflush is set. */
 493 static int
 494 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 495                  char __user *user_data,
 496                  bool page_do_bit17_swizzling, bool needs_clflush)
 497 {
 498         char *vaddr;
 499         int ret;
 500
 501         if (unlikely(page_do_bit17_swizzling))
 502                 return -EINVAL;
 503
 504         vaddr = kmap_atomic(page);
 505         if (needs_clflush)
 506                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 507                                        page_length);
 508         ret = __copy_to_user_inatomic(user_data,
 509                                       vaddr + shmem_page_offset,
 510                                       page_length);
 511         kunmap_atomic(vaddr);
 512
 513         return ret ? -EFAULT : 0;
 514 }
 515
 516 static void
 517 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 518                              bool swizzled)
 519 {
 520         if (unlikely(swizzled)) {
 521                 unsigned long start = (unsigned long) addr;
 522                 unsigned long end = (unsigned long) addr + length;
 523
 524                 /* For swizzling simply ensure that we always flush both
 525                  * channels. Lame, but simple and it works. Swizzled
 526                  * pwrite/pread is far from a hotpath - current userspace
 527                  * doesn't use it at all. */
 528                 start = round_down(start, 128);
 529                 end = round_up(end, 128);
 530
 531                 drm_clflush_virt_range((void *)start, end - start);
 532         } else {
 533                 drm_clflush_virt_range(addr, length);
 534         }
 535
 536 }
 537
 538 /* Only difference to the fast-path function is that this can handle bit17
 539  * and uses non-atomic copy and kmap functions. */
 540 static int
 541 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 542                  char __user *user_data,
 543                  bool page_do_bit17_swizzling, bool needs_clflush)
 544 {
 545         char *vaddr;
 546         int ret;
 547
 548         vaddr = kmap(page);
 549         if (needs_clflush)
 550                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 551                                              page_length,
 552                                              page_do_bit17_swizzling);
 553
 554         if (page_do_bit17_swizzling)
 555                 ret = __copy_to_user_swizzled(user_data,
 556                                               vaddr, shmem_page_offset,
 557                                               page_length);
 558         else
 559                 ret = __copy_to_user(user_data,
 560                                      vaddr + shmem_page_offset,
 561                                      page_length);
 562         kunmap(page);
 563
 564         return ret ? - EFAULT : 0;
 565 }
 566
 567 static int
 568 i915_gem_shmem_pread(struct drm_device *dev,
 569                      struct drm_i915_gem_object *obj,
 570                      struct drm_i915_gem_pread *args,
 571                      struct drm_file *file)
 572 {
 573         char __user *user_data;
 574         ssize_t remain;
 575         loff_t offset;
 576         int shmem_page_offset, page_length, ret = 0;
 577         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 578         int prefaulted = 0;
 579         int needs_clflush = 0;
 580         struct sg_page_iter sg_iter;
 581
 582         user_data = to_user_ptr(args->data_ptr);
 583         remain = args->size;
 584
 585         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 586
 587         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 588         if (ret)
 589                 return ret;
 590
 591         offset = args->offset;
 592
 593         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 594                          offset >> PAGE_SHIFT) {
 595                 struct page *page = sg_page_iter_page(&sg_iter);
 596
 597                 if (remain <= 0)
 598                         break;
 599
 600                 /* Operation in this page
 601                  *
 602                  * shmem_page_offset = offset within page in shmem file
 603                  * page_length = bytes to copy for this page
 604                  */
 605                 shmem_page_offset = offset_in_page(offset);
 606                 page_length = remain;
 607                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 608                         page_length = PAGE_SIZE - shmem_page_offset;
 609
 610                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 611                         (page_to_phys(page) & (1 << 17)) != 0;
 612
 613                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 614                                        user_data, page_do_bit17_swizzling,
 615                                        needs_clflush);
 616                 if (ret == 0)
 617                         goto next_page;
 618
 619                 mutex_unlock(&dev->struct_mutex);
 620
 621                 if (likely(!i915.prefault_disable) && !prefaulted) {
 622                         ret = fault_in_multipages_writeable(user_data, remain);
 623                         /* Userspace is tricking us, but we've already clobbered
 624                          * its pages with the prefault and promised to write the
 625                          * data up to the first fault. Hence ignore any errors
 626                          * and just continue. */
 627                         (void)ret;
 628                         prefaulted = 1;
 629                 }
 630
 631                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 632                                        user_data, page_do_bit17_swizzling,
 633                                        needs_clflush);
 634
 635                 mutex_lock(&dev->struct_mutex);
 636
 637                 if (ret)
 638                         goto out;
 639
 640 next_page:
 641                 remain -= page_length;
 642                 user_data += page_length;
 643                 offset += page_length;
 644         }
 645
 646 out:
 647         i915_gem_object_unpin_pages(obj);
 648
 649         return ret;
 650 }
 651
 652 /**
 653  * Reads data from the object referenced by handle.
 654  *
 655  * On error, the contents of *data are undefined.
 656  */
 657 int
 658 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 659                      struct drm_file *file)
 660 {
 661         struct drm_i915_gem_pread *args = data;
 662         struct drm_i915_gem_object *obj;
 663         int ret = 0;
 664
 665         if (args->size == 0)
 666                 return 0;
 667
 668         if (!access_ok(VERIFY_WRITE,
 669                        to_user_ptr(args->data_ptr),
 670                        args->size))
 671                 return -EFAULT;
 672
 673         ret = i915_mutex_lock_interruptible(dev);
 674         if (ret)
 675                 return ret;
 676
 677         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 678         if (&obj->base == NULL) {
 679                 ret = -ENOENT;
 680                 goto unlock;
 681         }
 682
 683         /* Bounds check source.  */
 684         if (args->offset > obj->base.size ||
 685             args->size > obj->base.size - args->offset) {
 686                 ret = -EINVAL;
 687                 goto out;
 688         }
 689
 690         /* prime objects have no backing filp to GEM pread/pwrite
 691          * pages from.
 692          */
 693         if (!obj->base.filp) {
 694                 ret = -EINVAL;
 695                 goto out;
 696         }
 697
 698         trace_i915_gem_object_pread(obj, args->offset, args->size);
 699
 700         ret = i915_gem_shmem_pread(dev, obj, args, file);
 701
 702 out:
 703         drm_gem_object_unreference(&obj->base);
 704 unlock:
 705         mutex_unlock(&dev->struct_mutex);
 706         return ret;
 707 }
 708
 709 /* This is the fast write path which cannot handle
 710  * page faults in the source data
 711  */
 712
 713 static inline int
 714 fast_user_write(struct io_mapping *mapping,
 715                 loff_t page_base, int page_offset,
 716                 char __user *user_data,
 717                 int length)
 718 {
 719         void __iomem *vaddr_atomic;
 720         void *vaddr;
 721         unsigned long unwritten;
 722
 723         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 724         /* We can use the cpu mem copy function because this is X86. */
 725         vaddr = (void __force*)vaddr_atomic + page_offset;
 726         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 727                                                       user_data, length);
 728         io_mapping_unmap_atomic(vaddr_atomic);
 729         return unwritten;
 730 }
 731
 732 /**
 733  * This is the fast pwrite path, where we copy the data directly from the
 734  * user into the GTT, uncached.
 735  */
 736 static int
 737 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 738                          struct drm_i915_gem_object *obj,
 739                          struct drm_i915_gem_pwrite *args,
 740                          struct drm_file *file)
 741 {
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         ssize_t remain;
 744         loff_t offset, page_base;
 745         char __user *user_data;
 746         int page_offset, page_length, ret;
 747
 748         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 749         if (ret)
 750                 goto out;
 751
 752         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 753         if (ret)
 754                 goto out_unpin;
 755
 756         ret = i915_gem_object_put_fence(obj);
 757         if (ret)
 758                 goto out_unpin;
 759
 760         user_data = to_user_ptr(args->data_ptr);
 761         remain = args->size;
 762
 763         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 764
 765         while (remain > 0) {
 766                 /* Operation in this page
 767                  *
 768                  * page_base = page offset within aperture
 769                  * page_offset = offset within page
 770                  * page_length = bytes to copy for this page
 771                  */
 772                 page_base = offset & PAGE_MASK;
 773                 page_offset = offset_in_page(offset);
 774                 page_length = remain;
 775                 if ((page_offset + remain) > PAGE_SIZE)
 776                         page_length = PAGE_SIZE - page_offset;
 777
 778                 /* If we get a fault while copying data, then (presumably) our
 779                  * source page isn't available.  Return the error and we'll
 780                  * retry in the slow path.
 781                  */
 782                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 783                                     page_offset, user_data, page_length)) {
 784                         ret = -EFAULT;
 785                         goto out_unpin;
 786                 }
 787
 788                 remain -= page_length;
 789                 user_data += page_length;
 790                 offset += page_length;
 791         }
 792
 793 out_unpin:
 794         i915_gem_object_ggtt_unpin(obj);
 795 out:
 796         return ret;
 797 }
 798
 799 /* Per-page copy function for the shmem pwrite fastpath.
 800  * Flushes invalid cachelines before writing to the target if
 801  * needs_clflush_before is set and flushes out any written cachelines after
 802  * writing if needs_clflush is set. */
 803 static int
 804 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 805                   char __user *user_data,
 806                   bool page_do_bit17_swizzling,
 807                   bool needs_clflush_before,
 808                   bool needs_clflush_after)
 809 {
 810         char *vaddr;
 811         int ret;
 812
 813         if (unlikely(page_do_bit17_swizzling))
 814                 return -EINVAL;
 815
 816         vaddr = kmap_atomic(page);
 817         if (needs_clflush_before)
 818                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 819                                        page_length);
 820         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 821                                         user_data, page_length);
 822         if (needs_clflush_after)
 823                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 824                                        page_length);
 825         kunmap_atomic(vaddr);
 826
 827         return ret ? -EFAULT : 0;
 828 }
 829
 830 /* Only difference to the fast-path function is that this can handle bit17
 831  * and uses non-atomic copy and kmap functions. */
 832 static int
 833 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 834                   char __user *user_data,
 835                   bool page_do_bit17_swizzling,
 836                   bool needs_clflush_before,
 837                   bool needs_clflush_after)
 838 {
 839         char *vaddr;
 840         int ret;
 841
 842         vaddr = kmap(page);
 843         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 844                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 845                                              page_length,
 846                                              page_do_bit17_swizzling);
 847         if (page_do_bit17_swizzling)
 848                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 849                                                 user_data,
 850                                                 page_length);
 851         else
 852                 ret = __copy_from_user(vaddr + shmem_page_offset,
 853                                        user_data,
 854                                        page_length);
 855         if (needs_clflush_after)
 856                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 857                                              page_length,
 858                                              page_do_bit17_swizzling);
 859         kunmap(page);
 860
 861         return ret ? -EFAULT : 0;
 862 }
 863
 864 static int
 865 i915_gem_shmem_pwrite(struct drm_device *dev,
 866                       struct drm_i915_gem_object *obj,
 867                       struct drm_i915_gem_pwrite *args,
 868                       struct drm_file *file)
 869 {
 870         ssize_t remain;
 871         loff_t offset;
 872         char __user *user_data;
 873         int shmem_page_offset, page_length, ret = 0;
 874         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 875         int hit_slowpath = 0;
 876         int needs_clflush_after = 0;
 877         int needs_clflush_before = 0;
 878         struct sg_page_iter sg_iter;
 879
 880         user_data = to_user_ptr(args->data_ptr);
 881         remain = args->size;
 882
 883         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 884
 885         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 886                 /* If we're not in the cpu write domain, set ourself into the gtt
 887                  * write domain and manually flush cachelines (if required). This
 888                  * optimizes for the case when the gpu will use the data
 889                  * right away and we therefore have to clflush anyway. */
 890                 needs_clflush_after = cpu_write_needs_clflush(obj);
 891                 ret = i915_gem_object_wait_rendering(obj, false);
 892                 if (ret)
 893                         return ret;
 894
 895                 i915_gem_object_retire(obj);
 896         }
 897         /* Same trick applies to invalidate partially written cachelines read
 898          * before writing. */
 899         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 900                 needs_clflush_before =
 901                         !cpu_cache_is_coherent(dev, obj->cache_level);
 902
 903         ret = i915_gem_object_get_pages(obj);
 904         if (ret)
 905                 return ret;
 906
 907         i915_gem_object_pin_pages(obj);
 908
 909         offset = args->offset;
 910         obj->dirty = 1;
 911
 912         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 913                          offset >> PAGE_SHIFT) {
 914                 struct page *page = sg_page_iter_page(&sg_iter);
 915                 int partial_cacheline_write;
 916
 917                 if (remain <= 0)
 918                         break;
 919
 920                 /* Operation in this page
 921                  *
 922                  * shmem_page_offset = offset within page in shmem file
 923                  * page_length = bytes to copy for this page
 924                  */
 925                 shmem_page_offset = offset_in_page(offset);
 926
 927                 page_length = remain;
 928                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 929                         page_length = PAGE_SIZE - shmem_page_offset;
 930
 931                 /* If we don't overwrite a cacheline completely we need to be
 932                  * careful to have up-to-date data by first clflushing. Don't
 933                  * overcomplicate things and flush the entire patch. */
 934                 partial_cacheline_write = needs_clflush_before &&
 935                         ((shmem_page_offset | page_length)
 936                                 & (boot_cpu_data.x86_clflush_size - 1));
 937
 938                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 939                         (page_to_phys(page) & (1 << 17)) != 0;
 940
 941                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 942                                         user_data, page_do_bit17_swizzling,
 943                                         partial_cacheline_write,
 944                                         needs_clflush_after);
 945                 if (ret == 0)
 946                         goto next_page;
 947
 948                 hit_slowpath = 1;
 949                 mutex_unlock(&dev->struct_mutex);
 950                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 951                                         user_data, page_do_bit17_swizzling,
 952                                         partial_cacheline_write,
 953                                         needs_clflush_after);
 954
 955                 mutex_lock(&dev->struct_mutex);
 956
 957                 if (ret)
 958                         goto out;
 959
 960 next_page:
 961                 remain -= page_length;
 962                 user_data += page_length;
 963                 offset += page_length;
 964         }
 965
 966 out:
 967         i915_gem_object_unpin_pages(obj);
 968
 969         if (hit_slowpath) {
 970                 /*
 971                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 972                  * cachelines in-line while writing and the object moved
 973                  * out of the cpu write domain while we've dropped the lock.
 974                  */
 975                 if (!needs_clflush_after &&
 976                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 977                         if (i915_gem_clflush_object(obj, obj->pin_display))
 978                                 i915_gem_chipset_flush(dev);
 979                 }
 980         }
 981
 982         if (needs_clflush_after)
 983                 i915_gem_chipset_flush(dev);
 984
 985         return ret;
 986 }
 987
 988 /**
 989  * Writes data to the object referenced by handle.
 990  *
 991  * On error, the contents of the buffer that were to be modified are undefined.
 992  */
 993 int
 994 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 995                       struct drm_file *file)
 996 {
 997         struct drm_i915_gem_pwrite *args = data;
 998         struct drm_i915_gem_object *obj;
 999         int ret;
1000
1001         if (args->size == 0)
1002                 return 0;
1003
1004         if (!access_ok(VERIFY_READ,
1005                        to_user_ptr(args->data_ptr),
1006                        args->size))
1007                 return -EFAULT;
1008
1009         if (likely(!i915.prefault_disable)) {
1010                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1011                                                    args->size);
1012                 if (ret)
1013                         return -EFAULT;
1014         }
1015
1016         ret = i915_mutex_lock_interruptible(dev);
1017         if (ret)
1018                 return ret;
1019
1020         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1021         if (&obj->base == NULL) {
1022                 ret = -ENOENT;
1023                 goto unlock;
1024         }
1025
1026         /* Bounds check destination. */
1027         if (args->offset > obj->base.size ||
1028             args->size > obj->base.size - args->offset) {
1029                 ret = -EINVAL;
1030                 goto out;
1031         }
1032
1033         /* prime objects have no backing filp to GEM pread/pwrite
1034          * pages from.
1035          */
1036         if (!obj->base.filp) {
1037                 ret = -EINVAL;
1038                 goto out;
1039         }
1040
1041         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1042
1043         ret = -EFAULT;
1044         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1045          * it would end up going through the fenced access, and we'll get
1046          * different detiling behavior between reading and writing.
1047          * pread/pwrite currently are reading and writing from the CPU
1048          * perspective, requiring manual detiling by the client.
1049          */
1050         if (obj->phys_handle) {
1051                 ret = i915_gem_phys_pwrite(obj, args, file);
1052                 goto out;
1053         }
1054
1055         if (obj->tiling_mode == I915_TILING_NONE &&
1056             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1057             cpu_write_needs_clflush(obj)) {
1058                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1059                 /* Note that the gtt paths might fail with non-page-backed user
1060                  * pointers (e.g. gtt mappings when moving data between
1061                  * textures). Fallback to the shmem path in that case. */
1062         }
1063
1064         if (ret == -EFAULT || ret == -ENOSPC)
1065                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1066
1067 out:
1068         drm_gem_object_unreference(&obj->base);
1069 unlock:
1070         mutex_unlock(&dev->struct_mutex);
1071         return ret;
1072 }
1073
1074 int
1075 i915_gem_check_wedge(struct i915_gpu_error *error,
1076                      bool interruptible)
1077 {
1078         if (i915_reset_in_progress(error)) {
1079                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1080                  * -EIO unconditionally for these. */
1081                 if (!interruptible)
1082                         return -EIO;
1083
1084                 /* Recovery complete, but the reset failed ... */
1085                 if (i915_terminally_wedged(error))
1086                         return -EIO;
1087
1088                 return -EAGAIN;
1089         }
1090
1091         return 0;
1092 }
1093
1094 /*
1095  * Compare seqno against outstanding lazy request. Emit a request if they are
1096  * equal.
1097  */
1098 static int
1099 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1100 {
1101         int ret;
1102
1103         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1104
1105         ret = 0;
1106         if (seqno == ring->outstanding_lazy_seqno)
1107                 ret = i915_add_request(ring, NULL);
1108
1109         return ret;
1110 }
1111
1112 static void fake_irq(unsigned long data)
1113 {
1114         wake_up_process((struct task_struct *)data);
1115 }
1116
1117 static bool missed_irq(struct drm_i915_private *dev_priv,
1118                        struct intel_engine_cs *ring)
1119 {
1120         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1121 }
1122
1123 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1124 {
1125         if (file_priv == NULL)
1126                 return true;
1127
1128         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1129 }
1130
1131 /**
1132  * __wait_seqno - wait until execution of seqno has finished
1133  * @ring: the ring expected to report seqno
1134  * @seqno: duh!
1135  * @reset_counter: reset sequence associated with the given seqno
1136  * @interruptible: do an interruptible wait (normally yes)
1137  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1138  *
1139  * Note: It is of utmost importance that the passed in seqno and reset_counter
1140  * values have been read by the caller in an smp safe manner. Where read-side
1141  * locks are involved, it is sufficient to read the reset_counter before
1142  * unlocking the lock that protects the seqno. For lockless tricks, the
1143  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1144  * inserted.
1145  *
1146  * Returns 0 if the seqno was found within the alloted time. Else returns the
1147  * errno with remaining time filled in timeout argument.
1148  */
1149 static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1150                         unsigned reset_counter,
1151                         bool interruptible,
1152                         s64 *timeout,
1153                         struct drm_i915_file_private *file_priv)
1154 {
1155         struct drm_device *dev = ring->dev;
1156         struct drm_i915_private *dev_priv = dev->dev_private;
1157         const bool irq_test_in_progress =
1158                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1159         DEFINE_WAIT(wait);
1160         unsigned long timeout_expire;
1161         s64 before, now;
1162         int ret;
1163
1164         WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n");
1165
1166         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1167                 return 0;
1168
1169         timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1170
1171         if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
1172                 gen6_rps_boost(dev_priv);
1173                 if (file_priv)
1174                         mod_delayed_work(dev_priv->wq,
1175                                          &file_priv->mm.idle_work,
1176                                          msecs_to_jiffies(100));
1177         }
1178
1179         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1180                 return -ENODEV;
1181
1182         /* Record current time in case interrupted by signal, or wedged */
1183         trace_i915_gem_request_wait_begin(ring, seqno);
1184         before = ktime_get_raw_ns();
1185         for (;;) {
1186                 struct timer_list timer;
1187
1188                 prepare_to_wait(&ring->irq_queue, &wait,
1189                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1190
1191                 /* We need to check whether any gpu reset happened in between
1192                  * the caller grabbing the seqno and now ... */
1193                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1194                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1195                          * is truely gone. */
1196                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1197                         if (ret == 0)
1198                                 ret = -EAGAIN;
1199                         break;
1200                 }
1201
1202                 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1203                         ret = 0;
1204                         break;
1205                 }
1206
1207                 if (interruptible && signal_pending(current)) {
1208                         ret = -ERESTARTSYS;
1209                         break;
1210                 }
1211
1212                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1213                         ret = -ETIME;
1214                         break;
1215                 }
1216
1217                 timer.function = NULL;
1218                 if (timeout || missed_irq(dev_priv, ring)) {
1219                         unsigned long expire;
1220
1221                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1222                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1223                         mod_timer(&timer, expire);
1224                 }
1225
1226                 io_schedule();
1227
1228                 if (timer.function) {
1229                         del_singleshot_timer_sync(&timer);
1230                         destroy_timer_on_stack(&timer);
1231                 }
1232         }
1233         now = ktime_get_raw_ns();
1234         trace_i915_gem_request_wait_end(ring, seqno);
1235
1236         if (!irq_test_in_progress)
1237                 ring->irq_put(ring);
1238
1239         finish_wait(&ring->irq_queue, &wait);
1240
1241         if (timeout) {
1242                 s64 tres = *timeout - (now - before);
1243
1244                 *timeout = tres < 0 ? 0 : tres;
1245         }
1246
1247         return ret;
1248 }
1249
1250 /**
1251  * Waits for a sequence number to be signaled, and cleans up the
1252  * request and object lists appropriately for that event.
1253  */
1254 int
1255 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1256 {
1257         struct drm_device *dev = ring->dev;
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259         bool interruptible = dev_priv->mm.interruptible;
1260         int ret;
1261
1262         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1263         BUG_ON(seqno == 0);
1264
1265         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1266         if (ret)
1267                 return ret;
1268
1269         ret = i915_gem_check_olr(ring, seqno);
1270         if (ret)
1271                 return ret;
1272
1273         return __wait_seqno(ring, seqno,
1274                             atomic_read(&dev_priv->gpu_error.reset_counter),
1275                             interruptible, NULL, NULL);
1276 }
1277
1278 static int
1279 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1280                                      struct intel_engine_cs *ring)
1281 {
1282         if (!obj->active)
1283                 return 0;
1284
1285         /* Manually manage the write flush as we may have not yet
1286          * retired the buffer.
1287          *
1288          * Note that the last_write_seqno is always the earlier of
1289          * the two (read/write) seqno, so if we haved successfully waited,
1290          * we know we have passed the last write.
1291          */
1292         obj->last_write_seqno = 0;
1293
1294         return 0;
1295 }
1296
1297 /**
1298  * Ensures that all rendering to the object has completed and the object is
1299  * safe to unbind from the GTT or access from the CPU.
1300  */
1301 static __must_check int
1302 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1303                                bool readonly)
1304 {
1305         struct intel_engine_cs *ring = obj->ring;
1306         u32 seqno;
1307         int ret;
1308
1309         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1310         if (seqno == 0)
1311                 return 0;
1312
1313         ret = i915_wait_seqno(ring, seqno);
1314         if (ret)
1315                 return ret;
1316
1317         return i915_gem_object_wait_rendering__tail(obj, ring);
1318 }
1319
1320 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1321  * as the object state may change during this call.
1322  */
1323 static __must_check int
1324 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1325                                             struct drm_i915_file_private *file_priv,
1326                                             bool readonly)
1327 {
1328         struct drm_device *dev = obj->base.dev;
1329         struct drm_i915_private *dev_priv = dev->dev_private;
1330         struct intel_engine_cs *ring = obj->ring;
1331         unsigned reset_counter;
1332         u32 seqno;
1333         int ret;
1334
1335         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1336         BUG_ON(!dev_priv->mm.interruptible);
1337
1338         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1339         if (seqno == 0)
1340                 return 0;
1341
1342         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1343         if (ret)
1344                 return ret;
1345
1346         ret = i915_gem_check_olr(ring, seqno);
1347         if (ret)
1348                 return ret;
1349
1350         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1351         mutex_unlock(&dev->struct_mutex);
1352         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1353         mutex_lock(&dev->struct_mutex);
1354         if (ret)
1355                 return ret;
1356
1357         return i915_gem_object_wait_rendering__tail(obj, ring);
1358 }
1359
1360 /**
1361  * Called when user space prepares to use an object with the CPU, either
1362  * through the mmap ioctl's mapping or a GTT mapping.
1363  */
1364 int
1365 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1366                           struct drm_file *file)
1367 {
1368         struct drm_i915_gem_set_domain *args = data;
1369         struct drm_i915_gem_object *obj;
1370         uint32_t read_domains = args->read_domains;
1371         uint32_t write_domain = args->write_domain;
1372         int ret;
1373
1374         /* Only handle setting domains to types used by the CPU. */
1375         if (write_domain & I915_GEM_GPU_DOMAINS)
1376                 return -EINVAL;
1377
1378         if (read_domains & I915_GEM_GPU_DOMAINS)
1379                 return -EINVAL;
1380
1381         /* Having something in the write domain implies it's in the read
1382          * domain, and only that read domain.  Enforce that in the request.
1383          */
1384         if (write_domain != 0 && read_domains != write_domain)
1385                 return -EINVAL;
1386
1387         ret = i915_mutex_lock_interruptible(dev);
1388         if (ret)
1389                 return ret;
1390
1391         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1392         if (&obj->base == NULL) {
1393                 ret = -ENOENT;
1394                 goto unlock;
1395         }
1396
1397         /* Try to flush the object off the GPU without holding the lock.
1398          * We will repeat the flush holding the lock in the normal manner
1399          * to catch cases where we are gazumped.
1400          */
1401         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1402                                                           file->driver_priv,
1403                                                           !write_domain);
1404         if (ret)
1405                 goto unref;
1406
1407         if (read_domains & I915_GEM_DOMAIN_GTT) {
1408                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1409
1410                 /* Silently promote "you're not bound, there was nothing to do"
1411                  * to success, since the client was just asking us to
1412                  * make sure everything was done.
1413                  */
1414                 if (ret == -EINVAL)
1415                         ret = 0;
1416         } else {
1417                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1418         }
1419
1420 unref:
1421         drm_gem_object_unreference(&obj->base);
1422 unlock:
1423         mutex_unlock(&dev->struct_mutex);
1424         return ret;
1425 }
1426
1427 /**
1428  * Called when user space has done writes to this buffer
1429  */
1430 int
1431 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1432                          struct drm_file *file)
1433 {
1434         struct drm_i915_gem_sw_finish *args = data;
1435         struct drm_i915_gem_object *obj;
1436         int ret = 0;
1437
1438         ret = i915_mutex_lock_interruptible(dev);
1439         if (ret)
1440                 return ret;
1441
1442         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1443         if (&obj->base == NULL) {
1444                 ret = -ENOENT;
1445                 goto unlock;
1446         }
1447
1448         /* Pinned buffers may be scanout, so flush the cache */
1449         if (obj->pin_display)
1450                 i915_gem_object_flush_cpu_write_domain(obj, true);
1451
1452         drm_gem_object_unreference(&obj->base);
1453 unlock:
1454         mutex_unlock(&dev->struct_mutex);
1455         return ret;
1456 }
1457
1458 /**
1459  * Maps the contents of an object, returning the address it is mapped
1460  * into.
1461  *
1462  * While the mapping holds a reference on the contents of the object, it doesn't
1463  * imply a ref on the object itself.
1464  */
1465 int
1466 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1467                     struct drm_file *file)
1468 {
1469         struct drm_i915_gem_mmap *args = data;
1470         struct drm_gem_object *obj;
1471         unsigned long addr;
1472
1473         obj = drm_gem_object_lookup(dev, file, args->handle);
1474         if (obj == NULL)
1475                 return -ENOENT;
1476
1477         /* prime objects have no backing filp to GEM mmap
1478          * pages from.
1479          */
1480         if (!obj->filp) {
1481                 drm_gem_object_unreference_unlocked(obj);
1482                 return -EINVAL;
1483         }
1484
1485         addr = vm_mmap(obj->filp, 0, args->size,
1486                        PROT_READ | PROT_WRITE, MAP_SHARED,
1487                        args->offset);
1488         drm_gem_object_unreference_unlocked(obj);
1489         if (IS_ERR((void *)addr))
1490                 return addr;
1491
1492         args->addr_ptr = (uint64_t) addr;
1493
1494         return 0;
1495 }
1496
1497 /**
1498  * i915_gem_fault - fault a page into the GTT
1499  * vma: VMA in question
1500  * vmf: fault info
1501  *
1502  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1503  * from userspace.  The fault handler takes care of binding the object to
1504  * the GTT (if needed), allocating and programming a fence register (again,
1505  * only if needed based on whether the old reg is still valid or the object
1506  * is tiled) and inserting a new PTE into the faulting process.
1507  *
1508  * Note that the faulting process may involve evicting existing objects
1509  * from the GTT and/or fence registers to make room.  So performance may
1510  * suffer if the GTT working set is large or there are few fence registers
1511  * left.
1512  */
1513 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1514 {
1515         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1516         struct drm_device *dev = obj->base.dev;
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518         pgoff_t page_offset;
1519         unsigned long pfn;
1520         int ret = 0;
1521         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1522
1523         intel_runtime_pm_get(dev_priv);
1524
1525         /* We don't use vmf->pgoff since that has the fake offset */
1526         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1527                 PAGE_SHIFT;
1528
1529         ret = i915_mutex_lock_interruptible(dev);
1530         if (ret)
1531                 goto out;
1532
1533         trace_i915_gem_object_fault(obj, page_offset, true, write);
1534
1535         /* Try to flush the object off the GPU first without holding the lock.
1536          * Upon reacquiring the lock, we will perform our sanity checks and then
1537          * repeat the flush holding the lock in the normal manner to catch cases
1538          * where we are gazumped.
1539          */
1540         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1541         if (ret)
1542                 goto unlock;
1543
1544         /* Access to snoopable pages through the GTT is incoherent. */
1545         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1546                 ret = -EFAULT;
1547                 goto unlock;
1548         }
1549
1550         /* Now bind it into the GTT if needed */
1551         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1552         if (ret)
1553                 goto unlock;
1554
1555         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1556         if (ret)
1557                 goto unpin;
1558
1559         ret = i915_gem_object_get_fence(obj);
1560         if (ret)
1561                 goto unpin;
1562
1563         obj->fault_mappable = true;
1564
1565         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1566         pfn >>= PAGE_SHIFT;
1567         pfn += page_offset;
1568
1569         /* Finally, remap it using the new GTT offset */
1570         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1571 unpin:
1572         i915_gem_object_ggtt_unpin(obj);
1573 unlock:
1574         mutex_unlock(&dev->struct_mutex);
1575 out:
1576         switch (ret) {
1577         case -EIO:
1578                 /* If this -EIO is due to a gpu hang, give the reset code a
1579                  * chance to clean up the mess. Otherwise return the proper
1580                  * SIGBUS. */
1581                 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1582                         ret = VM_FAULT_SIGBUS;
1583                         break;
1584                 }
1585         case -EAGAIN:
1586                 /*
1587                  * EAGAIN means the gpu is hung and we'll wait for the error
1588                  * handler to reset everything when re-faulting in
1589                  * i915_mutex_lock_interruptible.
1590                  */
1591         case 0:
1592         case -ERESTARTSYS:
1593         case -EINTR:
1594         case -EBUSY:
1595                 /*
1596                  * EBUSY is ok: this just means that another thread
1597                  * already did the job.
1598                  */
1599                 ret = VM_FAULT_NOPAGE;
1600                 break;
1601         case -ENOMEM:
1602                 ret = VM_FAULT_OOM;
1603                 break;
1604         case -ENOSPC:
1605         case -EFAULT:
1606                 ret = VM_FAULT_SIGBUS;
1607                 break;
1608         default:
1609                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1610                 ret = VM_FAULT_SIGBUS;
1611                 break;
1612         }
1613
1614         intel_runtime_pm_put(dev_priv);
1615         return ret;
1616 }
1617
1618 /**
1619  * i915_gem_release_mmap - remove physical page mappings
1620  * @obj: obj in question
1621  *
1622  * Preserve the reservation of the mmapping with the DRM core code, but
1623  * relinquish ownership of the pages back to the system.
1624  *
1625  * It is vital that we remove the page mapping if we have mapped a tiled
1626  * object through the GTT and then lose the fence register due to
1627  * resource pressure. Similarly if the object has been moved out of the
1628  * aperture, than pages mapped into userspace must be revoked. Removing the
1629  * mapping will then trigger a page fault on the next user access, allowing
1630  * fixup by i915_gem_fault().
1631  */
1632 void
1633 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1634 {
1635         if (!obj->fault_mappable)
1636                 return;
1637
1638         drm_vma_node_unmap(&obj->base.vma_node,
1639                            obj->base.dev->anon_inode->i_mapping);
1640         obj->fault_mappable = false;
1641 }
1642
1643 void
1644 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1645 {
1646         struct drm_i915_gem_object *obj;
1647
1648         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1649                 i915_gem_release_mmap(obj);
1650 }
1651
1652 uint32_t
1653 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1654 {
1655         uint32_t gtt_size;
1656
1657         if (INTEL_INFO(dev)->gen >= 4 ||
1658             tiling_mode == I915_TILING_NONE)
1659                 return size;
1660
1661         /* Previous chips need a power-of-two fence region when tiling */
1662         if (INTEL_INFO(dev)->gen == 3)
1663                 gtt_size = 1024*1024;
1664         else
1665                 gtt_size = 512*1024;
1666
1667         while (gtt_size < size)
1668                 gtt_size <<= 1;
1669
1670         return gtt_size;
1671 }
1672
1673 /**
1674  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1675  * @obj: object to check
1676  *
1677  * Return the required GTT alignment for an object, taking into account
1678  * potential fence register mapping.
1679  */
1680 uint32_t
1681 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1682                            int tiling_mode, bool fenced)
1683 {
1684         /*
1685          * Minimum alignment is 4k (GTT page size), but might be greater
1686          * if a fence register is needed for the object.
1687          */
1688         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1689             tiling_mode == I915_TILING_NONE)
1690                 return 4096;
1691
1692         /*
1693          * Previous chips need to be aligned to the size of the smallest
1694          * fence register that can contain the object.
1695          */
1696         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1697 }
1698
1699 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1700 {
1701         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1702         int ret;
1703
1704         if (drm_vma_node_has_offset(&obj->base.vma_node))
1705                 return 0;
1706
1707         dev_priv->mm.shrinker_no_lock_stealing = true;
1708
1709         ret = drm_gem_create_mmap_offset(&obj->base);
1710         if (ret != -ENOSPC)
1711                 goto out;
1712
1713         /* Badly fragmented mmap space? The only way we can recover
1714          * space is by destroying unwanted objects. We can't randomly release
1715          * mmap_offsets as userspace expects them to be persistent for the
1716          * lifetime of the objects. The closest we can is to release the
1717          * offsets on purgeable objects by truncating it and marking it purged,
1718          * which prevents userspace from ever using that object again.
1719          */
1720         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1721         ret = drm_gem_create_mmap_offset(&obj->base);
1722         if (ret != -ENOSPC)
1723                 goto out;
1724
1725         i915_gem_shrink_all(dev_priv);
1726         ret = drm_gem_create_mmap_offset(&obj->base);
1727 out:
1728         dev_priv->mm.shrinker_no_lock_stealing = false;
1729
1730         return ret;
1731 }
1732
1733 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1734 {
1735         drm_gem_free_mmap_offset(&obj->base);
1736 }
1737
1738 int
1739 i915_gem_mmap_gtt(struct drm_file *file,
1740                   struct drm_device *dev,
1741                   uint32_t handle,
1742                   uint64_t *offset)
1743 {
1744         struct drm_i915_private *dev_priv = dev->dev_private;
1745         struct drm_i915_gem_object *obj;
1746         int ret;
1747
1748         ret = i915_mutex_lock_interruptible(dev);
1749         if (ret)
1750                 return ret;
1751
1752         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1753         if (&obj->base == NULL) {
1754                 ret = -ENOENT;
1755                 goto unlock;
1756         }
1757
1758         if (obj->base.size > dev_priv->gtt.mappable_end) {
1759                 ret = -E2BIG;
1760                 goto out;
1761         }
1762
1763         if (obj->madv != I915_MADV_WILLNEED) {
1764                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1765                 ret = -EFAULT;
1766                 goto out;
1767         }
1768
1769         ret = i915_gem_object_create_mmap_offset(obj);
1770         if (ret)
1771                 goto out;
1772
1773         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1774
1775 out:
1776         drm_gem_object_unreference(&obj->base);
1777 unlock:
1778         mutex_unlock(&dev->struct_mutex);
1779         return ret;
1780 }
1781
1782 /**
1783  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1784  * @dev: DRM device
1785  * @data: GTT mapping ioctl data
1786  * @file: GEM object info
1787  *
1788  * Simply returns the fake offset to userspace so it can mmap it.
1789  * The mmap call will end up in drm_gem_mmap(), which will set things
1790  * up so we can get faults in the handler above.
1791  *
1792  * The fault handler will take care of binding the object into the GTT
1793  * (since it may have been evicted to make room for something), allocating
1794  * a fence register, and mapping the appropriate aperture address into
1795  * userspace.
1796  */
1797 int
1798 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1799                         struct drm_file *file)
1800 {
1801         struct drm_i915_gem_mmap_gtt *args = data;
1802
1803         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1804 }
1805
1806 static inline int
1807 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1808 {
1809         return obj->madv == I915_MADV_DONTNEED;
1810 }
1811
1812 /* Immediately discard the backing storage */
1813 static void
1814 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1815 {
1816         i915_gem_object_free_mmap_offset(obj);
1817
1818         if (obj->base.filp == NULL)
1819                 return;
1820
1821         /* Our goal here is to return as much of the memory as
1822          * is possible back to the system as we are called from OOM.
1823          * To do this we must instruct the shmfs to drop all of its
1824          * backing pages, *now*.
1825          */
1826         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1827         obj->madv = __I915_MADV_PURGED;
1828 }
1829
1830 /* Try to discard unwanted pages */
1831 static void
1832 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1833 {
1834         struct address_space *mapping;
1835
1836         switch (obj->madv) {
1837         case I915_MADV_DONTNEED:
1838                 i915_gem_object_truncate(obj);
1839         case __I915_MADV_PURGED:
1840                 return;
1841         }
1842
1843         if (obj->base.filp == NULL)
1844                 return;
1845
1846         mapping = file_inode(obj->base.filp)->i_mapping,
1847         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1848 }
1849
1850 static void
1851 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1852 {
1853         struct sg_page_iter sg_iter;
1854         int ret;
1855
1856         BUG_ON(obj->madv == __I915_MADV_PURGED);
1857
1858         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1859         if (ret) {
1860                 /* In the event of a disaster, abandon all caches and
1861                  * hope for the best.
1862                  */
1863                 WARN_ON(ret != -EIO);
1864                 i915_gem_clflush_object(obj, true);
1865                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1866         }
1867
1868         if (i915_gem_object_needs_bit17_swizzle(obj))
1869                 i915_gem_object_save_bit_17_swizzle(obj);
1870
1871         if (obj->madv == I915_MADV_DONTNEED)
1872                 obj->dirty = 0;
1873
1874         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1875                 struct page *page = sg_page_iter_page(&sg_iter);
1876
1877                 if (obj->dirty)
1878                         set_page_dirty(page);
1879
1880                 if (obj->madv == I915_MADV_WILLNEED)
1881                         mark_page_accessed(page);
1882
1883                 page_cache_release(page);
1884         }
1885         obj->dirty = 0;
1886
1887         sg_free_table(obj->pages);
1888         kfree(obj->pages);
1889 }
1890
1891 int
1892 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1893 {
1894         const struct drm_i915_gem_object_ops *ops = obj->ops;
1895
1896         if (obj->pages == NULL)
1897                 return 0;
1898
1899         if (obj->pages_pin_count)
1900                 return -EBUSY;
1901
1902         BUG_ON(i915_gem_obj_bound_any(obj));
1903
1904         /* ->put_pages might need to allocate memory for the bit17 swizzle
1905          * array, hence protect them from being reaped by removing them from gtt
1906          * lists early. */
1907         list_del(&obj->global_list);
1908
1909         ops->put_pages(obj);
1910         obj->pages = NULL;
1911
1912         i915_gem_object_invalidate(obj);
1913
1914         return 0;
1915 }
1916
1917 static unsigned long
1918 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1919                   bool purgeable_only)
1920 {
1921         struct list_head still_in_list;
1922         struct drm_i915_gem_object *obj;
1923         unsigned long count = 0;
1924
1925         /*
1926          * As we may completely rewrite the (un)bound list whilst unbinding
1927          * (due to retiring requests) we have to strictly process only
1928          * one element of the list at the time, and recheck the list
1929          * on every iteration.
1930          *
1931          * In particular, we must hold a reference whilst removing the
1932          * object as we may end up waiting for and/or retiring the objects.
1933          * This might release the final reference (held by the active list)
1934          * and result in the object being freed from under us. This is
1935          * similar to the precautions the eviction code must take whilst
1936          * removing objects.
1937          *
1938          * Also note that although these lists do not hold a reference to
1939          * the object we can safely grab one here: The final object
1940          * unreferencing and the bound_list are both protected by the
1941          * dev->struct_mutex and so we won't ever be able to observe an
1942          * object on the bound_list with a reference count equals 0.
1943          */
1944         INIT_LIST_HEAD(&still_in_list);
1945         while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
1946                 obj = list_first_entry(&dev_priv->mm.unbound_list,
1947                                        typeof(*obj), global_list);
1948                 list_move_tail(&obj->global_list, &still_in_list);
1949
1950                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1951                         continue;
1952
1953                 drm_gem_object_reference(&obj->base);
1954
1955                 if (i915_gem_object_put_pages(obj) == 0)
1956                         count += obj->base.size >> PAGE_SHIFT;
1957
1958                 drm_gem_object_unreference(&obj->base);
1959         }
1960         list_splice(&still_in_list, &dev_priv->mm.unbound_list);
1961
1962         INIT_LIST_HEAD(&still_in_list);
1963         while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1964                 struct i915_vma *vma, *v;
1965
1966                 obj = list_first_entry(&dev_priv->mm.bound_list,
1967                                        typeof(*obj), global_list);
1968                 list_move_tail(&obj->global_list, &still_in_list);
1969
1970                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1971                         continue;
1972
1973                 drm_gem_object_reference(&obj->base);
1974
1975                 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1976                         if (i915_vma_unbind(vma))
1977                                 break;
1978
1979                 if (i915_gem_object_put_pages(obj) == 0)
1980                         count += obj->base.size >> PAGE_SHIFT;
1981
1982                 drm_gem_object_unreference(&obj->base);
1983         }
1984         list_splice(&still_in_list, &dev_priv->mm.bound_list);
1985
1986         return count;
1987 }
1988
1989 static unsigned long
1990 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1991 {
1992         return __i915_gem_shrink(dev_priv, target, true);
1993 }
1994
1995 static unsigned long
1996 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1997 {
1998         i915_gem_evict_everything(dev_priv->dev);
1999         return __i915_gem_shrink(dev_priv, LONG_MAX, false);
2000 }
2001
2002 static int
2003 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2004 {
2005         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2006         int page_count, i;
2007         struct address_space *mapping;
2008         struct sg_table *st;
2009         struct scatterlist *sg;
2010         struct sg_page_iter sg_iter;
2011         struct page *page;
2012         unsigned long last_pfn = 0;     /* suppress gcc warning */
2013         gfp_t gfp;
2014
2015         /* Assert that the object is not currently in any GPU domain. As it
2016          * wasn't in the GTT, there shouldn't be any way it could have been in
2017          * a GPU cache
2018          */
2019         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2020         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2021
2022         st = kmalloc(sizeof(*st), GFP_KERNEL);
2023         if (st == NULL)
2024                 return -ENOMEM;
2025
2026         page_count = obj->base.size / PAGE_SIZE;
2027         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2028                 kfree(st);
2029                 return -ENOMEM;
2030         }
2031
2032         /* Get the list of pages out of our struct file.  They'll be pinned
2033          * at this point until we release them.
2034          *
2035          * Fail silently without starting the shrinker
2036          */
2037         mapping = file_inode(obj->base.filp)->i_mapping;
2038         gfp = mapping_gfp_mask(mapping);
2039         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2040         gfp &= ~(__GFP_IO | __GFP_WAIT);
2041         sg = st->sgl;
2042         st->nents = 0;
2043         for (i = 0; i < page_count; i++) {
2044                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2045                 if (IS_ERR(page)) {
2046                         i915_gem_purge(dev_priv, page_count);
2047                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2048                 }
2049                 if (IS_ERR(page)) {
2050                         /* We've tried hard to allocate the memory by reaping
2051                          * our own buffer, now let the real VM do its job and
2052                          * go down in flames if truly OOM.
2053                          */
2054                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
2055                         gfp |= __GFP_IO | __GFP_WAIT;
2056
2057                         i915_gem_shrink_all(dev_priv);
2058                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2059                         if (IS_ERR(page))
2060                                 goto err_pages;
2061
2062                         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2063                         gfp &= ~(__GFP_IO | __GFP_WAIT);
2064                 }
2065 #ifdef CONFIG_SWIOTLB
2066                 if (swiotlb_nr_tbl()) {
2067                         st->nents++;
2068                         sg_set_page(sg, page, PAGE_SIZE, 0);
2069                         sg = sg_next(sg);
2070                         continue;
2071                 }
2072 #endif
2073                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2074                         if (i)
2075                                 sg = sg_next(sg);
2076                         st->nents++;
2077                         sg_set_page(sg, page, PAGE_SIZE, 0);
2078                 } else {
2079                         sg->length += PAGE_SIZE;
2080                 }
2081                 last_pfn = page_to_pfn(page);
2082
2083                 /* Check that the i965g/gm workaround works. */
2084                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2085         }
2086 #ifdef CONFIG_SWIOTLB
2087         if (!swiotlb_nr_tbl())
2088 #endif
2089                 sg_mark_end(sg);
2090         obj->pages = st;
2091
2092         if (i915_gem_object_needs_bit17_swizzle(obj))
2093                 i915_gem_object_do_bit_17_swizzle(obj);
2094
2095         return 0;
2096
2097 err_pages:
2098         sg_mark_end(sg);
2099         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2100                 page_cache_release(sg_page_iter_page(&sg_iter));
2101         sg_free_table(st);
2102         kfree(st);
2103
2104         /* shmemfs first checks if there is enough memory to allocate the page
2105          * and reports ENOSPC should there be insufficient, along with the usual
2106          * ENOMEM for a genuine allocation failure.
2107          *
2108          * We use ENOSPC in our driver to mean that we have run out of aperture
2109          * space and so want to translate the error from shmemfs back to our
2110          * usual understanding of ENOMEM.
2111          */
2112         if (PTR_ERR(page) == -ENOSPC)
2113                 return -ENOMEM;
2114         else
2115                 return PTR_ERR(page);
2116 }
2117
2118 /* Ensure that the associated pages are gathered from the backing storage
2119  * and pinned into our object. i915_gem_object_get_pages() may be called
2120  * multiple times before they are released by a single call to
2121  * i915_gem_object_put_pages() - once the pages are no longer referenced
2122  * either as a result of memory pressure (reaping pages under the shrinker)
2123  * or as the object is itself released.
2124  */
2125 int
2126 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2127 {
2128         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129         const struct drm_i915_gem_object_ops *ops = obj->ops;
2130         int ret;
2131
2132         if (obj->pages)
2133                 return 0;
2134
2135         if (obj->madv != I915_MADV_WILLNEED) {
2136                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2137                 return -EFAULT;
2138         }
2139
2140         BUG_ON(obj->pages_pin_count);
2141
2142         ret = ops->get_pages(obj);
2143         if (ret)
2144                 return ret;
2145
2146         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2147         return 0;
2148 }
2149
2150 static void
2151 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2152                                struct intel_engine_cs *ring)
2153 {
2154         struct drm_device *dev = obj->base.dev;
2155         struct drm_i915_private *dev_priv = dev->dev_private;
2156         u32 seqno = intel_ring_get_seqno(ring);
2157
2158         BUG_ON(ring == NULL);
2159         if (obj->ring != ring && obj->last_write_seqno) {
2160                 /* Keep the seqno relative to the current ring */
2161                 obj->last_write_seqno = seqno;
2162         }
2163         obj->ring = ring;
2164
2165         /* Add a reference if we're newly entering the active list. */
2166         if (!obj->active) {
2167                 drm_gem_object_reference(&obj->base);
2168                 obj->active = 1;
2169         }
2170
2171         list_move_tail(&obj->ring_list, &ring->active_list);
2172
2173         obj->last_read_seqno = seqno;
2174
2175         if (obj->fenced_gpu_access) {
2176                 obj->last_fenced_seqno = seqno;
2177
2178                 /* Bump MRU to take account of the delayed flush */
2179                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2180                         struct drm_i915_fence_reg *reg;
2181
2182                         reg = &dev_priv->fence_regs[obj->fence_reg];
2183                         list_move_tail(&reg->lru_list,
2184                                        &dev_priv->mm.fence_list);
2185                 }
2186         }
2187 }
2188
2189 void i915_vma_move_to_active(struct i915_vma *vma,
2190                              struct intel_engine_cs *ring)
2191 {
2192         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2193         return i915_gem_object_move_to_active(vma->obj, ring);
2194 }
2195
2196 static void
2197 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2198 {
2199         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2200         struct i915_address_space *vm;
2201         struct i915_vma *vma;
2202
2203         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2204         BUG_ON(!obj->active);
2205
2206         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2207                 vma = i915_gem_obj_to_vma(obj, vm);
2208                 if (vma && !list_empty(&vma->mm_list))
2209                         list_move_tail(&vma->mm_list, &vm->inactive_list);
2210         }
2211
2212         list_del_init(&obj->ring_list);
2213         obj->ring = NULL;
2214
2215         obj->last_read_seqno = 0;
2216         obj->last_write_seqno = 0;
2217         obj->base.write_domain = 0;
2218
2219         obj->last_fenced_seqno = 0;
2220         obj->fenced_gpu_access = false;
2221
2222         obj->active = 0;
2223         drm_gem_object_unreference(&obj->base);
2224
2225         WARN_ON(i915_verify_lists(dev));
2226 }
2227
2228 static void
2229 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2230 {
2231         struct intel_engine_cs *ring = obj->ring;
2232
2233         if (ring == NULL)
2234                 return;
2235
2236         if (i915_seqno_passed(ring->get_seqno(ring, true),
2237                               obj->last_read_seqno))
2238                 i915_gem_object_move_to_inactive(obj);
2239 }
2240
2241 static int
2242 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2243 {
2244         struct drm_i915_private *dev_priv = dev->dev_private;
2245         struct intel_engine_cs *ring;
2246         int ret, i, j;
2247
2248         /* Carefully retire all requests without writing to the rings */
2249         for_each_ring(ring, dev_priv, i) {
2250                 ret = intel_ring_idle(ring);
2251                 if (ret)
2252                         return ret;
2253         }
2254         i915_gem_retire_requests(dev);
2255
2256         /* Finally reset hw state */
2257         for_each_ring(ring, dev_priv, i) {
2258                 intel_ring_init_seqno(ring, seqno);
2259
2260                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2261                         ring->semaphore.sync_seqno[j] = 0;
2262         }
2263
2264         return 0;
2265 }
2266
2267 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2268 {
2269         struct drm_i915_private *dev_priv = dev->dev_private;
2270         int ret;
2271
2272         if (seqno == 0)
2273                 return -EINVAL;
2274
2275         /* HWS page needs to be set less than what we
2276          * will inject to ring
2277          */
2278         ret = i915_gem_init_seqno(dev, seqno - 1);
2279         if (ret)
2280                 return ret;
2281
2282         /* Carefully set the last_seqno value so that wrap
2283          * detection still works
2284          */
2285         dev_priv->next_seqno = seqno;
2286         dev_priv->last_seqno = seqno - 1;
2287         if (dev_priv->last_seqno == 0)
2288                 dev_priv->last_seqno--;
2289
2290         return 0;
2291 }
2292
2293 int
2294 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2295 {
2296         struct drm_i915_private *dev_priv = dev->dev_private;
2297
2298         /* reserve 0 for non-seqno */
2299         if (dev_priv->next_seqno == 0) {
2300                 int ret = i915_gem_init_seqno(dev, 0);
2301                 if (ret)
2302                         return ret;
2303
2304                 dev_priv->next_seqno = 1;
2305         }
2306
2307         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2308         return 0;
2309 }
2310
2311 int __i915_add_request(struct intel_engine_cs *ring,
2312                        struct drm_file *file,
2313                        struct drm_i915_gem_object *obj,
2314                        u32 *out_seqno)
2315 {
2316         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2317         struct drm_i915_gem_request *request;
2318         u32 request_ring_position, request_start;
2319         int ret;
2320
2321         request_start = intel_ring_get_tail(ring);
2322         /*
2323          * Emit any outstanding flushes - execbuf can fail to emit the flush
2324          * after having emitted the batchbuffer command. Hence we need to fix
2325          * things up similar to emitting the lazy request. The difference here
2326          * is that the flush _must_ happen before the next request, no matter
2327          * what.
2328          */
2329         ret = intel_ring_flush_all_caches(ring);
2330         if (ret)
2331                 return ret;
2332
2333         request = ring->preallocated_lazy_request;
2334         if (WARN_ON(request == NULL))
2335                 return -ENOMEM;
2336
2337         /* Record the position of the start of the request so that
2338          * should we detect the updated seqno part-way through the
2339          * GPU processing the request, we never over-estimate the
2340          * position of the head.
2341          */
2342         request_ring_position = intel_ring_get_tail(ring);
2343
2344         ret = ring->add_request(ring);
2345         if (ret)
2346                 return ret;
2347
2348         request->seqno = intel_ring_get_seqno(ring);
2349         request->ring = ring;
2350         request->head = request_start;
2351         request->tail = request_ring_position;
2352
2353         /* Whilst this request exists, batch_obj will be on the
2354          * active_list, and so will hold the active reference. Only when this
2355          * request is retired will the the batch_obj be moved onto the
2356          * inactive_list and lose its active reference. Hence we do not need
2357          * to explicitly hold another reference here.
2358          */
2359         request->batch_obj = obj;
2360
2361         /* Hold a reference to the current context so that we can inspect
2362          * it later in case a hangcheck error event fires.
2363          */
2364         request->ctx = ring->last_context;
2365         if (request->ctx)
2366                 i915_gem_context_reference(request->ctx);
2367
2368         request->emitted_jiffies = jiffies;
2369         list_add_tail(&request->list, &ring->request_list);
2370         request->file_priv = NULL;
2371
2372         if (file) {
2373                 struct drm_i915_file_private *file_priv = file->driver_priv;
2374
2375                 spin_lock(&file_priv->mm.lock);
2376                 request->file_priv = file_priv;
2377                 list_add_tail(&request->client_list,
2378                               &file_priv->mm.request_list);
2379                 spin_unlock(&file_priv->mm.lock);
2380         }
2381
2382         trace_i915_gem_request_add(ring, request->seqno);
2383         ring->outstanding_lazy_seqno = 0;
2384         ring->preallocated_lazy_request = NULL;
2385
2386         if (!dev_priv->ums.mm_suspended) {
2387                 i915_queue_hangcheck(ring->dev);
2388
2389                 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2390                 queue_delayed_work(dev_priv->wq,
2391                                    &dev_priv->mm.retire_work,
2392                                    round_jiffies_up_relative(HZ));
2393                 intel_mark_busy(dev_priv->dev);
2394         }
2395
2396         if (out_seqno)
2397                 *out_seqno = request->seqno;
2398         return 0;
2399 }
2400
2401 static inline void
2402 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2403 {
2404         struct drm_i915_file_private *file_priv = request->file_priv;
2405
2406         if (!file_priv)
2407                 return;
2408
2409         spin_lock(&file_priv->mm.lock);
2410         list_del(&request->client_list);
2411         request->file_priv = NULL;
2412         spin_unlock(&file_priv->mm.lock);
2413 }
2414
2415 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2416                                    const struct intel_context *ctx)
2417 {
2418         unsigned long elapsed;
2419
2420         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2421
2422         if (ctx->hang_stats.banned)
2423                 return true;
2424
2425         if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2426                 if (!i915_gem_context_is_default(ctx)) {
2427                         DRM_DEBUG("context hanging too fast, banning!\n");
2428                         return true;
2429                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2430                         if (i915_stop_ring_allow_warn(dev_priv))
2431                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2432                         return true;
2433                 }
2434         }
2435
2436         return false;
2437 }
2438
2439 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2440                                   struct intel_context *ctx,
2441                                   const bool guilty)
2442 {
2443         struct i915_ctx_hang_stats *hs;
2444
2445         if (WARN_ON(!ctx))
2446                 return;
2447
2448         hs = &ctx->hang_stats;
2449
2450         if (guilty) {
2451                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2452                 hs->batch_active++;
2453                 hs->guilty_ts = get_seconds();
2454         } else {
2455                 hs->batch_pending++;
2456         }
2457 }
2458
2459 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2460 {
2461         list_del(&request->list);
2462         i915_gem_request_remove_from_client(request);
2463
2464         if (request->ctx)
2465                 i915_gem_context_unreference(request->ctx);
2466
2467         kfree(request);
2468 }
2469
2470 struct drm_i915_gem_request *
2471 i915_gem_find_active_request(struct intel_engine_cs *ring)
2472 {
2473         struct drm_i915_gem_request *request;
2474         u32 completed_seqno;
2475
2476         completed_seqno = ring->get_seqno(ring, false);
2477
2478         list_for_each_entry(request, &ring->request_list, list) {
2479                 if (i915_seqno_passed(completed_seqno, request->seqno))
2480                         continue;
2481
2482                 return request;
2483         }
2484
2485         return NULL;
2486 }
2487
2488 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2489                                        struct intel_engine_cs *ring)
2490 {
2491         struct drm_i915_gem_request *request;
2492         bool ring_hung;
2493
2494         request = i915_gem_find_active_request(ring);
2495
2496         if (request == NULL)
2497                 return;
2498
2499         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2500
2501         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2502
2503         list_for_each_entry_continue(request, &ring->request_list, list)
2504                 i915_set_reset_status(dev_priv, request->ctx, false);
2505 }
2506
2507 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2508                                         struct intel_engine_cs *ring)
2509 {
2510         while (!list_empty(&ring->active_list)) {
2511                 struct drm_i915_gem_object *obj;
2512
2513                 obj = list_first_entry(&ring->active_list,
2514                                        struct drm_i915_gem_object,
2515                                        ring_list);
2516
2517                 i915_gem_object_move_to_inactive(obj);
2518         }
2519
2520         /*
2521          * We must free the requests after all the corresponding objects have
2522          * been moved off active lists. Which is the same order as the normal
2523          * retire_requests function does. This is important if object hold
2524          * implicit references on things like e.g. ppgtt address spaces through
2525          * the request.
2526          */
2527         while (!list_empty(&ring->request_list)) {
2528                 struct drm_i915_gem_request *request;
2529
2530                 request = list_first_entry(&ring->request_list,
2531                                            struct drm_i915_gem_request,
2532                                            list);
2533
2534                 i915_gem_free_request(request);
2535         }
2536
2537         /* These may not have been flush before the reset, do so now */
2538         kfree(ring->preallocated_lazy_request);
2539         ring->preallocated_lazy_request = NULL;
2540         ring->outstanding_lazy_seqno = 0;
2541 }
2542
2543 void i915_gem_restore_fences(struct drm_device *dev)
2544 {
2545         struct drm_i915_private *dev_priv = dev->dev_private;
2546         int i;
2547
2548         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2549                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2550
2551                 /*
2552                  * Commit delayed tiling changes if we have an object still
2553                  * attached to the fence, otherwise just clear the fence.
2554                  */
2555                 if (reg->obj) {
2556                         i915_gem_object_update_fence(reg->obj, reg,
2557                                                      reg->obj->tiling_mode);
2558                 } else {
2559                         i915_gem_write_fence(dev, i, NULL);
2560                 }
2561         }
2562 }
2563
2564 void i915_gem_reset(struct drm_device *dev)
2565 {
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         struct intel_engine_cs *ring;
2568         int i;
2569
2570         /*
2571          * Before we free the objects from the requests, we need to inspect
2572          * them for finding the guilty party. As the requests only borrow
2573          * their reference to the objects, the inspection must be done first.
2574          */
2575         for_each_ring(ring, dev_priv, i)
2576                 i915_gem_reset_ring_status(dev_priv, ring);
2577
2578         for_each_ring(ring, dev_priv, i)
2579                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2580
2581         i915_gem_context_reset(dev);
2582
2583         i915_gem_restore_fences(dev);
2584 }
2585
2586 /**
2587  * This function clears the request list as sequence numbers are passed.
2588  */
2589 void
2590 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2591 {
2592         uint32_t seqno;
2593
2594         if (list_empty(&ring->request_list))
2595                 return;
2596
2597         WARN_ON(i915_verify_lists(ring->dev));
2598
2599         seqno = ring->get_seqno(ring, true);
2600
2601         /* Move any buffers on the active list that are no longer referenced
2602          * by the ringbuffer to the flushing/inactive lists as appropriate,
2603          * before we free the context associated with the requests.
2604          */
2605         while (!list_empty(&ring->active_list)) {
2606                 struct drm_i915_gem_object *obj;
2607
2608                 obj = list_first_entry(&ring->active_list,
2609                                       struct drm_i915_gem_object,
2610                                       ring_list);
2611
2612                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2613                         break;
2614
2615                 i915_gem_object_move_to_inactive(obj);
2616         }
2617
2618
2619         while (!list_empty(&ring->request_list)) {
2620                 struct drm_i915_gem_request *request;
2621
2622                 request = list_first_entry(&ring->request_list,
2623                                            struct drm_i915_gem_request,
2624                                            list);
2625
2626                 if (!i915_seqno_passed(seqno, request->seqno))
2627                         break;
2628
2629                 trace_i915_gem_request_retire(ring, request->seqno);
2630                 /* We know the GPU must have read the request to have
2631                  * sent us the seqno + interrupt, so use the position
2632                  * of tail of the request to update the last known position
2633                  * of the GPU head.
2634                  */
2635                 ring->buffer->last_retired_head = request->tail;
2636
2637                 i915_gem_free_request(request);
2638         }
2639
2640         if (unlikely(ring->trace_irq_seqno &&
2641                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2642                 ring->irq_put(ring);
2643                 ring->trace_irq_seqno = 0;
2644         }
2645
2646         WARN_ON(i915_verify_lists(ring->dev));
2647 }
2648
2649 bool
2650 i915_gem_retire_requests(struct drm_device *dev)
2651 {
2652         struct drm_i915_private *dev_priv = dev->dev_private;
2653         struct intel_engine_cs *ring;
2654         bool idle = true;
2655         int i;
2656
2657         for_each_ring(ring, dev_priv, i) {
2658                 i915_gem_retire_requests_ring(ring);
2659                 idle &= list_empty(&ring->request_list);
2660         }
2661
2662         if (idle)
2663                 mod_delayed_work(dev_priv->wq,
2664                                    &dev_priv->mm.idle_work,
2665                                    msecs_to_jiffies(100));
2666
2667         return idle;
2668 }
2669
2670 static void
2671 i915_gem_retire_work_handler(struct work_struct *work)
2672 {
2673         struct drm_i915_private *dev_priv =
2674                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2675         struct drm_device *dev = dev_priv->dev;
2676         bool idle;
2677
2678         /* Come back later if the device is busy... */
2679         idle = false;
2680         if (mutex_trylock(&dev->struct_mutex)) {
2681                 idle = i915_gem_retire_requests(dev);
2682                 mutex_unlock(&dev->struct_mutex);
2683         }
2684         if (!idle)
2685                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2686                                    round_jiffies_up_relative(HZ));
2687 }
2688
2689 static void
2690 i915_gem_idle_work_handler(struct work_struct *work)
2691 {
2692         struct drm_i915_private *dev_priv =
2693                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2694
2695         intel_mark_idle(dev_priv->dev);
2696 }
2697
2698 /**
2699  * Ensures that an object will eventually get non-busy by flushing any required
2700  * write domains, emitting any outstanding lazy request and retiring and
2701  * completed requests.
2702  */
2703 static int
2704 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2705 {
2706         int ret;
2707
2708         if (obj->active) {
2709                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2710                 if (ret)
2711                         return ret;
2712
2713                 i915_gem_retire_requests_ring(obj->ring);
2714         }
2715
2716         return 0;
2717 }
2718
2719 /**
2720  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2721  * @DRM_IOCTL_ARGS: standard ioctl arguments
2722  *
2723  * Returns 0 if successful, else an error is returned with the remaining time in
2724  * the timeout parameter.
2725  *  -ETIME: object is still busy after timeout
2726  *  -ERESTARTSYS: signal interrupted the wait
2727  *  -ENONENT: object doesn't exist
2728  * Also possible, but rare:
2729  *  -EAGAIN: GPU wedged
2730  *  -ENOMEM: damn
2731  *  -ENODEV: Internal IRQ fail
2732  *  -E?: The add request failed
2733  *
2734  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2735  * non-zero timeout parameter the wait ioctl will wait for the given number of
2736  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2737  * without holding struct_mutex the object may become re-busied before this
2738  * function completes. A similar but shorter * race condition exists in the busy
2739  * ioctl
2740  */
2741 int
2742 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2743 {
2744         struct drm_i915_private *dev_priv = dev->dev_private;
2745         struct drm_i915_gem_wait *args = data;
2746         struct drm_i915_gem_object *obj;
2747         struct intel_engine_cs *ring = NULL;
2748         unsigned reset_counter;
2749         u32 seqno = 0;
2750         int ret = 0;
2751
2752         ret = i915_mutex_lock_interruptible(dev);
2753         if (ret)
2754                 return ret;
2755
2756         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2757         if (&obj->base == NULL) {
2758                 mutex_unlock(&dev->struct_mutex);
2759                 return -ENOENT;
2760         }
2761
2762         /* Need to make sure the object gets inactive eventually. */
2763         ret = i915_gem_object_flush_active(obj);
2764         if (ret)
2765                 goto out;
2766
2767         if (obj->active) {
2768                 seqno = obj->last_read_seqno;
2769                 ring = obj->ring;
2770         }
2771
2772         if (seqno == 0)
2773                  goto out;
2774
2775         /* Do this after OLR check to make sure we make forward progress polling
2776          * on this IOCTL with a timeout <=0 (like busy ioctl)
2777          */
2778         if (args->timeout_ns <= 0) {
2779                 ret = -ETIME;
2780                 goto out;
2781         }
2782
2783         drm_gem_object_unreference(&obj->base);
2784         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2785         mutex_unlock(&dev->struct_mutex);
2786
2787         return __wait_seqno(ring, seqno, reset_counter, true, &args->timeout_ns,
2788                             file->driver_priv);
2789
2790 out:
2791         drm_gem_object_unreference(&obj->base);
2792         mutex_unlock(&dev->struct_mutex);
2793         return ret;
2794 }
2795
2796 /**
2797  * i915_gem_object_sync - sync an object to a ring.
2798  *
2799  * @obj: object which may be in use on another ring.
2800  * @to: ring we wish to use the object on. May be NULL.
2801  *
2802  * This code is meant to abstract object synchronization with the GPU.
2803  * Calling with NULL implies synchronizing the object with the CPU
2804  * rather than a particular GPU ring.
2805  *
2806  * Returns 0 if successful, else propagates up the lower layer error.
2807  */
2808 int
2809 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2810                      struct intel_engine_cs *to)
2811 {
2812         struct intel_engine_cs *from = obj->ring;
2813         u32 seqno;
2814         int ret, idx;
2815
2816         if (from == NULL || to == from)
2817                 return 0;
2818
2819         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2820                 return i915_gem_object_wait_rendering(obj, false);
2821
2822         idx = intel_ring_sync_index(from, to);
2823
2824         seqno = obj->last_read_seqno;
2825         if (seqno <= from->semaphore.sync_seqno[idx])
2826                 return 0;
2827
2828         ret = i915_gem_check_olr(obj->ring, seqno);
2829         if (ret)
2830                 return ret;
2831
2832         trace_i915_gem_ring_sync_to(from, to, seqno);
2833         ret = to->semaphore.sync_to(to, from, seqno);
2834         if (!ret)
2835                 /* We use last_read_seqno because sync_to()
2836                  * might have just caused seqno wrap under
2837                  * the radar.
2838                  */
2839                 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2840
2841         return ret;
2842 }
2843
2844 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2845 {
2846         u32 old_write_domain, old_read_domains;
2847
2848         /* Force a pagefault for domain tracking on next user access */
2849         i915_gem_release_mmap(obj);
2850
2851         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2852                 return;
2853
2854         /* Wait for any direct GTT access to complete */
2855         mb();
2856
2857         old_read_domains = obj->base.read_domains;
2858         old_write_domain = obj->base.write_domain;
2859
2860         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2861         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2862
2863         trace_i915_gem_object_change_domain(obj,
2864                                             old_read_domains,
2865                                             old_write_domain);
2866 }
2867
2868 int i915_vma_unbind(struct i915_vma *vma)
2869 {
2870         struct drm_i915_gem_object *obj = vma->obj;
2871         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2872         int ret;
2873
2874         if (list_empty(&vma->vma_link))
2875                 return 0;
2876
2877         if (!drm_mm_node_allocated(&vma->node)) {
2878                 i915_gem_vma_destroy(vma);
2879                 return 0;
2880         }
2881
2882         if (vma->pin_count)
2883                 return -EBUSY;
2884
2885         BUG_ON(obj->pages == NULL);
2886
2887         ret = i915_gem_object_finish_gpu(obj);
2888         if (ret)
2889                 return ret;
2890         /* Continue on if we fail due to EIO, the GPU is hung so we
2891          * should be safe and we need to cleanup or else we might
2892          * cause memory corruption through use-after-free.
2893          */
2894
2895         if (i915_is_ggtt(vma->vm)) {
2896                 i915_gem_object_finish_gtt(obj);
2897
2898                 /* release the fence reg _after_ flushing */
2899                 ret = i915_gem_object_put_fence(obj);
2900                 if (ret)
2901                         return ret;
2902         }
2903
2904         trace_i915_vma_unbind(vma);
2905
2906         vma->unbind_vma(vma);
2907
2908         i915_gem_gtt_finish_object(obj);
2909
2910         list_del_init(&vma->mm_list);
2911         /* Avoid an unnecessary call to unbind on rebind. */
2912         if (i915_is_ggtt(vma->vm))
2913                 obj->map_and_fenceable = true;
2914
2915         drm_mm_remove_node(&vma->node);
2916         i915_gem_vma_destroy(vma);
2917
2918         /* Since the unbound list is global, only move to that list if
2919          * no more VMAs exist. */
2920         if (list_empty(&obj->vma_list))
2921                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2922
2923         /* And finally now the object is completely decoupled from this vma,
2924          * we can drop its hold on the backing storage and allow it to be
2925          * reaped by the shrinker.
2926          */
2927         i915_gem_object_unpin_pages(obj);
2928
2929         return 0;
2930 }
2931
2932 int i915_gpu_idle(struct drm_device *dev)
2933 {
2934         struct drm_i915_private *dev_priv = dev->dev_private;
2935         struct intel_engine_cs *ring;
2936         int ret, i;
2937
2938         /* Flush everything onto the inactive list. */
2939         for_each_ring(ring, dev_priv, i) {
2940                 ret = i915_switch_context(ring, ring->default_context);
2941                 if (ret)
2942                         return ret;
2943
2944                 ret = intel_ring_idle(ring);
2945                 if (ret)
2946                         return ret;
2947         }
2948
2949         return 0;
2950 }
2951
2952 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2953                                  struct drm_i915_gem_object *obj)
2954 {
2955         struct drm_i915_private *dev_priv = dev->dev_private;
2956         int fence_reg;
2957         int fence_pitch_shift;
2958
2959         if (INTEL_INFO(dev)->gen >= 6) {
2960                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2961                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2962         } else {
2963                 fence_reg = FENCE_REG_965_0;
2964                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2965         }
2966
2967         fence_reg += reg * 8;
2968
2969         /* To w/a incoherency with non-atomic 64-bit register updates,
2970          * we split the 64-bit update into two 32-bit writes. In order
2971          * for a partial fence not to be evaluated between writes, we
2972          * precede the update with write to turn off the fence register,
2973          * and only enable the fence as the last step.
2974          *
2975          * For extra levels of paranoia, we make sure each step lands
2976          * before applying the next step.
2977          */
2978         I915_WRITE(fence_reg, 0);
2979         POSTING_READ(fence_reg);
2980
2981         if (obj) {
2982                 u32 size = i915_gem_obj_ggtt_size(obj);
2983                 uint64_t val;
2984
2985                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2986                                  0xfffff000) << 32;
2987                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2988                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2989                 if (obj->tiling_mode == I915_TILING_Y)
2990                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2991                 val |= I965_FENCE_REG_VALID;
2992
2993                 I915_WRITE(fence_reg + 4, val >> 32);
2994                 POSTING_READ(fence_reg + 4);
2995
2996                 I915_WRITE(fence_reg + 0, val);
2997                 POSTING_READ(fence_reg);
2998         } else {
2999                 I915_WRITE(fence_reg + 4, 0);
3000                 POSTING_READ(fence_reg + 4);
3001         }
3002 }
3003
3004 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3005                                  struct drm_i915_gem_object *obj)
3006 {
3007         struct drm_i915_private *dev_priv = dev->dev_private;
3008         u32 val;
3009
3010         if (obj) {
3011                 u32 size = i915_gem_obj_ggtt_size(obj);
3012                 int pitch_val;
3013                 int tile_width;
3014
3015                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3016                      (size & -size) != size ||
3017                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3018                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3019                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3020
3021                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3022                         tile_width = 128;
3023                 else
3024                         tile_width = 512;
3025
3026                 /* Note: pitch better be a power of two tile widths */
3027                 pitch_val = obj->stride / tile_width;
3028                 pitch_val = ffs(pitch_val) - 1;
3029
3030                 val = i915_gem_obj_ggtt_offset(obj);
3031                 if (obj->tiling_mode == I915_TILING_Y)
3032                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3033                 val |= I915_FENCE_SIZE_BITS(size);
3034                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3035                 val |= I830_FENCE_REG_VALID;
3036         } else
3037                 val = 0;
3038
3039         if (reg < 8)
3040                 reg = FENCE_REG_830_0 + reg * 4;
3041         else
3042                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3043
3044         I915_WRITE(reg, val);
3045         POSTING_READ(reg);
3046 }
3047
3048 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3049                                 struct drm_i915_gem_object *obj)
3050 {
3051         struct drm_i915_private *dev_priv = dev->dev_private;
3052         uint32_t val;
3053
3054         if (obj) {
3055                 u32 size = i915_gem_obj_ggtt_size(obj);
3056                 uint32_t pitch_val;
3057
3058                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3059                      (size & -size) != size ||
3060                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3061                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3062                      i915_gem_obj_ggtt_offset(obj), size);
3063
3064                 pitch_val = obj->stride / 128;
3065                 pitch_val = ffs(pitch_val) - 1;
3066
3067                 val = i915_gem_obj_ggtt_offset(obj);
3068                 if (obj->tiling_mode == I915_TILING_Y)
3069                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3070                 val |= I830_FENCE_SIZE_BITS(size);
3071                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3072                 val |= I830_FENCE_REG_VALID;
3073         } else
3074                 val = 0;
3075
3076         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3077         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3078 }
3079
3080 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3081 {
3082         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3083 }
3084
3085 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3086                                  struct drm_i915_gem_object *obj)
3087 {
3088         struct drm_i915_private *dev_priv = dev->dev_private;
3089
3090         /* Ensure that all CPU reads are completed before installing a fence
3091          * and all writes before removing the fence.
3092          */
3093         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3094                 mb();
3095
3096         WARN(obj && (!obj->stride || !obj->tiling_mode),
3097              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3098              obj->stride, obj->tiling_mode);
3099
3100         switch (INTEL_INFO(dev)->gen) {
3101         case 8:
3102         case 7:
3103         case 6:
3104         case 5:
3105         case 4: i965_write_fence_reg(dev, reg, obj); break;
3106         case 3: i915_write_fence_reg(dev, reg, obj); break;
3107         case 2: i830_write_fence_reg(dev, reg, obj); break;
3108         default: BUG();
3109         }
3110
3111         /* And similarly be paranoid that no direct access to this region
3112          * is reordered to before the fence is installed.
3113          */
3114         if (i915_gem_object_needs_mb(obj))
3115                 mb();
3116 }
3117
3118 static inline int fence_number(struct drm_i915_private *dev_priv,
3119                                struct drm_i915_fence_reg *fence)
3120 {
3121         return fence - dev_priv->fence_regs;
3122 }
3123
3124 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3125                                          struct drm_i915_fence_reg *fence,
3126                                          bool enable)
3127 {
3128         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3129         int reg = fence_number(dev_priv, fence);
3130
3131         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3132
3133         if (enable) {
3134                 obj->fence_reg = reg;
3135                 fence->obj = obj;
3136                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3137         } else {
3138                 obj->fence_reg = I915_FENCE_REG_NONE;
3139                 fence->obj = NULL;
3140                 list_del_init(&fence->lru_list);
3141         }
3142         obj->fence_dirty = false;
3143 }
3144
3145 static int
3146 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3147 {
3148         if (obj->last_fenced_seqno) {
3149                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3150                 if (ret)
3151                         return ret;
3152
3153                 obj->last_fenced_seqno = 0;
3154         }
3155
3156         obj->fenced_gpu_access = false;
3157         return 0;
3158 }
3159
3160 int
3161 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3162 {
3163         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3164         struct drm_i915_fence_reg *fence;
3165         int ret;
3166
3167         ret = i915_gem_object_wait_fence(obj);
3168         if (ret)
3169                 return ret;
3170
3171         if (obj->fence_reg == I915_FENCE_REG_NONE)
3172                 return 0;
3173
3174         fence = &dev_priv->fence_regs[obj->fence_reg];
3175
3176         if (WARN_ON(fence->pin_count))
3177                 return -EBUSY;
3178
3179         i915_gem_object_fence_lost(obj);
3180         i915_gem_object_update_fence(obj, fence, false);
3181
3182         return 0;
3183 }
3184
3185 static struct drm_i915_fence_reg *
3186 i915_find_fence_reg(struct drm_device *dev)
3187 {
3188         struct drm_i915_private *dev_priv = dev->dev_private;
3189         struct drm_i915_fence_reg *reg, *avail;
3190         int i;
3191
3192         /* First try to find a free reg */
3193         avail = NULL;
3194         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3195                 reg = &dev_priv->fence_regs[i];
3196                 if (!reg->obj)
3197                         return reg;
3198
3199                 if (!reg->pin_count)
3200                         avail = reg;
3201         }
3202
3203         if (avail == NULL)
3204                 goto deadlock;
3205
3206         /* None available, try to steal one or wait for a user to finish */
3207         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3208                 if (reg->pin_count)
3209                         continue;
3210
3211                 return reg;
3212         }
3213
3214 deadlock:
3215         /* Wait for completion of pending flips which consume fences */
3216         if (intel_has_pending_fb_unpin(dev))
3217                 return ERR_PTR(-EAGAIN);
3218
3219         return ERR_PTR(-EDEADLK);
3220 }
3221
3222 /**
3223  * i915_gem_object_get_fence - set up fencing for an object
3224  * @obj: object to map through a fence reg
3225  *
3226  * When mapping objects through the GTT, userspace wants to be able to write
3227  * to them without having to worry about swizzling if the object is tiled.
3228  * This function walks the fence regs looking for a free one for @obj,
3229  * stealing one if it can't find any.
3230  *
3231  * It then sets up the reg based on the object's properties: address, pitch
3232  * and tiling format.
3233  *
3234  * For an untiled surface, this removes any existing fence.
3235  */
3236 int
3237 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3238 {
3239         struct drm_device *dev = obj->base.dev;
3240         struct drm_i915_private *dev_priv = dev->dev_private;
3241         bool enable = obj->tiling_mode != I915_TILING_NONE;
3242         struct drm_i915_fence_reg *reg;
3243         int ret;
3244
3245         /* Have we updated the tiling parameters upon the object and so
3246          * will need to serialise the write to the associated fence register?
3247          */
3248         if (obj->fence_dirty) {
3249                 ret = i915_gem_object_wait_fence(obj);
3250                 if (ret)
3251                         return ret;
3252         }
3253
3254         /* Just update our place in the LRU if our fence is getting reused. */
3255         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3256                 reg = &dev_priv->fence_regs[obj->fence_reg];
3257                 if (!obj->fence_dirty) {
3258                         list_move_tail(&reg->lru_list,
3259                                        &dev_priv->mm.fence_list);
3260                         return 0;
3261                 }
3262         } else if (enable) {
3263                 reg = i915_find_fence_reg(dev);
3264                 if (IS_ERR(reg))
3265                         return PTR_ERR(reg);
3266
3267                 if (reg->obj) {
3268                         struct drm_i915_gem_object *old = reg->obj;
3269
3270                         ret = i915_gem_object_wait_fence(old);
3271                         if (ret)
3272                                 return ret;
3273
3274                         i915_gem_object_fence_lost(old);
3275                 }
3276         } else
3277                 return 0;
3278
3279         i915_gem_object_update_fence(obj, reg, enable);
3280
3281         return 0;
3282 }
3283
3284 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3285                                      struct drm_mm_node *gtt_space,
3286                                      unsigned long cache_level)
3287 {
3288         struct drm_mm_node *other;
3289
3290         /* On non-LLC machines we have to be careful when putting differing
3291          * types of snoopable memory together to avoid the prefetcher
3292          * crossing memory domains and dying.
3293          */
3294         if (HAS_LLC(dev))
3295                 return true;
3296
3297         if (!drm_mm_node_allocated(gtt_space))
3298                 return true;
3299
3300         if (list_empty(&gtt_space->node_list))
3301                 return true;
3302
3303         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3304         if (other->allocated && !other->hole_follows && other->color != cache_level)
3305                 return false;
3306
3307         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3308         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3309                 return false;
3310
3311         return true;
3312 }
3313
3314 static void i915_gem_verify_gtt(struct drm_device *dev)
3315 {
3316 #if WATCH_GTT
3317         struct drm_i915_private *dev_priv = dev->dev_private;
3318         struct drm_i915_gem_object *obj;
3319         int err = 0;
3320
3321         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3322                 if (obj->gtt_space == NULL) {
3323                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3324                         err++;
3325                         continue;
3326                 }
3327
3328                 if (obj->cache_level != obj->gtt_space->color) {
3329                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3330                                i915_gem_obj_ggtt_offset(obj),
3331                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3332                                obj->cache_level,
3333                                obj->gtt_space->color);
3334                         err++;
3335                         continue;
3336                 }
3337
3338                 if (!i915_gem_valid_gtt_space(dev,
3339                                               obj->gtt_space,
3340                                               obj->cache_level)) {
3341                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3342                                i915_gem_obj_ggtt_offset(obj),
3343                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3344                                obj->cache_level);
3345                         err++;
3346                         continue;
3347                 }
3348         }
3349
3350         WARN_ON(err);
3351 #endif
3352 }
3353
3354 /**
3355  * Finds free space in the GTT aperture and binds the object there.
3356  */
3357 static struct i915_vma *
3358 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3359                            struct i915_address_space *vm,
3360                            unsigned alignment,
3361                            uint64_t flags)
3362 {
3363         struct drm_device *dev = obj->base.dev;
3364         struct drm_i915_private *dev_priv = dev->dev_private;
3365         u32 size, fence_size, fence_alignment, unfenced_alignment;
3366         unsigned long start =
3367                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3368         unsigned long end =
3369                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3370         struct i915_vma *vma;
3371         int ret;
3372
3373         fence_size = i915_gem_get_gtt_size(dev,
3374                                            obj->base.size,
3375                                            obj->tiling_mode);
3376         fence_alignment = i915_gem_get_gtt_alignment(dev,
3377                                                      obj->base.size,
3378                                                      obj->tiling_mode, true);
3379         unfenced_alignment =
3380                 i915_gem_get_gtt_alignment(dev,
3381                                            obj->base.size,
3382                                            obj->tiling_mode, false);
3383
3384         if (alignment == 0)
3385                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3386                                                 unfenced_alignment;
3387         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3388                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3389                 return ERR_PTR(-EINVAL);
3390         }
3391
3392         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3393
3394         /* If the object is bigger than the entire aperture, reject it early
3395          * before evicting everything in a vain attempt to find space.
3396          */
3397         if (obj->base.size > end) {
3398                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3399                           obj->base.size,
3400                           flags & PIN_MAPPABLE ? "mappable" : "total",
3401                           end);
3402                 return ERR_PTR(-E2BIG);
3403         }
3404
3405         ret = i915_gem_object_get_pages(obj);
3406         if (ret)
3407                 return ERR_PTR(ret);
3408
3409         i915_gem_object_pin_pages(obj);
3410
3411         vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3412         if (IS_ERR(vma))
3413                 goto err_unpin;
3414
3415 search_free:
3416         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3417                                                   size, alignment,
3418                                                   obj->cache_level,
3419                                                   start, end,
3420                                                   DRM_MM_SEARCH_DEFAULT,
3421                                                   DRM_MM_CREATE_DEFAULT);
3422         if (ret) {
3423                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3424                                                obj->cache_level,
3425                                                start, end,
3426                                                flags);
3427                 if (ret == 0)
3428                         goto search_free;
3429
3430                 goto err_free_vma;
3431         }
3432         if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3433                                               obj->cache_level))) {
3434                 ret = -EINVAL;
3435                 goto err_remove_node;
3436         }
3437
3438         ret = i915_gem_gtt_prepare_object(obj);
3439         if (ret)
3440                 goto err_remove_node;
3441
3442         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3443         list_add_tail(&vma->mm_list, &vm->inactive_list);
3444
3445         if (i915_is_ggtt(vm)) {
3446                 bool mappable, fenceable;
3447
3448                 fenceable = (vma->node.size == fence_size &&
3449                              (vma->node.start & (fence_alignment - 1)) == 0);
3450
3451                 mappable = (vma->node.start + obj->base.size <=
3452                             dev_priv->gtt.mappable_end);
3453
3454                 obj->map_and_fenceable = mappable && fenceable;
3455         }
3456
3457         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3458
3459         trace_i915_vma_bind(vma, flags);
3460         vma->bind_vma(vma, obj->cache_level,
3461                       flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3462
3463         i915_gem_verify_gtt(dev);
3464         return vma;
3465
3466 err_remove_node:
3467         drm_mm_remove_node(&vma->node);
3468 err_free_vma:
3469         i915_gem_vma_destroy(vma);
3470         vma = ERR_PTR(ret);
3471 err_unpin:
3472         i915_gem_object_unpin_pages(obj);
3473         return vma;
3474 }
3475
3476 bool
3477 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3478                         bool force)
3479 {
3480         /* If we don't have a page list set up, then we're not pinned
3481          * to GPU, and we can ignore the cache flush because it'll happen
3482          * again at bind time.
3483          */
3484         if (obj->pages == NULL)
3485                 return false;
3486
3487         /*
3488          * Stolen memory is always coherent with the GPU as it is explicitly
3489          * marked as wc by the system, or the system is cache-coherent.
3490          */
3491         if (obj->stolen)
3492                 return false;
3493
3494         /* If the GPU is snooping the contents of the CPU cache,
3495          * we do not need to manually clear the CPU cache lines.  However,
3496          * the caches are only snooped when the render cache is
3497          * flushed/invalidated.  As we always have to emit invalidations
3498          * and flushes when moving into and out of the RENDER domain, correct
3499          * snooping behaviour occurs naturally as the result of our domain
3500          * tracking.
3501          */
3502         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3503                 return false;
3504
3505         trace_i915_gem_object_clflush(obj);
3506         drm_clflush_sg(obj->pages);
3507
3508         return true;
3509 }
3510
3511 /** Flushes the GTT write domain for the object if it's dirty. */
3512 static void
3513 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3514 {
3515         uint32_t old_write_domain;
3516
3517         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3518                 return;
3519
3520         /* No actual flushing is required for the GTT write domain.  Writes
3521          * to it immediately go to main memory as far as we know, so there's
3522          * no chipset flush.  It also doesn't land in render cache.
3523          *
3524          * However, we do have to enforce the order so that all writes through
3525          * the GTT land before any writes to the device, such as updates to
3526          * the GATT itself.
3527          */
3528         wmb();
3529
3530         old_write_domain = obj->base.write_domain;
3531         obj->base.write_domain = 0;
3532
3533         trace_i915_gem_object_change_domain(obj,
3534                                             obj->base.read_domains,
3535                                             old_write_domain);
3536 }
3537
3538 /** Flushes the CPU write domain for the object if it's dirty. */
3539 static void
3540 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3541                                        bool force)
3542 {
3543         uint32_t old_write_domain;
3544
3545         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3546                 return;
3547
3548         if (i915_gem_clflush_object(obj, force))
3549                 i915_gem_chipset_flush(obj->base.dev);
3550
3551         old_write_domain = obj->base.write_domain;
3552         obj->base.write_domain = 0;
3553
3554         trace_i915_gem_object_change_domain(obj,
3555                                             obj->base.read_domains,
3556                                             old_write_domain);
3557 }
3558
3559 /**
3560  * Moves a single object to the GTT read, and possibly write domain.
3561  *
3562  * This function returns when the move is complete, including waiting on
3563  * flushes to occur.
3564  */
3565 int
3566 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3567 {
3568         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3569         uint32_t old_write_domain, old_read_domains;
3570         int ret;
3571
3572         /* Not valid to be called on unbound objects. */
3573         if (!i915_gem_obj_bound_any(obj))
3574                 return -EINVAL;
3575
3576         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3577                 return 0;
3578
3579         ret = i915_gem_object_wait_rendering(obj, !write);
3580         if (ret)
3581                 return ret;
3582
3583         i915_gem_object_retire(obj);
3584         i915_gem_object_flush_cpu_write_domain(obj, false);
3585
3586         /* Serialise direct access to this object with the barriers for
3587          * coherent writes from the GPU, by effectively invalidating the
3588          * GTT domain upon first access.
3589          */
3590         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3591                 mb();
3592
3593         old_write_domain = obj->base.write_domain;
3594         old_read_domains = obj->base.read_domains;
3595
3596         /* It should now be out of any other write domains, and we can update
3597          * the domain values for our changes.
3598          */
3599         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3600         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3601         if (write) {
3602                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3603                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3604                 obj->dirty = 1;
3605         }
3606
3607         trace_i915_gem_object_change_domain(obj,
3608                                             old_read_domains,
3609                                             old_write_domain);
3610
3611         /* And bump the LRU for this access */
3612         if (i915_gem_object_is_inactive(obj)) {
3613                 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3614                 if (vma)
3615                         list_move_tail(&vma->mm_list,
3616                                        &dev_priv->gtt.base.inactive_list);
3617
3618         }
3619
3620         return 0;
3621 }
3622
3623 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3624                                     enum i915_cache_level cache_level)
3625 {
3626         struct drm_device *dev = obj->base.dev;
3627         struct i915_vma *vma, *next;
3628         int ret;
3629
3630         if (obj->cache_level == cache_level)
3631                 return 0;
3632
3633         if (i915_gem_obj_is_pinned(obj)) {
3634                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3635                 return -EBUSY;
3636         }
3637
3638         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3639                 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3640                         ret = i915_vma_unbind(vma);
3641                         if (ret)
3642                                 return ret;
3643                 }
3644         }
3645
3646         if (i915_gem_obj_bound_any(obj)) {
3647                 ret = i915_gem_object_finish_gpu(obj);
3648                 if (ret)
3649                         return ret;
3650
3651                 i915_gem_object_finish_gtt(obj);
3652
3653                 /* Before SandyBridge, you could not use tiling or fence
3654                  * registers with snooped memory, so relinquish any fences
3655                  * currently pointing to our region in the aperture.
3656                  */
3657                 if (INTEL_INFO(dev)->gen < 6) {
3658                         ret = i915_gem_object_put_fence(obj);
3659                         if (ret)
3660                                 return ret;
3661                 }
3662
3663                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3664                         if (drm_mm_node_allocated(&vma->node))
3665                                 vma->bind_vma(vma, cache_level,
3666                                               obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3667         }
3668
3669         list_for_each_entry(vma, &obj->vma_list, vma_link)
3670                 vma->node.color = cache_level;
3671         obj->cache_level = cache_level;
3672
3673         if (cpu_write_needs_clflush(obj)) {
3674                 u32 old_read_domains, old_write_domain;
3675
3676                 /* If we're coming from LLC cached, then we haven't
3677                  * actually been tracking whether the data is in the
3678                  * CPU cache or not, since we only allow one bit set
3679                  * in obj->write_domain and have been skipping the clflushes.
3680                  * Just set it to the CPU cache for now.
3681                  */
3682                 i915_gem_object_retire(obj);
3683                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3684
3685                 old_read_domains = obj->base.read_domains;
3686                 old_write_domain = obj->base.write_domain;
3687
3688                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3689                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3690
3691                 trace_i915_gem_object_change_domain(obj,
3692                                                     old_read_domains,
3693                                                     old_write_domain);
3694         }
3695
3696         i915_gem_verify_gtt(dev);
3697         return 0;
3698 }
3699
3700 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3701                                struct drm_file *file)
3702 {
3703         struct drm_i915_gem_caching *args = data;
3704         struct drm_i915_gem_object *obj;
3705         int ret;
3706
3707         ret = i915_mutex_lock_interruptible(dev);
3708         if (ret)
3709                 return ret;
3710
3711         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3712         if (&obj->base == NULL) {
3713                 ret = -ENOENT;
3714                 goto unlock;
3715         }
3716
3717         switch (obj->cache_level) {
3718         case I915_CACHE_LLC:
3719         case I915_CACHE_L3_LLC:
3720                 args->caching = I915_CACHING_CACHED;
3721                 break;
3722
3723         case I915_CACHE_WT:
3724                 args->caching = I915_CACHING_DISPLAY;
3725                 break;
3726
3727         default:
3728                 args->caching = I915_CACHING_NONE;
3729                 break;
3730         }
3731
3732         drm_gem_object_unreference(&obj->base);
3733 unlock:
3734         mutex_unlock(&dev->struct_mutex);
3735         return ret;
3736 }
3737
3738 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3739                                struct drm_file *file)
3740 {
3741         struct drm_i915_gem_caching *args = data;
3742         struct drm_i915_gem_object *obj;
3743         enum i915_cache_level level;
3744         int ret;
3745
3746         switch (args->caching) {
3747         case I915_CACHING_NONE:
3748                 level = I915_CACHE_NONE;
3749                 break;
3750         case I915_CACHING_CACHED:
3751                 level = I915_CACHE_LLC;
3752                 break;
3753         case I915_CACHING_DISPLAY:
3754                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3755                 break;
3756         default:
3757                 return -EINVAL;
3758         }
3759
3760         ret = i915_mutex_lock_interruptible(dev);
3761         if (ret)
3762                 return ret;
3763
3764         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3765         if (&obj->base == NULL) {
3766                 ret = -ENOENT;
3767                 goto unlock;
3768         }
3769
3770         ret = i915_gem_object_set_cache_level(obj, level);
3771
3772         drm_gem_object_unreference(&obj->base);
3773 unlock:
3774         mutex_unlock(&dev->struct_mutex);
3775         return ret;
3776 }
3777
3778 static bool is_pin_display(struct drm_i915_gem_object *obj)
3779 {
3780         struct i915_vma *vma;
3781
3782         if (list_empty(&obj->vma_list))
3783                 return false;
3784
3785         vma = i915_gem_obj_to_ggtt(obj);
3786         if (!vma)
3787                 return false;
3788
3789         /* There are 3 sources that pin objects:
3790          *   1. The display engine (scanouts, sprites, cursors);
3791          *   2. Reservations for execbuffer;
3792          *   3. The user.
3793          *
3794          * We can ignore reservations as we hold the struct_mutex and
3795          * are only called outside of the reservation path.  The user
3796          * can only increment pin_count once, and so if after
3797          * subtracting the potential reference by the user, any pin_count
3798          * remains, it must be due to another use by the display engine.
3799          */
3800         return vma->pin_count - !!obj->user_pin_count;
3801 }
3802
3803 /*
3804  * Prepare buffer for display plane (scanout, cursors, etc).
3805  * Can be called from an uninterruptible phase (modesetting) and allows
3806  * any flushes to be pipelined (for pageflips).
3807  */
3808 int
3809 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3810                                      u32 alignment,
3811                                      struct intel_engine_cs *pipelined)
3812 {
3813         u32 old_read_domains, old_write_domain;
3814         bool was_pin_display;
3815         int ret;
3816
3817         if (pipelined != obj->ring) {
3818                 ret = i915_gem_object_sync(obj, pipelined);
3819                 if (ret)
3820                         return ret;
3821         }
3822
3823         /* Mark the pin_display early so that we account for the
3824          * display coherency whilst setting up the cache domains.
3825          */
3826         was_pin_display = obj->pin_display;
3827         obj->pin_display = true;
3828
3829         /* The display engine is not coherent with the LLC cache on gen6.  As
3830          * a result, we make sure that the pinning that is about to occur is
3831          * done with uncached PTEs. This is lowest common denominator for all
3832          * chipsets.
3833          *
3834          * However for gen6+, we could do better by using the GFDT bit instead
3835          * of uncaching, which would allow us to flush all the LLC-cached data
3836          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3837          */
3838         ret = i915_gem_object_set_cache_level(obj,
3839                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3840         if (ret)
3841                 goto err_unpin_display;
3842
3843         /* As the user may map the buffer once pinned in the display plane
3844          * (e.g. libkms for the bootup splash), we have to ensure that we
3845          * always use map_and_fenceable for all scanout buffers.
3846          */
3847         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3848         if (ret)
3849                 goto err_unpin_display;
3850
3851         i915_gem_object_flush_cpu_write_domain(obj, true);
3852
3853         old_write_domain = obj->base.write_domain;
3854         old_read_domains = obj->base.read_domains;
3855
3856         /* It should now be out of any other write domains, and we can update
3857          * the domain values for our changes.
3858          */
3859         obj->base.write_domain = 0;
3860         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3861
3862         trace_i915_gem_object_change_domain(obj,
3863                                             old_read_domains,
3864                                             old_write_domain);
3865
3866         return 0;
3867
3868 err_unpin_display:
3869         WARN_ON(was_pin_display != is_pin_display(obj));
3870         obj->pin_display = was_pin_display;
3871         return ret;
3872 }
3873
3874 void
3875 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3876 {
3877         i915_gem_object_ggtt_unpin(obj);
3878         obj->pin_display = is_pin_display(obj);
3879 }
3880
3881 int
3882 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3883 {
3884         int ret;
3885
3886         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3887                 return 0;
3888
3889         ret = i915_gem_object_wait_rendering(obj, false);
3890         if (ret)
3891                 return ret;
3892
3893         /* Ensure that we invalidate the GPU's caches and TLBs. */
3894         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3895         return 0;
3896 }
3897
3898 /**
3899  * Moves a single object to the CPU read, and possibly write domain.
3900  *
3901  * This function returns when the move is complete, including waiting on
3902  * flushes to occur.
3903  */
3904 int
3905 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3906 {
3907         uint32_t old_write_domain, old_read_domains;
3908         int ret;
3909
3910         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3911                 return 0;
3912
3913         ret = i915_gem_object_wait_rendering(obj, !write);
3914         if (ret)
3915                 return ret;
3916
3917         i915_gem_object_retire(obj);
3918         i915_gem_object_flush_gtt_write_domain(obj);
3919
3920         old_write_domain = obj->base.write_domain;
3921         old_read_domains = obj->base.read_domains;
3922
3923         /* Flush the CPU cache if it's still invalid. */
3924         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3925                 i915_gem_clflush_object(obj, false);
3926
3927                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3928         }
3929
3930         /* It should now be out of any other write domains, and we can update
3931          * the domain values for our changes.
3932          */
3933         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3934
3935         /* If we're writing through the CPU, then the GPU read domains will
3936          * need to be invalidated at next use.
3937          */
3938         if (write) {
3939                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3940                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3941         }
3942
3943         trace_i915_gem_object_change_domain(obj,
3944                                             old_read_domains,
3945                                             old_write_domain);
3946
3947         return 0;
3948 }
3949
3950 /* Throttle our rendering by waiting until the ring has completed our requests
3951  * emitted over 20 msec ago.
3952  *
3953  * Note that if we were to use the current jiffies each time around the loop,
3954  * we wouldn't escape the function with any frames outstanding if the time to
3955  * render a frame was over 20ms.
3956  *
3957  * This should get us reasonable parallelism between CPU and GPU but also
3958  * relatively low latency when blocking on a particular request to finish.
3959  */
3960 static int
3961 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3962 {
3963         struct drm_i915_private *dev_priv = dev->dev_private;
3964         struct drm_i915_file_private *file_priv = file->driver_priv;
3965         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3966         struct drm_i915_gem_request *request;
3967         struct intel_engine_cs *ring = NULL;
3968         unsigned reset_counter;
3969         u32 seqno = 0;
3970         int ret;
3971
3972         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3973         if (ret)
3974                 return ret;
3975
3976         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3977         if (ret)
3978                 return ret;
3979
3980         spin_lock(&file_priv->mm.lock);
3981         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3982                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3983                         break;
3984
3985                 ring = request->ring;
3986                 seqno = request->seqno;
3987         }
3988         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3989         spin_unlock(&file_priv->mm.lock);
3990
3991         if (seqno == 0)
3992                 return 0;
3993
3994         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
3995         if (ret == 0)
3996                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3997
3998         return ret;
3999 }
4000
4001 static bool
4002 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4003 {
4004         struct drm_i915_gem_object *obj = vma->obj;
4005
4006         if (alignment &&
4007             vma->node.start & (alignment - 1))
4008                 return true;
4009
4010         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4011                 return true;
4012
4013         if (flags & PIN_OFFSET_BIAS &&
4014             vma->node.start < (flags & PIN_OFFSET_MASK))
4015                 return true;
4016
4017         return false;
4018 }
4019
4020 int
4021 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4022                     struct i915_address_space *vm,
4023                     uint32_t alignment,
4024                     uint64_t flags)
4025 {
4026         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4027         struct i915_vma *vma;
4028         int ret;
4029
4030         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4031                 return -ENODEV;
4032
4033         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4034                 return -EINVAL;
4035
4036         vma = i915_gem_obj_to_vma(obj, vm);
4037         if (vma) {
4038                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4039                         return -EBUSY;
4040
4041                 if (i915_vma_misplaced(vma, alignment, flags)) {
4042                         WARN(vma->pin_count,
4043                              "bo is already pinned with incorrect alignment:"
4044                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4045                              " obj->map_and_fenceable=%d\n",
4046                              i915_gem_obj_offset(obj, vm), alignment,
4047                              !!(flags & PIN_MAPPABLE),
4048                              obj->map_and_fenceable);
4049                         ret = i915_vma_unbind(vma);
4050                         if (ret)
4051                                 return ret;
4052
4053                         vma = NULL;
4054                 }
4055         }
4056
4057         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4058                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4059                 if (IS_ERR(vma))
4060                         return PTR_ERR(vma);
4061         }
4062
4063         if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
4064                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4065
4066         vma->pin_count++;
4067         if (flags & PIN_MAPPABLE)
4068                 obj->pin_mappable |= true;
4069
4070         return 0;
4071 }
4072
4073 void
4074 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4075 {
4076         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4077
4078         BUG_ON(!vma);
4079         BUG_ON(vma->pin_count == 0);
4080         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4081
4082         if (--vma->pin_count == 0)
4083                 obj->pin_mappable = false;
4084 }
4085
4086 bool
4087 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4088 {
4089         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4090                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4091                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4092
4093                 WARN_ON(!ggtt_vma ||
4094                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4095                         ggtt_vma->pin_count);
4096                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4097                 return true;
4098         } else
4099                 return false;
4100 }
4101
4102 void
4103 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4104 {
4105         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4106                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4107                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4108                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4109         }
4110 }
4111
4112 int
4113 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4114                    struct drm_file *file)
4115 {
4116         struct drm_i915_gem_pin *args = data;
4117         struct drm_i915_gem_object *obj;
4118         int ret;
4119
4120         if (INTEL_INFO(dev)->gen >= 6)
4121                 return -ENODEV;
4122
4123         ret = i915_mutex_lock_interruptible(dev);
4124         if (ret)
4125                 return ret;
4126
4127         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4128         if (&obj->base == NULL) {
4129                 ret = -ENOENT;
4130                 goto unlock;
4131         }
4132
4133         if (obj->madv != I915_MADV_WILLNEED) {
4134                 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4135                 ret = -EFAULT;
4136                 goto out;
4137         }
4138
4139         if (obj->pin_filp != NULL && obj->pin_filp != file) {
4140                 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4141                           args->handle);
4142                 ret = -EINVAL;
4143                 goto out;
4144         }
4145
4146         if (obj->user_pin_count == ULONG_MAX) {
4147                 ret = -EBUSY;
4148                 goto out;
4149         }
4150
4151         if (obj->user_pin_count == 0) {
4152                 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4153                 if (ret)
4154                         goto out;
4155         }
4156
4157         obj->user_pin_count++;
4158         obj->pin_filp = file;
4159
4160         args->offset = i915_gem_obj_ggtt_offset(obj);
4161 out:
4162         drm_gem_object_unreference(&obj->base);
4163 unlock:
4164         mutex_unlock(&dev->struct_mutex);
4165         return ret;
4166 }
4167
4168 int
4169 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4170                      struct drm_file *file)
4171 {
4172         struct drm_i915_gem_pin *args = data;
4173         struct drm_i915_gem_object *obj;
4174         int ret;
4175
4176         ret = i915_mutex_lock_interruptible(dev);
4177         if (ret)
4178                 return ret;
4179
4180         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4181         if (&obj->base == NULL) {
4182                 ret = -ENOENT;
4183                 goto unlock;
4184         }
4185
4186         if (obj->pin_filp != file) {
4187                 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4188                           args->handle);
4189                 ret = -EINVAL;
4190                 goto out;
4191         }
4192         obj->user_pin_count--;
4193         if (obj->user_pin_count == 0) {
4194                 obj->pin_filp = NULL;
4195                 i915_gem_object_ggtt_unpin(obj);
4196         }
4197
4198 out:
4199         drm_gem_object_unreference(&obj->base);
4200 unlock:
4201         mutex_unlock(&dev->struct_mutex);
4202         return ret;
4203 }
4204
4205 int
4206 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4207                     struct drm_file *file)
4208 {
4209         struct drm_i915_gem_busy *args = data;
4210         struct drm_i915_gem_object *obj;
4211         int ret;
4212
4213         ret = i915_mutex_lock_interruptible(dev);
4214         if (ret)
4215                 return ret;
4216
4217         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4218         if (&obj->base == NULL) {
4219                 ret = -ENOENT;
4220                 goto unlock;
4221         }
4222
4223         /* Count all active objects as busy, even if they are currently not used
4224          * by the gpu. Users of this interface expect objects to eventually
4225          * become non-busy without any further actions, therefore emit any
4226          * necessary flushes here.
4227          */
4228         ret = i915_gem_object_flush_active(obj);
4229
4230         args->busy = obj->active;
4231         if (obj->ring) {
4232                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4233                 args->busy |= intel_ring_flag(obj->ring) << 16;
4234         }
4235
4236         drm_gem_object_unreference(&obj->base);
4237 unlock:
4238         mutex_unlock(&dev->struct_mutex);
4239         return ret;
4240 }
4241
4242 int
4243 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4244                         struct drm_file *file_priv)
4245 {
4246         return i915_gem_ring_throttle(dev, file_priv);
4247 }
4248
4249 int
4250 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4251                        struct drm_file *file_priv)
4252 {
4253         struct drm_i915_gem_madvise *args = data;
4254         struct drm_i915_gem_object *obj;
4255         int ret;
4256
4257         switch (args->madv) {
4258         case I915_MADV_DONTNEED:
4259         case I915_MADV_WILLNEED:
4260             break;
4261         default:
4262             return -EINVAL;
4263         }
4264
4265         ret = i915_mutex_lock_interruptible(dev);
4266         if (ret)
4267                 return ret;
4268
4269         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4270         if (&obj->base == NULL) {
4271                 ret = -ENOENT;
4272                 goto unlock;
4273         }
4274
4275         if (i915_gem_obj_is_pinned(obj)) {
4276                 ret = -EINVAL;
4277                 goto out;
4278         }
4279
4280         if (obj->madv != __I915_MADV_PURGED)
4281                 obj->madv = args->madv;
4282
4283         /* if the object is no longer attached, discard its backing storage */
4284         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4285                 i915_gem_object_truncate(obj);
4286
4287         args->retained = obj->madv != __I915_MADV_PURGED;
4288
4289 out:
4290         drm_gem_object_unreference(&obj->base);
4291 unlock:
4292         mutex_unlock(&dev->struct_mutex);
4293         return ret;
4294 }
4295
4296 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4297                           const struct drm_i915_gem_object_ops *ops)
4298 {
4299         INIT_LIST_HEAD(&obj->global_list);
4300         INIT_LIST_HEAD(&obj->ring_list);
4301         INIT_LIST_HEAD(&obj->obj_exec_link);
4302         INIT_LIST_HEAD(&obj->vma_list);
4303
4304         obj->ops = ops;
4305
4306         obj->fence_reg = I915_FENCE_REG_NONE;
4307         obj->madv = I915_MADV_WILLNEED;
4308         /* Avoid an unnecessary call to unbind on the first bind. */
4309         obj->map_and_fenceable = true;
4310
4311         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4312 }
4313
4314 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4315         .get_pages = i915_gem_object_get_pages_gtt,
4316         .put_pages = i915_gem_object_put_pages_gtt,
4317 };
4318
4319 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4320                                                   size_t size)
4321 {
4322         struct drm_i915_gem_object *obj;
4323         struct address_space *mapping;
4324         gfp_t mask;
4325
4326         obj = i915_gem_object_alloc(dev);
4327         if (obj == NULL)
4328                 return NULL;
4329
4330         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4331                 i915_gem_object_free(obj);
4332                 return NULL;
4333         }
4334
4335         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4336         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4337                 /* 965gm cannot relocate objects above 4GiB. */
4338                 mask &= ~__GFP_HIGHMEM;
4339                 mask |= __GFP_DMA32;
4340         }
4341
4342         mapping = file_inode(obj->base.filp)->i_mapping;
4343         mapping_set_gfp_mask(mapping, mask);
4344
4345         i915_gem_object_init(obj, &i915_gem_object_ops);
4346
4347         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4348         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4349
4350         if (HAS_LLC(dev)) {
4351                 /* On some devices, we can have the GPU use the LLC (the CPU
4352                  * cache) for about a 10% performance improvement
4353                  * compared to uncached.  Graphics requests other than
4354                  * display scanout are coherent with the CPU in
4355                  * accessing this cache.  This means in this mode we
4356                  * don't need to clflush on the CPU side, and on the
4357                  * GPU side we only need to flush internal caches to
4358                  * get data visible to the CPU.
4359                  *
4360                  * However, we maintain the display planes as UC, and so
4361                  * need to rebind when first used as such.
4362                  */
4363                 obj->cache_level = I915_CACHE_LLC;
4364         } else
4365                 obj->cache_level = I915_CACHE_NONE;
4366
4367         trace_i915_gem_object_create(obj);
4368
4369         return obj;
4370 }
4371
4372 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4373 {
4374         /* If we are the last user of the backing storage (be it shmemfs
4375          * pages or stolen etc), we know that the pages are going to be
4376          * immediately released. In this case, we can then skip copying
4377          * back the contents from the GPU.
4378          */
4379
4380         if (obj->madv != I915_MADV_WILLNEED)
4381                 return false;
4382
4383         if (obj->base.filp == NULL)
4384                 return true;
4385
4386         /* At first glance, this looks racy, but then again so would be
4387          * userspace racing mmap against close. However, the first external
4388          * reference to the filp can only be obtained through the
4389          * i915_gem_mmap_ioctl() which safeguards us against the user
4390          * acquiring such a reference whilst we are in the middle of
4391          * freeing the object.
4392          */
4393         return atomic_long_read(&obj->base.filp->f_count) == 1;
4394 }
4395
4396 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4397 {
4398         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4399         struct drm_device *dev = obj->base.dev;
4400         struct drm_i915_private *dev_priv = dev->dev_private;
4401         struct i915_vma *vma, *next;
4402
4403         intel_runtime_pm_get(dev_priv);
4404
4405         trace_i915_gem_object_destroy(obj);
4406
4407         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4408                 int ret;
4409
4410                 vma->pin_count = 0;
4411                 ret = i915_vma_unbind(vma);
4412                 if (WARN_ON(ret == -ERESTARTSYS)) {
4413                         bool was_interruptible;
4414
4415                         was_interruptible = dev_priv->mm.interruptible;
4416                         dev_priv->mm.interruptible = false;
4417
4418                         WARN_ON(i915_vma_unbind(vma));
4419
4420                         dev_priv->mm.interruptible = was_interruptible;
4421                 }
4422         }
4423
4424         i915_gem_object_detach_phys(obj);
4425
4426         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4427          * before progressing. */
4428         if (obj->stolen)
4429                 i915_gem_object_unpin_pages(obj);
4430
4431         if (WARN_ON(obj->pages_pin_count))
4432                 obj->pages_pin_count = 0;
4433         if (discard_backing_storage(obj))
4434                 obj->madv = I915_MADV_DONTNEED;
4435         i915_gem_object_put_pages(obj);
4436         i915_gem_object_free_mmap_offset(obj);
4437         i915_gem_object_release_stolen(obj);
4438
4439         BUG_ON(obj->pages);
4440
4441         if (obj->base.import_attach)
4442                 drm_prime_gem_destroy(&obj->base, NULL);
4443
4444         if (obj->ops->release)
4445                 obj->ops->release(obj);
4446
4447         drm_gem_object_release(&obj->base);
4448         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4449
4450         kfree(obj->bit_17);
4451         i915_gem_object_free(obj);
4452
4453         intel_runtime_pm_put(dev_priv);
4454 }
4455
4456 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4457                                      struct i915_address_space *vm)
4458 {
4459         struct i915_vma *vma;
4460         list_for_each_entry(vma, &obj->vma_list, vma_link)
4461                 if (vma->vm == vm)
4462                         return vma;
4463
4464         return NULL;
4465 }
4466
4467 void i915_gem_vma_destroy(struct i915_vma *vma)
4468 {
4469         WARN_ON(vma->node.allocated);
4470
4471         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4472         if (!list_empty(&vma->exec_list))
4473                 return;
4474
4475         list_del(&vma->vma_link);
4476
4477         kfree(vma);
4478 }
4479
4480 static void
4481 i915_gem_stop_ringbuffers(struct drm_device *dev)
4482 {
4483         struct drm_i915_private *dev_priv = dev->dev_private;
4484         struct intel_engine_cs *ring;
4485         int i;
4486
4487         for_each_ring(ring, dev_priv, i)
4488                 intel_stop_ring_buffer(ring);
4489 }
4490
4491 int
4492 i915_gem_suspend(struct drm_device *dev)
4493 {
4494         struct drm_i915_private *dev_priv = dev->dev_private;
4495         int ret = 0;
4496
4497         mutex_lock(&dev->struct_mutex);
4498         if (dev_priv->ums.mm_suspended)
4499                 goto err;
4500
4501         ret = i915_gpu_idle(dev);
4502         if (ret)
4503                 goto err;
4504
4505         i915_gem_retire_requests(dev);
4506
4507         /* Under UMS, be paranoid and evict. */
4508         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4509                 i915_gem_evict_everything(dev);
4510
4511         i915_kernel_lost_context(dev);
4512         i915_gem_stop_ringbuffers(dev);
4513
4514         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4515          * We need to replace this with a semaphore, or something.
4516          * And not confound ums.mm_suspended!
4517          */
4518         dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4519                                                              DRIVER_MODESET);
4520         mutex_unlock(&dev->struct_mutex);
4521
4522         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4523         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4524         cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4525
4526         return 0;
4527
4528 err:
4529         mutex_unlock(&dev->struct_mutex);
4530         return ret;
4531 }
4532
4533 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4534 {
4535         struct drm_device *dev = ring->dev;
4536         struct drm_i915_private *dev_priv = dev->dev_private;
4537         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4538         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4539         int i, ret;
4540
4541         if (!HAS_L3_DPF(dev) || !remap_info)
4542                 return 0;
4543
4544         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4545         if (ret)
4546                 return ret;
4547
4548         /*
4549          * Note: We do not worry about the concurrent register cacheline hang
4550          * here because no other code should access these registers other than
4551          * at initialization time.
4552          */
4553         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4554                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4555                 intel_ring_emit(ring, reg_base + i);
4556                 intel_ring_emit(ring, remap_info[i/4]);
4557         }
4558
4559         intel_ring_advance(ring);
4560
4561         return ret;
4562 }
4563
4564 void i915_gem_init_swizzling(struct drm_device *dev)
4565 {
4566         struct drm_i915_private *dev_priv = dev->dev_private;
4567
4568         if (INTEL_INFO(dev)->gen < 5 ||
4569             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4570                 return;
4571
4572         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4573                                  DISP_TILE_SURFACE_SWIZZLING);
4574
4575         if (IS_GEN5(dev))
4576                 return;
4577
4578         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4579         if (IS_GEN6(dev))
4580                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4581         else if (IS_GEN7(dev))
4582                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4583         else if (IS_GEN8(dev))
4584                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4585         else
4586                 BUG();
4587 }
4588
4589 static bool
4590 intel_enable_blt(struct drm_device *dev)
4591 {
4592         if (!HAS_BLT(dev))
4593                 return false;
4594
4595         /* The blitter was dysfunctional on early prototypes */
4596         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4597                 DRM_INFO("BLT not supported on this pre-production hardware;"
4598                          " graphics performance will be degraded.\n");
4599                 return false;
4600         }
4601
4602         return true;
4603 }
4604
4605 static int i915_gem_init_rings(struct drm_device *dev)
4606 {
4607         struct drm_i915_private *dev_priv = dev->dev_private;
4608         int ret;
4609
4610         ret = intel_init_render_ring_buffer(dev);
4611         if (ret)
4612                 return ret;
4613
4614         if (HAS_BSD(dev)) {
4615                 ret = intel_init_bsd_ring_buffer(dev);
4616                 if (ret)
4617                         goto cleanup_render_ring;
4618         }
4619
4620         if (intel_enable_blt(dev)) {
4621                 ret = intel_init_blt_ring_buffer(dev);
4622                 if (ret)
4623                         goto cleanup_bsd_ring;
4624         }
4625
4626         if (HAS_VEBOX(dev)) {
4627                 ret = intel_init_vebox_ring_buffer(dev);
4628                 if (ret)
4629                         goto cleanup_blt_ring;
4630         }
4631
4632         if (HAS_BSD2(dev)) {
4633                 ret = intel_init_bsd2_ring_buffer(dev);
4634                 if (ret)
4635                         goto cleanup_vebox_ring;
4636         }
4637
4638         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4639         if (ret)
4640                 goto cleanup_bsd2_ring;
4641
4642         return 0;
4643
4644 cleanup_bsd2_ring:
4645         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4646 cleanup_vebox_ring:
4647         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4648 cleanup_blt_ring:
4649         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4650 cleanup_bsd_ring:
4651         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4652 cleanup_render_ring:
4653         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4654
4655         return ret;
4656 }
4657
4658 int
4659 i915_gem_init_hw(struct drm_device *dev)
4660 {
4661         struct drm_i915_private *dev_priv = dev->dev_private;
4662         int ret, i;
4663
4664         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4665                 return -EIO;
4666
4667         if (dev_priv->ellc_size)
4668                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4669
4670         if (IS_HASWELL(dev))
4671                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4672                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4673
4674         if (HAS_PCH_NOP(dev)) {
4675                 if (IS_IVYBRIDGE(dev)) {
4676                         u32 temp = I915_READ(GEN7_MSG_CTL);
4677                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4678                         I915_WRITE(GEN7_MSG_CTL, temp);
4679                 } else if (INTEL_INFO(dev)->gen >= 7) {
4680                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4681                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4682                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4683                 }
4684         }
4685
4686         i915_gem_init_swizzling(dev);
4687
4688         ret = i915_gem_init_rings(dev);
4689         if (ret)
4690                 return ret;
4691
4692         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4693                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4694
4695         /*
4696          * XXX: Contexts should only be initialized once. Doing a switch to the
4697          * default context switch however is something we'd like to do after
4698          * reset or thaw (the latter may not actually be necessary for HW, but
4699          * goes with our code better). Context switching requires rings (for
4700          * the do_switch), but before enabling PPGTT. So don't move this.
4701          */
4702         ret = i915_gem_context_enable(dev_priv);
4703         if (ret && ret != -EIO) {
4704                 DRM_ERROR("Context enable failed %d\n", ret);
4705                 i915_gem_cleanup_ringbuffer(dev);
4706         }
4707
4708         return ret;
4709 }
4710
4711 int i915_gem_init(struct drm_device *dev)
4712 {
4713         struct drm_i915_private *dev_priv = dev->dev_private;
4714         int ret;
4715
4716         mutex_lock(&dev->struct_mutex);
4717
4718         if (IS_VALLEYVIEW(dev)) {
4719                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4720                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4721                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4722                               VLV_GTLC_ALLOWWAKEACK), 10))
4723                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4724         }
4725
4726         i915_gem_init_userptr(dev);
4727         i915_gem_init_global_gtt(dev);
4728
4729         ret = i915_gem_context_init(dev);
4730         if (ret) {
4731                 mutex_unlock(&dev->struct_mutex);
4732                 return ret;
4733         }
4734
4735         ret = i915_gem_init_hw(dev);
4736         if (ret == -EIO) {
4737                 /* Allow ring initialisation to fail by marking the GPU as
4738                  * wedged. But we only want to do this where the GPU is angry,
4739                  * for all other failure, such as an allocation failure, bail.
4740                  */
4741                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4742                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4743                 ret = 0;
4744         }
4745         mutex_unlock(&dev->struct_mutex);
4746
4747         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4748         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4749                 dev_priv->dri1.allow_batchbuffer = 1;
4750         return ret;
4751 }
4752
4753 void
4754 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4755 {
4756         struct drm_i915_private *dev_priv = dev->dev_private;
4757         struct intel_engine_cs *ring;
4758         int i;
4759
4760         for_each_ring(ring, dev_priv, i)
4761                 intel_cleanup_ring_buffer(ring);
4762 }
4763
4764 int
4765 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4766                        struct drm_file *file_priv)
4767 {
4768         struct drm_i915_private *dev_priv = dev->dev_private;
4769         int ret;
4770
4771         if (drm_core_check_feature(dev, DRIVER_MODESET))
4772                 return 0;
4773
4774         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4775                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4776                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4777         }
4778
4779         mutex_lock(&dev->struct_mutex);
4780         dev_priv->ums.mm_suspended = 0;
4781
4782         ret = i915_gem_init_hw(dev);
4783         if (ret != 0) {
4784                 mutex_unlock(&dev->struct_mutex);
4785                 return ret;
4786         }
4787
4788         BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4789
4790         ret = drm_irq_install(dev, dev->pdev->irq);
4791         if (ret)
4792                 goto cleanup_ringbuffer;
4793         mutex_unlock(&dev->struct_mutex);
4794
4795         return 0;
4796
4797 cleanup_ringbuffer:
4798         i915_gem_cleanup_ringbuffer(dev);
4799         dev_priv->ums.mm_suspended = 1;
4800         mutex_unlock(&dev->struct_mutex);
4801
4802         return ret;
4803 }
4804
4805 int
4806 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4807                        struct drm_file *file_priv)
4808 {
4809         if (drm_core_check_feature(dev, DRIVER_MODESET))
4810                 return 0;
4811
4812         mutex_lock(&dev->struct_mutex);
4813         drm_irq_uninstall(dev);
4814         mutex_unlock(&dev->struct_mutex);
4815
4816         return i915_gem_suspend(dev);
4817 }
4818
4819 void
4820 i915_gem_lastclose(struct drm_device *dev)
4821 {
4822         int ret;
4823
4824         if (drm_core_check_feature(dev, DRIVER_MODESET))
4825                 return;
4826
4827         ret = i915_gem_suspend(dev);
4828         if (ret)
4829                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4830 }
4831
4832 static void
4833 init_ring_lists(struct intel_engine_cs *ring)
4834 {
4835         INIT_LIST_HEAD(&ring->active_list);
4836         INIT_LIST_HEAD(&ring->request_list);
4837 }
4838
4839 void i915_init_vm(struct drm_i915_private *dev_priv,
4840                   struct i915_address_space *vm)
4841 {
4842         if (!i915_is_ggtt(vm))
4843                 drm_mm_init(&vm->mm, vm->start, vm->total);
4844         vm->dev = dev_priv->dev;
4845         INIT_LIST_HEAD(&vm->active_list);
4846         INIT_LIST_HEAD(&vm->inactive_list);
4847         INIT_LIST_HEAD(&vm->global_link);
4848         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4849 }
4850
4851 void
4852 i915_gem_load(struct drm_device *dev)
4853 {
4854         struct drm_i915_private *dev_priv = dev->dev_private;
4855         int i;
4856
4857         dev_priv->slab =
4858                 kmem_cache_create("i915_gem_object",
4859                                   sizeof(struct drm_i915_gem_object), 0,
4860                                   SLAB_HWCACHE_ALIGN,
4861                                   NULL);
4862
4863         INIT_LIST_HEAD(&dev_priv->vm_list);
4864         i915_init_vm(dev_priv, &dev_priv->gtt.base);
4865
4866         INIT_LIST_HEAD(&dev_priv->context_list);
4867         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4868         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4869         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4870         for (i = 0; i < I915_NUM_RINGS; i++)
4871                 init_ring_lists(&dev_priv->ring[i]);
4872         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4873                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4874         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4875                           i915_gem_retire_work_handler);
4876         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4877                           i915_gem_idle_work_handler);
4878         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4879
4880         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4881         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4882                 I915_WRITE(MI_ARB_STATE,
4883                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4884         }
4885
4886         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4887
4888         /* Old X drivers will take 0-2 for front, back, depth buffers */
4889         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4890                 dev_priv->fence_reg_start = 3;
4891
4892         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4893                 dev_priv->num_fence_regs = 32;
4894         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4895                 dev_priv->num_fence_regs = 16;
4896         else
4897                 dev_priv->num_fence_regs = 8;
4898
4899         /* Initialize fence registers to zero */
4900         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4901         i915_gem_restore_fences(dev);
4902
4903         i915_gem_detect_bit_6_swizzle(dev);
4904         init_waitqueue_head(&dev_priv->pending_flip_queue);
4905
4906         dev_priv->mm.interruptible = true;
4907
4908         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4909         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4910         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4911         register_shrinker(&dev_priv->mm.shrinker);
4912
4913         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4914         register_oom_notifier(&dev_priv->mm.oom_notifier);
4915 }
4916
4917 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4918 {
4919         struct drm_i915_file_private *file_priv = file->driver_priv;
4920
4921         cancel_delayed_work_sync(&file_priv->mm.idle_work);
4922
4923         /* Clean up our request list when the client is going away, so that
4924          * later retire_requests won't dereference our soon-to-be-gone
4925          * file_priv.
4926          */
4927         spin_lock(&file_priv->mm.lock);
4928         while (!list_empty(&file_priv->mm.request_list)) {
4929                 struct drm_i915_gem_request *request;
4930
4931                 request = list_first_entry(&file_priv->mm.request_list,
4932                                            struct drm_i915_gem_request,
4933                                            client_list);
4934                 list_del(&request->client_list);
4935                 request->file_priv = NULL;
4936         }
4937         spin_unlock(&file_priv->mm.lock);
4938 }
4939
4940 static void
4941 i915_gem_file_idle_work_handler(struct work_struct *work)
4942 {
4943         struct drm_i915_file_private *file_priv =
4944                 container_of(work, typeof(*file_priv), mm.idle_work.work);
4945
4946         atomic_set(&file_priv->rps_wait_boost, false);
4947 }
4948
4949 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4950 {
4951         struct drm_i915_file_private *file_priv;
4952         int ret;
4953
4954         DRM_DEBUG_DRIVER("\n");
4955
4956         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4957         if (!file_priv)
4958                 return -ENOMEM;
4959
4960         file->driver_priv = file_priv;
4961         file_priv->dev_priv = dev->dev_private;
4962         file_priv->file = file;
4963
4964         spin_lock_init(&file_priv->mm.lock);
4965         INIT_LIST_HEAD(&file_priv->mm.request_list);
4966         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4967                           i915_gem_file_idle_work_handler);
4968
4969         ret = i915_gem_context_open(dev, file);
4970         if (ret)
4971                 kfree(file_priv);
4972
4973         return ret;
4974 }
4975
4976 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4977 {
4978         if (!mutex_is_locked(mutex))
4979                 return false;
4980
4981 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4982         return mutex->owner == task;
4983 #else
4984         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4985         return false;
4986 #endif
4987 }
4988
4989 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
4990 {
4991         if (!mutex_trylock(&dev->struct_mutex)) {
4992                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4993                         return false;
4994
4995                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
4996                         return false;
4997
4998                 *unlock = false;
4999         } else
5000                 *unlock = true;
5001
5002         return true;
5003 }
5004
5005 static int num_vma_bound(struct drm_i915_gem_object *obj)
5006 {
5007         struct i915_vma *vma;
5008         int count = 0;
5009
5010         list_for_each_entry(vma, &obj->vma_list, vma_link)
5011                 if (drm_mm_node_allocated(&vma->node))
5012                         count++;
5013
5014         return count;
5015 }
5016
5017 static unsigned long
5018 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5019 {
5020         struct drm_i915_private *dev_priv =
5021                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5022         struct drm_device *dev = dev_priv->dev;
5023         struct drm_i915_gem_object *obj;
5024         unsigned long count;
5025         bool unlock;
5026
5027         if (!i915_gem_shrinker_lock(dev, &unlock))
5028                 return 0;
5029
5030         count = 0;
5031         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5032                 if (obj->pages_pin_count == 0)
5033                         count += obj->base.size >> PAGE_SHIFT;
5034
5035         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5036                 if (!i915_gem_obj_is_pinned(obj) &&
5037                     obj->pages_pin_count == num_vma_bound(obj))
5038                         count += obj->base.size >> PAGE_SHIFT;
5039         }
5040
5041         if (unlock)
5042                 mutex_unlock(&dev->struct_mutex);
5043
5044         return count;
5045 }
5046
5047 /* All the new VM stuff */
5048 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5049                                   struct i915_address_space *vm)
5050 {
5051         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5052         struct i915_vma *vma;
5053
5054         if (!dev_priv->mm.aliasing_ppgtt ||
5055             vm == &dev_priv->mm.aliasing_ppgtt->base)
5056                 vm = &dev_priv->gtt.base;
5057
5058         BUG_ON(list_empty(&o->vma_list));
5059         list_for_each_entry(vma, &o->vma_list, vma_link) {
5060                 if (vma->vm == vm)
5061                         return vma->node.start;
5062
5063         }
5064         return -1;
5065 }
5066
5067 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5068                         struct i915_address_space *vm)
5069 {
5070         struct i915_vma *vma;
5071
5072         list_for_each_entry(vma, &o->vma_list, vma_link)
5073                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5074                         return true;
5075
5076         return false;
5077 }
5078
5079 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5080 {
5081         struct i915_vma *vma;
5082
5083         list_for_each_entry(vma, &o->vma_list, vma_link)
5084                 if (drm_mm_node_allocated(&vma->node))
5085                         return true;
5086
5087         return false;
5088 }
5089
5090 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5091                                 struct i915_address_space *vm)
5092 {
5093         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5094         struct i915_vma *vma;
5095
5096         if (!dev_priv->mm.aliasing_ppgtt ||
5097             vm == &dev_priv->mm.aliasing_ppgtt->base)
5098                 vm = &dev_priv->gtt.base;
5099
5100         BUG_ON(list_empty(&o->vma_list));
5101
5102         list_for_each_entry(vma, &o->vma_list, vma_link)
5103                 if (vma->vm == vm)
5104                         return vma->node.size;
5105
5106         return 0;
5107 }
5108
5109 static unsigned long
5110 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5111 {
5112         struct drm_i915_private *dev_priv =
5113                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5114         struct drm_device *dev = dev_priv->dev;
5115         unsigned long freed;
5116         bool unlock;
5117
5118         if (!i915_gem_shrinker_lock(dev, &unlock))
5119                 return SHRINK_STOP;
5120
5121         freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5122         if (freed < sc->nr_to_scan)
5123                 freed += __i915_gem_shrink(dev_priv,
5124                                            sc->nr_to_scan - freed,
5125                                            false);
5126         if (unlock)
5127                 mutex_unlock(&dev->struct_mutex);
5128
5129         return freed;
5130 }
5131
5132 static int
5133 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5134 {
5135         struct drm_i915_private *dev_priv =
5136                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5137         struct drm_device *dev = dev_priv->dev;
5138         struct drm_i915_gem_object *obj;
5139         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5140         unsigned long pinned, bound, unbound, freed;
5141         bool was_interruptible;
5142         bool unlock;
5143
5144         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout)
5145                 schedule_timeout_killable(1);
5146         if (timeout == 0) {
5147                 pr_err("Unable to purge GPU memory due lock contention.\n");
5148                 return NOTIFY_DONE;
5149         }
5150
5151         was_interruptible = dev_priv->mm.interruptible;
5152         dev_priv->mm.interruptible = false;
5153
5154         freed = i915_gem_shrink_all(dev_priv);
5155
5156         dev_priv->mm.interruptible = was_interruptible;
5157
5158         /* Because we may be allocating inside our own driver, we cannot
5159          * assert that there are no objects with pinned pages that are not
5160          * being pointed to by hardware.
5161          */
5162         unbound = bound = pinned = 0;
5163         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5164                 if (!obj->base.filp) /* not backed by a freeable object */
5165                         continue;
5166
5167                 if (obj->pages_pin_count)
5168                         pinned += obj->base.size;
5169                 else
5170                         unbound += obj->base.size;
5171         }
5172         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5173                 if (!obj->base.filp)
5174                         continue;
5175
5176                 if (obj->pages_pin_count)
5177                         pinned += obj->base.size;
5178                 else
5179                         bound += obj->base.size;
5180         }
5181
5182         if (unlock)
5183                 mutex_unlock(&dev->struct_mutex);
5184
5185         pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5186                 freed, pinned);
5187         if (unbound || bound)
5188                 pr_err("%lu and %lu bytes still available in the "
5189                        "bound and unbound GPU page lists.\n",
5190                        bound, unbound);
5191
5192         *(unsigned long *)ptr += freed;
5193         return NOTIFY_DONE;
5194 }
5195
5196 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5197 {
5198         struct i915_vma *vma;
5199
5200         /* This WARN has probably outlived its usefulness (callers already
5201          * WARN if they don't find the GGTT vma they expect). When removing,
5202          * remember to remove the pre-check in is_pin_display() as well */
5203         if (WARN_ON(list_empty(&obj->vma_list)))
5204                 return NULL;
5205
5206         vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5207         if (vma->vm != obj_to_ggtt(obj))
5208                 return NULL;
5209
5210         return vma;
5211 }