drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/oom.h>
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  43                                                    bool force);
  44 static __must_check int
  45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  46                                bool readonly);
  47 static void
  48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  57                                              struct shrink_control *sc);
  58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  59                                             struct shrink_control *sc);
  60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  61                                  unsigned long event,
  62                                  void *ptr);
  63 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  64 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  65
  66 static bool cpu_cache_is_coherent(struct drm_device *dev,
  67                                   enum i915_cache_level level)
  68 {
  69         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  70 }
  71
  72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  73 {
  74         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  75                 return true;
  76
  77         return obj->pin_display;
  78 }
  79
  80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  81 {
  82         if (obj->tiling_mode)
  83                 i915_gem_release_mmap(obj);
  84
  85         /* As we do not have an associated fence register, we will force
  86          * a tiling change if we ever need to acquire one.
  87          */
  88         obj->fence_dirty = false;
  89         obj->fence_reg = I915_FENCE_REG_NONE;
  90 }
  91
  92 /* some bookkeeping */
  93 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  94                                   size_t size)
  95 {
  96         spin_lock(&dev_priv->mm.object_stat_lock);
  97         dev_priv->mm.object_count++;
  98         dev_priv->mm.object_memory += size;
  99         spin_unlock(&dev_priv->mm.object_stat_lock);
 100 }
 101
 102 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 103                                      size_t size)
 104 {
 105         spin_lock(&dev_priv->mm.object_stat_lock);
 106         dev_priv->mm.object_count--;
 107         dev_priv->mm.object_memory -= size;
 108         spin_unlock(&dev_priv->mm.object_stat_lock);
 109 }
 110
 111 static int
 112 i915_gem_wait_for_error(struct i915_gpu_error *error)
 113 {
 114         int ret;
 115
 116 #define EXIT_COND (!i915_reset_in_progress(error) || \
 117                    i915_terminally_wedged(error))
 118         if (EXIT_COND)
 119                 return 0;
 120
 121         /*
 122          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 123          * userspace. If it takes that long something really bad is going on and
 124          * we should simply try to bail out and fail as gracefully as possible.
 125          */
 126         ret = wait_event_interruptible_timeout(error->reset_queue,
 127                                                EXIT_COND,
 128                                                10*HZ);
 129         if (ret == 0) {
 130                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 131                 return -EIO;
 132         } else if (ret < 0) {
 133                 return ret;
 134         }
 135 #undef EXIT_COND
 136
 137         return 0;
 138 }
 139
 140 int i915_mutex_lock_interruptible(struct drm_device *dev)
 141 {
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         int ret;
 144
 145         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 146         if (ret)
 147                 return ret;
 148
 149         ret = mutex_lock_interruptible(&dev->struct_mutex);
 150         if (ret)
 151                 return ret;
 152
 153         WARN_ON(i915_verify_lists(dev));
 154         return 0;
 155 }
 156
 157 static inline bool
 158 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 159 {
 160         return i915_gem_obj_bound_any(obj) && !obj->active;
 161 }
 162
 163 int
 164 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 165                     struct drm_file *file)
 166 {
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         struct drm_i915_gem_init *args = data;
 169
 170         if (drm_core_check_feature(dev, DRIVER_MODESET))
 171                 return -ENODEV;
 172
 173         if (args->gtt_start >= args->gtt_end ||
 174             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 175                 return -EINVAL;
 176
 177         /* GEM with user mode setting was never supported on ilk and later. */
 178         if (INTEL_INFO(dev)->gen >= 5)
 179                 return -ENODEV;
 180
 181         mutex_lock(&dev->struct_mutex);
 182         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 183                                   args->gtt_end);
 184         dev_priv->gtt.mappable_end = args->gtt_end;
 185         mutex_unlock(&dev->struct_mutex);
 186
 187         return 0;
 188 }
 189
 190 int
 191 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 192                             struct drm_file *file)
 193 {
 194         struct drm_i915_private *dev_priv = dev->dev_private;
 195         struct drm_i915_gem_get_aperture *args = data;
 196         struct drm_i915_gem_object *obj;
 197         size_t pinned;
 198
 199         pinned = 0;
 200         mutex_lock(&dev->struct_mutex);
 201         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 202                 if (i915_gem_obj_is_pinned(obj))
 203                         pinned += i915_gem_obj_ggtt_size(obj);
 204         mutex_unlock(&dev->struct_mutex);
 205
 206         args->aper_size = dev_priv->gtt.base.total;
 207         args->aper_available_size = args->aper_size - pinned;
 208
 209         return 0;
 210 }
 211
 212 static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
 213 {
 214         drm_dma_handle_t *phys = obj->phys_handle;
 215
 216         if (!phys)
 217                 return;
 218
 219         if (obj->madv == I915_MADV_WILLNEED) {
 220                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 221                 char *vaddr = phys->vaddr;
 222                 int i;
 223
 224                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 225                         struct page *page = shmem_read_mapping_page(mapping, i);
 226                         if (!IS_ERR(page)) {
 227                                 char *dst = kmap_atomic(page);
 228                                 memcpy(dst, vaddr, PAGE_SIZE);
 229                                 drm_clflush_virt_range(dst, PAGE_SIZE);
 230                                 kunmap_atomic(dst);
 231
 232                                 set_page_dirty(page);
 233                                 mark_page_accessed(page);
 234                                 page_cache_release(page);
 235                         }
 236                         vaddr += PAGE_SIZE;
 237                 }
 238                 i915_gem_chipset_flush(obj->base.dev);
 239         }
 240
 241 #ifdef CONFIG_X86
 242         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 243 #endif
 244         drm_pci_free(obj->base.dev, phys);
 245         obj->phys_handle = NULL;
 246 }
 247
 248 int
 249 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 250                             int align)
 251 {
 252         drm_dma_handle_t *phys;
 253         struct address_space *mapping;
 254         char *vaddr;
 255         int i;
 256
 257         if (obj->phys_handle) {
 258                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 259                         return -EBUSY;
 260
 261                 return 0;
 262         }
 263
 264         if (obj->madv != I915_MADV_WILLNEED)
 265                 return -EFAULT;
 266
 267         if (obj->base.filp == NULL)
 268                 return -EINVAL;
 269
 270         /* create a new object */
 271         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 272         if (!phys)
 273                 return -ENOMEM;
 274
 275         vaddr = phys->vaddr;
 276 #ifdef CONFIG_X86
 277         set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
 278 #endif
 279         mapping = file_inode(obj->base.filp)->i_mapping;
 280         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 281                 struct page *page;
 282                 char *src;
 283
 284                 page = shmem_read_mapping_page(mapping, i);
 285                 if (IS_ERR(page)) {
 286 #ifdef CONFIG_X86
 287                         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 288 #endif
 289                         drm_pci_free(obj->base.dev, phys);
 290                         return PTR_ERR(page);
 291                 }
 292
 293                 src = kmap_atomic(page);
 294                 memcpy(vaddr, src, PAGE_SIZE);
 295                 kunmap_atomic(src);
 296
 297                 mark_page_accessed(page);
 298                 page_cache_release(page);
 299
 300                 vaddr += PAGE_SIZE;
 301         }
 302
 303         obj->phys_handle = phys;
 304         return 0;
 305 }
 306
 307 static int
 308 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 309                      struct drm_i915_gem_pwrite *args,
 310                      struct drm_file *file_priv)
 311 {
 312         struct drm_device *dev = obj->base.dev;
 313         void *vaddr = obj->phys_handle->vaddr + args->offset;
 314         char __user *user_data = to_user_ptr(args->data_ptr);
 315
 316         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 317                 unsigned long unwritten;
 318
 319                 /* The physical object once assigned is fixed for the lifetime
 320                  * of the obj, so we can safely drop the lock and continue
 321                  * to access vaddr.
 322                  */
 323                 mutex_unlock(&dev->struct_mutex);
 324                 unwritten = copy_from_user(vaddr, user_data, args->size);
 325                 mutex_lock(&dev->struct_mutex);
 326                 if (unwritten)
 327                         return -EFAULT;
 328         }
 329
 330         i915_gem_chipset_flush(dev);
 331         return 0;
 332 }
 333
 334 void *i915_gem_object_alloc(struct drm_device *dev)
 335 {
 336         struct drm_i915_private *dev_priv = dev->dev_private;
 337         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 338 }
 339
 340 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 341 {
 342         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 343         kmem_cache_free(dev_priv->slab, obj);
 344 }
 345
 346 static int
 347 i915_gem_create(struct drm_file *file,
 348                 struct drm_device *dev,
 349                 uint64_t size,
 350                 uint32_t *handle_p)
 351 {
 352         struct drm_i915_gem_object *obj;
 353         int ret;
 354         u32 handle;
 355
 356         size = roundup(size, PAGE_SIZE);
 357         if (size == 0)
 358                 return -EINVAL;
 359
 360         /* Allocate the new object */
 361         obj = i915_gem_alloc_object(dev, size);
 362         if (obj == NULL)
 363                 return -ENOMEM;
 364
 365         ret = drm_gem_handle_create(file, &obj->base, &handle);
 366         /* drop reference from allocate - handle holds it now */
 367         drm_gem_object_unreference_unlocked(&obj->base);
 368         if (ret)
 369                 return ret;
 370
 371         *handle_p = handle;
 372         return 0;
 373 }
 374
 375 int
 376 i915_gem_dumb_create(struct drm_file *file,
 377                      struct drm_device *dev,
 378                      struct drm_mode_create_dumb *args)
 379 {
 380         /* have to work out size/pitch and return them */
 381         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 382         args->size = args->pitch * args->height;
 383         return i915_gem_create(file, dev,
 384                                args->size, &args->handle);
 385 }
 386
 387 /**
 388  * Creates a new mm object and returns a handle to it.
 389  */
 390 int
 391 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 392                       struct drm_file *file)
 393 {
 394         struct drm_i915_gem_create *args = data;
 395
 396         return i915_gem_create(file, dev,
 397                                args->size, &args->handle);
 398 }
 399
 400 static inline int
 401 __copy_to_user_swizzled(char __user *cpu_vaddr,
 402                         const char *gpu_vaddr, int gpu_offset,
 403                         int length)
 404 {
 405         int ret, cpu_offset = 0;
 406
 407         while (length > 0) {
 408                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 409                 int this_length = min(cacheline_end - gpu_offset, length);
 410                 int swizzled_gpu_offset = gpu_offset ^ 64;
 411
 412                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 413                                      gpu_vaddr + swizzled_gpu_offset,
 414                                      this_length);
 415                 if (ret)
 416                         return ret + length;
 417
 418                 cpu_offset += this_length;
 419                 gpu_offset += this_length;
 420                 length -= this_length;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static inline int
 427 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 428                           const char __user *cpu_vaddr,
 429                           int length)
 430 {
 431         int ret, cpu_offset = 0;
 432
 433         while (length > 0) {
 434                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 435                 int this_length = min(cacheline_end - gpu_offset, length);
 436                 int swizzled_gpu_offset = gpu_offset ^ 64;
 437
 438                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 439                                        cpu_vaddr + cpu_offset,
 440                                        this_length);
 441                 if (ret)
 442                         return ret + length;
 443
 444                 cpu_offset += this_length;
 445                 gpu_offset += this_length;
 446                 length -= this_length;
 447         }
 448
 449         return 0;
 450 }
 451
 452 /*
 453  * Pins the specified object's pages and synchronizes the object with
 454  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 455  * flush the object from the CPU cache.
 456  */
 457 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 458                                     int *needs_clflush)
 459 {
 460         int ret;
 461
 462         *needs_clflush = 0;
 463
 464         if (!obj->base.filp)
 465                 return -EINVAL;
 466
 467         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 468                 /* If we're not in the cpu read domain, set ourself into the gtt
 469                  * read domain and manually flush cachelines (if required). This
 470                  * optimizes for the case when the gpu will dirty the data
 471                  * anyway again before the next pread happens. */
 472                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 473                                                         obj->cache_level);
 474                 ret = i915_gem_object_wait_rendering(obj, true);
 475                 if (ret)
 476                         return ret;
 477
 478                 i915_gem_object_retire(obj);
 479         }
 480
 481         ret = i915_gem_object_get_pages(obj);
 482         if (ret)
 483                 return ret;
 484
 485         i915_gem_object_pin_pages(obj);
 486
 487         return ret;
 488 }
 489
 490 /* Per-page copy function for the shmem pread fastpath.
 491  * Flushes invalid cachelines before reading the target if
 492  * needs_clflush is set. */
 493 static int
 494 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 495                  char __user *user_data,
 496                  bool page_do_bit17_swizzling, bool needs_clflush)
 497 {
 498         char *vaddr;
 499         int ret;
 500
 501         if (unlikely(page_do_bit17_swizzling))
 502                 return -EINVAL;
 503
 504         vaddr = kmap_atomic(page);
 505         if (needs_clflush)
 506                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 507                                        page_length);
 508         ret = __copy_to_user_inatomic(user_data,
 509                                       vaddr + shmem_page_offset,
 510                                       page_length);
 511         kunmap_atomic(vaddr);
 512
 513         return ret ? -EFAULT : 0;
 514 }
 515
 516 static void
 517 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 518                              bool swizzled)
 519 {
 520         if (unlikely(swizzled)) {
 521                 unsigned long start = (unsigned long) addr;
 522                 unsigned long end = (unsigned long) addr + length;
 523
 524                 /* For swizzling simply ensure that we always flush both
 525                  * channels. Lame, but simple and it works. Swizzled
 526                  * pwrite/pread is far from a hotpath - current userspace
 527                  * doesn't use it at all. */
 528                 start = round_down(start, 128);
 529                 end = round_up(end, 128);
 530
 531                 drm_clflush_virt_range((void *)start, end - start);
 532         } else {
 533                 drm_clflush_virt_range(addr, length);
 534         }
 535
 536 }
 537
 538 /* Only difference to the fast-path function is that this can handle bit17
 539  * and uses non-atomic copy and kmap functions. */
 540 static int
 541 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 542                  char __user *user_data,
 543                  bool page_do_bit17_swizzling, bool needs_clflush)
 544 {
 545         char *vaddr;
 546         int ret;
 547
 548         vaddr = kmap(page);
 549         if (needs_clflush)
 550                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 551                                              page_length,
 552                                              page_do_bit17_swizzling);
 553
 554         if (page_do_bit17_swizzling)
 555                 ret = __copy_to_user_swizzled(user_data,
 556                                               vaddr, shmem_page_offset,
 557                                               page_length);
 558         else
 559                 ret = __copy_to_user(user_data,
 560                                      vaddr + shmem_page_offset,
 561                                      page_length);
 562         kunmap(page);
 563
 564         return ret ? - EFAULT : 0;
 565 }
 566
 567 static int
 568 i915_gem_shmem_pread(struct drm_device *dev,
 569                      struct drm_i915_gem_object *obj,
 570                      struct drm_i915_gem_pread *args,
 571                      struct drm_file *file)
 572 {
 573         char __user *user_data;
 574         ssize_t remain;
 575         loff_t offset;
 576         int shmem_page_offset, page_length, ret = 0;
 577         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 578         int prefaulted = 0;
 579         int needs_clflush = 0;
 580         struct sg_page_iter sg_iter;
 581
 582         user_data = to_user_ptr(args->data_ptr);
 583         remain = args->size;
 584
 585         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 586
 587         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 588         if (ret)
 589                 return ret;
 590
 591         offset = args->offset;
 592
 593         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 594                          offset >> PAGE_SHIFT) {
 595                 struct page *page = sg_page_iter_page(&sg_iter);
 596
 597                 if (remain <= 0)
 598                         break;
 599
 600                 /* Operation in this page
 601                  *
 602                  * shmem_page_offset = offset within page in shmem file
 603                  * page_length = bytes to copy for this page
 604                  */
 605                 shmem_page_offset = offset_in_page(offset);
 606                 page_length = remain;
 607                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 608                         page_length = PAGE_SIZE - shmem_page_offset;
 609
 610                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 611                         (page_to_phys(page) & (1 << 17)) != 0;
 612
 613                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 614                                        user_data, page_do_bit17_swizzling,
 615                                        needs_clflush);
 616                 if (ret == 0)
 617                         goto next_page;
 618
 619                 mutex_unlock(&dev->struct_mutex);
 620
 621                 if (likely(!i915.prefault_disable) && !prefaulted) {
 622                         ret = fault_in_multipages_writeable(user_data, remain);
 623                         /* Userspace is tricking us, but we've already clobbered
 624                          * its pages with the prefault and promised to write the
 625                          * data up to the first fault. Hence ignore any errors
 626                          * and just continue. */
 627                         (void)ret;
 628                         prefaulted = 1;
 629                 }
 630
 631                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 632                                        user_data, page_do_bit17_swizzling,
 633                                        needs_clflush);
 634
 635                 mutex_lock(&dev->struct_mutex);
 636
 637                 if (ret)
 638                         goto out;
 639
 640 next_page:
 641                 remain -= page_length;
 642                 user_data += page_length;
 643                 offset += page_length;
 644         }
 645
 646 out:
 647         i915_gem_object_unpin_pages(obj);
 648
 649         return ret;
 650 }
 651
 652 /**
 653  * Reads data from the object referenced by handle.
 654  *
 655  * On error, the contents of *data are undefined.
 656  */
 657 int
 658 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 659                      struct drm_file *file)
 660 {
 661         struct drm_i915_gem_pread *args = data;
 662         struct drm_i915_gem_object *obj;
 663         int ret = 0;
 664
 665         if (args->size == 0)
 666                 return 0;
 667
 668         if (!access_ok(VERIFY_WRITE,
 669                        to_user_ptr(args->data_ptr),
 670                        args->size))
 671                 return -EFAULT;
 672
 673         ret = i915_mutex_lock_interruptible(dev);
 674         if (ret)
 675                 return ret;
 676
 677         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 678         if (&obj->base == NULL) {
 679                 ret = -ENOENT;
 680                 goto unlock;
 681         }
 682
 683         /* Bounds check source.  */
 684         if (args->offset > obj->base.size ||
 685             args->size > obj->base.size - args->offset) {
 686                 ret = -EINVAL;
 687                 goto out;
 688         }
 689
 690         /* prime objects have no backing filp to GEM pread/pwrite
 691          * pages from.
 692          */
 693         if (!obj->base.filp) {
 694                 ret = -EINVAL;
 695                 goto out;
 696         }
 697
 698         trace_i915_gem_object_pread(obj, args->offset, args->size);
 699
 700         ret = i915_gem_shmem_pread(dev, obj, args, file);
 701
 702 out:
 703         drm_gem_object_unreference(&obj->base);
 704 unlock:
 705         mutex_unlock(&dev->struct_mutex);
 706         return ret;
 707 }
 708
 709 /* This is the fast write path which cannot handle
 710  * page faults in the source data
 711  */
 712
 713 static inline int
 714 fast_user_write(struct io_mapping *mapping,
 715                 loff_t page_base, int page_offset,
 716                 char __user *user_data,
 717                 int length)
 718 {
 719         void __iomem *vaddr_atomic;
 720         void *vaddr;
 721         unsigned long unwritten;
 722
 723         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 724         /* We can use the cpu mem copy function because this is X86. */
 725         vaddr = (void __force*)vaddr_atomic + page_offset;
 726         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 727                                                       user_data, length);
 728         io_mapping_unmap_atomic(vaddr_atomic);
 729         return unwritten;
 730 }
 731
 732 /**
 733  * This is the fast pwrite path, where we copy the data directly from the
 734  * user into the GTT, uncached.
 735  */
 736 static int
 737 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 738                          struct drm_i915_gem_object *obj,
 739                          struct drm_i915_gem_pwrite *args,
 740                          struct drm_file *file)
 741 {
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         ssize_t remain;
 744         loff_t offset, page_base;
 745         char __user *user_data;
 746         int page_offset, page_length, ret;
 747
 748         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 749         if (ret)
 750                 goto out;
 751
 752         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 753         if (ret)
 754                 goto out_unpin;
 755
 756         ret = i915_gem_object_put_fence(obj);
 757         if (ret)
 758                 goto out_unpin;
 759
 760         user_data = to_user_ptr(args->data_ptr);
 761         remain = args->size;
 762
 763         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 764
 765         while (remain > 0) {
 766                 /* Operation in this page
 767                  *
 768                  * page_base = page offset within aperture
 769                  * page_offset = offset within page
 770                  * page_length = bytes to copy for this page
 771                  */
 772                 page_base = offset & PAGE_MASK;
 773                 page_offset = offset_in_page(offset);
 774                 page_length = remain;
 775                 if ((page_offset + remain) > PAGE_SIZE)
 776                         page_length = PAGE_SIZE - page_offset;
 777
 778                 /* If we get a fault while copying data, then (presumably) our
 779                  * source page isn't available.  Return the error and we'll
 780                  * retry in the slow path.
 781                  */
 782                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 783                                     page_offset, user_data, page_length)) {
 784                         ret = -EFAULT;
 785                         goto out_unpin;
 786                 }
 787
 788                 remain -= page_length;
 789                 user_data += page_length;
 790                 offset += page_length;
 791         }
 792
 793 out_unpin:
 794         i915_gem_object_ggtt_unpin(obj);
 795 out:
 796         return ret;
 797 }
 798
 799 /* Per-page copy function for the shmem pwrite fastpath.
 800  * Flushes invalid cachelines before writing to the target if
 801  * needs_clflush_before is set and flushes out any written cachelines after
 802  * writing if needs_clflush is set. */
 803 static int
 804 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 805                   char __user *user_data,
 806                   bool page_do_bit17_swizzling,
 807                   bool needs_clflush_before,
 808                   bool needs_clflush_after)
 809 {
 810         char *vaddr;
 811         int ret;
 812
 813         if (unlikely(page_do_bit17_swizzling))
 814                 return -EINVAL;
 815
 816         vaddr = kmap_atomic(page);
 817         if (needs_clflush_before)
 818                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 819                                        page_length);
 820         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 821                                         user_data, page_length);
 822         if (needs_clflush_after)
 823                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 824                                        page_length);
 825         kunmap_atomic(vaddr);
 826
 827         return ret ? -EFAULT : 0;
 828 }
 829
 830 /* Only difference to the fast-path function is that this can handle bit17
 831  * and uses non-atomic copy and kmap functions. */
 832 static int
 833 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 834                   char __user *user_data,
 835                   bool page_do_bit17_swizzling,
 836                   bool needs_clflush_before,
 837                   bool needs_clflush_after)
 838 {
 839         char *vaddr;
 840         int ret;
 841
 842         vaddr = kmap(page);
 843         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 844                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 845                                              page_length,
 846                                              page_do_bit17_swizzling);
 847         if (page_do_bit17_swizzling)
 848                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 849                                                 user_data,
 850                                                 page_length);
 851         else
 852                 ret = __copy_from_user(vaddr + shmem_page_offset,
 853                                        user_data,
 854                                        page_length);
 855         if (needs_clflush_after)
 856                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 857                                              page_length,
 858                                              page_do_bit17_swizzling);
 859         kunmap(page);
 860
 861         return ret ? -EFAULT : 0;
 862 }
 863
 864 static int
 865 i915_gem_shmem_pwrite(struct drm_device *dev,
 866                       struct drm_i915_gem_object *obj,
 867                       struct drm_i915_gem_pwrite *args,
 868                       struct drm_file *file)
 869 {
 870         ssize_t remain;
 871         loff_t offset;
 872         char __user *user_data;
 873         int shmem_page_offset, page_length, ret = 0;
 874         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 875         int hit_slowpath = 0;
 876         int needs_clflush_after = 0;
 877         int needs_clflush_before = 0;
 878         struct sg_page_iter sg_iter;
 879
 880         user_data = to_user_ptr(args->data_ptr);
 881         remain = args->size;
 882
 883         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 884
 885         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 886                 /* If we're not in the cpu write domain, set ourself into the gtt
 887                  * write domain and manually flush cachelines (if required). This
 888                  * optimizes for the case when the gpu will use the data
 889                  * right away and we therefore have to clflush anyway. */
 890                 needs_clflush_after = cpu_write_needs_clflush(obj);
 891                 ret = i915_gem_object_wait_rendering(obj, false);
 892                 if (ret)
 893                         return ret;
 894
 895                 i915_gem_object_retire(obj);
 896         }
 897         /* Same trick applies to invalidate partially written cachelines read
 898          * before writing. */
 899         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 900                 needs_clflush_before =
 901                         !cpu_cache_is_coherent(dev, obj->cache_level);
 902
 903         ret = i915_gem_object_get_pages(obj);
 904         if (ret)
 905                 return ret;
 906
 907         i915_gem_object_pin_pages(obj);
 908
 909         offset = args->offset;
 910         obj->dirty = 1;
 911
 912         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 913                          offset >> PAGE_SHIFT) {
 914                 struct page *page = sg_page_iter_page(&sg_iter);
 915                 int partial_cacheline_write;
 916
 917                 if (remain <= 0)
 918                         break;
 919
 920                 /* Operation in this page
 921                  *
 922                  * shmem_page_offset = offset within page in shmem file
 923                  * page_length = bytes to copy for this page
 924                  */
 925                 shmem_page_offset = offset_in_page(offset);
 926
 927                 page_length = remain;
 928                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 929                         page_length = PAGE_SIZE - shmem_page_offset;
 930
 931                 /* If we don't overwrite a cacheline completely we need to be
 932                  * careful to have up-to-date data by first clflushing. Don't
 933                  * overcomplicate things and flush the entire patch. */
 934                 partial_cacheline_write = needs_clflush_before &&
 935                         ((shmem_page_offset | page_length)
 936                                 & (boot_cpu_data.x86_clflush_size - 1));
 937
 938                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 939                         (page_to_phys(page) & (1 << 17)) != 0;
 940
 941                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 942                                         user_data, page_do_bit17_swizzling,
 943                                         partial_cacheline_write,
 944                                         needs_clflush_after);
 945                 if (ret == 0)
 946                         goto next_page;
 947
 948                 hit_slowpath = 1;
 949                 mutex_unlock(&dev->struct_mutex);
 950                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 951                                         user_data, page_do_bit17_swizzling,
 952                                         partial_cacheline_write,
 953                                         needs_clflush_after);
 954
 955                 mutex_lock(&dev->struct_mutex);
 956
 957                 if (ret)
 958                         goto out;
 959
 960 next_page:
 961                 remain -= page_length;
 962                 user_data += page_length;
 963                 offset += page_length;
 964         }
 965
 966 out:
 967         i915_gem_object_unpin_pages(obj);
 968
 969         if (hit_slowpath) {
 970                 /*
 971                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 972                  * cachelines in-line while writing and the object moved
 973                  * out of the cpu write domain while we've dropped the lock.
 974                  */
 975                 if (!needs_clflush_after &&
 976                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 977                         if (i915_gem_clflush_object(obj, obj->pin_display))
 978                                 i915_gem_chipset_flush(dev);
 979                 }
 980         }
 981
 982         if (needs_clflush_after)
 983                 i915_gem_chipset_flush(dev);
 984
 985         return ret;
 986 }
 987
 988 /**
 989  * Writes data to the object referenced by handle.
 990  *
 991  * On error, the contents of the buffer that were to be modified are undefined.
 992  */
 993 int
 994 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 995                       struct drm_file *file)
 996 {
 997         struct drm_i915_gem_pwrite *args = data;
 998         struct drm_i915_gem_object *obj;
 999         int ret;
1000
1001         if (args->size == 0)
1002                 return 0;
1003
1004         if (!access_ok(VERIFY_READ,
1005                        to_user_ptr(args->data_ptr),
1006                        args->size))
1007                 return -EFAULT;
1008
1009         if (likely(!i915.prefault_disable)) {
1010                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1011                                                    args->size);
1012                 if (ret)
1013                         return -EFAULT;
1014         }
1015
1016         ret = i915_mutex_lock_interruptible(dev);
1017         if (ret)
1018                 return ret;
1019
1020         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1021         if (&obj->base == NULL) {
1022                 ret = -ENOENT;
1023                 goto unlock;
1024         }
1025
1026         /* Bounds check destination. */
1027         if (args->offset > obj->base.size ||
1028             args->size > obj->base.size - args->offset) {
1029                 ret = -EINVAL;
1030                 goto out;
1031         }
1032
1033         /* prime objects have no backing filp to GEM pread/pwrite
1034          * pages from.
1035          */
1036         if (!obj->base.filp) {
1037                 ret = -EINVAL;
1038                 goto out;
1039         }
1040
1041         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1042
1043         ret = -EFAULT;
1044         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1045          * it would end up going through the fenced access, and we'll get
1046          * different detiling behavior between reading and writing.
1047          * pread/pwrite currently are reading and writing from the CPU
1048          * perspective, requiring manual detiling by the client.
1049          */
1050         if (obj->phys_handle) {
1051                 ret = i915_gem_phys_pwrite(obj, args, file);
1052                 goto out;
1053         }
1054
1055         if (obj->tiling_mode == I915_TILING_NONE &&
1056             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1057             cpu_write_needs_clflush(obj)) {
1058                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1059                 /* Note that the gtt paths might fail with non-page-backed user
1060                  * pointers (e.g. gtt mappings when moving data between
1061                  * textures). Fallback to the shmem path in that case. */
1062         }
1063
1064         if (ret == -EFAULT || ret == -ENOSPC)
1065                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1066
1067 out:
1068         drm_gem_object_unreference(&obj->base);
1069 unlock:
1070         mutex_unlock(&dev->struct_mutex);
1071         return ret;
1072 }
1073
1074 int
1075 i915_gem_check_wedge(struct i915_gpu_error *error,
1076                      bool interruptible)
1077 {
1078         if (i915_reset_in_progress(error)) {
1079                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1080                  * -EIO unconditionally for these. */
1081                 if (!interruptible)
1082                         return -EIO;
1083
1084                 /* Recovery complete, but the reset failed ... */
1085                 if (i915_terminally_wedged(error))
1086                         return -EIO;
1087
1088                 return -EAGAIN;
1089         }
1090
1091         return 0;
1092 }
1093
1094 /*
1095  * Compare seqno against outstanding lazy request. Emit a request if they are
1096  * equal.
1097  */
1098 static int
1099 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1100 {
1101         int ret;
1102
1103         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1104
1105         ret = 0;
1106         if (seqno == ring->outstanding_lazy_seqno)
1107                 ret = i915_add_request(ring, NULL);
1108
1109         return ret;
1110 }
1111
1112 static void fake_irq(unsigned long data)
1113 {
1114         wake_up_process((struct task_struct *)data);
1115 }
1116
1117 static bool missed_irq(struct drm_i915_private *dev_priv,
1118                        struct intel_engine_cs *ring)
1119 {
1120         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1121 }
1122
1123 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1124 {
1125         if (file_priv == NULL)
1126                 return true;
1127
1128         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1129 }
1130
1131 /**
1132  * __wait_seqno - wait until execution of seqno has finished
1133  * @ring: the ring expected to report seqno
1134  * @seqno: duh!
1135  * @reset_counter: reset sequence associated with the given seqno
1136  * @interruptible: do an interruptible wait (normally yes)
1137  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1138  *
1139  * Note: It is of utmost importance that the passed in seqno and reset_counter
1140  * values have been read by the caller in an smp safe manner. Where read-side
1141  * locks are involved, it is sufficient to read the reset_counter before
1142  * unlocking the lock that protects the seqno. For lockless tricks, the
1143  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1144  * inserted.
1145  *
1146  * Returns 0 if the seqno was found within the alloted time. Else returns the
1147  * errno with remaining time filled in timeout argument.
1148  */
1149 static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1150                         unsigned reset_counter,
1151                         bool interruptible,
1152                         struct timespec *timeout,
1153                         struct drm_i915_file_private *file_priv)
1154 {
1155         struct drm_device *dev = ring->dev;
1156         struct drm_i915_private *dev_priv = dev->dev_private;
1157         const bool irq_test_in_progress =
1158                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1159         struct timespec before, now;
1160         DEFINE_WAIT(wait);
1161         unsigned long timeout_expire;
1162         int ret;
1163
1164         WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n");
1165
1166         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1167                 return 0;
1168
1169         timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
1170
1171         if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
1172                 gen6_rps_boost(dev_priv);
1173                 if (file_priv)
1174                         mod_delayed_work(dev_priv->wq,
1175                                          &file_priv->mm.idle_work,
1176                                          msecs_to_jiffies(100));
1177         }
1178
1179         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1180                 return -ENODEV;
1181
1182         /* Record current time in case interrupted by signal, or wedged */
1183         trace_i915_gem_request_wait_begin(ring, seqno);
1184         getrawmonotonic(&before);
1185         for (;;) {
1186                 struct timer_list timer;
1187
1188                 prepare_to_wait(&ring->irq_queue, &wait,
1189                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1190
1191                 /* We need to check whether any gpu reset happened in between
1192                  * the caller grabbing the seqno and now ... */
1193                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1194                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1195                          * is truely gone. */
1196                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1197                         if (ret == 0)
1198                                 ret = -EAGAIN;
1199                         break;
1200                 }
1201
1202                 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1203                         ret = 0;
1204                         break;
1205                 }
1206
1207                 if (interruptible && signal_pending(current)) {
1208                         ret = -ERESTARTSYS;
1209                         break;
1210                 }
1211
1212                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1213                         ret = -ETIME;
1214                         break;
1215                 }
1216
1217                 timer.function = NULL;
1218                 if (timeout || missed_irq(dev_priv, ring)) {
1219                         unsigned long expire;
1220
1221                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1222                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1223                         mod_timer(&timer, expire);
1224                 }
1225
1226                 io_schedule();
1227
1228                 if (timer.function) {
1229                         del_singleshot_timer_sync(&timer);
1230                         destroy_timer_on_stack(&timer);
1231                 }
1232         }
1233         getrawmonotonic(&now);
1234         trace_i915_gem_request_wait_end(ring, seqno);
1235
1236         if (!irq_test_in_progress)
1237                 ring->irq_put(ring);
1238
1239         finish_wait(&ring->irq_queue, &wait);
1240
1241         if (timeout) {
1242                 struct timespec sleep_time = timespec_sub(now, before);
1243                 *timeout = timespec_sub(*timeout, sleep_time);
1244                 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1245                         set_normalized_timespec(timeout, 0, 0);
1246         }
1247
1248         return ret;
1249 }
1250
1251 /**
1252  * Waits for a sequence number to be signaled, and cleans up the
1253  * request and object lists appropriately for that event.
1254  */
1255 int
1256 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1257 {
1258         struct drm_device *dev = ring->dev;
1259         struct drm_i915_private *dev_priv = dev->dev_private;
1260         bool interruptible = dev_priv->mm.interruptible;
1261         int ret;
1262
1263         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1264         BUG_ON(seqno == 0);
1265
1266         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1267         if (ret)
1268                 return ret;
1269
1270         ret = i915_gem_check_olr(ring, seqno);
1271         if (ret)
1272                 return ret;
1273
1274         return __wait_seqno(ring, seqno,
1275                             atomic_read(&dev_priv->gpu_error.reset_counter),
1276                             interruptible, NULL, NULL);
1277 }
1278
1279 static int
1280 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1281                                      struct intel_engine_cs *ring)
1282 {
1283         if (!obj->active)
1284                 return 0;
1285
1286         /* Manually manage the write flush as we may have not yet
1287          * retired the buffer.
1288          *
1289          * Note that the last_write_seqno is always the earlier of
1290          * the two (read/write) seqno, so if we haved successfully waited,
1291          * we know we have passed the last write.
1292          */
1293         obj->last_write_seqno = 0;
1294
1295         return 0;
1296 }
1297
1298 /**
1299  * Ensures that all rendering to the object has completed and the object is
1300  * safe to unbind from the GTT or access from the CPU.
1301  */
1302 static __must_check int
1303 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1304                                bool readonly)
1305 {
1306         struct intel_engine_cs *ring = obj->ring;
1307         u32 seqno;
1308         int ret;
1309
1310         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1311         if (seqno == 0)
1312                 return 0;
1313
1314         ret = i915_wait_seqno(ring, seqno);
1315         if (ret)
1316                 return ret;
1317
1318         return i915_gem_object_wait_rendering__tail(obj, ring);
1319 }
1320
1321 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1322  * as the object state may change during this call.
1323  */
1324 static __must_check int
1325 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1326                                             struct drm_i915_file_private *file_priv,
1327                                             bool readonly)
1328 {
1329         struct drm_device *dev = obj->base.dev;
1330         struct drm_i915_private *dev_priv = dev->dev_private;
1331         struct intel_engine_cs *ring = obj->ring;
1332         unsigned reset_counter;
1333         u32 seqno;
1334         int ret;
1335
1336         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1337         BUG_ON(!dev_priv->mm.interruptible);
1338
1339         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1340         if (seqno == 0)
1341                 return 0;
1342
1343         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1344         if (ret)
1345                 return ret;
1346
1347         ret = i915_gem_check_olr(ring, seqno);
1348         if (ret)
1349                 return ret;
1350
1351         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1352         mutex_unlock(&dev->struct_mutex);
1353         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1354         mutex_lock(&dev->struct_mutex);
1355         if (ret)
1356                 return ret;
1357
1358         return i915_gem_object_wait_rendering__tail(obj, ring);
1359 }
1360
1361 /**
1362  * Called when user space prepares to use an object with the CPU, either
1363  * through the mmap ioctl's mapping or a GTT mapping.
1364  */
1365 int
1366 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1367                           struct drm_file *file)
1368 {
1369         struct drm_i915_gem_set_domain *args = data;
1370         struct drm_i915_gem_object *obj;
1371         uint32_t read_domains = args->read_domains;
1372         uint32_t write_domain = args->write_domain;
1373         int ret;
1374
1375         /* Only handle setting domains to types used by the CPU. */
1376         if (write_domain & I915_GEM_GPU_DOMAINS)
1377                 return -EINVAL;
1378
1379         if (read_domains & I915_GEM_GPU_DOMAINS)
1380                 return -EINVAL;
1381
1382         /* Having something in the write domain implies it's in the read
1383          * domain, and only that read domain.  Enforce that in the request.
1384          */
1385         if (write_domain != 0 && read_domains != write_domain)
1386                 return -EINVAL;
1387
1388         ret = i915_mutex_lock_interruptible(dev);
1389         if (ret)
1390                 return ret;
1391
1392         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1393         if (&obj->base == NULL) {
1394                 ret = -ENOENT;
1395                 goto unlock;
1396         }
1397
1398         /* Try to flush the object off the GPU without holding the lock.
1399          * We will repeat the flush holding the lock in the normal manner
1400          * to catch cases where we are gazumped.
1401          */
1402         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1403                                                           file->driver_priv,
1404                                                           !write_domain);
1405         if (ret)
1406                 goto unref;
1407
1408         if (read_domains & I915_GEM_DOMAIN_GTT) {
1409                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1410
1411                 /* Silently promote "you're not bound, there was nothing to do"
1412                  * to success, since the client was just asking us to
1413                  * make sure everything was done.
1414                  */
1415                 if (ret == -EINVAL)
1416                         ret = 0;
1417         } else {
1418                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1419         }
1420
1421 unref:
1422         drm_gem_object_unreference(&obj->base);
1423 unlock:
1424         mutex_unlock(&dev->struct_mutex);
1425         return ret;
1426 }
1427
1428 /**
1429  * Called when user space has done writes to this buffer
1430  */
1431 int
1432 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1433                          struct drm_file *file)
1434 {
1435         struct drm_i915_gem_sw_finish *args = data;
1436         struct drm_i915_gem_object *obj;
1437         int ret = 0;
1438
1439         ret = i915_mutex_lock_interruptible(dev);
1440         if (ret)
1441                 return ret;
1442
1443         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1444         if (&obj->base == NULL) {
1445                 ret = -ENOENT;
1446                 goto unlock;
1447         }
1448
1449         /* Pinned buffers may be scanout, so flush the cache */
1450         if (obj->pin_display)
1451                 i915_gem_object_flush_cpu_write_domain(obj, true);
1452
1453         drm_gem_object_unreference(&obj->base);
1454 unlock:
1455         mutex_unlock(&dev->struct_mutex);
1456         return ret;
1457 }
1458
1459 /**
1460  * Maps the contents of an object, returning the address it is mapped
1461  * into.
1462  *
1463  * While the mapping holds a reference on the contents of the object, it doesn't
1464  * imply a ref on the object itself.
1465  */
1466 int
1467 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1468                     struct drm_file *file)
1469 {
1470         struct drm_i915_gem_mmap *args = data;
1471         struct drm_gem_object *obj;
1472         unsigned long addr;
1473
1474         obj = drm_gem_object_lookup(dev, file, args->handle);
1475         if (obj == NULL)
1476                 return -ENOENT;
1477
1478         /* prime objects have no backing filp to GEM mmap
1479          * pages from.
1480          */
1481         if (!obj->filp) {
1482                 drm_gem_object_unreference_unlocked(obj);
1483                 return -EINVAL;
1484         }
1485
1486         addr = vm_mmap(obj->filp, 0, args->size,
1487                        PROT_READ | PROT_WRITE, MAP_SHARED,
1488                        args->offset);
1489         drm_gem_object_unreference_unlocked(obj);
1490         if (IS_ERR((void *)addr))
1491                 return addr;
1492
1493         args->addr_ptr = (uint64_t) addr;
1494
1495         return 0;
1496 }
1497
1498 /**
1499  * i915_gem_fault - fault a page into the GTT
1500  * vma: VMA in question
1501  * vmf: fault info
1502  *
1503  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1504  * from userspace.  The fault handler takes care of binding the object to
1505  * the GTT (if needed), allocating and programming a fence register (again,
1506  * only if needed based on whether the old reg is still valid or the object
1507  * is tiled) and inserting a new PTE into the faulting process.
1508  *
1509  * Note that the faulting process may involve evicting existing objects
1510  * from the GTT and/or fence registers to make room.  So performance may
1511  * suffer if the GTT working set is large or there are few fence registers
1512  * left.
1513  */
1514 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1515 {
1516         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1517         struct drm_device *dev = obj->base.dev;
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519         pgoff_t page_offset;
1520         unsigned long pfn;
1521         int ret = 0;
1522         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1523
1524         intel_runtime_pm_get(dev_priv);
1525
1526         /* We don't use vmf->pgoff since that has the fake offset */
1527         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1528                 PAGE_SHIFT;
1529
1530         ret = i915_mutex_lock_interruptible(dev);
1531         if (ret)
1532                 goto out;
1533
1534         trace_i915_gem_object_fault(obj, page_offset, true, write);
1535
1536         /* Try to flush the object off the GPU first without holding the lock.
1537          * Upon reacquiring the lock, we will perform our sanity checks and then
1538          * repeat the flush holding the lock in the normal manner to catch cases
1539          * where we are gazumped.
1540          */
1541         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1542         if (ret)
1543                 goto unlock;
1544
1545         /* Access to snoopable pages through the GTT is incoherent. */
1546         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1547                 ret = -EFAULT;
1548                 goto unlock;
1549         }
1550
1551         /* Now bind it into the GTT if needed */
1552         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1553         if (ret)
1554                 goto unlock;
1555
1556         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1557         if (ret)
1558                 goto unpin;
1559
1560         ret = i915_gem_object_get_fence(obj);
1561         if (ret)
1562                 goto unpin;
1563
1564         obj->fault_mappable = true;
1565
1566         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1567         pfn >>= PAGE_SHIFT;
1568         pfn += page_offset;
1569
1570         /* Finally, remap it using the new GTT offset */
1571         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1572 unpin:
1573         i915_gem_object_ggtt_unpin(obj);
1574 unlock:
1575         mutex_unlock(&dev->struct_mutex);
1576 out:
1577         switch (ret) {
1578         case -EIO:
1579                 /* If this -EIO is due to a gpu hang, give the reset code a
1580                  * chance to clean up the mess. Otherwise return the proper
1581                  * SIGBUS. */
1582                 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1583                         ret = VM_FAULT_SIGBUS;
1584                         break;
1585                 }
1586         case -EAGAIN:
1587                 /*
1588                  * EAGAIN means the gpu is hung and we'll wait for the error
1589                  * handler to reset everything when re-faulting in
1590                  * i915_mutex_lock_interruptible.
1591                  */
1592         case 0:
1593         case -ERESTARTSYS:
1594         case -EINTR:
1595         case -EBUSY:
1596                 /*
1597                  * EBUSY is ok: this just means that another thread
1598                  * already did the job.
1599                  */
1600                 ret = VM_FAULT_NOPAGE;
1601                 break;
1602         case -ENOMEM:
1603                 ret = VM_FAULT_OOM;
1604                 break;
1605         case -ENOSPC:
1606         case -EFAULT:
1607                 ret = VM_FAULT_SIGBUS;
1608                 break;
1609         default:
1610                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1611                 ret = VM_FAULT_SIGBUS;
1612                 break;
1613         }
1614
1615         intel_runtime_pm_put(dev_priv);
1616         return ret;
1617 }
1618
1619 /**
1620  * i915_gem_release_mmap - remove physical page mappings
1621  * @obj: obj in question
1622  *
1623  * Preserve the reservation of the mmapping with the DRM core code, but
1624  * relinquish ownership of the pages back to the system.
1625  *
1626  * It is vital that we remove the page mapping if we have mapped a tiled
1627  * object through the GTT and then lose the fence register due to
1628  * resource pressure. Similarly if the object has been moved out of the
1629  * aperture, than pages mapped into userspace must be revoked. Removing the
1630  * mapping will then trigger a page fault on the next user access, allowing
1631  * fixup by i915_gem_fault().
1632  */
1633 void
1634 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1635 {
1636         if (!obj->fault_mappable)
1637                 return;
1638
1639         drm_vma_node_unmap(&obj->base.vma_node,
1640                            obj->base.dev->anon_inode->i_mapping);
1641         obj->fault_mappable = false;
1642 }
1643
1644 void
1645 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1646 {
1647         struct drm_i915_gem_object *obj;
1648
1649         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1650                 i915_gem_release_mmap(obj);
1651 }
1652
1653 uint32_t
1654 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1655 {
1656         uint32_t gtt_size;
1657
1658         if (INTEL_INFO(dev)->gen >= 4 ||
1659             tiling_mode == I915_TILING_NONE)
1660                 return size;
1661
1662         /* Previous chips need a power-of-two fence region when tiling */
1663         if (INTEL_INFO(dev)->gen == 3)
1664                 gtt_size = 1024*1024;
1665         else
1666                 gtt_size = 512*1024;
1667
1668         while (gtt_size < size)
1669                 gtt_size <<= 1;
1670
1671         return gtt_size;
1672 }
1673
1674 /**
1675  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1676  * @obj: object to check
1677  *
1678  * Return the required GTT alignment for an object, taking into account
1679  * potential fence register mapping.
1680  */
1681 uint32_t
1682 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1683                            int tiling_mode, bool fenced)
1684 {
1685         /*
1686          * Minimum alignment is 4k (GTT page size), but might be greater
1687          * if a fence register is needed for the object.
1688          */
1689         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1690             tiling_mode == I915_TILING_NONE)
1691                 return 4096;
1692
1693         /*
1694          * Previous chips need to be aligned to the size of the smallest
1695          * fence register that can contain the object.
1696          */
1697         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1698 }
1699
1700 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1701 {
1702         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1703         int ret;
1704
1705         if (drm_vma_node_has_offset(&obj->base.vma_node))
1706                 return 0;
1707
1708         dev_priv->mm.shrinker_no_lock_stealing = true;
1709
1710         ret = drm_gem_create_mmap_offset(&obj->base);
1711         if (ret != -ENOSPC)
1712                 goto out;
1713
1714         /* Badly fragmented mmap space? The only way we can recover
1715          * space is by destroying unwanted objects. We can't randomly release
1716          * mmap_offsets as userspace expects them to be persistent for the
1717          * lifetime of the objects. The closest we can is to release the
1718          * offsets on purgeable objects by truncating it and marking it purged,
1719          * which prevents userspace from ever using that object again.
1720          */
1721         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1722         ret = drm_gem_create_mmap_offset(&obj->base);
1723         if (ret != -ENOSPC)
1724                 goto out;
1725
1726         i915_gem_shrink_all(dev_priv);
1727         ret = drm_gem_create_mmap_offset(&obj->base);
1728 out:
1729         dev_priv->mm.shrinker_no_lock_stealing = false;
1730
1731         return ret;
1732 }
1733
1734 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1735 {
1736         drm_gem_free_mmap_offset(&obj->base);
1737 }
1738
1739 int
1740 i915_gem_mmap_gtt(struct drm_file *file,
1741                   struct drm_device *dev,
1742                   uint32_t handle,
1743                   uint64_t *offset)
1744 {
1745         struct drm_i915_private *dev_priv = dev->dev_private;
1746         struct drm_i915_gem_object *obj;
1747         int ret;
1748
1749         ret = i915_mutex_lock_interruptible(dev);
1750         if (ret)
1751                 return ret;
1752
1753         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1754         if (&obj->base == NULL) {
1755                 ret = -ENOENT;
1756                 goto unlock;
1757         }
1758
1759         if (obj->base.size > dev_priv->gtt.mappable_end) {
1760                 ret = -E2BIG;
1761                 goto out;
1762         }
1763
1764         if (obj->madv != I915_MADV_WILLNEED) {
1765                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1766                 ret = -EFAULT;
1767                 goto out;
1768         }
1769
1770         ret = i915_gem_object_create_mmap_offset(obj);
1771         if (ret)
1772                 goto out;
1773
1774         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1775
1776 out:
1777         drm_gem_object_unreference(&obj->base);
1778 unlock:
1779         mutex_unlock(&dev->struct_mutex);
1780         return ret;
1781 }
1782
1783 /**
1784  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1785  * @dev: DRM device
1786  * @data: GTT mapping ioctl data
1787  * @file: GEM object info
1788  *
1789  * Simply returns the fake offset to userspace so it can mmap it.
1790  * The mmap call will end up in drm_gem_mmap(), which will set things
1791  * up so we can get faults in the handler above.
1792  *
1793  * The fault handler will take care of binding the object into the GTT
1794  * (since it may have been evicted to make room for something), allocating
1795  * a fence register, and mapping the appropriate aperture address into
1796  * userspace.
1797  */
1798 int
1799 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1800                         struct drm_file *file)
1801 {
1802         struct drm_i915_gem_mmap_gtt *args = data;
1803
1804         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1805 }
1806
1807 static inline int
1808 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1809 {
1810         return obj->madv == I915_MADV_DONTNEED;
1811 }
1812
1813 /* Immediately discard the backing storage */
1814 static void
1815 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1816 {
1817         i915_gem_object_free_mmap_offset(obj);
1818
1819         if (obj->base.filp == NULL)
1820                 return;
1821
1822         /* Our goal here is to return as much of the memory as
1823          * is possible back to the system as we are called from OOM.
1824          * To do this we must instruct the shmfs to drop all of its
1825          * backing pages, *now*.
1826          */
1827         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1828         obj->madv = __I915_MADV_PURGED;
1829 }
1830
1831 /* Try to discard unwanted pages */
1832 static void
1833 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1834 {
1835         struct address_space *mapping;
1836
1837         switch (obj->madv) {
1838         case I915_MADV_DONTNEED:
1839                 i915_gem_object_truncate(obj);
1840         case __I915_MADV_PURGED:
1841                 return;
1842         }
1843
1844         if (obj->base.filp == NULL)
1845                 return;
1846
1847         mapping = file_inode(obj->base.filp)->i_mapping,
1848         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1849 }
1850
1851 static void
1852 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1853 {
1854         struct sg_page_iter sg_iter;
1855         int ret;
1856
1857         BUG_ON(obj->madv == __I915_MADV_PURGED);
1858
1859         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1860         if (ret) {
1861                 /* In the event of a disaster, abandon all caches and
1862                  * hope for the best.
1863                  */
1864                 WARN_ON(ret != -EIO);
1865                 i915_gem_clflush_object(obj, true);
1866                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1867         }
1868
1869         if (i915_gem_object_needs_bit17_swizzle(obj))
1870                 i915_gem_object_save_bit_17_swizzle(obj);
1871
1872         if (obj->madv == I915_MADV_DONTNEED)
1873                 obj->dirty = 0;
1874
1875         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1876                 struct page *page = sg_page_iter_page(&sg_iter);
1877
1878                 if (obj->dirty)
1879                         set_page_dirty(page);
1880
1881                 if (obj->madv == I915_MADV_WILLNEED)
1882                         mark_page_accessed(page);
1883
1884                 page_cache_release(page);
1885         }
1886         obj->dirty = 0;
1887
1888         sg_free_table(obj->pages);
1889         kfree(obj->pages);
1890 }
1891
1892 int
1893 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1894 {
1895         const struct drm_i915_gem_object_ops *ops = obj->ops;
1896
1897         if (obj->pages == NULL)
1898                 return 0;
1899
1900         if (obj->pages_pin_count)
1901                 return -EBUSY;
1902
1903         BUG_ON(i915_gem_obj_bound_any(obj));
1904
1905         /* ->put_pages might need to allocate memory for the bit17 swizzle
1906          * array, hence protect them from being reaped by removing them from gtt
1907          * lists early. */
1908         list_del(&obj->global_list);
1909
1910         ops->put_pages(obj);
1911         obj->pages = NULL;
1912
1913         i915_gem_object_invalidate(obj);
1914
1915         return 0;
1916 }
1917
1918 static unsigned long
1919 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1920                   bool purgeable_only)
1921 {
1922         struct list_head still_in_list;
1923         struct drm_i915_gem_object *obj;
1924         unsigned long count = 0;
1925
1926         /*
1927          * As we may completely rewrite the (un)bound list whilst unbinding
1928          * (due to retiring requests) we have to strictly process only
1929          * one element of the list at the time, and recheck the list
1930          * on every iteration.
1931          *
1932          * In particular, we must hold a reference whilst removing the
1933          * object as we may end up waiting for and/or retiring the objects.
1934          * This might release the final reference (held by the active list)
1935          * and result in the object being freed from under us. This is
1936          * similar to the precautions the eviction code must take whilst
1937          * removing objects.
1938          *
1939          * Also note that although these lists do not hold a reference to
1940          * the object we can safely grab one here: The final object
1941          * unreferencing and the bound_list are both protected by the
1942          * dev->struct_mutex and so we won't ever be able to observe an
1943          * object on the bound_list with a reference count equals 0.
1944          */
1945         INIT_LIST_HEAD(&still_in_list);
1946         while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
1947                 obj = list_first_entry(&dev_priv->mm.unbound_list,
1948                                        typeof(*obj), global_list);
1949                 list_move_tail(&obj->global_list, &still_in_list);
1950
1951                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1952                         continue;
1953
1954                 drm_gem_object_reference(&obj->base);
1955
1956                 if (i915_gem_object_put_pages(obj) == 0)
1957                         count += obj->base.size >> PAGE_SHIFT;
1958
1959                 drm_gem_object_unreference(&obj->base);
1960         }
1961         list_splice(&still_in_list, &dev_priv->mm.unbound_list);
1962
1963         INIT_LIST_HEAD(&still_in_list);
1964         while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1965                 struct i915_vma *vma, *v;
1966
1967                 obj = list_first_entry(&dev_priv->mm.bound_list,
1968                                        typeof(*obj), global_list);
1969                 list_move_tail(&obj->global_list, &still_in_list);
1970
1971                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1972                         continue;
1973
1974                 drm_gem_object_reference(&obj->base);
1975
1976                 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1977                         if (i915_vma_unbind(vma))
1978                                 break;
1979
1980                 if (i915_gem_object_put_pages(obj) == 0)
1981                         count += obj->base.size >> PAGE_SHIFT;
1982
1983                 drm_gem_object_unreference(&obj->base);
1984         }
1985         list_splice(&still_in_list, &dev_priv->mm.bound_list);
1986
1987         return count;
1988 }
1989
1990 static unsigned long
1991 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1992 {
1993         return __i915_gem_shrink(dev_priv, target, true);
1994 }
1995
1996 static unsigned long
1997 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1998 {
1999         i915_gem_evict_everything(dev_priv->dev);
2000         return __i915_gem_shrink(dev_priv, LONG_MAX, false);
2001 }
2002
2003 static int
2004 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2005 {
2006         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2007         int page_count, i;
2008         struct address_space *mapping;
2009         struct sg_table *st;
2010         struct scatterlist *sg;
2011         struct sg_page_iter sg_iter;
2012         struct page *page;
2013         unsigned long last_pfn = 0;     /* suppress gcc warning */
2014         gfp_t gfp;
2015
2016         /* Assert that the object is not currently in any GPU domain. As it
2017          * wasn't in the GTT, there shouldn't be any way it could have been in
2018          * a GPU cache
2019          */
2020         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2021         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2022
2023         st = kmalloc(sizeof(*st), GFP_KERNEL);
2024         if (st == NULL)
2025                 return -ENOMEM;
2026
2027         page_count = obj->base.size / PAGE_SIZE;
2028         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2029                 kfree(st);
2030                 return -ENOMEM;
2031         }
2032
2033         /* Get the list of pages out of our struct file.  They'll be pinned
2034          * at this point until we release them.
2035          *
2036          * Fail silently without starting the shrinker
2037          */
2038         mapping = file_inode(obj->base.filp)->i_mapping;
2039         gfp = mapping_gfp_mask(mapping);
2040         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2041         gfp &= ~(__GFP_IO | __GFP_WAIT);
2042         sg = st->sgl;
2043         st->nents = 0;
2044         for (i = 0; i < page_count; i++) {
2045                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2046                 if (IS_ERR(page)) {
2047                         i915_gem_purge(dev_priv, page_count);
2048                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2049                 }
2050                 if (IS_ERR(page)) {
2051                         /* We've tried hard to allocate the memory by reaping
2052                          * our own buffer, now let the real VM do its job and
2053                          * go down in flames if truly OOM.
2054                          */
2055                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
2056                         gfp |= __GFP_IO | __GFP_WAIT;
2057
2058                         i915_gem_shrink_all(dev_priv);
2059                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2060                         if (IS_ERR(page))
2061                                 goto err_pages;
2062
2063                         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2064                         gfp &= ~(__GFP_IO | __GFP_WAIT);
2065                 }
2066 #ifdef CONFIG_SWIOTLB
2067                 if (swiotlb_nr_tbl()) {
2068                         st->nents++;
2069                         sg_set_page(sg, page, PAGE_SIZE, 0);
2070                         sg = sg_next(sg);
2071                         continue;
2072                 }
2073 #endif
2074                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2075                         if (i)
2076                                 sg = sg_next(sg);
2077                         st->nents++;
2078                         sg_set_page(sg, page, PAGE_SIZE, 0);
2079                 } else {
2080                         sg->length += PAGE_SIZE;
2081                 }
2082                 last_pfn = page_to_pfn(page);
2083
2084                 /* Check that the i965g/gm workaround works. */
2085                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2086         }
2087 #ifdef CONFIG_SWIOTLB
2088         if (!swiotlb_nr_tbl())
2089 #endif
2090                 sg_mark_end(sg);
2091         obj->pages = st;
2092
2093         if (i915_gem_object_needs_bit17_swizzle(obj))
2094                 i915_gem_object_do_bit_17_swizzle(obj);
2095
2096         return 0;
2097
2098 err_pages:
2099         sg_mark_end(sg);
2100         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2101                 page_cache_release(sg_page_iter_page(&sg_iter));
2102         sg_free_table(st);
2103         kfree(st);
2104
2105         /* shmemfs first checks if there is enough memory to allocate the page
2106          * and reports ENOSPC should there be insufficient, along with the usual
2107          * ENOMEM for a genuine allocation failure.
2108          *
2109          * We use ENOSPC in our driver to mean that we have run out of aperture
2110          * space and so want to translate the error from shmemfs back to our
2111          * usual understanding of ENOMEM.
2112          */
2113         if (PTR_ERR(page) == -ENOSPC)
2114                 return -ENOMEM;
2115         else
2116                 return PTR_ERR(page);
2117 }
2118
2119 /* Ensure that the associated pages are gathered from the backing storage
2120  * and pinned into our object. i915_gem_object_get_pages() may be called
2121  * multiple times before they are released by a single call to
2122  * i915_gem_object_put_pages() - once the pages are no longer referenced
2123  * either as a result of memory pressure (reaping pages under the shrinker)
2124  * or as the object is itself released.
2125  */
2126 int
2127 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2128 {
2129         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2130         const struct drm_i915_gem_object_ops *ops = obj->ops;
2131         int ret;
2132
2133         if (obj->pages)
2134                 return 0;
2135
2136         if (obj->madv != I915_MADV_WILLNEED) {
2137                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2138                 return -EFAULT;
2139         }
2140
2141         BUG_ON(obj->pages_pin_count);
2142
2143         ret = ops->get_pages(obj);
2144         if (ret)
2145                 return ret;
2146
2147         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2148         return 0;
2149 }
2150
2151 static void
2152 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2153                                struct intel_engine_cs *ring)
2154 {
2155         struct drm_device *dev = obj->base.dev;
2156         struct drm_i915_private *dev_priv = dev->dev_private;
2157         u32 seqno = intel_ring_get_seqno(ring);
2158
2159         BUG_ON(ring == NULL);
2160         if (obj->ring != ring && obj->last_write_seqno) {
2161                 /* Keep the seqno relative to the current ring */
2162                 obj->last_write_seqno = seqno;
2163         }
2164         obj->ring = ring;
2165
2166         /* Add a reference if we're newly entering the active list. */
2167         if (!obj->active) {
2168                 drm_gem_object_reference(&obj->base);
2169                 obj->active = 1;
2170         }
2171
2172         list_move_tail(&obj->ring_list, &ring->active_list);
2173
2174         obj->last_read_seqno = seqno;
2175
2176         if (obj->fenced_gpu_access) {
2177                 obj->last_fenced_seqno = seqno;
2178
2179                 /* Bump MRU to take account of the delayed flush */
2180                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2181                         struct drm_i915_fence_reg *reg;
2182
2183                         reg = &dev_priv->fence_regs[obj->fence_reg];
2184                         list_move_tail(&reg->lru_list,
2185                                        &dev_priv->mm.fence_list);
2186                 }
2187         }
2188 }
2189
2190 void i915_vma_move_to_active(struct i915_vma *vma,
2191                              struct intel_engine_cs *ring)
2192 {
2193         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2194         return i915_gem_object_move_to_active(vma->obj, ring);
2195 }
2196
2197 static void
2198 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2199 {
2200         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2201         struct i915_address_space *vm;
2202         struct i915_vma *vma;
2203
2204         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2205         BUG_ON(!obj->active);
2206
2207         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2208                 vma = i915_gem_obj_to_vma(obj, vm);
2209                 if (vma && !list_empty(&vma->mm_list))
2210                         list_move_tail(&vma->mm_list, &vm->inactive_list);
2211         }
2212
2213         list_del_init(&obj->ring_list);
2214         obj->ring = NULL;
2215
2216         obj->last_read_seqno = 0;
2217         obj->last_write_seqno = 0;
2218         obj->base.write_domain = 0;
2219
2220         obj->last_fenced_seqno = 0;
2221         obj->fenced_gpu_access = false;
2222
2223         obj->active = 0;
2224         drm_gem_object_unreference(&obj->base);
2225
2226         WARN_ON(i915_verify_lists(dev));
2227 }
2228
2229 static void
2230 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2231 {
2232         struct intel_engine_cs *ring = obj->ring;
2233
2234         if (ring == NULL)
2235                 return;
2236
2237         if (i915_seqno_passed(ring->get_seqno(ring, true),
2238                               obj->last_read_seqno))
2239                 i915_gem_object_move_to_inactive(obj);
2240 }
2241
2242 static int
2243 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2244 {
2245         struct drm_i915_private *dev_priv = dev->dev_private;
2246         struct intel_engine_cs *ring;
2247         int ret, i, j;
2248
2249         /* Carefully retire all requests without writing to the rings */
2250         for_each_ring(ring, dev_priv, i) {
2251                 ret = intel_ring_idle(ring);
2252                 if (ret)
2253                         return ret;
2254         }
2255         i915_gem_retire_requests(dev);
2256
2257         /* Finally reset hw state */
2258         for_each_ring(ring, dev_priv, i) {
2259                 intel_ring_init_seqno(ring, seqno);
2260
2261                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2262                         ring->semaphore.sync_seqno[j] = 0;
2263         }
2264
2265         return 0;
2266 }
2267
2268 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2269 {
2270         struct drm_i915_private *dev_priv = dev->dev_private;
2271         int ret;
2272
2273         if (seqno == 0)
2274                 return -EINVAL;
2275
2276         /* HWS page needs to be set less than what we
2277          * will inject to ring
2278          */
2279         ret = i915_gem_init_seqno(dev, seqno - 1);
2280         if (ret)
2281                 return ret;
2282
2283         /* Carefully set the last_seqno value so that wrap
2284          * detection still works
2285          */
2286         dev_priv->next_seqno = seqno;
2287         dev_priv->last_seqno = seqno - 1;
2288         if (dev_priv->last_seqno == 0)
2289                 dev_priv->last_seqno--;
2290
2291         return 0;
2292 }
2293
2294 int
2295 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2296 {
2297         struct drm_i915_private *dev_priv = dev->dev_private;
2298
2299         /* reserve 0 for non-seqno */
2300         if (dev_priv->next_seqno == 0) {
2301                 int ret = i915_gem_init_seqno(dev, 0);
2302                 if (ret)
2303                         return ret;
2304
2305                 dev_priv->next_seqno = 1;
2306         }
2307
2308         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2309         return 0;
2310 }
2311
2312 int __i915_add_request(struct intel_engine_cs *ring,
2313                        struct drm_file *file,
2314                        struct drm_i915_gem_object *obj,
2315                        u32 *out_seqno)
2316 {
2317         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2318         struct drm_i915_gem_request *request;
2319         u32 request_ring_position, request_start;
2320         int ret;
2321
2322         request_start = intel_ring_get_tail(ring);
2323         /*
2324          * Emit any outstanding flushes - execbuf can fail to emit the flush
2325          * after having emitted the batchbuffer command. Hence we need to fix
2326          * things up similar to emitting the lazy request. The difference here
2327          * is that the flush _must_ happen before the next request, no matter
2328          * what.
2329          */
2330         ret = intel_ring_flush_all_caches(ring);
2331         if (ret)
2332                 return ret;
2333
2334         request = ring->preallocated_lazy_request;
2335         if (WARN_ON(request == NULL))
2336                 return -ENOMEM;
2337
2338         /* Record the position of the start of the request so that
2339          * should we detect the updated seqno part-way through the
2340          * GPU processing the request, we never over-estimate the
2341          * position of the head.
2342          */
2343         request_ring_position = intel_ring_get_tail(ring);
2344
2345         ret = ring->add_request(ring);
2346         if (ret)
2347                 return ret;
2348
2349         request->seqno = intel_ring_get_seqno(ring);
2350         request->ring = ring;
2351         request->head = request_start;
2352         request->tail = request_ring_position;
2353
2354         /* Whilst this request exists, batch_obj will be on the
2355          * active_list, and so will hold the active reference. Only when this
2356          * request is retired will the the batch_obj be moved onto the
2357          * inactive_list and lose its active reference. Hence we do not need
2358          * to explicitly hold another reference here.
2359          */
2360         request->batch_obj = obj;
2361
2362         /* Hold a reference to the current context so that we can inspect
2363          * it later in case a hangcheck error event fires.
2364          */
2365         request->ctx = ring->last_context;
2366         if (request->ctx)
2367                 i915_gem_context_reference(request->ctx);
2368
2369         request->emitted_jiffies = jiffies;
2370         list_add_tail(&request->list, &ring->request_list);
2371         request->file_priv = NULL;
2372
2373         if (file) {
2374                 struct drm_i915_file_private *file_priv = file->driver_priv;
2375
2376                 spin_lock(&file_priv->mm.lock);
2377                 request->file_priv = file_priv;
2378                 list_add_tail(&request->client_list,
2379                               &file_priv->mm.request_list);
2380                 spin_unlock(&file_priv->mm.lock);
2381         }
2382
2383         trace_i915_gem_request_add(ring, request->seqno);
2384         ring->outstanding_lazy_seqno = 0;
2385         ring->preallocated_lazy_request = NULL;
2386
2387         if (!dev_priv->ums.mm_suspended) {
2388                 i915_queue_hangcheck(ring->dev);
2389
2390                 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2391                 queue_delayed_work(dev_priv->wq,
2392                                    &dev_priv->mm.retire_work,
2393                                    round_jiffies_up_relative(HZ));
2394                 intel_mark_busy(dev_priv->dev);
2395         }
2396
2397         if (out_seqno)
2398                 *out_seqno = request->seqno;
2399         return 0;
2400 }
2401
2402 static inline void
2403 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2404 {
2405         struct drm_i915_file_private *file_priv = request->file_priv;
2406
2407         if (!file_priv)
2408                 return;
2409
2410         spin_lock(&file_priv->mm.lock);
2411         list_del(&request->client_list);
2412         request->file_priv = NULL;
2413         spin_unlock(&file_priv->mm.lock);
2414 }
2415
2416 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2417                                    const struct intel_context *ctx)
2418 {
2419         unsigned long elapsed;
2420
2421         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2422
2423         if (ctx->hang_stats.banned)
2424                 return true;
2425
2426         if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2427                 if (!i915_gem_context_is_default(ctx)) {
2428                         DRM_DEBUG("context hanging too fast, banning!\n");
2429                         return true;
2430                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2431                         if (i915_stop_ring_allow_warn(dev_priv))
2432                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2433                         return true;
2434                 }
2435         }
2436
2437         return false;
2438 }
2439
2440 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2441                                   struct intel_context *ctx,
2442                                   const bool guilty)
2443 {
2444         struct i915_ctx_hang_stats *hs;
2445
2446         if (WARN_ON(!ctx))
2447                 return;
2448
2449         hs = &ctx->hang_stats;
2450
2451         if (guilty) {
2452                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2453                 hs->batch_active++;
2454                 hs->guilty_ts = get_seconds();
2455         } else {
2456                 hs->batch_pending++;
2457         }
2458 }
2459
2460 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2461 {
2462         list_del(&request->list);
2463         i915_gem_request_remove_from_client(request);
2464
2465         if (request->ctx)
2466                 i915_gem_context_unreference(request->ctx);
2467
2468         kfree(request);
2469 }
2470
2471 struct drm_i915_gem_request *
2472 i915_gem_find_active_request(struct intel_engine_cs *ring)
2473 {
2474         struct drm_i915_gem_request *request;
2475         u32 completed_seqno;
2476
2477         completed_seqno = ring->get_seqno(ring, false);
2478
2479         list_for_each_entry(request, &ring->request_list, list) {
2480                 if (i915_seqno_passed(completed_seqno, request->seqno))
2481                         continue;
2482
2483                 return request;
2484         }
2485
2486         return NULL;
2487 }
2488
2489 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2490                                        struct intel_engine_cs *ring)
2491 {
2492         struct drm_i915_gem_request *request;
2493         bool ring_hung;
2494
2495         request = i915_gem_find_active_request(ring);
2496
2497         if (request == NULL)
2498                 return;
2499
2500         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2501
2502         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2503
2504         list_for_each_entry_continue(request, &ring->request_list, list)
2505                 i915_set_reset_status(dev_priv, request->ctx, false);
2506 }
2507
2508 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2509                                         struct intel_engine_cs *ring)
2510 {
2511         while (!list_empty(&ring->active_list)) {
2512                 struct drm_i915_gem_object *obj;
2513
2514                 obj = list_first_entry(&ring->active_list,
2515                                        struct drm_i915_gem_object,
2516                                        ring_list);
2517
2518                 i915_gem_object_move_to_inactive(obj);
2519         }
2520
2521         /*
2522          * We must free the requests after all the corresponding objects have
2523          * been moved off active lists. Which is the same order as the normal
2524          * retire_requests function does. This is important if object hold
2525          * implicit references on things like e.g. ppgtt address spaces through
2526          * the request.
2527          */
2528         while (!list_empty(&ring->request_list)) {
2529                 struct drm_i915_gem_request *request;
2530
2531                 request = list_first_entry(&ring->request_list,
2532                                            struct drm_i915_gem_request,
2533                                            list);
2534
2535                 i915_gem_free_request(request);
2536         }
2537
2538         /* These may not have been flush before the reset, do so now */
2539         kfree(ring->preallocated_lazy_request);
2540         ring->preallocated_lazy_request = NULL;
2541         ring->outstanding_lazy_seqno = 0;
2542 }
2543
2544 void i915_gem_restore_fences(struct drm_device *dev)
2545 {
2546         struct drm_i915_private *dev_priv = dev->dev_private;
2547         int i;
2548
2549         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2550                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2551
2552                 /*
2553                  * Commit delayed tiling changes if we have an object still
2554                  * attached to the fence, otherwise just clear the fence.
2555                  */
2556                 if (reg->obj) {
2557                         i915_gem_object_update_fence(reg->obj, reg,
2558                                                      reg->obj->tiling_mode);
2559                 } else {
2560                         i915_gem_write_fence(dev, i, NULL);
2561                 }
2562         }
2563 }
2564
2565 void i915_gem_reset(struct drm_device *dev)
2566 {
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct intel_engine_cs *ring;
2569         int i;
2570
2571         /*
2572          * Before we free the objects from the requests, we need to inspect
2573          * them for finding the guilty party. As the requests only borrow
2574          * their reference to the objects, the inspection must be done first.
2575          */
2576         for_each_ring(ring, dev_priv, i)
2577                 i915_gem_reset_ring_status(dev_priv, ring);
2578
2579         for_each_ring(ring, dev_priv, i)
2580                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2581
2582         i915_gem_context_reset(dev);
2583
2584         i915_gem_restore_fences(dev);
2585 }
2586
2587 /**
2588  * This function clears the request list as sequence numbers are passed.
2589  */
2590 void
2591 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2592 {
2593         uint32_t seqno;
2594
2595         if (list_empty(&ring->request_list))
2596                 return;
2597
2598         WARN_ON(i915_verify_lists(ring->dev));
2599
2600         seqno = ring->get_seqno(ring, true);
2601
2602         /* Move any buffers on the active list that are no longer referenced
2603          * by the ringbuffer to the flushing/inactive lists as appropriate,
2604          * before we free the context associated with the requests.
2605          */
2606         while (!list_empty(&ring->active_list)) {
2607                 struct drm_i915_gem_object *obj;
2608
2609                 obj = list_first_entry(&ring->active_list,
2610                                       struct drm_i915_gem_object,
2611                                       ring_list);
2612
2613                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2614                         break;
2615
2616                 i915_gem_object_move_to_inactive(obj);
2617         }
2618
2619
2620         while (!list_empty(&ring->request_list)) {
2621                 struct drm_i915_gem_request *request;
2622
2623                 request = list_first_entry(&ring->request_list,
2624                                            struct drm_i915_gem_request,
2625                                            list);
2626
2627                 if (!i915_seqno_passed(seqno, request->seqno))
2628                         break;
2629
2630                 trace_i915_gem_request_retire(ring, request->seqno);
2631                 /* We know the GPU must have read the request to have
2632                  * sent us the seqno + interrupt, so use the position
2633                  * of tail of the request to update the last known position
2634                  * of the GPU head.
2635                  */
2636                 ring->buffer->last_retired_head = request->tail;
2637
2638                 i915_gem_free_request(request);
2639         }
2640
2641         if (unlikely(ring->trace_irq_seqno &&
2642                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2643                 ring->irq_put(ring);
2644                 ring->trace_irq_seqno = 0;
2645         }
2646
2647         WARN_ON(i915_verify_lists(ring->dev));
2648 }
2649
2650 bool
2651 i915_gem_retire_requests(struct drm_device *dev)
2652 {
2653         struct drm_i915_private *dev_priv = dev->dev_private;
2654         struct intel_engine_cs *ring;
2655         bool idle = true;
2656         int i;
2657
2658         for_each_ring(ring, dev_priv, i) {
2659                 i915_gem_retire_requests_ring(ring);
2660                 idle &= list_empty(&ring->request_list);
2661         }
2662
2663         if (idle)
2664                 mod_delayed_work(dev_priv->wq,
2665                                    &dev_priv->mm.idle_work,
2666                                    msecs_to_jiffies(100));
2667
2668         return idle;
2669 }
2670
2671 static void
2672 i915_gem_retire_work_handler(struct work_struct *work)
2673 {
2674         struct drm_i915_private *dev_priv =
2675                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2676         struct drm_device *dev = dev_priv->dev;
2677         bool idle;
2678
2679         /* Come back later if the device is busy... */
2680         idle = false;
2681         if (mutex_trylock(&dev->struct_mutex)) {
2682                 idle = i915_gem_retire_requests(dev);
2683                 mutex_unlock(&dev->struct_mutex);
2684         }
2685         if (!idle)
2686                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2687                                    round_jiffies_up_relative(HZ));
2688 }
2689
2690 static void
2691 i915_gem_idle_work_handler(struct work_struct *work)
2692 {
2693         struct drm_i915_private *dev_priv =
2694                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2695
2696         intel_mark_idle(dev_priv->dev);
2697 }
2698
2699 /**
2700  * Ensures that an object will eventually get non-busy by flushing any required
2701  * write domains, emitting any outstanding lazy request and retiring and
2702  * completed requests.
2703  */
2704 static int
2705 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2706 {
2707         int ret;
2708
2709         if (obj->active) {
2710                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2711                 if (ret)
2712                         return ret;
2713
2714                 i915_gem_retire_requests_ring(obj->ring);
2715         }
2716
2717         return 0;
2718 }
2719
2720 /**
2721  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2722  * @DRM_IOCTL_ARGS: standard ioctl arguments
2723  *
2724  * Returns 0 if successful, else an error is returned with the remaining time in
2725  * the timeout parameter.
2726  *  -ETIME: object is still busy after timeout
2727  *  -ERESTARTSYS: signal interrupted the wait
2728  *  -ENONENT: object doesn't exist
2729  * Also possible, but rare:
2730  *  -EAGAIN: GPU wedged
2731  *  -ENOMEM: damn
2732  *  -ENODEV: Internal IRQ fail
2733  *  -E?: The add request failed
2734  *
2735  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2736  * non-zero timeout parameter the wait ioctl will wait for the given number of
2737  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2738  * without holding struct_mutex the object may become re-busied before this
2739  * function completes. A similar but shorter * race condition exists in the busy
2740  * ioctl
2741  */
2742 int
2743 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2744 {
2745         struct drm_i915_private *dev_priv = dev->dev_private;
2746         struct drm_i915_gem_wait *args = data;
2747         struct drm_i915_gem_object *obj;
2748         struct intel_engine_cs *ring = NULL;
2749         struct timespec timeout_stack, *timeout = NULL;
2750         unsigned reset_counter;
2751         u32 seqno = 0;
2752         int ret = 0;
2753
2754         if (args->timeout_ns >= 0) {
2755                 timeout_stack = ns_to_timespec(args->timeout_ns);
2756                 timeout = &timeout_stack;
2757         }
2758
2759         ret = i915_mutex_lock_interruptible(dev);
2760         if (ret)
2761                 return ret;
2762
2763         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2764         if (&obj->base == NULL) {
2765                 mutex_unlock(&dev->struct_mutex);
2766                 return -ENOENT;
2767         }
2768
2769         /* Need to make sure the object gets inactive eventually. */
2770         ret = i915_gem_object_flush_active(obj);
2771         if (ret)
2772                 goto out;
2773
2774         if (obj->active) {
2775                 seqno = obj->last_read_seqno;
2776                 ring = obj->ring;
2777         }
2778
2779         if (seqno == 0)
2780                  goto out;
2781
2782         /* Do this after OLR check to make sure we make forward progress polling
2783          * on this IOCTL with a 0 timeout (like busy ioctl)
2784          */
2785         if (!args->timeout_ns) {
2786                 ret = -ETIME;
2787                 goto out;
2788         }
2789
2790         drm_gem_object_unreference(&obj->base);
2791         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2792         mutex_unlock(&dev->struct_mutex);
2793
2794         ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2795         if (timeout)
2796                 args->timeout_ns = timespec_to_ns(timeout);
2797         return ret;
2798
2799 out:
2800         drm_gem_object_unreference(&obj->base);
2801         mutex_unlock(&dev->struct_mutex);
2802         return ret;
2803 }
2804
2805 /**
2806  * i915_gem_object_sync - sync an object to a ring.
2807  *
2808  * @obj: object which may be in use on another ring.
2809  * @to: ring we wish to use the object on. May be NULL.
2810  *
2811  * This code is meant to abstract object synchronization with the GPU.
2812  * Calling with NULL implies synchronizing the object with the CPU
2813  * rather than a particular GPU ring.
2814  *
2815  * Returns 0 if successful, else propagates up the lower layer error.
2816  */
2817 int
2818 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2819                      struct intel_engine_cs *to)
2820 {
2821         struct intel_engine_cs *from = obj->ring;
2822         u32 seqno;
2823         int ret, idx;
2824
2825         if (from == NULL || to == from)
2826                 return 0;
2827
2828         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2829                 return i915_gem_object_wait_rendering(obj, false);
2830
2831         idx = intel_ring_sync_index(from, to);
2832
2833         seqno = obj->last_read_seqno;
2834         if (seqno <= from->semaphore.sync_seqno[idx])
2835                 return 0;
2836
2837         ret = i915_gem_check_olr(obj->ring, seqno);
2838         if (ret)
2839                 return ret;
2840
2841         trace_i915_gem_ring_sync_to(from, to, seqno);
2842         ret = to->semaphore.sync_to(to, from, seqno);
2843         if (!ret)
2844                 /* We use last_read_seqno because sync_to()
2845                  * might have just caused seqno wrap under
2846                  * the radar.
2847                  */
2848                 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2849
2850         return ret;
2851 }
2852
2853 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2854 {
2855         u32 old_write_domain, old_read_domains;
2856
2857         /* Force a pagefault for domain tracking on next user access */
2858         i915_gem_release_mmap(obj);
2859
2860         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2861                 return;
2862
2863         /* Wait for any direct GTT access to complete */
2864         mb();
2865
2866         old_read_domains = obj->base.read_domains;
2867         old_write_domain = obj->base.write_domain;
2868
2869         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2870         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2871
2872         trace_i915_gem_object_change_domain(obj,
2873                                             old_read_domains,
2874                                             old_write_domain);
2875 }
2876
2877 int i915_vma_unbind(struct i915_vma *vma)
2878 {
2879         struct drm_i915_gem_object *obj = vma->obj;
2880         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2881         int ret;
2882
2883         if (list_empty(&vma->vma_link))
2884                 return 0;
2885
2886         if (!drm_mm_node_allocated(&vma->node)) {
2887                 i915_gem_vma_destroy(vma);
2888                 return 0;
2889         }
2890
2891         if (vma->pin_count)
2892                 return -EBUSY;
2893
2894         BUG_ON(obj->pages == NULL);
2895
2896         ret = i915_gem_object_finish_gpu(obj);
2897         if (ret)
2898                 return ret;
2899         /* Continue on if we fail due to EIO, the GPU is hung so we
2900          * should be safe and we need to cleanup or else we might
2901          * cause memory corruption through use-after-free.
2902          */
2903
2904         if (i915_is_ggtt(vma->vm)) {
2905                 i915_gem_object_finish_gtt(obj);
2906
2907                 /* release the fence reg _after_ flushing */
2908                 ret = i915_gem_object_put_fence(obj);
2909                 if (ret)
2910                         return ret;
2911         }
2912
2913         trace_i915_vma_unbind(vma);
2914
2915         vma->unbind_vma(vma);
2916
2917         i915_gem_gtt_finish_object(obj);
2918
2919         list_del_init(&vma->mm_list);
2920         /* Avoid an unnecessary call to unbind on rebind. */
2921         if (i915_is_ggtt(vma->vm))
2922                 obj->map_and_fenceable = true;
2923
2924         drm_mm_remove_node(&vma->node);
2925         i915_gem_vma_destroy(vma);
2926
2927         /* Since the unbound list is global, only move to that list if
2928          * no more VMAs exist. */
2929         if (list_empty(&obj->vma_list))
2930                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2931
2932         /* And finally now the object is completely decoupled from this vma,
2933          * we can drop its hold on the backing storage and allow it to be
2934          * reaped by the shrinker.
2935          */
2936         i915_gem_object_unpin_pages(obj);
2937
2938         return 0;
2939 }
2940
2941 int i915_gpu_idle(struct drm_device *dev)
2942 {
2943         struct drm_i915_private *dev_priv = dev->dev_private;
2944         struct intel_engine_cs *ring;
2945         int ret, i;
2946
2947         /* Flush everything onto the inactive list. */
2948         for_each_ring(ring, dev_priv, i) {
2949                 ret = i915_switch_context(ring, ring->default_context);
2950                 if (ret)
2951                         return ret;
2952
2953                 ret = intel_ring_idle(ring);
2954                 if (ret)
2955                         return ret;
2956         }
2957
2958         return 0;
2959 }
2960
2961 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2962                                  struct drm_i915_gem_object *obj)
2963 {
2964         struct drm_i915_private *dev_priv = dev->dev_private;
2965         int fence_reg;
2966         int fence_pitch_shift;
2967
2968         if (INTEL_INFO(dev)->gen >= 6) {
2969                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2970                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2971         } else {
2972                 fence_reg = FENCE_REG_965_0;
2973                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2974         }
2975
2976         fence_reg += reg * 8;
2977
2978         /* To w/a incoherency with non-atomic 64-bit register updates,
2979          * we split the 64-bit update into two 32-bit writes. In order
2980          * for a partial fence not to be evaluated between writes, we
2981          * precede the update with write to turn off the fence register,
2982          * and only enable the fence as the last step.
2983          *
2984          * For extra levels of paranoia, we make sure each step lands
2985          * before applying the next step.
2986          */
2987         I915_WRITE(fence_reg, 0);
2988         POSTING_READ(fence_reg);
2989
2990         if (obj) {
2991                 u32 size = i915_gem_obj_ggtt_size(obj);
2992                 uint64_t val;
2993
2994                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2995                                  0xfffff000) << 32;
2996                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2997                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2998                 if (obj->tiling_mode == I915_TILING_Y)
2999                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3000                 val |= I965_FENCE_REG_VALID;
3001
3002                 I915_WRITE(fence_reg + 4, val >> 32);
3003                 POSTING_READ(fence_reg + 4);
3004
3005                 I915_WRITE(fence_reg + 0, val);
3006                 POSTING_READ(fence_reg);
3007         } else {
3008                 I915_WRITE(fence_reg + 4, 0);
3009                 POSTING_READ(fence_reg + 4);
3010         }
3011 }
3012
3013 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3014                                  struct drm_i915_gem_object *obj)
3015 {
3016         struct drm_i915_private *dev_priv = dev->dev_private;
3017         u32 val;
3018
3019         if (obj) {
3020                 u32 size = i915_gem_obj_ggtt_size(obj);
3021                 int pitch_val;
3022                 int tile_width;
3023
3024                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3025                      (size & -size) != size ||
3026                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3027                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3028                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3029
3030                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3031                         tile_width = 128;
3032                 else
3033                         tile_width = 512;
3034
3035                 /* Note: pitch better be a power of two tile widths */
3036                 pitch_val = obj->stride / tile_width;
3037                 pitch_val = ffs(pitch_val) - 1;
3038
3039                 val = i915_gem_obj_ggtt_offset(obj);
3040                 if (obj->tiling_mode == I915_TILING_Y)
3041                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3042                 val |= I915_FENCE_SIZE_BITS(size);
3043                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3044                 val |= I830_FENCE_REG_VALID;
3045         } else
3046                 val = 0;
3047
3048         if (reg < 8)
3049                 reg = FENCE_REG_830_0 + reg * 4;
3050         else
3051                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3052
3053         I915_WRITE(reg, val);
3054         POSTING_READ(reg);
3055 }
3056
3057 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3058                                 struct drm_i915_gem_object *obj)
3059 {
3060         struct drm_i915_private *dev_priv = dev->dev_private;
3061         uint32_t val;
3062
3063         if (obj) {
3064                 u32 size = i915_gem_obj_ggtt_size(obj);
3065                 uint32_t pitch_val;
3066
3067                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3068                      (size & -size) != size ||
3069                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3070                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3071                      i915_gem_obj_ggtt_offset(obj), size);
3072
3073                 pitch_val = obj->stride / 128;
3074                 pitch_val = ffs(pitch_val) - 1;
3075
3076                 val = i915_gem_obj_ggtt_offset(obj);
3077                 if (obj->tiling_mode == I915_TILING_Y)
3078                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3079                 val |= I830_FENCE_SIZE_BITS(size);
3080                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3081                 val |= I830_FENCE_REG_VALID;
3082         } else
3083                 val = 0;
3084
3085         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3086         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3087 }
3088
3089 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3090 {
3091         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3092 }
3093
3094 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3095                                  struct drm_i915_gem_object *obj)
3096 {
3097         struct drm_i915_private *dev_priv = dev->dev_private;
3098
3099         /* Ensure that all CPU reads are completed before installing a fence
3100          * and all writes before removing the fence.
3101          */
3102         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3103                 mb();
3104
3105         WARN(obj && (!obj->stride || !obj->tiling_mode),
3106              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3107              obj->stride, obj->tiling_mode);
3108
3109         switch (INTEL_INFO(dev)->gen) {
3110         case 8:
3111         case 7:
3112         case 6:
3113         case 5:
3114         case 4: i965_write_fence_reg(dev, reg, obj); break;
3115         case 3: i915_write_fence_reg(dev, reg, obj); break;
3116         case 2: i830_write_fence_reg(dev, reg, obj); break;
3117         default: BUG();
3118         }
3119
3120         /* And similarly be paranoid that no direct access to this region
3121          * is reordered to before the fence is installed.
3122          */
3123         if (i915_gem_object_needs_mb(obj))
3124                 mb();
3125 }
3126
3127 static inline int fence_number(struct drm_i915_private *dev_priv,
3128                                struct drm_i915_fence_reg *fence)
3129 {
3130         return fence - dev_priv->fence_regs;
3131 }
3132
3133 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3134                                          struct drm_i915_fence_reg *fence,
3135                                          bool enable)
3136 {
3137         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3138         int reg = fence_number(dev_priv, fence);
3139
3140         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3141
3142         if (enable) {
3143                 obj->fence_reg = reg;
3144                 fence->obj = obj;
3145                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3146         } else {
3147                 obj->fence_reg = I915_FENCE_REG_NONE;
3148                 fence->obj = NULL;
3149                 list_del_init(&fence->lru_list);
3150         }
3151         obj->fence_dirty = false;
3152 }
3153
3154 static int
3155 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3156 {
3157         if (obj->last_fenced_seqno) {
3158                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3159                 if (ret)
3160                         return ret;
3161
3162                 obj->last_fenced_seqno = 0;
3163         }
3164
3165         obj->fenced_gpu_access = false;
3166         return 0;
3167 }
3168
3169 int
3170 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3171 {
3172         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3173         struct drm_i915_fence_reg *fence;
3174         int ret;
3175
3176         ret = i915_gem_object_wait_fence(obj);
3177         if (ret)
3178                 return ret;
3179
3180         if (obj->fence_reg == I915_FENCE_REG_NONE)
3181                 return 0;
3182
3183         fence = &dev_priv->fence_regs[obj->fence_reg];
3184
3185         if (WARN_ON(fence->pin_count))
3186                 return -EBUSY;
3187
3188         i915_gem_object_fence_lost(obj);
3189         i915_gem_object_update_fence(obj, fence, false);
3190
3191         return 0;
3192 }
3193
3194 static struct drm_i915_fence_reg *
3195 i915_find_fence_reg(struct drm_device *dev)
3196 {
3197         struct drm_i915_private *dev_priv = dev->dev_private;
3198         struct drm_i915_fence_reg *reg, *avail;
3199         int i;
3200
3201         /* First try to find a free reg */
3202         avail = NULL;
3203         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3204                 reg = &dev_priv->fence_regs[i];
3205                 if (!reg->obj)
3206                         return reg;
3207
3208                 if (!reg->pin_count)
3209                         avail = reg;
3210         }
3211
3212         if (avail == NULL)
3213                 goto deadlock;
3214
3215         /* None available, try to steal one or wait for a user to finish */
3216         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3217                 if (reg->pin_count)
3218                         continue;
3219
3220                 return reg;
3221         }
3222
3223 deadlock:
3224         /* Wait for completion of pending flips which consume fences */
3225         if (intel_has_pending_fb_unpin(dev))
3226                 return ERR_PTR(-EAGAIN);
3227
3228         return ERR_PTR(-EDEADLK);
3229 }
3230
3231 /**
3232  * i915_gem_object_get_fence - set up fencing for an object
3233  * @obj: object to map through a fence reg
3234  *
3235  * When mapping objects through the GTT, userspace wants to be able to write
3236  * to them without having to worry about swizzling if the object is tiled.
3237  * This function walks the fence regs looking for a free one for @obj,
3238  * stealing one if it can't find any.
3239  *
3240  * It then sets up the reg based on the object's properties: address, pitch
3241  * and tiling format.
3242  *
3243  * For an untiled surface, this removes any existing fence.
3244  */
3245 int
3246 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3247 {
3248         struct drm_device *dev = obj->base.dev;
3249         struct drm_i915_private *dev_priv = dev->dev_private;
3250         bool enable = obj->tiling_mode != I915_TILING_NONE;
3251         struct drm_i915_fence_reg *reg;
3252         int ret;
3253
3254         /* Have we updated the tiling parameters upon the object and so
3255          * will need to serialise the write to the associated fence register?
3256          */
3257         if (obj->fence_dirty) {
3258                 ret = i915_gem_object_wait_fence(obj);
3259                 if (ret)
3260                         return ret;
3261         }
3262
3263         /* Just update our place in the LRU if our fence is getting reused. */
3264         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3265                 reg = &dev_priv->fence_regs[obj->fence_reg];
3266                 if (!obj->fence_dirty) {
3267                         list_move_tail(&reg->lru_list,
3268                                        &dev_priv->mm.fence_list);
3269                         return 0;
3270                 }
3271         } else if (enable) {
3272                 reg = i915_find_fence_reg(dev);
3273                 if (IS_ERR(reg))
3274                         return PTR_ERR(reg);
3275
3276                 if (reg->obj) {
3277                         struct drm_i915_gem_object *old = reg->obj;
3278
3279                         ret = i915_gem_object_wait_fence(old);
3280                         if (ret)
3281                                 return ret;
3282
3283                         i915_gem_object_fence_lost(old);
3284                 }
3285         } else
3286                 return 0;
3287
3288         i915_gem_object_update_fence(obj, reg, enable);
3289
3290         return 0;
3291 }
3292
3293 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3294                                      struct drm_mm_node *gtt_space,
3295                                      unsigned long cache_level)
3296 {
3297         struct drm_mm_node *other;
3298
3299         /* On non-LLC machines we have to be careful when putting differing
3300          * types of snoopable memory together to avoid the prefetcher
3301          * crossing memory domains and dying.
3302          */
3303         if (HAS_LLC(dev))
3304                 return true;
3305
3306         if (!drm_mm_node_allocated(gtt_space))
3307                 return true;
3308
3309         if (list_empty(&gtt_space->node_list))
3310                 return true;
3311
3312         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3313         if (other->allocated && !other->hole_follows && other->color != cache_level)
3314                 return false;
3315
3316         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3317         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3318                 return false;
3319
3320         return true;
3321 }
3322
3323 static void i915_gem_verify_gtt(struct drm_device *dev)
3324 {
3325 #if WATCH_GTT
3326         struct drm_i915_private *dev_priv = dev->dev_private;
3327         struct drm_i915_gem_object *obj;
3328         int err = 0;
3329
3330         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3331                 if (obj->gtt_space == NULL) {
3332                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3333                         err++;
3334                         continue;
3335                 }
3336
3337                 if (obj->cache_level != obj->gtt_space->color) {
3338                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3339                                i915_gem_obj_ggtt_offset(obj),
3340                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3341                                obj->cache_level,
3342                                obj->gtt_space->color);
3343                         err++;
3344                         continue;
3345                 }
3346
3347                 if (!i915_gem_valid_gtt_space(dev,
3348                                               obj->gtt_space,
3349                                               obj->cache_level)) {
3350                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3351                                i915_gem_obj_ggtt_offset(obj),
3352                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3353                                obj->cache_level);
3354                         err++;
3355                         continue;
3356                 }
3357         }
3358
3359         WARN_ON(err);
3360 #endif
3361 }
3362
3363 /**
3364  * Finds free space in the GTT aperture and binds the object there.
3365  */
3366 static struct i915_vma *
3367 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3368                            struct i915_address_space *vm,
3369                            unsigned alignment,
3370                            uint64_t flags)
3371 {
3372         struct drm_device *dev = obj->base.dev;
3373         struct drm_i915_private *dev_priv = dev->dev_private;
3374         u32 size, fence_size, fence_alignment, unfenced_alignment;
3375         unsigned long start =
3376                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3377         unsigned long end =
3378                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3379         struct i915_vma *vma;
3380         int ret;
3381
3382         fence_size = i915_gem_get_gtt_size(dev,
3383                                            obj->base.size,
3384                                            obj->tiling_mode);
3385         fence_alignment = i915_gem_get_gtt_alignment(dev,
3386                                                      obj->base.size,
3387                                                      obj->tiling_mode, true);
3388         unfenced_alignment =
3389                 i915_gem_get_gtt_alignment(dev,
3390                                            obj->base.size,
3391                                            obj->tiling_mode, false);
3392
3393         if (alignment == 0)
3394                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3395                                                 unfenced_alignment;
3396         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3397                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3398                 return ERR_PTR(-EINVAL);
3399         }
3400
3401         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3402
3403         /* If the object is bigger than the entire aperture, reject it early
3404          * before evicting everything in a vain attempt to find space.
3405          */
3406         if (obj->base.size > end) {
3407                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3408                           obj->base.size,
3409                           flags & PIN_MAPPABLE ? "mappable" : "total",
3410                           end);
3411                 return ERR_PTR(-E2BIG);
3412         }
3413
3414         ret = i915_gem_object_get_pages(obj);
3415         if (ret)
3416                 return ERR_PTR(ret);
3417
3418         i915_gem_object_pin_pages(obj);
3419
3420         vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3421         if (IS_ERR(vma))
3422                 goto err_unpin;
3423
3424 search_free:
3425         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3426                                                   size, alignment,
3427                                                   obj->cache_level,
3428                                                   start, end,
3429                                                   DRM_MM_SEARCH_DEFAULT,
3430                                                   DRM_MM_CREATE_DEFAULT);
3431         if (ret) {
3432                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3433                                                obj->cache_level,
3434                                                start, end,
3435                                                flags);
3436                 if (ret == 0)
3437                         goto search_free;
3438
3439                 goto err_free_vma;
3440         }
3441         if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3442                                               obj->cache_level))) {
3443                 ret = -EINVAL;
3444                 goto err_remove_node;
3445         }
3446
3447         ret = i915_gem_gtt_prepare_object(obj);
3448         if (ret)
3449                 goto err_remove_node;
3450
3451         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3452         list_add_tail(&vma->mm_list, &vm->inactive_list);
3453
3454         if (i915_is_ggtt(vm)) {
3455                 bool mappable, fenceable;
3456
3457                 fenceable = (vma->node.size == fence_size &&
3458                              (vma->node.start & (fence_alignment - 1)) == 0);
3459
3460                 mappable = (vma->node.start + obj->base.size <=
3461                             dev_priv->gtt.mappable_end);
3462
3463                 obj->map_and_fenceable = mappable && fenceable;
3464         }
3465
3466         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3467
3468         trace_i915_vma_bind(vma, flags);
3469         vma->bind_vma(vma, obj->cache_level,
3470                       flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3471
3472         i915_gem_verify_gtt(dev);
3473         return vma;
3474
3475 err_remove_node:
3476         drm_mm_remove_node(&vma->node);
3477 err_free_vma:
3478         i915_gem_vma_destroy(vma);
3479         vma = ERR_PTR(ret);
3480 err_unpin:
3481         i915_gem_object_unpin_pages(obj);
3482         return vma;
3483 }
3484
3485 bool
3486 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3487                         bool force)
3488 {
3489         /* If we don't have a page list set up, then we're not pinned
3490          * to GPU, and we can ignore the cache flush because it'll happen
3491          * again at bind time.
3492          */
3493         if (obj->pages == NULL)
3494                 return false;
3495
3496         /*
3497          * Stolen memory is always coherent with the GPU as it is explicitly
3498          * marked as wc by the system, or the system is cache-coherent.
3499          */
3500         if (obj->stolen)
3501                 return false;
3502
3503         /* If the GPU is snooping the contents of the CPU cache,
3504          * we do not need to manually clear the CPU cache lines.  However,
3505          * the caches are only snooped when the render cache is
3506          * flushed/invalidated.  As we always have to emit invalidations
3507          * and flushes when moving into and out of the RENDER domain, correct
3508          * snooping behaviour occurs naturally as the result of our domain
3509          * tracking.
3510          */
3511         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3512                 return false;
3513
3514         trace_i915_gem_object_clflush(obj);
3515         drm_clflush_sg(obj->pages);
3516
3517         return true;
3518 }
3519
3520 /** Flushes the GTT write domain for the object if it's dirty. */
3521 static void
3522 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3523 {
3524         uint32_t old_write_domain;
3525
3526         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3527                 return;
3528
3529         /* No actual flushing is required for the GTT write domain.  Writes
3530          * to it immediately go to main memory as far as we know, so there's
3531          * no chipset flush.  It also doesn't land in render cache.
3532          *
3533          * However, we do have to enforce the order so that all writes through
3534          * the GTT land before any writes to the device, such as updates to
3535          * the GATT itself.
3536          */
3537         wmb();
3538
3539         old_write_domain = obj->base.write_domain;
3540         obj->base.write_domain = 0;
3541
3542         trace_i915_gem_object_change_domain(obj,
3543                                             obj->base.read_domains,
3544                                             old_write_domain);
3545 }
3546
3547 /** Flushes the CPU write domain for the object if it's dirty. */
3548 static void
3549 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3550                                        bool force)
3551 {
3552         uint32_t old_write_domain;
3553
3554         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3555                 return;
3556
3557         if (i915_gem_clflush_object(obj, force))
3558                 i915_gem_chipset_flush(obj->base.dev);
3559
3560         old_write_domain = obj->base.write_domain;
3561         obj->base.write_domain = 0;
3562
3563         trace_i915_gem_object_change_domain(obj,
3564                                             obj->base.read_domains,
3565                                             old_write_domain);
3566 }
3567
3568 /**
3569  * Moves a single object to the GTT read, and possibly write domain.
3570  *
3571  * This function returns when the move is complete, including waiting on
3572  * flushes to occur.
3573  */
3574 int
3575 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3576 {
3577         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3578         uint32_t old_write_domain, old_read_domains;
3579         int ret;
3580
3581         /* Not valid to be called on unbound objects. */
3582         if (!i915_gem_obj_bound_any(obj))
3583                 return -EINVAL;
3584
3585         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3586                 return 0;
3587
3588         ret = i915_gem_object_wait_rendering(obj, !write);
3589         if (ret)
3590                 return ret;
3591
3592         i915_gem_object_retire(obj);
3593         i915_gem_object_flush_cpu_write_domain(obj, false);
3594
3595         /* Serialise direct access to this object with the barriers for
3596          * coherent writes from the GPU, by effectively invalidating the
3597          * GTT domain upon first access.
3598          */
3599         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3600                 mb();
3601
3602         old_write_domain = obj->base.write_domain;
3603         old_read_domains = obj->base.read_domains;
3604
3605         /* It should now be out of any other write domains, and we can update
3606          * the domain values for our changes.
3607          */
3608         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3609         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3610         if (write) {
3611                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3612                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3613                 obj->dirty = 1;
3614         }
3615
3616         trace_i915_gem_object_change_domain(obj,
3617                                             old_read_domains,
3618                                             old_write_domain);
3619
3620         /* And bump the LRU for this access */
3621         if (i915_gem_object_is_inactive(obj)) {
3622                 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3623                 if (vma)
3624                         list_move_tail(&vma->mm_list,
3625                                        &dev_priv->gtt.base.inactive_list);
3626
3627         }
3628
3629         return 0;
3630 }
3631
3632 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3633                                     enum i915_cache_level cache_level)
3634 {
3635         struct drm_device *dev = obj->base.dev;
3636         struct i915_vma *vma, *next;
3637         int ret;
3638
3639         if (obj->cache_level == cache_level)
3640                 return 0;
3641
3642         if (i915_gem_obj_is_pinned(obj)) {
3643                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3644                 return -EBUSY;
3645         }
3646
3647         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3648                 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3649                         ret = i915_vma_unbind(vma);
3650                         if (ret)
3651                                 return ret;
3652                 }
3653         }
3654
3655         if (i915_gem_obj_bound_any(obj)) {
3656                 ret = i915_gem_object_finish_gpu(obj);
3657                 if (ret)
3658                         return ret;
3659
3660                 i915_gem_object_finish_gtt(obj);
3661
3662                 /* Before SandyBridge, you could not use tiling or fence
3663                  * registers with snooped memory, so relinquish any fences
3664                  * currently pointing to our region in the aperture.
3665                  */
3666                 if (INTEL_INFO(dev)->gen < 6) {
3667                         ret = i915_gem_object_put_fence(obj);
3668                         if (ret)
3669                                 return ret;
3670                 }
3671
3672                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3673                         if (drm_mm_node_allocated(&vma->node))
3674                                 vma->bind_vma(vma, cache_level,
3675                                               obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3676         }
3677
3678         list_for_each_entry(vma, &obj->vma_list, vma_link)
3679                 vma->node.color = cache_level;
3680         obj->cache_level = cache_level;
3681
3682         if (cpu_write_needs_clflush(obj)) {
3683                 u32 old_read_domains, old_write_domain;
3684
3685                 /* If we're coming from LLC cached, then we haven't
3686                  * actually been tracking whether the data is in the
3687                  * CPU cache or not, since we only allow one bit set
3688                  * in obj->write_domain and have been skipping the clflushes.
3689                  * Just set it to the CPU cache for now.
3690                  */
3691                 i915_gem_object_retire(obj);
3692                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3693
3694                 old_read_domains = obj->base.read_domains;
3695                 old_write_domain = obj->base.write_domain;
3696
3697                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3698                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3699
3700                 trace_i915_gem_object_change_domain(obj,
3701                                                     old_read_domains,
3702                                                     old_write_domain);
3703         }
3704
3705         i915_gem_verify_gtt(dev);
3706         return 0;
3707 }
3708
3709 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3710                                struct drm_file *file)
3711 {
3712         struct drm_i915_gem_caching *args = data;
3713         struct drm_i915_gem_object *obj;
3714         int ret;
3715
3716         ret = i915_mutex_lock_interruptible(dev);
3717         if (ret)
3718                 return ret;
3719
3720         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3721         if (&obj->base == NULL) {
3722                 ret = -ENOENT;
3723                 goto unlock;
3724         }
3725
3726         switch (obj->cache_level) {
3727         case I915_CACHE_LLC:
3728         case I915_CACHE_L3_LLC:
3729                 args->caching = I915_CACHING_CACHED;
3730                 break;
3731
3732         case I915_CACHE_WT:
3733                 args->caching = I915_CACHING_DISPLAY;
3734                 break;
3735
3736         default:
3737                 args->caching = I915_CACHING_NONE;
3738                 break;
3739         }
3740
3741         drm_gem_object_unreference(&obj->base);
3742 unlock:
3743         mutex_unlock(&dev->struct_mutex);
3744         return ret;
3745 }
3746
3747 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3748                                struct drm_file *file)
3749 {
3750         struct drm_i915_gem_caching *args = data;
3751         struct drm_i915_gem_object *obj;
3752         enum i915_cache_level level;
3753         int ret;
3754
3755         switch (args->caching) {
3756         case I915_CACHING_NONE:
3757                 level = I915_CACHE_NONE;
3758                 break;
3759         case I915_CACHING_CACHED:
3760                 level = I915_CACHE_LLC;
3761                 break;
3762         case I915_CACHING_DISPLAY:
3763                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3764                 break;
3765         default:
3766                 return -EINVAL;
3767         }
3768
3769         ret = i915_mutex_lock_interruptible(dev);
3770         if (ret)
3771                 return ret;
3772
3773         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3774         if (&obj->base == NULL) {
3775                 ret = -ENOENT;
3776                 goto unlock;
3777         }
3778
3779         ret = i915_gem_object_set_cache_level(obj, level);
3780
3781         drm_gem_object_unreference(&obj->base);
3782 unlock:
3783         mutex_unlock(&dev->struct_mutex);
3784         return ret;
3785 }
3786
3787 static bool is_pin_display(struct drm_i915_gem_object *obj)
3788 {
3789         struct i915_vma *vma;
3790
3791         if (list_empty(&obj->vma_list))
3792                 return false;
3793
3794         vma = i915_gem_obj_to_ggtt(obj);
3795         if (!vma)
3796                 return false;
3797
3798         /* There are 3 sources that pin objects:
3799          *   1. The display engine (scanouts, sprites, cursors);
3800          *   2. Reservations for execbuffer;
3801          *   3. The user.
3802          *
3803          * We can ignore reservations as we hold the struct_mutex and
3804          * are only called outside of the reservation path.  The user
3805          * can only increment pin_count once, and so if after
3806          * subtracting the potential reference by the user, any pin_count
3807          * remains, it must be due to another use by the display engine.
3808          */
3809         return vma->pin_count - !!obj->user_pin_count;
3810 }
3811
3812 /*
3813  * Prepare buffer for display plane (scanout, cursors, etc).
3814  * Can be called from an uninterruptible phase (modesetting) and allows
3815  * any flushes to be pipelined (for pageflips).
3816  */
3817 int
3818 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3819                                      u32 alignment,
3820                                      struct intel_engine_cs *pipelined)
3821 {
3822         u32 old_read_domains, old_write_domain;
3823         bool was_pin_display;
3824         int ret;
3825
3826         if (pipelined != obj->ring) {
3827                 ret = i915_gem_object_sync(obj, pipelined);
3828                 if (ret)
3829                         return ret;
3830         }
3831
3832         /* Mark the pin_display early so that we account for the
3833          * display coherency whilst setting up the cache domains.
3834          */
3835         was_pin_display = obj->pin_display;
3836         obj->pin_display = true;
3837
3838         /* The display engine is not coherent with the LLC cache on gen6.  As
3839          * a result, we make sure that the pinning that is about to occur is
3840          * done with uncached PTEs. This is lowest common denominator for all
3841          * chipsets.
3842          *
3843          * However for gen6+, we could do better by using the GFDT bit instead
3844          * of uncaching, which would allow us to flush all the LLC-cached data
3845          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3846          */
3847         ret = i915_gem_object_set_cache_level(obj,
3848                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3849         if (ret)
3850                 goto err_unpin_display;
3851
3852         /* As the user may map the buffer once pinned in the display plane
3853          * (e.g. libkms for the bootup splash), we have to ensure that we
3854          * always use map_and_fenceable for all scanout buffers.
3855          */
3856         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3857         if (ret)
3858                 goto err_unpin_display;
3859
3860         i915_gem_object_flush_cpu_write_domain(obj, true);
3861
3862         old_write_domain = obj->base.write_domain;
3863         old_read_domains = obj->base.read_domains;
3864
3865         /* It should now be out of any other write domains, and we can update
3866          * the domain values for our changes.
3867          */
3868         obj->base.write_domain = 0;
3869         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3870
3871         trace_i915_gem_object_change_domain(obj,
3872                                             old_read_domains,
3873                                             old_write_domain);
3874
3875         return 0;
3876
3877 err_unpin_display:
3878         WARN_ON(was_pin_display != is_pin_display(obj));
3879         obj->pin_display = was_pin_display;
3880         return ret;
3881 }
3882
3883 void
3884 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3885 {
3886         i915_gem_object_ggtt_unpin(obj);
3887         obj->pin_display = is_pin_display(obj);
3888 }
3889
3890 int
3891 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3892 {
3893         int ret;
3894
3895         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3896                 return 0;
3897
3898         ret = i915_gem_object_wait_rendering(obj, false);
3899         if (ret)
3900                 return ret;
3901
3902         /* Ensure that we invalidate the GPU's caches and TLBs. */
3903         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3904         return 0;
3905 }
3906
3907 /**
3908  * Moves a single object to the CPU read, and possibly write domain.
3909  *
3910  * This function returns when the move is complete, including waiting on
3911  * flushes to occur.
3912  */
3913 int
3914 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3915 {
3916         uint32_t old_write_domain, old_read_domains;
3917         int ret;
3918
3919         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3920                 return 0;
3921
3922         ret = i915_gem_object_wait_rendering(obj, !write);
3923         if (ret)
3924                 return ret;
3925
3926         i915_gem_object_retire(obj);
3927         i915_gem_object_flush_gtt_write_domain(obj);
3928
3929         old_write_domain = obj->base.write_domain;
3930         old_read_domains = obj->base.read_domains;
3931
3932         /* Flush the CPU cache if it's still invalid. */
3933         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3934                 i915_gem_clflush_object(obj, false);
3935
3936                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3937         }
3938
3939         /* It should now be out of any other write domains, and we can update
3940          * the domain values for our changes.
3941          */
3942         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3943
3944         /* If we're writing through the CPU, then the GPU read domains will
3945          * need to be invalidated at next use.
3946          */
3947         if (write) {
3948                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3949                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3950         }
3951
3952         trace_i915_gem_object_change_domain(obj,
3953                                             old_read_domains,
3954                                             old_write_domain);
3955
3956         return 0;
3957 }
3958
3959 /* Throttle our rendering by waiting until the ring has completed our requests
3960  * emitted over 20 msec ago.
3961  *
3962  * Note that if we were to use the current jiffies each time around the loop,
3963  * we wouldn't escape the function with any frames outstanding if the time to
3964  * render a frame was over 20ms.
3965  *
3966  * This should get us reasonable parallelism between CPU and GPU but also
3967  * relatively low latency when blocking on a particular request to finish.
3968  */
3969 static int
3970 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3971 {
3972         struct drm_i915_private *dev_priv = dev->dev_private;
3973         struct drm_i915_file_private *file_priv = file->driver_priv;
3974         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3975         struct drm_i915_gem_request *request;
3976         struct intel_engine_cs *ring = NULL;
3977         unsigned reset_counter;
3978         u32 seqno = 0;
3979         int ret;
3980
3981         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3982         if (ret)
3983                 return ret;
3984
3985         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3986         if (ret)
3987                 return ret;
3988
3989         spin_lock(&file_priv->mm.lock);
3990         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3991                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3992                         break;
3993
3994                 ring = request->ring;
3995                 seqno = request->seqno;
3996         }
3997         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3998         spin_unlock(&file_priv->mm.lock);
3999
4000         if (seqno == 0)
4001                 return 0;
4002
4003         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4004         if (ret == 0)
4005                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4006
4007         return ret;
4008 }
4009
4010 static bool
4011 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4012 {
4013         struct drm_i915_gem_object *obj = vma->obj;
4014
4015         if (alignment &&
4016             vma->node.start & (alignment - 1))
4017                 return true;
4018
4019         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4020                 return true;
4021
4022         if (flags & PIN_OFFSET_BIAS &&
4023             vma->node.start < (flags & PIN_OFFSET_MASK))
4024                 return true;
4025
4026         return false;
4027 }
4028
4029 int
4030 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4031                     struct i915_address_space *vm,
4032                     uint32_t alignment,
4033                     uint64_t flags)
4034 {
4035         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4036         struct i915_vma *vma;
4037         int ret;
4038
4039         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4040                 return -ENODEV;
4041
4042         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4043                 return -EINVAL;
4044
4045         vma = i915_gem_obj_to_vma(obj, vm);
4046         if (vma) {
4047                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4048                         return -EBUSY;
4049
4050                 if (i915_vma_misplaced(vma, alignment, flags)) {
4051                         WARN(vma->pin_count,
4052                              "bo is already pinned with incorrect alignment:"
4053                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4054                              " obj->map_and_fenceable=%d\n",
4055                              i915_gem_obj_offset(obj, vm), alignment,
4056                              !!(flags & PIN_MAPPABLE),
4057                              obj->map_and_fenceable);
4058                         ret = i915_vma_unbind(vma);
4059                         if (ret)
4060                                 return ret;
4061
4062                         vma = NULL;
4063                 }
4064         }
4065
4066         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4067                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4068                 if (IS_ERR(vma))
4069                         return PTR_ERR(vma);
4070         }
4071
4072         if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
4073                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4074
4075         vma->pin_count++;
4076         if (flags & PIN_MAPPABLE)
4077                 obj->pin_mappable |= true;
4078
4079         return 0;
4080 }
4081
4082 void
4083 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4084 {
4085         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4086
4087         BUG_ON(!vma);
4088         BUG_ON(vma->pin_count == 0);
4089         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4090
4091         if (--vma->pin_count == 0)
4092                 obj->pin_mappable = false;
4093 }
4094
4095 bool
4096 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4097 {
4098         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4099                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4100                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4101
4102                 WARN_ON(!ggtt_vma ||
4103                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4104                         ggtt_vma->pin_count);
4105                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4106                 return true;
4107         } else
4108                 return false;
4109 }
4110
4111 void
4112 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4113 {
4114         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4115                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4116                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4117                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4118         }
4119 }
4120
4121 int
4122 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4123                    struct drm_file *file)
4124 {
4125         struct drm_i915_gem_pin *args = data;
4126         struct drm_i915_gem_object *obj;
4127         int ret;
4128
4129         if (INTEL_INFO(dev)->gen >= 6)
4130                 return -ENODEV;
4131
4132         ret = i915_mutex_lock_interruptible(dev);
4133         if (ret)
4134                 return ret;
4135
4136         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4137         if (&obj->base == NULL) {
4138                 ret = -ENOENT;
4139                 goto unlock;
4140         }
4141
4142         if (obj->madv != I915_MADV_WILLNEED) {
4143                 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4144                 ret = -EFAULT;
4145                 goto out;
4146         }
4147
4148         if (obj->pin_filp != NULL && obj->pin_filp != file) {
4149                 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4150                           args->handle);
4151                 ret = -EINVAL;
4152                 goto out;
4153         }
4154
4155         if (obj->user_pin_count == ULONG_MAX) {
4156                 ret = -EBUSY;
4157                 goto out;
4158         }
4159
4160         if (obj->user_pin_count == 0) {
4161                 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4162                 if (ret)
4163                         goto out;
4164         }
4165
4166         obj->user_pin_count++;
4167         obj->pin_filp = file;
4168
4169         args->offset = i915_gem_obj_ggtt_offset(obj);
4170 out:
4171         drm_gem_object_unreference(&obj->base);
4172 unlock:
4173         mutex_unlock(&dev->struct_mutex);
4174         return ret;
4175 }
4176
4177 int
4178 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4179                      struct drm_file *file)
4180 {
4181         struct drm_i915_gem_pin *args = data;
4182         struct drm_i915_gem_object *obj;
4183         int ret;
4184
4185         ret = i915_mutex_lock_interruptible(dev);
4186         if (ret)
4187                 return ret;
4188
4189         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4190         if (&obj->base == NULL) {
4191                 ret = -ENOENT;
4192                 goto unlock;
4193         }
4194
4195         if (obj->pin_filp != file) {
4196                 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4197                           args->handle);
4198                 ret = -EINVAL;
4199                 goto out;
4200         }
4201         obj->user_pin_count--;
4202         if (obj->user_pin_count == 0) {
4203                 obj->pin_filp = NULL;
4204                 i915_gem_object_ggtt_unpin(obj);
4205         }
4206
4207 out:
4208         drm_gem_object_unreference(&obj->base);
4209 unlock:
4210         mutex_unlock(&dev->struct_mutex);
4211         return ret;
4212 }
4213
4214 int
4215 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4216                     struct drm_file *file)
4217 {
4218         struct drm_i915_gem_busy *args = data;
4219         struct drm_i915_gem_object *obj;
4220         int ret;
4221
4222         ret = i915_mutex_lock_interruptible(dev);
4223         if (ret)
4224                 return ret;
4225
4226         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4227         if (&obj->base == NULL) {
4228                 ret = -ENOENT;
4229                 goto unlock;
4230         }
4231
4232         /* Count all active objects as busy, even if they are currently not used
4233          * by the gpu. Users of this interface expect objects to eventually
4234          * become non-busy without any further actions, therefore emit any
4235          * necessary flushes here.
4236          */
4237         ret = i915_gem_object_flush_active(obj);
4238
4239         args->busy = obj->active;
4240         if (obj->ring) {
4241                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4242                 args->busy |= intel_ring_flag(obj->ring) << 16;
4243         }
4244
4245         drm_gem_object_unreference(&obj->base);
4246 unlock:
4247         mutex_unlock(&dev->struct_mutex);
4248         return ret;
4249 }
4250
4251 int
4252 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4253                         struct drm_file *file_priv)
4254 {
4255         return i915_gem_ring_throttle(dev, file_priv);
4256 }
4257
4258 int
4259 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4260                        struct drm_file *file_priv)
4261 {
4262         struct drm_i915_gem_madvise *args = data;
4263         struct drm_i915_gem_object *obj;
4264         int ret;
4265
4266         switch (args->madv) {
4267         case I915_MADV_DONTNEED:
4268         case I915_MADV_WILLNEED:
4269             break;
4270         default:
4271             return -EINVAL;
4272         }
4273
4274         ret = i915_mutex_lock_interruptible(dev);
4275         if (ret)
4276                 return ret;
4277
4278         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4279         if (&obj->base == NULL) {
4280                 ret = -ENOENT;
4281                 goto unlock;
4282         }
4283
4284         if (i915_gem_obj_is_pinned(obj)) {
4285                 ret = -EINVAL;
4286                 goto out;
4287         }
4288
4289         if (obj->madv != __I915_MADV_PURGED)
4290                 obj->madv = args->madv;
4291
4292         /* if the object is no longer attached, discard its backing storage */
4293         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4294                 i915_gem_object_truncate(obj);
4295
4296         args->retained = obj->madv != __I915_MADV_PURGED;
4297
4298 out:
4299         drm_gem_object_unreference(&obj->base);
4300 unlock:
4301         mutex_unlock(&dev->struct_mutex);
4302         return ret;
4303 }
4304
4305 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4306                           const struct drm_i915_gem_object_ops *ops)
4307 {
4308         INIT_LIST_HEAD(&obj->global_list);
4309         INIT_LIST_HEAD(&obj->ring_list);
4310         INIT_LIST_HEAD(&obj->obj_exec_link);
4311         INIT_LIST_HEAD(&obj->vma_list);
4312
4313         obj->ops = ops;
4314
4315         obj->fence_reg = I915_FENCE_REG_NONE;
4316         obj->madv = I915_MADV_WILLNEED;
4317         /* Avoid an unnecessary call to unbind on the first bind. */
4318         obj->map_and_fenceable = true;
4319
4320         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4321 }
4322
4323 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4324         .get_pages = i915_gem_object_get_pages_gtt,
4325         .put_pages = i915_gem_object_put_pages_gtt,
4326 };
4327
4328 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4329                                                   size_t size)
4330 {
4331         struct drm_i915_gem_object *obj;
4332         struct address_space *mapping;
4333         gfp_t mask;
4334
4335         obj = i915_gem_object_alloc(dev);
4336         if (obj == NULL)
4337                 return NULL;
4338
4339         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4340                 i915_gem_object_free(obj);
4341                 return NULL;
4342         }
4343
4344         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4345         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4346                 /* 965gm cannot relocate objects above 4GiB. */
4347                 mask &= ~__GFP_HIGHMEM;
4348                 mask |= __GFP_DMA32;
4349         }
4350
4351         mapping = file_inode(obj->base.filp)->i_mapping;
4352         mapping_set_gfp_mask(mapping, mask);
4353
4354         i915_gem_object_init(obj, &i915_gem_object_ops);
4355
4356         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4357         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4358
4359         if (HAS_LLC(dev)) {
4360                 /* On some devices, we can have the GPU use the LLC (the CPU
4361                  * cache) for about a 10% performance improvement
4362                  * compared to uncached.  Graphics requests other than
4363                  * display scanout are coherent with the CPU in
4364                  * accessing this cache.  This means in this mode we
4365                  * don't need to clflush on the CPU side, and on the
4366                  * GPU side we only need to flush internal caches to
4367                  * get data visible to the CPU.
4368                  *
4369                  * However, we maintain the display planes as UC, and so
4370                  * need to rebind when first used as such.
4371                  */
4372                 obj->cache_level = I915_CACHE_LLC;
4373         } else
4374                 obj->cache_level = I915_CACHE_NONE;
4375
4376         trace_i915_gem_object_create(obj);
4377
4378         return obj;
4379 }
4380
4381 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4382 {
4383         /* If we are the last user of the backing storage (be it shmemfs
4384          * pages or stolen etc), we know that the pages are going to be
4385          * immediately released. In this case, we can then skip copying
4386          * back the contents from the GPU.
4387          */
4388
4389         if (obj->madv != I915_MADV_WILLNEED)
4390                 return false;
4391
4392         if (obj->base.filp == NULL)
4393                 return true;
4394
4395         /* At first glance, this looks racy, but then again so would be
4396          * userspace racing mmap against close. However, the first external
4397          * reference to the filp can only be obtained through the
4398          * i915_gem_mmap_ioctl() which safeguards us against the user
4399          * acquiring such a reference whilst we are in the middle of
4400          * freeing the object.
4401          */
4402         return atomic_long_read(&obj->base.filp->f_count) == 1;
4403 }
4404
4405 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4406 {
4407         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4408         struct drm_device *dev = obj->base.dev;
4409         struct drm_i915_private *dev_priv = dev->dev_private;
4410         struct i915_vma *vma, *next;
4411
4412         intel_runtime_pm_get(dev_priv);
4413
4414         trace_i915_gem_object_destroy(obj);
4415
4416         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4417                 int ret;
4418
4419                 vma->pin_count = 0;
4420                 ret = i915_vma_unbind(vma);
4421                 if (WARN_ON(ret == -ERESTARTSYS)) {
4422                         bool was_interruptible;
4423
4424                         was_interruptible = dev_priv->mm.interruptible;
4425                         dev_priv->mm.interruptible = false;
4426
4427                         WARN_ON(i915_vma_unbind(vma));
4428
4429                         dev_priv->mm.interruptible = was_interruptible;
4430                 }
4431         }
4432
4433         i915_gem_object_detach_phys(obj);
4434
4435         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4436          * before progressing. */
4437         if (obj->stolen)
4438                 i915_gem_object_unpin_pages(obj);
4439
4440         if (WARN_ON(obj->pages_pin_count))
4441                 obj->pages_pin_count = 0;
4442         if (discard_backing_storage(obj))
4443                 obj->madv = I915_MADV_DONTNEED;
4444         i915_gem_object_put_pages(obj);
4445         i915_gem_object_free_mmap_offset(obj);
4446         i915_gem_object_release_stolen(obj);
4447
4448         BUG_ON(obj->pages);
4449
4450         if (obj->base.import_attach)
4451                 drm_prime_gem_destroy(&obj->base, NULL);
4452
4453         if (obj->ops->release)
4454                 obj->ops->release(obj);
4455
4456         drm_gem_object_release(&obj->base);
4457         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4458
4459         kfree(obj->bit_17);
4460         i915_gem_object_free(obj);
4461
4462         intel_runtime_pm_put(dev_priv);
4463 }
4464
4465 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4466                                      struct i915_address_space *vm)
4467 {
4468         struct i915_vma *vma;
4469         list_for_each_entry(vma, &obj->vma_list, vma_link)
4470                 if (vma->vm == vm)
4471                         return vma;
4472
4473         return NULL;
4474 }
4475
4476 void i915_gem_vma_destroy(struct i915_vma *vma)
4477 {
4478         WARN_ON(vma->node.allocated);
4479
4480         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4481         if (!list_empty(&vma->exec_list))
4482                 return;
4483
4484         list_del(&vma->vma_link);
4485
4486         kfree(vma);
4487 }
4488
4489 static void
4490 i915_gem_stop_ringbuffers(struct drm_device *dev)
4491 {
4492         struct drm_i915_private *dev_priv = dev->dev_private;
4493         struct intel_engine_cs *ring;
4494         int i;
4495
4496         for_each_ring(ring, dev_priv, i)
4497                 intel_stop_ring_buffer(ring);
4498 }
4499
4500 int
4501 i915_gem_suspend(struct drm_device *dev)
4502 {
4503         struct drm_i915_private *dev_priv = dev->dev_private;
4504         int ret = 0;
4505
4506         mutex_lock(&dev->struct_mutex);
4507         if (dev_priv->ums.mm_suspended)
4508                 goto err;
4509
4510         ret = i915_gpu_idle(dev);
4511         if (ret)
4512                 goto err;
4513
4514         i915_gem_retire_requests(dev);
4515
4516         /* Under UMS, be paranoid and evict. */
4517         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4518                 i915_gem_evict_everything(dev);
4519
4520         i915_kernel_lost_context(dev);
4521         i915_gem_stop_ringbuffers(dev);
4522
4523         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4524          * We need to replace this with a semaphore, or something.
4525          * And not confound ums.mm_suspended!
4526          */
4527         dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4528                                                              DRIVER_MODESET);
4529         mutex_unlock(&dev->struct_mutex);
4530
4531         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4532         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4533         cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4534
4535         return 0;
4536
4537 err:
4538         mutex_unlock(&dev->struct_mutex);
4539         return ret;
4540 }
4541
4542 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4543 {
4544         struct drm_device *dev = ring->dev;
4545         struct drm_i915_private *dev_priv = dev->dev_private;
4546         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4547         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4548         int i, ret;
4549
4550         if (!HAS_L3_DPF(dev) || !remap_info)
4551                 return 0;
4552
4553         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4554         if (ret)
4555                 return ret;
4556
4557         /*
4558          * Note: We do not worry about the concurrent register cacheline hang
4559          * here because no other code should access these registers other than
4560          * at initialization time.
4561          */
4562         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4563                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4564                 intel_ring_emit(ring, reg_base + i);
4565                 intel_ring_emit(ring, remap_info[i/4]);
4566         }
4567
4568         intel_ring_advance(ring);
4569
4570         return ret;
4571 }
4572
4573 void i915_gem_init_swizzling(struct drm_device *dev)
4574 {
4575         struct drm_i915_private *dev_priv = dev->dev_private;
4576
4577         if (INTEL_INFO(dev)->gen < 5 ||
4578             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4579                 return;
4580
4581         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4582                                  DISP_TILE_SURFACE_SWIZZLING);
4583
4584         if (IS_GEN5(dev))
4585                 return;
4586
4587         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4588         if (IS_GEN6(dev))
4589                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4590         else if (IS_GEN7(dev))
4591                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4592         else if (IS_GEN8(dev))
4593                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4594         else
4595                 BUG();
4596 }
4597
4598 static bool
4599 intel_enable_blt(struct drm_device *dev)
4600 {
4601         if (!HAS_BLT(dev))
4602                 return false;
4603
4604         /* The blitter was dysfunctional on early prototypes */
4605         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4606                 DRM_INFO("BLT not supported on this pre-production hardware;"
4607                          " graphics performance will be degraded.\n");
4608                 return false;
4609         }
4610
4611         return true;
4612 }
4613
4614 static int i915_gem_init_rings(struct drm_device *dev)
4615 {
4616         struct drm_i915_private *dev_priv = dev->dev_private;
4617         int ret;
4618
4619         ret = intel_init_render_ring_buffer(dev);
4620         if (ret)
4621                 return ret;
4622
4623         if (HAS_BSD(dev)) {
4624                 ret = intel_init_bsd_ring_buffer(dev);
4625                 if (ret)
4626                         goto cleanup_render_ring;
4627         }
4628
4629         if (intel_enable_blt(dev)) {
4630                 ret = intel_init_blt_ring_buffer(dev);
4631                 if (ret)
4632                         goto cleanup_bsd_ring;
4633         }
4634
4635         if (HAS_VEBOX(dev)) {
4636                 ret = intel_init_vebox_ring_buffer(dev);
4637                 if (ret)
4638                         goto cleanup_blt_ring;
4639         }
4640
4641         if (HAS_BSD2(dev)) {
4642                 ret = intel_init_bsd2_ring_buffer(dev);
4643                 if (ret)
4644                         goto cleanup_vebox_ring;
4645         }
4646
4647         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4648         if (ret)
4649                 goto cleanup_bsd2_ring;
4650
4651         return 0;
4652
4653 cleanup_bsd2_ring:
4654         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4655 cleanup_vebox_ring:
4656         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4657 cleanup_blt_ring:
4658         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4659 cleanup_bsd_ring:
4660         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4661 cleanup_render_ring:
4662         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4663
4664         return ret;
4665 }
4666
4667 int
4668 i915_gem_init_hw(struct drm_device *dev)
4669 {
4670         struct drm_i915_private *dev_priv = dev->dev_private;
4671         int ret, i;
4672
4673         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4674                 return -EIO;
4675
4676         if (dev_priv->ellc_size)
4677                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4678
4679         if (IS_HASWELL(dev))
4680                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4681                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4682
4683         if (HAS_PCH_NOP(dev)) {
4684                 if (IS_IVYBRIDGE(dev)) {
4685                         u32 temp = I915_READ(GEN7_MSG_CTL);
4686                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4687                         I915_WRITE(GEN7_MSG_CTL, temp);
4688                 } else if (INTEL_INFO(dev)->gen >= 7) {
4689                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4690                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4691                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4692                 }
4693         }
4694
4695         i915_gem_init_swizzling(dev);
4696
4697         ret = i915_gem_init_rings(dev);
4698         if (ret)
4699                 return ret;
4700
4701         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4702                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4703
4704         /*
4705          * XXX: Contexts should only be initialized once. Doing a switch to the
4706          * default context switch however is something we'd like to do after
4707          * reset or thaw (the latter may not actually be necessary for HW, but
4708          * goes with our code better). Context switching requires rings (for
4709          * the do_switch), but before enabling PPGTT. So don't move this.
4710          */
4711         ret = i915_gem_context_enable(dev_priv);
4712         if (ret && ret != -EIO) {
4713                 DRM_ERROR("Context enable failed %d\n", ret);
4714                 i915_gem_cleanup_ringbuffer(dev);
4715         }
4716
4717         return ret;
4718 }
4719
4720 int i915_gem_init(struct drm_device *dev)
4721 {
4722         struct drm_i915_private *dev_priv = dev->dev_private;
4723         int ret;
4724
4725         mutex_lock(&dev->struct_mutex);
4726
4727         if (IS_VALLEYVIEW(dev)) {
4728                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4729                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4730                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4731                               VLV_GTLC_ALLOWWAKEACK), 10))
4732                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4733         }
4734
4735         i915_gem_init_userptr(dev);
4736         i915_gem_init_global_gtt(dev);
4737
4738         ret = i915_gem_context_init(dev);
4739         if (ret) {
4740                 mutex_unlock(&dev->struct_mutex);
4741                 return ret;
4742         }
4743
4744         ret = i915_gem_init_hw(dev);
4745         if (ret == -EIO) {
4746                 /* Allow ring initialisation to fail by marking the GPU as
4747                  * wedged. But we only want to do this where the GPU is angry,
4748                  * for all other failure, such as an allocation failure, bail.
4749                  */
4750                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4751                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4752                 ret = 0;
4753         }
4754         mutex_unlock(&dev->struct_mutex);
4755
4756         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4757         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4758                 dev_priv->dri1.allow_batchbuffer = 1;
4759         return ret;
4760 }
4761
4762 void
4763 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4764 {
4765         struct drm_i915_private *dev_priv = dev->dev_private;
4766         struct intel_engine_cs *ring;
4767         int i;
4768
4769         for_each_ring(ring, dev_priv, i)
4770                 intel_cleanup_ring_buffer(ring);
4771 }
4772
4773 int
4774 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4775                        struct drm_file *file_priv)
4776 {
4777         struct drm_i915_private *dev_priv = dev->dev_private;
4778         int ret;
4779
4780         if (drm_core_check_feature(dev, DRIVER_MODESET))
4781                 return 0;
4782
4783         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4784                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4785                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4786         }
4787
4788         mutex_lock(&dev->struct_mutex);
4789         dev_priv->ums.mm_suspended = 0;
4790
4791         ret = i915_gem_init_hw(dev);
4792         if (ret != 0) {
4793                 mutex_unlock(&dev->struct_mutex);
4794                 return ret;
4795         }
4796
4797         BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4798
4799         ret = drm_irq_install(dev, dev->pdev->irq);
4800         if (ret)
4801                 goto cleanup_ringbuffer;
4802         mutex_unlock(&dev->struct_mutex);
4803
4804         return 0;
4805
4806 cleanup_ringbuffer:
4807         i915_gem_cleanup_ringbuffer(dev);
4808         dev_priv->ums.mm_suspended = 1;
4809         mutex_unlock(&dev->struct_mutex);
4810
4811         return ret;
4812 }
4813
4814 int
4815 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4816                        struct drm_file *file_priv)
4817 {
4818         if (drm_core_check_feature(dev, DRIVER_MODESET))
4819                 return 0;
4820
4821         mutex_lock(&dev->struct_mutex);
4822         drm_irq_uninstall(dev);
4823         mutex_unlock(&dev->struct_mutex);
4824
4825         return i915_gem_suspend(dev);
4826 }
4827
4828 void
4829 i915_gem_lastclose(struct drm_device *dev)
4830 {
4831         int ret;
4832
4833         if (drm_core_check_feature(dev, DRIVER_MODESET))
4834                 return;
4835
4836         ret = i915_gem_suspend(dev);
4837         if (ret)
4838                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4839 }
4840
4841 static void
4842 init_ring_lists(struct intel_engine_cs *ring)
4843 {
4844         INIT_LIST_HEAD(&ring->active_list);
4845         INIT_LIST_HEAD(&ring->request_list);
4846 }
4847
4848 void i915_init_vm(struct drm_i915_private *dev_priv,
4849                   struct i915_address_space *vm)
4850 {
4851         if (!i915_is_ggtt(vm))
4852                 drm_mm_init(&vm->mm, vm->start, vm->total);
4853         vm->dev = dev_priv->dev;
4854         INIT_LIST_HEAD(&vm->active_list);
4855         INIT_LIST_HEAD(&vm->inactive_list);
4856         INIT_LIST_HEAD(&vm->global_link);
4857         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4858 }
4859
4860 void
4861 i915_gem_load(struct drm_device *dev)
4862 {
4863         struct drm_i915_private *dev_priv = dev->dev_private;
4864         int i;
4865
4866         dev_priv->slab =
4867                 kmem_cache_create("i915_gem_object",
4868                                   sizeof(struct drm_i915_gem_object), 0,
4869                                   SLAB_HWCACHE_ALIGN,
4870                                   NULL);
4871
4872         INIT_LIST_HEAD(&dev_priv->vm_list);
4873         i915_init_vm(dev_priv, &dev_priv->gtt.base);
4874
4875         INIT_LIST_HEAD(&dev_priv->context_list);
4876         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4877         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4878         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4879         for (i = 0; i < I915_NUM_RINGS; i++)
4880                 init_ring_lists(&dev_priv->ring[i]);
4881         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4882                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4883         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4884                           i915_gem_retire_work_handler);
4885         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4886                           i915_gem_idle_work_handler);
4887         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4888
4889         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4890         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4891                 I915_WRITE(MI_ARB_STATE,
4892                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4893         }
4894
4895         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4896
4897         /* Old X drivers will take 0-2 for front, back, depth buffers */
4898         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4899                 dev_priv->fence_reg_start = 3;
4900
4901         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4902                 dev_priv->num_fence_regs = 32;
4903         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4904                 dev_priv->num_fence_regs = 16;
4905         else
4906                 dev_priv->num_fence_regs = 8;
4907
4908         /* Initialize fence registers to zero */
4909         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4910         i915_gem_restore_fences(dev);
4911
4912         i915_gem_detect_bit_6_swizzle(dev);
4913         init_waitqueue_head(&dev_priv->pending_flip_queue);
4914
4915         dev_priv->mm.interruptible = true;
4916
4917         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4918         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4919         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4920         register_shrinker(&dev_priv->mm.shrinker);
4921
4922         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4923         register_oom_notifier(&dev_priv->mm.oom_notifier);
4924 }
4925
4926 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4927 {
4928         struct drm_i915_file_private *file_priv = file->driver_priv;
4929
4930         cancel_delayed_work_sync(&file_priv->mm.idle_work);
4931
4932         /* Clean up our request list when the client is going away, so that
4933          * later retire_requests won't dereference our soon-to-be-gone
4934          * file_priv.
4935          */
4936         spin_lock(&file_priv->mm.lock);
4937         while (!list_empty(&file_priv->mm.request_list)) {
4938                 struct drm_i915_gem_request *request;
4939
4940                 request = list_first_entry(&file_priv->mm.request_list,
4941                                            struct drm_i915_gem_request,
4942                                            client_list);
4943                 list_del(&request->client_list);
4944                 request->file_priv = NULL;
4945         }
4946         spin_unlock(&file_priv->mm.lock);
4947 }
4948
4949 static void
4950 i915_gem_file_idle_work_handler(struct work_struct *work)
4951 {
4952         struct drm_i915_file_private *file_priv =
4953                 container_of(work, typeof(*file_priv), mm.idle_work.work);
4954
4955         atomic_set(&file_priv->rps_wait_boost, false);
4956 }
4957
4958 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4959 {
4960         struct drm_i915_file_private *file_priv;
4961         int ret;
4962
4963         DRM_DEBUG_DRIVER("\n");
4964
4965         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4966         if (!file_priv)
4967                 return -ENOMEM;
4968
4969         file->driver_priv = file_priv;
4970         file_priv->dev_priv = dev->dev_private;
4971         file_priv->file = file;
4972
4973         spin_lock_init(&file_priv->mm.lock);
4974         INIT_LIST_HEAD(&file_priv->mm.request_list);
4975         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4976                           i915_gem_file_idle_work_handler);
4977
4978         ret = i915_gem_context_open(dev, file);
4979         if (ret)
4980                 kfree(file_priv);
4981
4982         return ret;
4983 }
4984
4985 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4986 {
4987         if (!mutex_is_locked(mutex))
4988                 return false;
4989
4990 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4991         return mutex->owner == task;
4992 #else
4993         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4994         return false;
4995 #endif
4996 }
4997
4998 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
4999 {
5000         if (!mutex_trylock(&dev->struct_mutex)) {
5001                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5002                         return false;
5003
5004                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5005                         return false;
5006
5007                 *unlock = false;
5008         } else
5009                 *unlock = true;
5010
5011         return true;
5012 }
5013
5014 static int num_vma_bound(struct drm_i915_gem_object *obj)
5015 {
5016         struct i915_vma *vma;
5017         int count = 0;
5018
5019         list_for_each_entry(vma, &obj->vma_list, vma_link)
5020                 if (drm_mm_node_allocated(&vma->node))
5021                         count++;
5022
5023         return count;
5024 }
5025
5026 static unsigned long
5027 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5028 {
5029         struct drm_i915_private *dev_priv =
5030                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5031         struct drm_device *dev = dev_priv->dev;
5032         struct drm_i915_gem_object *obj;
5033         unsigned long count;
5034         bool unlock;
5035
5036         if (!i915_gem_shrinker_lock(dev, &unlock))
5037                 return 0;
5038
5039         count = 0;
5040         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5041                 if (obj->pages_pin_count == 0)
5042                         count += obj->base.size >> PAGE_SHIFT;
5043
5044         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5045                 if (!i915_gem_obj_is_pinned(obj) &&
5046                     obj->pages_pin_count == num_vma_bound(obj))
5047                         count += obj->base.size >> PAGE_SHIFT;
5048         }
5049
5050         if (unlock)
5051                 mutex_unlock(&dev->struct_mutex);
5052
5053         return count;
5054 }
5055
5056 /* All the new VM stuff */
5057 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5058                                   struct i915_address_space *vm)
5059 {
5060         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5061         struct i915_vma *vma;
5062
5063         if (!dev_priv->mm.aliasing_ppgtt ||
5064             vm == &dev_priv->mm.aliasing_ppgtt->base)
5065                 vm = &dev_priv->gtt.base;
5066
5067         BUG_ON(list_empty(&o->vma_list));
5068         list_for_each_entry(vma, &o->vma_list, vma_link) {
5069                 if (vma->vm == vm)
5070                         return vma->node.start;
5071
5072         }
5073         return -1;
5074 }
5075
5076 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5077                         struct i915_address_space *vm)
5078 {
5079         struct i915_vma *vma;
5080
5081         list_for_each_entry(vma, &o->vma_list, vma_link)
5082                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5083                         return true;
5084
5085         return false;
5086 }
5087
5088 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5089 {
5090         struct i915_vma *vma;
5091
5092         list_for_each_entry(vma, &o->vma_list, vma_link)
5093                 if (drm_mm_node_allocated(&vma->node))
5094                         return true;
5095
5096         return false;
5097 }
5098
5099 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5100                                 struct i915_address_space *vm)
5101 {
5102         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5103         struct i915_vma *vma;
5104
5105         if (!dev_priv->mm.aliasing_ppgtt ||
5106             vm == &dev_priv->mm.aliasing_ppgtt->base)
5107                 vm = &dev_priv->gtt.base;
5108
5109         BUG_ON(list_empty(&o->vma_list));
5110
5111         list_for_each_entry(vma, &o->vma_list, vma_link)
5112                 if (vma->vm == vm)
5113                         return vma->node.size;
5114
5115         return 0;
5116 }
5117
5118 static unsigned long
5119 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5120 {
5121         struct drm_i915_private *dev_priv =
5122                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5123         struct drm_device *dev = dev_priv->dev;
5124         unsigned long freed;
5125         bool unlock;
5126
5127         if (!i915_gem_shrinker_lock(dev, &unlock))
5128                 return SHRINK_STOP;
5129
5130         freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5131         if (freed < sc->nr_to_scan)
5132                 freed += __i915_gem_shrink(dev_priv,
5133                                            sc->nr_to_scan - freed,
5134                                            false);
5135         if (unlock)
5136                 mutex_unlock(&dev->struct_mutex);
5137
5138         return freed;
5139 }
5140
5141 static int
5142 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5143 {
5144         struct drm_i915_private *dev_priv =
5145                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5146         struct drm_device *dev = dev_priv->dev;
5147         struct drm_i915_gem_object *obj;
5148         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5149         unsigned long pinned, bound, unbound, freed;
5150         bool was_interruptible;
5151         bool unlock;
5152
5153         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout)
5154                 schedule_timeout_killable(1);
5155         if (timeout == 0) {
5156                 pr_err("Unable to purge GPU memory due lock contention.\n");
5157                 return NOTIFY_DONE;
5158         }
5159
5160         was_interruptible = dev_priv->mm.interruptible;
5161         dev_priv->mm.interruptible = false;
5162
5163         freed = i915_gem_shrink_all(dev_priv);
5164
5165         dev_priv->mm.interruptible = was_interruptible;
5166
5167         /* Because we may be allocating inside our own driver, we cannot
5168          * assert that there are no objects with pinned pages that are not
5169          * being pointed to by hardware.
5170          */
5171         unbound = bound = pinned = 0;
5172         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5173                 if (!obj->base.filp) /* not backed by a freeable object */
5174                         continue;
5175
5176                 if (obj->pages_pin_count)
5177                         pinned += obj->base.size;
5178                 else
5179                         unbound += obj->base.size;
5180         }
5181         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5182                 if (!obj->base.filp)
5183                         continue;
5184
5185                 if (obj->pages_pin_count)
5186                         pinned += obj->base.size;
5187                 else
5188                         bound += obj->base.size;
5189         }
5190
5191         if (unlock)
5192                 mutex_unlock(&dev->struct_mutex);
5193
5194         pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5195                 freed, pinned);
5196         if (unbound || bound)
5197                 pr_err("%lu and %lu bytes still available in the "
5198                        "bound and unbound GPU page lists.\n",
5199                        bound, unbound);
5200
5201         *(unsigned long *)ptr += freed;
5202         return NOTIFY_DONE;
5203 }
5204
5205 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5206 {
5207         struct i915_vma *vma;
5208
5209         /* This WARN has probably outlived its usefulness (callers already
5210          * WARN if they don't find the GGTT vma they expect). When removing,
5211          * remember to remove the pre-check in is_pin_display() as well */
5212         if (WARN_ON(list_empty(&obj->vma_list)))
5213                 return NULL;
5214
5215         vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5216         if (vma->vm != obj_to_ggtt(obj))
5217                 return NULL;
5218
5219         return vma;
5220 }