drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <drm/drmP.h>
  28 #include <drm/i915_drm.h>
  29 #include "i915_drv.h"
  30 #include "i915_vgpu.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33
  34 /**
  35  * DOC: Global GTT views
  36  *
  37  * Background and previous state
  38  *
  39  * Historically objects could exists (be bound) in global GTT space only as
  40  * singular instances with a view representing all of the object's backing pages
  41  * in a linear fashion. This view will be called a normal view.
  42  *
  43  * To support multiple views of the same object, where the number of mapped
  44  * pages is not equal to the backing store, or where the layout of the pages
  45  * is not linear, concept of a GGTT view was added.
  46  *
  47  * One example of an alternative view is a stereo display driven by a single
  48  * image. In this case we would have a framebuffer looking like this
  49  * (2x2 pages):
  50  *
  51  *    12
  52  *    34
  53  *
  54  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  55  * rendering. In contrast, fed to the display engine would be an alternative
  56  * view which could look something like this:
  57  *
  58  *   1212
  59  *   3434
  60  *
  61  * In this example both the size and layout of pages in the alternative view is
  62  * different from the normal view.
  63  *
  64  * Implementation and usage
  65  *
  66  * GGTT views are implemented using VMAs and are distinguished via enum
  67  * i915_ggtt_view_type and struct i915_ggtt_view.
  68  *
  69  * A new flavour of core GEM functions which work with GGTT bound objects were
  70  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  71  * renaming  in large amounts of code. They take the struct i915_ggtt_view
  72  * parameter encapsulating all metadata required to implement a view.
  73  *
  74  * As a helper for callers which are only interested in the normal view,
  75  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  76  * GEM API functions, the ones not taking the view parameter, are operating on,
  77  * or with the normal GGTT view.
  78  *
  79  * Code wanting to add or use a new GGTT view needs to:
  80  *
  81  * 1. Add a new enum with a suitable name.
  82  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  83  * 3. Add support to i915_get_vma_pages().
  84  *
  85  * New views are required to build a scatter-gather table from within the
  86  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  87  * exists for the lifetime of an VMA.
  88  *
  89  * Core API is designed to have copy semantics which means that passed in
  90  * struct i915_ggtt_view does not need to be persistent (left around after
  91  * calling the core API functions).
  92  *
  93  */
  94
  95 static int
  96 i915_get_ggtt_vma_pages(struct i915_vma *vma);
  97
  98 const struct i915_ggtt_view i915_ggtt_view_normal;
  99 const struct i915_ggtt_view i915_ggtt_view_rotated = {
 100         .type = I915_GGTT_VIEW_ROTATED
 101 };
 102
 103 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 104 {
 105         bool has_aliasing_ppgtt;
 106         bool has_full_ppgtt;
 107
 108         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 109         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 110
 111         if (intel_vgpu_active(dev))
 112                 has_full_ppgtt = false; /* emulation is too hard */
 113
 114         /*
 115          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 116          * execlists, the sole mechanism available to submit work.
 117          */
 118         if (INTEL_INFO(dev)->gen < 9 &&
 119             (enable_ppgtt == 0 || !has_aliasing_ppgtt))
 120                 return 0;
 121
 122         if (enable_ppgtt == 1)
 123                 return 1;
 124
 125         if (enable_ppgtt == 2 && has_full_ppgtt)
 126                 return 2;
 127
 128 #ifdef CONFIG_INTEL_IOMMU
 129         /* Disable ppgtt on SNB if VT-d is on. */
 130         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
 131                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
 132                 return 0;
 133         }
 134 #endif
 135
 136         /* Early VLV doesn't have this */
 137         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 138             dev->pdev->revision < 0xb) {
 139                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 140                 return 0;
 141         }
 142
 143         if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
 144                 return 2;
 145         else
 146                 return has_aliasing_ppgtt ? 1 : 0;
 147 }
 148
 149 static int ppgtt_bind_vma(struct i915_vma *vma,
 150                           enum i915_cache_level cache_level,
 151                           u32 unused)
 152 {
 153         u32 pte_flags = 0;
 154
 155         /* Currently applicable only to VLV */
 156         if (vma->obj->gt_ro)
 157                 pte_flags |= PTE_READ_ONLY;
 158
 159         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
 160                                 cache_level, pte_flags);
 161
 162         return 0;
 163 }
 164
 165 static void ppgtt_unbind_vma(struct i915_vma *vma)
 166 {
 167         vma->vm->clear_range(vma->vm,
 168                              vma->node.start,
 169                              vma->obj->base.size,
 170                              true);
 171 }
 172
 173 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 174                                   enum i915_cache_level level,
 175                                   bool valid)
 176 {
 177         gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 178         pte |= addr;
 179
 180         switch (level) {
 181         case I915_CACHE_NONE:
 182                 pte |= PPAT_UNCACHED_INDEX;
 183                 break;
 184         case I915_CACHE_WT:
 185                 pte |= PPAT_DISPLAY_ELLC_INDEX;
 186                 break;
 187         default:
 188                 pte |= PPAT_CACHED_INDEX;
 189                 break;
 190         }
 191
 192         return pte;
 193 }
 194
 195 static gen8_pde_t gen8_pde_encode(struct drm_device *dev,
 196                                   dma_addr_t addr,
 197                                   enum i915_cache_level level)
 198 {
 199         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 200         pde |= addr;
 201         if (level != I915_CACHE_NONE)
 202                 pde |= PPAT_CACHED_PDE_INDEX;
 203         else
 204                 pde |= PPAT_UNCACHED_INDEX;
 205         return pde;
 206 }
 207
 208 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 209                                  enum i915_cache_level level,
 210                                  bool valid, u32 unused)
 211 {
 212         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 213         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 214
 215         switch (level) {
 216         case I915_CACHE_L3_LLC:
 217         case I915_CACHE_LLC:
 218                 pte |= GEN6_PTE_CACHE_LLC;
 219                 break;
 220         case I915_CACHE_NONE:
 221                 pte |= GEN6_PTE_UNCACHED;
 222                 break;
 223         default:
 224                 MISSING_CASE(level);
 225         }
 226
 227         return pte;
 228 }
 229
 230 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 231                                  enum i915_cache_level level,
 232                                  bool valid, u32 unused)
 233 {
 234         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 235         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 236
 237         switch (level) {
 238         case I915_CACHE_L3_LLC:
 239                 pte |= GEN7_PTE_CACHE_L3_LLC;
 240                 break;
 241         case I915_CACHE_LLC:
 242                 pte |= GEN6_PTE_CACHE_LLC;
 243                 break;
 244         case I915_CACHE_NONE:
 245                 pte |= GEN6_PTE_UNCACHED;
 246                 break;
 247         default:
 248                 MISSING_CASE(level);
 249         }
 250
 251         return pte;
 252 }
 253
 254 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 255                                  enum i915_cache_level level,
 256                                  bool valid, u32 flags)
 257 {
 258         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 259         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 260
 261         if (!(flags & PTE_READ_ONLY))
 262                 pte |= BYT_PTE_WRITEABLE;
 263
 264         if (level != I915_CACHE_NONE)
 265                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 266
 267         return pte;
 268 }
 269
 270 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
 271                                  enum i915_cache_level level,
 272                                  bool valid, u32 unused)
 273 {
 274         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 275         pte |= HSW_PTE_ADDR_ENCODE(addr);
 276
 277         if (level != I915_CACHE_NONE)
 278                 pte |= HSW_WB_LLC_AGE3;
 279
 280         return pte;
 281 }
 282
 283 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
 284                                   enum i915_cache_level level,
 285                                   bool valid, u32 unused)
 286 {
 287         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 288         pte |= HSW_PTE_ADDR_ENCODE(addr);
 289
 290         switch (level) {
 291         case I915_CACHE_NONE:
 292                 break;
 293         case I915_CACHE_WT:
 294                 pte |= HSW_WT_ELLC_LLC_AGE3;
 295                 break;
 296         default:
 297                 pte |= HSW_WB_ELLC_LLC_AGE3;
 298                 break;
 299         }
 300
 301         return pte;
 302 }
 303
 304 #define i915_dma_unmap_single(px, dev) \
 305         __i915_dma_unmap_single((px)->daddr, dev)
 306
 307 static void __i915_dma_unmap_single(dma_addr_t daddr,
 308                                     struct drm_device *dev)
 309 {
 310         struct device *device = &dev->pdev->dev;
 311
 312         dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
 313 }
 314
 315 /**
 316  * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc.
 317  * @px: Page table/dir/etc to get a DMA map for
 318  * @dev:        drm device
 319  *
 320  * Page table allocations are unified across all gens. They always require a
 321  * single 4k allocation, as well as a DMA mapping. If we keep the structs
 322  * symmetric here, the simple macro covers us for every page table type.
 323  *
 324  * Return: 0 if success.
 325  */
 326 #define i915_dma_map_single(px, dev) \
 327         i915_dma_map_page_single((px)->page, (dev), &(px)->daddr)
 328
 329 static int i915_dma_map_page_single(struct page *page,
 330                                     struct drm_device *dev,
 331                                     dma_addr_t *daddr)
 332 {
 333         struct device *device = &dev->pdev->dev;
 334
 335         *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
 336         if (dma_mapping_error(device, *daddr))
 337                 return -ENOMEM;
 338
 339         return 0;
 340 }
 341
 342 static void unmap_and_free_pt(struct i915_page_table *pt,
 343                                struct drm_device *dev)
 344 {
 345         if (WARN_ON(!pt->page))
 346                 return;
 347
 348         i915_dma_unmap_single(pt, dev);
 349         __free_page(pt->page);
 350         kfree(pt->used_ptes);
 351         kfree(pt);
 352 }
 353
 354 static void gen8_initialize_pt(struct i915_address_space *vm,
 355                                struct i915_page_table *pt)
 356 {
 357         gen8_pte_t *pt_vaddr, scratch_pte;
 358         int i;
 359
 360         pt_vaddr = kmap_atomic(pt->page);
 361         scratch_pte = gen8_pte_encode(vm->scratch.addr,
 362                                       I915_CACHE_LLC, true);
 363
 364         for (i = 0; i < GEN8_PTES; i++)
 365                 pt_vaddr[i] = scratch_pte;
 366
 367         if (!HAS_LLC(vm->dev))
 368                 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 369         kunmap_atomic(pt_vaddr);
 370 }
 371
 372 static struct i915_page_table *alloc_pt_single(struct drm_device *dev)
 373 {
 374         struct i915_page_table *pt;
 375         const size_t count = INTEL_INFO(dev)->gen >= 8 ?
 376                 GEN8_PTES : GEN6_PTES;
 377         int ret = -ENOMEM;
 378
 379         pt = kzalloc(sizeof(*pt), GFP_KERNEL);
 380         if (!pt)
 381                 return ERR_PTR(-ENOMEM);
 382
 383         pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
 384                                 GFP_KERNEL);
 385
 386         if (!pt->used_ptes)
 387                 goto fail_bitmap;
 388
 389         pt->page = alloc_page(GFP_KERNEL);
 390         if (!pt->page)
 391                 goto fail_page;
 392
 393         ret = i915_dma_map_single(pt, dev);
 394         if (ret)
 395                 goto fail_dma;
 396
 397         return pt;
 398
 399 fail_dma:
 400         __free_page(pt->page);
 401 fail_page:
 402         kfree(pt->used_ptes);
 403 fail_bitmap:
 404         kfree(pt);
 405
 406         return ERR_PTR(ret);
 407 }
 408
 409 static void unmap_and_free_pd(struct i915_page_directory *pd,
 410                               struct drm_device *dev)
 411 {
 412         if (pd->page) {
 413                 i915_dma_unmap_single(pd, dev);
 414                 __free_page(pd->page);
 415                 kfree(pd->used_pdes);
 416                 kfree(pd);
 417         }
 418 }
 419
 420 static struct i915_page_directory *alloc_pd_single(struct drm_device *dev)
 421 {
 422         struct i915_page_directory *pd;
 423         int ret = -ENOMEM;
 424
 425         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 426         if (!pd)
 427                 return ERR_PTR(-ENOMEM);
 428
 429         pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
 430                                 sizeof(*pd->used_pdes), GFP_KERNEL);
 431         if (!pd->used_pdes)
 432                 goto free_pd;
 433
 434         pd->page = alloc_page(GFP_KERNEL);
 435         if (!pd->page)
 436                 goto free_bitmap;
 437
 438         ret = i915_dma_map_single(pd, dev);
 439         if (ret)
 440                 goto free_page;
 441
 442         return pd;
 443
 444 free_page:
 445         __free_page(pd->page);
 446 free_bitmap:
 447         kfree(pd->used_pdes);
 448 free_pd:
 449         kfree(pd);
 450
 451         return ERR_PTR(ret);
 452 }
 453
 454 /* Broadwell Page Directory Pointer Descriptors */
 455 static int gen8_write_pdp(struct intel_engine_cs *ring,
 456                           unsigned entry,
 457                           dma_addr_t addr)
 458 {
 459         int ret;
 460
 461         BUG_ON(entry >= 4);
 462
 463         ret = intel_ring_begin(ring, 6);
 464         if (ret)
 465                 return ret;
 466
 467         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 468         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 469         intel_ring_emit(ring, upper_32_bits(addr));
 470         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 471         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 472         intel_ring_emit(ring, lower_32_bits(addr));
 473         intel_ring_advance(ring);
 474
 475         return 0;
 476 }
 477
 478 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
 479                           struct intel_engine_cs *ring)
 480 {
 481         int i, ret;
 482
 483         for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 484                 struct i915_page_directory *pd = ppgtt->pdp.page_directory[i];
 485                 dma_addr_t pd_daddr = pd ? pd->daddr : ppgtt->scratch_pd->daddr;
 486                 /* The page directory might be NULL, but we need to clear out
 487                  * whatever the previous context might have used. */
 488                 ret = gen8_write_pdp(ring, i, pd_daddr);
 489                 if (ret)
 490                         return ret;
 491         }
 492
 493         return 0;
 494 }
 495
 496 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 497                                    uint64_t start,
 498                                    uint64_t length,
 499                                    bool use_scratch)
 500 {
 501         struct i915_hw_ppgtt *ppgtt =
 502                 container_of(vm, struct i915_hw_ppgtt, base);
 503         gen8_pte_t *pt_vaddr, scratch_pte;
 504         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 505         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 506         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 507         unsigned num_entries = length >> PAGE_SHIFT;
 508         unsigned last_pte, i;
 509
 510         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 511                                       I915_CACHE_LLC, use_scratch);
 512
 513         while (num_entries) {
 514                 struct i915_page_directory *pd;
 515                 struct i915_page_table *pt;
 516                 struct page *page_table;
 517
 518                 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
 519                         continue;
 520
 521                 pd = ppgtt->pdp.page_directory[pdpe];
 522
 523                 if (WARN_ON(!pd->page_table[pde]))
 524                         continue;
 525
 526                 pt = pd->page_table[pde];
 527
 528                 if (WARN_ON(!pt->page))
 529                         continue;
 530
 531                 page_table = pt->page;
 532
 533                 last_pte = pte + num_entries;
 534                 if (last_pte > GEN8_PTES)
 535                         last_pte = GEN8_PTES;
 536
 537                 pt_vaddr = kmap_atomic(page_table);
 538
 539                 for (i = pte; i < last_pte; i++) {
 540                         pt_vaddr[i] = scratch_pte;
 541                         num_entries--;
 542                 }
 543
 544                 if (!HAS_LLC(ppgtt->base.dev))
 545                         drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 546                 kunmap_atomic(pt_vaddr);
 547
 548                 pte = 0;
 549                 if (++pde == I915_PDES) {
 550                         pdpe++;
 551                         pde = 0;
 552                 }
 553         }
 554 }
 555
 556 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 557                                       struct sg_table *pages,
 558                                       uint64_t start,
 559                                       enum i915_cache_level cache_level, u32 unused)
 560 {
 561         struct i915_hw_ppgtt *ppgtt =
 562                 container_of(vm, struct i915_hw_ppgtt, base);
 563         gen8_pte_t *pt_vaddr;
 564         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 565         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 566         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 567         struct sg_page_iter sg_iter;
 568
 569         pt_vaddr = NULL;
 570
 571         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 572                 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
 573                         break;
 574
 575                 if (pt_vaddr == NULL) {
 576                         struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe];
 577                         struct i915_page_table *pt = pd->page_table[pde];
 578                         struct page *page_table = pt->page;
 579
 580                         pt_vaddr = kmap_atomic(page_table);
 581                 }
 582
 583                 pt_vaddr[pte] =
 584                         gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
 585                                         cache_level, true);
 586                 if (++pte == GEN8_PTES) {
 587                         if (!HAS_LLC(ppgtt->base.dev))
 588                                 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 589                         kunmap_atomic(pt_vaddr);
 590                         pt_vaddr = NULL;
 591                         if (++pde == I915_PDES) {
 592                                 pdpe++;
 593                                 pde = 0;
 594                         }
 595                         pte = 0;
 596                 }
 597         }
 598         if (pt_vaddr) {
 599                 if (!HAS_LLC(ppgtt->base.dev))
 600                         drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 601                 kunmap_atomic(pt_vaddr);
 602         }
 603 }
 604
 605 static void __gen8_do_map_pt(gen8_pde_t * const pde,
 606                              struct i915_page_table *pt,
 607                              struct drm_device *dev)
 608 {
 609         gen8_pde_t entry =
 610                 gen8_pde_encode(dev, pt->daddr, I915_CACHE_LLC);
 611         *pde = entry;
 612 }
 613
 614 static void gen8_initialize_pd(struct i915_address_space *vm,
 615                                struct i915_page_directory *pd)
 616 {
 617         struct i915_hw_ppgtt *ppgtt =
 618                         container_of(vm, struct i915_hw_ppgtt, base);
 619         gen8_pde_t *page_directory;
 620         struct i915_page_table *pt;
 621         int i;
 622
 623         page_directory = kmap_atomic(pd->page);
 624         pt = ppgtt->scratch_pt;
 625         for (i = 0; i < I915_PDES; i++)
 626                 /* Map the PDE to the page table */
 627                 __gen8_do_map_pt(page_directory + i, pt, vm->dev);
 628
 629         if (!HAS_LLC(vm->dev))
 630                 drm_clflush_virt_range(page_directory, PAGE_SIZE);
 631         kunmap_atomic(page_directory);
 632 }
 633
 634 static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev)
 635 {
 636         int i;
 637
 638         if (!pd->page)
 639                 return;
 640
 641         for_each_set_bit(i, pd->used_pdes, I915_PDES) {
 642                 if (WARN_ON(!pd->page_table[i]))
 643                         continue;
 644
 645                 unmap_and_free_pt(pd->page_table[i], dev);
 646                 pd->page_table[i] = NULL;
 647         }
 648 }
 649
 650 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 651 {
 652         struct i915_hw_ppgtt *ppgtt =
 653                 container_of(vm, struct i915_hw_ppgtt, base);
 654         int i;
 655
 656         for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) {
 657                 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
 658                         continue;
 659
 660                 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
 661                 unmap_and_free_pd(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
 662         }
 663
 664         unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev);
 665         unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
 666 }
 667
 668 /**
 669  * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
 670  * @ppgtt:      Master ppgtt structure.
 671  * @pd:         Page directory for this address range.
 672  * @start:      Starting virtual address to begin allocations.
 673  * @length      Size of the allocations.
 674  * @new_pts:    Bitmap set by function with new allocations. Likely used by the
 675  *              caller to free on error.
 676  *
 677  * Allocate the required number of page tables. Extremely similar to
 678  * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
 679  * the page directory boundary (instead of the page directory pointer). That
 680  * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
 681  * possible, and likely that the caller will need to use multiple calls of this
 682  * function to achieve the appropriate allocation.
 683  *
 684  * Return: 0 if success; negative error code otherwise.
 685  */
 686 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt,
 687                                      struct i915_page_directory *pd,
 688                                      uint64_t start,
 689                                      uint64_t length,
 690                                      unsigned long *new_pts)
 691 {
 692         struct drm_device *dev = ppgtt->base.dev;
 693         struct i915_page_table *pt;
 694         uint64_t temp;
 695         uint32_t pde;
 696
 697         gen8_for_each_pde(pt, pd, start, length, temp, pde) {
 698                 /* Don't reallocate page tables */
 699                 if (pt) {
 700                         /* Scratch is never allocated this way */
 701                         WARN_ON(pt == ppgtt->scratch_pt);
 702                         continue;
 703                 }
 704
 705                 pt = alloc_pt_single(dev);
 706                 if (IS_ERR(pt))
 707                         goto unwind_out;
 708
 709                 gen8_initialize_pt(&ppgtt->base, pt);
 710                 pd->page_table[pde] = pt;
 711                 set_bit(pde, new_pts);
 712         }
 713
 714         return 0;
 715
 716 unwind_out:
 717         for_each_set_bit(pde, new_pts, I915_PDES)
 718                 unmap_and_free_pt(pd->page_table[pde], dev);
 719
 720         return -ENOMEM;
 721 }
 722
 723 /**
 724  * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
 725  * @ppgtt:      Master ppgtt structure.
 726  * @pdp:        Page directory pointer for this address range.
 727  * @start:      Starting virtual address to begin allocations.
 728  * @length      Size of the allocations.
 729  * @new_pds     Bitmap set by function with new allocations. Likely used by the
 730  *              caller to free on error.
 731  *
 732  * Allocate the required number of page directories starting at the pde index of
 733  * @start, and ending at the pde index @start + @length. This function will skip
 734  * over already allocated page directories within the range, and only allocate
 735  * new ones, setting the appropriate pointer within the pdp as well as the
 736  * correct position in the bitmap @new_pds.
 737  *
 738  * The function will only allocate the pages within the range for a give page
 739  * directory pointer. In other words, if @start + @length straddles a virtually
 740  * addressed PDP boundary (512GB for 4k pages), there will be more allocations
 741  * required by the caller, This is not currently possible, and the BUG in the
 742  * code will prevent it.
 743  *
 744  * Return: 0 if success; negative error code otherwise.
 745  */
 746 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt,
 747                                      struct i915_page_directory_pointer *pdp,
 748                                      uint64_t start,
 749                                      uint64_t length,
 750                                      unsigned long *new_pds)
 751 {
 752         struct drm_device *dev = ppgtt->base.dev;
 753         struct i915_page_directory *pd;
 754         uint64_t temp;
 755         uint32_t pdpe;
 756
 757         WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES));
 758
 759         /* FIXME: upper bound must not overflow 32 bits  */
 760         WARN_ON((start + length) >= (1ULL << 32));
 761
 762         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
 763                 if (pd)
 764                         continue;
 765
 766                 pd = alloc_pd_single(dev);
 767                 if (IS_ERR(pd))
 768                         goto unwind_out;
 769
 770                 gen8_initialize_pd(&ppgtt->base, pd);
 771                 pdp->page_directory[pdpe] = pd;
 772                 set_bit(pdpe, new_pds);
 773         }
 774
 775         return 0;
 776
 777 unwind_out:
 778         for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES)
 779                 unmap_and_free_pd(pdp->page_directory[pdpe], dev);
 780
 781         return -ENOMEM;
 782 }
 783
 784 static void
 785 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
 786 {
 787         int i;
 788
 789         for (i = 0; i < GEN8_LEGACY_PDPES; i++)
 790                 kfree(new_pts[i]);
 791         kfree(new_pts);
 792         kfree(new_pds);
 793 }
 794
 795 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
 796  * of these are based on the number of PDPEs in the system.
 797  */
 798 static
 799 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
 800                                          unsigned long ***new_pts)
 801 {
 802         int i;
 803         unsigned long *pds;
 804         unsigned long **pts;
 805
 806         pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL);
 807         if (!pds)
 808                 return -ENOMEM;
 809
 810         pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL);
 811         if (!pts) {
 812                 kfree(pds);
 813                 return -ENOMEM;
 814         }
 815
 816         for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 817                 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
 818                                  sizeof(unsigned long), GFP_KERNEL);
 819                 if (!pts[i])
 820                         goto err_out;
 821         }
 822
 823         *new_pds = pds;
 824         *new_pts = pts;
 825
 826         return 0;
 827
 828 err_out:
 829         free_gen8_temp_bitmaps(pds, pts);
 830         return -ENOMEM;
 831 }
 832
 833 static int gen8_alloc_va_range(struct i915_address_space *vm,
 834                                uint64_t start,
 835                                uint64_t length)
 836 {
 837         struct i915_hw_ppgtt *ppgtt =
 838                 container_of(vm, struct i915_hw_ppgtt, base);
 839         unsigned long *new_page_dirs, **new_page_tables;
 840         struct i915_page_directory *pd;
 841         const uint64_t orig_start = start;
 842         const uint64_t orig_length = length;
 843         uint64_t temp;
 844         uint32_t pdpe;
 845         int ret;
 846
 847         /* Wrap is never okay since we can only represent 48b, and we don't
 848          * actually use the other side of the canonical address space.
 849          */
 850         if (WARN_ON(start + length < start))
 851                 return -ERANGE;
 852
 853         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables);
 854         if (ret)
 855                 return ret;
 856
 857         /* Do the allocations first so we can easily bail out */
 858         ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length,
 859                                         new_page_dirs);
 860         if (ret) {
 861                 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 862                 return ret;
 863         }
 864
 865         /* For every page directory referenced, allocate page tables */
 866         gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
 867                 ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length,
 868                                                 new_page_tables[pdpe]);
 869                 if (ret)
 870                         goto err_out;
 871         }
 872
 873         start = orig_start;
 874         length = orig_length;
 875
 876         /* Allocations have completed successfully, so set the bitmaps, and do
 877          * the mappings. */
 878         gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
 879                 gen8_pde_t *const page_directory = kmap_atomic(pd->page);
 880                 struct i915_page_table *pt;
 881                 uint64_t pd_len = gen8_clamp_pd(start, length);
 882                 uint64_t pd_start = start;
 883                 uint32_t pde;
 884
 885                 /* Every pd should be allocated, we just did that above. */
 886                 WARN_ON(!pd);
 887
 888                 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
 889                         /* Same reasoning as pd */
 890                         WARN_ON(!pt);
 891                         WARN_ON(!pd_len);
 892                         WARN_ON(!gen8_pte_count(pd_start, pd_len));
 893
 894                         /* Set our used ptes within the page table */
 895                         bitmap_set(pt->used_ptes,
 896                                    gen8_pte_index(pd_start),
 897                                    gen8_pte_count(pd_start, pd_len));
 898
 899                         /* Our pde is now pointing to the pagetable, pt */
 900                         set_bit(pde, pd->used_pdes);
 901
 902                         /* Map the PDE to the page table */
 903                         __gen8_do_map_pt(page_directory + pde, pt, vm->dev);
 904
 905                         /* NB: We haven't yet mapped ptes to pages. At this
 906                          * point we're still relying on insert_entries() */
 907                 }
 908
 909                 if (!HAS_LLC(vm->dev))
 910                         drm_clflush_virt_range(page_directory, PAGE_SIZE);
 911
 912                 kunmap_atomic(page_directory);
 913
 914                 set_bit(pdpe, ppgtt->pdp.used_pdpes);
 915         }
 916
 917         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 918         return 0;
 919
 920 err_out:
 921         while (pdpe--) {
 922                 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
 923                         unmap_and_free_pt(ppgtt->pdp.page_directory[pdpe]->page_table[temp], vm->dev);
 924         }
 925
 926         for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES)
 927                 unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe], vm->dev);
 928
 929         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 930         return ret;
 931 }
 932
 933 /*
 934  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
 935  * with a net effect resembling a 2-level page table in normal x86 terms. Each
 936  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
 937  * space.
 938  *
 939  */
 940 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 941 {
 942         ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev);
 943         if (IS_ERR(ppgtt->scratch_pt))
 944                 return PTR_ERR(ppgtt->scratch_pt);
 945
 946         ppgtt->scratch_pd = alloc_pd_single(ppgtt->base.dev);
 947         if (IS_ERR(ppgtt->scratch_pd))
 948                 return PTR_ERR(ppgtt->scratch_pd);
 949
 950         gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
 951         gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd);
 952
 953         ppgtt->base.start = 0;
 954         ppgtt->base.total = 1ULL << 32;
 955         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 956         ppgtt->base.allocate_va_range = gen8_alloc_va_range;
 957         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 958         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 959         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
 960         ppgtt->base.bind_vma = ppgtt_bind_vma;
 961
 962         ppgtt->switch_mm = gen8_mm_switch;
 963
 964         return 0;
 965 }
 966
 967 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
 968 {
 969         struct i915_address_space *vm = &ppgtt->base;
 970         struct i915_page_table *unused;
 971         gen6_pte_t scratch_pte;
 972         uint32_t pd_entry;
 973         uint32_t  pte, pde, temp;
 974         uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
 975
 976         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
 977
 978         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
 979                 u32 expected;
 980                 gen6_pte_t *pt_vaddr;
 981                 dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr;
 982                 pd_entry = readl(ppgtt->pd_addr + pde);
 983                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
 984
 985                 if (pd_entry != expected)
 986                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
 987                                    pde,
 988                                    pd_entry,
 989                                    expected);
 990                 seq_printf(m, "\tPDE: %x\n", pd_entry);
 991
 992                 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page);
 993                 for (pte = 0; pte < GEN6_PTES; pte+=4) {
 994                         unsigned long va =
 995                                 (pde * PAGE_SIZE * GEN6_PTES) +
 996                                 (pte * PAGE_SIZE);
 997                         int i;
 998                         bool found = false;
 999                         for (i = 0; i < 4; i++)
1000                                 if (pt_vaddr[pte + i] != scratch_pte)
1001                                         found = true;
1002                         if (!found)
1003                                 continue;
1004
1005                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1006                         for (i = 0; i < 4; i++) {
1007                                 if (pt_vaddr[pte + i] != scratch_pte)
1008                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
1009                                 else
1010                                         seq_puts(m, "  SCRATCH ");
1011                         }
1012                         seq_puts(m, "\n");
1013                 }
1014                 kunmap_atomic(pt_vaddr);
1015         }
1016 }
1017
1018 /* Write pde (index) from the page directory @pd to the page table @pt */
1019 static void gen6_write_pde(struct i915_page_directory *pd,
1020                             const int pde, struct i915_page_table *pt)
1021 {
1022         /* Caller needs to make sure the write completes if necessary */
1023         struct i915_hw_ppgtt *ppgtt =
1024                 container_of(pd, struct i915_hw_ppgtt, pd);
1025         u32 pd_entry;
1026
1027         pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr);
1028         pd_entry |= GEN6_PDE_VALID;
1029
1030         writel(pd_entry, ppgtt->pd_addr + pde);
1031 }
1032
1033 /* Write all the page tables found in the ppgtt structure to incrementing page
1034  * directories. */
1035 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1036                                   struct i915_page_directory *pd,
1037                                   uint32_t start, uint32_t length)
1038 {
1039         struct i915_page_table *pt;
1040         uint32_t pde, temp;
1041
1042         gen6_for_each_pde(pt, pd, start, length, temp, pde)
1043                 gen6_write_pde(pd, pde, pt);
1044
1045         /* Make sure write is complete before other code can use this page
1046          * table. Also require for WC mapped PTEs */
1047         readl(dev_priv->gtt.gsm);
1048 }
1049
1050 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1051 {
1052         BUG_ON(ppgtt->pd.pd_offset & 0x3f);
1053
1054         return (ppgtt->pd.pd_offset / 64) << 16;
1055 }
1056
1057 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1058                          struct intel_engine_cs *ring)
1059 {
1060         int ret;
1061
1062         /* NB: TLBs must be flushed and invalidated before a switch */
1063         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1064         if (ret)
1065                 return ret;
1066
1067         ret = intel_ring_begin(ring, 6);
1068         if (ret)
1069                 return ret;
1070
1071         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1072         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1073         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1074         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1075         intel_ring_emit(ring, get_pd_offset(ppgtt));
1076         intel_ring_emit(ring, MI_NOOP);
1077         intel_ring_advance(ring);
1078
1079         return 0;
1080 }
1081
1082 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1083                           struct intel_engine_cs *ring)
1084 {
1085         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1086
1087         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1088         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1089         return 0;
1090 }
1091
1092 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1093                           struct intel_engine_cs *ring)
1094 {
1095         int ret;
1096
1097         /* NB: TLBs must be flushed and invalidated before a switch */
1098         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1099         if (ret)
1100                 return ret;
1101
1102         ret = intel_ring_begin(ring, 6);
1103         if (ret)
1104                 return ret;
1105
1106         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1107         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1108         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1109         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1110         intel_ring_emit(ring, get_pd_offset(ppgtt));
1111         intel_ring_emit(ring, MI_NOOP);
1112         intel_ring_advance(ring);
1113
1114         /* XXX: RCS is the only one to auto invalidate the TLBs? */
1115         if (ring->id != RCS) {
1116                 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1117                 if (ret)
1118                         return ret;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1125                           struct intel_engine_cs *ring)
1126 {
1127         struct drm_device *dev = ppgtt->base.dev;
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129
1130
1131         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1132         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1133
1134         POSTING_READ(RING_PP_DIR_DCLV(ring));
1135
1136         return 0;
1137 }
1138
1139 static void gen8_ppgtt_enable(struct drm_device *dev)
1140 {
1141         struct drm_i915_private *dev_priv = dev->dev_private;
1142         struct intel_engine_cs *ring;
1143         int j;
1144
1145         for_each_ring(ring, dev_priv, j) {
1146                 I915_WRITE(RING_MODE_GEN7(ring),
1147                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1148         }
1149 }
1150
1151 static void gen7_ppgtt_enable(struct drm_device *dev)
1152 {
1153         struct drm_i915_private *dev_priv = dev->dev_private;
1154         struct intel_engine_cs *ring;
1155         uint32_t ecochk, ecobits;
1156         int i;
1157
1158         ecobits = I915_READ(GAC_ECO_BITS);
1159         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1160
1161         ecochk = I915_READ(GAM_ECOCHK);
1162         if (IS_HASWELL(dev)) {
1163                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1164         } else {
1165                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1166                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1167         }
1168         I915_WRITE(GAM_ECOCHK, ecochk);
1169
1170         for_each_ring(ring, dev_priv, i) {
1171                 /* GFX_MODE is per-ring on gen7+ */
1172                 I915_WRITE(RING_MODE_GEN7(ring),
1173                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1174         }
1175 }
1176
1177 static void gen6_ppgtt_enable(struct drm_device *dev)
1178 {
1179         struct drm_i915_private *dev_priv = dev->dev_private;
1180         uint32_t ecochk, gab_ctl, ecobits;
1181
1182         ecobits = I915_READ(GAC_ECO_BITS);
1183         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1184                    ECOBITS_PPGTT_CACHE64B);
1185
1186         gab_ctl = I915_READ(GAB_CTL);
1187         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1188
1189         ecochk = I915_READ(GAM_ECOCHK);
1190         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1191
1192         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1193 }
1194
1195 /* PPGTT support for Sandybdrige/Gen6 and later */
1196 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1197                                    uint64_t start,
1198                                    uint64_t length,
1199                                    bool use_scratch)
1200 {
1201         struct i915_hw_ppgtt *ppgtt =
1202                 container_of(vm, struct i915_hw_ppgtt, base);
1203         gen6_pte_t *pt_vaddr, scratch_pte;
1204         unsigned first_entry = start >> PAGE_SHIFT;
1205         unsigned num_entries = length >> PAGE_SHIFT;
1206         unsigned act_pt = first_entry / GEN6_PTES;
1207         unsigned first_pte = first_entry % GEN6_PTES;
1208         unsigned last_pte, i;
1209
1210         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
1211
1212         while (num_entries) {
1213                 last_pte = first_pte + num_entries;
1214                 if (last_pte > GEN6_PTES)
1215                         last_pte = GEN6_PTES;
1216
1217                 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1218
1219                 for (i = first_pte; i < last_pte; i++)
1220                         pt_vaddr[i] = scratch_pte;
1221
1222                 kunmap_atomic(pt_vaddr);
1223
1224                 num_entries -= last_pte - first_pte;
1225                 first_pte = 0;
1226                 act_pt++;
1227         }
1228 }
1229
1230 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1231                                       struct sg_table *pages,
1232                                       uint64_t start,
1233                                       enum i915_cache_level cache_level, u32 flags)
1234 {
1235         struct i915_hw_ppgtt *ppgtt =
1236                 container_of(vm, struct i915_hw_ppgtt, base);
1237         gen6_pte_t *pt_vaddr;
1238         unsigned first_entry = start >> PAGE_SHIFT;
1239         unsigned act_pt = first_entry / GEN6_PTES;
1240         unsigned act_pte = first_entry % GEN6_PTES;
1241         struct sg_page_iter sg_iter;
1242
1243         pt_vaddr = NULL;
1244         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1245                 if (pt_vaddr == NULL)
1246                         pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1247
1248                 pt_vaddr[act_pte] =
1249                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1250                                        cache_level, true, flags);
1251
1252                 if (++act_pte == GEN6_PTES) {
1253                         kunmap_atomic(pt_vaddr);
1254                         pt_vaddr = NULL;
1255                         act_pt++;
1256                         act_pte = 0;
1257                 }
1258         }
1259         if (pt_vaddr)
1260                 kunmap_atomic(pt_vaddr);
1261 }
1262
1263 /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we
1264  * are switching between contexts with the same LRCA, we also must do a force
1265  * restore.
1266  */
1267 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1268 {
1269         /* If current vm != vm, */
1270         ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1271 }
1272
1273 static void gen6_initialize_pt(struct i915_address_space *vm,
1274                 struct i915_page_table *pt)
1275 {
1276         gen6_pte_t *pt_vaddr, scratch_pte;
1277         int i;
1278
1279         WARN_ON(vm->scratch.addr == 0);
1280
1281         scratch_pte = vm->pte_encode(vm->scratch.addr,
1282                         I915_CACHE_LLC, true, 0);
1283
1284         pt_vaddr = kmap_atomic(pt->page);
1285
1286         for (i = 0; i < GEN6_PTES; i++)
1287                 pt_vaddr[i] = scratch_pte;
1288
1289         kunmap_atomic(pt_vaddr);
1290 }
1291
1292 static int gen6_alloc_va_range(struct i915_address_space *vm,
1293                                uint64_t start, uint64_t length)
1294 {
1295         DECLARE_BITMAP(new_page_tables, I915_PDES);
1296         struct drm_device *dev = vm->dev;
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298         struct i915_hw_ppgtt *ppgtt =
1299                                 container_of(vm, struct i915_hw_ppgtt, base);
1300         struct i915_page_table *pt;
1301         const uint32_t start_save = start, length_save = length;
1302         uint32_t pde, temp;
1303         int ret;
1304
1305         WARN_ON(upper_32_bits(start));
1306
1307         bitmap_zero(new_page_tables, I915_PDES);
1308
1309         /* The allocation is done in two stages so that we can bail out with
1310          * minimal amount of pain. The first stage finds new page tables that
1311          * need allocation. The second stage marks use ptes within the page
1312          * tables.
1313          */
1314         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1315                 if (pt != ppgtt->scratch_pt) {
1316                         WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1317                         continue;
1318                 }
1319
1320                 /* We've already allocated a page table */
1321                 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1322
1323                 pt = alloc_pt_single(dev);
1324                 if (IS_ERR(pt)) {
1325                         ret = PTR_ERR(pt);
1326                         goto unwind_out;
1327                 }
1328
1329                 gen6_initialize_pt(vm, pt);
1330
1331                 ppgtt->pd.page_table[pde] = pt;
1332                 set_bit(pde, new_page_tables);
1333                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1334         }
1335
1336         start = start_save;
1337         length = length_save;
1338
1339         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1340                 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1341
1342                 bitmap_zero(tmp_bitmap, GEN6_PTES);
1343                 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1344                            gen6_pte_count(start, length));
1345
1346                 if (test_and_clear_bit(pde, new_page_tables))
1347                         gen6_write_pde(&ppgtt->pd, pde, pt);
1348
1349                 trace_i915_page_table_entry_map(vm, pde, pt,
1350                                          gen6_pte_index(start),
1351                                          gen6_pte_count(start, length),
1352                                          GEN6_PTES);
1353                 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1354                                 GEN6_PTES);
1355         }
1356
1357         WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1358
1359         /* Make sure write is complete before other code can use this page
1360          * table. Also require for WC mapped PTEs */
1361         readl(dev_priv->gtt.gsm);
1362
1363         mark_tlbs_dirty(ppgtt);
1364         return 0;
1365
1366 unwind_out:
1367         for_each_set_bit(pde, new_page_tables, I915_PDES) {
1368                 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1369
1370                 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1371                 unmap_and_free_pt(pt, vm->dev);
1372         }
1373
1374         mark_tlbs_dirty(ppgtt);
1375         return ret;
1376 }
1377
1378 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1379 {
1380         struct i915_hw_ppgtt *ppgtt =
1381                 container_of(vm, struct i915_hw_ppgtt, base);
1382         struct i915_page_table *pt;
1383         uint32_t pde;
1384
1385
1386         drm_mm_remove_node(&ppgtt->node);
1387
1388         gen6_for_all_pdes(pt, ppgtt, pde) {
1389                 if (pt != ppgtt->scratch_pt)
1390                         unmap_and_free_pt(pt, ppgtt->base.dev);
1391         }
1392
1393         unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
1394         unmap_and_free_pd(&ppgtt->pd, ppgtt->base.dev);
1395 }
1396
1397 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1398 {
1399         struct drm_device *dev = ppgtt->base.dev;
1400         struct drm_i915_private *dev_priv = dev->dev_private;
1401         bool retried = false;
1402         int ret;
1403
1404         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1405          * allocator works in address space sizes, so it's multiplied by page
1406          * size. We allocate at the top of the GTT to avoid fragmentation.
1407          */
1408         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1409         ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev);
1410         if (IS_ERR(ppgtt->scratch_pt))
1411                 return PTR_ERR(ppgtt->scratch_pt);
1412
1413         gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
1414
1415 alloc:
1416         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1417                                                   &ppgtt->node, GEN6_PD_SIZE,
1418                                                   GEN6_PD_ALIGN, 0,
1419                                                   0, dev_priv->gtt.base.total,
1420                                                   DRM_MM_TOPDOWN);
1421         if (ret == -ENOSPC && !retried) {
1422                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1423                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
1424                                                I915_CACHE_NONE,
1425                                                0, dev_priv->gtt.base.total,
1426                                                0);
1427                 if (ret)
1428                         goto err_out;
1429
1430                 retried = true;
1431                 goto alloc;
1432         }
1433
1434         if (ret)
1435                 goto err_out;
1436
1437
1438         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1439                 DRM_DEBUG("Forced to use aperture for PDEs\n");
1440
1441         return 0;
1442
1443 err_out:
1444         unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
1445         return ret;
1446 }
1447
1448 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1449 {
1450         return gen6_ppgtt_allocate_page_directories(ppgtt);
1451 }
1452
1453 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1454                                   uint64_t start, uint64_t length)
1455 {
1456         struct i915_page_table *unused;
1457         uint32_t pde, temp;
1458
1459         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
1460                 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1461 }
1462
1463 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1464 {
1465         struct drm_device *dev = ppgtt->base.dev;
1466         struct drm_i915_private *dev_priv = dev->dev_private;
1467         int ret;
1468
1469         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1470         if (IS_GEN6(dev)) {
1471                 ppgtt->switch_mm = gen6_mm_switch;
1472         } else if (IS_HASWELL(dev)) {
1473                 ppgtt->switch_mm = hsw_mm_switch;
1474         } else if (IS_GEN7(dev)) {
1475                 ppgtt->switch_mm = gen7_mm_switch;
1476         } else
1477                 BUG();
1478
1479         if (intel_vgpu_active(dev))
1480                 ppgtt->switch_mm = vgpu_mm_switch;
1481
1482         ret = gen6_ppgtt_alloc(ppgtt);
1483         if (ret)
1484                 return ret;
1485
1486         ppgtt->base.allocate_va_range = gen6_alloc_va_range;
1487         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1488         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1489         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1490         ppgtt->base.bind_vma = ppgtt_bind_vma;
1491         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1492         ppgtt->base.start = 0;
1493         ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
1494         ppgtt->debug_dump = gen6_dump_ppgtt;
1495
1496         ppgtt->pd.pd_offset =
1497                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1498
1499         ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
1500                 ppgtt->pd.pd_offset / sizeof(gen6_pte_t);
1501
1502         gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1503
1504         gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1505
1506         DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1507                          ppgtt->node.size >> 20,
1508                          ppgtt->node.start / PAGE_SIZE);
1509
1510         DRM_DEBUG("Adding PPGTT at offset %x\n",
1511                   ppgtt->pd.pd_offset << 10);
1512
1513         return 0;
1514 }
1515
1516 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1517 {
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519
1520         ppgtt->base.dev = dev;
1521         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1522
1523         if (INTEL_INFO(dev)->gen < 8)
1524                 return gen6_ppgtt_init(ppgtt);
1525         else
1526                 return gen8_ppgtt_init(ppgtt);
1527 }
1528 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1529 {
1530         struct drm_i915_private *dev_priv = dev->dev_private;
1531         int ret = 0;
1532
1533         ret = __hw_ppgtt_init(dev, ppgtt);
1534         if (ret == 0) {
1535                 kref_init(&ppgtt->ref);
1536                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1537                             ppgtt->base.total);
1538                 i915_init_vm(dev_priv, &ppgtt->base);
1539         }
1540
1541         return ret;
1542 }
1543
1544 int i915_ppgtt_init_hw(struct drm_device *dev)
1545 {
1546         struct drm_i915_private *dev_priv = dev->dev_private;
1547         struct intel_engine_cs *ring;
1548         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1549         int i, ret = 0;
1550
1551         /* In the case of execlists, PPGTT is enabled by the context descriptor
1552          * and the PDPs are contained within the context itself.  We don't
1553          * need to do anything here. */
1554         if (i915.enable_execlists)
1555                 return 0;
1556
1557         if (!USES_PPGTT(dev))
1558                 return 0;
1559
1560         if (IS_GEN6(dev))
1561                 gen6_ppgtt_enable(dev);
1562         else if (IS_GEN7(dev))
1563                 gen7_ppgtt_enable(dev);
1564         else if (INTEL_INFO(dev)->gen >= 8)
1565                 gen8_ppgtt_enable(dev);
1566         else
1567                 MISSING_CASE(INTEL_INFO(dev)->gen);
1568
1569         if (ppgtt) {
1570                 for_each_ring(ring, dev_priv, i) {
1571                         ret = ppgtt->switch_mm(ppgtt, ring);
1572                         if (ret != 0)
1573                                 return ret;
1574                 }
1575         }
1576
1577         return ret;
1578 }
1579 struct i915_hw_ppgtt *
1580 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1581 {
1582         struct i915_hw_ppgtt *ppgtt;
1583         int ret;
1584
1585         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1586         if (!ppgtt)
1587                 return ERR_PTR(-ENOMEM);
1588
1589         ret = i915_ppgtt_init(dev, ppgtt);
1590         if (ret) {
1591                 kfree(ppgtt);
1592                 return ERR_PTR(ret);
1593         }
1594
1595         ppgtt->file_priv = fpriv;
1596
1597         trace_i915_ppgtt_create(&ppgtt->base);
1598
1599         return ppgtt;
1600 }
1601
1602 void  i915_ppgtt_release(struct kref *kref)
1603 {
1604         struct i915_hw_ppgtt *ppgtt =
1605                 container_of(kref, struct i915_hw_ppgtt, ref);
1606
1607         trace_i915_ppgtt_release(&ppgtt->base);
1608
1609         /* vmas should already be unbound */
1610         WARN_ON(!list_empty(&ppgtt->base.active_list));
1611         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1612
1613         list_del(&ppgtt->base.global_link);
1614         drm_mm_takedown(&ppgtt->base.mm);
1615
1616         ppgtt->base.cleanup(&ppgtt->base);
1617         kfree(ppgtt);
1618 }
1619
1620 extern int intel_iommu_gfx_mapped;
1621 /* Certain Gen5 chipsets require require idling the GPU before
1622  * unmapping anything from the GTT when VT-d is enabled.
1623  */
1624 static bool needs_idle_maps(struct drm_device *dev)
1625 {
1626 #ifdef CONFIG_INTEL_IOMMU
1627         /* Query intel_iommu to see if we need the workaround. Presumably that
1628          * was loaded first.
1629          */
1630         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1631                 return true;
1632 #endif
1633         return false;
1634 }
1635
1636 static bool do_idling(struct drm_i915_private *dev_priv)
1637 {
1638         bool ret = dev_priv->mm.interruptible;
1639
1640         if (unlikely(dev_priv->gtt.do_idle_maps)) {
1641                 dev_priv->mm.interruptible = false;
1642                 if (i915_gpu_idle(dev_priv->dev)) {
1643                         DRM_ERROR("Couldn't idle GPU\n");
1644                         /* Wait a bit, in hopes it avoids the hang */
1645                         udelay(10);
1646                 }
1647         }
1648
1649         return ret;
1650 }
1651
1652 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1653 {
1654         if (unlikely(dev_priv->gtt.do_idle_maps))
1655                 dev_priv->mm.interruptible = interruptible;
1656 }
1657
1658 void i915_check_and_clear_faults(struct drm_device *dev)
1659 {
1660         struct drm_i915_private *dev_priv = dev->dev_private;
1661         struct intel_engine_cs *ring;
1662         int i;
1663
1664         if (INTEL_INFO(dev)->gen < 6)
1665                 return;
1666
1667         for_each_ring(ring, dev_priv, i) {
1668                 u32 fault_reg;
1669                 fault_reg = I915_READ(RING_FAULT_REG(ring));
1670                 if (fault_reg & RING_FAULT_VALID) {
1671                         DRM_DEBUG_DRIVER("Unexpected fault\n"
1672                                          "\tAddr: 0x%08lx\n"
1673                                          "\tAddress space: %s\n"
1674                                          "\tSource ID: %d\n"
1675                                          "\tType: %d\n",
1676                                          fault_reg & PAGE_MASK,
1677                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1678                                          RING_FAULT_SRCID(fault_reg),
1679                                          RING_FAULT_FAULT_TYPE(fault_reg));
1680                         I915_WRITE(RING_FAULT_REG(ring),
1681                                    fault_reg & ~RING_FAULT_VALID);
1682                 }
1683         }
1684         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1685 }
1686
1687 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1688 {
1689         if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1690                 intel_gtt_chipset_flush();
1691         } else {
1692                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1693                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1694         }
1695 }
1696
1697 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1698 {
1699         struct drm_i915_private *dev_priv = dev->dev_private;
1700
1701         /* Don't bother messing with faults pre GEN6 as we have little
1702          * documentation supporting that it's a good idea.
1703          */
1704         if (INTEL_INFO(dev)->gen < 6)
1705                 return;
1706
1707         i915_check_and_clear_faults(dev);
1708
1709         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1710                                        dev_priv->gtt.base.start,
1711                                        dev_priv->gtt.base.total,
1712                                        true);
1713
1714         i915_ggtt_flush(dev_priv);
1715 }
1716
1717 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1718 {
1719         if (obj->has_dma_mapping)
1720                 return 0;
1721
1722         if (!dma_map_sg(&obj->base.dev->pdev->dev,
1723                         obj->pages->sgl, obj->pages->nents,
1724                         PCI_DMA_BIDIRECTIONAL))
1725                 return -ENOSPC;
1726
1727         return 0;
1728 }
1729
1730 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
1731 {
1732 #ifdef writeq
1733         writeq(pte, addr);
1734 #else
1735         iowrite32((u32)pte, addr);
1736         iowrite32(pte >> 32, addr + 4);
1737 #endif
1738 }
1739
1740 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1741                                      struct sg_table *st,
1742                                      uint64_t start,
1743                                      enum i915_cache_level level, u32 unused)
1744 {
1745         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1746         unsigned first_entry = start >> PAGE_SHIFT;
1747         gen8_pte_t __iomem *gtt_entries =
1748                 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1749         int i = 0;
1750         struct sg_page_iter sg_iter;
1751         dma_addr_t addr = 0; /* shut up gcc */
1752
1753         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1754                 addr = sg_dma_address(sg_iter.sg) +
1755                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
1756                 gen8_set_pte(&gtt_entries[i],
1757                              gen8_pte_encode(addr, level, true));
1758                 i++;
1759         }
1760
1761         /*
1762          * XXX: This serves as a posting read to make sure that the PTE has
1763          * actually been updated. There is some concern that even though
1764          * registers and PTEs are within the same BAR that they are potentially
1765          * of NUMA access patterns. Therefore, even with the way we assume
1766          * hardware should work, we must keep this posting read for paranoia.
1767          */
1768         if (i != 0)
1769                 WARN_ON(readq(&gtt_entries[i-1])
1770                         != gen8_pte_encode(addr, level, true));
1771
1772         /* This next bit makes the above posting read even more important. We
1773          * want to flush the TLBs only after we're certain all the PTE updates
1774          * have finished.
1775          */
1776         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1777         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1778 }
1779
1780 /*
1781  * Binds an object into the global gtt with the specified cache level. The object
1782  * will be accessible to the GPU via commands whose operands reference offsets
1783  * within the global GTT as well as accessible by the GPU through the GMADR
1784  * mapped BAR (dev_priv->mm.gtt->gtt).
1785  */
1786 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1787                                      struct sg_table *st,
1788                                      uint64_t start,
1789                                      enum i915_cache_level level, u32 flags)
1790 {
1791         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1792         unsigned first_entry = start >> PAGE_SHIFT;
1793         gen6_pte_t __iomem *gtt_entries =
1794                 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1795         int i = 0;
1796         struct sg_page_iter sg_iter;
1797         dma_addr_t addr = 0;
1798
1799         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1800                 addr = sg_page_iter_dma_address(&sg_iter);
1801                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1802                 i++;
1803         }
1804
1805         /* XXX: This serves as a posting read to make sure that the PTE has
1806          * actually been updated. There is some concern that even though
1807          * registers and PTEs are within the same BAR that they are potentially
1808          * of NUMA access patterns. Therefore, even with the way we assume
1809          * hardware should work, we must keep this posting read for paranoia.
1810          */
1811         if (i != 0) {
1812                 unsigned long gtt = readl(&gtt_entries[i-1]);
1813                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1814         }
1815
1816         /* This next bit makes the above posting read even more important. We
1817          * want to flush the TLBs only after we're certain all the PTE updates
1818          * have finished.
1819          */
1820         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1821         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1822 }
1823
1824 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1825                                   uint64_t start,
1826                                   uint64_t length,
1827                                   bool use_scratch)
1828 {
1829         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1830         unsigned first_entry = start >> PAGE_SHIFT;
1831         unsigned num_entries = length >> PAGE_SHIFT;
1832         gen8_pte_t scratch_pte, __iomem *gtt_base =
1833                 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1834         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1835         int i;
1836
1837         if (WARN(num_entries > max_entries,
1838                  "First entry = %d; Num entries = %d (max=%d)\n",
1839                  first_entry, num_entries, max_entries))
1840                 num_entries = max_entries;
1841
1842         scratch_pte = gen8_pte_encode(vm->scratch.addr,
1843                                       I915_CACHE_LLC,
1844                                       use_scratch);
1845         for (i = 0; i < num_entries; i++)
1846                 gen8_set_pte(&gtt_base[i], scratch_pte);
1847         readl(gtt_base);
1848 }
1849
1850 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1851                                   uint64_t start,
1852                                   uint64_t length,
1853                                   bool use_scratch)
1854 {
1855         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1856         unsigned first_entry = start >> PAGE_SHIFT;
1857         unsigned num_entries = length >> PAGE_SHIFT;
1858         gen6_pte_t scratch_pte, __iomem *gtt_base =
1859                 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1860         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1861         int i;
1862
1863         if (WARN(num_entries > max_entries,
1864                  "First entry = %d; Num entries = %d (max=%d)\n",
1865                  first_entry, num_entries, max_entries))
1866                 num_entries = max_entries;
1867
1868         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1869
1870         for (i = 0; i < num_entries; i++)
1871                 iowrite32(scratch_pte, &gtt_base[i]);
1872         readl(gtt_base);
1873 }
1874
1875 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1876                                      struct sg_table *pages,
1877                                      uint64_t start,
1878                                      enum i915_cache_level cache_level, u32 unused)
1879 {
1880         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1881                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1882
1883         intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
1884
1885 }
1886
1887 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1888                                   uint64_t start,
1889                                   uint64_t length,
1890                                   bool unused)
1891 {
1892         unsigned first_entry = start >> PAGE_SHIFT;
1893         unsigned num_entries = length >> PAGE_SHIFT;
1894         intel_gtt_clear_range(first_entry, num_entries);
1895 }
1896
1897 static int ggtt_bind_vma(struct i915_vma *vma,
1898                          enum i915_cache_level cache_level,
1899                          u32 flags)
1900 {
1901         struct drm_device *dev = vma->vm->dev;
1902         struct drm_i915_private *dev_priv = dev->dev_private;
1903         struct drm_i915_gem_object *obj = vma->obj;
1904         struct sg_table *pages = obj->pages;
1905         u32 pte_flags = 0;
1906         int ret;
1907
1908         ret = i915_get_ggtt_vma_pages(vma);
1909         if (ret)
1910                 return ret;
1911         pages = vma->ggtt_view.pages;
1912
1913         /* Currently applicable only to VLV */
1914         if (obj->gt_ro)
1915                 pte_flags |= PTE_READ_ONLY;
1916
1917
1918         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1919                 vma->vm->insert_entries(vma->vm, pages,
1920                                         vma->node.start,
1921                                         cache_level, pte_flags);
1922         }
1923
1924         if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
1925                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1926                 appgtt->base.insert_entries(&appgtt->base, pages,
1927                                             vma->node.start,
1928                                             cache_level, pte_flags);
1929         }
1930
1931         return 0;
1932 }
1933
1934 static void ggtt_unbind_vma(struct i915_vma *vma)
1935 {
1936         struct drm_device *dev = vma->vm->dev;
1937         struct drm_i915_private *dev_priv = dev->dev_private;
1938         struct drm_i915_gem_object *obj = vma->obj;
1939         const uint64_t size = min_t(uint64_t,
1940                                     obj->base.size,
1941                                     vma->node.size);
1942
1943         if (vma->bound & GLOBAL_BIND) {
1944                 vma->vm->clear_range(vma->vm,
1945                                      vma->node.start,
1946                                      size,
1947                                      true);
1948         }
1949
1950         if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
1951                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1952
1953                 appgtt->base.clear_range(&appgtt->base,
1954                                          vma->node.start,
1955                                          size,
1956                                          true);
1957         }
1958 }
1959
1960 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1961 {
1962         struct drm_device *dev = obj->base.dev;
1963         struct drm_i915_private *dev_priv = dev->dev_private;
1964         bool interruptible;
1965
1966         interruptible = do_idling(dev_priv);
1967
1968         if (!obj->has_dma_mapping)
1969                 dma_unmap_sg(&dev->pdev->dev,
1970                              obj->pages->sgl, obj->pages->nents,
1971                              PCI_DMA_BIDIRECTIONAL);
1972
1973         undo_idling(dev_priv, interruptible);
1974 }
1975
1976 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1977                                   unsigned long color,
1978                                   u64 *start,
1979                                   u64 *end)
1980 {
1981         if (node->color != color)
1982                 *start += 4096;
1983
1984         if (!list_empty(&node->node_list)) {
1985                 node = list_entry(node->node_list.next,
1986                                   struct drm_mm_node,
1987                                   node_list);
1988                 if (node->allocated && node->color != color)
1989                         *end -= 4096;
1990         }
1991 }
1992
1993 static int i915_gem_setup_global_gtt(struct drm_device *dev,
1994                                      unsigned long start,
1995                                      unsigned long mappable_end,
1996                                      unsigned long end)
1997 {
1998         /* Let GEM Manage all of the aperture.
1999          *
2000          * However, leave one page at the end still bound to the scratch page.
2001          * There are a number of places where the hardware apparently prefetches
2002          * past the end of the object, and we've seen multiple hangs with the
2003          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2004          * aperture.  One page should be enough to keep any prefetching inside
2005          * of the aperture.
2006          */
2007         struct drm_i915_private *dev_priv = dev->dev_private;
2008         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2009         struct drm_mm_node *entry;
2010         struct drm_i915_gem_object *obj;
2011         unsigned long hole_start, hole_end;
2012         int ret;
2013
2014         BUG_ON(mappable_end > end);
2015
2016         /* Subtract the guard page ... */
2017         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
2018
2019         dev_priv->gtt.base.start = start;
2020         dev_priv->gtt.base.total = end - start;
2021
2022         if (intel_vgpu_active(dev)) {
2023                 ret = intel_vgt_balloon(dev);
2024                 if (ret)
2025                         return ret;
2026         }
2027
2028         if (!HAS_LLC(dev))
2029                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
2030
2031         /* Mark any preallocated objects as occupied */
2032         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2033                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2034
2035                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2036                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
2037
2038                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2039                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2040                 if (ret) {
2041                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2042                         return ret;
2043                 }
2044                 vma->bound |= GLOBAL_BIND;
2045         }
2046
2047         /* Clear any non-preallocated blocks */
2048         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2049                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2050                               hole_start, hole_end);
2051                 ggtt_vm->clear_range(ggtt_vm, hole_start,
2052                                      hole_end - hole_start, true);
2053         }
2054
2055         /* And finally clear the reserved guard page */
2056         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2057
2058         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2059                 struct i915_hw_ppgtt *ppgtt;
2060
2061                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2062                 if (!ppgtt)
2063                         return -ENOMEM;
2064
2065                 ret = __hw_ppgtt_init(dev, ppgtt);
2066                 if (ret) {
2067                         ppgtt->base.cleanup(&ppgtt->base);
2068                         kfree(ppgtt);
2069                         return ret;
2070                 }
2071
2072                 if (ppgtt->base.allocate_va_range)
2073                         ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2074                                                             ppgtt->base.total);
2075                 if (ret) {
2076                         ppgtt->base.cleanup(&ppgtt->base);
2077                         kfree(ppgtt);
2078                         return ret;
2079                 }
2080
2081                 ppgtt->base.clear_range(&ppgtt->base,
2082                                         ppgtt->base.start,
2083                                         ppgtt->base.total,
2084                                         true);
2085
2086                 dev_priv->mm.aliasing_ppgtt = ppgtt;
2087         }
2088
2089         return 0;
2090 }
2091
2092 void i915_gem_init_global_gtt(struct drm_device *dev)
2093 {
2094         struct drm_i915_private *dev_priv = dev->dev_private;
2095         unsigned long gtt_size, mappable_size;
2096
2097         gtt_size = dev_priv->gtt.base.total;
2098         mappable_size = dev_priv->gtt.mappable_end;
2099
2100         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2101 }
2102
2103 void i915_global_gtt_cleanup(struct drm_device *dev)
2104 {
2105         struct drm_i915_private *dev_priv = dev->dev_private;
2106         struct i915_address_space *vm = &dev_priv->gtt.base;
2107
2108         if (dev_priv->mm.aliasing_ppgtt) {
2109                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2110
2111                 ppgtt->base.cleanup(&ppgtt->base);
2112         }
2113
2114         if (drm_mm_initialized(&vm->mm)) {
2115                 if (intel_vgpu_active(dev))
2116                         intel_vgt_deballoon();
2117
2118                 drm_mm_takedown(&vm->mm);
2119                 list_del(&vm->global_link);
2120         }
2121
2122         vm->cleanup(vm);
2123 }
2124
2125 static int setup_scratch_page(struct drm_device *dev)
2126 {
2127         struct drm_i915_private *dev_priv = dev->dev_private;
2128         struct page *page;
2129         dma_addr_t dma_addr;
2130
2131         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
2132         if (page == NULL)
2133                 return -ENOMEM;
2134         set_pages_uc(page, 1);
2135
2136 #ifdef CONFIG_INTEL_IOMMU
2137         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
2138                                 PCI_DMA_BIDIRECTIONAL);
2139         if (pci_dma_mapping_error(dev->pdev, dma_addr))
2140                 return -EINVAL;
2141 #else
2142         dma_addr = page_to_phys(page);
2143 #endif
2144         dev_priv->gtt.base.scratch.page = page;
2145         dev_priv->gtt.base.scratch.addr = dma_addr;
2146
2147         return 0;
2148 }
2149
2150 static void teardown_scratch_page(struct drm_device *dev)
2151 {
2152         struct drm_i915_private *dev_priv = dev->dev_private;
2153         struct page *page = dev_priv->gtt.base.scratch.page;
2154
2155         set_pages_wb(page, 1);
2156         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
2157                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
2158         __free_page(page);
2159 }
2160
2161 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2162 {
2163         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2164         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2165         return snb_gmch_ctl << 20;
2166 }
2167
2168 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2169 {
2170         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2171         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2172         if (bdw_gmch_ctl)
2173                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2174
2175 #ifdef CONFIG_X86_32
2176         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2177         if (bdw_gmch_ctl > 4)
2178                 bdw_gmch_ctl = 4;
2179 #endif
2180
2181         return bdw_gmch_ctl << 20;
2182 }
2183
2184 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2185 {
2186         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2187         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2188
2189         if (gmch_ctrl)
2190                 return 1 << (20 + gmch_ctrl);
2191
2192         return 0;
2193 }
2194
2195 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2196 {
2197         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2198         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2199         return snb_gmch_ctl << 25; /* 32 MB units */
2200 }
2201
2202 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2203 {
2204         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2205         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2206         return bdw_gmch_ctl << 25; /* 32 MB units */
2207 }
2208
2209 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2210 {
2211         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2212         gmch_ctrl &= SNB_GMCH_GMS_MASK;
2213
2214         /*
2215          * 0x0  to 0x10: 32MB increments starting at 0MB
2216          * 0x11 to 0x16: 4MB increments starting at 8MB
2217          * 0x17 to 0x1d: 4MB increments start at 36MB
2218          */
2219         if (gmch_ctrl < 0x11)
2220                 return gmch_ctrl << 25;
2221         else if (gmch_ctrl < 0x17)
2222                 return (gmch_ctrl - 0x11 + 2) << 22;
2223         else
2224                 return (gmch_ctrl - 0x17 + 9) << 22;
2225 }
2226
2227 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2228 {
2229         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2230         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2231
2232         if (gen9_gmch_ctl < 0xf0)
2233                 return gen9_gmch_ctl << 25; /* 32 MB units */
2234         else
2235                 /* 4MB increments starting at 0xf0 for 4MB */
2236                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2237 }
2238
2239 static int ggtt_probe_common(struct drm_device *dev,
2240                              size_t gtt_size)
2241 {
2242         struct drm_i915_private *dev_priv = dev->dev_private;
2243         phys_addr_t gtt_phys_addr;
2244         int ret;
2245
2246         /* For Modern GENs the PTEs and register space are split in the BAR */
2247         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2248                 (pci_resource_len(dev->pdev, 0) / 2);
2249
2250         /*
2251          * On BXT writes larger than 64 bit to the GTT pagetable range will be
2252          * dropped. For WC mappings in general we have 64 byte burst writes
2253          * when the WC buffer is flushed, so we can't use it, but have to
2254          * resort to an uncached mapping. The WC issue is easily caught by the
2255          * readback check when writing GTT PTE entries.
2256          */
2257         if (IS_BROXTON(dev))
2258                 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2259         else
2260                 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2261         if (!dev_priv->gtt.gsm) {
2262                 DRM_ERROR("Failed to map the gtt page table\n");
2263                 return -ENOMEM;
2264         }
2265
2266         ret = setup_scratch_page(dev);
2267         if (ret) {
2268                 DRM_ERROR("Scratch setup failed\n");
2269                 /* iounmap will also get called at remove, but meh */
2270                 iounmap(dev_priv->gtt.gsm);
2271         }
2272
2273         return ret;
2274 }
2275
2276 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2277  * bits. When using advanced contexts each context stores its own PAT, but
2278  * writing this data shouldn't be harmful even in those cases. */
2279 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2280 {
2281         uint64_t pat;
2282
2283         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
2284               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2285               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2286               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
2287               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2288               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2289               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2290               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2291
2292         if (!USES_PPGTT(dev_priv->dev))
2293                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2294                  * so RTL will always use the value corresponding to
2295                  * pat_sel = 000".
2296                  * So let's disable cache for GGTT to avoid screen corruptions.
2297                  * MOCS still can be used though.
2298                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2299                  * before this patch, i.e. the same uncached + snooping access
2300                  * like on gen6/7 seems to be in effect.
2301                  * - So this just fixes blitter/render access. Again it looks
2302                  * like it's not just uncached access, but uncached + snooping.
2303                  * So we can still hold onto all our assumptions wrt cpu
2304                  * clflushing on LLC machines.
2305                  */
2306                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2307
2308         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2309          * write would work. */
2310         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2311         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2312 }
2313
2314 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2315 {
2316         uint64_t pat;
2317
2318         /*
2319          * Map WB on BDW to snooped on CHV.
2320          *
2321          * Only the snoop bit has meaning for CHV, the rest is
2322          * ignored.
2323          *
2324          * The hardware will never snoop for certain types of accesses:
2325          * - CPU GTT (GMADR->GGTT->no snoop->memory)
2326          * - PPGTT page tables
2327          * - some other special cycles
2328          *
2329          * As with BDW, we also need to consider the following for GT accesses:
2330          * "For GGTT, there is NO pat_sel[2:0] from the entry,
2331          * so RTL will always use the value corresponding to
2332          * pat_sel = 000".
2333          * Which means we must set the snoop bit in PAT entry 0
2334          * in order to keep the global status page working.
2335          */
2336         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2337               GEN8_PPAT(1, 0) |
2338               GEN8_PPAT(2, 0) |
2339               GEN8_PPAT(3, 0) |
2340               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2341               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2342               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2343               GEN8_PPAT(7, CHV_PPAT_SNOOP);
2344
2345         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2346         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2347 }
2348
2349 static int gen8_gmch_probe(struct drm_device *dev,
2350                            size_t *gtt_total,
2351                            size_t *stolen,
2352                            phys_addr_t *mappable_base,
2353                            unsigned long *mappable_end)
2354 {
2355         struct drm_i915_private *dev_priv = dev->dev_private;
2356         unsigned int gtt_size;
2357         u16 snb_gmch_ctl;
2358         int ret;
2359
2360         /* TODO: We're not aware of mappable constraints on gen8 yet */
2361         *mappable_base = pci_resource_start(dev->pdev, 2);
2362         *mappable_end = pci_resource_len(dev->pdev, 2);
2363
2364         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2365                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2366
2367         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2368
2369         if (INTEL_INFO(dev)->gen >= 9) {
2370                 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2371                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2372         } else if (IS_CHERRYVIEW(dev)) {
2373                 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2374                 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2375         } else {
2376                 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2377                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2378         }
2379
2380         *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2381
2382         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2383                 chv_setup_private_ppat(dev_priv);
2384         else
2385                 bdw_setup_private_ppat(dev_priv);
2386
2387         ret = ggtt_probe_common(dev, gtt_size);
2388
2389         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2390         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2391         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2392         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2393
2394         return ret;
2395 }
2396
2397 static int gen6_gmch_probe(struct drm_device *dev,
2398                            size_t *gtt_total,
2399                            size_t *stolen,
2400                            phys_addr_t *mappable_base,
2401                            unsigned long *mappable_end)
2402 {
2403         struct drm_i915_private *dev_priv = dev->dev_private;
2404         unsigned int gtt_size;
2405         u16 snb_gmch_ctl;
2406         int ret;
2407
2408         *mappable_base = pci_resource_start(dev->pdev, 2);
2409         *mappable_end = pci_resource_len(dev->pdev, 2);
2410
2411         /* 64/512MB is the current min/max we actually know of, but this is just
2412          * a coarse sanity check.
2413          */
2414         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2415                 DRM_ERROR("Unknown GMADR size (%lx)\n",
2416                           dev_priv->gtt.mappable_end);
2417                 return -ENXIO;
2418         }
2419
2420         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2421                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2422         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2423
2424         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2425
2426         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2427         *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
2428
2429         ret = ggtt_probe_common(dev, gtt_size);
2430
2431         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2432         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2433         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2434         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2435
2436         return ret;
2437 }
2438
2439 static void gen6_gmch_remove(struct i915_address_space *vm)
2440 {
2441
2442         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2443
2444         iounmap(gtt->gsm);
2445         teardown_scratch_page(vm->dev);
2446 }
2447
2448 static int i915_gmch_probe(struct drm_device *dev,
2449                            size_t *gtt_total,
2450                            size_t *stolen,
2451                            phys_addr_t *mappable_base,
2452                            unsigned long *mappable_end)
2453 {
2454         struct drm_i915_private *dev_priv = dev->dev_private;
2455         int ret;
2456
2457         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2458         if (!ret) {
2459                 DRM_ERROR("failed to set up gmch\n");
2460                 return -EIO;
2461         }
2462
2463         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2464
2465         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2466         dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
2467         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2468         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2469         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2470
2471         if (unlikely(dev_priv->gtt.do_idle_maps))
2472                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2473
2474         return 0;
2475 }
2476
2477 static void i915_gmch_remove(struct i915_address_space *vm)
2478 {
2479         intel_gmch_remove();
2480 }
2481
2482 int i915_gem_gtt_init(struct drm_device *dev)
2483 {
2484         struct drm_i915_private *dev_priv = dev->dev_private;
2485         struct i915_gtt *gtt = &dev_priv->gtt;
2486         int ret;
2487
2488         if (INTEL_INFO(dev)->gen <= 5) {
2489                 gtt->gtt_probe = i915_gmch_probe;
2490                 gtt->base.cleanup = i915_gmch_remove;
2491         } else if (INTEL_INFO(dev)->gen < 8) {
2492                 gtt->gtt_probe = gen6_gmch_probe;
2493                 gtt->base.cleanup = gen6_gmch_remove;
2494                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2495                         gtt->base.pte_encode = iris_pte_encode;
2496                 else if (IS_HASWELL(dev))
2497                         gtt->base.pte_encode = hsw_pte_encode;
2498                 else if (IS_VALLEYVIEW(dev))
2499                         gtt->base.pte_encode = byt_pte_encode;
2500                 else if (INTEL_INFO(dev)->gen >= 7)
2501                         gtt->base.pte_encode = ivb_pte_encode;
2502                 else
2503                         gtt->base.pte_encode = snb_pte_encode;
2504         } else {
2505                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2506                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2507         }
2508
2509         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2510                              &gtt->mappable_base, &gtt->mappable_end);
2511         if (ret)
2512                 return ret;
2513
2514         gtt->base.dev = dev;
2515
2516         /* GMADR is the PCI mmio aperture into the global GTT. */
2517         DRM_INFO("Memory usable by graphics device = %zdM\n",
2518                  gtt->base.total >> 20);
2519         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2520         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2521 #ifdef CONFIG_INTEL_IOMMU
2522         if (intel_iommu_gfx_mapped)
2523                 DRM_INFO("VT-d active for gfx access\n");
2524 #endif
2525         /*
2526          * i915.enable_ppgtt is read-only, so do an early pass to validate the
2527          * user's requested state against the hardware/driver capabilities.  We
2528          * do this now so that we can print out any log messages once rather
2529          * than every time we check intel_enable_ppgtt().
2530          */
2531         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2532         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2533
2534         return 0;
2535 }
2536
2537 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2538 {
2539         struct drm_i915_private *dev_priv = dev->dev_private;
2540         struct drm_i915_gem_object *obj;
2541         struct i915_address_space *vm;
2542
2543         i915_check_and_clear_faults(dev);
2544
2545         /* First fill our portion of the GTT with scratch pages */
2546         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2547                                        dev_priv->gtt.base.start,
2548                                        dev_priv->gtt.base.total,
2549                                        true);
2550
2551         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2552                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
2553                                                            &dev_priv->gtt.base);
2554                 if (!vma)
2555                         continue;
2556
2557                 i915_gem_clflush_object(obj, obj->pin_display);
2558                 WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
2559         }
2560
2561
2562         if (INTEL_INFO(dev)->gen >= 8) {
2563                 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2564                         chv_setup_private_ppat(dev_priv);
2565                 else
2566                         bdw_setup_private_ppat(dev_priv);
2567
2568                 return;
2569         }
2570
2571         if (USES_PPGTT(dev)) {
2572                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2573                         /* TODO: Perhaps it shouldn't be gen6 specific */
2574
2575                         struct i915_hw_ppgtt *ppgtt =
2576                                         container_of(vm, struct i915_hw_ppgtt,
2577                                                      base);
2578
2579                         if (i915_is_ggtt(vm))
2580                                 ppgtt = dev_priv->mm.aliasing_ppgtt;
2581
2582                         gen6_write_page_range(dev_priv, &ppgtt->pd,
2583                                               0, ppgtt->base.total);
2584                 }
2585         }
2586
2587         i915_ggtt_flush(dev_priv);
2588 }
2589
2590 static struct i915_vma *
2591 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
2592                       struct i915_address_space *vm,
2593                       const struct i915_ggtt_view *ggtt_view)
2594 {
2595         struct i915_vma *vma;
2596
2597         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2598                 return ERR_PTR(-EINVAL);
2599
2600         vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
2601         if (vma == NULL)
2602                 return ERR_PTR(-ENOMEM);
2603
2604         INIT_LIST_HEAD(&vma->vma_link);
2605         INIT_LIST_HEAD(&vma->mm_list);
2606         INIT_LIST_HEAD(&vma->exec_list);
2607         vma->vm = vm;
2608         vma->obj = obj;
2609
2610         if (i915_is_ggtt(vm))
2611                 vma->ggtt_view = *ggtt_view;
2612
2613         list_add_tail(&vma->vma_link, &obj->vma_list);
2614         if (!i915_is_ggtt(vm))
2615                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2616
2617         return vma;
2618 }
2619
2620 struct i915_vma *
2621 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2622                                   struct i915_address_space *vm)
2623 {
2624         struct i915_vma *vma;
2625
2626         vma = i915_gem_obj_to_vma(obj, vm);
2627         if (!vma)
2628                 vma = __i915_gem_vma_create(obj, vm,
2629                                             i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2630
2631         return vma;
2632 }
2633
2634 struct i915_vma *
2635 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2636                                        const struct i915_ggtt_view *view)
2637 {
2638         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2639         struct i915_vma *vma;
2640
2641         if (WARN_ON(!view))
2642                 return ERR_PTR(-EINVAL);
2643
2644         vma = i915_gem_obj_to_ggtt_view(obj, view);
2645
2646         if (IS_ERR(vma))
2647                 return vma;
2648
2649         if (!vma)
2650                 vma = __i915_gem_vma_create(obj, ggtt, view);
2651
2652         return vma;
2653
2654 }
2655
2656 static void
2657 rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2658              struct sg_table *st)
2659 {
2660         unsigned int column, row;
2661         unsigned int src_idx;
2662         struct scatterlist *sg = st->sgl;
2663
2664         st->nents = 0;
2665
2666         for (column = 0; column < width; column++) {
2667                 src_idx = width * (height - 1) + column;
2668                 for (row = 0; row < height; row++) {
2669                         st->nents++;
2670                         /* We don't need the pages, but need to initialize
2671                          * the entries so the sg list can be happily traversed.
2672                          * The only thing we need are DMA addresses.
2673                          */
2674                         sg_set_page(sg, NULL, PAGE_SIZE, 0);
2675                         sg_dma_address(sg) = in[src_idx];
2676                         sg_dma_len(sg) = PAGE_SIZE;
2677                         sg = sg_next(sg);
2678                         src_idx -= width;
2679                 }
2680         }
2681 }
2682
2683 static struct sg_table *
2684 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2685                           struct drm_i915_gem_object *obj)
2686 {
2687         struct drm_device *dev = obj->base.dev;
2688         struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
2689         unsigned long size, pages, rot_pages;
2690         struct sg_page_iter sg_iter;
2691         unsigned long i;
2692         dma_addr_t *page_addr_list;
2693         struct sg_table *st;
2694         unsigned int tile_pitch, tile_height;
2695         unsigned int width_pages, height_pages;
2696         int ret = -ENOMEM;
2697
2698         pages = obj->base.size / PAGE_SIZE;
2699
2700         /* Calculate tiling geometry. */
2701         tile_height = intel_tile_height(dev, rot_info->pixel_format,
2702                                         rot_info->fb_modifier);
2703         tile_pitch = PAGE_SIZE / tile_height;
2704         width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch);
2705         height_pages = DIV_ROUND_UP(rot_info->height, tile_height);
2706         rot_pages = width_pages * height_pages;
2707         size = rot_pages * PAGE_SIZE;
2708
2709         /* Allocate a temporary list of source pages for random access. */
2710         page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t));
2711         if (!page_addr_list)
2712                 return ERR_PTR(ret);
2713
2714         /* Allocate target SG list. */
2715         st = kmalloc(sizeof(*st), GFP_KERNEL);
2716         if (!st)
2717                 goto err_st_alloc;
2718
2719         ret = sg_alloc_table(st, rot_pages, GFP_KERNEL);
2720         if (ret)
2721                 goto err_sg_alloc;
2722
2723         /* Populate source page list from the object. */
2724         i = 0;
2725         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2726                 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2727                 i++;
2728         }
2729
2730         /* Rotate the pages. */
2731         rotate_pages(page_addr_list, width_pages, height_pages, st);
2732
2733         DRM_DEBUG_KMS(
2734                       "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n",
2735                       size, rot_info->pitch, rot_info->height,
2736                       rot_info->pixel_format, width_pages, height_pages,
2737                       rot_pages);
2738
2739         drm_free_large(page_addr_list);
2740
2741         return st;
2742
2743 err_sg_alloc:
2744         kfree(st);
2745 err_st_alloc:
2746         drm_free_large(page_addr_list);
2747
2748         DRM_DEBUG_KMS(
2749                       "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n",
2750                       size, ret, rot_info->pitch, rot_info->height,
2751                       rot_info->pixel_format, width_pages, height_pages,
2752                       rot_pages);
2753         return ERR_PTR(ret);
2754 }
2755
2756 static struct sg_table *
2757 intel_partial_pages(const struct i915_ggtt_view *view,
2758                     struct drm_i915_gem_object *obj)
2759 {
2760         struct sg_table *st;
2761         struct scatterlist *sg;
2762         struct sg_page_iter obj_sg_iter;
2763         int ret = -ENOMEM;
2764
2765         st = kmalloc(sizeof(*st), GFP_KERNEL);
2766         if (!st)
2767                 goto err_st_alloc;
2768
2769         ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2770         if (ret)
2771                 goto err_sg_alloc;
2772
2773         sg = st->sgl;
2774         st->nents = 0;
2775         for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2776                 view->params.partial.offset)
2777         {
2778                 if (st->nents >= view->params.partial.size)
2779                         break;
2780
2781                 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2782                 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2783                 sg_dma_len(sg) = PAGE_SIZE;
2784
2785                 sg = sg_next(sg);
2786                 st->nents++;
2787         }
2788
2789         return st;
2790
2791 err_sg_alloc:
2792         kfree(st);
2793 err_st_alloc:
2794         return ERR_PTR(ret);
2795 }
2796
2797 static int
2798 i915_get_ggtt_vma_pages(struct i915_vma *vma)
2799 {
2800         int ret = 0;
2801
2802         if (vma->ggtt_view.pages)
2803                 return 0;
2804
2805         if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2806                 vma->ggtt_view.pages = vma->obj->pages;
2807         else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2808                 vma->ggtt_view.pages =
2809                         intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
2810         else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2811                 vma->ggtt_view.pages =
2812                         intel_partial_pages(&vma->ggtt_view, vma->obj);
2813         else
2814                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2815                           vma->ggtt_view.type);
2816
2817         if (!vma->ggtt_view.pages) {
2818                 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2819                           vma->ggtt_view.type);
2820                 ret = -EINVAL;
2821         } else if (IS_ERR(vma->ggtt_view.pages)) {
2822                 ret = PTR_ERR(vma->ggtt_view.pages);
2823                 vma->ggtt_view.pages = NULL;
2824                 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2825                           vma->ggtt_view.type, ret);
2826         }
2827
2828         return ret;
2829 }
2830
2831 /**
2832  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2833  * @vma: VMA to map
2834  * @cache_level: mapping cache level
2835  * @flags: flags like global or local mapping
2836  *
2837  * DMA addresses are taken from the scatter-gather table of this object (or of
2838  * this VMA in case of non-default GGTT views) and PTE entries set up.
2839  * Note that DMA addresses are also the only part of the SG table we care about.
2840  */
2841 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2842                   u32 flags)
2843 {
2844         int ret;
2845         u32 bind_flags;
2846
2847         if (WARN_ON(flags == 0))
2848                 return -EINVAL;
2849
2850         bind_flags = 0;
2851         if (flags & PIN_GLOBAL)
2852                 bind_flags |= GLOBAL_BIND;
2853         if (flags & PIN_USER)
2854                 bind_flags |= LOCAL_BIND;
2855
2856         if (flags & PIN_UPDATE)
2857                 bind_flags |= vma->bound;
2858         else
2859                 bind_flags &= ~vma->bound;
2860
2861         if (bind_flags == 0)
2862                 return 0;
2863
2864         if (vma->bound == 0 && vma->vm->allocate_va_range) {
2865                 trace_i915_va_alloc(vma->vm,
2866                                     vma->node.start,
2867                                     vma->node.size,
2868                                     VM_TO_TRACE_NAME(vma->vm));
2869
2870                 ret = vma->vm->allocate_va_range(vma->vm,
2871                                                  vma->node.start,
2872                                                  vma->node.size);
2873                 if (ret)
2874                         return ret;
2875         }
2876
2877         ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
2878         if (ret)
2879                 return ret;
2880
2881         vma->bound |= bind_flags;
2882
2883         return 0;
2884 }
2885
2886 /**
2887  * i915_ggtt_view_size - Get the size of a GGTT view.
2888  * @obj: Object the view is of.
2889  * @view: The view in question.
2890  *
2891  * @return The size of the GGTT view in bytes.
2892  */
2893 size_t
2894 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
2895                     const struct i915_ggtt_view *view)
2896 {
2897         if (view->type == I915_GGTT_VIEW_NORMAL ||
2898             view->type == I915_GGTT_VIEW_ROTATED) {
2899                 return obj->base.size;
2900         } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
2901                 return view->params.partial.size << PAGE_SHIFT;
2902         } else {
2903                 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
2904                 return obj->base.size;
2905         }
2906 }