1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29 #define _PLANE(plane, a, b) _PIPE(plane, a, b)
30 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
32 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
33 (pipe) == PIPE_B ? (b) : (c))
34 #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
35 (port) == PORT_B ? (b) : (c))
37 #define _MASKED_FIELD(mask, value) ({ \
38 if (__builtin_constant_p(mask)) \
39 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
40 if (__builtin_constant_p(value)) \
41 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
42 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
43 BUILD_BUG_ON_MSG((value) & ~(mask), \
44 "Incorrect value for mask"); \
45 (mask) << 16 | (value); })
46 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
47 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
51 /* PCI config space */
53 #define HPLLCC 0xc0 /* 855 only */
54 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
55 #define GC_CLOCK_133_200 (0 << 0)
56 #define GC_CLOCK_100_200 (1 << 0)
57 #define GC_CLOCK_100_133 (2 << 0)
58 #define GC_CLOCK_166_250 (3 << 0)
60 #define GCFGC 0xf0 /* 915+ only */
61 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
62 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
63 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
64 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
65 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
66 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
67 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
68 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
69 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
70 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
71 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
72 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
73 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
74 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
75 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
76 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
77 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
78 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
79 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
80 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
81 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
82 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
83 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
84 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
85 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
86 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
87 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
88 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
89 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
91 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
94 /* Graphics reset regs */
95 #define I915_GDRST 0xc0 /* PCI config register */
96 #define GRDOM_FULL (0<<2)
97 #define GRDOM_RENDER (1<<2)
98 #define GRDOM_MEDIA (3<<2)
99 #define GRDOM_MASK (3<<2)
100 #define GRDOM_RESET_STATUS (1<<1)
101 #define GRDOM_RESET_ENABLE (1<<0)
103 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
104 #define ILK_GRDOM_FULL (0<<1)
105 #define ILK_GRDOM_RENDER (1<<1)
106 #define ILK_GRDOM_MEDIA (3<<1)
107 #define ILK_GRDOM_MASK (3<<1)
108 #define ILK_GRDOM_RESET_ENABLE (1<<0)
110 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
111 #define GEN6_MBC_SNPCR_SHIFT 21
112 #define GEN6_MBC_SNPCR_MASK (3<<21)
113 #define GEN6_MBC_SNPCR_MAX (0<<21)
114 #define GEN6_MBC_SNPCR_MED (1<<21)
115 #define GEN6_MBC_SNPCR_LOW (2<<21)
116 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
118 #define VLV_G3DCTL 0x9024
119 #define VLV_GSCKGCTL 0x9028
121 #define GEN6_MBCTL 0x0907c
122 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
123 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
124 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
125 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
126 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
128 #define GEN6_GDRST 0x941c
129 #define GEN6_GRDOM_FULL (1 << 0)
130 #define GEN6_GRDOM_RENDER (1 << 1)
131 #define GEN6_GRDOM_MEDIA (1 << 2)
132 #define GEN6_GRDOM_BLT (1 << 3)
134 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
135 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
136 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
137 #define PP_DIR_DCLV_2G 0xffffffff
139 #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
140 #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
142 #define GAM_ECOCHK 0x4090
143 #define ECOCHK_SNB_BIT (1<<10)
144 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
145 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
146 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
147 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
148 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
149 #define ECOCHK_PPGTT_UC_HSW (0x1<<3)
150 #define ECOCHK_PPGTT_WT_HSW (0x2<<3)
151 #define ECOCHK_PPGTT_WB_HSW (0x3<<3)
153 #define GAC_ECO_BITS 0x14090
154 #define ECOBITS_SNB_BIT (1<<13)
155 #define ECOBITS_PPGTT_CACHE64B (3<<8)
156 #define ECOBITS_PPGTT_CACHE4B (0<<8)
158 #define GAB_CTL 0x24000
159 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
161 #define GEN7_BIOS_RESERVED 0x1082C0
162 #define GEN7_BIOS_RESERVED_1M (0 << 5)
163 #define GEN7_BIOS_RESERVED_256K (1 << 5)
164 #define GEN8_BIOS_RESERVED_SHIFT 7
165 #define GEN7_BIOS_RESERVED_MASK 0x1
166 #define GEN8_BIOS_RESERVED_MASK 0x3
171 #define VGA_ST01_MDA 0x3ba
172 #define VGA_ST01_CGA 0x3da
174 #define VGA_MSR_WRITE 0x3c2
175 #define VGA_MSR_READ 0x3cc
176 #define VGA_MSR_MEM_EN (1<<1)
177 #define VGA_MSR_CGA_MODE (1<<0)
179 #define VGA_SR_INDEX 0x3c4
181 #define VGA_SR_DATA 0x3c5
183 #define VGA_AR_INDEX 0x3c0
184 #define VGA_AR_VID_EN (1<<5)
185 #define VGA_AR_DATA_WRITE 0x3c0
186 #define VGA_AR_DATA_READ 0x3c1
188 #define VGA_GR_INDEX 0x3ce
189 #define VGA_GR_DATA 0x3cf
191 #define VGA_GR_MEM_READ_MODE_SHIFT 3
192 #define VGA_GR_MEM_READ_MODE_PLANE 1
194 #define VGA_GR_MEM_MODE_MASK 0xc
195 #define VGA_GR_MEM_MODE_SHIFT 2
196 #define VGA_GR_MEM_A0000_AFFFF 0
197 #define VGA_GR_MEM_A0000_BFFFF 1
198 #define VGA_GR_MEM_B0000_B7FFF 2
199 #define VGA_GR_MEM_B0000_BFFFF 3
201 #define VGA_DACMASK 0x3c6
202 #define VGA_DACRX 0x3c7
203 #define VGA_DACWX 0x3c8
204 #define VGA_DACDATA 0x3c9
206 #define VGA_CR_INDEX_MDA 0x3b4
207 #define VGA_CR_DATA_MDA 0x3b5
208 #define VGA_CR_INDEX_CGA 0x3d4
209 #define VGA_CR_DATA_CGA 0x3d5
212 * Instruction field definitions used by the command parser
214 #define INSTR_CLIENT_SHIFT 29
215 #define INSTR_CLIENT_MASK 0xE0000000
216 #define INSTR_MI_CLIENT 0x0
217 #define INSTR_BC_CLIENT 0x2
218 #define INSTR_RC_CLIENT 0x3
219 #define INSTR_SUBCLIENT_SHIFT 27
220 #define INSTR_SUBCLIENT_MASK 0x18000000
221 #define INSTR_MEDIA_SUBCLIENT 0x2
222 #define INSTR_26_TO_24_MASK 0x7000000
223 #define INSTR_26_TO_24_SHIFT 24
226 * Memory interface instructions used by the kernel
228 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
229 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
230 #define MI_GLOBAL_GTT (1<<22)
232 #define MI_NOOP MI_INSTR(0, 0)
233 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
234 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
235 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
236 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
237 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
238 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
239 #define MI_FLUSH MI_INSTR(0x04, 0)
240 #define MI_READ_FLUSH (1 << 0)
241 #define MI_EXE_FLUSH (1 << 1)
242 #define MI_NO_WRITE_FLUSH (1 << 2)
243 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
244 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
245 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
246 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
247 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
248 #define MI_ARB_ENABLE (1<<0)
249 #define MI_ARB_DISABLE (0<<0)
250 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
251 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
252 #define MI_SUSPEND_FLUSH_EN (1<<0)
253 #define MI_SET_APPID MI_INSTR(0x0e, 0)
254 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
255 #define MI_OVERLAY_CONTINUE (0x0<<21)
256 #define MI_OVERLAY_ON (0x1<<21)
257 #define MI_OVERLAY_OFF (0x2<<21)
258 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
259 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
260 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
261 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
262 /* IVB has funny definitions for which plane to flip. */
263 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
264 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
265 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
266 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
267 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
268 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
270 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
271 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
272 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
273 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
274 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
275 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
276 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
277 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
278 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
279 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
280 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
281 #define MI_SEMAPHORE_UPDATE (1<<21)
282 #define MI_SEMAPHORE_COMPARE (1<<20)
283 #define MI_SEMAPHORE_REGISTER (1<<18)
284 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
285 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
286 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
287 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
288 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
289 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
290 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
291 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
292 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
293 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
294 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
295 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
296 #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
297 #define MI_SEMAPHORE_SYNC_MASK (3<<16)
298 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
299 #define MI_MM_SPACE_GTT (1<<8)
300 #define MI_MM_SPACE_PHYSICAL (0<<8)
301 #define MI_SAVE_EXT_STATE_EN (1<<3)
302 #define MI_RESTORE_EXT_STATE_EN (1<<2)
303 #define MI_FORCE_RESTORE (1<<1)
304 #define MI_RESTORE_INHIBIT (1<<0)
305 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
306 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
307 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
308 #define MI_SEMAPHORE_POLL (1<<15)
309 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
310 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
311 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
312 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
313 #define MI_USE_GGTT (1 << 22) /* g4x+ */
314 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
315 #define MI_STORE_DWORD_INDEX_SHIFT 2
316 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
317 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
318 * simply ignores the register load under certain conditions.
319 * - One can actually load arbitrary many arbitrary registers: Simply issue x
320 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
322 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
323 #define MI_LRI_FORCE_POSTED (1<<12)
324 #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
325 #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
326 #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
327 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
328 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
329 #define MI_INVALIDATE_TLB (1<<18)
330 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
331 #define MI_FLUSH_DW_OP_MASK (3<<14)
332 #define MI_FLUSH_DW_NOTIFY (1<<8)
333 #define MI_INVALIDATE_BSD (1<<7)
334 #define MI_FLUSH_DW_USE_GTT (1<<2)
335 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
336 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
337 #define MI_BATCH_NON_SECURE (1)
338 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
339 #define MI_BATCH_NON_SECURE_I965 (1<<8)
340 #define MI_BATCH_PPGTT_HSW (1<<8)
341 #define MI_BATCH_NON_SECURE_HSW (1<<13)
342 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
343 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
344 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
346 #define MI_PREDICATE_SRC0 (0x2400)
347 #define MI_PREDICATE_SRC1 (0x2408)
349 #define MI_PREDICATE_RESULT_2 (0x2214)
350 #define LOWER_SLICE_ENABLED (1<<0)
351 #define LOWER_SLICE_DISABLED (0<<0)
354 * 3D instructions used by the kernel
356 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
358 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
359 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
360 #define SC_UPDATE_SCISSOR (0x1<<1)
361 #define SC_ENABLE_MASK (0x1<<0)
362 #define SC_ENABLE (0x1<<0)
363 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
364 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
365 #define SCI_YMIN_MASK (0xffff<<16)
366 #define SCI_XMIN_MASK (0xffff<<0)
367 #define SCI_YMAX_MASK (0xffff<<16)
368 #define SCI_XMAX_MASK (0xffff<<0)
369 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
370 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
371 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
372 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
373 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
374 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
375 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
376 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
377 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
379 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
380 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
381 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
382 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
383 #define BLT_WRITE_A (2<<20)
384 #define BLT_WRITE_RGB (1<<20)
385 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
386 #define BLT_DEPTH_8 (0<<24)
387 #define BLT_DEPTH_16_565 (1<<24)
388 #define BLT_DEPTH_16_1555 (2<<24)
389 #define BLT_DEPTH_32 (3<<24)
390 #define BLT_ROP_SRC_COPY (0xcc<<16)
391 #define BLT_ROP_COLOR_COPY (0xf0<<16)
392 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
393 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
394 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
395 #define ASYNC_FLIP (1<<22)
396 #define DISPLAY_PLANE_A (0<<20)
397 #define DISPLAY_PLANE_B (1<<20)
398 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
399 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
400 #define PIPE_CONTROL_MMIO_WRITE (1<<23)
401 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
402 #define PIPE_CONTROL_CS_STALL (1<<20)
403 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
404 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
405 #define PIPE_CONTROL_QW_WRITE (1<<14)
406 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
407 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
408 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
409 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
410 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
411 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
412 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
413 #define PIPE_CONTROL_NOTIFY (1<<8)
414 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
415 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
416 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
417 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
418 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
419 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
420 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
423 * Commands used only by the command parser
425 #define MI_SET_PREDICATE MI_INSTR(0x01, 0)
426 #define MI_ARB_CHECK MI_INSTR(0x05, 0)
427 #define MI_RS_CONTROL MI_INSTR(0x06, 0)
428 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
429 #define MI_PREDICATE MI_INSTR(0x0C, 0)
430 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
431 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
432 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
433 #define MI_URB_CLEAR MI_INSTR(0x19, 0)
434 #define MI_UPDATE_GTT MI_INSTR(0x23, 0)
435 #define MI_CLFLUSH MI_INSTR(0x27, 0)
436 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
437 #define MI_REPORT_PERF_COUNT_GGTT (1<<0)
438 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
439 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
440 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
441 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
442 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
443 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
445 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
446 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
447 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
448 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
449 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
450 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
451 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
452 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
453 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
454 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
455 #define GFX_OP_3DSTATE_SO_DECL_LIST \
456 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
458 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
459 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
460 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
461 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
462 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
463 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
464 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
465 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
466 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
467 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
469 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
471 #define COLOR_BLT ((0x2<<29)|(0x40<<22))
472 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
475 * Registers used only by the command parser
477 #define BCS_SWCTRL 0x22200
479 #define GPGPU_THREADS_DISPATCHED 0x2290
480 #define HS_INVOCATION_COUNT 0x2300
481 #define DS_INVOCATION_COUNT 0x2308
482 #define IA_VERTICES_COUNT 0x2310
483 #define IA_PRIMITIVES_COUNT 0x2318
484 #define VS_INVOCATION_COUNT 0x2320
485 #define GS_INVOCATION_COUNT 0x2328
486 #define GS_PRIMITIVES_COUNT 0x2330
487 #define CL_INVOCATION_COUNT 0x2338
488 #define CL_PRIMITIVES_COUNT 0x2340
489 #define PS_INVOCATION_COUNT 0x2348
490 #define PS_DEPTH_COUNT 0x2350
492 /* There are the 4 64-bit counter registers, one for each stream output */
493 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
495 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
497 #define GEN7_3DPRIM_END_OFFSET 0x2420
498 #define GEN7_3DPRIM_START_VERTEX 0x2430
499 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
500 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
501 #define GEN7_3DPRIM_START_INSTANCE 0x243C
502 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
504 #define OACONTROL 0x2360
506 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
507 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
508 #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
509 _GEN7_PIPEA_DE_LOAD_SL, \
510 _GEN7_PIPEB_DE_LOAD_SL)
515 #define DEBUG_RESET_I830 0x6070
516 #define DEBUG_RESET_FULL (1<<7)
517 #define DEBUG_RESET_RENDER (1<<8)
518 #define DEBUG_RESET_DISPLAY (1<<9)
523 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
524 #define IOSF_DEVFN_SHIFT 24
525 #define IOSF_OPCODE_SHIFT 16
526 #define IOSF_PORT_SHIFT 8
527 #define IOSF_BYTE_ENABLES_SHIFT 4
528 #define IOSF_BAR_SHIFT 1
529 #define IOSF_SB_BUSY (1<<0)
530 #define IOSF_PORT_BUNIT 0x3
531 #define IOSF_PORT_PUNIT 0x4
532 #define IOSF_PORT_NC 0x11
533 #define IOSF_PORT_DPIO 0x12
534 #define IOSF_PORT_DPIO_2 0x1a
535 #define IOSF_PORT_GPIO_NC 0x13
536 #define IOSF_PORT_CCK 0x14
537 #define IOSF_PORT_CCU 0xA9
538 #define IOSF_PORT_GPS_CORE 0x48
539 #define IOSF_PORT_FLISDSI 0x1B
540 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
541 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
543 /* See configdb bunit SB addr map */
544 #define BUNIT_REG_BISOC 0x11
546 #define PUNIT_REG_DSPFREQ 0x36
547 #define DSPFREQSTAT_SHIFT_CHV 24
548 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
549 #define DSPFREQGUAR_SHIFT_CHV 8
550 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
551 #define DSPFREQSTAT_SHIFT 30
552 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
553 #define DSPFREQGUAR_SHIFT 14
554 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
555 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
556 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
557 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
558 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
559 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
560 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
561 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
562 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
563 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
564 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
565 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
566 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
568 /* See the PUNIT HAS v0.8 for the below bits */
569 enum punit_power_well {
570 PUNIT_POWER_WELL_RENDER = 0,
571 PUNIT_POWER_WELL_MEDIA = 1,
572 PUNIT_POWER_WELL_DISP2D = 3,
573 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
574 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
575 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
576 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
577 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
578 PUNIT_POWER_WELL_DPIO_RX0 = 10,
579 PUNIT_POWER_WELL_DPIO_RX1 = 11,
580 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
581 /* FIXME: guesswork below */
582 PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13,
583 PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14,
584 PUNIT_POWER_WELL_DPIO_RX2 = 15,
586 PUNIT_POWER_WELL_NUM,
589 #define PUNIT_REG_PWRGT_CTRL 0x60
590 #define PUNIT_REG_PWRGT_STATUS 0x61
591 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
592 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
593 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
594 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
595 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
597 #define PUNIT_REG_GPU_LFM 0xd3
598 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
599 #define PUNIT_REG_GPU_FREQ_STS 0xd8
600 #define GPLLENABLE (1<<4)
601 #define GENFREQSTATUS (1<<0)
602 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
603 #define PUNIT_REG_CZ_TIMESTAMP 0xce
605 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
606 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
608 #define PUNIT_GPU_STATUS_REG 0xdb
609 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
610 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
611 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
612 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
614 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
615 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
616 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
618 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
619 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
620 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
621 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
622 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
623 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
624 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
625 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
626 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
627 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
629 #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
630 #define VLV_RP_UP_EI_THRESHOLD 90
631 #define VLV_RP_DOWN_EI_THRESHOLD 70
632 #define VLV_INT_COUNT_FOR_DOWN_EI 5
634 /* vlv2 north clock has */
635 #define CCK_FUSE_REG 0x8
636 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
637 #define CCK_REG_DSI_PLL_FUSE 0x44
638 #define CCK_REG_DSI_PLL_CONTROL 0x48
639 #define DSI_PLL_VCO_EN (1 << 31)
640 #define DSI_PLL_LDO_GATE (1 << 30)
641 #define DSI_PLL_P1_POST_DIV_SHIFT 17
642 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
643 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
644 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
645 #define DSI_PLL_MUX_MASK (3 << 9)
646 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
647 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
648 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
649 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
650 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
651 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
652 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
653 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
654 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
655 #define DSI_PLL_LOCK (1 << 0)
656 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
657 #define DSI_PLL_LFSR (1 << 31)
658 #define DSI_PLL_FRACTION_EN (1 << 30)
659 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
660 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
661 #define DSI_PLL_USYNC_CNT_SHIFT 18
662 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
663 #define DSI_PLL_N1_DIV_SHIFT 16
664 #define DSI_PLL_N1_DIV_MASK (3 << 16)
665 #define DSI_PLL_M1_DIV_SHIFT 0
666 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
667 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
668 #define DISPLAY_TRUNK_FORCE_ON (1 << 17)
669 #define DISPLAY_TRUNK_FORCE_OFF (1 << 16)
670 #define DISPLAY_FREQUENCY_STATUS (0x1f << 8)
671 #define DISPLAY_FREQUENCY_STATUS_SHIFT 8
672 #define DISPLAY_FREQUENCY_VALUES (0x1f << 0)
677 * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
678 * ports. DPIO is the name given to such a display PHY. These PHYs
679 * don't follow the standard programming model using direct MMIO
680 * registers, and instead their registers must be accessed trough IOSF
681 * sideband. VLV has one such PHY for driving ports B and C, and CHV
682 * adds another PHY for driving port D. Each PHY responds to specific
685 * Each display PHY is made up of one or two channels. Each channel
686 * houses a common lane part which contains the PLL and other common
687 * logic. CH0 common lane also contains the IOSF-SB logic for the
688 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
689 * must be running when any DPIO registers are accessed.
691 * In addition to having their own registers, the PHYs are also
692 * controlled through some dedicated signals from the display
693 * controller. These include PLL reference clock enable, PLL enable,
694 * and CRI clock selection, for example.
696 * Eeach channel also has two splines (also called data lanes), and
697 * each spline is made up of one Physical Access Coding Sub-Layer
698 * (PCS) block and two TX lanes. So each channel has two PCS blocks
699 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
700 * data/clock pairs depending on the output type.
702 * Additionally the PHY also contains an AUX lane with AUX blocks
703 * for each channel. This is used for DP AUX communication, but
704 * this fact isn't really relevant for the driver since AUX is
705 * controlled from the display controller side. No DPIO registers
706 * need to be accessed during AUX communication,
708 * Generally the common lane corresponds to the pipe and
709 * the spline (PCS/TX) corresponds to the port.
711 * For dual channel PHY (VLV/CHV):
713 * pipe A == CMN/PLL/REF CH0
715 * pipe B == CMN/PLL/REF CH1
717 * port B == PCS/TX CH0
719 * port C == PCS/TX CH1
721 * This is especially important when we cross the streams
722 * ie. drive port B with pipe B, or port C with pipe A.
724 * For single channel PHY (CHV):
726 * pipe C == CMN/PLL/REF CH0
728 * port D == PCS/TX CH0
730 * Note: digital port B is DDI0, digital port C is DDI1,
731 * digital port D is DDI2
734 * Dual channel PHY (VLV/CHV)
735 * ---------------------------------
737 * | CMN/PLL/REF | CMN/PLL/REF |
738 * |---------------|---------------| Display PHY
739 * | PCS01 | PCS23 | PCS01 | PCS23 |
740 * |-------|-------|-------|-------|
741 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
742 * ---------------------------------
743 * | DDI0 | DDI1 | DP/HDMI ports
744 * ---------------------------------
746 * Single channel PHY (CHV)
750 * |---------------| Display PHY
755 * | DDI2 | DP/HDMI port
760 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
761 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
762 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
763 #define DPIO_SFR_BYPASS (1<<1)
764 #define DPIO_CMNRST (1<<0)
766 #define DPIO_PHY(pipe) ((pipe) >> 1)
767 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
770 * Per pipe/PLL DPIO regs
772 #define _VLV_PLL_DW3_CH0 0x800c
773 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
774 #define DPIO_POST_DIV_DAC 0
775 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
776 #define DPIO_POST_DIV_LVDS1 2
777 #define DPIO_POST_DIV_LVDS2 3
778 #define DPIO_K_SHIFT (24) /* 4 bits */
779 #define DPIO_P1_SHIFT (21) /* 3 bits */
780 #define DPIO_P2_SHIFT (16) /* 5 bits */
781 #define DPIO_N_SHIFT (12) /* 4 bits */
782 #define DPIO_ENABLE_CALIBRATION (1<<11)
783 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
784 #define DPIO_M2DIV_MASK 0xff
785 #define _VLV_PLL_DW3_CH1 0x802c
786 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
788 #define _VLV_PLL_DW5_CH0 0x8014
789 #define DPIO_REFSEL_OVERRIDE 27
790 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
791 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
792 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
793 #define DPIO_PLL_REFCLK_SEL_MASK 3
794 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
795 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
796 #define _VLV_PLL_DW5_CH1 0x8034
797 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
799 #define _VLV_PLL_DW7_CH0 0x801c
800 #define _VLV_PLL_DW7_CH1 0x803c
801 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
803 #define _VLV_PLL_DW8_CH0 0x8040
804 #define _VLV_PLL_DW8_CH1 0x8060
805 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
807 #define VLV_PLL_DW9_BCAST 0xc044
808 #define _VLV_PLL_DW9_CH0 0x8044
809 #define _VLV_PLL_DW9_CH1 0x8064
810 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
812 #define _VLV_PLL_DW10_CH0 0x8048
813 #define _VLV_PLL_DW10_CH1 0x8068
814 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
816 #define _VLV_PLL_DW11_CH0 0x804c
817 #define _VLV_PLL_DW11_CH1 0x806c
818 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
820 /* Spec for ref block start counts at DW10 */
821 #define VLV_REF_DW13 0x80ac
823 #define VLV_CMN_DW0 0x8100
826 * Per DDI channel DPIO regs
829 #define _VLV_PCS_DW0_CH0 0x8200
830 #define _VLV_PCS_DW0_CH1 0x8400
831 #define DPIO_PCS_TX_LANE2_RESET (1<<16)
832 #define DPIO_PCS_TX_LANE1_RESET (1<<7)
833 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
834 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
835 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
837 #define _VLV_PCS01_DW0_CH0 0x200
838 #define _VLV_PCS23_DW0_CH0 0x400
839 #define _VLV_PCS01_DW0_CH1 0x2600
840 #define _VLV_PCS23_DW0_CH1 0x2800
841 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
842 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
844 #define _VLV_PCS_DW1_CH0 0x8204
845 #define _VLV_PCS_DW1_CH1 0x8404
846 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
847 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
848 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
849 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
850 #define DPIO_PCS_CLK_SOFT_RESET (1<<5)
851 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
853 #define _VLV_PCS01_DW1_CH0 0x204
854 #define _VLV_PCS23_DW1_CH0 0x404
855 #define _VLV_PCS01_DW1_CH1 0x2604
856 #define _VLV_PCS23_DW1_CH1 0x2804
857 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
858 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
860 #define _VLV_PCS_DW8_CH0 0x8220
861 #define _VLV_PCS_DW8_CH1 0x8420
862 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
863 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
864 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
866 #define _VLV_PCS01_DW8_CH0 0x0220
867 #define _VLV_PCS23_DW8_CH0 0x0420
868 #define _VLV_PCS01_DW8_CH1 0x2620
869 #define _VLV_PCS23_DW8_CH1 0x2820
870 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
871 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
873 #define _VLV_PCS_DW9_CH0 0x8224
874 #define _VLV_PCS_DW9_CH1 0x8424
875 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
876 #define DPIO_PCS_TX2MARGIN_000 (0<<13)
877 #define DPIO_PCS_TX2MARGIN_101 (1<<13)
878 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
879 #define DPIO_PCS_TX1MARGIN_000 (0<<10)
880 #define DPIO_PCS_TX1MARGIN_101 (1<<10)
881 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
883 #define _VLV_PCS01_DW9_CH0 0x224
884 #define _VLV_PCS23_DW9_CH0 0x424
885 #define _VLV_PCS01_DW9_CH1 0x2624
886 #define _VLV_PCS23_DW9_CH1 0x2824
887 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
888 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
890 #define _CHV_PCS_DW10_CH0 0x8228
891 #define _CHV_PCS_DW10_CH1 0x8428
892 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
893 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
894 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
895 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
896 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
897 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
898 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
899 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
900 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
902 #define _VLV_PCS01_DW10_CH0 0x0228
903 #define _VLV_PCS23_DW10_CH0 0x0428
904 #define _VLV_PCS01_DW10_CH1 0x2628
905 #define _VLV_PCS23_DW10_CH1 0x2828
906 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
907 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
909 #define _VLV_PCS_DW11_CH0 0x822c
910 #define _VLV_PCS_DW11_CH1 0x842c
911 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
912 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
913 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
914 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
916 #define _VLV_PCS01_DW11_CH0 0x022c
917 #define _VLV_PCS23_DW11_CH0 0x042c
918 #define _VLV_PCS01_DW11_CH1 0x262c
919 #define _VLV_PCS23_DW11_CH1 0x282c
920 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
921 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
923 #define _VLV_PCS_DW12_CH0 0x8230
924 #define _VLV_PCS_DW12_CH1 0x8430
925 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
927 #define _VLV_PCS_DW14_CH0 0x8238
928 #define _VLV_PCS_DW14_CH1 0x8438
929 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
931 #define _VLV_PCS_DW23_CH0 0x825c
932 #define _VLV_PCS_DW23_CH1 0x845c
933 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
935 #define _VLV_TX_DW2_CH0 0x8288
936 #define _VLV_TX_DW2_CH1 0x8488
937 #define DPIO_SWING_MARGIN000_SHIFT 16
938 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
939 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
940 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
942 #define _VLV_TX_DW3_CH0 0x828c
943 #define _VLV_TX_DW3_CH1 0x848c
944 /* The following bit for CHV phy */
945 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
946 #define DPIO_SWING_MARGIN101_SHIFT 16
947 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
948 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
950 #define _VLV_TX_DW4_CH0 0x8290
951 #define _VLV_TX_DW4_CH1 0x8490
952 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
953 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
954 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
955 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
956 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
958 #define _VLV_TX3_DW4_CH0 0x690
959 #define _VLV_TX3_DW4_CH1 0x2a90
960 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
962 #define _VLV_TX_DW5_CH0 0x8294
963 #define _VLV_TX_DW5_CH1 0x8494
964 #define DPIO_TX_OCALINIT_EN (1<<31)
965 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
967 #define _VLV_TX_DW11_CH0 0x82ac
968 #define _VLV_TX_DW11_CH1 0x84ac
969 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
971 #define _VLV_TX_DW14_CH0 0x82b8
972 #define _VLV_TX_DW14_CH1 0x84b8
973 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
975 /* CHV dpPhy registers */
976 #define _CHV_PLL_DW0_CH0 0x8000
977 #define _CHV_PLL_DW0_CH1 0x8180
978 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
980 #define _CHV_PLL_DW1_CH0 0x8004
981 #define _CHV_PLL_DW1_CH1 0x8184
982 #define DPIO_CHV_N_DIV_SHIFT 8
983 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
984 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
986 #define _CHV_PLL_DW2_CH0 0x8008
987 #define _CHV_PLL_DW2_CH1 0x8188
988 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
990 #define _CHV_PLL_DW3_CH0 0x800c
991 #define _CHV_PLL_DW3_CH1 0x818c
992 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
993 #define DPIO_CHV_FIRST_MOD (0 << 8)
994 #define DPIO_CHV_SECOND_MOD (1 << 8)
995 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
996 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
998 #define _CHV_PLL_DW6_CH0 0x8018
999 #define _CHV_PLL_DW6_CH1 0x8198
1000 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
1001 #define DPIO_CHV_INT_COEFF_SHIFT 8
1002 #define DPIO_CHV_PROP_COEFF_SHIFT 0
1003 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1005 #define _CHV_CMN_DW5_CH0 0x8114
1006 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1007 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1008 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1009 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
1010 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1011 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1012 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
1013 #define CHV_BUFLEFTENA1_MASK (3 << 22)
1015 #define _CHV_CMN_DW13_CH0 0x8134
1016 #define _CHV_CMN_DW0_CH1 0x8080
1017 #define DPIO_CHV_S1_DIV_SHIFT 21
1018 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1019 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1020 #define DPIO_CHV_K_DIV_SHIFT 4
1021 #define DPIO_PLL_FREQLOCK (1 << 1)
1022 #define DPIO_PLL_LOCK (1 << 0)
1023 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1025 #define _CHV_CMN_DW14_CH0 0x8138
1026 #define _CHV_CMN_DW1_CH1 0x8084
1027 #define DPIO_AFC_RECAL (1 << 14)
1028 #define DPIO_DCLKP_EN (1 << 13)
1029 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1030 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1031 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1032 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1033 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1034 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1035 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1036 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1037 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1039 #define _CHV_CMN_DW19_CH0 0x814c
1040 #define _CHV_CMN_DW6_CH1 0x8098
1041 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1042 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1044 #define CHV_CMN_DW30 0x8178
1045 #define DPIO_LRC_BYPASS (1 << 3)
1047 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1048 (lane) * 0x200 + (offset))
1050 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1051 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1052 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1053 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1054 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1055 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1056 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1057 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1058 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1059 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1060 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1061 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1062 #define DPIO_FRC_LATENCY_SHFIT 8
1063 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1064 #define DPIO_UPAR_SHIFT 30
1068 #define FENCE_REG_830_0 0x2000
1069 #define FENCE_REG_945_8 0x3000
1070 #define I830_FENCE_START_MASK 0x07f80000
1071 #define I830_FENCE_TILING_Y_SHIFT 12
1072 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
1073 #define I830_FENCE_PITCH_SHIFT 4
1074 #define I830_FENCE_REG_VALID (1<<0)
1075 #define I915_FENCE_MAX_PITCH_VAL 4
1076 #define I830_FENCE_MAX_PITCH_VAL 6
1077 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
1079 #define I915_FENCE_START_MASK 0x0ff00000
1080 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
1082 #define FENCE_REG_965_0 0x03000
1083 #define I965_FENCE_PITCH_SHIFT 2
1084 #define I965_FENCE_TILING_Y_SHIFT 1
1085 #define I965_FENCE_REG_VALID (1<<0)
1086 #define I965_FENCE_MAX_PITCH_VAL 0x0400
1088 #define FENCE_REG_SANDYBRIDGE_0 0x100000
1089 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
1090 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
1093 /* control register for cpu gtt access */
1094 #define TILECTL 0x101000
1095 #define TILECTL_SWZCTL (1 << 0)
1096 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
1097 #define TILECTL_BACKSNOOP_DIS (1 << 3)
1100 * Instruction and interrupt control regs
1102 #define PGTBL_CTL 0x02020
1103 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1104 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
1105 #define PGTBL_ER 0x02024
1106 #define PRB0_BASE (0x2030-0x30)
1107 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1108 #define PRB2_BASE (0x2050-0x30) /* gen3 */
1109 #define SRB0_BASE (0x2100-0x30) /* gen2 */
1110 #define SRB1_BASE (0x2110-0x30) /* gen2 */
1111 #define SRB2_BASE (0x2120-0x30) /* 830 */
1112 #define SRB3_BASE (0x2130-0x30) /* 830 */
1113 #define RENDER_RING_BASE 0x02000
1114 #define BSD_RING_BASE 0x04000
1115 #define GEN6_BSD_RING_BASE 0x12000
1116 #define GEN8_BSD2_RING_BASE 0x1c000
1117 #define VEBOX_RING_BASE 0x1a000
1118 #define BLT_RING_BASE 0x22000
1119 #define RING_TAIL(base) ((base)+0x30)
1120 #define RING_HEAD(base) ((base)+0x34)
1121 #define RING_START(base) ((base)+0x38)
1122 #define RING_CTL(base) ((base)+0x3c)
1123 #define RING_SYNC_0(base) ((base)+0x40)
1124 #define RING_SYNC_1(base) ((base)+0x44)
1125 #define RING_SYNC_2(base) ((base)+0x48)
1126 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
1127 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
1128 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
1129 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
1130 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
1131 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
1132 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
1133 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
1134 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
1135 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1136 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1137 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
1138 #define GEN6_NOSYNC 0
1139 #define RING_PSMI_CTL(base) ((base)+0x50)
1140 #define RING_MAX_IDLE(base) ((base)+0x54)
1141 #define RING_HWS_PGA(base) ((base)+0x80)
1142 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
1144 #define GEN7_WR_WATERMARK 0x4028
1145 #define GEN7_GFX_PRIO_CTRL 0x402C
1146 #define ARB_MODE 0x4030
1147 #define ARB_MODE_SWIZZLE_SNB (1<<4)
1148 #define ARB_MODE_SWIZZLE_IVB (1<<5)
1149 #define GEN7_GFX_PEND_TLB0 0x4034
1150 #define GEN7_GFX_PEND_TLB1 0x4038
1151 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1152 #define GEN7_LRA_LIMITS_BASE 0x403C
1153 #define GEN7_LRA_LIMITS_REG_NUM 13
1154 #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070
1155 #define GEN7_GFX_MAX_REQ_COUNT 0x4074
1157 #define GAMTARBMODE 0x04a08
1158 #define ARB_MODE_BWGTLB_DISABLE (1<<9)
1159 #define ARB_MODE_SWIZZLE_BDW (1<<1)
1160 #define RENDER_HWS_PGA_GEN7 (0x04080)
1161 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
1162 #define RING_FAULT_GTTSEL_MASK (1<<11)
1163 #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
1164 #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
1165 #define RING_FAULT_VALID (1<<0)
1166 #define DONE_REG 0x40b0
1167 #define GEN8_PRIVATE_PAT 0x40e0
1168 #define BSD_HWS_PGA_GEN7 (0x04180)
1169 #define BLT_HWS_PGA_GEN7 (0x04280)
1170 #define VEBOX_HWS_PGA_GEN7 (0x04380)
1171 #define RING_ACTHD(base) ((base)+0x74)
1172 #define RING_ACTHD_UDW(base) ((base)+0x5c)
1173 #define RING_NOPID(base) ((base)+0x94)
1174 #define RING_IMR(base) ((base)+0xa8)
1175 #define RING_HWSTAM(base) ((base)+0x98)
1176 #define RING_TIMESTAMP(base) ((base)+0x358)
1177 #define TAIL_ADDR 0x001FFFF8
1178 #define HEAD_WRAP_COUNT 0xFFE00000
1179 #define HEAD_WRAP_ONE 0x00200000
1180 #define HEAD_ADDR 0x001FFFFC
1181 #define RING_NR_PAGES 0x001FF000
1182 #define RING_REPORT_MASK 0x00000006
1183 #define RING_REPORT_64K 0x00000002
1184 #define RING_REPORT_128K 0x00000004
1185 #define RING_NO_REPORT 0x00000000
1186 #define RING_VALID_MASK 0x00000001
1187 #define RING_VALID 0x00000001
1188 #define RING_INVALID 0x00000000
1189 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
1190 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
1191 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
1193 #define GEN7_TLB_RD_ADDR 0x4700
1196 #define PRB0_TAIL 0x02030
1197 #define PRB0_HEAD 0x02034
1198 #define PRB0_START 0x02038
1199 #define PRB0_CTL 0x0203c
1200 #define PRB1_TAIL 0x02040 /* 915+ only */
1201 #define PRB1_HEAD 0x02044 /* 915+ only */
1202 #define PRB1_START 0x02048 /* 915+ only */
1203 #define PRB1_CTL 0x0204c /* 915+ only */
1205 #define IPEIR_I965 0x02064
1206 #define IPEHR_I965 0x02068
1207 #define INSTDONE_I965 0x0206c
1208 #define GEN7_INSTDONE_1 0x0206c
1209 #define GEN7_SC_INSTDONE 0x07100
1210 #define GEN7_SAMPLER_INSTDONE 0x0e160
1211 #define GEN7_ROW_INSTDONE 0x0e164
1212 #define I915_NUM_INSTDONE_REG 4
1213 #define RING_IPEIR(base) ((base)+0x64)
1214 #define RING_IPEHR(base) ((base)+0x68)
1215 #define RING_INSTDONE(base) ((base)+0x6c)
1216 #define RING_INSTPS(base) ((base)+0x70)
1217 #define RING_DMA_FADD(base) ((base)+0x78)
1218 #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */
1219 #define RING_INSTPM(base) ((base)+0xc0)
1220 #define RING_MI_MODE(base) ((base)+0x9c)
1221 #define INSTPS 0x02070 /* 965+ only */
1222 #define INSTDONE1 0x0207c /* 965+ only */
1223 #define ACTHD_I965 0x02074
1224 #define HWS_PGA 0x02080
1225 #define HWS_ADDRESS_MASK 0xfffff000
1226 #define HWS_START_ADDRESS_SHIFT 4
1227 #define PWRCTXA 0x2088 /* 965GM+ only */
1228 #define PWRCTX_EN (1<<0)
1229 #define IPEIR 0x02088
1230 #define IPEHR 0x0208c
1231 #define INSTDONE 0x02090
1232 #define NOPID 0x02094
1233 #define HWSTAM 0x02098
1234 #define DMA_FADD_I8XX 0x020d0
1235 #define RING_BBSTATE(base) ((base)+0x110)
1236 #define RING_BBADDR(base) ((base)+0x140)
1237 #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
1239 #define ERROR_GEN6 0x040a0
1240 #define GEN7_ERR_INT 0x44040
1241 #define ERR_INT_POISON (1<<31)
1242 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
1243 #define ERR_INT_PIPE_CRC_DONE_C (1<<8)
1244 #define ERR_INT_FIFO_UNDERRUN_C (1<<6)
1245 #define ERR_INT_PIPE_CRC_DONE_B (1<<5)
1246 #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
1247 #define ERR_INT_PIPE_CRC_DONE_A (1<<2)
1248 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
1249 #define ERR_INT_FIFO_UNDERRUN_A (1<<0)
1250 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
1252 #define FPGA_DBG 0x42300
1253 #define FPGA_DBG_RM_NOCLAIM (1<<31)
1255 #define DERRMR 0x44050
1256 /* Note that HBLANK events are reserved on bdw+ */
1257 #define DERRMR_PIPEA_SCANLINE (1<<0)
1258 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
1259 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
1260 #define DERRMR_PIPEA_VBLANK (1<<3)
1261 #define DERRMR_PIPEA_HBLANK (1<<5)
1262 #define DERRMR_PIPEB_SCANLINE (1<<8)
1263 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
1264 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
1265 #define DERRMR_PIPEB_VBLANK (1<<11)
1266 #define DERRMR_PIPEB_HBLANK (1<<13)
1267 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1268 #define DERRMR_PIPEC_SCANLINE (1<<14)
1269 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
1270 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
1271 #define DERRMR_PIPEC_VBLANK (1<<21)
1272 #define DERRMR_PIPEC_HBLANK (1<<22)
1275 /* GM45+ chicken bits -- debug workaround bits that may be required
1276 * for various sorts of correct behavior. The top 16 bits of each are
1277 * the enables for writing to the corresponding low bit.
1279 #define _3D_CHICKEN 0x02084
1280 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
1281 #define _3D_CHICKEN2 0x0208c
1282 /* Disables pipelining of read flushes past the SF-WIZ interface.
1283 * Required on all Ironlake steppings according to the B-Spec, but the
1284 * particular danger of not doing so is not specified.
1286 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
1287 #define _3D_CHICKEN3 0x02090
1288 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
1289 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
1290 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1291 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
1293 #define MI_MODE 0x0209c
1294 # define VS_TIMER_DISPATCH (1 << 6)
1295 # define MI_FLUSH_ENABLE (1 << 12)
1296 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
1297 # define MODE_IDLE (1 << 9)
1298 # define STOP_RING (1 << 8)
1300 #define GEN6_GT_MODE 0x20d0
1301 #define GEN7_GT_MODE 0x7008
1302 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
1303 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1304 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
1305 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
1306 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
1307 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
1309 #define GFX_MODE 0x02520
1310 #define GFX_MODE_GEN7 0x0229c
1311 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
1312 #define GFX_RUN_LIST_ENABLE (1<<15)
1313 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
1314 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
1315 #define GFX_REPLAY_MODE (1<<11)
1316 #define GFX_PSMI_GRANULARITY (1<<10)
1317 #define GFX_PPGTT_ENABLE (1<<9)
1319 #define VLV_DISPLAY_BASE 0x180000
1320 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
1322 #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
1323 #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
1324 #define SCPD0 0x0209c /* 915+ only */
1329 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
1330 #define GINT_DIS (1<<22)
1331 #define GCFG_DIS (1<<8)
1332 #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064)
1333 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
1334 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
1335 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
1336 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
1337 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
1338 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
1339 #define VLV_PCBR_ADDR_SHIFT 12
1341 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
1345 #define GM45_ERROR_PAGE_TABLE (1<<5)
1346 #define GM45_ERROR_MEM_PRIV (1<<4)
1347 #define I915_ERROR_PAGE_TABLE (1<<4)
1348 #define GM45_ERROR_CP_PRIV (1<<3)
1349 #define I915_ERROR_MEMORY_REFRESH (1<<1)
1350 #define I915_ERROR_INSTRUCTION (1<<0)
1351 #define INSTPM 0x020c0
1352 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
1353 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
1354 will not assert AGPBUSY# and will only
1355 be delivered when out of C3. */
1356 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
1357 #define INSTPM_TLB_INVALIDATE (1<<9)
1358 #define INSTPM_SYNC_FLUSH (1<<5)
1359 #define ACTHD 0x020c8
1360 #define MEM_MODE 0x020cc
1361 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1362 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1363 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
1364 #define FW_BLC 0x020d8
1365 #define FW_BLC2 0x020dc
1366 #define FW_BLC_SELF 0x020e0 /* 915+ only */
1367 #define FW_BLC_SELF_EN_MASK (1<<31)
1368 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1369 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
1370 #define MM_BURST_LENGTH 0x00700000
1371 #define MM_FIFO_WATERMARK 0x0001F000
1372 #define LM_BURST_LENGTH 0x00000700
1373 #define LM_FIFO_WATERMARK 0x0000001F
1374 #define MI_ARB_STATE 0x020e4 /* 915+ only */
1376 /* Make render/texture TLB fetches lower priorty than associated data
1377 * fetches. This is not turned on by default
1379 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1381 /* Isoch request wait on GTT enable (Display A/B/C streams).
1382 * Make isoch requests stall on the TLB update. May cause
1383 * display underruns (test mode only)
1385 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1387 /* Block grant count for isoch requests when block count is
1388 * set to a finite value.
1390 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1391 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1392 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1393 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1394 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1396 /* Enable render writes to complete in C2/C3/C4 power states.
1397 * If this isn't enabled, render writes are prevented in low
1398 * power states. That seems bad to me.
1400 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1402 /* This acknowledges an async flip immediately instead
1403 * of waiting for 2TLB fetches.
1405 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1407 /* Enables non-sequential data reads through arbiter
1409 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
1411 /* Disable FSB snooping of cacheable write cycles from binner/render
1414 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1416 /* Arbiter time slice for non-isoch streams */
1417 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
1418 #define MI_ARB_TIME_SLICE_1 (0 << 5)
1419 #define MI_ARB_TIME_SLICE_2 (1 << 5)
1420 #define MI_ARB_TIME_SLICE_4 (2 << 5)
1421 #define MI_ARB_TIME_SLICE_6 (3 << 5)
1422 #define MI_ARB_TIME_SLICE_8 (4 << 5)
1423 #define MI_ARB_TIME_SLICE_10 (5 << 5)
1424 #define MI_ARB_TIME_SLICE_14 (6 << 5)
1425 #define MI_ARB_TIME_SLICE_16 (7 << 5)
1427 /* Low priority grace period page size */
1428 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1429 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1431 /* Disable display A/B trickle feed */
1432 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1434 /* Set display plane priority */
1435 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1436 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1438 #define MI_STATE 0x020e4 /* gen2 only */
1439 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1440 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1442 #define CACHE_MODE_0 0x02120 /* 915+ only */
1443 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
1444 #define CM0_IZ_OPT_DISABLE (1<<6)
1445 #define CM0_ZR_OPT_DISABLE (1<<5)
1446 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
1447 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
1448 #define CM0_COLOR_EVICT_DISABLE (1<<3)
1449 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
1450 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1451 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
1452 #define GFX_FLSH_CNTL_GEN6 0x101008
1453 #define GFX_FLSH_CNTL_EN (1<<0)
1454 #define ECOSKPD 0x021d0
1455 #define ECO_GATING_CX_ONLY (1<<3)
1456 #define ECO_FLIP_DONE (1<<0)
1458 #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
1459 #define RC_OP_FLUSH_ENABLE (1<<0)
1460 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
1461 #define CACHE_MODE_1 0x7004 /* IVB+ */
1462 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1463 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
1465 #define GEN6_BLITTER_ECOSKPD 0x221d0
1466 #define GEN6_BLITTER_LOCK_SHIFT 16
1467 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
1469 #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
1470 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
1471 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
1472 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
1474 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
1475 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
1476 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
1477 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
1478 #define GEN6_BSD_GO_INDICATOR (1 << 4)
1480 /* On modern GEN architectures interrupt control consists of two sets
1481 * of registers. The first set pertains to the ring generating the
1482 * interrupt. The second control is for the functional block generating the
1483 * interrupt. These are PM, GT, DE, etc.
1485 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1486 * GT interrupt bits, so we don't need to duplicate the defines.
1488 * These defines should cover us well from SNB->HSW with minor exceptions
1489 * it can also work on ILK.
1491 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1492 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1493 #define GT_BLT_USER_INTERRUPT (1 << 22)
1494 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1495 #define GT_BSD_USER_INTERRUPT (1 << 12)
1496 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1497 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
1498 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1499 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1500 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
1501 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1502 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1503 #define GT_RENDER_USER_INTERRUPT (1 << 0)
1505 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1506 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1508 #define GT_PARITY_ERROR(dev) \
1509 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
1510 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1512 /* These are all the "old" interrupts */
1513 #define ILK_BSD_USER_INTERRUPT (1<<5)
1515 #define I915_PM_INTERRUPT (1<<31)
1516 #define I915_ISP_INTERRUPT (1<<22)
1517 #define I915_LPE_PIPE_B_INTERRUPT (1<<21)
1518 #define I915_LPE_PIPE_A_INTERRUPT (1<<20)
1519 #define I915_MIPIC_INTERRUPT (1<<19)
1520 #define I915_MIPIA_INTERRUPT (1<<18)
1521 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1522 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
1523 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
1524 #define I915_MASTER_ERROR_INTERRUPT (1<<15)
1525 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
1526 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
1527 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
1528 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
1529 #define I915_HWB_OOM_INTERRUPT (1<<13)
1530 #define I915_LPE_PIPE_C_INTERRUPT (1<<12)
1531 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
1532 #define I915_MISC_INTERRUPT (1<<11)
1533 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
1534 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
1535 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
1536 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
1537 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
1538 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
1539 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1540 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1541 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1542 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1543 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
1544 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
1545 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
1546 #define I915_DEBUG_INTERRUPT (1<<2)
1547 #define I915_WINVALID_INTERRUPT (1<<1)
1548 #define I915_USER_INTERRUPT (1<<1)
1549 #define I915_ASLE_INTERRUPT (1<<0)
1550 #define I915_BSD_USER_INTERRUPT (1<<25)
1552 #define GEN6_BSD_RNCID 0x12198
1554 #define GEN7_FF_THREAD_MODE 0x20a0
1555 #define GEN7_FF_SCHED_MASK 0x0077070
1556 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
1557 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1558 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1559 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1560 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
1561 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
1562 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1563 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1564 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
1565 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
1566 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1567 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1568 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
1569 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
1572 * Framebuffer compression (915+ only)
1575 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1576 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
1577 #define FBC_CONTROL 0x03208
1578 #define FBC_CTL_EN (1<<31)
1579 #define FBC_CTL_PERIODIC (1<<30)
1580 #define FBC_CTL_INTERVAL_SHIFT (16)
1581 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
1582 #define FBC_CTL_C3_IDLE (1<<13)
1583 #define FBC_CTL_STRIDE_SHIFT (5)
1584 #define FBC_CTL_FENCENO_SHIFT (0)
1585 #define FBC_COMMAND 0x0320c
1586 #define FBC_CMD_COMPRESS (1<<0)
1587 #define FBC_STATUS 0x03210
1588 #define FBC_STAT_COMPRESSING (1<<31)
1589 #define FBC_STAT_COMPRESSED (1<<30)
1590 #define FBC_STAT_MODIFIED (1<<29)
1591 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
1592 #define FBC_CONTROL2 0x03214
1593 #define FBC_CTL_FENCE_DBL (0<<4)
1594 #define FBC_CTL_IDLE_IMM (0<<2)
1595 #define FBC_CTL_IDLE_FULL (1<<2)
1596 #define FBC_CTL_IDLE_LINE (2<<2)
1597 #define FBC_CTL_IDLE_DEBUG (3<<2)
1598 #define FBC_CTL_CPU_FENCE (1<<1)
1599 #define FBC_CTL_PLANE(plane) ((plane)<<0)
1600 #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */
1601 #define FBC_TAG 0x03300
1603 #define FBC_LL_SIZE (1536)
1605 /* Framebuffer compression for GM45+ */
1606 #define DPFC_CB_BASE 0x3200
1607 #define DPFC_CONTROL 0x3208
1608 #define DPFC_CTL_EN (1<<31)
1609 #define DPFC_CTL_PLANE(plane) ((plane)<<30)
1610 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
1611 #define DPFC_CTL_FENCE_EN (1<<29)
1612 #define IVB_DPFC_CTL_FENCE_EN (1<<28)
1613 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
1614 #define DPFC_SR_EN (1<<10)
1615 #define DPFC_CTL_LIMIT_1X (0<<6)
1616 #define DPFC_CTL_LIMIT_2X (1<<6)
1617 #define DPFC_CTL_LIMIT_4X (2<<6)
1618 #define DPFC_RECOMP_CTL 0x320c
1619 #define DPFC_RECOMP_STALL_EN (1<<27)
1620 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
1621 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
1622 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
1623 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
1624 #define DPFC_STATUS 0x3210
1625 #define DPFC_INVAL_SEG_SHIFT (16)
1626 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
1627 #define DPFC_COMP_SEG_SHIFT (0)
1628 #define DPFC_COMP_SEG_MASK (0x000003ff)
1629 #define DPFC_STATUS2 0x3214
1630 #define DPFC_FENCE_YOFF 0x3218
1631 #define DPFC_CHICKEN 0x3224
1632 #define DPFC_HT_MODIFY (1<<31)
1634 /* Framebuffer compression for Ironlake */
1635 #define ILK_DPFC_CB_BASE 0x43200
1636 #define ILK_DPFC_CONTROL 0x43208
1637 #define FBC_CTL_FALSE_COLOR (1<<10)
1638 /* The bit 28-8 is reserved */
1639 #define DPFC_RESERVED (0x1FFFFF00)
1640 #define ILK_DPFC_RECOMP_CTL 0x4320c
1641 #define ILK_DPFC_STATUS 0x43210
1642 #define ILK_DPFC_FENCE_YOFF 0x43218
1643 #define ILK_DPFC_CHICKEN 0x43224
1644 #define ILK_FBC_RT_BASE 0x2128
1645 #define ILK_FBC_RT_VALID (1<<0)
1646 #define SNB_FBC_FRONT_BUFFER (1<<1)
1648 #define ILK_DISPLAY_CHICKEN1 0x42000
1649 #define ILK_FBCQ_DIS (1<<22)
1650 #define ILK_PABSTRETCH_DIS (1<<21)
1654 * Framebuffer compression for Sandybridge
1656 * The following two registers are of type GTTMMADR
1658 #define SNB_DPFC_CTL_SA 0x100100
1659 #define SNB_CPU_FENCE_ENABLE (1<<29)
1660 #define DPFC_CPU_FENCE_OFFSET 0x100104
1662 /* Framebuffer compression for Ivybridge */
1663 #define IVB_FBC_RT_BASE 0x7020
1665 #define IPS_CTL 0x43408
1666 #define IPS_ENABLE (1 << 31)
1668 #define MSG_FBC_REND_STATE 0x50380
1669 #define FBC_REND_NUKE (1<<2)
1670 #define FBC_REND_CACHE_CLEAN (1<<1)
1675 #define GPIOA 0x5010
1676 #define GPIOB 0x5014
1677 #define GPIOC 0x5018
1678 #define GPIOD 0x501c
1679 #define GPIOE 0x5020
1680 #define GPIOF 0x5024
1681 #define GPIOG 0x5028
1682 #define GPIOH 0x502c
1683 # define GPIO_CLOCK_DIR_MASK (1 << 0)
1684 # define GPIO_CLOCK_DIR_IN (0 << 1)
1685 # define GPIO_CLOCK_DIR_OUT (1 << 1)
1686 # define GPIO_CLOCK_VAL_MASK (1 << 2)
1687 # define GPIO_CLOCK_VAL_OUT (1 << 3)
1688 # define GPIO_CLOCK_VAL_IN (1 << 4)
1689 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1690 # define GPIO_DATA_DIR_MASK (1 << 8)
1691 # define GPIO_DATA_DIR_IN (0 << 9)
1692 # define GPIO_DATA_DIR_OUT (1 << 9)
1693 # define GPIO_DATA_VAL_MASK (1 << 10)
1694 # define GPIO_DATA_VAL_OUT (1 << 11)
1695 # define GPIO_DATA_VAL_IN (1 << 12)
1696 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1698 #define GMBUS0 0x5100 /* clock/port select */
1699 #define GMBUS_RATE_100KHZ (0<<8)
1700 #define GMBUS_RATE_50KHZ (1<<8)
1701 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
1702 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
1703 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
1704 #define GMBUS_PORT_DISABLED 0
1705 #define GMBUS_PORT_SSC 1
1706 #define GMBUS_PORT_VGADDC 2
1707 #define GMBUS_PORT_PANEL 3
1708 #define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */
1709 #define GMBUS_PORT_DPC 4 /* HDMIC */
1710 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
1711 #define GMBUS_PORT_DPD 6 /* HDMID */
1712 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */
1713 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
1714 #define GMBUS1 0x5104 /* command/status */
1715 #define GMBUS_SW_CLR_INT (1<<31)
1716 #define GMBUS_SW_RDY (1<<30)
1717 #define GMBUS_ENT (1<<29) /* enable timeout */
1718 #define GMBUS_CYCLE_NONE (0<<25)
1719 #define GMBUS_CYCLE_WAIT (1<<25)
1720 #define GMBUS_CYCLE_INDEX (2<<25)
1721 #define GMBUS_CYCLE_STOP (4<<25)
1722 #define GMBUS_BYTE_COUNT_SHIFT 16
1723 #define GMBUS_SLAVE_INDEX_SHIFT 8
1724 #define GMBUS_SLAVE_ADDR_SHIFT 1
1725 #define GMBUS_SLAVE_READ (1<<0)
1726 #define GMBUS_SLAVE_WRITE (0<<0)
1727 #define GMBUS2 0x5108 /* status */
1728 #define GMBUS_INUSE (1<<15)
1729 #define GMBUS_HW_WAIT_PHASE (1<<14)
1730 #define GMBUS_STALL_TIMEOUT (1<<13)
1731 #define GMBUS_INT (1<<12)
1732 #define GMBUS_HW_RDY (1<<11)
1733 #define GMBUS_SATOER (1<<10)
1734 #define GMBUS_ACTIVE (1<<9)
1735 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
1736 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
1737 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1738 #define GMBUS_NAK_EN (1<<3)
1739 #define GMBUS_IDLE_EN (1<<2)
1740 #define GMBUS_HW_WAIT_EN (1<<1)
1741 #define GMBUS_HW_RDY_EN (1<<0)
1742 #define GMBUS5 0x5120 /* byte index */
1743 #define GMBUS_2BYTE_INDEX_EN (1<<31)
1746 * Clock control & power management
1748 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
1749 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
1750 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
1751 #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
1755 #define VGA_PD 0x6010
1756 #define VGA0_PD_P2_DIV_4 (1 << 7)
1757 #define VGA0_PD_P1_DIV_2 (1 << 5)
1758 #define VGA0_PD_P1_SHIFT 0
1759 #define VGA0_PD_P1_MASK (0x1f << 0)
1760 #define VGA1_PD_P2_DIV_4 (1 << 15)
1761 #define VGA1_PD_P1_DIV_2 (1 << 13)
1762 #define VGA1_PD_P1_SHIFT 8
1763 #define VGA1_PD_P1_MASK (0x1f << 8)
1764 #define DPLL_VCO_ENABLE (1 << 31)
1765 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
1766 #define DPLL_DVO_2X_MODE (1 << 30)
1767 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
1768 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
1769 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
1770 #define DPLL_VGA_MODE_DIS (1 << 28)
1771 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1772 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1773 #define DPLL_MODE_MASK (3 << 26)
1774 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1775 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1776 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1777 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1778 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1779 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1780 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
1781 #define DPLL_LOCK_VLV (1<<15)
1782 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
1783 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
1784 #define DPLL_SSC_REF_CLOCK_CHV (1<<13)
1785 #define DPLL_PORTC_READY_MASK (0xf << 4)
1786 #define DPLL_PORTB_READY_MASK (0xf)
1788 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1790 /* Additional CHV pll/phy registers */
1791 #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)
1792 #define DPLL_PORTD_READY_MASK (0xf)
1793 #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
1794 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
1795 #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
1796 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
1799 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1800 * this field (only one bit may be set).
1802 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1803 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1804 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1805 /* i830, required in DVO non-gang */
1806 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
1807 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1808 #define PLL_REF_INPUT_DREFCLK (0 << 13)
1809 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1810 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1811 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1812 #define PLL_REF_INPUT_MASK (3 << 13)
1813 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
1815 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1816 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1817 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
1818 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1819 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1822 * Parallel to Serial Load Pulse phase selection.
1823 * Selects the phase for the 10X DPLL clock for the PCIe
1824 * digital display port. The range is 4 to 13; 10 or more
1825 * is just a flip delay. The default is 6
1827 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1828 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1830 * SDVO multiplier for 945G/GM. Not used on 965.
1832 #define SDVO_MULTIPLIER_MASK 0x000000ff
1833 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
1834 #define SDVO_MULTIPLIER_SHIFT_VGA 0
1836 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
1837 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
1838 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
1839 #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
1842 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1844 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1846 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1847 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
1848 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1849 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1850 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1852 * SDVO/UDI pixel multiplier.
1854 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1855 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1856 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1857 * dummy bytes in the datastream at an increased clock rate, with both sides of
1858 * the link knowing how many bytes are fill.
1860 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1861 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1862 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1863 * through an SDVO command.
1865 * This register field has values of multiplication factor minus 1, with
1866 * a maximum multiplier of 5 for SDVO.
1868 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1869 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1871 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1872 * This best be set to the default value (3) or the CRT won't work. No,
1873 * I don't entirely understand what this does...
1875 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1876 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1878 #define _FPA0 0x06040
1879 #define _FPA1 0x06044
1880 #define _FPB0 0x06048
1881 #define _FPB1 0x0604c
1882 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1883 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1884 #define FP_N_DIV_MASK 0x003f0000
1885 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1886 #define FP_N_DIV_SHIFT 16
1887 #define FP_M1_DIV_MASK 0x00003f00
1888 #define FP_M1_DIV_SHIFT 8
1889 #define FP_M2_DIV_MASK 0x0000003f
1890 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1891 #define FP_M2_DIV_SHIFT 0
1892 #define DPLL_TEST 0x606c
1893 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1894 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1895 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1896 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1897 #define DPLLB_TEST_N_BYPASS (1 << 19)
1898 #define DPLLB_TEST_M_BYPASS (1 << 18)
1899 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1900 #define DPLLA_TEST_N_BYPASS (1 << 3)
1901 #define DPLLA_TEST_M_BYPASS (1 << 2)
1902 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1903 #define D_STATE 0x6104
1904 #define DSTATE_GFX_RESET_I830 (1<<6)
1905 #define DSTATE_PLL_D3_OFF (1<<3)
1906 #define DSTATE_GFX_CLOCK_GATING (1<<1)
1907 #define DSTATE_DOT_CLOCK_GATING (1<<0)
1908 #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
1909 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1910 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1911 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1912 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1913 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1914 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1915 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1916 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1917 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1918 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1919 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1920 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1921 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1922 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1923 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1924 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1925 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1926 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1927 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1928 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1929 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1930 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1931 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1932 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1933 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1934 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1935 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1936 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1938 * This bit must be set on the 830 to prevent hangs when turning off the
1941 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1942 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1943 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1944 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1945 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1947 #define RENCLK_GATE_D1 0x6204
1948 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1949 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1950 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1951 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1952 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1953 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1954 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1955 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1956 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
1957 /* This bit must be unset on 855,865 */
1958 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
1959 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1960 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
1961 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
1962 /* This bit must be set on 855,865. */
1963 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1964 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1965 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1966 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1967 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1968 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1969 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1970 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1971 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1972 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1973 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1974 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1975 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1976 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1977 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1978 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1979 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1980 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1982 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1983 /* This bit must always be set on 965G/965GM */
1984 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1985 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1986 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1987 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1988 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1989 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1990 /* This bit must always be set on 965G */
1991 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1992 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1993 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1994 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1995 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1996 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1997 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1998 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1999 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
2000 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
2001 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
2002 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
2003 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
2004 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
2005 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
2006 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
2007 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
2008 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
2009 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
2011 #define RENCLK_GATE_D2 0x6208
2012 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
2013 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
2014 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
2016 #define VDECCLK_GATE_D 0x620C /* g4x only */
2017 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
2019 #define RAMCLK_GATE_D 0x6210 /* CRL only */
2020 #define DEUC 0x6214 /* CRL only */
2022 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
2023 #define FW_CSPWRDWNEN (1<<15)
2025 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
2027 #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
2028 #define CDCLK_FREQ_SHIFT 4
2029 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
2030 #define CZCLK_FREQ_MASK 0xf
2031 #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
2036 #define PALETTE_A_OFFSET 0xa000
2037 #define PALETTE_B_OFFSET 0xa800
2038 #define CHV_PALETTE_C_OFFSET 0xc000
2039 #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
2040 dev_priv->info.display_mmio_offset)
2042 /* MCH MMIO space */
2047 * This mirrors the MCHBAR MMIO space whose location is determined by
2048 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
2049 * every way. It is not accessible from the CP register read instructions.
2051 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
2054 #define MCHBAR_MIRROR_BASE 0x10000
2056 #define MCHBAR_MIRROR_BASE_SNB 0x140000
2058 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
2059 #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
2061 /* 915-945 and GM965 MCH register controlling DRAM channel access */
2063 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
2064 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
2065 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
2066 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
2067 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
2068 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
2069 #define DCC2 0x10204
2070 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
2072 /* Pineview MCH register contains DDR3 setting */
2073 #define CSHRDDR3CTL 0x101a8
2074 #define CSHRDDR3CTL_DDR3 (1 << 2)
2076 /* 965 MCH register controlling DRAM channel configuration */
2077 #define C0DRB3 0x10206
2078 #define C1DRB3 0x10606
2080 /* snb MCH registers for reading the DRAM channel configuration */
2081 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
2082 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
2083 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
2084 #define MAD_DIMM_ECC_MASK (0x3 << 24)
2085 #define MAD_DIMM_ECC_OFF (0x0 << 24)
2086 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
2087 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
2088 #define MAD_DIMM_ECC_ON (0x3 << 24)
2089 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
2090 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
2091 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
2092 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
2093 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
2094 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
2095 #define MAD_DIMM_A_SELECT (0x1 << 16)
2096 /* DIMM sizes are in multiples of 256mb. */
2097 #define MAD_DIMM_B_SIZE_SHIFT 8
2098 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
2099 #define MAD_DIMM_A_SIZE_SHIFT 0
2100 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
2102 /* snb MCH registers for priority tuning */
2103 #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
2104 #define MCH_SSKPD_WM0_MASK 0x3f
2105 #define MCH_SSKPD_WM0_VAL 0xc
2107 #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
2109 /* Clocking configuration register */
2110 #define CLKCFG 0x10c00
2111 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
2112 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
2113 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
2114 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
2115 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
2116 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
2117 /* Note, below two are guess */
2118 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
2119 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
2120 #define CLKCFG_FSB_MASK (7 << 0)
2121 #define CLKCFG_MEM_533 (1 << 4)
2122 #define CLKCFG_MEM_667 (2 << 4)
2123 #define CLKCFG_MEM_800 (3 << 4)
2124 #define CLKCFG_MEM_MASK (7 << 4)
2126 #define TSC1 0x11001
2129 #define TSFS 0x11020
2130 #define TSFS_SLOPE_MASK 0x0000ff00
2131 #define TSFS_SLOPE_SHIFT 8
2132 #define TSFS_INTR_MASK 0x000000ff
2134 #define CRSTANDVID 0x11100
2135 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2136 #define PXVFREQ_PX_MASK 0x7f000000
2137 #define PXVFREQ_PX_SHIFT 24
2138 #define VIDFREQ_BASE 0x11110
2139 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2140 #define VIDFREQ2 0x11114
2141 #define VIDFREQ3 0x11118
2142 #define VIDFREQ4 0x1111c
2143 #define VIDFREQ_P0_MASK 0x1f000000
2144 #define VIDFREQ_P0_SHIFT 24
2145 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
2146 #define VIDFREQ_P0_CSCLK_SHIFT 20
2147 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
2148 #define VIDFREQ_P0_CRCLK_SHIFT 16
2149 #define VIDFREQ_P1_MASK 0x00001f00
2150 #define VIDFREQ_P1_SHIFT 8
2151 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2152 #define VIDFREQ_P1_CSCLK_SHIFT 4
2153 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
2154 #define INTTOEXT_BASE_ILK 0x11300
2155 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
2156 #define INTTOEXT_MAP3_SHIFT 24
2157 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2158 #define INTTOEXT_MAP2_SHIFT 16
2159 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
2160 #define INTTOEXT_MAP1_SHIFT 8
2161 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2162 #define INTTOEXT_MAP0_SHIFT 0
2163 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
2164 #define MEMSWCTL 0x11170 /* Ironlake only */
2165 #define MEMCTL_CMD_MASK 0xe000
2166 #define MEMCTL_CMD_SHIFT 13
2167 #define MEMCTL_CMD_RCLK_OFF 0
2168 #define MEMCTL_CMD_RCLK_ON 1
2169 #define MEMCTL_CMD_CHFREQ 2
2170 #define MEMCTL_CMD_CHVID 3
2171 #define MEMCTL_CMD_VMMOFF 4
2172 #define MEMCTL_CMD_VMMON 5
2173 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
2174 when command complete */
2175 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
2176 #define MEMCTL_FREQ_SHIFT 8
2177 #define MEMCTL_SFCAVM (1<<7)
2178 #define MEMCTL_TGT_VID_MASK 0x007f
2179 #define MEMIHYST 0x1117c
2180 #define MEMINTREN 0x11180 /* 16 bits */
2181 #define MEMINT_RSEXIT_EN (1<<8)
2182 #define MEMINT_CX_SUPR_EN (1<<7)
2183 #define MEMINT_CONT_BUSY_EN (1<<6)
2184 #define MEMINT_AVG_BUSY_EN (1<<5)
2185 #define MEMINT_EVAL_CHG_EN (1<<4)
2186 #define MEMINT_MON_IDLE_EN (1<<3)
2187 #define MEMINT_UP_EVAL_EN (1<<2)
2188 #define MEMINT_DOWN_EVAL_EN (1<<1)
2189 #define MEMINT_SW_CMD_EN (1<<0)
2190 #define MEMINTRSTR 0x11182 /* 16 bits */
2191 #define MEM_RSEXIT_MASK 0xc000
2192 #define MEM_RSEXIT_SHIFT 14
2193 #define MEM_CONT_BUSY_MASK 0x3000
2194 #define MEM_CONT_BUSY_SHIFT 12
2195 #define MEM_AVG_BUSY_MASK 0x0c00
2196 #define MEM_AVG_BUSY_SHIFT 10
2197 #define MEM_EVAL_CHG_MASK 0x0300
2198 #define MEM_EVAL_BUSY_SHIFT 8
2199 #define MEM_MON_IDLE_MASK 0x00c0
2200 #define MEM_MON_IDLE_SHIFT 6
2201 #define MEM_UP_EVAL_MASK 0x0030
2202 #define MEM_UP_EVAL_SHIFT 4
2203 #define MEM_DOWN_EVAL_MASK 0x000c
2204 #define MEM_DOWN_EVAL_SHIFT 2
2205 #define MEM_SW_CMD_MASK 0x0003
2206 #define MEM_INT_STEER_GFX 0
2207 #define MEM_INT_STEER_CMR 1
2208 #define MEM_INT_STEER_SMI 2
2209 #define MEM_INT_STEER_SCI 3
2210 #define MEMINTRSTS 0x11184
2211 #define MEMINT_RSEXIT (1<<7)
2212 #define MEMINT_CONT_BUSY (1<<6)
2213 #define MEMINT_AVG_BUSY (1<<5)
2214 #define MEMINT_EVAL_CHG (1<<4)
2215 #define MEMINT_MON_IDLE (1<<3)
2216 #define MEMINT_UP_EVAL (1<<2)
2217 #define MEMINT_DOWN_EVAL (1<<1)
2218 #define MEMINT_SW_CMD (1<<0)
2219 #define MEMMODECTL 0x11190
2220 #define MEMMODE_BOOST_EN (1<<31)
2221 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2222 #define MEMMODE_BOOST_FREQ_SHIFT 24
2223 #define MEMMODE_IDLE_MODE_MASK 0x00030000
2224 #define MEMMODE_IDLE_MODE_SHIFT 16
2225 #define MEMMODE_IDLE_MODE_EVAL 0
2226 #define MEMMODE_IDLE_MODE_CONT 1
2227 #define MEMMODE_HWIDLE_EN (1<<15)
2228 #define MEMMODE_SWMODE_EN (1<<14)
2229 #define MEMMODE_RCLK_GATE (1<<13)
2230 #define MEMMODE_HW_UPDATE (1<<12)
2231 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
2232 #define MEMMODE_FSTART_SHIFT 8
2233 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2234 #define MEMMODE_FMAX_SHIFT 4
2235 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
2236 #define RCBMAXAVG 0x1119c
2237 #define MEMSWCTL2 0x1119e /* Cantiga only */
2238 #define SWMEMCMD_RENDER_OFF (0 << 13)
2239 #define SWMEMCMD_RENDER_ON (1 << 13)
2240 #define SWMEMCMD_SWFREQ (2 << 13)
2241 #define SWMEMCMD_TARVID (3 << 13)
2242 #define SWMEMCMD_VRM_OFF (4 << 13)
2243 #define SWMEMCMD_VRM_ON (5 << 13)
2244 #define CMDSTS (1<<12)
2245 #define SFCAVM (1<<11)
2246 #define SWFREQ_MASK 0x0380 /* P0-7 */
2247 #define SWFREQ_SHIFT 7
2248 #define TARVID_MASK 0x001f
2249 #define MEMSTAT_CTG 0x111a0
2250 #define RCBMINAVG 0x111a0
2251 #define RCUPEI 0x111b0
2252 #define RCDNEI 0x111b4
2253 #define RSTDBYCTL 0x111b8
2254 #define RS1EN (1<<31)
2255 #define RS2EN (1<<30)
2256 #define RS3EN (1<<29)
2257 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
2258 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
2259 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
2260 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
2261 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
2262 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
2263 #define RSX_STATUS_MASK (7<<20)
2264 #define RSX_STATUS_ON (0<<20)
2265 #define RSX_STATUS_RC1 (1<<20)
2266 #define RSX_STATUS_RC1E (2<<20)
2267 #define RSX_STATUS_RS1 (3<<20)
2268 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
2269 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
2270 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
2271 #define RSX_STATUS_RSVD2 (7<<20)
2272 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
2273 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
2274 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
2275 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
2276 #define RS1CONTSAV_MASK (3<<14)
2277 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
2278 #define RS1CONTSAV_RSVD (1<<14)
2279 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
2280 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
2281 #define NORMSLEXLAT_MASK (3<<12)
2282 #define SLOW_RS123 (0<<12)
2283 #define SLOW_RS23 (1<<12)
2284 #define SLOW_RS3 (2<<12)
2285 #define NORMAL_RS123 (3<<12)
2286 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
2287 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2288 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
2289 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
2290 #define RS_CSTATE_MASK (3<<4)
2291 #define RS_CSTATE_C367_RS1 (0<<4)
2292 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2293 #define RS_CSTATE_RSVD (2<<4)
2294 #define RS_CSTATE_C367_RS2 (3<<4)
2295 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2296 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
2297 #define VIDCTL 0x111c0
2298 #define VIDSTS 0x111c8
2299 #define VIDSTART 0x111cc /* 8 bits */
2300 #define MEMSTAT_ILK 0x111f8
2301 #define MEMSTAT_VID_MASK 0x7f00
2302 #define MEMSTAT_VID_SHIFT 8
2303 #define MEMSTAT_PSTATE_MASK 0x00f8
2304 #define MEMSTAT_PSTATE_SHIFT 3
2305 #define MEMSTAT_MON_ACTV (1<<2)
2306 #define MEMSTAT_SRC_CTL_MASK 0x0003
2307 #define MEMSTAT_SRC_CTL_CORE 0
2308 #define MEMSTAT_SRC_CTL_TRB 1
2309 #define MEMSTAT_SRC_CTL_THM 2
2310 #define MEMSTAT_SRC_CTL_STDBY 3
2311 #define RCPREVBSYTUPAVG 0x113b8
2312 #define RCPREVBSYTDNAVG 0x113bc
2313 #define PMMISC 0x11214
2314 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
2315 #define SDEW 0x1124c
2316 #define CSIEW0 0x11250
2317 #define CSIEW1 0x11254
2318 #define CSIEW2 0x11258
2321 #define MCHAFE 0x112c0
2322 #define CSIEC 0x112e0
2323 #define DMIEC 0x112e4
2324 #define DDREC 0x112e8
2325 #define PEG0EC 0x112ec
2326 #define PEG1EC 0x112f0
2327 #define GFXEC 0x112f4
2328 #define RPPREVBSYTUPAVG 0x113b8
2329 #define RPPREVBSYTDNAVG 0x113bc
2331 #define ECR_GPFE (1<<31)
2332 #define ECR_IMONE (1<<30)
2333 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
2334 #define OGW0 0x11608
2335 #define OGW1 0x1160c
2345 #define PXWL 0x11680
2346 #define LCFUSE02 0x116c0
2347 #define LCFUSE_HIV_MASK 0x000000ff
2348 #define CSIPLL0 0x12c10
2349 #define DDRMPLL1 0X12c20
2350 #define PEG_BAND_GAP_DATA 0x14d68
2352 #define GEN6_GT_THREAD_STATUS_REG 0x13805c
2353 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2355 #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
2356 #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
2357 #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
2360 * Logical Context regs
2363 #define CCID_EN (1<<0)
2365 * Notes on SNB/IVB/VLV context size:
2366 * - Power context is saved elsewhere (LLC or stolen)
2367 * - Ring/execlist context is saved on SNB, not on IVB
2368 * - Extended context size already includes render context size
2369 * - We always need to follow the extended context size.
2370 * SNB BSpec has comments indicating that we should use the
2371 * render context size instead if execlists are disabled, but
2372 * based on empirical testing that's just nonsense.
2373 * - Pipelined/VF state is saved on SNB/IVB respectively
2374 * - GT1 size just indicates how much of render context
2375 * doesn't need saving on GT1
2377 #define CXT_SIZE 0x21a0
2378 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
2379 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
2380 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
2381 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
2382 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
2383 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
2384 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2385 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
2386 #define GEN7_CXT_SIZE 0x21a8
2387 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
2388 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
2389 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
2390 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
2391 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
2392 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
2393 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
2394 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
2395 /* Haswell does have the CXT_SIZE register however it does not appear to be
2396 * valid. Now, docs explain in dwords what is in the context object. The full
2397 * size is 70720 bytes, however, the power context and execlist context will
2398 * never be saved (power context is stored elsewhere, and execlists don't work
2399 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
2401 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
2402 /* Same as Haswell, but 72064 bytes now. */
2403 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
2405 #define CHV_CLK_CTL1 0x101100
2406 #define VLV_CLK_CTL2 0x101104
2407 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
2413 #define OVADD 0x30000
2414 #define DOVSTA 0x30008
2415 #define OC_BUF (0x3<<20)
2416 #define OGAMC5 0x30010
2417 #define OGAMC4 0x30014
2418 #define OGAMC3 0x30018
2419 #define OGAMC2 0x3001c
2420 #define OGAMC1 0x30020
2421 #define OGAMC0 0x30024
2424 * Display engine regs
2427 /* Pipe A CRC regs */
2428 #define _PIPE_CRC_CTL_A 0x60050
2429 #define PIPE_CRC_ENABLE (1 << 31)
2430 /* ivb+ source selection */
2431 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
2432 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
2433 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
2434 /* ilk+ source selection */
2435 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
2436 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
2437 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
2438 /* embedded DP port on the north display block, reserved on ivb */
2439 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
2440 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
2441 /* vlv source selection */
2442 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
2443 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
2444 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
2445 /* with DP port the pipe source is invalid */
2446 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
2447 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
2448 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
2449 /* gen3+ source selection */
2450 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
2451 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
2452 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
2453 /* with DP/TV port the pipe source is invalid */
2454 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
2455 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
2456 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
2457 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
2458 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
2459 /* gen2 doesn't have source selection bits */
2460 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
2462 #define _PIPE_CRC_RES_1_A_IVB 0x60064
2463 #define _PIPE_CRC_RES_2_A_IVB 0x60068
2464 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
2465 #define _PIPE_CRC_RES_4_A_IVB 0x60070
2466 #define _PIPE_CRC_RES_5_A_IVB 0x60074
2468 #define _PIPE_CRC_RES_RED_A 0x60060
2469 #define _PIPE_CRC_RES_GREEN_A 0x60064
2470 #define _PIPE_CRC_RES_BLUE_A 0x60068
2471 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
2472 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
2474 /* Pipe B CRC regs */
2475 #define _PIPE_CRC_RES_1_B_IVB 0x61064
2476 #define _PIPE_CRC_RES_2_B_IVB 0x61068
2477 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
2478 #define _PIPE_CRC_RES_4_B_IVB 0x61070
2479 #define _PIPE_CRC_RES_5_B_IVB 0x61074
2481 #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
2482 #define PIPE_CRC_RES_1_IVB(pipe) \
2483 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
2484 #define PIPE_CRC_RES_2_IVB(pipe) \
2485 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
2486 #define PIPE_CRC_RES_3_IVB(pipe) \
2487 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
2488 #define PIPE_CRC_RES_4_IVB(pipe) \
2489 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
2490 #define PIPE_CRC_RES_5_IVB(pipe) \
2491 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
2493 #define PIPE_CRC_RES_RED(pipe) \
2494 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
2495 #define PIPE_CRC_RES_GREEN(pipe) \
2496 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
2497 #define PIPE_CRC_RES_BLUE(pipe) \
2498 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
2499 #define PIPE_CRC_RES_RES1_I915(pipe) \
2500 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
2501 #define PIPE_CRC_RES_RES2_G4X(pipe) \
2502 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
2504 /* Pipe A timing regs */
2505 #define _HTOTAL_A 0x60000
2506 #define _HBLANK_A 0x60004
2507 #define _HSYNC_A 0x60008
2508 #define _VTOTAL_A 0x6000c
2509 #define _VBLANK_A 0x60010
2510 #define _VSYNC_A 0x60014
2511 #define _PIPEASRC 0x6001c
2512 #define _BCLRPAT_A 0x60020
2513 #define _VSYNCSHIFT_A 0x60028
2514 #define _PIPE_MULT_A 0x6002c
2516 /* Pipe B timing regs */
2517 #define _HTOTAL_B 0x61000
2518 #define _HBLANK_B 0x61004
2519 #define _HSYNC_B 0x61008
2520 #define _VTOTAL_B 0x6100c
2521 #define _VBLANK_B 0x61010
2522 #define _VSYNC_B 0x61014
2523 #define _PIPEBSRC 0x6101c
2524 #define _BCLRPAT_B 0x61020
2525 #define _VSYNCSHIFT_B 0x61028
2526 #define _PIPE_MULT_B 0x6102c
2528 #define TRANSCODER_A_OFFSET 0x60000
2529 #define TRANSCODER_B_OFFSET 0x61000
2530 #define TRANSCODER_C_OFFSET 0x62000
2531 #define CHV_TRANSCODER_C_OFFSET 0x63000
2532 #define TRANSCODER_EDP_OFFSET 0x6f000
2534 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
2535 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
2536 dev_priv->info.display_mmio_offset)
2538 #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
2539 #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
2540 #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
2541 #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
2542 #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
2543 #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
2544 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
2545 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
2546 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
2547 #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
2549 /* VLV eDP PSR registers */
2550 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
2551 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
2552 #define VLV_EDP_PSR_ENABLE (1<<0)
2553 #define VLV_EDP_PSR_RESET (1<<1)
2554 #define VLV_EDP_PSR_MODE_MASK (7<<2)
2555 #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
2556 #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
2557 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
2558 #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
2559 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
2560 #define VLV_EDP_PSR_DBL_FRAME (1<<10)
2561 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
2562 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
2563 #define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB)
2565 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
2566 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
2567 #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
2568 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
2569 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
2570 #define VLV_VSCSDP(pipe) _PIPE(pipe, _VSCSDPA, _VSCSDPB)
2572 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
2573 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
2574 #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
2575 #define VLV_EDP_PSR_CURR_STATE_MASK 7
2576 #define VLV_EDP_PSR_DISABLED (0<<0)
2577 #define VLV_EDP_PSR_INACTIVE (1<<0)
2578 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
2579 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
2580 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
2581 #define VLV_EDP_PSR_EXIT (5<<0)
2582 #define VLV_EDP_PSR_IN_TRANS (1<<7)
2583 #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
2585 /* HSW+ eDP PSR registers */
2586 #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
2587 #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
2588 #define EDP_PSR_ENABLE (1<<31)
2589 #define BDW_PSR_SINGLE_FRAME (1<<30)
2590 #define EDP_PSR_LINK_DISABLE (0<<27)
2591 #define EDP_PSR_LINK_STANDBY (1<<27)
2592 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
2593 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
2594 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
2595 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
2596 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
2597 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
2598 #define EDP_PSR_SKIP_AUX_EXIT (1<<12)
2599 #define EDP_PSR_TP1_TP2_SEL (0<<11)
2600 #define EDP_PSR_TP1_TP3_SEL (1<<11)
2601 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
2602 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
2603 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
2604 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
2605 #define EDP_PSR_TP1_TIME_500us (0<<4)
2606 #define EDP_PSR_TP1_TIME_100us (1<<4)
2607 #define EDP_PSR_TP1_TIME_2500us (2<<4)
2608 #define EDP_PSR_TP1_TIME_0us (3<<4)
2609 #define EDP_PSR_IDLE_FRAME_SHIFT 0
2611 #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
2612 #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
2613 #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
2614 #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
2615 #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
2616 #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
2618 #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
2619 #define EDP_PSR_STATUS_STATE_MASK (7<<29)
2620 #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
2621 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
2622 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
2623 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
2624 #define EDP_PSR_STATUS_STATE_BUFON (4<<29)
2625 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
2626 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
2627 #define EDP_PSR_STATUS_LINK_MASK (3<<26)
2628 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
2629 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
2630 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
2631 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2632 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2633 #define EDP_PSR_STATUS_COUNT_SHIFT 16
2634 #define EDP_PSR_STATUS_COUNT_MASK 0xf
2635 #define EDP_PSR_STATUS_AUX_ERROR (1<<15)
2636 #define EDP_PSR_STATUS_AUX_SENDING (1<<12)
2637 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
2638 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
2639 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
2640 #define EDP_PSR_STATUS_IDLE_MASK 0xf
2642 #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
2643 #define EDP_PSR_PERF_CNT_MASK 0xffffff
2645 #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
2646 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
2647 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
2648 #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
2650 /* VGA port control */
2651 #define ADPA 0x61100
2652 #define PCH_ADPA 0xe1100
2653 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
2655 #define ADPA_DAC_ENABLE (1<<31)
2656 #define ADPA_DAC_DISABLE 0
2657 #define ADPA_PIPE_SELECT_MASK (1<<30)
2658 #define ADPA_PIPE_A_SELECT 0
2659 #define ADPA_PIPE_B_SELECT (1<<30)
2660 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
2661 /* CPT uses bits 29:30 for pch transcoder select */
2662 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2663 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2664 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2665 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2666 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2667 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2668 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2669 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2670 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2671 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2672 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2673 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2674 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2675 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2676 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2677 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2678 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2679 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2680 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2681 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
2682 #define ADPA_SETS_HVPOLARITY 0
2683 #define ADPA_VSYNC_CNTL_DISABLE (1<<10)
2684 #define ADPA_VSYNC_CNTL_ENABLE 0
2685 #define ADPA_HSYNC_CNTL_DISABLE (1<<11)
2686 #define ADPA_HSYNC_CNTL_ENABLE 0
2687 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
2688 #define ADPA_VSYNC_ACTIVE_LOW 0
2689 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
2690 #define ADPA_HSYNC_ACTIVE_LOW 0
2691 #define ADPA_DPMS_MASK (~(3<<10))
2692 #define ADPA_DPMS_ON (0<<10)
2693 #define ADPA_DPMS_SUSPEND (1<<10)
2694 #define ADPA_DPMS_STANDBY (2<<10)
2695 #define ADPA_DPMS_OFF (3<<10)
2698 /* Hotplug control (945+ only) */
2699 #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
2700 #define PORTB_HOTPLUG_INT_EN (1 << 29)
2701 #define PORTC_HOTPLUG_INT_EN (1 << 28)
2702 #define PORTD_HOTPLUG_INT_EN (1 << 27)
2703 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
2704 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
2705 #define TV_HOTPLUG_INT_EN (1 << 18)
2706 #define CRT_HOTPLUG_INT_EN (1 << 9)
2707 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2708 PORTC_HOTPLUG_INT_EN | \
2709 PORTD_HOTPLUG_INT_EN | \
2710 SDVOC_HOTPLUG_INT_EN | \
2711 SDVOB_HOTPLUG_INT_EN | \
2713 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
2714 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2715 /* must use period 64 on GM45 according to docs */
2716 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2717 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2718 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2719 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2720 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2721 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2722 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2723 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2724 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2725 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2726 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2727 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
2729 #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
2731 * HDMI/DP bits are gen4+
2733 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
2734 * Please check the detailed lore in the commit message for for experimental
2737 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2738 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2739 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2740 /* VLV DP/HDMI bits again match Bspec */
2741 #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
2742 #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
2743 #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
2744 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2745 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
2746 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
2747 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2748 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
2749 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
2750 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
2751 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
2752 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
2753 /* CRT/TV common between gen3+ */
2754 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
2755 #define TV_HOTPLUG_INT_STATUS (1 << 10)
2756 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2757 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2758 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2759 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
2760 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2761 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2762 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
2763 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2765 /* SDVO is different across gen3/4 */
2766 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2767 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
2769 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2770 * since reality corrobates that they're the same as on gen3. But keep these
2771 * bits here (and the comment!) to help any other lost wanderers back onto the
2774 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2775 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2776 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2777 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
2778 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2779 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2780 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2781 PORTB_HOTPLUG_INT_STATUS | \
2782 PORTC_HOTPLUG_INT_STATUS | \
2783 PORTD_HOTPLUG_INT_STATUS)
2785 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2786 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2787 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2788 PORTB_HOTPLUG_INT_STATUS | \
2789 PORTC_HOTPLUG_INT_STATUS | \
2790 PORTD_HOTPLUG_INT_STATUS)
2792 /* SDVO and HDMI port control.
2793 * The same register may be used for SDVO or HDMI */
2794 #define GEN3_SDVOB 0x61140
2795 #define GEN3_SDVOC 0x61160
2796 #define GEN4_HDMIB GEN3_SDVOB
2797 #define GEN4_HDMIC GEN3_SDVOC
2798 #define CHV_HDMID 0x6116C
2799 #define PCH_SDVOB 0xe1140
2800 #define PCH_HDMIB PCH_SDVOB
2801 #define PCH_HDMIC 0xe1150
2802 #define PCH_HDMID 0xe1160
2804 #define PORT_DFT_I9XX 0x61150
2805 #define DC_BALANCE_RESET (1 << 25)
2806 #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
2807 #define DC_BALANCE_RESET_VLV (1 << 31)
2808 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
2809 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
2810 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
2811 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
2813 /* Gen 3 SDVO bits: */
2814 #define SDVO_ENABLE (1 << 31)
2815 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2816 #define SDVO_PIPE_SEL_MASK (1 << 30)
2817 #define SDVO_PIPE_B_SELECT (1 << 30)
2818 #define SDVO_STALL_SELECT (1 << 29)
2819 #define SDVO_INTERRUPT_ENABLE (1 << 26)
2821 * 915G/GM SDVO pixel multiplier.
2822 * Programmed value is multiplier - 1, up to 5x.
2823 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2825 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
2826 #define SDVO_PORT_MULTIPLY_SHIFT 23
2827 #define SDVO_PHASE_SELECT_MASK (15 << 19)
2828 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2829 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2830 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2831 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2832 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2833 #define SDVO_DETECTED (1 << 2)
2834 /* Bits to be preserved when writing */
2835 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2836 SDVO_INTERRUPT_ENABLE)
2837 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2839 /* Gen 4 SDVO/HDMI bits: */
2840 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
2841 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
2842 #define SDVO_ENCODING_SDVO (0 << 10)
2843 #define SDVO_ENCODING_HDMI (2 << 10)
2844 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2845 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
2846 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
2847 #define SDVO_AUDIO_ENABLE (1 << 6)
2848 /* VSYNC/HSYNC bits new with 965, default is to be set */
2849 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2850 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2852 /* Gen 5 (IBX) SDVO/HDMI bits: */
2853 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
2854 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2856 /* Gen 6 (CPT) SDVO/HDMI bits: */
2857 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2858 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
2860 /* CHV SDVO/HDMI bits: */
2861 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
2862 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
2865 /* DVO port control */
2866 #define DVOA 0x61120
2867 #define DVOB 0x61140
2868 #define DVOC 0x61160
2869 #define DVO_ENABLE (1 << 31)
2870 #define DVO_PIPE_B_SELECT (1 << 30)
2871 #define DVO_PIPE_STALL_UNUSED (0 << 28)
2872 #define DVO_PIPE_STALL (1 << 28)
2873 #define DVO_PIPE_STALL_TV (2 << 28)
2874 #define DVO_PIPE_STALL_MASK (3 << 28)
2875 #define DVO_USE_VGA_SYNC (1 << 15)
2876 #define DVO_DATA_ORDER_I740 (0 << 14)
2877 #define DVO_DATA_ORDER_FP (1 << 14)
2878 #define DVO_VSYNC_DISABLE (1 << 11)
2879 #define DVO_HSYNC_DISABLE (1 << 10)
2880 #define DVO_VSYNC_TRISTATE (1 << 9)
2881 #define DVO_HSYNC_TRISTATE (1 << 8)
2882 #define DVO_BORDER_ENABLE (1 << 7)
2883 #define DVO_DATA_ORDER_GBRG (1 << 6)
2884 #define DVO_DATA_ORDER_RGGB (0 << 6)
2885 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2886 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2887 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2888 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2889 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2890 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2891 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2892 #define DVO_PRESERVE_MASK (0x7<<24)
2893 #define DVOA_SRCDIM 0x61124
2894 #define DVOB_SRCDIM 0x61144
2895 #define DVOC_SRCDIM 0x61164
2896 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2897 #define DVO_SRCDIM_VERTICAL_SHIFT 0
2899 /* LVDS port control */
2900 #define LVDS 0x61180
2902 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2903 * the DPLL semantics change when the LVDS is assigned to that pipe.
2905 #define LVDS_PORT_EN (1 << 31)
2906 /* Selects pipe B for LVDS data. Must be set on pre-965. */
2907 #define LVDS_PIPEB_SELECT (1 << 30)
2908 #define LVDS_PIPE_MASK (1 << 30)
2909 #define LVDS_PIPE(pipe) ((pipe) << 30)
2910 /* LVDS dithering flag on 965/g4x platform */
2911 #define LVDS_ENABLE_DITHER (1 << 25)
2912 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
2913 #define LVDS_VSYNC_POLARITY (1 << 21)
2914 #define LVDS_HSYNC_POLARITY (1 << 20)
2916 /* Enable border for unscaled (or aspect-scaled) display */
2917 #define LVDS_BORDER_ENABLE (1 << 15)
2919 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2922 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2923 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2924 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2926 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2927 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2930 #define LVDS_A3_POWER_MASK (3 << 6)
2931 #define LVDS_A3_POWER_DOWN (0 << 6)
2932 #define LVDS_A3_POWER_UP (3 << 6)
2934 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2937 #define LVDS_CLKB_POWER_MASK (3 << 4)
2938 #define LVDS_CLKB_POWER_DOWN (0 << 4)
2939 #define LVDS_CLKB_POWER_UP (3 << 4)
2941 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2942 * setting for whether we are in dual-channel mode. The B3 pair will
2943 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2945 #define LVDS_B0B3_POWER_MASK (3 << 2)
2946 #define LVDS_B0B3_POWER_DOWN (0 << 2)
2947 #define LVDS_B0B3_POWER_UP (3 << 2)
2949 /* Video Data Island Packet control */
2950 #define VIDEO_DIP_DATA 0x61178
2951 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
2952 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2953 * of the infoframe structure specified by CEA-861. */
2954 #define VIDEO_DIP_DATA_SIZE 32
2955 #define VIDEO_DIP_VSC_DATA_SIZE 36
2956 #define VIDEO_DIP_CTL 0x61170
2958 #define VIDEO_DIP_ENABLE (1 << 31)
2959 #define VIDEO_DIP_PORT(port) ((port) << 29)
2960 #define VIDEO_DIP_PORT_MASK (3 << 29)
2961 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
2962 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
2963 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
2964 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
2965 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
2966 #define VIDEO_DIP_SELECT_AVI (0 << 19)
2967 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2968 #define VIDEO_DIP_SELECT_SPD (3 << 19)
2969 #define VIDEO_DIP_SELECT_MASK (3 << 19)
2970 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
2971 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2972 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
2973 #define VIDEO_DIP_FREQ_MASK (3 << 16)
2974 /* HSW and later: */
2975 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2976 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
2977 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
2978 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2979 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
2980 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
2982 /* Panel power sequencing */
2983 #define PP_STATUS 0x61200
2984 #define PP_ON (1 << 31)
2986 * Indicates that all dependencies of the panel are on:
2990 * - LVDS/DVOB/DVOC on
2992 #define PP_READY (1 << 30)
2993 #define PP_SEQUENCE_NONE (0 << 28)
2994 #define PP_SEQUENCE_POWER_UP (1 << 28)
2995 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
2996 #define PP_SEQUENCE_MASK (3 << 28)
2997 #define PP_SEQUENCE_SHIFT 28
2998 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
2999 #define PP_SEQUENCE_STATE_MASK 0x0000000f
3000 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
3001 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
3002 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
3003 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
3004 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
3005 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
3006 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
3007 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
3008 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
3009 #define PP_CONTROL 0x61204
3010 #define POWER_TARGET_ON (1 << 0)
3011 #define PP_ON_DELAYS 0x61208
3012 #define PP_OFF_DELAYS 0x6120c
3013 #define PP_DIVISOR 0x61210
3016 #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
3017 #define PFIT_ENABLE (1 << 31)
3018 #define PFIT_PIPE_MASK (3 << 29)
3019 #define PFIT_PIPE_SHIFT 29
3020 #define VERT_INTERP_DISABLE (0 << 10)
3021 #define VERT_INTERP_BILINEAR (1 << 10)
3022 #define VERT_INTERP_MASK (3 << 10)
3023 #define VERT_AUTO_SCALE (1 << 9)
3024 #define HORIZ_INTERP_DISABLE (0 << 6)
3025 #define HORIZ_INTERP_BILINEAR (1 << 6)
3026 #define HORIZ_INTERP_MASK (3 << 6)
3027 #define HORIZ_AUTO_SCALE (1 << 5)
3028 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
3029 #define PFIT_FILTER_FUZZY (0 << 24)
3030 #define PFIT_SCALING_AUTO (0 << 26)
3031 #define PFIT_SCALING_PROGRAMMED (1 << 26)
3032 #define PFIT_SCALING_PILLAR (2 << 26)
3033 #define PFIT_SCALING_LETTER (3 << 26)
3034 #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
3036 #define PFIT_VERT_SCALE_SHIFT 20
3037 #define PFIT_VERT_SCALE_MASK 0xfff00000
3038 #define PFIT_HORIZ_SCALE_SHIFT 4
3039 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
3041 #define PFIT_VERT_SCALE_SHIFT_965 16
3042 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
3043 #define PFIT_HORIZ_SCALE_SHIFT_965 0
3044 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
3046 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
3048 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3049 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
3050 #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
3051 _VLV_BLC_PWM_CTL2_B)
3053 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3054 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
3055 #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
3058 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3059 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3060 #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
3061 _VLV_BLC_HIST_CTL_B)
3063 /* Backlight control */
3064 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3065 #define BLM_PWM_ENABLE (1 << 31)
3066 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
3067 #define BLM_PIPE_SELECT (1 << 29)
3068 #define BLM_PIPE_SELECT_IVB (3 << 29)
3069 #define BLM_PIPE_A (0 << 29)
3070 #define BLM_PIPE_B (1 << 29)
3071 #define BLM_PIPE_C (2 << 29) /* ivb + */
3072 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
3073 #define BLM_TRANSCODER_B BLM_PIPE_B
3074 #define BLM_TRANSCODER_C BLM_PIPE_C
3075 #define BLM_TRANSCODER_EDP (3 << 29)
3076 #define BLM_PIPE(pipe) ((pipe) << 29)
3077 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
3078 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
3079 #define BLM_PHASE_IN_ENABLE (1 << 25)
3080 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
3081 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
3082 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
3083 #define BLM_PHASE_IN_COUNT_SHIFT (8)
3084 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
3085 #define BLM_PHASE_IN_INCR_SHIFT (0)
3086 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
3087 #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
3089 * This is the most significant 15 bits of the number of backlight cycles in a
3090 * complete cycle of the modulated backlight control.
3092 * The actual value is this field multiplied by two.
3094 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
3095 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
3096 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
3098 * This is the number of cycles out of the backlight modulation cycle for which
3099 * the backlight is on.
3101 * This field must be no greater than the number of cycles in the complete
3102 * backlight modulation cycle.
3104 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
3105 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
3106 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
3107 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
3109 #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
3111 /* New registers for PCH-split platforms. Safe where new bits show up, the
3112 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
3113 #define BLC_PWM_CPU_CTL2 0x48250
3114 #define BLC_PWM_CPU_CTL 0x48254
3116 #define HSW_BLC_PWM2_CTL 0x48350
3118 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3119 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
3120 #define BLC_PWM_PCH_CTL1 0xc8250
3121 #define BLM_PCH_PWM_ENABLE (1 << 31)
3122 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
3123 #define BLM_PCH_POLARITY (1 << 29)
3124 #define BLC_PWM_PCH_CTL2 0xc8254
3126 #define UTIL_PIN_CTL 0x48400
3127 #define UTIL_PIN_ENABLE (1 << 31)
3129 #define PCH_GTC_CTL 0xe7000
3130 #define PCH_GTC_ENABLE (1 << 31)
3132 /* TV port control */
3133 #define TV_CTL 0x68000
3134 /* Enables the TV encoder */
3135 # define TV_ENC_ENABLE (1 << 31)
3136 /* Sources the TV encoder input from pipe B instead of A. */
3137 # define TV_ENC_PIPEB_SELECT (1 << 30)
3138 /* Outputs composite video (DAC A only) */
3139 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
3140 /* Outputs SVideo video (DAC B/C) */
3141 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
3142 /* Outputs Component video (DAC A/B/C) */
3143 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
3144 /* Outputs Composite and SVideo (DAC A/B/C) */
3145 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
3146 # define TV_TRILEVEL_SYNC (1 << 21)
3147 /* Enables slow sync generation (945GM only) */
3148 # define TV_SLOW_SYNC (1 << 20)
3149 /* Selects 4x oversampling for 480i and 576p */
3150 # define TV_OVERSAMPLE_4X (0 << 18)
3151 /* Selects 2x oversampling for 720p and 1080i */
3152 # define TV_OVERSAMPLE_2X (1 << 18)
3153 /* Selects no oversampling for 1080p */
3154 # define TV_OVERSAMPLE_NONE (2 << 18)
3155 /* Selects 8x oversampling */
3156 # define TV_OVERSAMPLE_8X (3 << 18)
3157 /* Selects progressive mode rather than interlaced */
3158 # define TV_PROGRESSIVE (1 << 17)
3159 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
3160 # define TV_PAL_BURST (1 << 16)
3161 /* Field for setting delay of Y compared to C */
3162 # define TV_YC_SKEW_MASK (7 << 12)
3163 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
3164 # define TV_ENC_SDP_FIX (1 << 11)
3166 * Enables a fix for the 915GM only.
3168 * Not sure what it does.
3170 # define TV_ENC_C0_FIX (1 << 10)
3171 /* Bits that must be preserved by software */
3172 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
3173 # define TV_FUSE_STATE_MASK (3 << 4)
3174 /* Read-only state that reports all features enabled */
3175 # define TV_FUSE_STATE_ENABLED (0 << 4)
3176 /* Read-only state that reports that Macrovision is disabled in hardware*/
3177 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
3178 /* Read-only state that reports that TV-out is disabled in hardware. */
3179 # define TV_FUSE_STATE_DISABLED (2 << 4)
3180 /* Normal operation */
3181 # define TV_TEST_MODE_NORMAL (0 << 0)
3182 /* Encoder test pattern 1 - combo pattern */
3183 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
3184 /* Encoder test pattern 2 - full screen vertical 75% color bars */
3185 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
3186 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
3187 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
3188 /* Encoder test pattern 4 - random noise */
3189 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
3190 /* Encoder test pattern 5 - linear color ramps */
3191 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
3193 * This test mode forces the DACs to 50% of full output.
3195 * This is used for load detection in combination with TVDAC_SENSE_MASK
3197 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3198 # define TV_TEST_MODE_MASK (7 << 0)
3200 #define TV_DAC 0x68004
3201 # define TV_DAC_SAVE 0x00ffff00
3203 * Reports that DAC state change logic has reported change (RO).
3205 * This gets cleared when TV_DAC_STATE_EN is cleared
3207 # define TVDAC_STATE_CHG (1 << 31)
3208 # define TVDAC_SENSE_MASK (7 << 28)
3209 /* Reports that DAC A voltage is above the detect threshold */
3210 # define TVDAC_A_SENSE (1 << 30)
3211 /* Reports that DAC B voltage is above the detect threshold */
3212 # define TVDAC_B_SENSE (1 << 29)
3213 /* Reports that DAC C voltage is above the detect threshold */
3214 # define TVDAC_C_SENSE (1 << 28)
3216 * Enables DAC state detection logic, for load-based TV detection.
3218 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3219 * to off, for load detection to work.
3221 # define TVDAC_STATE_CHG_EN (1 << 27)
3222 /* Sets the DAC A sense value to high */
3223 # define TVDAC_A_SENSE_CTL (1 << 26)
3224 /* Sets the DAC B sense value to high */
3225 # define TVDAC_B_SENSE_CTL (1 << 25)
3226 /* Sets the DAC C sense value to high */
3227 # define TVDAC_C_SENSE_CTL (1 << 24)
3228 /* Overrides the ENC_ENABLE and DAC voltage levels */
3229 # define DAC_CTL_OVERRIDE (1 << 7)
3230 /* Sets the slew rate. Must be preserved in software */
3231 # define ENC_TVDAC_SLEW_FAST (1 << 6)
3232 # define DAC_A_1_3_V (0 << 4)
3233 # define DAC_A_1_1_V (1 << 4)
3234 # define DAC_A_0_7_V (2 << 4)
3235 # define DAC_A_MASK (3 << 4)
3236 # define DAC_B_1_3_V (0 << 2)
3237 # define DAC_B_1_1_V (1 << 2)
3238 # define DAC_B_0_7_V (2 << 2)
3239 # define DAC_B_MASK (3 << 2)
3240 # define DAC_C_1_3_V (0 << 0)
3241 # define DAC_C_1_1_V (1 << 0)
3242 # define DAC_C_0_7_V (2 << 0)
3243 # define DAC_C_MASK (3 << 0)
3246 * CSC coefficients are stored in a floating point format with 9 bits of
3247 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
3248 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3249 * -1 (0x3) being the only legal negative value.
3251 #define TV_CSC_Y 0x68010
3252 # define TV_RY_MASK 0x07ff0000
3253 # define TV_RY_SHIFT 16
3254 # define TV_GY_MASK 0x00000fff
3255 # define TV_GY_SHIFT 0
3257 #define TV_CSC_Y2 0x68014
3258 # define TV_BY_MASK 0x07ff0000
3259 # define TV_BY_SHIFT 16
3261 * Y attenuation for component video.
3263 * Stored in 1.9 fixed point.
3265 # define TV_AY_MASK 0x000003ff
3266 # define TV_AY_SHIFT 0
3268 #define TV_CSC_U 0x68018
3269 # define TV_RU_MASK 0x07ff0000
3270 # define TV_RU_SHIFT 16
3271 # define TV_GU_MASK 0x000007ff
3272 # define TV_GU_SHIFT 0
3274 #define TV_CSC_U2 0x6801c
3275 # define TV_BU_MASK 0x07ff0000
3276 # define TV_BU_SHIFT 16
3278 * U attenuation for component video.
3280 * Stored in 1.9 fixed point.
3282 # define TV_AU_MASK 0x000003ff
3283 # define TV_AU_SHIFT 0
3285 #define TV_CSC_V 0x68020
3286 # define TV_RV_MASK 0x0fff0000
3287 # define TV_RV_SHIFT 16
3288 # define TV_GV_MASK 0x000007ff
3289 # define TV_GV_SHIFT 0
3291 #define TV_CSC_V2 0x68024
3292 # define TV_BV_MASK 0x07ff0000
3293 # define TV_BV_SHIFT 16
3295 * V attenuation for component video.
3297 * Stored in 1.9 fixed point.
3299 # define TV_AV_MASK 0x000007ff
3300 # define TV_AV_SHIFT 0
3302 #define TV_CLR_KNOBS 0x68028
3303 /* 2s-complement brightness adjustment */
3304 # define TV_BRIGHTNESS_MASK 0xff000000
3305 # define TV_BRIGHTNESS_SHIFT 24
3306 /* Contrast adjustment, as a 2.6 unsigned floating point number */
3307 # define TV_CONTRAST_MASK 0x00ff0000
3308 # define TV_CONTRAST_SHIFT 16
3309 /* Saturation adjustment, as a 2.6 unsigned floating point number */
3310 # define TV_SATURATION_MASK 0x0000ff00
3311 # define TV_SATURATION_SHIFT 8
3312 /* Hue adjustment, as an integer phase angle in degrees */
3313 # define TV_HUE_MASK 0x000000ff
3314 # define TV_HUE_SHIFT 0
3316 #define TV_CLR_LEVEL 0x6802c
3317 /* Controls the DAC level for black */
3318 # define TV_BLACK_LEVEL_MASK 0x01ff0000
3319 # define TV_BLACK_LEVEL_SHIFT 16
3320 /* Controls the DAC level for blanking */
3321 # define TV_BLANK_LEVEL_MASK 0x000001ff
3322 # define TV_BLANK_LEVEL_SHIFT 0
3324 #define TV_H_CTL_1 0x68030
3325 /* Number of pixels in the hsync. */
3326 # define TV_HSYNC_END_MASK 0x1fff0000
3327 # define TV_HSYNC_END_SHIFT 16
3328 /* Total number of pixels minus one in the line (display and blanking). */
3329 # define TV_HTOTAL_MASK 0x00001fff
3330 # define TV_HTOTAL_SHIFT 0
3332 #define TV_H_CTL_2 0x68034
3333 /* Enables the colorburst (needed for non-component color) */
3334 # define TV_BURST_ENA (1 << 31)
3335 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
3336 # define TV_HBURST_START_SHIFT 16
3337 # define TV_HBURST_START_MASK 0x1fff0000
3338 /* Length of the colorburst */
3339 # define TV_HBURST_LEN_SHIFT 0
3340 # define TV_HBURST_LEN_MASK 0x0001fff
3342 #define TV_H_CTL_3 0x68038
3343 /* End of hblank, measured in pixels minus one from start of hsync */
3344 # define TV_HBLANK_END_SHIFT 16
3345 # define TV_HBLANK_END_MASK 0x1fff0000
3346 /* Start of hblank, measured in pixels minus one from start of hsync */
3347 # define TV_HBLANK_START_SHIFT 0
3348 # define TV_HBLANK_START_MASK 0x0001fff
3350 #define TV_V_CTL_1 0x6803c
3352 # define TV_NBR_END_SHIFT 16
3353 # define TV_NBR_END_MASK 0x07ff0000
3355 # define TV_VI_END_F1_SHIFT 8
3356 # define TV_VI_END_F1_MASK 0x00003f00
3358 # define TV_VI_END_F2_SHIFT 0
3359 # define TV_VI_END_F2_MASK 0x0000003f
3361 #define TV_V_CTL_2 0x68040
3362 /* Length of vsync, in half lines */
3363 # define TV_VSYNC_LEN_MASK 0x07ff0000
3364 # define TV_VSYNC_LEN_SHIFT 16
3365 /* Offset of the start of vsync in field 1, measured in one less than the
3366 * number of half lines.
3368 # define TV_VSYNC_START_F1_MASK 0x00007f00
3369 # define TV_VSYNC_START_F1_SHIFT 8
3371 * Offset of the start of vsync in field 2, measured in one less than the
3372 * number of half lines.
3374 # define TV_VSYNC_START_F2_MASK 0x0000007f
3375 # define TV_VSYNC_START_F2_SHIFT 0
3377 #define TV_V_CTL_3 0x68044
3378 /* Enables generation of the equalization signal */
3379 # define TV_EQUAL_ENA (1 << 31)
3380 /* Length of vsync, in half lines */
3381 # define TV_VEQ_LEN_MASK 0x007f0000
3382 # define TV_VEQ_LEN_SHIFT 16
3383 /* Offset of the start of equalization in field 1, measured in one less than
3384 * the number of half lines.
3386 # define TV_VEQ_START_F1_MASK 0x0007f00
3387 # define TV_VEQ_START_F1_SHIFT 8
3389 * Offset of the start of equalization in field 2, measured in one less than
3390 * the number of half lines.
3392 # define TV_VEQ_START_F2_MASK 0x000007f
3393 # define TV_VEQ_START_F2_SHIFT 0
3395 #define TV_V_CTL_4 0x68048
3397 * Offset to start of vertical colorburst, measured in one less than the
3398 * number of lines from vertical start.
3400 # define TV_VBURST_START_F1_MASK 0x003f0000
3401 # define TV_VBURST_START_F1_SHIFT 16
3403 * Offset to the end of vertical colorburst, measured in one less than the
3404 * number of lines from the start of NBR.
3406 # define TV_VBURST_END_F1_MASK 0x000000ff
3407 # define TV_VBURST_END_F1_SHIFT 0
3409 #define TV_V_CTL_5 0x6804c
3411 * Offset to start of vertical colorburst, measured in one less than the
3412 * number of lines from vertical start.
3414 # define TV_VBURST_START_F2_MASK 0x003f0000
3415 # define TV_VBURST_START_F2_SHIFT 16
3417 * Offset to the end of vertical colorburst, measured in one less than the
3418 * number of lines from the start of NBR.
3420 # define TV_VBURST_END_F2_MASK 0x000000ff
3421 # define TV_VBURST_END_F2_SHIFT 0
3423 #define TV_V_CTL_6 0x68050
3425 * Offset to start of vertical colorburst, measured in one less than the
3426 * number of lines from vertical start.
3428 # define TV_VBURST_START_F3_MASK 0x003f0000
3429 # define TV_VBURST_START_F3_SHIFT 16
3431 * Offset to the end of vertical colorburst, measured in one less than the
3432 * number of lines from the start of NBR.
3434 # define TV_VBURST_END_F3_MASK 0x000000ff
3435 # define TV_VBURST_END_F3_SHIFT 0
3437 #define TV_V_CTL_7 0x68054
3439 * Offset to start of vertical colorburst, measured in one less than the
3440 * number of lines from vertical start.
3442 # define TV_VBURST_START_F4_MASK 0x003f0000
3443 # define TV_VBURST_START_F4_SHIFT 16
3445 * Offset to the end of vertical colorburst, measured in one less than the
3446 * number of lines from the start of NBR.
3448 # define TV_VBURST_END_F4_MASK 0x000000ff
3449 # define TV_VBURST_END_F4_SHIFT 0
3451 #define TV_SC_CTL_1 0x68060
3452 /* Turns on the first subcarrier phase generation DDA */
3453 # define TV_SC_DDA1_EN (1 << 31)
3454 /* Turns on the first subcarrier phase generation DDA */
3455 # define TV_SC_DDA2_EN (1 << 30)
3456 /* Turns on the first subcarrier phase generation DDA */
3457 # define TV_SC_DDA3_EN (1 << 29)
3458 /* Sets the subcarrier DDA to reset frequency every other field */
3459 # define TV_SC_RESET_EVERY_2 (0 << 24)
3460 /* Sets the subcarrier DDA to reset frequency every fourth field */
3461 # define TV_SC_RESET_EVERY_4 (1 << 24)
3462 /* Sets the subcarrier DDA to reset frequency every eighth field */
3463 # define TV_SC_RESET_EVERY_8 (2 << 24)
3464 /* Sets the subcarrier DDA to never reset the frequency */
3465 # define TV_SC_RESET_NEVER (3 << 24)
3466 /* Sets the peak amplitude of the colorburst.*/
3467 # define TV_BURST_LEVEL_MASK 0x00ff0000
3468 # define TV_BURST_LEVEL_SHIFT 16
3469 /* Sets the increment of the first subcarrier phase generation DDA */
3470 # define TV_SCDDA1_INC_MASK 0x00000fff
3471 # define TV_SCDDA1_INC_SHIFT 0
3473 #define TV_SC_CTL_2 0x68064
3474 /* Sets the rollover for the second subcarrier phase generation DDA */
3475 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
3476 # define TV_SCDDA2_SIZE_SHIFT 16
3477 /* Sets the increent of the second subcarrier phase generation DDA */
3478 # define TV_SCDDA2_INC_MASK 0x00007fff
3479 # define TV_SCDDA2_INC_SHIFT 0
3481 #define TV_SC_CTL_3 0x68068
3482 /* Sets the rollover for the third subcarrier phase generation DDA */
3483 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
3484 # define TV_SCDDA3_SIZE_SHIFT 16
3485 /* Sets the increent of the third subcarrier phase generation DDA */
3486 # define TV_SCDDA3_INC_MASK 0x00007fff
3487 # define TV_SCDDA3_INC_SHIFT 0
3489 #define TV_WIN_POS 0x68070
3490 /* X coordinate of the display from the start of horizontal active */
3491 # define TV_XPOS_MASK 0x1fff0000
3492 # define TV_XPOS_SHIFT 16
3493 /* Y coordinate of the display from the start of vertical active (NBR) */
3494 # define TV_YPOS_MASK 0x00000fff
3495 # define TV_YPOS_SHIFT 0
3497 #define TV_WIN_SIZE 0x68074
3498 /* Horizontal size of the display window, measured in pixels*/
3499 # define TV_XSIZE_MASK 0x1fff0000
3500 # define TV_XSIZE_SHIFT 16
3502 * Vertical size of the display window, measured in pixels.
3504 * Must be even for interlaced modes.
3506 # define TV_YSIZE_MASK 0x00000fff
3507 # define TV_YSIZE_SHIFT 0
3509 #define TV_FILTER_CTL_1 0x68080
3511 * Enables automatic scaling calculation.
3513 * If set, the rest of the registers are ignored, and the calculated values can
3514 * be read back from the register.
3516 # define TV_AUTO_SCALE (1 << 31)
3518 * Disables the vertical filter.
3520 * This is required on modes more than 1024 pixels wide */
3521 # define TV_V_FILTER_BYPASS (1 << 29)
3522 /* Enables adaptive vertical filtering */
3523 # define TV_VADAPT (1 << 28)
3524 # define TV_VADAPT_MODE_MASK (3 << 26)
3525 /* Selects the least adaptive vertical filtering mode */
3526 # define TV_VADAPT_MODE_LEAST (0 << 26)
3527 /* Selects the moderately adaptive vertical filtering mode */
3528 # define TV_VADAPT_MODE_MODERATE (1 << 26)
3529 /* Selects the most adaptive vertical filtering mode */
3530 # define TV_VADAPT_MODE_MOST (3 << 26)
3532 * Sets the horizontal scaling factor.
3534 * This should be the fractional part of the horizontal scaling factor divided
3535 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
3537 * (src width - 1) / ((oversample * dest width) - 1)
3539 # define TV_HSCALE_FRAC_MASK 0x00003fff
3540 # define TV_HSCALE_FRAC_SHIFT 0
3542 #define TV_FILTER_CTL_2 0x68084
3544 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3546 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
3548 # define TV_VSCALE_INT_MASK 0x00038000
3549 # define TV_VSCALE_INT_SHIFT 15
3551 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3553 * \sa TV_VSCALE_INT_MASK
3555 # define TV_VSCALE_FRAC_MASK 0x00007fff
3556 # define TV_VSCALE_FRAC_SHIFT 0
3558 #define TV_FILTER_CTL_3 0x68088
3560 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3562 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
3564 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3566 # define TV_VSCALE_IP_INT_MASK 0x00038000
3567 # define TV_VSCALE_IP_INT_SHIFT 15
3569 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3571 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3573 * \sa TV_VSCALE_IP_INT_MASK
3575 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
3576 # define TV_VSCALE_IP_FRAC_SHIFT 0
3578 #define TV_CC_CONTROL 0x68090
3579 # define TV_CC_ENABLE (1 << 31)
3581 * Specifies which field to send the CC data in.
3583 * CC data is usually sent in field 0.
3585 # define TV_CC_FID_MASK (1 << 27)
3586 # define TV_CC_FID_SHIFT 27
3587 /* Sets the horizontal position of the CC data. Usually 135. */
3588 # define TV_CC_HOFF_MASK 0x03ff0000
3589 # define TV_CC_HOFF_SHIFT 16
3590 /* Sets the vertical position of the CC data. Usually 21 */
3591 # define TV_CC_LINE_MASK 0x0000003f
3592 # define TV_CC_LINE_SHIFT 0
3594 #define TV_CC_DATA 0x68094
3595 # define TV_CC_RDY (1 << 31)
3596 /* Second word of CC data to be transmitted. */
3597 # define TV_CC_DATA_2_MASK 0x007f0000
3598 # define TV_CC_DATA_2_SHIFT 16
3599 /* First word of CC data to be transmitted. */
3600 # define TV_CC_DATA_1_MASK 0x0000007f
3601 # define TV_CC_DATA_1_SHIFT 0
3603 #define TV_H_LUMA_0 0x68100
3604 #define TV_H_LUMA_59 0x681ec
3605 #define TV_H_CHROMA_0 0x68200
3606 #define TV_H_CHROMA_59 0x682ec
3607 #define TV_V_LUMA_0 0x68300
3608 #define TV_V_LUMA_42 0x683a8
3609 #define TV_V_CHROMA_0 0x68400
3610 #define TV_V_CHROMA_42 0x684a8
3613 #define DP_A 0x64000 /* eDP */
3614 #define DP_B 0x64100
3615 #define DP_C 0x64200
3616 #define DP_D 0x64300
3618 #define DP_PORT_EN (1 << 31)
3619 #define DP_PIPEB_SELECT (1 << 30)
3620 #define DP_PIPE_MASK (1 << 30)
3621 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
3622 #define DP_PIPE_MASK_CHV (3 << 16)
3624 /* Link training mode - select a suitable mode for each stage */
3625 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
3626 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
3627 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
3628 #define DP_LINK_TRAIN_OFF (3 << 28)
3629 #define DP_LINK_TRAIN_MASK (3 << 28)
3630 #define DP_LINK_TRAIN_SHIFT 28
3631 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
3632 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
3634 /* CPT Link training mode */
3635 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
3636 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
3637 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
3638 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
3639 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
3640 #define DP_LINK_TRAIN_SHIFT_CPT 8
3642 /* Signal voltages. These are mostly controlled by the other end */
3643 #define DP_VOLTAGE_0_4 (0 << 25)
3644 #define DP_VOLTAGE_0_6 (1 << 25)
3645 #define DP_VOLTAGE_0_8 (2 << 25)
3646 #define DP_VOLTAGE_1_2 (3 << 25)
3647 #define DP_VOLTAGE_MASK (7 << 25)
3648 #define DP_VOLTAGE_SHIFT 25
3650 /* Signal pre-emphasis levels, like voltages, the other end tells us what
3653 #define DP_PRE_EMPHASIS_0 (0 << 22)
3654 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
3655 #define DP_PRE_EMPHASIS_6 (2 << 22)
3656 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
3657 #define DP_PRE_EMPHASIS_MASK (7 << 22)
3658 #define DP_PRE_EMPHASIS_SHIFT 22
3660 /* How many wires to use. I guess 3 was too hard */
3661 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
3662 #define DP_PORT_WIDTH_MASK (7 << 19)
3664 /* Mystic DPCD version 1.1 special mode */
3665 #define DP_ENHANCED_FRAMING (1 << 18)
3668 #define DP_PLL_FREQ_270MHZ (0 << 16)
3669 #define DP_PLL_FREQ_160MHZ (1 << 16)
3670 #define DP_PLL_FREQ_MASK (3 << 16)
3672 /* locked once port is enabled */
3673 #define DP_PORT_REVERSAL (1 << 15)
3676 #define DP_PLL_ENABLE (1 << 14)
3678 /* sends the clock on lane 15 of the PEG for debug */
3679 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3681 #define DP_SCRAMBLING_DISABLE (1 << 12)
3682 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
3684 /* limit RGB values to avoid confusing TVs */
3685 #define DP_COLOR_RANGE_16_235 (1 << 8)
3687 /* Turn on the audio link */
3688 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3690 /* vs and hs sync polarity */
3691 #define DP_SYNC_VS_HIGH (1 << 4)
3692 #define DP_SYNC_HS_HIGH (1 << 3)
3695 #define DP_DETECTED (1 << 2)
3697 /* The aux channel provides a way to talk to the
3698 * signal sink for DDC etc. Max packet size supported
3699 * is 20 bytes in each direction, hence the 5 fixed
3702 #define DPA_AUX_CH_CTL 0x64010
3703 #define DPA_AUX_CH_DATA1 0x64014
3704 #define DPA_AUX_CH_DATA2 0x64018
3705 #define DPA_AUX_CH_DATA3 0x6401c
3706 #define DPA_AUX_CH_DATA4 0x64020
3707 #define DPA_AUX_CH_DATA5 0x64024
3709 #define DPB_AUX_CH_CTL 0x64110
3710 #define DPB_AUX_CH_DATA1 0x64114
3711 #define DPB_AUX_CH_DATA2 0x64118
3712 #define DPB_AUX_CH_DATA3 0x6411c
3713 #define DPB_AUX_CH_DATA4 0x64120
3714 #define DPB_AUX_CH_DATA5 0x64124
3716 #define DPC_AUX_CH_CTL 0x64210
3717 #define DPC_AUX_CH_DATA1 0x64214
3718 #define DPC_AUX_CH_DATA2 0x64218
3719 #define DPC_AUX_CH_DATA3 0x6421c
3720 #define DPC_AUX_CH_DATA4 0x64220
3721 #define DPC_AUX_CH_DATA5 0x64224
3723 #define DPD_AUX_CH_CTL 0x64310
3724 #define DPD_AUX_CH_DATA1 0x64314
3725 #define DPD_AUX_CH_DATA2 0x64318
3726 #define DPD_AUX_CH_DATA3 0x6431c
3727 #define DPD_AUX_CH_DATA4 0x64320
3728 #define DPD_AUX_CH_DATA5 0x64324
3730 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3731 #define DP_AUX_CH_CTL_DONE (1 << 30)
3732 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3733 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3734 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3735 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3736 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3737 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
3738 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3739 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3740 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3741 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3742 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3743 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3744 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3745 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3746 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3747 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3748 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3749 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3750 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3751 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
3754 * Computing GMCH M and N values for the Display Port link
3756 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
3758 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3760 * The GMCH value is used internally
3762 * bytes_per_pixel is the number of bytes coming out of the plane,
3763 * which is after the LUTs, so we want the bytes for our color format.
3764 * For our current usage, this is always 3, one byte for R, G and B.
3766 #define _PIPEA_DATA_M_G4X 0x70050
3767 #define _PIPEB_DATA_M_G4X 0x71050
3769 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
3770 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
3771 #define TU_SIZE_SHIFT 25
3772 #define TU_SIZE_MASK (0x3f << 25)
3774 #define DATA_LINK_M_N_MASK (0xffffff)
3775 #define DATA_LINK_N_MAX (0x800000)
3777 #define _PIPEA_DATA_N_G4X 0x70054
3778 #define _PIPEB_DATA_N_G4X 0x71054
3779 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
3782 * Computing Link M and N values for the Display Port link
3784 * Link M / N = pixel_clock / ls_clk
3786 * (the DP spec calls pixel_clock the 'strm_clk')
3788 * The Link value is transmitted in the Main Stream
3789 * Attributes and VB-ID.
3792 #define _PIPEA_LINK_M_G4X 0x70060
3793 #define _PIPEB_LINK_M_G4X 0x71060
3794 #define PIPEA_DP_LINK_M_MASK (0xffffff)
3796 #define _PIPEA_LINK_N_G4X 0x70064
3797 #define _PIPEB_LINK_N_G4X 0x71064
3798 #define PIPEA_DP_LINK_N_MASK (0xffffff)
3800 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3801 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3802 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3803 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
3805 /* Display & cursor control */
3808 #define _PIPEADSL 0x70000
3809 #define DSL_LINEMASK_GEN2 0x00000fff
3810 #define DSL_LINEMASK_GEN3 0x00001fff
3811 #define _PIPEACONF 0x70008
3812 #define PIPECONF_ENABLE (1<<31)
3813 #define PIPECONF_DISABLE 0
3814 #define PIPECONF_DOUBLE_WIDE (1<<30)
3815 #define I965_PIPECONF_ACTIVE (1<<30)
3816 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
3817 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
3818 #define PIPECONF_SINGLE_WIDE 0
3819 #define PIPECONF_PIPE_UNLOCKED 0
3820 #define PIPECONF_PIPE_LOCKED (1<<25)
3821 #define PIPECONF_PALETTE 0
3822 #define PIPECONF_GAMMA (1<<24)
3823 #define PIPECONF_FORCE_BORDER (1<<25)
3824 #define PIPECONF_INTERLACE_MASK (7 << 21)
3825 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
3826 /* Note that pre-gen3 does not support interlaced display directly. Panel
3827 * fitting must be disabled on pre-ilk for interlaced. */
3828 #define PIPECONF_PROGRESSIVE (0 << 21)
3829 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
3830 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
3831 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
3832 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
3833 /* Ironlake and later have a complete new set of values for interlaced. PFIT
3834 * means panel fitter required, PF means progressive fetch, DBL means power
3835 * saving pixel doubling. */
3836 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
3837 #define PIPECONF_INTERLACED_ILK (3 << 21)
3838 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
3839 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
3840 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
3841 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
3842 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
3843 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
3844 #define PIPECONF_BPC_MASK (0x7 << 5)
3845 #define PIPECONF_8BPC (0<<5)
3846 #define PIPECONF_10BPC (1<<5)
3847 #define PIPECONF_6BPC (2<<5)
3848 #define PIPECONF_12BPC (3<<5)
3849 #define PIPECONF_DITHER_EN (1<<4)
3850 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3851 #define PIPECONF_DITHER_TYPE_SP (0<<2)
3852 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3853 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3854 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
3855 #define _PIPEASTAT 0x70024
3856 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
3857 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
3858 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
3859 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
3860 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
3861 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
3862 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
3863 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
3864 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
3865 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
3866 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
3867 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
3868 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3869 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3870 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
3871 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
3872 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
3873 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
3874 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
3875 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
3876 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
3877 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
3878 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
3879 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
3880 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
3881 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
3882 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
3883 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
3884 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
3885 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
3886 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
3887 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3888 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3889 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
3890 #define PIPE_A_PSR_STATUS_VLV (1UL<<6)
3891 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
3892 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
3893 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
3894 #define PIPE_B_PSR_STATUS_VLV (1UL<<3)
3895 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
3896 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
3897 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
3898 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
3899 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
3900 #define PIPE_HBLANK_INT_STATUS (1UL<<0)
3901 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3903 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
3904 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
3906 #define PIPE_A_OFFSET 0x70000
3907 #define PIPE_B_OFFSET 0x71000
3908 #define PIPE_C_OFFSET 0x72000
3909 #define CHV_PIPE_C_OFFSET 0x74000
3911 * There's actually no pipe EDP. Some pipe registers have
3912 * simply shifted from the pipe to the transcoder, while
3913 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
3914 * to access such registers in transcoder EDP.
3916 #define PIPE_EDP_OFFSET 0x7f000
3918 #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
3919 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
3920 dev_priv->info.display_mmio_offset)
3922 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
3923 #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
3924 #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
3925 #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
3926 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
3928 #define _PIPE_MISC_A 0x70030
3929 #define _PIPE_MISC_B 0x71030
3930 #define PIPEMISC_DITHER_BPC_MASK (7<<5)
3931 #define PIPEMISC_DITHER_8_BPC (0<<5)
3932 #define PIPEMISC_DITHER_10_BPC (1<<5)
3933 #define PIPEMISC_DITHER_6_BPC (2<<5)
3934 #define PIPEMISC_DITHER_12_BPC (3<<5)
3935 #define PIPEMISC_DITHER_ENABLE (1<<4)
3936 #define PIPEMISC_DITHER_TYPE_MASK (3<<2)
3937 #define PIPEMISC_DITHER_TYPE_SP (0<<2)
3938 #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
3940 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
3941 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
3942 #define PIPEB_HLINE_INT_EN (1<<28)
3943 #define PIPEB_VBLANK_INT_EN (1<<27)
3944 #define SPRITED_FLIP_DONE_INT_EN (1<<26)
3945 #define SPRITEC_FLIP_DONE_INT_EN (1<<25)
3946 #define PLANEB_FLIP_DONE_INT_EN (1<<24)
3947 #define PIPE_PSR_INT_EN (1<<22)
3948 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
3949 #define PIPEA_HLINE_INT_EN (1<<20)
3950 #define PIPEA_VBLANK_INT_EN (1<<19)
3951 #define SPRITEB_FLIP_DONE_INT_EN (1<<18)
3952 #define SPRITEA_FLIP_DONE_INT_EN (1<<17)
3953 #define PLANEA_FLIPDONE_INT_EN (1<<16)
3954 #define PIPEC_LINE_COMPARE_INT_EN (1<<13)
3955 #define PIPEC_HLINE_INT_EN (1<<12)
3956 #define PIPEC_VBLANK_INT_EN (1<<11)
3957 #define SPRITEF_FLIPDONE_INT_EN (1<<10)
3958 #define SPRITEE_FLIPDONE_INT_EN (1<<9)
3959 #define PLANEC_FLIPDONE_INT_EN (1<<8)
3961 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
3962 #define SPRITEF_INVALID_GTT_INT_EN (1<<27)
3963 #define SPRITEE_INVALID_GTT_INT_EN (1<<26)
3964 #define PLANEC_INVALID_GTT_INT_EN (1<<25)
3965 #define CURSORC_INVALID_GTT_INT_EN (1<<24)
3966 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
3967 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
3968 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
3969 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
3970 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
3971 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
3972 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
3973 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
3974 #define DPINVGTT_EN_MASK 0xff0000
3975 #define DPINVGTT_EN_MASK_CHV 0xfff0000
3976 #define SPRITEF_INVALID_GTT_STATUS (1<<11)
3977 #define SPRITEE_INVALID_GTT_STATUS (1<<10)
3978 #define PLANEC_INVALID_GTT_STATUS (1<<9)
3979 #define CURSORC_INVALID_GTT_STATUS (1<<8)
3980 #define CURSORB_INVALID_GTT_STATUS (1<<7)
3981 #define CURSORA_INVALID_GTT_STATUS (1<<6)
3982 #define SPRITED_INVALID_GTT_STATUS (1<<5)
3983 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
3984 #define PLANEB_INVALID_GTT_STATUS (1<<3)
3985 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
3986 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
3987 #define PLANEA_INVALID_GTT_STATUS (1<<0)
3988 #define DPINVGTT_STATUS_MASK 0xff
3989 #define DPINVGTT_STATUS_MASK_CHV 0xfff
3991 #define DSPARB 0x70030
3992 #define DSPARB_CSTART_MASK (0x7f << 7)
3993 #define DSPARB_CSTART_SHIFT 7
3994 #define DSPARB_BSTART_MASK (0x7f)
3995 #define DSPARB_BSTART_SHIFT 0
3996 #define DSPARB_BEND_SHIFT 9 /* on 855 */
3997 #define DSPARB_AEND_SHIFT 0
3999 /* pnv/gen4/g4x/vlv/chv */
4000 #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
4001 #define DSPFW_SR_SHIFT 23
4002 #define DSPFW_SR_MASK (0x1ff<<23)
4003 #define DSPFW_CURSORB_SHIFT 16
4004 #define DSPFW_CURSORB_MASK (0x3f<<16)
4005 #define DSPFW_PLANEB_SHIFT 8
4006 #define DSPFW_PLANEB_MASK (0x7f<<8)
4007 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
4008 #define DSPFW_PLANEA_SHIFT 0
4009 #define DSPFW_PLANEA_MASK (0x7f<<0)
4010 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
4011 #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
4012 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */
4013 #define DSPFW_FBC_SR_SHIFT 28
4014 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
4015 #define DSPFW_FBC_HPLL_SR_SHIFT 24
4016 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
4017 #define DSPFW_SPRITEB_SHIFT (16)
4018 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
4019 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
4020 #define DSPFW_CURSORA_SHIFT 8
4021 #define DSPFW_CURSORA_MASK (0x3f<<8)
4022 #define DSPFW_PLANEC_SHIFT_OLD 0
4023 #define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */
4024 #define DSPFW_SPRITEA_SHIFT 0
4025 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
4026 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
4027 #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
4028 #define DSPFW_HPLL_SR_EN (1<<31)
4029 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
4030 #define DSPFW_CURSOR_SR_SHIFT 24
4031 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
4032 #define DSPFW_HPLL_CURSOR_SHIFT 16
4033 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
4034 #define DSPFW_HPLL_SR_SHIFT 0
4035 #define DSPFW_HPLL_SR_MASK (0x1ff<<0)
4038 #define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)
4039 #define DSPFW_SPRITEB_WM1_SHIFT 16
4040 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
4041 #define DSPFW_CURSORA_WM1_SHIFT 8
4042 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
4043 #define DSPFW_SPRITEA_WM1_SHIFT 0
4044 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
4045 #define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)
4046 #define DSPFW_PLANEB_WM1_SHIFT 24
4047 #define DSPFW_PLANEB_WM1_MASK (0xff<<24)
4048 #define DSPFW_PLANEA_WM1_SHIFT 16
4049 #define DSPFW_PLANEA_WM1_MASK (0xff<<16)
4050 #define DSPFW_CURSORB_WM1_SHIFT 8
4051 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
4052 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
4053 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
4054 #define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)
4055 #define DSPFW_SR_WM1_SHIFT 0
4056 #define DSPFW_SR_WM1_MASK (0x1ff<<0)
4057 #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)
4058 #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
4059 #define DSPFW_SPRITED_WM1_SHIFT 24
4060 #define DSPFW_SPRITED_WM1_MASK (0xff<<24)
4061 #define DSPFW_SPRITED_SHIFT 16
4062 #define DSPFW_SPRITED_MASK (0xff<<16)
4063 #define DSPFW_SPRITEC_WM1_SHIFT 8
4064 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
4065 #define DSPFW_SPRITEC_SHIFT 0
4066 #define DSPFW_SPRITEC_MASK (0xff<<0)
4067 #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8)
4068 #define DSPFW_SPRITEF_WM1_SHIFT 24
4069 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
4070 #define DSPFW_SPRITEF_SHIFT 16
4071 #define DSPFW_SPRITEF_MASK (0xff<<16)
4072 #define DSPFW_SPRITEE_WM1_SHIFT 8
4073 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
4074 #define DSPFW_SPRITEE_SHIFT 0
4075 #define DSPFW_SPRITEE_MASK (0xff<<0)
4076 #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
4077 #define DSPFW_PLANEC_WM1_SHIFT 24
4078 #define DSPFW_PLANEC_WM1_MASK (0xff<<24)
4079 #define DSPFW_PLANEC_SHIFT 16
4080 #define DSPFW_PLANEC_MASK (0xff<<16)
4081 #define DSPFW_CURSORC_WM1_SHIFT 8
4082 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
4083 #define DSPFW_CURSORC_SHIFT 0
4084 #define DSPFW_CURSORC_MASK (0x3f<<0)
4086 /* vlv/chv high order bits */
4087 #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064)
4088 #define DSPFW_SR_HI_SHIFT 24
4089 #define DSPFW_SR_HI_MASK (1<<24)
4090 #define DSPFW_SPRITEF_HI_SHIFT 23
4091 #define DSPFW_SPRITEF_HI_MASK (1<<23)
4092 #define DSPFW_SPRITEE_HI_SHIFT 22
4093 #define DSPFW_SPRITEE_HI_MASK (1<<22)
4094 #define DSPFW_PLANEC_HI_SHIFT 21
4095 #define DSPFW_PLANEC_HI_MASK (1<<21)
4096 #define DSPFW_SPRITED_HI_SHIFT 20
4097 #define DSPFW_SPRITED_HI_MASK (1<<20)
4098 #define DSPFW_SPRITEC_HI_SHIFT 16
4099 #define DSPFW_SPRITEC_HI_MASK (1<<16)
4100 #define DSPFW_PLANEB_HI_SHIFT 12
4101 #define DSPFW_PLANEB_HI_MASK (1<<12)
4102 #define DSPFW_SPRITEB_HI_SHIFT 8
4103 #define DSPFW_SPRITEB_HI_MASK (1<<8)
4104 #define DSPFW_SPRITEA_HI_SHIFT 4
4105 #define DSPFW_SPRITEA_HI_MASK (1<<4)
4106 #define DSPFW_PLANEA_HI_SHIFT 0
4107 #define DSPFW_PLANEA_HI_MASK (1<<0)
4108 #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068)
4109 #define DSPFW_SR_WM1_HI_SHIFT 24
4110 #define DSPFW_SR_WM1_HI_MASK (1<<24)
4111 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
4112 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
4113 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
4114 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
4115 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
4116 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
4117 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
4118 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
4119 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
4120 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
4121 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
4122 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
4123 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
4124 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
4125 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
4126 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
4127 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
4128 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
4130 /* drain latency register values*/
4131 #define DRAIN_LATENCY_PRECISION_16 16
4132 #define DRAIN_LATENCY_PRECISION_32 32
4133 #define DRAIN_LATENCY_PRECISION_64 64
4134 #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
4135 #define DDL_CURSOR_PRECISION_HIGH (1<<31)
4136 #define DDL_CURSOR_PRECISION_LOW (0<<31)
4137 #define DDL_CURSOR_SHIFT 24
4138 #define DDL_SPRITE_PRECISION_HIGH(sprite) (1<<(15+8*(sprite)))
4139 #define DDL_SPRITE_PRECISION_LOW(sprite) (0<<(15+8*(sprite)))
4140 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
4141 #define DDL_PLANE_PRECISION_HIGH (1<<7)
4142 #define DDL_PLANE_PRECISION_LOW (0<<7)
4143 #define DDL_PLANE_SHIFT 0
4144 #define DRAIN_LATENCY_MASK 0x7f
4146 /* FIFO watermark sizes etc */
4147 #define G4X_FIFO_LINE_SIZE 64
4148 #define I915_FIFO_LINE_SIZE 64
4149 #define I830_FIFO_LINE_SIZE 32
4151 #define VALLEYVIEW_FIFO_SIZE 255
4152 #define G4X_FIFO_SIZE 127
4153 #define I965_FIFO_SIZE 512
4154 #define I945_FIFO_SIZE 127
4155 #define I915_FIFO_SIZE 95
4156 #define I855GM_FIFO_SIZE 127 /* In cachelines */
4157 #define I830_FIFO_SIZE 95
4159 #define VALLEYVIEW_MAX_WM 0xff
4160 #define G4X_MAX_WM 0x3f
4161 #define I915_MAX_WM 0x3f
4163 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
4164 #define PINEVIEW_FIFO_LINE_SIZE 64
4165 #define PINEVIEW_MAX_WM 0x1ff
4166 #define PINEVIEW_DFT_WM 0x3f
4167 #define PINEVIEW_DFT_HPLLOFF_WM 0
4168 #define PINEVIEW_GUARD_WM 10
4169 #define PINEVIEW_CURSOR_FIFO 64
4170 #define PINEVIEW_CURSOR_MAX_WM 0x3f
4171 #define PINEVIEW_CURSOR_DFT_WM 0
4172 #define PINEVIEW_CURSOR_GUARD_WM 5
4174 #define VALLEYVIEW_CURSOR_MAX_WM 64
4175 #define I965_CURSOR_FIFO 64
4176 #define I965_CURSOR_MAX_WM 32
4177 #define I965_CURSOR_DFT_WM 8
4179 /* Watermark register definitions for SKL */
4180 #define CUR_WM_A_0 0x70140
4181 #define CUR_WM_B_0 0x71140
4182 #define PLANE_WM_1_A_0 0x70240
4183 #define PLANE_WM_1_B_0 0x71240
4184 #define PLANE_WM_2_A_0 0x70340
4185 #define PLANE_WM_2_B_0 0x71340
4186 #define PLANE_WM_TRANS_1_A_0 0x70268
4187 #define PLANE_WM_TRANS_1_B_0 0x71268
4188 #define PLANE_WM_TRANS_2_A_0 0x70368
4189 #define PLANE_WM_TRANS_2_B_0 0x71368
4190 #define CUR_WM_TRANS_A_0 0x70168
4191 #define CUR_WM_TRANS_B_0 0x71168
4192 #define PLANE_WM_EN (1 << 31)
4193 #define PLANE_WM_LINES_SHIFT 14
4194 #define PLANE_WM_LINES_MASK 0x1f
4195 #define PLANE_WM_BLOCKS_MASK 0x3ff
4197 #define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0)
4198 #define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level)))
4199 #define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0)
4201 #define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0)
4202 #define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0)
4203 #define _PLANE_WM_BASE(pipe, plane) \
4204 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4205 #define PLANE_WM(pipe, plane, level) \
4206 (_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4207 #define _PLANE_WM_TRANS_1(pipe) \
4208 _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)
4209 #define _PLANE_WM_TRANS_2(pipe) \
4210 _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0)
4211 #define PLANE_WM_TRANS(pipe, plane) \
4212 _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
4214 /* define the Watermark register on Ironlake */
4215 #define WM0_PIPEA_ILK 0x45100
4216 #define WM0_PIPE_PLANE_MASK (0xffff<<16)
4217 #define WM0_PIPE_PLANE_SHIFT 16
4218 #define WM0_PIPE_SPRITE_MASK (0xff<<8)
4219 #define WM0_PIPE_SPRITE_SHIFT 8
4220 #define WM0_PIPE_CURSOR_MASK (0xff)
4222 #define WM0_PIPEB_ILK 0x45104
4223 #define WM0_PIPEC_IVB 0x45200
4224 #define WM1_LP_ILK 0x45108
4225 #define WM1_LP_SR_EN (1<<31)
4226 #define WM1_LP_LATENCY_SHIFT 24
4227 #define WM1_LP_LATENCY_MASK (0x7f<<24)
4228 #define WM1_LP_FBC_MASK (0xf<<20)
4229 #define WM1_LP_FBC_SHIFT 20
4230 #define WM1_LP_FBC_SHIFT_BDW 19
4231 #define WM1_LP_SR_MASK (0x7ff<<8)
4232 #define WM1_LP_SR_SHIFT 8
4233 #define WM1_LP_CURSOR_MASK (0xff)
4234 #define WM2_LP_ILK 0x4510c
4235 #define WM2_LP_EN (1<<31)
4236 #define WM3_LP_ILK 0x45110
4237 #define WM3_LP_EN (1<<31)
4238 #define WM1S_LP_ILK 0x45120
4239 #define WM2S_LP_IVB 0x45124
4240 #define WM3S_LP_IVB 0x45128
4241 #define WM1S_LP_EN (1<<31)
4243 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
4244 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
4245 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
4247 /* Memory latency timer register */
4248 #define MLTR_ILK 0x11222
4249 #define MLTR_WM1_SHIFT 0
4250 #define MLTR_WM2_SHIFT 8
4251 /* the unit of memory self-refresh latency time is 0.5us */
4252 #define ILK_SRLT_MASK 0x3f
4255 /* the address where we get all kinds of latency value */
4256 #define SSKPD 0x5d10
4257 #define SSKPD_WM_MASK 0x3f
4258 #define SSKPD_WM0_SHIFT 0
4259 #define SSKPD_WM1_SHIFT 8
4260 #define SSKPD_WM2_SHIFT 16
4261 #define SSKPD_WM3_SHIFT 24
4264 * The two pipe frame counter registers are not synchronized, so
4265 * reading a stable value is somewhat tricky. The following code
4269 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4270 * PIPE_FRAME_HIGH_SHIFT;
4271 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4272 * PIPE_FRAME_LOW_SHIFT);
4273 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4274 * PIPE_FRAME_HIGH_SHIFT);
4275 * } while (high1 != high2);
4276 * frame = (high1 << 8) | low1;
4278 #define _PIPEAFRAMEHIGH 0x70040
4279 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
4280 #define PIPE_FRAME_HIGH_SHIFT 0
4281 #define _PIPEAFRAMEPIXEL 0x70044
4282 #define PIPE_FRAME_LOW_MASK 0xff000000
4283 #define PIPE_FRAME_LOW_SHIFT 24
4284 #define PIPE_PIXEL_MASK 0x00ffffff
4285 #define PIPE_PIXEL_SHIFT 0
4286 /* GM45+ just has to be different */
4287 #define _PIPEA_FRMCOUNT_GM45 0x70040
4288 #define _PIPEA_FLIPCOUNT_GM45 0x70044
4289 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
4290 #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
4292 /* Cursor A & B regs */
4293 #define _CURACNTR 0x70080
4294 /* Old style CUR*CNTR flags (desktop 8xx) */
4295 #define CURSOR_ENABLE 0x80000000
4296 #define CURSOR_GAMMA_ENABLE 0x40000000
4297 #define CURSOR_STRIDE_SHIFT 28
4298 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
4299 #define CURSOR_PIPE_CSC_ENABLE (1<<24)
4300 #define CURSOR_FORMAT_SHIFT 24
4301 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
4302 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
4303 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
4304 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
4305 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
4306 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
4307 /* New style CUR*CNTR flags */
4308 #define CURSOR_MODE 0x27
4309 #define CURSOR_MODE_DISABLE 0x00
4310 #define CURSOR_MODE_128_32B_AX 0x02
4311 #define CURSOR_MODE_256_32B_AX 0x03
4312 #define CURSOR_MODE_64_32B_AX 0x07
4313 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
4314 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
4315 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
4316 #define MCURSOR_PIPE_SELECT (1 << 28)
4317 #define MCURSOR_PIPE_A 0x00
4318 #define MCURSOR_PIPE_B (1 << 28)
4319 #define MCURSOR_GAMMA_ENABLE (1 << 26)
4320 #define CURSOR_ROTATE_180 (1<<15)
4321 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
4322 #define _CURABASE 0x70084
4323 #define _CURAPOS 0x70088
4324 #define CURSOR_POS_MASK 0x007FF
4325 #define CURSOR_POS_SIGN 0x8000
4326 #define CURSOR_X_SHIFT 0
4327 #define CURSOR_Y_SHIFT 16
4328 #define CURSIZE 0x700a0
4329 #define _CURBCNTR 0x700c0
4330 #define _CURBBASE 0x700c4
4331 #define _CURBPOS 0x700c8
4333 #define _CURBCNTR_IVB 0x71080
4334 #define _CURBBASE_IVB 0x71084
4335 #define _CURBPOS_IVB 0x71088
4337 #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4338 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4339 dev_priv->info.display_mmio_offset)
4341 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4342 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4343 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4345 #define CURSOR_A_OFFSET 0x70080
4346 #define CURSOR_B_OFFSET 0x700c0
4347 #define CHV_CURSOR_C_OFFSET 0x700e0
4348 #define IVB_CURSOR_B_OFFSET 0x71080
4349 #define IVB_CURSOR_C_OFFSET 0x72080
4351 /* Display A control */
4352 #define _DSPACNTR 0x70180
4353 #define DISPLAY_PLANE_ENABLE (1<<31)
4354 #define DISPLAY_PLANE_DISABLE 0
4355 #define DISPPLANE_GAMMA_ENABLE (1<<30)
4356 #define DISPPLANE_GAMMA_DISABLE 0
4357 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
4358 #define DISPPLANE_YUV422 (0x0<<26)
4359 #define DISPPLANE_8BPP (0x2<<26)
4360 #define DISPPLANE_BGRA555 (0x3<<26)
4361 #define DISPPLANE_BGRX555 (0x4<<26)
4362 #define DISPPLANE_BGRX565 (0x5<<26)
4363 #define DISPPLANE_BGRX888 (0x6<<26)
4364 #define DISPPLANE_BGRA888 (0x7<<26)
4365 #define DISPPLANE_RGBX101010 (0x8<<26)
4366 #define DISPPLANE_RGBA101010 (0x9<<26)
4367 #define DISPPLANE_BGRX101010 (0xa<<26)
4368 #define DISPPLANE_RGBX161616 (0xc<<26)
4369 #define DISPPLANE_RGBX888 (0xe<<26)
4370 #define DISPPLANE_RGBA888 (0xf<<26)
4371 #define DISPPLANE_STEREO_ENABLE (1<<25)
4372 #define DISPPLANE_STEREO_DISABLE 0
4373 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
4374 #define DISPPLANE_SEL_PIPE_SHIFT 24
4375 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
4376 #define DISPPLANE_SEL_PIPE_A 0
4377 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
4378 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
4379 #define DISPPLANE_SRC_KEY_DISABLE 0
4380 #define DISPPLANE_LINE_DOUBLE (1<<20)
4381 #define DISPPLANE_NO_LINE_DOUBLE 0
4382 #define DISPPLANE_STEREO_POLARITY_FIRST 0
4383 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
4384 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
4385 #define DISPPLANE_ROTATE_180 (1<<15)
4386 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
4387 #define DISPPLANE_TILED (1<<10)
4388 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
4389 #define _DSPAADDR 0x70184
4390 #define _DSPASTRIDE 0x70188
4391 #define _DSPAPOS 0x7018C /* reserved */
4392 #define _DSPASIZE 0x70190
4393 #define _DSPASURF 0x7019C /* 965+ only */
4394 #define _DSPATILEOFF 0x701A4 /* 965+ only */
4395 #define _DSPAOFFSET 0x701A4 /* HSW */
4396 #define _DSPASURFLIVE 0x701AC
4398 #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
4399 #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
4400 #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
4401 #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
4402 #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
4403 #define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
4404 #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
4405 #define DSPLINOFF(plane) DSPADDR(plane)
4406 #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
4407 #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
4409 /* CHV pipe B blender and primary plane */
4410 #define _CHV_BLEND_A 0x60a00
4411 #define CHV_BLEND_LEGACY (0<<30)
4412 #define CHV_BLEND_ANDROID (1<<30)
4413 #define CHV_BLEND_MPO (2<<30)
4414 #define CHV_BLEND_MASK (3<<30)
4415 #define _CHV_CANVAS_A 0x60a04
4416 #define _PRIMPOS_A 0x60a08
4417 #define _PRIMSIZE_A 0x60a0c
4418 #define _PRIMCNSTALPHA_A 0x60a10
4419 #define PRIM_CONST_ALPHA_ENABLE (1<<31)
4421 #define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
4422 #define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
4423 #define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
4424 #define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
4425 #define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
4427 /* Display/Sprite base address macros */
4428 #define DISP_BASEADDR_MASK (0xfffff000)
4429 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
4430 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
4433 #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
4434 #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
4435 #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
4436 #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
4437 #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
4438 #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
4439 #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
4440 #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
4441 #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
4442 #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
4443 #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
4444 #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
4445 #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
4448 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
4449 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
4450 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
4451 #define _PIPEBFRAMEHIGH 0x71040
4452 #define _PIPEBFRAMEPIXEL 0x71044
4453 #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
4454 #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
4457 /* Display B control */
4458 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
4459 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
4460 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
4461 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
4462 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
4463 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
4464 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
4465 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
4466 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
4467 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
4468 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
4469 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
4470 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
4472 /* Sprite A control */
4473 #define _DVSACNTR 0x72180
4474 #define DVS_ENABLE (1<<31)
4475 #define DVS_GAMMA_ENABLE (1<<30)
4476 #define DVS_PIXFORMAT_MASK (3<<25)
4477 #define DVS_FORMAT_YUV422 (0<<25)
4478 #define DVS_FORMAT_RGBX101010 (1<<25)
4479 #define DVS_FORMAT_RGBX888 (2<<25)
4480 #define DVS_FORMAT_RGBX161616 (3<<25)
4481 #define DVS_PIPE_CSC_ENABLE (1<<24)
4482 #define DVS_SOURCE_KEY (1<<22)
4483 #define DVS_RGB_ORDER_XBGR (1<<20)
4484 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
4485 #define DVS_YUV_ORDER_YUYV (0<<16)
4486 #define DVS_YUV_ORDER_UYVY (1<<16)
4487 #define DVS_YUV_ORDER_YVYU (2<<16)
4488 #define DVS_YUV_ORDER_VYUY (3<<16)
4489 #define DVS_ROTATE_180 (1<<15)
4490 #define DVS_DEST_KEY (1<<2)
4491 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
4492 #define DVS_TILED (1<<10)
4493 #define _DVSALINOFF 0x72184
4494 #define _DVSASTRIDE 0x72188
4495 #define _DVSAPOS 0x7218c
4496 #define _DVSASIZE 0x72190
4497 #define _DVSAKEYVAL 0x72194
4498 #define _DVSAKEYMSK 0x72198
4499 #define _DVSASURF 0x7219c
4500 #define _DVSAKEYMAXVAL 0x721a0
4501 #define _DVSATILEOFF 0x721a4
4502 #define _DVSASURFLIVE 0x721ac
4503 #define _DVSASCALE 0x72204
4504 #define DVS_SCALE_ENABLE (1<<31)
4505 #define DVS_FILTER_MASK (3<<29)
4506 #define DVS_FILTER_MEDIUM (0<<29)
4507 #define DVS_FILTER_ENHANCING (1<<29)
4508 #define DVS_FILTER_SOFTENING (2<<29)
4509 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4510 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
4511 #define _DVSAGAMC 0x72300
4513 #define _DVSBCNTR 0x73180
4514 #define _DVSBLINOFF 0x73184
4515 #define _DVSBSTRIDE 0x73188
4516 #define _DVSBPOS 0x7318c
4517 #define _DVSBSIZE 0x73190
4518 #define _DVSBKEYVAL 0x73194
4519 #define _DVSBKEYMSK 0x73198
4520 #define _DVSBSURF 0x7319c
4521 #define _DVSBKEYMAXVAL 0x731a0
4522 #define _DVSBTILEOFF 0x731a4
4523 #define _DVSBSURFLIVE 0x731ac
4524 #define _DVSBSCALE 0x73204
4525 #define _DVSBGAMC 0x73300
4527 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
4528 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
4529 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
4530 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
4531 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
4532 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
4533 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
4534 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
4535 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
4536 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
4537 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
4538 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
4540 #define _SPRA_CTL 0x70280
4541 #define SPRITE_ENABLE (1<<31)
4542 #define SPRITE_GAMMA_ENABLE (1<<30)
4543 #define SPRITE_PIXFORMAT_MASK (7<<25)
4544 #define SPRITE_FORMAT_YUV422 (0<<25)
4545 #define SPRITE_FORMAT_RGBX101010 (1<<25)
4546 #define SPRITE_FORMAT_RGBX888 (2<<25)
4547 #define SPRITE_FORMAT_RGBX161616 (3<<25)
4548 #define SPRITE_FORMAT_YUV444 (4<<25)
4549 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
4550 #define SPRITE_PIPE_CSC_ENABLE (1<<24)
4551 #define SPRITE_SOURCE_KEY (1<<22)
4552 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
4553 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
4554 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
4555 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
4556 #define SPRITE_YUV_ORDER_YUYV (0<<16)
4557 #define SPRITE_YUV_ORDER_UYVY (1<<16)
4558 #define SPRITE_YUV_ORDER_YVYU (2<<16)
4559 #define SPRITE_YUV_ORDER_VYUY (3<<16)
4560 #define SPRITE_ROTATE_180 (1<<15)
4561 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
4562 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
4563 #define SPRITE_TILED (1<<10)
4564 #define SPRITE_DEST_KEY (1<<2)
4565 #define _SPRA_LINOFF 0x70284
4566 #define _SPRA_STRIDE 0x70288
4567 #define _SPRA_POS 0x7028c
4568 #define _SPRA_SIZE 0x70290
4569 #define _SPRA_KEYVAL 0x70294
4570 #define _SPRA_KEYMSK 0x70298
4571 #define _SPRA_SURF 0x7029c
4572 #define _SPRA_KEYMAX 0x702a0
4573 #define _SPRA_TILEOFF 0x702a4
4574 #define _SPRA_OFFSET 0x702a4
4575 #define _SPRA_SURFLIVE 0x702ac
4576 #define _SPRA_SCALE 0x70304
4577 #define SPRITE_SCALE_ENABLE (1<<31)
4578 #define SPRITE_FILTER_MASK (3<<29)
4579 #define SPRITE_FILTER_MEDIUM (0<<29)
4580 #define SPRITE_FILTER_ENHANCING (1<<29)
4581 #define SPRITE_FILTER_SOFTENING (2<<29)
4582 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4583 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
4584 #define _SPRA_GAMC 0x70400
4586 #define _SPRB_CTL 0x71280
4587 #define _SPRB_LINOFF 0x71284
4588 #define _SPRB_STRIDE 0x71288
4589 #define _SPRB_POS 0x7128c
4590 #define _SPRB_SIZE 0x71290
4591 #define _SPRB_KEYVAL 0x71294
4592 #define _SPRB_KEYMSK 0x71298
4593 #define _SPRB_SURF 0x7129c
4594 #define _SPRB_KEYMAX 0x712a0
4595 #define _SPRB_TILEOFF 0x712a4
4596 #define _SPRB_OFFSET 0x712a4
4597 #define _SPRB_SURFLIVE 0x712ac
4598 #define _SPRB_SCALE 0x71304
4599 #define _SPRB_GAMC 0x71400
4601 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
4602 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
4603 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
4604 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
4605 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
4606 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
4607 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
4608 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
4609 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
4610 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
4611 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
4612 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
4613 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
4614 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
4616 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
4617 #define SP_ENABLE (1<<31)
4618 #define SP_GAMMA_ENABLE (1<<30)
4619 #define SP_PIXFORMAT_MASK (0xf<<26)
4620 #define SP_FORMAT_YUV422 (0<<26)
4621 #define SP_FORMAT_BGR565 (5<<26)
4622 #define SP_FORMAT_BGRX8888 (6<<26)
4623 #define SP_FORMAT_BGRA8888 (7<<26)
4624 #define SP_FORMAT_RGBX1010102 (8<<26)
4625 #define SP_FORMAT_RGBA1010102 (9<<26)
4626 #define SP_FORMAT_RGBX8888 (0xe<<26)
4627 #define SP_FORMAT_RGBA8888 (0xf<<26)
4628 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
4629 #define SP_SOURCE_KEY (1<<22)
4630 #define SP_YUV_BYTE_ORDER_MASK (3<<16)
4631 #define SP_YUV_ORDER_YUYV (0<<16)
4632 #define SP_YUV_ORDER_UYVY (1<<16)
4633 #define SP_YUV_ORDER_YVYU (2<<16)
4634 #define SP_YUV_ORDER_VYUY (3<<16)
4635 #define SP_ROTATE_180 (1<<15)
4636 #define SP_TILED (1<<10)
4637 #define SP_MIRROR (1<<8) /* CHV pipe B */
4638 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
4639 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
4640 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
4641 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
4642 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
4643 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
4644 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
4645 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
4646 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
4647 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
4648 #define SP_CONST_ALPHA_ENABLE (1<<31)
4649 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
4651 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
4652 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
4653 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
4654 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
4655 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
4656 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
4657 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
4658 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
4659 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
4660 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
4661 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
4662 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
4664 #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
4665 #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
4666 #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
4667 #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
4668 #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
4669 #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
4670 #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
4671 #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
4672 #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
4673 #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
4674 #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
4675 #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
4678 * CHV pipe B sprite CSC
4680 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
4681 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
4682 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
4684 #define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
4685 #define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
4686 #define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
4687 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
4688 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
4690 #define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
4691 #define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
4692 #define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
4693 #define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
4694 #define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
4695 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
4696 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
4698 #define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
4699 #define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
4700 #define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
4701 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
4702 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
4704 #define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
4705 #define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
4706 #define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
4707 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */
4708 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */
4710 /* Skylake plane registers */
4712 #define _PLANE_CTL_1_A 0x70180
4713 #define _PLANE_CTL_2_A 0x70280
4714 #define _PLANE_CTL_3_A 0x70380
4715 #define PLANE_CTL_ENABLE (1 << 31)
4716 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
4717 #define PLANE_CTL_FORMAT_MASK (0xf << 24)
4718 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
4719 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
4720 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
4721 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
4722 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
4723 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
4724 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
4725 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
4726 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
4727 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
4728 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
4729 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
4730 #define PLANE_CTL_ORDER_BGRX (0 << 20)
4731 #define PLANE_CTL_ORDER_RGBX (1 << 20)
4732 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
4733 #define PLANE_CTL_YUV422_YUYV ( 0 << 16)
4734 #define PLANE_CTL_YUV422_UYVY ( 1 << 16)
4735 #define PLANE_CTL_YUV422_YVYU ( 2 << 16)
4736 #define PLANE_CTL_YUV422_VYUY ( 3 << 16)
4737 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
4738 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
4739 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
4740 #define PLANE_CTL_TILED_MASK (0x7 << 10)
4741 #define PLANE_CTL_TILED_LINEAR ( 0 << 10)
4742 #define PLANE_CTL_TILED_X ( 1 << 10)
4743 #define PLANE_CTL_TILED_Y ( 4 << 10)
4744 #define PLANE_CTL_TILED_YF ( 5 << 10)
4745 #define PLANE_CTL_ALPHA_MASK (0x3 << 4)
4746 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
4747 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
4748 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
4749 #define PLANE_CTL_ROTATE_MASK 0x3
4750 #define PLANE_CTL_ROTATE_0 0x0
4751 #define PLANE_CTL_ROTATE_180 0x2
4752 #define _PLANE_STRIDE_1_A 0x70188
4753 #define _PLANE_STRIDE_2_A 0x70288
4754 #define _PLANE_STRIDE_3_A 0x70388
4755 #define _PLANE_POS_1_A 0x7018c
4756 #define _PLANE_POS_2_A 0x7028c
4757 #define _PLANE_POS_3_A 0x7038c
4758 #define _PLANE_SIZE_1_A 0x70190
4759 #define _PLANE_SIZE_2_A 0x70290
4760 #define _PLANE_SIZE_3_A 0x70390
4761 #define _PLANE_SURF_1_A 0x7019c
4762 #define _PLANE_SURF_2_A 0x7029c
4763 #define _PLANE_SURF_3_A 0x7039c
4764 #define _PLANE_OFFSET_1_A 0x701a4
4765 #define _PLANE_OFFSET_2_A 0x702a4
4766 #define _PLANE_OFFSET_3_A 0x703a4
4767 #define _PLANE_KEYVAL_1_A 0x70194
4768 #define _PLANE_KEYVAL_2_A 0x70294
4769 #define _PLANE_KEYMSK_1_A 0x70198
4770 #define _PLANE_KEYMSK_2_A 0x70298
4771 #define _PLANE_KEYMAX_1_A 0x701a0
4772 #define _PLANE_KEYMAX_2_A 0x702a0
4773 #define _PLANE_BUF_CFG_1_A 0x7027c
4774 #define _PLANE_BUF_CFG_2_A 0x7037c
4776 #define _PLANE_CTL_1_B 0x71180
4777 #define _PLANE_CTL_2_B 0x71280
4778 #define _PLANE_CTL_3_B 0x71380
4779 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
4780 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
4781 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
4782 #define PLANE_CTL(pipe, plane) \
4783 _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
4785 #define _PLANE_STRIDE_1_B 0x71188
4786 #define _PLANE_STRIDE_2_B 0x71288
4787 #define _PLANE_STRIDE_3_B 0x71388
4788 #define _PLANE_STRIDE_1(pipe) \
4789 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
4790 #define _PLANE_STRIDE_2(pipe) \
4791 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
4792 #define _PLANE_STRIDE_3(pipe) \
4793 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
4794 #define PLANE_STRIDE(pipe, plane) \
4795 _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
4797 #define _PLANE_POS_1_B 0x7118c
4798 #define _PLANE_POS_2_B 0x7128c
4799 #define _PLANE_POS_3_B 0x7138c
4800 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
4801 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
4802 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
4803 #define PLANE_POS(pipe, plane) \
4804 _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
4806 #define _PLANE_SIZE_1_B 0x71190
4807 #define _PLANE_SIZE_2_B 0x71290
4808 #define _PLANE_SIZE_3_B 0x71390
4809 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
4810 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
4811 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
4812 #define PLANE_SIZE(pipe, plane) \
4813 _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
4815 #define _PLANE_SURF_1_B 0x7119c
4816 #define _PLANE_SURF_2_B 0x7129c
4817 #define _PLANE_SURF_3_B 0x7139c
4818 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
4819 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
4820 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
4821 #define PLANE_SURF(pipe, plane) \
4822 _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
4824 #define _PLANE_OFFSET_1_B 0x711a4
4825 #define _PLANE_OFFSET_2_B 0x712a4
4826 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
4827 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
4828 #define PLANE_OFFSET(pipe, plane) \
4829 _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
4831 #define _PLANE_KEYVAL_1_B 0x71194
4832 #define _PLANE_KEYVAL_2_B 0x71294
4833 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
4834 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
4835 #define PLANE_KEYVAL(pipe, plane) \
4836 _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
4838 #define _PLANE_KEYMSK_1_B 0x71198
4839 #define _PLANE_KEYMSK_2_B 0x71298
4840 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
4841 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
4842 #define PLANE_KEYMSK(pipe, plane) \
4843 _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
4845 #define _PLANE_KEYMAX_1_B 0x711a0
4846 #define _PLANE_KEYMAX_2_B 0x712a0
4847 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
4848 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
4849 #define PLANE_KEYMAX(pipe, plane) \
4850 _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
4852 #define _PLANE_BUF_CFG_1_B 0x7127c
4853 #define _PLANE_BUF_CFG_2_B 0x7137c
4854 #define _PLANE_BUF_CFG_1(pipe) \
4855 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
4856 #define _PLANE_BUF_CFG_2(pipe) \
4857 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
4858 #define PLANE_BUF_CFG(pipe, plane) \
4859 _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
4861 /* SKL new cursor registers */
4862 #define _CUR_BUF_CFG_A 0x7017c
4863 #define _CUR_BUF_CFG_B 0x7117c
4864 #define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
4867 #define VGACNTRL 0x71400
4868 # define VGA_DISP_DISABLE (1 << 31)
4869 # define VGA_2X_MODE (1 << 30)
4870 # define VGA_PIPE_B_SELECT (1 << 29)
4872 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
4876 #define CPU_VGACNTRL 0x41000
4878 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
4879 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
4880 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
4881 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
4882 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
4883 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
4884 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
4885 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
4886 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
4888 /* refresh rate hardware control */
4889 #define RR_HW_CTL 0x45300
4890 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
4891 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
4893 #define FDI_PLL_BIOS_0 0x46000
4894 #define FDI_PLL_FB_CLOCK_MASK 0xff
4895 #define FDI_PLL_BIOS_1 0x46004
4896 #define FDI_PLL_BIOS_2 0x46008
4897 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
4898 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
4899 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
4901 #define PCH_3DCGDIS0 0x46020
4902 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
4903 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
4905 #define PCH_3DCGDIS1 0x46024
4906 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
4908 #define FDI_PLL_FREQ_CTL 0x46030
4909 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
4910 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
4911 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
4914 #define _PIPEA_DATA_M1 0x60030
4915 #define PIPE_DATA_M1_OFFSET 0
4916 #define _PIPEA_DATA_N1 0x60034
4917 #define PIPE_DATA_N1_OFFSET 0
4919 #define _PIPEA_DATA_M2 0x60038
4920 #define PIPE_DATA_M2_OFFSET 0
4921 #define _PIPEA_DATA_N2 0x6003c
4922 #define PIPE_DATA_N2_OFFSET 0
4924 #define _PIPEA_LINK_M1 0x60040
4925 #define PIPE_LINK_M1_OFFSET 0
4926 #define _PIPEA_LINK_N1 0x60044
4927 #define PIPE_LINK_N1_OFFSET 0
4929 #define _PIPEA_LINK_M2 0x60048
4930 #define PIPE_LINK_M2_OFFSET 0
4931 #define _PIPEA_LINK_N2 0x6004c
4932 #define PIPE_LINK_N2_OFFSET 0
4934 /* PIPEB timing regs are same start from 0x61000 */
4936 #define _PIPEB_DATA_M1 0x61030
4937 #define _PIPEB_DATA_N1 0x61034
4938 #define _PIPEB_DATA_M2 0x61038
4939 #define _PIPEB_DATA_N2 0x6103c
4940 #define _PIPEB_LINK_M1 0x61040
4941 #define _PIPEB_LINK_N1 0x61044
4942 #define _PIPEB_LINK_M2 0x61048
4943 #define _PIPEB_LINK_N2 0x6104c
4945 #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
4946 #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
4947 #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
4948 #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
4949 #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
4950 #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
4951 #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
4952 #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
4954 /* CPU panel fitter */
4955 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
4956 #define _PFA_CTL_1 0x68080
4957 #define _PFB_CTL_1 0x68880
4958 #define PF_ENABLE (1<<31)
4959 #define PF_PIPE_SEL_MASK_IVB (3<<29)
4960 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
4961 #define PF_FILTER_MASK (3<<23)
4962 #define PF_FILTER_PROGRAMMED (0<<23)
4963 #define PF_FILTER_MED_3x3 (1<<23)
4964 #define PF_FILTER_EDGE_ENHANCE (2<<23)
4965 #define PF_FILTER_EDGE_SOFTEN (3<<23)
4966 #define _PFA_WIN_SZ 0x68074
4967 #define _PFB_WIN_SZ 0x68874
4968 #define _PFA_WIN_POS 0x68070
4969 #define _PFB_WIN_POS 0x68870
4970 #define _PFA_VSCALE 0x68084
4971 #define _PFB_VSCALE 0x68884
4972 #define _PFA_HSCALE 0x68090
4973 #define _PFB_HSCALE 0x68890
4975 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
4976 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
4977 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
4978 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
4979 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
4981 #define _PSA_CTL 0x68180
4982 #define _PSB_CTL 0x68980
4983 #define PS_ENABLE (1<<31)
4984 #define _PSA_WIN_SZ 0x68174
4985 #define _PSB_WIN_SZ 0x68974
4986 #define _PSA_WIN_POS 0x68170
4987 #define _PSB_WIN_POS 0x68970
4989 #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL)
4990 #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
4991 #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
4993 /* legacy palette */
4994 #define _LGC_PALETTE_A 0x4a000
4995 #define _LGC_PALETTE_B 0x4a800
4996 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
4998 #define _GAMMA_MODE_A 0x4a480
4999 #define _GAMMA_MODE_B 0x4ac80
5000 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
5001 #define GAMMA_MODE_MODE_MASK (3 << 0)
5002 #define GAMMA_MODE_MODE_8BIT (0 << 0)
5003 #define GAMMA_MODE_MODE_10BIT (1 << 0)
5004 #define GAMMA_MODE_MODE_12BIT (2 << 0)
5005 #define GAMMA_MODE_MODE_SPLIT (3 << 0)
5008 #define DE_MASTER_IRQ_CONTROL (1 << 31)
5009 #define DE_SPRITEB_FLIP_DONE (1 << 29)
5010 #define DE_SPRITEA_FLIP_DONE (1 << 28)
5011 #define DE_PLANEB_FLIP_DONE (1 << 27)
5012 #define DE_PLANEA_FLIP_DONE (1 << 26)
5013 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
5014 #define DE_PCU_EVENT (1 << 25)
5015 #define DE_GTT_FAULT (1 << 24)
5016 #define DE_POISON (1 << 23)
5017 #define DE_PERFORM_COUNTER (1 << 22)
5018 #define DE_PCH_EVENT (1 << 21)
5019 #define DE_AUX_CHANNEL_A (1 << 20)
5020 #define DE_DP_A_HOTPLUG (1 << 19)
5021 #define DE_GSE (1 << 18)
5022 #define DE_PIPEB_VBLANK (1 << 15)
5023 #define DE_PIPEB_EVEN_FIELD (1 << 14)
5024 #define DE_PIPEB_ODD_FIELD (1 << 13)
5025 #define DE_PIPEB_LINE_COMPARE (1 << 12)
5026 #define DE_PIPEB_VSYNC (1 << 11)
5027 #define DE_PIPEB_CRC_DONE (1 << 10)
5028 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
5029 #define DE_PIPEA_VBLANK (1 << 7)
5030 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
5031 #define DE_PIPEA_EVEN_FIELD (1 << 6)
5032 #define DE_PIPEA_ODD_FIELD (1 << 5)
5033 #define DE_PIPEA_LINE_COMPARE (1 << 4)
5034 #define DE_PIPEA_VSYNC (1 << 3)
5035 #define DE_PIPEA_CRC_DONE (1 << 2)
5036 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
5037 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
5038 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
5040 /* More Ivybridge lolz */
5041 #define DE_ERR_INT_IVB (1<<30)
5042 #define DE_GSE_IVB (1<<29)
5043 #define DE_PCH_EVENT_IVB (1<<28)
5044 #define DE_DP_A_HOTPLUG_IVB (1<<27)
5045 #define DE_AUX_CHANNEL_A_IVB (1<<26)
5046 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
5047 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
5048 #define DE_PIPEC_VBLANK_IVB (1<<10)
5049 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
5050 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
5051 #define DE_PIPEB_VBLANK_IVB (1<<5)
5052 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
5053 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
5054 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
5055 #define DE_PIPEA_VBLANK_IVB (1<<0)
5056 #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
5058 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */
5059 #define MASTER_INTERRUPT_ENABLE (1<<31)
5061 #define DEISR 0x44000
5062 #define DEIMR 0x44004
5063 #define DEIIR 0x44008
5064 #define DEIER 0x4400c
5066 #define GTISR 0x44010
5067 #define GTIMR 0x44014
5068 #define GTIIR 0x44018
5069 #define GTIER 0x4401c
5071 #define GEN8_MASTER_IRQ 0x44200
5072 #define GEN8_MASTER_IRQ_CONTROL (1<<31)
5073 #define GEN8_PCU_IRQ (1<<30)
5074 #define GEN8_DE_PCH_IRQ (1<<23)
5075 #define GEN8_DE_MISC_IRQ (1<<22)
5076 #define GEN8_DE_PORT_IRQ (1<<20)
5077 #define GEN8_DE_PIPE_C_IRQ (1<<18)
5078 #define GEN8_DE_PIPE_B_IRQ (1<<17)
5079 #define GEN8_DE_PIPE_A_IRQ (1<<16)
5080 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
5081 #define GEN8_GT_VECS_IRQ (1<<6)
5082 #define GEN8_GT_PM_IRQ (1<<4)
5083 #define GEN8_GT_VCS2_IRQ (1<<3)
5084 #define GEN8_GT_VCS1_IRQ (1<<2)
5085 #define GEN8_GT_BCS_IRQ (1<<1)
5086 #define GEN8_GT_RCS_IRQ (1<<0)
5088 #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
5089 #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
5090 #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
5091 #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
5093 #define GEN8_BCS_IRQ_SHIFT 16
5094 #define GEN8_RCS_IRQ_SHIFT 0
5095 #define GEN8_VCS2_IRQ_SHIFT 16
5096 #define GEN8_VCS1_IRQ_SHIFT 0
5097 #define GEN8_VECS_IRQ_SHIFT 0
5099 #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
5100 #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
5101 #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
5102 #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
5103 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
5104 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
5105 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
5106 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
5107 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
5108 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
5109 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
5110 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
5111 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
5112 #define GEN8_PIPE_VSYNC (1 << 1)
5113 #define GEN8_PIPE_VBLANK (1 << 0)
5114 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
5115 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
5116 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
5117 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
5118 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
5119 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
5120 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
5121 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p))
5122 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5123 (GEN8_PIPE_CURSOR_FAULT | \
5124 GEN8_PIPE_SPRITE_FAULT | \
5125 GEN8_PIPE_PRIMARY_FAULT)
5126 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5127 (GEN9_PIPE_CURSOR_FAULT | \
5128 GEN9_PIPE_PLANE3_FAULT | \
5129 GEN9_PIPE_PLANE2_FAULT | \
5130 GEN9_PIPE_PLANE1_FAULT)
5132 #define GEN8_DE_PORT_ISR 0x44440
5133 #define GEN8_DE_PORT_IMR 0x44444
5134 #define GEN8_DE_PORT_IIR 0x44448
5135 #define GEN8_DE_PORT_IER 0x4444c
5136 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
5137 #define GEN9_AUX_CHANNEL_D (1 << 27)
5138 #define GEN9_AUX_CHANNEL_C (1 << 26)
5139 #define GEN9_AUX_CHANNEL_B (1 << 25)
5140 #define GEN8_AUX_CHANNEL_A (1 << 0)
5142 #define GEN8_DE_MISC_ISR 0x44460
5143 #define GEN8_DE_MISC_IMR 0x44464
5144 #define GEN8_DE_MISC_IIR 0x44468
5145 #define GEN8_DE_MISC_IER 0x4446c
5146 #define GEN8_DE_MISC_GSE (1 << 27)
5148 #define GEN8_PCU_ISR 0x444e0
5149 #define GEN8_PCU_IMR 0x444e4
5150 #define GEN8_PCU_IIR 0x444e8
5151 #define GEN8_PCU_IER 0x444ec
5153 #define ILK_DISPLAY_CHICKEN2 0x42004
5154 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
5155 #define ILK_ELPIN_409_SELECT (1 << 25)
5156 #define ILK_DPARB_GATE (1<<22)
5157 #define ILK_VSDPFD_FULL (1<<21)
5158 #define FUSE_STRAP 0x42014
5159 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
5160 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
5161 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
5162 #define ILK_HDCP_DISABLE (1 << 25)
5163 #define ILK_eDP_A_DISABLE (1 << 24)
5164 #define HSW_CDCLK_LIMIT (1 << 24)
5165 #define ILK_DESKTOP (1 << 23)
5167 #define ILK_DSPCLK_GATE_D 0x42020
5168 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
5169 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
5170 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
5171 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
5172 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
5174 #define IVB_CHICKEN3 0x4200c
5175 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
5176 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
5178 #define CHICKEN_PAR1_1 0x42080
5179 #define DPA_MASK_VBLANK_SRD (1 << 15)
5180 #define FORCE_ARB_IDLE_PLANES (1 << 14)
5182 #define _CHICKEN_PIPESL_1_A 0x420b0
5183 #define _CHICKEN_PIPESL_1_B 0x420b4
5184 #define HSW_FBCQ_DIS (1 << 22)
5185 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
5186 #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
5188 #define DISP_ARB_CTL 0x45000
5189 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
5190 #define DISP_FBC_WM_DIS (1<<15)
5191 #define DISP_ARB_CTL2 0x45004
5192 #define DISP_DATA_PARTITION_5_6 (1<<6)
5193 #define GEN7_MSG_CTL 0x45010
5194 #define WAIT_FOR_PCH_RESET_ACK (1<<1)
5195 #define WAIT_FOR_PCH_FLR_ACK (1<<0)
5196 #define HSW_NDE_RSTWRN_OPT 0x46408
5197 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
5200 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
5201 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
5202 #define COMMON_SLICE_CHICKEN2 0x7014
5203 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
5205 #define GEN7_L3SQCREG1 0xB010
5206 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
5208 #define GEN7_L3CNTLREG1 0xB01C
5209 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
5210 #define GEN7_L3AGDIS (1<<19)
5211 #define GEN7_L3CNTLREG2 0xB020
5212 #define GEN7_L3CNTLREG3 0xB024
5214 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
5215 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
5217 #define GEN7_L3SQCREG4 0xb034
5218 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
5221 #define HDC_CHICKEN0 0x7300
5222 #define HDC_FORCE_NON_COHERENT (1<<4)
5223 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
5224 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
5226 /* WaCatErrorRejectionIssue */
5227 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
5228 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
5230 #define HSW_SCRATCH1 0xb038
5231 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
5235 /* south display engine interrupt: IBX */
5236 #define SDE_AUDIO_POWER_D (1 << 27)
5237 #define SDE_AUDIO_POWER_C (1 << 26)
5238 #define SDE_AUDIO_POWER_B (1 << 25)
5239 #define SDE_AUDIO_POWER_SHIFT (25)
5240 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
5241 #define SDE_GMBUS (1 << 24)
5242 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
5243 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
5244 #define SDE_AUDIO_HDCP_MASK (3 << 22)
5245 #define SDE_AUDIO_TRANSB (1 << 21)
5246 #define SDE_AUDIO_TRANSA (1 << 20)
5247 #define SDE_AUDIO_TRANS_MASK (3 << 20)
5248 #define SDE_POISON (1 << 19)
5250 #define SDE_FDI_RXB (1 << 17)
5251 #define SDE_FDI_RXA (1 << 16)
5252 #define SDE_FDI_MASK (3 << 16)
5253 #define SDE_AUXD (1 << 15)
5254 #define SDE_AUXC (1 << 14)
5255 #define SDE_AUXB (1 << 13)
5256 #define SDE_AUX_MASK (7 << 13)
5258 #define SDE_CRT_HOTPLUG (1 << 11)
5259 #define SDE_PORTD_HOTPLUG (1 << 10)
5260 #define SDE_PORTC_HOTPLUG (1 << 9)
5261 #define SDE_PORTB_HOTPLUG (1 << 8)
5262 #define SDE_SDVOB_HOTPLUG (1 << 6)
5263 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
5264 SDE_SDVOB_HOTPLUG | \
5265 SDE_PORTB_HOTPLUG | \
5266 SDE_PORTC_HOTPLUG | \
5268 #define SDE_TRANSB_CRC_DONE (1 << 5)
5269 #define SDE_TRANSB_CRC_ERR (1 << 4)
5270 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
5271 #define SDE_TRANSA_CRC_DONE (1 << 2)
5272 #define SDE_TRANSA_CRC_ERR (1 << 1)
5273 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
5274 #define SDE_TRANS_MASK (0x3f)
5276 /* south display engine interrupt: CPT/PPT */
5277 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
5278 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
5279 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
5280 #define SDE_AUDIO_POWER_SHIFT_CPT 29
5281 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
5282 #define SDE_AUXD_CPT (1 << 27)
5283 #define SDE_AUXC_CPT (1 << 26)
5284 #define SDE_AUXB_CPT (1 << 25)
5285 #define SDE_AUX_MASK_CPT (7 << 25)
5286 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
5287 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
5288 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
5289 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
5290 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
5291 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
5292 SDE_SDVOB_HOTPLUG_CPT | \
5293 SDE_PORTD_HOTPLUG_CPT | \
5294 SDE_PORTC_HOTPLUG_CPT | \
5295 SDE_PORTB_HOTPLUG_CPT)
5296 #define SDE_GMBUS_CPT (1 << 17)
5297 #define SDE_ERROR_CPT (1 << 16)
5298 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
5299 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
5300 #define SDE_FDI_RXC_CPT (1 << 8)
5301 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
5302 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
5303 #define SDE_FDI_RXB_CPT (1 << 4)
5304 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
5305 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
5306 #define SDE_FDI_RXA_CPT (1 << 0)
5307 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
5308 SDE_AUDIO_CP_REQ_B_CPT | \
5309 SDE_AUDIO_CP_REQ_A_CPT)
5310 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
5311 SDE_AUDIO_CP_CHG_B_CPT | \
5312 SDE_AUDIO_CP_CHG_A_CPT)
5313 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
5317 #define SDEISR 0xc4000
5318 #define SDEIMR 0xc4004
5319 #define SDEIIR 0xc4008
5320 #define SDEIER 0xc400c
5322 #define SERR_INT 0xc4040
5323 #define SERR_INT_POISON (1<<31)
5324 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
5325 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
5326 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
5327 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
5329 /* digital port hotplug */
5330 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
5331 #define PORTD_HOTPLUG_ENABLE (1 << 20)
5332 #define PORTD_PULSE_DURATION_2ms (0)
5333 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
5334 #define PORTD_PULSE_DURATION_6ms (2 << 18)
5335 #define PORTD_PULSE_DURATION_100ms (3 << 18)
5336 #define PORTD_PULSE_DURATION_MASK (3 << 18)
5337 #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
5338 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
5339 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
5340 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
5341 #define PORTC_HOTPLUG_ENABLE (1 << 12)
5342 #define PORTC_PULSE_DURATION_2ms (0)
5343 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
5344 #define PORTC_PULSE_DURATION_6ms (2 << 10)
5345 #define PORTC_PULSE_DURATION_100ms (3 << 10)
5346 #define PORTC_PULSE_DURATION_MASK (3 << 10)
5347 #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
5348 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
5349 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
5350 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
5351 #define PORTB_HOTPLUG_ENABLE (1 << 4)
5352 #define PORTB_PULSE_DURATION_2ms (0)
5353 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
5354 #define PORTB_PULSE_DURATION_6ms (2 << 2)
5355 #define PORTB_PULSE_DURATION_100ms (3 << 2)
5356 #define PORTB_PULSE_DURATION_MASK (3 << 2)
5357 #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
5358 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
5359 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
5360 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
5362 #define PCH_GPIOA 0xc5010
5363 #define PCH_GPIOB 0xc5014
5364 #define PCH_GPIOC 0xc5018
5365 #define PCH_GPIOD 0xc501c
5366 #define PCH_GPIOE 0xc5020
5367 #define PCH_GPIOF 0xc5024
5369 #define PCH_GMBUS0 0xc5100
5370 #define PCH_GMBUS1 0xc5104
5371 #define PCH_GMBUS2 0xc5108
5372 #define PCH_GMBUS3 0xc510c
5373 #define PCH_GMBUS4 0xc5110
5374 #define PCH_GMBUS5 0xc5120
5376 #define _PCH_DPLL_A 0xc6014
5377 #define _PCH_DPLL_B 0xc6018
5378 #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
5380 #define _PCH_FPA0 0xc6040
5381 #define FP_CB_TUNE (0x3<<22)
5382 #define _PCH_FPA1 0xc6044
5383 #define _PCH_FPB0 0xc6048
5384 #define _PCH_FPB1 0xc604c
5385 #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
5386 #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
5388 #define PCH_DPLL_TEST 0xc606c
5390 #define PCH_DREF_CONTROL 0xC6200
5391 #define DREF_CONTROL_MASK 0x7fc3
5392 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
5393 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
5394 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
5395 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
5396 #define DREF_SSC_SOURCE_DISABLE (0<<11)
5397 #define DREF_SSC_SOURCE_ENABLE (2<<11)
5398 #define DREF_SSC_SOURCE_MASK (3<<11)
5399 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
5400 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
5401 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
5402 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
5403 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
5404 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
5405 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
5406 #define DREF_SSC4_DOWNSPREAD (0<<6)
5407 #define DREF_SSC4_CENTERSPREAD (1<<6)
5408 #define DREF_SSC1_DISABLE (0<<1)
5409 #define DREF_SSC1_ENABLE (1<<1)
5410 #define DREF_SSC4_DISABLE (0)
5411 #define DREF_SSC4_ENABLE (1)
5413 #define PCH_RAWCLK_FREQ 0xc6204
5414 #define FDL_TP1_TIMER_SHIFT 12
5415 #define FDL_TP1_TIMER_MASK (3<<12)
5416 #define FDL_TP2_TIMER_SHIFT 10
5417 #define FDL_TP2_TIMER_MASK (3<<10)
5418 #define RAWCLK_FREQ_MASK 0x3ff
5420 #define PCH_DPLL_TMR_CFG 0xc6208
5422 #define PCH_SSC4_PARMS 0xc6210
5423 #define PCH_SSC4_AUX_PARMS 0xc6214
5425 #define PCH_DPLL_SEL 0xc7000
5426 #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
5427 #define TRANS_DPLLA_SEL(pipe) 0
5428 #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
5432 #define _PCH_TRANS_HTOTAL_A 0xe0000
5433 #define TRANS_HTOTAL_SHIFT 16
5434 #define TRANS_HACTIVE_SHIFT 0
5435 #define _PCH_TRANS_HBLANK_A 0xe0004
5436 #define TRANS_HBLANK_END_SHIFT 16
5437 #define TRANS_HBLANK_START_SHIFT 0
5438 #define _PCH_TRANS_HSYNC_A 0xe0008
5439 #define TRANS_HSYNC_END_SHIFT 16
5440 #define TRANS_HSYNC_START_SHIFT 0
5441 #define _PCH_TRANS_VTOTAL_A 0xe000c
5442 #define TRANS_VTOTAL_SHIFT 16
5443 #define TRANS_VACTIVE_SHIFT 0
5444 #define _PCH_TRANS_VBLANK_A 0xe0010
5445 #define TRANS_VBLANK_END_SHIFT 16
5446 #define TRANS_VBLANK_START_SHIFT 0
5447 #define _PCH_TRANS_VSYNC_A 0xe0014
5448 #define TRANS_VSYNC_END_SHIFT 16
5449 #define TRANS_VSYNC_START_SHIFT 0
5450 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
5452 #define _PCH_TRANSA_DATA_M1 0xe0030
5453 #define _PCH_TRANSA_DATA_N1 0xe0034
5454 #define _PCH_TRANSA_DATA_M2 0xe0038
5455 #define _PCH_TRANSA_DATA_N2 0xe003c
5456 #define _PCH_TRANSA_LINK_M1 0xe0040
5457 #define _PCH_TRANSA_LINK_N1 0xe0044
5458 #define _PCH_TRANSA_LINK_M2 0xe0048
5459 #define _PCH_TRANSA_LINK_N2 0xe004c
5461 /* Per-transcoder DIP controls (PCH) */
5462 #define _VIDEO_DIP_CTL_A 0xe0200
5463 #define _VIDEO_DIP_DATA_A 0xe0208
5464 #define _VIDEO_DIP_GCP_A 0xe0210
5466 #define _VIDEO_DIP_CTL_B 0xe1200
5467 #define _VIDEO_DIP_DATA_B 0xe1208
5468 #define _VIDEO_DIP_GCP_B 0xe1210
5470 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
5471 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
5472 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
5474 /* Per-transcoder DIP controls (VLV) */
5475 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
5476 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
5477 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
5479 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
5480 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
5481 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
5483 #define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
5484 #define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
5485 #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
5487 #define VLV_TVIDEO_DIP_CTL(pipe) \
5488 _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
5489 VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
5490 #define VLV_TVIDEO_DIP_DATA(pipe) \
5491 _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
5492 VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
5493 #define VLV_TVIDEO_DIP_GCP(pipe) \
5494 _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
5495 VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
5497 /* Haswell DIP controls */
5498 #define HSW_VIDEO_DIP_CTL_A 0x60200
5499 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
5500 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260
5501 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
5502 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
5503 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
5504 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
5505 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280
5506 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
5507 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
5508 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
5509 #define HSW_VIDEO_DIP_GCP_A 0x60210
5511 #define HSW_VIDEO_DIP_CTL_B 0x61200
5512 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
5513 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260
5514 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
5515 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
5516 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
5517 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
5518 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280
5519 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
5520 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
5521 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
5522 #define HSW_VIDEO_DIP_GCP_B 0x61210
5524 #define HSW_TVIDEO_DIP_CTL(trans) \
5525 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
5526 #define HSW_TVIDEO_DIP_AVI_DATA(trans) \
5527 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
5528 #define HSW_TVIDEO_DIP_VS_DATA(trans) \
5529 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
5530 #define HSW_TVIDEO_DIP_SPD_DATA(trans) \
5531 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
5532 #define HSW_TVIDEO_DIP_GCP(trans) \
5533 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
5534 #define HSW_TVIDEO_DIP_VSC_DATA(trans) \
5535 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
5537 #define HSW_STEREO_3D_CTL_A 0x70020
5538 #define S3D_ENABLE (1<<31)
5539 #define HSW_STEREO_3D_CTL_B 0x71020
5541 #define HSW_STEREO_3D_CTL(trans) \
5542 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
5544 #define _PCH_TRANS_HTOTAL_B 0xe1000
5545 #define _PCH_TRANS_HBLANK_B 0xe1004
5546 #define _PCH_TRANS_HSYNC_B 0xe1008
5547 #define _PCH_TRANS_VTOTAL_B 0xe100c
5548 #define _PCH_TRANS_VBLANK_B 0xe1010
5549 #define _PCH_TRANS_VSYNC_B 0xe1014
5550 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
5552 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
5553 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
5554 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
5555 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
5556 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
5557 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
5558 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
5559 _PCH_TRANS_VSYNCSHIFT_B)
5561 #define _PCH_TRANSB_DATA_M1 0xe1030
5562 #define _PCH_TRANSB_DATA_N1 0xe1034
5563 #define _PCH_TRANSB_DATA_M2 0xe1038
5564 #define _PCH_TRANSB_DATA_N2 0xe103c
5565 #define _PCH_TRANSB_LINK_M1 0xe1040
5566 #define _PCH_TRANSB_LINK_N1 0xe1044
5567 #define _PCH_TRANSB_LINK_M2 0xe1048
5568 #define _PCH_TRANSB_LINK_N2 0xe104c
5570 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
5571 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
5572 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
5573 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
5574 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
5575 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
5576 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
5577 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
5579 #define _PCH_TRANSACONF 0xf0008
5580 #define _PCH_TRANSBCONF 0xf1008
5581 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
5582 #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
5583 #define TRANS_DISABLE (0<<31)
5584 #define TRANS_ENABLE (1<<31)
5585 #define TRANS_STATE_MASK (1<<30)
5586 #define TRANS_STATE_DISABLE (0<<30)
5587 #define TRANS_STATE_ENABLE (1<<30)
5588 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
5589 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
5590 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
5591 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
5592 #define TRANS_INTERLACE_MASK (7<<21)
5593 #define TRANS_PROGRESSIVE (0<<21)
5594 #define TRANS_INTERLACED (3<<21)
5595 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
5596 #define TRANS_8BPC (0<<5)
5597 #define TRANS_10BPC (1<<5)
5598 #define TRANS_6BPC (2<<5)
5599 #define TRANS_12BPC (3<<5)
5601 #define _TRANSA_CHICKEN1 0xf0060
5602 #define _TRANSB_CHICKEN1 0xf1060
5603 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
5604 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
5605 #define _TRANSA_CHICKEN2 0xf0064
5606 #define _TRANSB_CHICKEN2 0xf1064
5607 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
5608 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
5609 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
5610 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
5611 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
5612 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
5614 #define SOUTH_CHICKEN1 0xc2000
5615 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
5616 #define FDIA_PHASE_SYNC_SHIFT_EN 18
5617 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
5618 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
5619 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
5620 #define SOUTH_CHICKEN2 0xc2004
5621 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
5622 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
5623 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
5625 #define _FDI_RXA_CHICKEN 0xc200c
5626 #define _FDI_RXB_CHICKEN 0xc2010
5627 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
5628 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
5629 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
5631 #define SOUTH_DSPCLK_GATE_D 0xc2020
5632 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
5633 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
5634 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
5635 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
5638 #define _FDI_TXA_CTL 0x60100
5639 #define _FDI_TXB_CTL 0x61100
5640 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
5641 #define FDI_TX_DISABLE (0<<31)
5642 #define FDI_TX_ENABLE (1<<31)
5643 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
5644 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
5645 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
5646 #define FDI_LINK_TRAIN_NONE (3<<28)
5647 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
5648 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
5649 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
5650 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
5651 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
5652 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
5653 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
5654 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
5655 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
5656 SNB has different settings. */
5657 /* SNB A-stepping */
5658 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
5659 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
5660 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
5661 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
5662 /* SNB B-stepping */
5663 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
5664 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
5665 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
5666 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
5667 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
5668 #define FDI_DP_PORT_WIDTH_SHIFT 19
5669 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
5670 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
5671 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
5672 /* Ironlake: hardwired to 1 */
5673 #define FDI_TX_PLL_ENABLE (1<<14)
5675 /* Ivybridge has different bits for lolz */
5676 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
5677 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
5678 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
5679 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
5681 /* both Tx and Rx */
5682 #define FDI_COMPOSITE_SYNC (1<<11)
5683 #define FDI_LINK_TRAIN_AUTO (1<<10)
5684 #define FDI_SCRAMBLING_ENABLE (0<<7)
5685 #define FDI_SCRAMBLING_DISABLE (1<<7)
5687 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
5688 #define _FDI_RXA_CTL 0xf000c
5689 #define _FDI_RXB_CTL 0xf100c
5690 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
5691 #define FDI_RX_ENABLE (1<<31)
5692 /* train, dp width same as FDI_TX */
5693 #define FDI_FS_ERRC_ENABLE (1<<27)
5694 #define FDI_FE_ERRC_ENABLE (1<<26)
5695 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
5696 #define FDI_8BPC (0<<16)
5697 #define FDI_10BPC (1<<16)
5698 #define FDI_6BPC (2<<16)
5699 #define FDI_12BPC (3<<16)
5700 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
5701 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
5702 #define FDI_RX_PLL_ENABLE (1<<13)
5703 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
5704 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
5705 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
5706 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
5707 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
5708 #define FDI_PCDCLK (1<<4)
5710 #define FDI_AUTO_TRAINING (1<<10)
5711 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
5712 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
5713 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
5714 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
5715 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
5717 #define _FDI_RXA_MISC 0xf0010
5718 #define _FDI_RXB_MISC 0xf1010
5719 #define FDI_RX_PWRDN_LANE1_MASK (3<<26)
5720 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
5721 #define FDI_RX_PWRDN_LANE0_MASK (3<<24)
5722 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
5723 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
5724 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
5725 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
5726 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
5728 #define _FDI_RXA_TUSIZE1 0xf0030
5729 #define _FDI_RXA_TUSIZE2 0xf0038
5730 #define _FDI_RXB_TUSIZE1 0xf1030
5731 #define _FDI_RXB_TUSIZE2 0xf1038
5732 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
5733 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
5735 /* FDI_RX interrupt register format */
5736 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
5737 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
5738 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
5739 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
5740 #define FDI_RX_FS_CODE_ERR (1<<6)
5741 #define FDI_RX_FE_CODE_ERR (1<<5)
5742 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
5743 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
5744 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
5745 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
5746 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
5748 #define _FDI_RXA_IIR 0xf0014
5749 #define _FDI_RXA_IMR 0xf0018
5750 #define _FDI_RXB_IIR 0xf1014
5751 #define _FDI_RXB_IMR 0xf1018
5752 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
5753 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
5755 #define FDI_PLL_CTL_1 0xfe000
5756 #define FDI_PLL_CTL_2 0xfe004
5758 #define PCH_LVDS 0xe1180
5759 #define LVDS_DETECTED (1 << 1)
5761 /* vlv has 2 sets of panel control regs. */
5762 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
5763 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
5764 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
5765 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
5766 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
5767 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
5769 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
5770 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
5771 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
5772 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
5773 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
5775 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
5776 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
5777 #define VLV_PIPE_PP_ON_DELAYS(pipe) \
5778 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
5779 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \
5780 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
5781 #define VLV_PIPE_PP_DIVISOR(pipe) \
5782 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
5784 #define PCH_PP_STATUS 0xc7200
5785 #define PCH_PP_CONTROL 0xc7204
5786 #define PANEL_UNLOCK_REGS (0xabcd << 16)
5787 #define PANEL_UNLOCK_MASK (0xffff << 16)
5788 #define EDP_FORCE_VDD (1 << 3)
5789 #define EDP_BLC_ENABLE (1 << 2)
5790 #define PANEL_POWER_RESET (1 << 1)
5791 #define PANEL_POWER_OFF (0 << 0)
5792 #define PANEL_POWER_ON (1 << 0)
5793 #define PCH_PP_ON_DELAYS 0xc7208
5794 #define PANEL_PORT_SELECT_MASK (3 << 30)
5795 #define PANEL_PORT_SELECT_LVDS (0 << 30)
5796 #define PANEL_PORT_SELECT_DPA (1 << 30)
5797 #define PANEL_PORT_SELECT_DPC (2 << 30)
5798 #define PANEL_PORT_SELECT_DPD (3 << 30)
5799 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
5800 #define PANEL_POWER_UP_DELAY_SHIFT 16
5801 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
5802 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
5804 #define PCH_PP_OFF_DELAYS 0xc720c
5805 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
5806 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
5807 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
5808 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
5810 #define PCH_PP_DIVISOR 0xc7210
5811 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
5812 #define PP_REFERENCE_DIVIDER_SHIFT 8
5813 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
5814 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
5816 #define PCH_DP_B 0xe4100
5817 #define PCH_DPB_AUX_CH_CTL 0xe4110
5818 #define PCH_DPB_AUX_CH_DATA1 0xe4114
5819 #define PCH_DPB_AUX_CH_DATA2 0xe4118
5820 #define PCH_DPB_AUX_CH_DATA3 0xe411c
5821 #define PCH_DPB_AUX_CH_DATA4 0xe4120
5822 #define PCH_DPB_AUX_CH_DATA5 0xe4124
5824 #define PCH_DP_C 0xe4200
5825 #define PCH_DPC_AUX_CH_CTL 0xe4210
5826 #define PCH_DPC_AUX_CH_DATA1 0xe4214
5827 #define PCH_DPC_AUX_CH_DATA2 0xe4218
5828 #define PCH_DPC_AUX_CH_DATA3 0xe421c
5829 #define PCH_DPC_AUX_CH_DATA4 0xe4220
5830 #define PCH_DPC_AUX_CH_DATA5 0xe4224
5832 #define PCH_DP_D 0xe4300
5833 #define PCH_DPD_AUX_CH_CTL 0xe4310
5834 #define PCH_DPD_AUX_CH_DATA1 0xe4314
5835 #define PCH_DPD_AUX_CH_DATA2 0xe4318
5836 #define PCH_DPD_AUX_CH_DATA3 0xe431c
5837 #define PCH_DPD_AUX_CH_DATA4 0xe4320
5838 #define PCH_DPD_AUX_CH_DATA5 0xe4324
5841 #define PORT_TRANS_A_SEL_CPT 0
5842 #define PORT_TRANS_B_SEL_CPT (1<<29)
5843 #define PORT_TRANS_C_SEL_CPT (2<<29)
5844 #define PORT_TRANS_SEL_MASK (3<<29)
5845 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
5846 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
5847 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
5848 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
5849 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
5851 #define TRANS_DP_CTL_A 0xe0300
5852 #define TRANS_DP_CTL_B 0xe1300
5853 #define TRANS_DP_CTL_C 0xe2300
5854 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
5855 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
5856 #define TRANS_DP_PORT_SEL_B (0<<29)
5857 #define TRANS_DP_PORT_SEL_C (1<<29)
5858 #define TRANS_DP_PORT_SEL_D (2<<29)
5859 #define TRANS_DP_PORT_SEL_NONE (3<<29)
5860 #define TRANS_DP_PORT_SEL_MASK (3<<29)
5861 #define TRANS_DP_AUDIO_ONLY (1<<26)
5862 #define TRANS_DP_ENH_FRAMING (1<<18)
5863 #define TRANS_DP_8BPC (0<<9)
5864 #define TRANS_DP_10BPC (1<<9)
5865 #define TRANS_DP_6BPC (2<<9)
5866 #define TRANS_DP_12BPC (3<<9)
5867 #define TRANS_DP_BPC_MASK (3<<9)
5868 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
5869 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
5870 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
5871 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
5872 #define TRANS_DP_SYNC_MASK (3<<3)
5874 /* SNB eDP training params */
5875 /* SNB A-stepping */
5876 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
5877 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
5878 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
5879 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
5880 /* SNB B-stepping */
5881 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
5882 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
5883 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
5884 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
5885 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
5886 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
5889 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
5890 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
5891 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
5892 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
5893 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
5894 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
5895 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
5898 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
5899 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
5900 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
5901 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
5902 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
5904 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
5906 #define VLV_PMWGICZ 0x1300a4
5908 #define FORCEWAKE 0xA18C
5909 #define FORCEWAKE_VLV 0x1300b0
5910 #define FORCEWAKE_ACK_VLV 0x1300b4
5911 #define FORCEWAKE_MEDIA_VLV 0x1300b8
5912 #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
5913 #define FORCEWAKE_ACK_HSW 0x130044
5914 #define FORCEWAKE_ACK 0x130090
5915 #define VLV_GTLC_WAKE_CTRL 0x130090
5916 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
5917 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
5918 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
5920 #define VLV_GTLC_PW_STATUS 0x130094
5921 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
5922 #define VLV_GTLC_ALLOWWAKEERR (1 << 1)
5923 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
5924 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
5925 #define FORCEWAKE_MT 0xa188 /* multi-threaded */
5926 #define FORCEWAKE_MEDIA_GEN9 0xa270
5927 #define FORCEWAKE_RENDER_GEN9 0xa278
5928 #define FORCEWAKE_BLITTER_GEN9 0xa188
5929 #define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88
5930 #define FORCEWAKE_ACK_RENDER_GEN9 0x0D84
5931 #define FORCEWAKE_ACK_BLITTER_GEN9 0x130044
5932 #define FORCEWAKE_KERNEL 0x1
5933 #define FORCEWAKE_USER 0x2
5934 #define FORCEWAKE_MT_ACK 0x130040
5935 #define ECOBUS 0xa180
5936 #define FORCEWAKE_MT_ENABLE (1<<5)
5937 #define VLV_SPAREG2H 0xA194
5939 #define GTFIFODBG 0x120000
5940 #define GT_FIFO_SBDROPERR (1<<6)
5941 #define GT_FIFO_BLOBDROPERR (1<<5)
5942 #define GT_FIFO_SB_READ_ABORTERR (1<<4)
5943 #define GT_FIFO_DROPERR (1<<3)
5944 #define GT_FIFO_OVFERR (1<<2)
5945 #define GT_FIFO_IAWRERR (1<<1)
5946 #define GT_FIFO_IARDERR (1<<0)
5948 #define GTFIFOCTL 0x120008
5949 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
5950 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
5952 #define HSW_IDICR 0x9008
5953 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
5954 #define HSW_EDRAM_PRESENT 0x120010
5956 #define GEN6_UCGCTL1 0x9400
5957 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
5958 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
5959 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
5961 #define GEN6_UCGCTL2 0x9404
5962 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
5963 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
5964 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
5965 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
5966 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
5968 #define GEN6_UCGCTL3 0x9408
5970 #define GEN7_UCGCTL4 0x940c
5971 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
5973 #define GEN6_RCGCTL1 0x9410
5974 #define GEN6_RCGCTL2 0x9414
5975 #define GEN6_RSTCTL 0x9420
5977 #define GEN8_UCGCTL6 0x9430
5978 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
5980 #define GEN6_GFXPAUSE 0xA000
5981 #define GEN6_RPNSWREQ 0xA008
5982 #define GEN6_TURBO_DISABLE (1<<31)
5983 #define GEN6_FREQUENCY(x) ((x)<<25)
5984 #define HSW_FREQUENCY(x) ((x)<<24)
5985 #define GEN6_OFFSET(x) ((x)<<19)
5986 #define GEN6_AGGRESSIVE_TURBO (0<<15)
5987 #define GEN6_RC_VIDEO_FREQ 0xA00C
5988 #define GEN6_RC_CONTROL 0xA090
5989 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
5990 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
5991 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
5992 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
5993 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
5994 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
5995 #define GEN7_RC_CTL_TO_MODE (1<<28)
5996 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
5997 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
5998 #define GEN6_RP_DOWN_TIMEOUT 0xA010
5999 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
6000 #define GEN6_RPSTAT1 0xA01C
6001 #define GEN6_CAGF_SHIFT 8
6002 #define HSW_CAGF_SHIFT 7
6003 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
6004 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
6005 #define GEN6_RP_CONTROL 0xA024
6006 #define GEN6_RP_MEDIA_TURBO (1<<11)
6007 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
6008 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
6009 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
6010 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
6011 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
6012 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
6013 #define GEN6_RP_ENABLE (1<<7)
6014 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
6015 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
6016 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
6017 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
6018 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
6019 #define GEN6_RP_UP_THRESHOLD 0xA02C
6020 #define GEN6_RP_DOWN_THRESHOLD 0xA030
6021 #define GEN6_RP_CUR_UP_EI 0xA050
6022 #define GEN6_CURICONT_MASK 0xffffff
6023 #define GEN6_RP_CUR_UP 0xA054
6024 #define GEN6_CURBSYTAVG_MASK 0xffffff
6025 #define GEN6_RP_PREV_UP 0xA058
6026 #define GEN6_RP_CUR_DOWN_EI 0xA05C
6027 #define GEN6_CURIAVG_MASK 0xffffff
6028 #define GEN6_RP_CUR_DOWN 0xA060
6029 #define GEN6_RP_PREV_DOWN 0xA064
6030 #define GEN6_RP_UP_EI 0xA068
6031 #define GEN6_RP_DOWN_EI 0xA06C
6032 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
6033 #define GEN6_RPDEUHWTC 0xA080
6034 #define GEN6_RPDEUC 0xA084
6035 #define GEN6_RPDEUCSW 0xA088
6036 #define GEN6_RC_STATE 0xA094
6037 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
6038 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
6039 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
6040 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
6041 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
6042 #define GEN6_RC_SLEEP 0xA0B0
6043 #define GEN6_RCUBMABDTMR 0xA0B0
6044 #define GEN6_RC1e_THRESHOLD 0xA0B4
6045 #define GEN6_RC6_THRESHOLD 0xA0B8
6046 #define GEN6_RC6p_THRESHOLD 0xA0BC
6047 #define VLV_RCEDATA 0xA0BC
6048 #define GEN6_RC6pp_THRESHOLD 0xA0C0
6049 #define GEN6_PMINTRMSK 0xA168
6050 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
6051 #define VLV_PWRDWNUPCTL 0xA294
6053 #define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
6054 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
6055 #define PIXEL_OVERLAP_CNT_SHIFT 30
6057 #define GEN6_PMISR 0x44020
6058 #define GEN6_PMIMR 0x44024 /* rps_lock */
6059 #define GEN6_PMIIR 0x44028
6060 #define GEN6_PMIER 0x4402C
6061 #define GEN6_PM_MBOX_EVENT (1<<25)
6062 #define GEN6_PM_THERMAL_EVENT (1<<24)
6063 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
6064 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
6065 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
6066 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
6067 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
6068 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
6069 GEN6_PM_RP_DOWN_THRESHOLD | \
6070 GEN6_PM_RP_DOWN_TIMEOUT)
6072 #define GEN7_GT_SCRATCH_BASE 0x4F100
6073 #define GEN7_GT_SCRATCH_REG_NUM 8
6075 #define VLV_GTLC_SURVIVABILITY_REG 0x130098
6076 #define VLV_GFX_CLK_STATUS_BIT (1<<3)
6077 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
6079 #define GEN6_GT_GFX_RC6_LOCKED 0x138104
6080 #define VLV_COUNTER_CONTROL 0x138104
6081 #define VLV_COUNT_RANGE_HIGH (1<<15)
6082 #define VLV_MEDIA_RC0_COUNT_EN (1<<5)
6083 #define VLV_RENDER_RC0_COUNT_EN (1<<4)
6084 #define VLV_MEDIA_RC6_COUNT_EN (1<<1)
6085 #define VLV_RENDER_RC6_COUNT_EN (1<<0)
6086 #define GEN6_GT_GFX_RC6 0x138108
6087 #define VLV_GT_RENDER_RC6 0x138108
6088 #define VLV_GT_MEDIA_RC6 0x13810C
6090 #define GEN6_GT_GFX_RC6p 0x13810C
6091 #define GEN6_GT_GFX_RC6pp 0x138110
6092 #define VLV_RENDER_C0_COUNT_REG 0x138118
6093 #define VLV_MEDIA_C0_COUNT_REG 0x13811C
6095 #define GEN6_PCODE_MAILBOX 0x138124
6096 #define GEN6_PCODE_READY (1<<31)
6097 #define GEN6_READ_OC_PARAMS 0xc
6098 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
6099 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
6100 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
6101 #define GEN6_PCODE_READ_RC6VIDS 0x5
6102 #define GEN6_PCODE_READ_D_COMP 0x10
6103 #define GEN6_PCODE_WRITE_D_COMP 0x11
6104 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
6105 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
6106 #define DISPLAY_IPS_CONTROL 0x19
6107 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
6108 #define GEN6_PCODE_DATA 0x138128
6109 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
6110 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
6111 #define GEN6_PCODE_DATA1 0x13812C
6113 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
6114 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
6115 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
6116 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
6117 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
6119 #define GEN6_GT_CORE_STATUS 0x138060
6120 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
6121 #define GEN6_RCn_MASK 7
6127 #define GEN7_MISCCPCTL (0x9424)
6128 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
6131 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
6132 #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
6133 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
6134 #define GEN7_PARITY_ERROR_VALID (1<<13)
6135 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
6136 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
6137 #define GEN7_PARITY_ERROR_ROW(reg) \
6138 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
6139 #define GEN7_PARITY_ERROR_BANK(reg) \
6140 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
6141 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
6142 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
6143 #define GEN7_L3CDERRST1_ENABLE (1<<7)
6145 #define GEN7_L3LOG_BASE 0xB070
6146 #define HSW_L3LOG_BASE_SLICE1 0xB270
6147 #define GEN7_L3LOG_SIZE 0x80
6149 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
6150 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
6151 #define GEN7_MAX_PS_THREAD_DEP (8<<12)
6152 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
6153 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
6155 #define GEN9_HALF_SLICE_CHICKEN5 0xe188
6156 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
6158 #define GEN8_ROW_CHICKEN 0xe4f0
6159 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
6160 #define STALL_DOP_GATING_DISABLE (1<<5)
6162 #define GEN7_ROW_CHICKEN2 0xe4f4
6163 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
6164 #define DOP_CLOCK_GATING_DISABLE (1<<0)
6166 #define HSW_ROW_CHICKEN3 0xe49c
6167 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
6169 #define HALF_SLICE_CHICKEN3 0xe184
6170 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
6171 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
6174 #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
6175 #define INTEL_AUDIO_DEVCL 0x808629FB
6176 #define INTEL_AUDIO_DEVBLC 0x80862801
6177 #define INTEL_AUDIO_DEVCTG 0x80862802
6179 #define G4X_AUD_CNTL_ST 0x620B4
6180 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
6181 #define G4X_ELDV_DEVCTG (1 << 14)
6182 #define G4X_ELD_ADDR_MASK (0xf << 5)
6183 #define G4X_ELD_ACK (1 << 4)
6184 #define G4X_HDMIW_HDMIEDID 0x6210C
6186 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
6187 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
6188 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6189 _IBX_HDMIW_HDMIEDID_A, \
6190 _IBX_HDMIW_HDMIEDID_B)
6191 #define _IBX_AUD_CNTL_ST_A 0xE20B4
6192 #define _IBX_AUD_CNTL_ST_B 0xE21B4
6193 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6194 _IBX_AUD_CNTL_ST_A, \
6196 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
6197 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
6198 #define IBX_ELD_ACK (1 << 4)
6199 #define IBX_AUD_CNTL_ST2 0xE20C0
6200 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
6201 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
6203 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
6204 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
6205 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6206 _CPT_HDMIW_HDMIEDID_A, \
6207 _CPT_HDMIW_HDMIEDID_B)
6208 #define _CPT_AUD_CNTL_ST_A 0xE50B4
6209 #define _CPT_AUD_CNTL_ST_B 0xE51B4
6210 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6211 _CPT_AUD_CNTL_ST_A, \
6213 #define CPT_AUD_CNTRL_ST2 0xE50C0
6215 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
6216 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
6217 #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6218 _VLV_HDMIW_HDMIEDID_A, \
6219 _VLV_HDMIW_HDMIEDID_B)
6220 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
6221 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
6222 #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6223 _VLV_AUD_CNTL_ST_A, \
6225 #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
6227 /* These are the 4 32-bit write offset registers for each stream
6228 * output buffer. It determines the offset from the
6229 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
6231 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
6233 #define _IBX_AUD_CONFIG_A 0xe2000
6234 #define _IBX_AUD_CONFIG_B 0xe2100
6235 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
6236 _IBX_AUD_CONFIG_A, \
6238 #define _CPT_AUD_CONFIG_A 0xe5000
6239 #define _CPT_AUD_CONFIG_B 0xe5100
6240 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
6241 _CPT_AUD_CONFIG_A, \
6243 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
6244 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
6245 #define VLV_AUD_CFG(pipe) _PIPE(pipe, \
6246 _VLV_AUD_CONFIG_A, \
6249 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
6250 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
6251 #define AUD_CONFIG_UPPER_N_SHIFT 20
6252 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
6253 #define AUD_CONFIG_LOWER_N_SHIFT 4
6254 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
6255 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
6256 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
6257 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
6258 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
6259 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
6260 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
6261 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
6262 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
6263 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
6264 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
6265 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
6266 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
6267 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
6270 #define _HSW_AUD_CONFIG_A 0x65000
6271 #define _HSW_AUD_CONFIG_B 0x65100
6272 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \
6273 _HSW_AUD_CONFIG_A, \
6276 #define _HSW_AUD_MISC_CTRL_A 0x65010
6277 #define _HSW_AUD_MISC_CTRL_B 0x65110
6278 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
6279 _HSW_AUD_MISC_CTRL_A, \
6280 _HSW_AUD_MISC_CTRL_B)
6282 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
6283 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
6284 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
6285 _HSW_AUD_DIP_ELD_CTRL_ST_A, \
6286 _HSW_AUD_DIP_ELD_CTRL_ST_B)
6288 /* Audio Digital Converter */
6289 #define _HSW_AUD_DIG_CNVT_1 0x65080
6290 #define _HSW_AUD_DIG_CNVT_2 0x65180
6291 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
6292 _HSW_AUD_DIG_CNVT_1, \
6293 _HSW_AUD_DIG_CNVT_2)
6294 #define DIP_PORT_SEL_MASK 0x3
6296 #define _HSW_AUD_EDID_DATA_A 0x65050
6297 #define _HSW_AUD_EDID_DATA_B 0x65150
6298 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
6299 _HSW_AUD_EDID_DATA_A, \
6300 _HSW_AUD_EDID_DATA_B)
6302 #define HSW_AUD_PIPE_CONV_CFG 0x6507c
6303 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0
6304 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
6305 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
6306 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
6307 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
6309 /* HSW Power Wells */
6310 #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
6311 #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
6312 #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
6313 #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
6314 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
6315 #define HSW_PWR_WELL_STATE_ENABLED (1<<30)
6316 #define HSW_PWR_WELL_CTL5 0x45410
6317 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
6318 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
6319 #define HSW_PWR_WELL_FORCE_ON (1<<19)
6320 #define HSW_PWR_WELL_CTL6 0x45414
6322 /* Per-pipe DDI Function Control */
6323 #define TRANS_DDI_FUNC_CTL_A 0x60400
6324 #define TRANS_DDI_FUNC_CTL_B 0x61400
6325 #define TRANS_DDI_FUNC_CTL_C 0x62400
6326 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400
6327 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
6329 #define TRANS_DDI_FUNC_ENABLE (1<<31)
6330 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
6331 #define TRANS_DDI_PORT_MASK (7<<28)
6332 #define TRANS_DDI_PORT_SHIFT 28
6333 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
6334 #define TRANS_DDI_PORT_NONE (0<<28)
6335 #define TRANS_DDI_MODE_SELECT_MASK (7<<24)
6336 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
6337 #define TRANS_DDI_MODE_SELECT_DVI (1<<24)
6338 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
6339 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
6340 #define TRANS_DDI_MODE_SELECT_FDI (4<<24)
6341 #define TRANS_DDI_BPC_MASK (7<<20)
6342 #define TRANS_DDI_BPC_8 (0<<20)
6343 #define TRANS_DDI_BPC_10 (1<<20)
6344 #define TRANS_DDI_BPC_6 (2<<20)
6345 #define TRANS_DDI_BPC_12 (3<<20)
6346 #define TRANS_DDI_PVSYNC (1<<17)
6347 #define TRANS_DDI_PHSYNC (1<<16)
6348 #define TRANS_DDI_EDP_INPUT_MASK (7<<12)
6349 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
6350 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
6351 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
6352 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
6353 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
6354 #define TRANS_DDI_BFI_ENABLE (1<<4)
6356 /* DisplayPort Transport Control */
6357 #define DP_TP_CTL_A 0x64040
6358 #define DP_TP_CTL_B 0x64140
6359 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
6360 #define DP_TP_CTL_ENABLE (1<<31)
6361 #define DP_TP_CTL_MODE_SST (0<<27)
6362 #define DP_TP_CTL_MODE_MST (1<<27)
6363 #define DP_TP_CTL_FORCE_ACT (1<<25)
6364 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
6365 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
6366 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
6367 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
6368 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
6369 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
6370 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
6371 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
6372 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
6374 /* DisplayPort Transport Status */
6375 #define DP_TP_STATUS_A 0x64044
6376 #define DP_TP_STATUS_B 0x64144
6377 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
6378 #define DP_TP_STATUS_IDLE_DONE (1<<25)
6379 #define DP_TP_STATUS_ACT_SENT (1<<24)
6380 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
6381 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
6382 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
6383 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
6384 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
6386 /* DDI Buffer Control */
6387 #define DDI_BUF_CTL_A 0x64000
6388 #define DDI_BUF_CTL_B 0x64100
6389 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
6390 #define DDI_BUF_CTL_ENABLE (1<<31)
6391 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
6392 #define DDI_BUF_EMP_MASK (0xf<<24)
6393 #define DDI_BUF_PORT_REVERSAL (1<<16)
6394 #define DDI_BUF_IS_IDLE (1<<7)
6395 #define DDI_A_4_LANES (1<<4)
6396 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
6397 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
6399 /* DDI Buffer Translations */
6400 #define DDI_BUF_TRANS_A 0x64E00
6401 #define DDI_BUF_TRANS_B 0x64E60
6402 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
6404 /* Sideband Interface (SBI) is programmed indirectly, via
6405 * SBI_ADDR, which contains the register offset; and SBI_DATA,
6406 * which contains the payload */
6407 #define SBI_ADDR 0xC6000
6408 #define SBI_DATA 0xC6004
6409 #define SBI_CTL_STAT 0xC6008
6410 #define SBI_CTL_DEST_ICLK (0x0<<16)
6411 #define SBI_CTL_DEST_MPHY (0x1<<16)
6412 #define SBI_CTL_OP_IORD (0x2<<8)
6413 #define SBI_CTL_OP_IOWR (0x3<<8)
6414 #define SBI_CTL_OP_CRRD (0x6<<8)
6415 #define SBI_CTL_OP_CRWR (0x7<<8)
6416 #define SBI_RESPONSE_FAIL (0x1<<1)
6417 #define SBI_RESPONSE_SUCCESS (0x0<<1)
6418 #define SBI_BUSY (0x1<<0)
6419 #define SBI_READY (0x0<<0)
6422 #define SBI_SSCDIVINTPHASE6 0x0600
6423 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
6424 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
6425 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
6426 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
6427 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
6428 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
6429 #define SBI_SSCCTL 0x020c
6430 #define SBI_SSCCTL6 0x060C
6431 #define SBI_SSCCTL_PATHALT (1<<3)
6432 #define SBI_SSCCTL_DISABLE (1<<0)
6433 #define SBI_SSCAUXDIV6 0x0610
6434 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
6435 #define SBI_DBUFF0 0x2a00
6436 #define SBI_GEN0 0x1f00
6437 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
6439 /* LPT PIXCLK_GATE */
6440 #define PIXCLK_GATE 0xC6020
6441 #define PIXCLK_GATE_UNGATE (1<<0)
6442 #define PIXCLK_GATE_GATE (0<<0)
6445 #define SPLL_CTL 0x46020
6446 #define SPLL_PLL_ENABLE (1<<31)
6447 #define SPLL_PLL_SSC (1<<28)
6448 #define SPLL_PLL_NON_SSC (2<<28)
6449 #define SPLL_PLL_LCPLL (3<<28)
6450 #define SPLL_PLL_REF_MASK (3<<28)
6451 #define SPLL_PLL_FREQ_810MHz (0<<26)
6452 #define SPLL_PLL_FREQ_1350MHz (1<<26)
6453 #define SPLL_PLL_FREQ_2700MHz (2<<26)
6454 #define SPLL_PLL_FREQ_MASK (3<<26)
6457 #define WRPLL_CTL1 0x46040
6458 #define WRPLL_CTL2 0x46060
6459 #define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
6460 #define WRPLL_PLL_ENABLE (1<<31)
6461 #define WRPLL_PLL_SSC (1<<28)
6462 #define WRPLL_PLL_NON_SSC (2<<28)
6463 #define WRPLL_PLL_LCPLL (3<<28)
6464 #define WRPLL_PLL_REF_MASK (3<<28)
6465 /* WRPLL divider programming */
6466 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
6467 #define WRPLL_DIVIDER_REF_MASK (0xff)
6468 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
6469 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
6470 #define WRPLL_DIVIDER_POST_SHIFT 8
6471 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
6472 #define WRPLL_DIVIDER_FB_SHIFT 16
6473 #define WRPLL_DIVIDER_FB_MASK (0xff<<16)
6475 /* Port clock selection */
6476 #define PORT_CLK_SEL_A 0x46100
6477 #define PORT_CLK_SEL_B 0x46104
6478 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
6479 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
6480 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
6481 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
6482 #define PORT_CLK_SEL_SPLL (3<<29)
6483 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
6484 #define PORT_CLK_SEL_WRPLL1 (4<<29)
6485 #define PORT_CLK_SEL_WRPLL2 (5<<29)
6486 #define PORT_CLK_SEL_NONE (7<<29)
6487 #define PORT_CLK_SEL_MASK (7<<29)
6489 /* Transcoder clock selection */
6490 #define TRANS_CLK_SEL_A 0x46140
6491 #define TRANS_CLK_SEL_B 0x46144
6492 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
6493 /* For each transcoder, we need to select the corresponding port clock */
6494 #define TRANS_CLK_SEL_DISABLED (0x0<<29)
6495 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
6497 #define TRANSA_MSA_MISC 0x60410
6498 #define TRANSB_MSA_MISC 0x61410
6499 #define TRANSC_MSA_MISC 0x62410
6500 #define TRANS_EDP_MSA_MISC 0x6f410
6501 #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
6503 #define TRANS_MSA_SYNC_CLK (1<<0)
6504 #define TRANS_MSA_6_BPC (0<<5)
6505 #define TRANS_MSA_8_BPC (1<<5)
6506 #define TRANS_MSA_10_BPC (2<<5)
6507 #define TRANS_MSA_12_BPC (3<<5)
6508 #define TRANS_MSA_16_BPC (4<<5)
6511 #define LCPLL_CTL 0x130040
6512 #define LCPLL_PLL_DISABLE (1<<31)
6513 #define LCPLL_PLL_LOCK (1<<30)
6514 #define LCPLL_CLK_FREQ_MASK (3<<26)
6515 #define LCPLL_CLK_FREQ_450 (0<<26)
6516 #define LCPLL_CLK_FREQ_54O_BDW (1<<26)
6517 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
6518 #define LCPLL_CLK_FREQ_675_BDW (3<<26)
6519 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
6520 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
6521 #define LCPLL_POWER_DOWN_ALLOW (1<<22)
6522 #define LCPLL_CD_SOURCE_FCLK (1<<21)
6523 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
6530 #define CDCLK_CTL 0x46000
6531 #define CDCLK_FREQ_SEL_MASK (3<<26)
6532 #define CDCLK_FREQ_450_432 (0<<26)
6533 #define CDCLK_FREQ_540 (1<<26)
6534 #define CDCLK_FREQ_337_308 (2<<26)
6535 #define CDCLK_FREQ_675_617 (3<<26)
6536 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
6539 #define LCPLL1_CTL 0x46010
6540 #define LCPLL2_CTL 0x46014
6541 #define LCPLL_PLL_ENABLE (1<<31)
6544 #define DPLL_CTRL1 0x6C058
6545 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
6546 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
6547 #define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
6548 #define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1)
6549 #define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
6550 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
6551 #define DPLL_CRTL1_LINK_RATE_2700 0
6552 #define DPLL_CRTL1_LINK_RATE_1350 1
6553 #define DPLL_CRTL1_LINK_RATE_810 2
6554 #define DPLL_CRTL1_LINK_RATE_1620 3
6555 #define DPLL_CRTL1_LINK_RATE_1080 4
6556 #define DPLL_CRTL1_LINK_RATE_2160 5
6559 #define DPLL_CTRL2 0x6C05C
6560 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15))
6561 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
6562 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
6563 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1))
6564 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
6567 #define DPLL_STATUS 0x6C060
6568 #define DPLL_LOCK(id) (1<<((id)*8))
6571 #define DPLL1_CFGCR1 0x6C040
6572 #define DPLL2_CFGCR1 0x6C048
6573 #define DPLL3_CFGCR1 0x6C050
6574 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
6575 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
6576 #define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9)
6577 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
6579 #define DPLL1_CFGCR2 0x6C044
6580 #define DPLL2_CFGCR2 0x6C04C
6581 #define DPLL3_CFGCR2 0x6C054
6582 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
6583 #define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8)
6584 #define DPLL_CFGCR2_QDIV_MODE(x) (x<<7)
6585 #define DPLL_CFGCR2_KDIV_MASK (3<<5)
6586 #define DPLL_CFGCR2_KDIV(x) (x<<5)
6587 #define DPLL_CFGCR2_KDIV_5 (0<<5)
6588 #define DPLL_CFGCR2_KDIV_2 (1<<5)
6589 #define DPLL_CFGCR2_KDIV_3 (2<<5)
6590 #define DPLL_CFGCR2_KDIV_1 (3<<5)
6591 #define DPLL_CFGCR2_PDIV_MASK (7<<2)
6592 #define DPLL_CFGCR2_PDIV(x) (x<<2)
6593 #define DPLL_CFGCR2_PDIV_1 (0<<2)
6594 #define DPLL_CFGCR2_PDIV_2 (1<<2)
6595 #define DPLL_CFGCR2_PDIV_3 (2<<2)
6596 #define DPLL_CFGCR2_PDIV_7 (4<<2)
6597 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
6599 #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
6600 #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
6602 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
6603 * since on HSW we can't write to it using I915_WRITE. */
6604 #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
6605 #define D_COMP_BDW 0x138144
6606 #define D_COMP_RCOMP_IN_PROGRESS (1<<9)
6607 #define D_COMP_COMP_FORCE (1<<8)
6608 #define D_COMP_COMP_DISABLE (1<<0)
6610 /* Pipe WM_LINETIME - watermark line time */
6611 #define PIPE_WM_LINETIME_A 0x45270
6612 #define PIPE_WM_LINETIME_B 0x45274
6613 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
6615 #define PIPE_WM_LINETIME_MASK (0x1ff)
6616 #define PIPE_WM_LINETIME_TIME(x) ((x))
6617 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
6618 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
6621 #define SFUSE_STRAP 0xc2014
6622 #define SFUSE_STRAP_FUSE_LOCK (1<<13)
6623 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
6624 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
6625 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
6626 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
6628 #define WM_MISC 0x45260
6629 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
6631 #define WM_DBG 0x45280
6632 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
6633 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
6634 #define WM_DBG_DISALLOW_SPRITE (1<<2)
6637 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
6638 #define _PIPE_A_CSC_COEFF_BY 0x49014
6639 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
6640 #define _PIPE_A_CSC_COEFF_BU 0x4901c
6641 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
6642 #define _PIPE_A_CSC_COEFF_BV 0x49024
6643 #define _PIPE_A_CSC_MODE 0x49028
6644 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
6645 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
6646 #define CSC_MODE_YUV_TO_RGB (1 << 0)
6647 #define _PIPE_A_CSC_PREOFF_HI 0x49030
6648 #define _PIPE_A_CSC_PREOFF_ME 0x49034
6649 #define _PIPE_A_CSC_PREOFF_LO 0x49038
6650 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
6651 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
6652 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
6654 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
6655 #define _PIPE_B_CSC_COEFF_BY 0x49114
6656 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
6657 #define _PIPE_B_CSC_COEFF_BU 0x4911c
6658 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
6659 #define _PIPE_B_CSC_COEFF_BV 0x49124
6660 #define _PIPE_B_CSC_MODE 0x49128
6661 #define _PIPE_B_CSC_PREOFF_HI 0x49130
6662 #define _PIPE_B_CSC_PREOFF_ME 0x49134
6663 #define _PIPE_B_CSC_PREOFF_LO 0x49138
6664 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
6665 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
6666 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
6668 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
6669 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
6670 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
6671 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
6672 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
6673 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
6674 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
6675 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
6676 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
6677 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
6678 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
6679 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
6680 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
6682 /* MIPI DSI registers */
6684 #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
6686 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
6687 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
6688 #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
6689 #define DPI_ENABLE (1 << 31) /* A + C */
6690 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
6691 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
6692 #define DUAL_LINK_MODE_SHIFT 26
6693 #define DUAL_LINK_MODE_MASK (1 << 26)
6694 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
6695 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
6696 #define DITHERING_ENABLE (1 << 25) /* A + C */
6697 #define FLOPPED_HSTX (1 << 23)
6698 #define DE_INVERT (1 << 19) /* XXX */
6699 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
6700 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
6701 #define AFE_LATCHOUT (1 << 17)
6702 #define LP_OUTPUT_HOLD (1 << 16)
6703 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
6704 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
6705 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
6706 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
6708 #define CSB_MASK (3 << 9)
6709 #define CSB_20MHZ (0 << 9)
6710 #define CSB_10MHZ (1 << 9)
6711 #define CSB_40MHZ (2 << 9)
6712 #define BANDGAP_MASK (1 << 8)
6713 #define BANDGAP_PNW_CIRCUIT (0 << 8)
6714 #define BANDGAP_LNC_CIRCUIT (1 << 8)
6715 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
6716 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
6717 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
6718 #define TEARING_EFFECT_SHIFT 2 /* A + C */
6719 #define TEARING_EFFECT_MASK (3 << 2)
6720 #define TEARING_EFFECT_OFF (0 << 2)
6721 #define TEARING_EFFECT_DSI (1 << 2)
6722 #define TEARING_EFFECT_GPIO (2 << 2)
6723 #define LANE_CONFIGURATION_SHIFT 0
6724 #define LANE_CONFIGURATION_MASK (3 << 0)
6725 #define LANE_CONFIGURATION_4LANE (0 << 0)
6726 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
6727 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
6729 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
6730 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
6731 #define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \
6732 _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
6733 #define TEARING_EFFECT_DELAY_SHIFT 0
6734 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
6736 /* XXX: all bits reserved */
6737 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
6739 /* MIPI DSI Controller and D-PHY registers */
6741 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
6742 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
6743 #define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \
6744 _MIPIC_DEVICE_READY)
6745 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
6746 #define ULPS_STATE_MASK (3 << 1)
6747 #define ULPS_STATE_ENTER (2 << 1)
6748 #define ULPS_STATE_EXIT (1 << 1)
6749 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
6750 #define DEVICE_READY (1 << 0)
6752 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
6753 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
6754 #define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \
6756 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
6757 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
6758 #define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \
6760 #define TEARING_EFFECT (1 << 31)
6761 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
6762 #define GEN_READ_DATA_AVAIL (1 << 29)
6763 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
6764 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
6765 #define RX_PROT_VIOLATION (1 << 26)
6766 #define RX_INVALID_TX_LENGTH (1 << 25)
6767 #define ACK_WITH_NO_ERROR (1 << 24)
6768 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
6769 #define LP_RX_TIMEOUT (1 << 22)
6770 #define HS_TX_TIMEOUT (1 << 21)
6771 #define DPI_FIFO_UNDERRUN (1 << 20)
6772 #define LOW_CONTENTION (1 << 19)
6773 #define HIGH_CONTENTION (1 << 18)
6774 #define TXDSI_VC_ID_INVALID (1 << 17)
6775 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
6776 #define TXCHECKSUM_ERROR (1 << 15)
6777 #define TXECC_MULTIBIT_ERROR (1 << 14)
6778 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
6779 #define TXFALSE_CONTROL_ERROR (1 << 12)
6780 #define RXDSI_VC_ID_INVALID (1 << 11)
6781 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
6782 #define RXCHECKSUM_ERROR (1 << 9)
6783 #define RXECC_MULTIBIT_ERROR (1 << 8)
6784 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
6785 #define RXFALSE_CONTROL_ERROR (1 << 6)
6786 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
6787 #define RX_LP_TX_SYNC_ERROR (1 << 4)
6788 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
6789 #define RXEOT_SYNC_ERROR (1 << 2)
6790 #define RXSOT_SYNC_ERROR (1 << 1)
6791 #define RXSOT_ERROR (1 << 0)
6793 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
6794 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
6795 #define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \
6796 _MIPIC_DSI_FUNC_PRG)
6797 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
6798 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
6799 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
6800 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
6801 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
6802 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
6803 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
6804 #define VID_MODE_FORMAT_MASK (0xf << 7)
6805 #define VID_MODE_NOT_SUPPORTED (0 << 7)
6806 #define VID_MODE_FORMAT_RGB565 (1 << 7)
6807 #define VID_MODE_FORMAT_RGB666 (2 << 7)
6808 #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
6809 #define VID_MODE_FORMAT_RGB888 (4 << 7)
6810 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
6811 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
6812 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
6813 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
6814 #define DATA_LANES_PRG_REG_SHIFT 0
6815 #define DATA_LANES_PRG_REG_MASK (7 << 0)
6817 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
6818 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
6819 #define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \
6820 _MIPIC_HS_TX_TIMEOUT)
6821 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
6823 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
6824 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
6825 #define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \
6826 _MIPIC_LP_RX_TIMEOUT)
6827 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
6829 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
6830 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
6831 #define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \
6832 _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
6833 #define TURN_AROUND_TIMEOUT_MASK 0x3f
6835 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
6836 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
6837 #define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \
6838 _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
6839 #define DEVICE_RESET_TIMER_MASK 0xffff
6841 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
6842 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
6843 #define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \
6844 _MIPIC_DPI_RESOLUTION)
6845 #define VERTICAL_ADDRESS_SHIFT 16
6846 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
6847 #define HORIZONTAL_ADDRESS_SHIFT 0
6848 #define HORIZONTAL_ADDRESS_MASK 0xffff
6850 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
6851 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
6852 #define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \
6853 _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
6854 #define DBI_FIFO_EMPTY_HALF (0 << 0)
6855 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
6856 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
6858 /* regs below are bits 15:0 */
6859 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
6860 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
6861 #define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \
6862 _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
6864 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
6865 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
6866 #define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \
6869 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
6870 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
6871 #define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \
6874 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
6875 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
6876 #define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \
6877 _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
6879 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
6880 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
6881 #define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \
6882 _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
6884 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
6885 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
6886 #define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \
6889 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
6890 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
6891 #define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \
6894 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
6895 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
6896 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \
6897 _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
6899 /* regs above are bits 15:0 */
6901 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
6902 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
6903 #define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \
6905 #define DPI_LP_MODE (1 << 6)
6906 #define BACKLIGHT_OFF (1 << 5)
6907 #define BACKLIGHT_ON (1 << 4)
6908 #define COLOR_MODE_OFF (1 << 3)
6909 #define COLOR_MODE_ON (1 << 2)
6910 #define TURN_ON (1 << 1)
6911 #define SHUTDOWN (1 << 0)
6913 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
6914 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
6915 #define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \
6917 #define COMMAND_BYTE_SHIFT 0
6918 #define COMMAND_BYTE_MASK (0x3f << 0)
6920 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
6921 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
6922 #define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \
6924 #define MASTER_INIT_TIMER_SHIFT 0
6925 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
6927 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
6928 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
6929 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \
6930 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
6931 #define MAX_RETURN_PKT_SIZE_SHIFT 0
6932 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
6934 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
6935 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
6936 #define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \
6937 _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
6938 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
6939 #define DISABLE_VIDEO_BTA (1 << 3)
6940 #define IP_TG_CONFIG (1 << 2)
6941 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
6942 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
6943 #define VIDEO_MODE_BURST (3 << 0)
6945 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
6946 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
6947 #define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \
6949 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
6950 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
6951 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
6952 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
6953 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
6954 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
6955 #define CLOCKSTOP (1 << 1)
6956 #define EOT_DISABLE (1 << 0)
6958 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
6959 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
6960 #define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \
6962 #define LP_BYTECLK_SHIFT 0
6963 #define LP_BYTECLK_MASK (0xffff << 0)
6966 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
6967 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
6968 #define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \
6972 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
6973 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
6974 #define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \
6977 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
6978 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
6979 #define MIPI_LP_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \
6981 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
6982 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
6983 #define MIPI_HS_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \
6985 #define LONG_PACKET_WORD_COUNT_SHIFT 8
6986 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
6987 #define SHORT_PACKET_PARAM_SHIFT 8
6988 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
6989 #define VIRTUAL_CHANNEL_SHIFT 6
6990 #define VIRTUAL_CHANNEL_MASK (3 << 6)
6991 #define DATA_TYPE_SHIFT 0
6992 #define DATA_TYPE_MASK (3f << 0)
6993 /* data type values, see include/video/mipi_display.h */
6995 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
6996 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
6997 #define MIPI_GEN_FIFO_STAT(port) _MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \
6998 _MIPIC_GEN_FIFO_STAT)
6999 #define DPI_FIFO_EMPTY (1 << 28)
7000 #define DBI_FIFO_EMPTY (1 << 27)
7001 #define LP_CTRL_FIFO_EMPTY (1 << 26)
7002 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
7003 #define LP_CTRL_FIFO_FULL (1 << 24)
7004 #define HS_CTRL_FIFO_EMPTY (1 << 18)
7005 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
7006 #define HS_CTRL_FIFO_FULL (1 << 16)
7007 #define LP_DATA_FIFO_EMPTY (1 << 10)
7008 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
7009 #define LP_DATA_FIFO_FULL (1 << 8)
7010 #define HS_DATA_FIFO_EMPTY (1 << 2)
7011 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
7012 #define HS_DATA_FIFO_FULL (1 << 0)
7014 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
7015 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
7016 #define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \
7017 _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
7018 #define DBI_HS_LP_MODE_MASK (1 << 0)
7019 #define DBI_LP_MODE (1 << 0)
7020 #define DBI_HS_MODE (0 << 0)
7022 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
7023 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
7024 #define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \
7026 #define EXIT_ZERO_COUNT_SHIFT 24
7027 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
7028 #define TRAIL_COUNT_SHIFT 16
7029 #define TRAIL_COUNT_MASK (0x1f << 16)
7030 #define CLK_ZERO_COUNT_SHIFT 8
7031 #define CLK_ZERO_COUNT_MASK (0xff << 8)
7032 #define PREPARE_COUNT_SHIFT 0
7033 #define PREPARE_COUNT_MASK (0x3f << 0)
7036 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
7037 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
7038 #define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \
7041 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
7043 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
7045 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \
7046 _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
7047 #define LP_HS_SSW_CNT_SHIFT 16
7048 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
7049 #define HS_LP_PWR_SW_CNT_SHIFT 0
7050 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
7052 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
7053 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
7054 #define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \
7055 _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
7056 #define STOP_STATE_STALL_COUNTER_SHIFT 0
7057 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
7059 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
7060 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
7061 #define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \
7062 _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
7063 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
7064 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
7065 #define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \
7066 _MIPIC_INTR_EN_REG_1)
7067 #define RX_CONTENTION_DETECTED (1 << 0)
7069 /* XXX: only pipe A ?!? */
7070 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
7071 #define DBI_TYPEC_ENABLE (1 << 31)
7072 #define DBI_TYPEC_WIP (1 << 30)
7073 #define DBI_TYPEC_OPTION_SHIFT 28
7074 #define DBI_TYPEC_OPTION_MASK (3 << 28)
7075 #define DBI_TYPEC_FREQ_SHIFT 24
7076 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
7077 #define DBI_TYPEC_OVERRIDE (1 << 8)
7078 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
7079 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
7082 /* MIPI adapter registers */
7084 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
7085 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
7086 #define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \
7088 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
7089 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
7090 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
7091 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
7092 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
7093 #define READ_REQUEST_PRIORITY_SHIFT 3
7094 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
7095 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
7096 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
7097 #define RGB_FLIP_TO_BGR (1 << 2)
7099 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
7100 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
7101 #define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
7102 _MIPIC_DATA_ADDRESS)
7103 #define DATA_MEM_ADDRESS_SHIFT 5
7104 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
7105 #define DATA_VALID (1 << 0)
7107 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
7108 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
7109 #define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \
7111 #define DATA_LENGTH_SHIFT 0
7112 #define DATA_LENGTH_MASK (0xfffff << 0)
7114 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
7115 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
7116 #define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \
7117 _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
7118 #define COMMAND_MEM_ADDRESS_SHIFT 5
7119 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
7120 #define AUTO_PWG_ENABLE (1 << 2)
7121 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
7122 #define COMMAND_VALID (1 << 0)
7124 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
7125 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
7126 #define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \
7127 _MIPIC_COMMAND_LENGTH)
7128 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
7129 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
7131 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
7132 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
7133 #define MIPI_READ_DATA_RETURN(port, n) \
7134 (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \
7135 + 4 * (n)) /* n: 0...7 */
7137 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
7138 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
7139 #define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \
7140 _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
7141 #define READ_DATA_VALID(n) (1 << (n))
7143 /* For UMS only (deprecated): */
7144 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
7145 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
7147 #endif /* _I915_REG_H_ */
projects / cascardo / linux.git / blob