1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29 #define _PLANE(plane, a, b) _PIPE(plane, a, b)
30 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
32 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
33 (pipe) == PIPE_B ? (b) : (c))
35 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
36 #define _MASKED_BIT_DISABLE(a) ((a) << 16)
38 /* PCI config space */
40 #define HPLLCC 0xc0 /* 855 only */
41 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
42 #define GC_CLOCK_133_200 (0 << 0)
43 #define GC_CLOCK_100_200 (1 << 0)
44 #define GC_CLOCK_100_133 (2 << 0)
45 #define GC_CLOCK_166_250 (3 << 0)
47 #define GCFGC 0xf0 /* 915+ only */
48 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
49 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
50 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
51 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
52 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
53 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
54 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
55 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
56 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
57 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
58 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
59 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
60 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
61 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
62 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
63 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
64 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
65 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
66 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
67 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
68 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
69 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
72 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
73 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
74 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
75 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
76 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
77 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
80 /* Graphics reset regs */
81 #define I915_GDRST 0xc0 /* PCI config register */
82 #define GRDOM_FULL (0<<2)
83 #define GRDOM_RENDER (1<<2)
84 #define GRDOM_MEDIA (3<<2)
85 #define GRDOM_MASK (3<<2)
86 #define GRDOM_RESET_STATUS (1<<1)
87 #define GRDOM_RESET_ENABLE (1<<0)
89 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
90 #define ILK_GRDOM_FULL (0<<1)
91 #define ILK_GRDOM_RENDER (1<<1)
92 #define ILK_GRDOM_MEDIA (3<<1)
93 #define ILK_GRDOM_MASK (3<<1)
94 #define ILK_GRDOM_RESET_ENABLE (1<<0)
96 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
97 #define GEN6_MBC_SNPCR_SHIFT 21
98 #define GEN6_MBC_SNPCR_MASK (3<<21)
99 #define GEN6_MBC_SNPCR_MAX (0<<21)
100 #define GEN6_MBC_SNPCR_MED (1<<21)
101 #define GEN6_MBC_SNPCR_LOW (2<<21)
102 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
104 #define VLV_G3DCTL 0x9024
105 #define VLV_GSCKGCTL 0x9028
107 #define GEN6_MBCTL 0x0907c
108 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
109 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
110 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
111 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
112 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
114 #define GEN6_GDRST 0x941c
115 #define GEN6_GRDOM_FULL (1 << 0)
116 #define GEN6_GRDOM_RENDER (1 << 1)
117 #define GEN6_GRDOM_MEDIA (1 << 2)
118 #define GEN6_GRDOM_BLT (1 << 3)
120 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
121 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
122 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
123 #define PP_DIR_DCLV_2G 0xffffffff
125 #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
126 #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
128 #define GAM_ECOCHK 0x4090
129 #define ECOCHK_SNB_BIT (1<<10)
130 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
131 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
132 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
133 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
134 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
135 #define ECOCHK_PPGTT_UC_HSW (0x1<<3)
136 #define ECOCHK_PPGTT_WT_HSW (0x2<<3)
137 #define ECOCHK_PPGTT_WB_HSW (0x3<<3)
139 #define GAC_ECO_BITS 0x14090
140 #define ECOBITS_SNB_BIT (1<<13)
141 #define ECOBITS_PPGTT_CACHE64B (3<<8)
142 #define ECOBITS_PPGTT_CACHE4B (0<<8)
144 #define GAB_CTL 0x24000
145 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
147 #define GEN7_BIOS_RESERVED 0x1082C0
148 #define GEN7_BIOS_RESERVED_1M (0 << 5)
149 #define GEN7_BIOS_RESERVED_256K (1 << 5)
150 #define GEN8_BIOS_RESERVED_SHIFT 7
151 #define GEN7_BIOS_RESERVED_MASK 0x1
152 #define GEN8_BIOS_RESERVED_MASK 0x3
157 #define VGA_ST01_MDA 0x3ba
158 #define VGA_ST01_CGA 0x3da
160 #define VGA_MSR_WRITE 0x3c2
161 #define VGA_MSR_READ 0x3cc
162 #define VGA_MSR_MEM_EN (1<<1)
163 #define VGA_MSR_CGA_MODE (1<<0)
165 #define VGA_SR_INDEX 0x3c4
167 #define VGA_SR_DATA 0x3c5
169 #define VGA_AR_INDEX 0x3c0
170 #define VGA_AR_VID_EN (1<<5)
171 #define VGA_AR_DATA_WRITE 0x3c0
172 #define VGA_AR_DATA_READ 0x3c1
174 #define VGA_GR_INDEX 0x3ce
175 #define VGA_GR_DATA 0x3cf
177 #define VGA_GR_MEM_READ_MODE_SHIFT 3
178 #define VGA_GR_MEM_READ_MODE_PLANE 1
180 #define VGA_GR_MEM_MODE_MASK 0xc
181 #define VGA_GR_MEM_MODE_SHIFT 2
182 #define VGA_GR_MEM_A0000_AFFFF 0
183 #define VGA_GR_MEM_A0000_BFFFF 1
184 #define VGA_GR_MEM_B0000_B7FFF 2
185 #define VGA_GR_MEM_B0000_BFFFF 3
187 #define VGA_DACMASK 0x3c6
188 #define VGA_DACRX 0x3c7
189 #define VGA_DACWX 0x3c8
190 #define VGA_DACDATA 0x3c9
192 #define VGA_CR_INDEX_MDA 0x3b4
193 #define VGA_CR_DATA_MDA 0x3b5
194 #define VGA_CR_INDEX_CGA 0x3d4
195 #define VGA_CR_DATA_CGA 0x3d5
198 * Instruction field definitions used by the command parser
200 #define INSTR_CLIENT_SHIFT 29
201 #define INSTR_CLIENT_MASK 0xE0000000
202 #define INSTR_MI_CLIENT 0x0
203 #define INSTR_BC_CLIENT 0x2
204 #define INSTR_RC_CLIENT 0x3
205 #define INSTR_SUBCLIENT_SHIFT 27
206 #define INSTR_SUBCLIENT_MASK 0x18000000
207 #define INSTR_MEDIA_SUBCLIENT 0x2
210 * Memory interface instructions used by the kernel
212 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
213 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
214 #define MI_GLOBAL_GTT (1<<22)
216 #define MI_NOOP MI_INSTR(0, 0)
217 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
218 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
219 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
220 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
221 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
222 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
223 #define MI_FLUSH MI_INSTR(0x04, 0)
224 #define MI_READ_FLUSH (1 << 0)
225 #define MI_EXE_FLUSH (1 << 1)
226 #define MI_NO_WRITE_FLUSH (1 << 2)
227 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
228 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
229 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
230 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
231 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
232 #define MI_ARB_ENABLE (1<<0)
233 #define MI_ARB_DISABLE (0<<0)
234 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
235 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
236 #define MI_SUSPEND_FLUSH_EN (1<<0)
237 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
238 #define MI_OVERLAY_CONTINUE (0x0<<21)
239 #define MI_OVERLAY_ON (0x1<<21)
240 #define MI_OVERLAY_OFF (0x2<<21)
241 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
242 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
243 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
244 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
245 /* IVB has funny definitions for which plane to flip. */
246 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
247 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
248 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
249 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
250 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
251 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
253 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
254 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
255 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
256 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
257 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
258 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
259 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
260 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
261 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
262 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
263 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
264 #define MI_SEMAPHORE_UPDATE (1<<21)
265 #define MI_SEMAPHORE_COMPARE (1<<20)
266 #define MI_SEMAPHORE_REGISTER (1<<18)
267 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
268 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
269 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
270 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
271 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
272 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
273 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
274 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
275 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
276 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
277 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
278 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
279 #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
280 #define MI_SEMAPHORE_SYNC_MASK (3<<16)
281 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
282 #define MI_MM_SPACE_GTT (1<<8)
283 #define MI_MM_SPACE_PHYSICAL (0<<8)
284 #define MI_SAVE_EXT_STATE_EN (1<<3)
285 #define MI_RESTORE_EXT_STATE_EN (1<<2)
286 #define MI_FORCE_RESTORE (1<<1)
287 #define MI_RESTORE_INHIBIT (1<<0)
288 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
289 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
290 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
291 #define MI_SEMAPHORE_POLL (1<<15)
292 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
293 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
294 #define MI_STORE_DWORD_IMM_GEN8 MI_INSTR(0x20, 2)
295 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
296 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
297 #define MI_STORE_DWORD_INDEX_SHIFT 2
298 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
299 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
300 * simply ignores the register load under certain conditions.
301 * - One can actually load arbitrary many arbitrary registers: Simply issue x
302 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
304 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
305 #define MI_LRI_FORCE_POSTED (1<<12)
306 #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
307 #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
308 #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
309 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
310 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
311 #define MI_INVALIDATE_TLB (1<<18)
312 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
313 #define MI_FLUSH_DW_OP_MASK (3<<14)
314 #define MI_FLUSH_DW_NOTIFY (1<<8)
315 #define MI_INVALIDATE_BSD (1<<7)
316 #define MI_FLUSH_DW_USE_GTT (1<<2)
317 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
318 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
319 #define MI_BATCH_NON_SECURE (1)
320 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
321 #define MI_BATCH_NON_SECURE_I965 (1<<8)
322 #define MI_BATCH_PPGTT_HSW (1<<8)
323 #define MI_BATCH_NON_SECURE_HSW (1<<13)
324 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
325 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
326 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
328 #define MI_PREDICATE_SRC0 (0x2400)
329 #define MI_PREDICATE_SRC1 (0x2408)
331 #define MI_PREDICATE_RESULT_2 (0x2214)
332 #define LOWER_SLICE_ENABLED (1<<0)
333 #define LOWER_SLICE_DISABLED (0<<0)
336 * 3D instructions used by the kernel
338 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
340 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
341 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
342 #define SC_UPDATE_SCISSOR (0x1<<1)
343 #define SC_ENABLE_MASK (0x1<<0)
344 #define SC_ENABLE (0x1<<0)
345 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
346 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
347 #define SCI_YMIN_MASK (0xffff<<16)
348 #define SCI_XMIN_MASK (0xffff<<0)
349 #define SCI_YMAX_MASK (0xffff<<16)
350 #define SCI_XMAX_MASK (0xffff<<0)
351 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
352 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
353 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
354 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
355 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
356 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
357 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
358 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
359 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
361 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
362 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
363 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
364 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
365 #define BLT_WRITE_A (2<<20)
366 #define BLT_WRITE_RGB (1<<20)
367 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
368 #define BLT_DEPTH_8 (0<<24)
369 #define BLT_DEPTH_16_565 (1<<24)
370 #define BLT_DEPTH_16_1555 (2<<24)
371 #define BLT_DEPTH_32 (3<<24)
372 #define BLT_ROP_SRC_COPY (0xcc<<16)
373 #define BLT_ROP_COLOR_COPY (0xf0<<16)
374 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
375 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
376 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
377 #define ASYNC_FLIP (1<<22)
378 #define DISPLAY_PLANE_A (0<<20)
379 #define DISPLAY_PLANE_B (1<<20)
380 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
381 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
382 #define PIPE_CONTROL_MMIO_WRITE (1<<23)
383 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
384 #define PIPE_CONTROL_CS_STALL (1<<20)
385 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
386 #define PIPE_CONTROL_QW_WRITE (1<<14)
387 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
388 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
389 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
390 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
391 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
392 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
393 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
394 #define PIPE_CONTROL_NOTIFY (1<<8)
395 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
396 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
397 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
398 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
399 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
400 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
401 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
404 * Commands used only by the command parser
406 #define MI_SET_PREDICATE MI_INSTR(0x01, 0)
407 #define MI_ARB_CHECK MI_INSTR(0x05, 0)
408 #define MI_RS_CONTROL MI_INSTR(0x06, 0)
409 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
410 #define MI_PREDICATE MI_INSTR(0x0C, 0)
411 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
412 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
413 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
414 #define MI_URB_CLEAR MI_INSTR(0x19, 0)
415 #define MI_UPDATE_GTT MI_INSTR(0x23, 0)
416 #define MI_CLFLUSH MI_INSTR(0x27, 0)
417 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
418 #define MI_REPORT_PERF_COUNT_GGTT (1<<0)
419 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
420 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
421 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
422 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
423 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
424 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
426 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
427 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
428 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
429 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
430 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
431 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
432 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
433 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
434 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
435 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
436 #define GFX_OP_3DSTATE_SO_DECL_LIST \
437 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
439 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
440 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
441 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
442 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
443 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
444 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
445 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
446 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
447 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
448 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
450 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
452 #define COLOR_BLT ((0x2<<29)|(0x40<<22))
453 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
456 * Registers used only by the command parser
458 #define BCS_SWCTRL 0x22200
460 #define HS_INVOCATION_COUNT 0x2300
461 #define DS_INVOCATION_COUNT 0x2308
462 #define IA_VERTICES_COUNT 0x2310
463 #define IA_PRIMITIVES_COUNT 0x2318
464 #define VS_INVOCATION_COUNT 0x2320
465 #define GS_INVOCATION_COUNT 0x2328
466 #define GS_PRIMITIVES_COUNT 0x2330
467 #define CL_INVOCATION_COUNT 0x2338
468 #define CL_PRIMITIVES_COUNT 0x2340
469 #define PS_INVOCATION_COUNT 0x2348
470 #define PS_DEPTH_COUNT 0x2350
472 /* There are the 4 64-bit counter registers, one for each stream output */
473 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
475 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
477 #define GEN7_3DPRIM_END_OFFSET 0x2420
478 #define GEN7_3DPRIM_START_VERTEX 0x2430
479 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
480 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
481 #define GEN7_3DPRIM_START_INSTANCE 0x243C
482 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
484 #define OACONTROL 0x2360
486 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
487 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
488 #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
489 _GEN7_PIPEA_DE_LOAD_SL, \
490 _GEN7_PIPEB_DE_LOAD_SL)
495 #define DEBUG_RESET_I830 0x6070
496 #define DEBUG_RESET_FULL (1<<7)
497 #define DEBUG_RESET_RENDER (1<<8)
498 #define DEBUG_RESET_DISPLAY (1<<9)
503 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
504 #define IOSF_DEVFN_SHIFT 24
505 #define IOSF_OPCODE_SHIFT 16
506 #define IOSF_PORT_SHIFT 8
507 #define IOSF_BYTE_ENABLES_SHIFT 4
508 #define IOSF_BAR_SHIFT 1
509 #define IOSF_SB_BUSY (1<<0)
510 #define IOSF_PORT_BUNIT 0x3
511 #define IOSF_PORT_PUNIT 0x4
512 #define IOSF_PORT_NC 0x11
513 #define IOSF_PORT_DPIO 0x12
514 #define IOSF_PORT_DPIO_2 0x1a
515 #define IOSF_PORT_GPIO_NC 0x13
516 #define IOSF_PORT_CCK 0x14
517 #define IOSF_PORT_CCU 0xA9
518 #define IOSF_PORT_GPS_CORE 0x48
519 #define IOSF_PORT_FLISDSI 0x1B
520 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
521 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
523 /* See configdb bunit SB addr map */
524 #define BUNIT_REG_BISOC 0x11
526 #define PUNIT_REG_DSPFREQ 0x36
527 #define DSPFREQSTAT_SHIFT_CHV 24
528 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
529 #define DSPFREQGUAR_SHIFT_CHV 8
530 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
531 #define DSPFREQSTAT_SHIFT 30
532 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
533 #define DSPFREQGUAR_SHIFT 14
534 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
535 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
536 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
537 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
538 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
539 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
540 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
541 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
542 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
543 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
544 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
545 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
546 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
548 /* See the PUNIT HAS v0.8 for the below bits */
549 enum punit_power_well {
550 PUNIT_POWER_WELL_RENDER = 0,
551 PUNIT_POWER_WELL_MEDIA = 1,
552 PUNIT_POWER_WELL_DISP2D = 3,
553 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
554 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
555 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
556 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
557 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
558 PUNIT_POWER_WELL_DPIO_RX0 = 10,
559 PUNIT_POWER_WELL_DPIO_RX1 = 11,
560 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
561 /* FIXME: guesswork below */
562 PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13,
563 PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14,
564 PUNIT_POWER_WELL_DPIO_RX2 = 15,
566 PUNIT_POWER_WELL_NUM,
569 #define PUNIT_REG_PWRGT_CTRL 0x60
570 #define PUNIT_REG_PWRGT_STATUS 0x61
571 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
572 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
573 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
574 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
575 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
577 #define PUNIT_REG_GPU_LFM 0xd3
578 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
579 #define PUNIT_REG_GPU_FREQ_STS 0xd8
580 #define GPLLENABLE (1<<4)
581 #define GENFREQSTATUS (1<<0)
582 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
583 #define PUNIT_REG_CZ_TIMESTAMP 0xce
585 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
586 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
588 #define PUNIT_GPU_STATUS_REG 0xdb
589 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
590 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
591 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
592 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
594 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
595 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
596 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
598 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
599 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
600 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
601 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
602 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
603 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
604 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
605 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
606 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
607 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
609 #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
610 #define VLV_RP_UP_EI_THRESHOLD 90
611 #define VLV_RP_DOWN_EI_THRESHOLD 70
612 #define VLV_INT_COUNT_FOR_DOWN_EI 5
614 /* vlv2 north clock has */
615 #define CCK_FUSE_REG 0x8
616 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
617 #define CCK_REG_DSI_PLL_FUSE 0x44
618 #define CCK_REG_DSI_PLL_CONTROL 0x48
619 #define DSI_PLL_VCO_EN (1 << 31)
620 #define DSI_PLL_LDO_GATE (1 << 30)
621 #define DSI_PLL_P1_POST_DIV_SHIFT 17
622 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
623 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
624 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
625 #define DSI_PLL_MUX_MASK (3 << 9)
626 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
627 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
628 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
629 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
630 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
631 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
632 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
633 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
634 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
635 #define DSI_PLL_LOCK (1 << 0)
636 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
637 #define DSI_PLL_LFSR (1 << 31)
638 #define DSI_PLL_FRACTION_EN (1 << 30)
639 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
640 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
641 #define DSI_PLL_USYNC_CNT_SHIFT 18
642 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
643 #define DSI_PLL_N1_DIV_SHIFT 16
644 #define DSI_PLL_N1_DIV_MASK (3 << 16)
645 #define DSI_PLL_M1_DIV_SHIFT 0
646 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
647 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
648 #define DISPLAY_TRUNK_FORCE_ON (1 << 17)
649 #define DISPLAY_TRUNK_FORCE_OFF (1 << 16)
650 #define DISPLAY_FREQUENCY_STATUS (0x1f << 8)
651 #define DISPLAY_FREQUENCY_STATUS_SHIFT 8
652 #define DISPLAY_FREQUENCY_VALUES (0x1f << 0)
657 * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
658 * ports. DPIO is the name given to such a display PHY. These PHYs
659 * don't follow the standard programming model using direct MMIO
660 * registers, and instead their registers must be accessed trough IOSF
661 * sideband. VLV has one such PHY for driving ports B and C, and CHV
662 * adds another PHY for driving port D. Each PHY responds to specific
665 * Each display PHY is made up of one or two channels. Each channel
666 * houses a common lane part which contains the PLL and other common
667 * logic. CH0 common lane also contains the IOSF-SB logic for the
668 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
669 * must be running when any DPIO registers are accessed.
671 * In addition to having their own registers, the PHYs are also
672 * controlled through some dedicated signals from the display
673 * controller. These include PLL reference clock enable, PLL enable,
674 * and CRI clock selection, for example.
676 * Eeach channel also has two splines (also called data lanes), and
677 * each spline is made up of one Physical Access Coding Sub-Layer
678 * (PCS) block and two TX lanes. So each channel has two PCS blocks
679 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
680 * data/clock pairs depending on the output type.
682 * Additionally the PHY also contains an AUX lane with AUX blocks
683 * for each channel. This is used for DP AUX communication, but
684 * this fact isn't really relevant for the driver since AUX is
685 * controlled from the display controller side. No DPIO registers
686 * need to be accessed during AUX communication,
688 * Generally the common lane corresponds to the pipe and
689 * the spline (PCS/TX) corresponds to the port.
691 * For dual channel PHY (VLV/CHV):
693 * pipe A == CMN/PLL/REF CH0
695 * pipe B == CMN/PLL/REF CH1
697 * port B == PCS/TX CH0
699 * port C == PCS/TX CH1
701 * This is especially important when we cross the streams
702 * ie. drive port B with pipe B, or port C with pipe A.
704 * For single channel PHY (CHV):
706 * pipe C == CMN/PLL/REF CH0
708 * port D == PCS/TX CH0
710 * Note: digital port B is DDI0, digital port C is DDI1,
711 * digital port D is DDI2
714 * Dual channel PHY (VLV/CHV)
715 * ---------------------------------
717 * | CMN/PLL/REF | CMN/PLL/REF |
718 * |---------------|---------------| Display PHY
719 * | PCS01 | PCS23 | PCS01 | PCS23 |
720 * |-------|-------|-------|-------|
721 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
722 * ---------------------------------
723 * | DDI0 | DDI1 | DP/HDMI ports
724 * ---------------------------------
726 * Single channel PHY (CHV)
730 * |---------------| Display PHY
735 * | DDI2 | DP/HDMI port
740 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
741 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
742 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
743 #define DPIO_SFR_BYPASS (1<<1)
744 #define DPIO_CMNRST (1<<0)
746 #define DPIO_PHY(pipe) ((pipe) >> 1)
747 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
750 * Per pipe/PLL DPIO regs
752 #define _VLV_PLL_DW3_CH0 0x800c
753 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
754 #define DPIO_POST_DIV_DAC 0
755 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
756 #define DPIO_POST_DIV_LVDS1 2
757 #define DPIO_POST_DIV_LVDS2 3
758 #define DPIO_K_SHIFT (24) /* 4 bits */
759 #define DPIO_P1_SHIFT (21) /* 3 bits */
760 #define DPIO_P2_SHIFT (16) /* 5 bits */
761 #define DPIO_N_SHIFT (12) /* 4 bits */
762 #define DPIO_ENABLE_CALIBRATION (1<<11)
763 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
764 #define DPIO_M2DIV_MASK 0xff
765 #define _VLV_PLL_DW3_CH1 0x802c
766 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
768 #define _VLV_PLL_DW5_CH0 0x8014
769 #define DPIO_REFSEL_OVERRIDE 27
770 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
771 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
772 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
773 #define DPIO_PLL_REFCLK_SEL_MASK 3
774 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
775 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
776 #define _VLV_PLL_DW5_CH1 0x8034
777 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
779 #define _VLV_PLL_DW7_CH0 0x801c
780 #define _VLV_PLL_DW7_CH1 0x803c
781 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
783 #define _VLV_PLL_DW8_CH0 0x8040
784 #define _VLV_PLL_DW8_CH1 0x8060
785 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
787 #define VLV_PLL_DW9_BCAST 0xc044
788 #define _VLV_PLL_DW9_CH0 0x8044
789 #define _VLV_PLL_DW9_CH1 0x8064
790 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
792 #define _VLV_PLL_DW10_CH0 0x8048
793 #define _VLV_PLL_DW10_CH1 0x8068
794 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
796 #define _VLV_PLL_DW11_CH0 0x804c
797 #define _VLV_PLL_DW11_CH1 0x806c
798 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
800 /* Spec for ref block start counts at DW10 */
801 #define VLV_REF_DW13 0x80ac
803 #define VLV_CMN_DW0 0x8100
806 * Per DDI channel DPIO regs
809 #define _VLV_PCS_DW0_CH0 0x8200
810 #define _VLV_PCS_DW0_CH1 0x8400
811 #define DPIO_PCS_TX_LANE2_RESET (1<<16)
812 #define DPIO_PCS_TX_LANE1_RESET (1<<7)
813 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
814 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
815 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
817 #define _VLV_PCS01_DW0_CH0 0x200
818 #define _VLV_PCS23_DW0_CH0 0x400
819 #define _VLV_PCS01_DW0_CH1 0x2600
820 #define _VLV_PCS23_DW0_CH1 0x2800
821 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
822 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
824 #define _VLV_PCS_DW1_CH0 0x8204
825 #define _VLV_PCS_DW1_CH1 0x8404
826 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
827 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
828 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
829 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
830 #define DPIO_PCS_CLK_SOFT_RESET (1<<5)
831 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
833 #define _VLV_PCS01_DW1_CH0 0x204
834 #define _VLV_PCS23_DW1_CH0 0x404
835 #define _VLV_PCS01_DW1_CH1 0x2604
836 #define _VLV_PCS23_DW1_CH1 0x2804
837 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
838 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
840 #define _VLV_PCS_DW8_CH0 0x8220
841 #define _VLV_PCS_DW8_CH1 0x8420
842 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
843 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
844 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
846 #define _VLV_PCS01_DW8_CH0 0x0220
847 #define _VLV_PCS23_DW8_CH0 0x0420
848 #define _VLV_PCS01_DW8_CH1 0x2620
849 #define _VLV_PCS23_DW8_CH1 0x2820
850 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
851 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
853 #define _VLV_PCS_DW9_CH0 0x8224
854 #define _VLV_PCS_DW9_CH1 0x8424
855 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
856 #define DPIO_PCS_TX2MARGIN_000 (0<<13)
857 #define DPIO_PCS_TX2MARGIN_101 (1<<13)
858 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
859 #define DPIO_PCS_TX1MARGIN_000 (0<<10)
860 #define DPIO_PCS_TX1MARGIN_101 (1<<10)
861 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
863 #define _VLV_PCS01_DW9_CH0 0x224
864 #define _VLV_PCS23_DW9_CH0 0x424
865 #define _VLV_PCS01_DW9_CH1 0x2624
866 #define _VLV_PCS23_DW9_CH1 0x2824
867 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
868 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
870 #define _CHV_PCS_DW10_CH0 0x8228
871 #define _CHV_PCS_DW10_CH1 0x8428
872 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
873 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
874 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
875 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
876 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
877 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
878 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
879 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
880 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
882 #define _VLV_PCS01_DW10_CH0 0x0228
883 #define _VLV_PCS23_DW10_CH0 0x0428
884 #define _VLV_PCS01_DW10_CH1 0x2628
885 #define _VLV_PCS23_DW10_CH1 0x2828
886 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
887 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
889 #define _VLV_PCS_DW11_CH0 0x822c
890 #define _VLV_PCS_DW11_CH1 0x842c
891 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
892 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
893 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
894 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
896 #define _VLV_PCS01_DW11_CH0 0x022c
897 #define _VLV_PCS23_DW11_CH0 0x042c
898 #define _VLV_PCS01_DW11_CH1 0x262c
899 #define _VLV_PCS23_DW11_CH1 0x282c
900 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
901 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
903 #define _VLV_PCS_DW12_CH0 0x8230
904 #define _VLV_PCS_DW12_CH1 0x8430
905 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
907 #define _VLV_PCS_DW14_CH0 0x8238
908 #define _VLV_PCS_DW14_CH1 0x8438
909 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
911 #define _VLV_PCS_DW23_CH0 0x825c
912 #define _VLV_PCS_DW23_CH1 0x845c
913 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
915 #define _VLV_TX_DW2_CH0 0x8288
916 #define _VLV_TX_DW2_CH1 0x8488
917 #define DPIO_SWING_MARGIN000_SHIFT 16
918 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
919 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
920 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
922 #define _VLV_TX_DW3_CH0 0x828c
923 #define _VLV_TX_DW3_CH1 0x848c
924 /* The following bit for CHV phy */
925 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
926 #define DPIO_SWING_MARGIN101_SHIFT 16
927 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
928 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
930 #define _VLV_TX_DW4_CH0 0x8290
931 #define _VLV_TX_DW4_CH1 0x8490
932 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
933 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
934 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
935 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
936 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
938 #define _VLV_TX3_DW4_CH0 0x690
939 #define _VLV_TX3_DW4_CH1 0x2a90
940 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
942 #define _VLV_TX_DW5_CH0 0x8294
943 #define _VLV_TX_DW5_CH1 0x8494
944 #define DPIO_TX_OCALINIT_EN (1<<31)
945 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
947 #define _VLV_TX_DW11_CH0 0x82ac
948 #define _VLV_TX_DW11_CH1 0x84ac
949 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
951 #define _VLV_TX_DW14_CH0 0x82b8
952 #define _VLV_TX_DW14_CH1 0x84b8
953 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
955 /* CHV dpPhy registers */
956 #define _CHV_PLL_DW0_CH0 0x8000
957 #define _CHV_PLL_DW0_CH1 0x8180
958 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
960 #define _CHV_PLL_DW1_CH0 0x8004
961 #define _CHV_PLL_DW1_CH1 0x8184
962 #define DPIO_CHV_N_DIV_SHIFT 8
963 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
964 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
966 #define _CHV_PLL_DW2_CH0 0x8008
967 #define _CHV_PLL_DW2_CH1 0x8188
968 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
970 #define _CHV_PLL_DW3_CH0 0x800c
971 #define _CHV_PLL_DW3_CH1 0x818c
972 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
973 #define DPIO_CHV_FIRST_MOD (0 << 8)
974 #define DPIO_CHV_SECOND_MOD (1 << 8)
975 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
976 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
978 #define _CHV_PLL_DW6_CH0 0x8018
979 #define _CHV_PLL_DW6_CH1 0x8198
980 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
981 #define DPIO_CHV_INT_COEFF_SHIFT 8
982 #define DPIO_CHV_PROP_COEFF_SHIFT 0
983 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
985 #define _CHV_CMN_DW5_CH0 0x8114
986 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
987 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
988 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
989 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
990 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
991 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
992 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
993 #define CHV_BUFLEFTENA1_MASK (3 << 22)
995 #define _CHV_CMN_DW13_CH0 0x8134
996 #define _CHV_CMN_DW0_CH1 0x8080
997 #define DPIO_CHV_S1_DIV_SHIFT 21
998 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
999 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1000 #define DPIO_CHV_K_DIV_SHIFT 4
1001 #define DPIO_PLL_FREQLOCK (1 << 1)
1002 #define DPIO_PLL_LOCK (1 << 0)
1003 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1005 #define _CHV_CMN_DW14_CH0 0x8138
1006 #define _CHV_CMN_DW1_CH1 0x8084
1007 #define DPIO_AFC_RECAL (1 << 14)
1008 #define DPIO_DCLKP_EN (1 << 13)
1009 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1010 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1011 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1012 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1013 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1014 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1015 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1016 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1017 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1019 #define _CHV_CMN_DW19_CH0 0x814c
1020 #define _CHV_CMN_DW6_CH1 0x8098
1021 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1022 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1024 #define CHV_CMN_DW30 0x8178
1025 #define DPIO_LRC_BYPASS (1 << 3)
1027 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1028 (lane) * 0x200 + (offset))
1030 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1031 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1032 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1033 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1034 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1035 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1036 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1037 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1038 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1039 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1040 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1041 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1042 #define DPIO_FRC_LATENCY_SHFIT 8
1043 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1044 #define DPIO_UPAR_SHIFT 30
1048 #define FENCE_REG_830_0 0x2000
1049 #define FENCE_REG_945_8 0x3000
1050 #define I830_FENCE_START_MASK 0x07f80000
1051 #define I830_FENCE_TILING_Y_SHIFT 12
1052 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
1053 #define I830_FENCE_PITCH_SHIFT 4
1054 #define I830_FENCE_REG_VALID (1<<0)
1055 #define I915_FENCE_MAX_PITCH_VAL 4
1056 #define I830_FENCE_MAX_PITCH_VAL 6
1057 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
1059 #define I915_FENCE_START_MASK 0x0ff00000
1060 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
1062 #define FENCE_REG_965_0 0x03000
1063 #define I965_FENCE_PITCH_SHIFT 2
1064 #define I965_FENCE_TILING_Y_SHIFT 1
1065 #define I965_FENCE_REG_VALID (1<<0)
1066 #define I965_FENCE_MAX_PITCH_VAL 0x0400
1068 #define FENCE_REG_SANDYBRIDGE_0 0x100000
1069 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
1070 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
1073 /* control register for cpu gtt access */
1074 #define TILECTL 0x101000
1075 #define TILECTL_SWZCTL (1 << 0)
1076 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
1077 #define TILECTL_BACKSNOOP_DIS (1 << 3)
1080 * Instruction and interrupt control regs
1082 #define PGTBL_CTL 0x02020
1083 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1084 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
1085 #define PGTBL_ER 0x02024
1086 #define PRB0_BASE (0x2030-0x30)
1087 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1088 #define PRB2_BASE (0x2050-0x30) /* gen3 */
1089 #define SRB0_BASE (0x2100-0x30) /* gen2 */
1090 #define SRB1_BASE (0x2110-0x30) /* gen2 */
1091 #define SRB2_BASE (0x2120-0x30) /* 830 */
1092 #define SRB3_BASE (0x2130-0x30) /* 830 */
1093 #define RENDER_RING_BASE 0x02000
1094 #define BSD_RING_BASE 0x04000
1095 #define GEN6_BSD_RING_BASE 0x12000
1096 #define GEN8_BSD2_RING_BASE 0x1c000
1097 #define VEBOX_RING_BASE 0x1a000
1098 #define BLT_RING_BASE 0x22000
1099 #define RING_TAIL(base) ((base)+0x30)
1100 #define RING_HEAD(base) ((base)+0x34)
1101 #define RING_START(base) ((base)+0x38)
1102 #define RING_CTL(base) ((base)+0x3c)
1103 #define RING_SYNC_0(base) ((base)+0x40)
1104 #define RING_SYNC_1(base) ((base)+0x44)
1105 #define RING_SYNC_2(base) ((base)+0x48)
1106 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
1107 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
1108 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
1109 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
1110 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
1111 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
1112 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
1113 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
1114 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
1115 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1116 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1117 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
1118 #define GEN6_NOSYNC 0
1119 #define RING_MAX_IDLE(base) ((base)+0x54)
1120 #define RING_HWS_PGA(base) ((base)+0x80)
1121 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
1123 #define GEN7_WR_WATERMARK 0x4028
1124 #define GEN7_GFX_PRIO_CTRL 0x402C
1125 #define ARB_MODE 0x4030
1126 #define ARB_MODE_SWIZZLE_SNB (1<<4)
1127 #define ARB_MODE_SWIZZLE_IVB (1<<5)
1128 #define GEN7_GFX_PEND_TLB0 0x4034
1129 #define GEN7_GFX_PEND_TLB1 0x4038
1130 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1131 #define GEN7_LRA_LIMITS_BASE 0x403C
1132 #define GEN7_LRA_LIMITS_REG_NUM 13
1133 #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070
1134 #define GEN7_GFX_MAX_REQ_COUNT 0x4074
1136 #define GAMTARBMODE 0x04a08
1137 #define ARB_MODE_BWGTLB_DISABLE (1<<9)
1138 #define ARB_MODE_SWIZZLE_BDW (1<<1)
1139 #define RENDER_HWS_PGA_GEN7 (0x04080)
1140 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
1141 #define RING_FAULT_GTTSEL_MASK (1<<11)
1142 #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
1143 #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
1144 #define RING_FAULT_VALID (1<<0)
1145 #define DONE_REG 0x40b0
1146 #define GEN8_PRIVATE_PAT 0x40e0
1147 #define BSD_HWS_PGA_GEN7 (0x04180)
1148 #define BLT_HWS_PGA_GEN7 (0x04280)
1149 #define VEBOX_HWS_PGA_GEN7 (0x04380)
1150 #define RING_ACTHD(base) ((base)+0x74)
1151 #define RING_ACTHD_UDW(base) ((base)+0x5c)
1152 #define RING_NOPID(base) ((base)+0x94)
1153 #define RING_IMR(base) ((base)+0xa8)
1154 #define RING_HWSTAM(base) ((base)+0x98)
1155 #define RING_TIMESTAMP(base) ((base)+0x358)
1156 #define TAIL_ADDR 0x001FFFF8
1157 #define HEAD_WRAP_COUNT 0xFFE00000
1158 #define HEAD_WRAP_ONE 0x00200000
1159 #define HEAD_ADDR 0x001FFFFC
1160 #define RING_NR_PAGES 0x001FF000
1161 #define RING_REPORT_MASK 0x00000006
1162 #define RING_REPORT_64K 0x00000002
1163 #define RING_REPORT_128K 0x00000004
1164 #define RING_NO_REPORT 0x00000000
1165 #define RING_VALID_MASK 0x00000001
1166 #define RING_VALID 0x00000001
1167 #define RING_INVALID 0x00000000
1168 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
1169 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
1170 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
1172 #define GEN7_TLB_RD_ADDR 0x4700
1175 #define PRB0_TAIL 0x02030
1176 #define PRB0_HEAD 0x02034
1177 #define PRB0_START 0x02038
1178 #define PRB0_CTL 0x0203c
1179 #define PRB1_TAIL 0x02040 /* 915+ only */
1180 #define PRB1_HEAD 0x02044 /* 915+ only */
1181 #define PRB1_START 0x02048 /* 915+ only */
1182 #define PRB1_CTL 0x0204c /* 915+ only */
1184 #define IPEIR_I965 0x02064
1185 #define IPEHR_I965 0x02068
1186 #define INSTDONE_I965 0x0206c
1187 #define GEN7_INSTDONE_1 0x0206c
1188 #define GEN7_SC_INSTDONE 0x07100
1189 #define GEN7_SAMPLER_INSTDONE 0x0e160
1190 #define GEN7_ROW_INSTDONE 0x0e164
1191 #define I915_NUM_INSTDONE_REG 4
1192 #define RING_IPEIR(base) ((base)+0x64)
1193 #define RING_IPEHR(base) ((base)+0x68)
1194 #define RING_INSTDONE(base) ((base)+0x6c)
1195 #define RING_INSTPS(base) ((base)+0x70)
1196 #define RING_DMA_FADD(base) ((base)+0x78)
1197 #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */
1198 #define RING_INSTPM(base) ((base)+0xc0)
1199 #define RING_MI_MODE(base) ((base)+0x9c)
1200 #define INSTPS 0x02070 /* 965+ only */
1201 #define INSTDONE1 0x0207c /* 965+ only */
1202 #define ACTHD_I965 0x02074
1203 #define HWS_PGA 0x02080
1204 #define HWS_ADDRESS_MASK 0xfffff000
1205 #define HWS_START_ADDRESS_SHIFT 4
1206 #define PWRCTXA 0x2088 /* 965GM+ only */
1207 #define PWRCTX_EN (1<<0)
1208 #define IPEIR 0x02088
1209 #define IPEHR 0x0208c
1210 #define INSTDONE 0x02090
1211 #define NOPID 0x02094
1212 #define HWSTAM 0x02098
1213 #define DMA_FADD_I8XX 0x020d0
1214 #define RING_BBSTATE(base) ((base)+0x110)
1215 #define RING_BBADDR(base) ((base)+0x140)
1216 #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
1218 #define ERROR_GEN6 0x040a0
1219 #define GEN7_ERR_INT 0x44040
1220 #define ERR_INT_POISON (1<<31)
1221 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
1222 #define ERR_INT_PIPE_CRC_DONE_C (1<<8)
1223 #define ERR_INT_FIFO_UNDERRUN_C (1<<6)
1224 #define ERR_INT_PIPE_CRC_DONE_B (1<<5)
1225 #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
1226 #define ERR_INT_PIPE_CRC_DONE_A (1<<2)
1227 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
1228 #define ERR_INT_FIFO_UNDERRUN_A (1<<0)
1229 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
1231 #define FPGA_DBG 0x42300
1232 #define FPGA_DBG_RM_NOCLAIM (1<<31)
1234 #define DERRMR 0x44050
1235 /* Note that HBLANK events are reserved on bdw+ */
1236 #define DERRMR_PIPEA_SCANLINE (1<<0)
1237 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
1238 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
1239 #define DERRMR_PIPEA_VBLANK (1<<3)
1240 #define DERRMR_PIPEA_HBLANK (1<<5)
1241 #define DERRMR_PIPEB_SCANLINE (1<<8)
1242 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
1243 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
1244 #define DERRMR_PIPEB_VBLANK (1<<11)
1245 #define DERRMR_PIPEB_HBLANK (1<<13)
1246 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1247 #define DERRMR_PIPEC_SCANLINE (1<<14)
1248 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
1249 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
1250 #define DERRMR_PIPEC_VBLANK (1<<21)
1251 #define DERRMR_PIPEC_HBLANK (1<<22)
1254 /* GM45+ chicken bits -- debug workaround bits that may be required
1255 * for various sorts of correct behavior. The top 16 bits of each are
1256 * the enables for writing to the corresponding low bit.
1258 #define _3D_CHICKEN 0x02084
1259 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
1260 #define _3D_CHICKEN2 0x0208c
1261 /* Disables pipelining of read flushes past the SF-WIZ interface.
1262 * Required on all Ironlake steppings according to the B-Spec, but the
1263 * particular danger of not doing so is not specified.
1265 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
1266 #define _3D_CHICKEN3 0x02090
1267 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
1268 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
1269 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1270 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
1272 #define MI_MODE 0x0209c
1273 # define VS_TIMER_DISPATCH (1 << 6)
1274 # define MI_FLUSH_ENABLE (1 << 12)
1275 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
1276 # define MODE_IDLE (1 << 9)
1277 # define STOP_RING (1 << 8)
1279 #define GEN6_GT_MODE 0x20d0
1280 #define GEN7_GT_MODE 0x7008
1281 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
1282 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1283 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
1284 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
1285 #define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16)
1286 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
1288 #define GFX_MODE 0x02520
1289 #define GFX_MODE_GEN7 0x0229c
1290 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
1291 #define GFX_RUN_LIST_ENABLE (1<<15)
1292 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
1293 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
1294 #define GFX_REPLAY_MODE (1<<11)
1295 #define GFX_PSMI_GRANULARITY (1<<10)
1296 #define GFX_PPGTT_ENABLE (1<<9)
1298 #define VLV_DISPLAY_BASE 0x180000
1299 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
1301 #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
1302 #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
1303 #define SCPD0 0x0209c /* 915+ only */
1308 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
1309 #define GINT_DIS (1<<22)
1310 #define GCFG_DIS (1<<8)
1311 #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064)
1312 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
1313 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
1314 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
1315 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
1316 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
1317 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
1318 #define VLV_PCBR_ADDR_SHIFT 12
1320 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
1324 #define GM45_ERROR_PAGE_TABLE (1<<5)
1325 #define GM45_ERROR_MEM_PRIV (1<<4)
1326 #define I915_ERROR_PAGE_TABLE (1<<4)
1327 #define GM45_ERROR_CP_PRIV (1<<3)
1328 #define I915_ERROR_MEMORY_REFRESH (1<<1)
1329 #define I915_ERROR_INSTRUCTION (1<<0)
1330 #define INSTPM 0x020c0
1331 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
1332 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
1333 will not assert AGPBUSY# and will only
1334 be delivered when out of C3. */
1335 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
1336 #define INSTPM_TLB_INVALIDATE (1<<9)
1337 #define INSTPM_SYNC_FLUSH (1<<5)
1338 #define ACTHD 0x020c8
1339 #define MEM_MODE 0x020cc
1340 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1341 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1342 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
1343 #define FW_BLC 0x020d8
1344 #define FW_BLC2 0x020dc
1345 #define FW_BLC_SELF 0x020e0 /* 915+ only */
1346 #define FW_BLC_SELF_EN_MASK (1<<31)
1347 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1348 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
1349 #define MM_BURST_LENGTH 0x00700000
1350 #define MM_FIFO_WATERMARK 0x0001F000
1351 #define LM_BURST_LENGTH 0x00000700
1352 #define LM_FIFO_WATERMARK 0x0000001F
1353 #define MI_ARB_STATE 0x020e4 /* 915+ only */
1355 /* Make render/texture TLB fetches lower priorty than associated data
1356 * fetches. This is not turned on by default
1358 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1360 /* Isoch request wait on GTT enable (Display A/B/C streams).
1361 * Make isoch requests stall on the TLB update. May cause
1362 * display underruns (test mode only)
1364 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1366 /* Block grant count for isoch requests when block count is
1367 * set to a finite value.
1369 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1370 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1371 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1372 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1373 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1375 /* Enable render writes to complete in C2/C3/C4 power states.
1376 * If this isn't enabled, render writes are prevented in low
1377 * power states. That seems bad to me.
1379 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1381 /* This acknowledges an async flip immediately instead
1382 * of waiting for 2TLB fetches.
1384 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1386 /* Enables non-sequential data reads through arbiter
1388 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
1390 /* Disable FSB snooping of cacheable write cycles from binner/render
1393 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1395 /* Arbiter time slice for non-isoch streams */
1396 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
1397 #define MI_ARB_TIME_SLICE_1 (0 << 5)
1398 #define MI_ARB_TIME_SLICE_2 (1 << 5)
1399 #define MI_ARB_TIME_SLICE_4 (2 << 5)
1400 #define MI_ARB_TIME_SLICE_6 (3 << 5)
1401 #define MI_ARB_TIME_SLICE_8 (4 << 5)
1402 #define MI_ARB_TIME_SLICE_10 (5 << 5)
1403 #define MI_ARB_TIME_SLICE_14 (6 << 5)
1404 #define MI_ARB_TIME_SLICE_16 (7 << 5)
1406 /* Low priority grace period page size */
1407 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1408 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1410 /* Disable display A/B trickle feed */
1411 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1413 /* Set display plane priority */
1414 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1415 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1417 #define MI_STATE 0x020e4 /* gen2 only */
1418 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1419 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1421 #define CACHE_MODE_0 0x02120 /* 915+ only */
1422 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
1423 #define CM0_IZ_OPT_DISABLE (1<<6)
1424 #define CM0_ZR_OPT_DISABLE (1<<5)
1425 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
1426 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
1427 #define CM0_COLOR_EVICT_DISABLE (1<<3)
1428 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
1429 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1430 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
1431 #define GFX_FLSH_CNTL_GEN6 0x101008
1432 #define GFX_FLSH_CNTL_EN (1<<0)
1433 #define ECOSKPD 0x021d0
1434 #define ECO_GATING_CX_ONLY (1<<3)
1435 #define ECO_FLIP_DONE (1<<0)
1437 #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
1438 #define RC_OP_FLUSH_ENABLE (1<<0)
1439 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
1440 #define CACHE_MODE_1 0x7004 /* IVB+ */
1441 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1442 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
1444 #define GEN6_BLITTER_ECOSKPD 0x221d0
1445 #define GEN6_BLITTER_LOCK_SHIFT 16
1446 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
1448 #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
1449 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
1450 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
1452 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
1453 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
1454 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
1455 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
1456 #define GEN6_BSD_GO_INDICATOR (1 << 4)
1458 /* On modern GEN architectures interrupt control consists of two sets
1459 * of registers. The first set pertains to the ring generating the
1460 * interrupt. The second control is for the functional block generating the
1461 * interrupt. These are PM, GT, DE, etc.
1463 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1464 * GT interrupt bits, so we don't need to duplicate the defines.
1466 * These defines should cover us well from SNB->HSW with minor exceptions
1467 * it can also work on ILK.
1469 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1470 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1471 #define GT_BLT_USER_INTERRUPT (1 << 22)
1472 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1473 #define GT_BSD_USER_INTERRUPT (1 << 12)
1474 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1475 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
1476 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1477 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1478 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
1479 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1480 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1481 #define GT_RENDER_USER_INTERRUPT (1 << 0)
1483 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1484 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1486 #define GT_PARITY_ERROR(dev) \
1487 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
1488 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1490 /* These are all the "old" interrupts */
1491 #define ILK_BSD_USER_INTERRUPT (1<<5)
1493 #define I915_PM_INTERRUPT (1<<31)
1494 #define I915_ISP_INTERRUPT (1<<22)
1495 #define I915_LPE_PIPE_B_INTERRUPT (1<<21)
1496 #define I915_LPE_PIPE_A_INTERRUPT (1<<20)
1497 #define I915_MIPIB_INTERRUPT (1<<19)
1498 #define I915_MIPIA_INTERRUPT (1<<18)
1499 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1500 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
1501 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
1502 #define I915_MASTER_ERROR_INTERRUPT (1<<15)
1503 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
1504 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
1505 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
1506 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
1507 #define I915_HWB_OOM_INTERRUPT (1<<13)
1508 #define I915_LPE_PIPE_C_INTERRUPT (1<<12)
1509 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
1510 #define I915_MISC_INTERRUPT (1<<11)
1511 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
1512 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
1513 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
1514 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
1515 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
1516 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
1517 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1518 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1519 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1520 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1521 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
1522 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
1523 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
1524 #define I915_DEBUG_INTERRUPT (1<<2)
1525 #define I915_WINVALID_INTERRUPT (1<<1)
1526 #define I915_USER_INTERRUPT (1<<1)
1527 #define I915_ASLE_INTERRUPT (1<<0)
1528 #define I915_BSD_USER_INTERRUPT (1<<25)
1530 #define GEN6_BSD_RNCID 0x12198
1532 #define GEN7_FF_THREAD_MODE 0x20a0
1533 #define GEN7_FF_SCHED_MASK 0x0077070
1534 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
1535 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1536 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1537 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1538 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
1539 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
1540 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1541 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1542 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
1543 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
1544 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1545 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1546 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
1547 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
1550 * Framebuffer compression (915+ only)
1553 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1554 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
1555 #define FBC_CONTROL 0x03208
1556 #define FBC_CTL_EN (1<<31)
1557 #define FBC_CTL_PERIODIC (1<<30)
1558 #define FBC_CTL_INTERVAL_SHIFT (16)
1559 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
1560 #define FBC_CTL_C3_IDLE (1<<13)
1561 #define FBC_CTL_STRIDE_SHIFT (5)
1562 #define FBC_CTL_FENCENO_SHIFT (0)
1563 #define FBC_COMMAND 0x0320c
1564 #define FBC_CMD_COMPRESS (1<<0)
1565 #define FBC_STATUS 0x03210
1566 #define FBC_STAT_COMPRESSING (1<<31)
1567 #define FBC_STAT_COMPRESSED (1<<30)
1568 #define FBC_STAT_MODIFIED (1<<29)
1569 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
1570 #define FBC_CONTROL2 0x03214
1571 #define FBC_CTL_FENCE_DBL (0<<4)
1572 #define FBC_CTL_IDLE_IMM (0<<2)
1573 #define FBC_CTL_IDLE_FULL (1<<2)
1574 #define FBC_CTL_IDLE_LINE (2<<2)
1575 #define FBC_CTL_IDLE_DEBUG (3<<2)
1576 #define FBC_CTL_CPU_FENCE (1<<1)
1577 #define FBC_CTL_PLANE(plane) ((plane)<<0)
1578 #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */
1579 #define FBC_TAG 0x03300
1581 #define FBC_LL_SIZE (1536)
1583 /* Framebuffer compression for GM45+ */
1584 #define DPFC_CB_BASE 0x3200
1585 #define DPFC_CONTROL 0x3208
1586 #define DPFC_CTL_EN (1<<31)
1587 #define DPFC_CTL_PLANE(plane) ((plane)<<30)
1588 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
1589 #define DPFC_CTL_FENCE_EN (1<<29)
1590 #define IVB_DPFC_CTL_FENCE_EN (1<<28)
1591 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
1592 #define DPFC_SR_EN (1<<10)
1593 #define DPFC_CTL_LIMIT_1X (0<<6)
1594 #define DPFC_CTL_LIMIT_2X (1<<6)
1595 #define DPFC_CTL_LIMIT_4X (2<<6)
1596 #define DPFC_RECOMP_CTL 0x320c
1597 #define DPFC_RECOMP_STALL_EN (1<<27)
1598 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
1599 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
1600 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
1601 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
1602 #define DPFC_STATUS 0x3210
1603 #define DPFC_INVAL_SEG_SHIFT (16)
1604 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
1605 #define DPFC_COMP_SEG_SHIFT (0)
1606 #define DPFC_COMP_SEG_MASK (0x000003ff)
1607 #define DPFC_STATUS2 0x3214
1608 #define DPFC_FENCE_YOFF 0x3218
1609 #define DPFC_CHICKEN 0x3224
1610 #define DPFC_HT_MODIFY (1<<31)
1612 /* Framebuffer compression for Ironlake */
1613 #define ILK_DPFC_CB_BASE 0x43200
1614 #define ILK_DPFC_CONTROL 0x43208
1615 #define FBC_CTL_FALSE_COLOR (1<<10)
1616 /* The bit 28-8 is reserved */
1617 #define DPFC_RESERVED (0x1FFFFF00)
1618 #define ILK_DPFC_RECOMP_CTL 0x4320c
1619 #define ILK_DPFC_STATUS 0x43210
1620 #define ILK_DPFC_FENCE_YOFF 0x43218
1621 #define ILK_DPFC_CHICKEN 0x43224
1622 #define ILK_FBC_RT_BASE 0x2128
1623 #define ILK_FBC_RT_VALID (1<<0)
1624 #define SNB_FBC_FRONT_BUFFER (1<<1)
1626 #define ILK_DISPLAY_CHICKEN1 0x42000
1627 #define ILK_FBCQ_DIS (1<<22)
1628 #define ILK_PABSTRETCH_DIS (1<<21)
1632 * Framebuffer compression for Sandybridge
1634 * The following two registers are of type GTTMMADR
1636 #define SNB_DPFC_CTL_SA 0x100100
1637 #define SNB_CPU_FENCE_ENABLE (1<<29)
1638 #define DPFC_CPU_FENCE_OFFSET 0x100104
1640 /* Framebuffer compression for Ivybridge */
1641 #define IVB_FBC_RT_BASE 0x7020
1643 #define IPS_CTL 0x43408
1644 #define IPS_ENABLE (1 << 31)
1646 #define MSG_FBC_REND_STATE 0x50380
1647 #define FBC_REND_NUKE (1<<2)
1648 #define FBC_REND_CACHE_CLEAN (1<<1)
1653 #define GPIOA 0x5010
1654 #define GPIOB 0x5014
1655 #define GPIOC 0x5018
1656 #define GPIOD 0x501c
1657 #define GPIOE 0x5020
1658 #define GPIOF 0x5024
1659 #define GPIOG 0x5028
1660 #define GPIOH 0x502c
1661 # define GPIO_CLOCK_DIR_MASK (1 << 0)
1662 # define GPIO_CLOCK_DIR_IN (0 << 1)
1663 # define GPIO_CLOCK_DIR_OUT (1 << 1)
1664 # define GPIO_CLOCK_VAL_MASK (1 << 2)
1665 # define GPIO_CLOCK_VAL_OUT (1 << 3)
1666 # define GPIO_CLOCK_VAL_IN (1 << 4)
1667 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1668 # define GPIO_DATA_DIR_MASK (1 << 8)
1669 # define GPIO_DATA_DIR_IN (0 << 9)
1670 # define GPIO_DATA_DIR_OUT (1 << 9)
1671 # define GPIO_DATA_VAL_MASK (1 << 10)
1672 # define GPIO_DATA_VAL_OUT (1 << 11)
1673 # define GPIO_DATA_VAL_IN (1 << 12)
1674 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1676 #define GMBUS0 0x5100 /* clock/port select */
1677 #define GMBUS_RATE_100KHZ (0<<8)
1678 #define GMBUS_RATE_50KHZ (1<<8)
1679 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
1680 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
1681 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
1682 #define GMBUS_PORT_DISABLED 0
1683 #define GMBUS_PORT_SSC 1
1684 #define GMBUS_PORT_VGADDC 2
1685 #define GMBUS_PORT_PANEL 3
1686 #define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */
1687 #define GMBUS_PORT_DPC 4 /* HDMIC */
1688 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
1689 #define GMBUS_PORT_DPD 6 /* HDMID */
1690 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */
1691 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
1692 #define GMBUS1 0x5104 /* command/status */
1693 #define GMBUS_SW_CLR_INT (1<<31)
1694 #define GMBUS_SW_RDY (1<<30)
1695 #define GMBUS_ENT (1<<29) /* enable timeout */
1696 #define GMBUS_CYCLE_NONE (0<<25)
1697 #define GMBUS_CYCLE_WAIT (1<<25)
1698 #define GMBUS_CYCLE_INDEX (2<<25)
1699 #define GMBUS_CYCLE_STOP (4<<25)
1700 #define GMBUS_BYTE_COUNT_SHIFT 16
1701 #define GMBUS_SLAVE_INDEX_SHIFT 8
1702 #define GMBUS_SLAVE_ADDR_SHIFT 1
1703 #define GMBUS_SLAVE_READ (1<<0)
1704 #define GMBUS_SLAVE_WRITE (0<<0)
1705 #define GMBUS2 0x5108 /* status */
1706 #define GMBUS_INUSE (1<<15)
1707 #define GMBUS_HW_WAIT_PHASE (1<<14)
1708 #define GMBUS_STALL_TIMEOUT (1<<13)
1709 #define GMBUS_INT (1<<12)
1710 #define GMBUS_HW_RDY (1<<11)
1711 #define GMBUS_SATOER (1<<10)
1712 #define GMBUS_ACTIVE (1<<9)
1713 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
1714 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
1715 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1716 #define GMBUS_NAK_EN (1<<3)
1717 #define GMBUS_IDLE_EN (1<<2)
1718 #define GMBUS_HW_WAIT_EN (1<<1)
1719 #define GMBUS_HW_RDY_EN (1<<0)
1720 #define GMBUS5 0x5120 /* byte index */
1721 #define GMBUS_2BYTE_INDEX_EN (1<<31)
1724 * Clock control & power management
1726 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
1727 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
1728 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
1729 #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
1733 #define VGA_PD 0x6010
1734 #define VGA0_PD_P2_DIV_4 (1 << 7)
1735 #define VGA0_PD_P1_DIV_2 (1 << 5)
1736 #define VGA0_PD_P1_SHIFT 0
1737 #define VGA0_PD_P1_MASK (0x1f << 0)
1738 #define VGA1_PD_P2_DIV_4 (1 << 15)
1739 #define VGA1_PD_P1_DIV_2 (1 << 13)
1740 #define VGA1_PD_P1_SHIFT 8
1741 #define VGA1_PD_P1_MASK (0x1f << 8)
1742 #define DPLL_VCO_ENABLE (1 << 31)
1743 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
1744 #define DPLL_DVO_2X_MODE (1 << 30)
1745 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
1746 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
1747 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
1748 #define DPLL_VGA_MODE_DIS (1 << 28)
1749 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1750 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1751 #define DPLL_MODE_MASK (3 << 26)
1752 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1753 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1754 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1755 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1756 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1757 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1758 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
1759 #define DPLL_LOCK_VLV (1<<15)
1760 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
1761 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
1762 #define DPLL_SSC_REF_CLOCK_CHV (1<<13)
1763 #define DPLL_PORTC_READY_MASK (0xf << 4)
1764 #define DPLL_PORTB_READY_MASK (0xf)
1766 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1768 /* Additional CHV pll/phy registers */
1769 #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)
1770 #define DPLL_PORTD_READY_MASK (0xf)
1771 #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
1772 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
1773 #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
1774 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
1777 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1778 * this field (only one bit may be set).
1780 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1781 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1782 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1783 /* i830, required in DVO non-gang */
1784 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
1785 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1786 #define PLL_REF_INPUT_DREFCLK (0 << 13)
1787 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1788 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1789 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1790 #define PLL_REF_INPUT_MASK (3 << 13)
1791 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
1793 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1794 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1795 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
1796 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1797 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1800 * Parallel to Serial Load Pulse phase selection.
1801 * Selects the phase for the 10X DPLL clock for the PCIe
1802 * digital display port. The range is 4 to 13; 10 or more
1803 * is just a flip delay. The default is 6
1805 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1806 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1808 * SDVO multiplier for 945G/GM. Not used on 965.
1810 #define SDVO_MULTIPLIER_MASK 0x000000ff
1811 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
1812 #define SDVO_MULTIPLIER_SHIFT_VGA 0
1814 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
1815 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
1816 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
1817 #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
1820 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1822 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1824 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1825 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
1826 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1827 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1828 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1830 * SDVO/UDI pixel multiplier.
1832 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1833 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1834 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1835 * dummy bytes in the datastream at an increased clock rate, with both sides of
1836 * the link knowing how many bytes are fill.
1838 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1839 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1840 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1841 * through an SDVO command.
1843 * This register field has values of multiplication factor minus 1, with
1844 * a maximum multiplier of 5 for SDVO.
1846 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1847 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1849 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1850 * This best be set to the default value (3) or the CRT won't work. No,
1851 * I don't entirely understand what this does...
1853 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1854 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1856 #define _FPA0 0x06040
1857 #define _FPA1 0x06044
1858 #define _FPB0 0x06048
1859 #define _FPB1 0x0604c
1860 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1861 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1862 #define FP_N_DIV_MASK 0x003f0000
1863 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1864 #define FP_N_DIV_SHIFT 16
1865 #define FP_M1_DIV_MASK 0x00003f00
1866 #define FP_M1_DIV_SHIFT 8
1867 #define FP_M2_DIV_MASK 0x0000003f
1868 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1869 #define FP_M2_DIV_SHIFT 0
1870 #define DPLL_TEST 0x606c
1871 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1872 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1873 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1874 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1875 #define DPLLB_TEST_N_BYPASS (1 << 19)
1876 #define DPLLB_TEST_M_BYPASS (1 << 18)
1877 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1878 #define DPLLA_TEST_N_BYPASS (1 << 3)
1879 #define DPLLA_TEST_M_BYPASS (1 << 2)
1880 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1881 #define D_STATE 0x6104
1882 #define DSTATE_GFX_RESET_I830 (1<<6)
1883 #define DSTATE_PLL_D3_OFF (1<<3)
1884 #define DSTATE_GFX_CLOCK_GATING (1<<1)
1885 #define DSTATE_DOT_CLOCK_GATING (1<<0)
1886 #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
1887 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1888 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1889 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1890 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1891 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1892 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1893 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1894 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1895 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1896 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1897 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1898 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1899 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1900 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1901 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1902 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1903 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1904 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1905 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1906 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1907 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1908 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1909 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1910 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1911 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1912 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1913 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1914 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1916 * This bit must be set on the 830 to prevent hangs when turning off the
1919 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1920 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1921 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1922 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1923 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1925 #define RENCLK_GATE_D1 0x6204
1926 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1927 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1928 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1929 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1930 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1931 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1932 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1933 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1934 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
1935 /* This bit must be unset on 855,865 */
1936 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
1937 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1938 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
1939 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
1940 /* This bit must be set on 855,865. */
1941 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1942 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1943 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1944 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1945 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1946 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1947 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1948 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1949 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1950 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1951 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1952 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1953 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1954 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1955 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1956 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1957 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1958 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1960 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1961 /* This bit must always be set on 965G/965GM */
1962 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1963 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1964 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1965 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1966 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1967 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1968 /* This bit must always be set on 965G */
1969 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1970 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1971 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1972 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1973 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1974 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1975 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1976 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1977 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1978 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1979 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1980 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1981 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1982 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1983 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1984 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1985 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1986 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1987 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1989 #define RENCLK_GATE_D2 0x6208
1990 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1991 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1992 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1994 #define VDECCLK_GATE_D 0x620C /* g4x only */
1995 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
1997 #define RAMCLK_GATE_D 0x6210 /* CRL only */
1998 #define DEUC 0x6214 /* CRL only */
2000 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
2001 #define FW_CSPWRDWNEN (1<<15)
2003 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
2005 #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
2006 #define CDCLK_FREQ_SHIFT 4
2007 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
2008 #define CZCLK_FREQ_MASK 0xf
2009 #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
2014 #define PALETTE_A_OFFSET 0xa000
2015 #define PALETTE_B_OFFSET 0xa800
2016 #define CHV_PALETTE_C_OFFSET 0xc000
2017 #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
2018 dev_priv->info.display_mmio_offset)
2020 /* MCH MMIO space */
2025 * This mirrors the MCHBAR MMIO space whose location is determined by
2026 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
2027 * every way. It is not accessible from the CP register read instructions.
2029 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
2032 #define MCHBAR_MIRROR_BASE 0x10000
2034 #define MCHBAR_MIRROR_BASE_SNB 0x140000
2036 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
2037 #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
2039 /* 915-945 and GM965 MCH register controlling DRAM channel access */
2041 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
2042 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
2043 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
2044 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
2045 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
2046 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
2047 #define DCC2 0x10204
2048 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
2050 /* Pineview MCH register contains DDR3 setting */
2051 #define CSHRDDR3CTL 0x101a8
2052 #define CSHRDDR3CTL_DDR3 (1 << 2)
2054 /* 965 MCH register controlling DRAM channel configuration */
2055 #define C0DRB3 0x10206
2056 #define C1DRB3 0x10606
2058 /* snb MCH registers for reading the DRAM channel configuration */
2059 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
2060 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
2061 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
2062 #define MAD_DIMM_ECC_MASK (0x3 << 24)
2063 #define MAD_DIMM_ECC_OFF (0x0 << 24)
2064 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
2065 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
2066 #define MAD_DIMM_ECC_ON (0x3 << 24)
2067 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
2068 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
2069 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
2070 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
2071 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
2072 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
2073 #define MAD_DIMM_A_SELECT (0x1 << 16)
2074 /* DIMM sizes are in multiples of 256mb. */
2075 #define MAD_DIMM_B_SIZE_SHIFT 8
2076 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
2077 #define MAD_DIMM_A_SIZE_SHIFT 0
2078 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
2080 /* snb MCH registers for priority tuning */
2081 #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
2082 #define MCH_SSKPD_WM0_MASK 0x3f
2083 #define MCH_SSKPD_WM0_VAL 0xc
2085 #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
2087 /* Clocking configuration register */
2088 #define CLKCFG 0x10c00
2089 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
2090 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
2091 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
2092 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
2093 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
2094 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
2095 /* Note, below two are guess */
2096 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
2097 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
2098 #define CLKCFG_FSB_MASK (7 << 0)
2099 #define CLKCFG_MEM_533 (1 << 4)
2100 #define CLKCFG_MEM_667 (2 << 4)
2101 #define CLKCFG_MEM_800 (3 << 4)
2102 #define CLKCFG_MEM_MASK (7 << 4)
2104 #define TSC1 0x11001
2107 #define TSFS 0x11020
2108 #define TSFS_SLOPE_MASK 0x0000ff00
2109 #define TSFS_SLOPE_SHIFT 8
2110 #define TSFS_INTR_MASK 0x000000ff
2112 #define CRSTANDVID 0x11100
2113 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2114 #define PXVFREQ_PX_MASK 0x7f000000
2115 #define PXVFREQ_PX_SHIFT 24
2116 #define VIDFREQ_BASE 0x11110
2117 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2118 #define VIDFREQ2 0x11114
2119 #define VIDFREQ3 0x11118
2120 #define VIDFREQ4 0x1111c
2121 #define VIDFREQ_P0_MASK 0x1f000000
2122 #define VIDFREQ_P0_SHIFT 24
2123 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
2124 #define VIDFREQ_P0_CSCLK_SHIFT 20
2125 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
2126 #define VIDFREQ_P0_CRCLK_SHIFT 16
2127 #define VIDFREQ_P1_MASK 0x00001f00
2128 #define VIDFREQ_P1_SHIFT 8
2129 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2130 #define VIDFREQ_P1_CSCLK_SHIFT 4
2131 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
2132 #define INTTOEXT_BASE_ILK 0x11300
2133 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
2134 #define INTTOEXT_MAP3_SHIFT 24
2135 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2136 #define INTTOEXT_MAP2_SHIFT 16
2137 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
2138 #define INTTOEXT_MAP1_SHIFT 8
2139 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2140 #define INTTOEXT_MAP0_SHIFT 0
2141 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
2142 #define MEMSWCTL 0x11170 /* Ironlake only */
2143 #define MEMCTL_CMD_MASK 0xe000
2144 #define MEMCTL_CMD_SHIFT 13
2145 #define MEMCTL_CMD_RCLK_OFF 0
2146 #define MEMCTL_CMD_RCLK_ON 1
2147 #define MEMCTL_CMD_CHFREQ 2
2148 #define MEMCTL_CMD_CHVID 3
2149 #define MEMCTL_CMD_VMMOFF 4
2150 #define MEMCTL_CMD_VMMON 5
2151 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
2152 when command complete */
2153 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
2154 #define MEMCTL_FREQ_SHIFT 8
2155 #define MEMCTL_SFCAVM (1<<7)
2156 #define MEMCTL_TGT_VID_MASK 0x007f
2157 #define MEMIHYST 0x1117c
2158 #define MEMINTREN 0x11180 /* 16 bits */
2159 #define MEMINT_RSEXIT_EN (1<<8)
2160 #define MEMINT_CX_SUPR_EN (1<<7)
2161 #define MEMINT_CONT_BUSY_EN (1<<6)
2162 #define MEMINT_AVG_BUSY_EN (1<<5)
2163 #define MEMINT_EVAL_CHG_EN (1<<4)
2164 #define MEMINT_MON_IDLE_EN (1<<3)
2165 #define MEMINT_UP_EVAL_EN (1<<2)
2166 #define MEMINT_DOWN_EVAL_EN (1<<1)
2167 #define MEMINT_SW_CMD_EN (1<<0)
2168 #define MEMINTRSTR 0x11182 /* 16 bits */
2169 #define MEM_RSEXIT_MASK 0xc000
2170 #define MEM_RSEXIT_SHIFT 14
2171 #define MEM_CONT_BUSY_MASK 0x3000
2172 #define MEM_CONT_BUSY_SHIFT 12
2173 #define MEM_AVG_BUSY_MASK 0x0c00
2174 #define MEM_AVG_BUSY_SHIFT 10
2175 #define MEM_EVAL_CHG_MASK 0x0300
2176 #define MEM_EVAL_BUSY_SHIFT 8
2177 #define MEM_MON_IDLE_MASK 0x00c0
2178 #define MEM_MON_IDLE_SHIFT 6
2179 #define MEM_UP_EVAL_MASK 0x0030
2180 #define MEM_UP_EVAL_SHIFT 4
2181 #define MEM_DOWN_EVAL_MASK 0x000c
2182 #define MEM_DOWN_EVAL_SHIFT 2
2183 #define MEM_SW_CMD_MASK 0x0003
2184 #define MEM_INT_STEER_GFX 0
2185 #define MEM_INT_STEER_CMR 1
2186 #define MEM_INT_STEER_SMI 2
2187 #define MEM_INT_STEER_SCI 3
2188 #define MEMINTRSTS 0x11184
2189 #define MEMINT_RSEXIT (1<<7)
2190 #define MEMINT_CONT_BUSY (1<<6)
2191 #define MEMINT_AVG_BUSY (1<<5)
2192 #define MEMINT_EVAL_CHG (1<<4)
2193 #define MEMINT_MON_IDLE (1<<3)
2194 #define MEMINT_UP_EVAL (1<<2)
2195 #define MEMINT_DOWN_EVAL (1<<1)
2196 #define MEMINT_SW_CMD (1<<0)
2197 #define MEMMODECTL 0x11190
2198 #define MEMMODE_BOOST_EN (1<<31)
2199 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2200 #define MEMMODE_BOOST_FREQ_SHIFT 24
2201 #define MEMMODE_IDLE_MODE_MASK 0x00030000
2202 #define MEMMODE_IDLE_MODE_SHIFT 16
2203 #define MEMMODE_IDLE_MODE_EVAL 0
2204 #define MEMMODE_IDLE_MODE_CONT 1
2205 #define MEMMODE_HWIDLE_EN (1<<15)
2206 #define MEMMODE_SWMODE_EN (1<<14)
2207 #define MEMMODE_RCLK_GATE (1<<13)
2208 #define MEMMODE_HW_UPDATE (1<<12)
2209 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
2210 #define MEMMODE_FSTART_SHIFT 8
2211 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2212 #define MEMMODE_FMAX_SHIFT 4
2213 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
2214 #define RCBMAXAVG 0x1119c
2215 #define MEMSWCTL2 0x1119e /* Cantiga only */
2216 #define SWMEMCMD_RENDER_OFF (0 << 13)
2217 #define SWMEMCMD_RENDER_ON (1 << 13)
2218 #define SWMEMCMD_SWFREQ (2 << 13)
2219 #define SWMEMCMD_TARVID (3 << 13)
2220 #define SWMEMCMD_VRM_OFF (4 << 13)
2221 #define SWMEMCMD_VRM_ON (5 << 13)
2222 #define CMDSTS (1<<12)
2223 #define SFCAVM (1<<11)
2224 #define SWFREQ_MASK 0x0380 /* P0-7 */
2225 #define SWFREQ_SHIFT 7
2226 #define TARVID_MASK 0x001f
2227 #define MEMSTAT_CTG 0x111a0
2228 #define RCBMINAVG 0x111a0
2229 #define RCUPEI 0x111b0
2230 #define RCDNEI 0x111b4
2231 #define RSTDBYCTL 0x111b8
2232 #define RS1EN (1<<31)
2233 #define RS2EN (1<<30)
2234 #define RS3EN (1<<29)
2235 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
2236 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
2237 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
2238 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
2239 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
2240 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
2241 #define RSX_STATUS_MASK (7<<20)
2242 #define RSX_STATUS_ON (0<<20)
2243 #define RSX_STATUS_RC1 (1<<20)
2244 #define RSX_STATUS_RC1E (2<<20)
2245 #define RSX_STATUS_RS1 (3<<20)
2246 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
2247 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
2248 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
2249 #define RSX_STATUS_RSVD2 (7<<20)
2250 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
2251 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
2252 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
2253 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
2254 #define RS1CONTSAV_MASK (3<<14)
2255 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
2256 #define RS1CONTSAV_RSVD (1<<14)
2257 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
2258 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
2259 #define NORMSLEXLAT_MASK (3<<12)
2260 #define SLOW_RS123 (0<<12)
2261 #define SLOW_RS23 (1<<12)
2262 #define SLOW_RS3 (2<<12)
2263 #define NORMAL_RS123 (3<<12)
2264 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
2265 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2266 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
2267 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
2268 #define RS_CSTATE_MASK (3<<4)
2269 #define RS_CSTATE_C367_RS1 (0<<4)
2270 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2271 #define RS_CSTATE_RSVD (2<<4)
2272 #define RS_CSTATE_C367_RS2 (3<<4)
2273 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2274 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
2275 #define VIDCTL 0x111c0
2276 #define VIDSTS 0x111c8
2277 #define VIDSTART 0x111cc /* 8 bits */
2278 #define MEMSTAT_ILK 0x111f8
2279 #define MEMSTAT_VID_MASK 0x7f00
2280 #define MEMSTAT_VID_SHIFT 8
2281 #define MEMSTAT_PSTATE_MASK 0x00f8
2282 #define MEMSTAT_PSTATE_SHIFT 3
2283 #define MEMSTAT_MON_ACTV (1<<2)
2284 #define MEMSTAT_SRC_CTL_MASK 0x0003
2285 #define MEMSTAT_SRC_CTL_CORE 0
2286 #define MEMSTAT_SRC_CTL_TRB 1
2287 #define MEMSTAT_SRC_CTL_THM 2
2288 #define MEMSTAT_SRC_CTL_STDBY 3
2289 #define RCPREVBSYTUPAVG 0x113b8
2290 #define RCPREVBSYTDNAVG 0x113bc
2291 #define PMMISC 0x11214
2292 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
2293 #define SDEW 0x1124c
2294 #define CSIEW0 0x11250
2295 #define CSIEW1 0x11254
2296 #define CSIEW2 0x11258
2299 #define MCHAFE 0x112c0
2300 #define CSIEC 0x112e0
2301 #define DMIEC 0x112e4
2302 #define DDREC 0x112e8
2303 #define PEG0EC 0x112ec
2304 #define PEG1EC 0x112f0
2305 #define GFXEC 0x112f4
2306 #define RPPREVBSYTUPAVG 0x113b8
2307 #define RPPREVBSYTDNAVG 0x113bc
2309 #define ECR_GPFE (1<<31)
2310 #define ECR_IMONE (1<<30)
2311 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
2312 #define OGW0 0x11608
2313 #define OGW1 0x1160c
2323 #define PXWL 0x11680
2324 #define LCFUSE02 0x116c0
2325 #define LCFUSE_HIV_MASK 0x000000ff
2326 #define CSIPLL0 0x12c10
2327 #define DDRMPLL1 0X12c20
2328 #define PEG_BAND_GAP_DATA 0x14d68
2330 #define GEN6_GT_THREAD_STATUS_REG 0x13805c
2331 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2333 #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
2334 #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
2335 #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
2338 * Logical Context regs
2341 #define CCID_EN (1<<0)
2343 * Notes on SNB/IVB/VLV context size:
2344 * - Power context is saved elsewhere (LLC or stolen)
2345 * - Ring/execlist context is saved on SNB, not on IVB
2346 * - Extended context size already includes render context size
2347 * - We always need to follow the extended context size.
2348 * SNB BSpec has comments indicating that we should use the
2349 * render context size instead if execlists are disabled, but
2350 * based on empirical testing that's just nonsense.
2351 * - Pipelined/VF state is saved on SNB/IVB respectively
2352 * - GT1 size just indicates how much of render context
2353 * doesn't need saving on GT1
2355 #define CXT_SIZE 0x21a0
2356 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
2357 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
2358 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
2359 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
2360 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
2361 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
2362 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2363 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
2364 #define GEN7_CXT_SIZE 0x21a8
2365 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
2366 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
2367 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
2368 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
2369 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
2370 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
2371 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
2372 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
2373 /* Haswell does have the CXT_SIZE register however it does not appear to be
2374 * valid. Now, docs explain in dwords what is in the context object. The full
2375 * size is 70720 bytes, however, the power context and execlist context will
2376 * never be saved (power context is stored elsewhere, and execlists don't work
2377 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
2379 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
2380 /* Same as Haswell, but 72064 bytes now. */
2381 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
2383 #define CHV_CLK_CTL1 0x101100
2384 #define VLV_CLK_CTL2 0x101104
2385 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
2391 #define OVADD 0x30000
2392 #define DOVSTA 0x30008
2393 #define OC_BUF (0x3<<20)
2394 #define OGAMC5 0x30010
2395 #define OGAMC4 0x30014
2396 #define OGAMC3 0x30018
2397 #define OGAMC2 0x3001c
2398 #define OGAMC1 0x30020
2399 #define OGAMC0 0x30024
2402 * Display engine regs
2405 /* Pipe A CRC regs */
2406 #define _PIPE_CRC_CTL_A 0x60050
2407 #define PIPE_CRC_ENABLE (1 << 31)
2408 /* ivb+ source selection */
2409 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
2410 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
2411 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
2412 /* ilk+ source selection */
2413 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
2414 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
2415 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
2416 /* embedded DP port on the north display block, reserved on ivb */
2417 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
2418 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
2419 /* vlv source selection */
2420 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
2421 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
2422 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
2423 /* with DP port the pipe source is invalid */
2424 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
2425 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
2426 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
2427 /* gen3+ source selection */
2428 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
2429 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
2430 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
2431 /* with DP/TV port the pipe source is invalid */
2432 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
2433 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
2434 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
2435 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
2436 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
2437 /* gen2 doesn't have source selection bits */
2438 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
2440 #define _PIPE_CRC_RES_1_A_IVB 0x60064
2441 #define _PIPE_CRC_RES_2_A_IVB 0x60068
2442 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
2443 #define _PIPE_CRC_RES_4_A_IVB 0x60070
2444 #define _PIPE_CRC_RES_5_A_IVB 0x60074
2446 #define _PIPE_CRC_RES_RED_A 0x60060
2447 #define _PIPE_CRC_RES_GREEN_A 0x60064
2448 #define _PIPE_CRC_RES_BLUE_A 0x60068
2449 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
2450 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
2452 /* Pipe B CRC regs */
2453 #define _PIPE_CRC_RES_1_B_IVB 0x61064
2454 #define _PIPE_CRC_RES_2_B_IVB 0x61068
2455 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
2456 #define _PIPE_CRC_RES_4_B_IVB 0x61070
2457 #define _PIPE_CRC_RES_5_B_IVB 0x61074
2459 #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
2460 #define PIPE_CRC_RES_1_IVB(pipe) \
2461 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
2462 #define PIPE_CRC_RES_2_IVB(pipe) \
2463 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
2464 #define PIPE_CRC_RES_3_IVB(pipe) \
2465 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
2466 #define PIPE_CRC_RES_4_IVB(pipe) \
2467 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
2468 #define PIPE_CRC_RES_5_IVB(pipe) \
2469 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
2471 #define PIPE_CRC_RES_RED(pipe) \
2472 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
2473 #define PIPE_CRC_RES_GREEN(pipe) \
2474 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
2475 #define PIPE_CRC_RES_BLUE(pipe) \
2476 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
2477 #define PIPE_CRC_RES_RES1_I915(pipe) \
2478 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
2479 #define PIPE_CRC_RES_RES2_G4X(pipe) \
2480 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
2482 /* Pipe A timing regs */
2483 #define _HTOTAL_A 0x60000
2484 #define _HBLANK_A 0x60004
2485 #define _HSYNC_A 0x60008
2486 #define _VTOTAL_A 0x6000c
2487 #define _VBLANK_A 0x60010
2488 #define _VSYNC_A 0x60014
2489 #define _PIPEASRC 0x6001c
2490 #define _BCLRPAT_A 0x60020
2491 #define _VSYNCSHIFT_A 0x60028
2492 #define _PIPE_MULT_A 0x6002c
2494 /* Pipe B timing regs */
2495 #define _HTOTAL_B 0x61000
2496 #define _HBLANK_B 0x61004
2497 #define _HSYNC_B 0x61008
2498 #define _VTOTAL_B 0x6100c
2499 #define _VBLANK_B 0x61010
2500 #define _VSYNC_B 0x61014
2501 #define _PIPEBSRC 0x6101c
2502 #define _BCLRPAT_B 0x61020
2503 #define _VSYNCSHIFT_B 0x61028
2504 #define _PIPE_MULT_B 0x6102c
2506 #define TRANSCODER_A_OFFSET 0x60000
2507 #define TRANSCODER_B_OFFSET 0x61000
2508 #define TRANSCODER_C_OFFSET 0x62000
2509 #define CHV_TRANSCODER_C_OFFSET 0x63000
2510 #define TRANSCODER_EDP_OFFSET 0x6f000
2512 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
2513 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
2514 dev_priv->info.display_mmio_offset)
2516 #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
2517 #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
2518 #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
2519 #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
2520 #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
2521 #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
2522 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
2523 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
2524 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
2525 #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
2527 /* HSW+ eDP PSR registers */
2528 #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
2529 #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
2530 #define EDP_PSR_ENABLE (1<<31)
2531 #define BDW_PSR_SINGLE_FRAME (1<<30)
2532 #define EDP_PSR_LINK_DISABLE (0<<27)
2533 #define EDP_PSR_LINK_STANDBY (1<<27)
2534 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
2535 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
2536 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
2537 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
2538 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
2539 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
2540 #define EDP_PSR_SKIP_AUX_EXIT (1<<12)
2541 #define EDP_PSR_TP1_TP2_SEL (0<<11)
2542 #define EDP_PSR_TP1_TP3_SEL (1<<11)
2543 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
2544 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
2545 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
2546 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
2547 #define EDP_PSR_TP1_TIME_500us (0<<4)
2548 #define EDP_PSR_TP1_TIME_100us (1<<4)
2549 #define EDP_PSR_TP1_TIME_2500us (2<<4)
2550 #define EDP_PSR_TP1_TIME_0us (3<<4)
2551 #define EDP_PSR_IDLE_FRAME_SHIFT 0
2553 #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
2554 #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
2555 #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
2556 #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
2557 #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
2558 #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
2560 #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
2561 #define EDP_PSR_STATUS_STATE_MASK (7<<29)
2562 #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
2563 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
2564 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
2565 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
2566 #define EDP_PSR_STATUS_STATE_BUFON (4<<29)
2567 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
2568 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
2569 #define EDP_PSR_STATUS_LINK_MASK (3<<26)
2570 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
2571 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
2572 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
2573 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2574 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2575 #define EDP_PSR_STATUS_COUNT_SHIFT 16
2576 #define EDP_PSR_STATUS_COUNT_MASK 0xf
2577 #define EDP_PSR_STATUS_AUX_ERROR (1<<15)
2578 #define EDP_PSR_STATUS_AUX_SENDING (1<<12)
2579 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
2580 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
2581 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
2582 #define EDP_PSR_STATUS_IDLE_MASK 0xf
2584 #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
2585 #define EDP_PSR_PERF_CNT_MASK 0xffffff
2587 #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
2588 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
2589 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
2590 #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
2592 /* VGA port control */
2593 #define ADPA 0x61100
2594 #define PCH_ADPA 0xe1100
2595 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
2597 #define ADPA_DAC_ENABLE (1<<31)
2598 #define ADPA_DAC_DISABLE 0
2599 #define ADPA_PIPE_SELECT_MASK (1<<30)
2600 #define ADPA_PIPE_A_SELECT 0
2601 #define ADPA_PIPE_B_SELECT (1<<30)
2602 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
2603 /* CPT uses bits 29:30 for pch transcoder select */
2604 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2605 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2606 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2607 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2608 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2609 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2610 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2611 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2612 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2613 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2614 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2615 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2616 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2617 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2618 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2619 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2620 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2621 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2622 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2623 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
2624 #define ADPA_SETS_HVPOLARITY 0
2625 #define ADPA_VSYNC_CNTL_DISABLE (1<<10)
2626 #define ADPA_VSYNC_CNTL_ENABLE 0
2627 #define ADPA_HSYNC_CNTL_DISABLE (1<<11)
2628 #define ADPA_HSYNC_CNTL_ENABLE 0
2629 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
2630 #define ADPA_VSYNC_ACTIVE_LOW 0
2631 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
2632 #define ADPA_HSYNC_ACTIVE_LOW 0
2633 #define ADPA_DPMS_MASK (~(3<<10))
2634 #define ADPA_DPMS_ON (0<<10)
2635 #define ADPA_DPMS_SUSPEND (1<<10)
2636 #define ADPA_DPMS_STANDBY (2<<10)
2637 #define ADPA_DPMS_OFF (3<<10)
2640 /* Hotplug control (945+ only) */
2641 #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
2642 #define PORTB_HOTPLUG_INT_EN (1 << 29)
2643 #define PORTC_HOTPLUG_INT_EN (1 << 28)
2644 #define PORTD_HOTPLUG_INT_EN (1 << 27)
2645 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
2646 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
2647 #define TV_HOTPLUG_INT_EN (1 << 18)
2648 #define CRT_HOTPLUG_INT_EN (1 << 9)
2649 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2650 PORTC_HOTPLUG_INT_EN | \
2651 PORTD_HOTPLUG_INT_EN | \
2652 SDVOC_HOTPLUG_INT_EN | \
2653 SDVOB_HOTPLUG_INT_EN | \
2655 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
2656 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2657 /* must use period 64 on GM45 according to docs */
2658 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2659 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2660 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2661 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2662 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2663 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2664 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2665 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2666 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2667 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2668 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2669 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
2671 #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
2673 * HDMI/DP bits are gen4+
2675 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
2676 * Please check the detailed lore in the commit message for for experimental
2679 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2680 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2681 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2682 /* VLV DP/HDMI bits again match Bspec */
2683 #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
2684 #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
2685 #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
2686 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2687 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
2688 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
2689 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2690 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
2691 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
2692 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
2693 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
2694 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
2695 /* CRT/TV common between gen3+ */
2696 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
2697 #define TV_HOTPLUG_INT_STATUS (1 << 10)
2698 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2699 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2700 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2701 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
2702 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2703 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2704 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
2705 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2707 /* SDVO is different across gen3/4 */
2708 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2709 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
2711 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2712 * since reality corrobates that they're the same as on gen3. But keep these
2713 * bits here (and the comment!) to help any other lost wanderers back onto the
2716 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2717 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2718 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2719 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
2720 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2721 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2722 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2723 PORTB_HOTPLUG_INT_STATUS | \
2724 PORTC_HOTPLUG_INT_STATUS | \
2725 PORTD_HOTPLUG_INT_STATUS)
2727 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2728 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2729 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2730 PORTB_HOTPLUG_INT_STATUS | \
2731 PORTC_HOTPLUG_INT_STATUS | \
2732 PORTD_HOTPLUG_INT_STATUS)
2734 /* SDVO and HDMI port control.
2735 * The same register may be used for SDVO or HDMI */
2736 #define GEN3_SDVOB 0x61140
2737 #define GEN3_SDVOC 0x61160
2738 #define GEN4_HDMIB GEN3_SDVOB
2739 #define GEN4_HDMIC GEN3_SDVOC
2740 #define CHV_HDMID 0x6116C
2741 #define PCH_SDVOB 0xe1140
2742 #define PCH_HDMIB PCH_SDVOB
2743 #define PCH_HDMIC 0xe1150
2744 #define PCH_HDMID 0xe1160
2746 #define PORT_DFT_I9XX 0x61150
2747 #define DC_BALANCE_RESET (1 << 25)
2748 #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
2749 #define DC_BALANCE_RESET_VLV (1 << 31)
2750 #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
2751 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
2752 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
2754 /* Gen 3 SDVO bits: */
2755 #define SDVO_ENABLE (1 << 31)
2756 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2757 #define SDVO_PIPE_SEL_MASK (1 << 30)
2758 #define SDVO_PIPE_B_SELECT (1 << 30)
2759 #define SDVO_STALL_SELECT (1 << 29)
2760 #define SDVO_INTERRUPT_ENABLE (1 << 26)
2762 * 915G/GM SDVO pixel multiplier.
2763 * Programmed value is multiplier - 1, up to 5x.
2764 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2766 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
2767 #define SDVO_PORT_MULTIPLY_SHIFT 23
2768 #define SDVO_PHASE_SELECT_MASK (15 << 19)
2769 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2770 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2771 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2772 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2773 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2774 #define SDVO_DETECTED (1 << 2)
2775 /* Bits to be preserved when writing */
2776 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2777 SDVO_INTERRUPT_ENABLE)
2778 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2780 /* Gen 4 SDVO/HDMI bits: */
2781 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
2782 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
2783 #define SDVO_ENCODING_SDVO (0 << 10)
2784 #define SDVO_ENCODING_HDMI (2 << 10)
2785 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2786 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
2787 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
2788 #define SDVO_AUDIO_ENABLE (1 << 6)
2789 /* VSYNC/HSYNC bits new with 965, default is to be set */
2790 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2791 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2793 /* Gen 5 (IBX) SDVO/HDMI bits: */
2794 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
2795 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2797 /* Gen 6 (CPT) SDVO/HDMI bits: */
2798 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2799 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
2801 /* CHV SDVO/HDMI bits: */
2802 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
2803 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
2806 /* DVO port control */
2807 #define DVOA 0x61120
2808 #define DVOB 0x61140
2809 #define DVOC 0x61160
2810 #define DVO_ENABLE (1 << 31)
2811 #define DVO_PIPE_B_SELECT (1 << 30)
2812 #define DVO_PIPE_STALL_UNUSED (0 << 28)
2813 #define DVO_PIPE_STALL (1 << 28)
2814 #define DVO_PIPE_STALL_TV (2 << 28)
2815 #define DVO_PIPE_STALL_MASK (3 << 28)
2816 #define DVO_USE_VGA_SYNC (1 << 15)
2817 #define DVO_DATA_ORDER_I740 (0 << 14)
2818 #define DVO_DATA_ORDER_FP (1 << 14)
2819 #define DVO_VSYNC_DISABLE (1 << 11)
2820 #define DVO_HSYNC_DISABLE (1 << 10)
2821 #define DVO_VSYNC_TRISTATE (1 << 9)
2822 #define DVO_HSYNC_TRISTATE (1 << 8)
2823 #define DVO_BORDER_ENABLE (1 << 7)
2824 #define DVO_DATA_ORDER_GBRG (1 << 6)
2825 #define DVO_DATA_ORDER_RGGB (0 << 6)
2826 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2827 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2828 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2829 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2830 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2831 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2832 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2833 #define DVO_PRESERVE_MASK (0x7<<24)
2834 #define DVOA_SRCDIM 0x61124
2835 #define DVOB_SRCDIM 0x61144
2836 #define DVOC_SRCDIM 0x61164
2837 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2838 #define DVO_SRCDIM_VERTICAL_SHIFT 0
2840 /* LVDS port control */
2841 #define LVDS 0x61180
2843 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2844 * the DPLL semantics change when the LVDS is assigned to that pipe.
2846 #define LVDS_PORT_EN (1 << 31)
2847 /* Selects pipe B for LVDS data. Must be set on pre-965. */
2848 #define LVDS_PIPEB_SELECT (1 << 30)
2849 #define LVDS_PIPE_MASK (1 << 30)
2850 #define LVDS_PIPE(pipe) ((pipe) << 30)
2851 /* LVDS dithering flag on 965/g4x platform */
2852 #define LVDS_ENABLE_DITHER (1 << 25)
2853 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
2854 #define LVDS_VSYNC_POLARITY (1 << 21)
2855 #define LVDS_HSYNC_POLARITY (1 << 20)
2857 /* Enable border for unscaled (or aspect-scaled) display */
2858 #define LVDS_BORDER_ENABLE (1 << 15)
2860 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2863 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2864 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2865 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2867 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2868 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2871 #define LVDS_A3_POWER_MASK (3 << 6)
2872 #define LVDS_A3_POWER_DOWN (0 << 6)
2873 #define LVDS_A3_POWER_UP (3 << 6)
2875 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2878 #define LVDS_CLKB_POWER_MASK (3 << 4)
2879 #define LVDS_CLKB_POWER_DOWN (0 << 4)
2880 #define LVDS_CLKB_POWER_UP (3 << 4)
2882 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2883 * setting for whether we are in dual-channel mode. The B3 pair will
2884 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2886 #define LVDS_B0B3_POWER_MASK (3 << 2)
2887 #define LVDS_B0B3_POWER_DOWN (0 << 2)
2888 #define LVDS_B0B3_POWER_UP (3 << 2)
2890 /* Video Data Island Packet control */
2891 #define VIDEO_DIP_DATA 0x61178
2892 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
2893 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2894 * of the infoframe structure specified by CEA-861. */
2895 #define VIDEO_DIP_DATA_SIZE 32
2896 #define VIDEO_DIP_VSC_DATA_SIZE 36
2897 #define VIDEO_DIP_CTL 0x61170
2899 #define VIDEO_DIP_ENABLE (1 << 31)
2900 #define VIDEO_DIP_PORT(port) ((port) << 29)
2901 #define VIDEO_DIP_PORT_MASK (3 << 29)
2902 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
2903 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
2904 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
2905 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
2906 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
2907 #define VIDEO_DIP_SELECT_AVI (0 << 19)
2908 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2909 #define VIDEO_DIP_SELECT_SPD (3 << 19)
2910 #define VIDEO_DIP_SELECT_MASK (3 << 19)
2911 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
2912 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2913 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
2914 #define VIDEO_DIP_FREQ_MASK (3 << 16)
2915 /* HSW and later: */
2916 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2917 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
2918 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
2919 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2920 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
2921 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
2923 /* Panel power sequencing */
2924 #define PP_STATUS 0x61200
2925 #define PP_ON (1 << 31)
2927 * Indicates that all dependencies of the panel are on:
2931 * - LVDS/DVOB/DVOC on
2933 #define PP_READY (1 << 30)
2934 #define PP_SEQUENCE_NONE (0 << 28)
2935 #define PP_SEQUENCE_POWER_UP (1 << 28)
2936 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
2937 #define PP_SEQUENCE_MASK (3 << 28)
2938 #define PP_SEQUENCE_SHIFT 28
2939 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
2940 #define PP_SEQUENCE_STATE_MASK 0x0000000f
2941 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
2942 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
2943 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
2944 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
2945 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
2946 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
2947 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
2948 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
2949 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
2950 #define PP_CONTROL 0x61204
2951 #define POWER_TARGET_ON (1 << 0)
2952 #define PP_ON_DELAYS 0x61208
2953 #define PP_OFF_DELAYS 0x6120c
2954 #define PP_DIVISOR 0x61210
2957 #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
2958 #define PFIT_ENABLE (1 << 31)
2959 #define PFIT_PIPE_MASK (3 << 29)
2960 #define PFIT_PIPE_SHIFT 29
2961 #define VERT_INTERP_DISABLE (0 << 10)
2962 #define VERT_INTERP_BILINEAR (1 << 10)
2963 #define VERT_INTERP_MASK (3 << 10)
2964 #define VERT_AUTO_SCALE (1 << 9)
2965 #define HORIZ_INTERP_DISABLE (0 << 6)
2966 #define HORIZ_INTERP_BILINEAR (1 << 6)
2967 #define HORIZ_INTERP_MASK (3 << 6)
2968 #define HORIZ_AUTO_SCALE (1 << 5)
2969 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
2970 #define PFIT_FILTER_FUZZY (0 << 24)
2971 #define PFIT_SCALING_AUTO (0 << 26)
2972 #define PFIT_SCALING_PROGRAMMED (1 << 26)
2973 #define PFIT_SCALING_PILLAR (2 << 26)
2974 #define PFIT_SCALING_LETTER (3 << 26)
2975 #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
2977 #define PFIT_VERT_SCALE_SHIFT 20
2978 #define PFIT_VERT_SCALE_MASK 0xfff00000
2979 #define PFIT_HORIZ_SCALE_SHIFT 4
2980 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2982 #define PFIT_VERT_SCALE_SHIFT_965 16
2983 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
2984 #define PFIT_HORIZ_SCALE_SHIFT_965 0
2985 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2987 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
2989 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
2990 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
2991 #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
2992 _VLV_BLC_PWM_CTL2_B)
2994 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
2995 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
2996 #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
2999 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3000 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3001 #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
3002 _VLV_BLC_HIST_CTL_B)
3004 /* Backlight control */
3005 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3006 #define BLM_PWM_ENABLE (1 << 31)
3007 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
3008 #define BLM_PIPE_SELECT (1 << 29)
3009 #define BLM_PIPE_SELECT_IVB (3 << 29)
3010 #define BLM_PIPE_A (0 << 29)
3011 #define BLM_PIPE_B (1 << 29)
3012 #define BLM_PIPE_C (2 << 29) /* ivb + */
3013 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
3014 #define BLM_TRANSCODER_B BLM_PIPE_B
3015 #define BLM_TRANSCODER_C BLM_PIPE_C
3016 #define BLM_TRANSCODER_EDP (3 << 29)
3017 #define BLM_PIPE(pipe) ((pipe) << 29)
3018 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
3019 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
3020 #define BLM_PHASE_IN_ENABLE (1 << 25)
3021 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
3022 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
3023 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
3024 #define BLM_PHASE_IN_COUNT_SHIFT (8)
3025 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
3026 #define BLM_PHASE_IN_INCR_SHIFT (0)
3027 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
3028 #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
3030 * This is the most significant 15 bits of the number of backlight cycles in a
3031 * complete cycle of the modulated backlight control.
3033 * The actual value is this field multiplied by two.
3035 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
3036 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
3037 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
3039 * This is the number of cycles out of the backlight modulation cycle for which
3040 * the backlight is on.
3042 * This field must be no greater than the number of cycles in the complete
3043 * backlight modulation cycle.
3045 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
3046 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
3047 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
3048 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
3050 #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
3052 /* New registers for PCH-split platforms. Safe where new bits show up, the
3053 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
3054 #define BLC_PWM_CPU_CTL2 0x48250
3055 #define BLC_PWM_CPU_CTL 0x48254
3057 #define HSW_BLC_PWM2_CTL 0x48350
3059 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3060 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
3061 #define BLC_PWM_PCH_CTL1 0xc8250
3062 #define BLM_PCH_PWM_ENABLE (1 << 31)
3063 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
3064 #define BLM_PCH_POLARITY (1 << 29)
3065 #define BLC_PWM_PCH_CTL2 0xc8254
3067 #define UTIL_PIN_CTL 0x48400
3068 #define UTIL_PIN_ENABLE (1 << 31)
3070 #define PCH_GTC_CTL 0xe7000
3071 #define PCH_GTC_ENABLE (1 << 31)
3073 /* TV port control */
3074 #define TV_CTL 0x68000
3075 /* Enables the TV encoder */
3076 # define TV_ENC_ENABLE (1 << 31)
3077 /* Sources the TV encoder input from pipe B instead of A. */
3078 # define TV_ENC_PIPEB_SELECT (1 << 30)
3079 /* Outputs composite video (DAC A only) */
3080 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
3081 /* Outputs SVideo video (DAC B/C) */
3082 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
3083 /* Outputs Component video (DAC A/B/C) */
3084 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
3085 /* Outputs Composite and SVideo (DAC A/B/C) */
3086 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
3087 # define TV_TRILEVEL_SYNC (1 << 21)
3088 /* Enables slow sync generation (945GM only) */
3089 # define TV_SLOW_SYNC (1 << 20)
3090 /* Selects 4x oversampling for 480i and 576p */
3091 # define TV_OVERSAMPLE_4X (0 << 18)
3092 /* Selects 2x oversampling for 720p and 1080i */
3093 # define TV_OVERSAMPLE_2X (1 << 18)
3094 /* Selects no oversampling for 1080p */
3095 # define TV_OVERSAMPLE_NONE (2 << 18)
3096 /* Selects 8x oversampling */
3097 # define TV_OVERSAMPLE_8X (3 << 18)
3098 /* Selects progressive mode rather than interlaced */
3099 # define TV_PROGRESSIVE (1 << 17)
3100 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
3101 # define TV_PAL_BURST (1 << 16)
3102 /* Field for setting delay of Y compared to C */
3103 # define TV_YC_SKEW_MASK (7 << 12)
3104 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
3105 # define TV_ENC_SDP_FIX (1 << 11)
3107 * Enables a fix for the 915GM only.
3109 * Not sure what it does.
3111 # define TV_ENC_C0_FIX (1 << 10)
3112 /* Bits that must be preserved by software */
3113 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
3114 # define TV_FUSE_STATE_MASK (3 << 4)
3115 /* Read-only state that reports all features enabled */
3116 # define TV_FUSE_STATE_ENABLED (0 << 4)
3117 /* Read-only state that reports that Macrovision is disabled in hardware*/
3118 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
3119 /* Read-only state that reports that TV-out is disabled in hardware. */
3120 # define TV_FUSE_STATE_DISABLED (2 << 4)
3121 /* Normal operation */
3122 # define TV_TEST_MODE_NORMAL (0 << 0)
3123 /* Encoder test pattern 1 - combo pattern */
3124 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
3125 /* Encoder test pattern 2 - full screen vertical 75% color bars */
3126 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
3127 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
3128 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
3129 /* Encoder test pattern 4 - random noise */
3130 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
3131 /* Encoder test pattern 5 - linear color ramps */
3132 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
3134 * This test mode forces the DACs to 50% of full output.
3136 * This is used for load detection in combination with TVDAC_SENSE_MASK
3138 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3139 # define TV_TEST_MODE_MASK (7 << 0)
3141 #define TV_DAC 0x68004
3142 # define TV_DAC_SAVE 0x00ffff00
3144 * Reports that DAC state change logic has reported change (RO).
3146 * This gets cleared when TV_DAC_STATE_EN is cleared
3148 # define TVDAC_STATE_CHG (1 << 31)
3149 # define TVDAC_SENSE_MASK (7 << 28)
3150 /* Reports that DAC A voltage is above the detect threshold */
3151 # define TVDAC_A_SENSE (1 << 30)
3152 /* Reports that DAC B voltage is above the detect threshold */
3153 # define TVDAC_B_SENSE (1 << 29)
3154 /* Reports that DAC C voltage is above the detect threshold */
3155 # define TVDAC_C_SENSE (1 << 28)
3157 * Enables DAC state detection logic, for load-based TV detection.
3159 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3160 * to off, for load detection to work.
3162 # define TVDAC_STATE_CHG_EN (1 << 27)
3163 /* Sets the DAC A sense value to high */
3164 # define TVDAC_A_SENSE_CTL (1 << 26)
3165 /* Sets the DAC B sense value to high */
3166 # define TVDAC_B_SENSE_CTL (1 << 25)
3167 /* Sets the DAC C sense value to high */
3168 # define TVDAC_C_SENSE_CTL (1 << 24)
3169 /* Overrides the ENC_ENABLE and DAC voltage levels */
3170 # define DAC_CTL_OVERRIDE (1 << 7)
3171 /* Sets the slew rate. Must be preserved in software */
3172 # define ENC_TVDAC_SLEW_FAST (1 << 6)
3173 # define DAC_A_1_3_V (0 << 4)
3174 # define DAC_A_1_1_V (1 << 4)
3175 # define DAC_A_0_7_V (2 << 4)
3176 # define DAC_A_MASK (3 << 4)
3177 # define DAC_B_1_3_V (0 << 2)
3178 # define DAC_B_1_1_V (1 << 2)
3179 # define DAC_B_0_7_V (2 << 2)
3180 # define DAC_B_MASK (3 << 2)
3181 # define DAC_C_1_3_V (0 << 0)
3182 # define DAC_C_1_1_V (1 << 0)
3183 # define DAC_C_0_7_V (2 << 0)
3184 # define DAC_C_MASK (3 << 0)
3187 * CSC coefficients are stored in a floating point format with 9 bits of
3188 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
3189 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3190 * -1 (0x3) being the only legal negative value.
3192 #define TV_CSC_Y 0x68010
3193 # define TV_RY_MASK 0x07ff0000
3194 # define TV_RY_SHIFT 16
3195 # define TV_GY_MASK 0x00000fff
3196 # define TV_GY_SHIFT 0
3198 #define TV_CSC_Y2 0x68014
3199 # define TV_BY_MASK 0x07ff0000
3200 # define TV_BY_SHIFT 16
3202 * Y attenuation for component video.
3204 * Stored in 1.9 fixed point.
3206 # define TV_AY_MASK 0x000003ff
3207 # define TV_AY_SHIFT 0
3209 #define TV_CSC_U 0x68018
3210 # define TV_RU_MASK 0x07ff0000
3211 # define TV_RU_SHIFT 16
3212 # define TV_GU_MASK 0x000007ff
3213 # define TV_GU_SHIFT 0
3215 #define TV_CSC_U2 0x6801c
3216 # define TV_BU_MASK 0x07ff0000
3217 # define TV_BU_SHIFT 16
3219 * U attenuation for component video.
3221 * Stored in 1.9 fixed point.
3223 # define TV_AU_MASK 0x000003ff
3224 # define TV_AU_SHIFT 0
3226 #define TV_CSC_V 0x68020
3227 # define TV_RV_MASK 0x0fff0000
3228 # define TV_RV_SHIFT 16
3229 # define TV_GV_MASK 0x000007ff
3230 # define TV_GV_SHIFT 0
3232 #define TV_CSC_V2 0x68024
3233 # define TV_BV_MASK 0x07ff0000
3234 # define TV_BV_SHIFT 16
3236 * V attenuation for component video.
3238 * Stored in 1.9 fixed point.
3240 # define TV_AV_MASK 0x000007ff
3241 # define TV_AV_SHIFT 0
3243 #define TV_CLR_KNOBS 0x68028
3244 /* 2s-complement brightness adjustment */
3245 # define TV_BRIGHTNESS_MASK 0xff000000
3246 # define TV_BRIGHTNESS_SHIFT 24
3247 /* Contrast adjustment, as a 2.6 unsigned floating point number */
3248 # define TV_CONTRAST_MASK 0x00ff0000
3249 # define TV_CONTRAST_SHIFT 16
3250 /* Saturation adjustment, as a 2.6 unsigned floating point number */
3251 # define TV_SATURATION_MASK 0x0000ff00
3252 # define TV_SATURATION_SHIFT 8
3253 /* Hue adjustment, as an integer phase angle in degrees */
3254 # define TV_HUE_MASK 0x000000ff
3255 # define TV_HUE_SHIFT 0
3257 #define TV_CLR_LEVEL 0x6802c
3258 /* Controls the DAC level for black */
3259 # define TV_BLACK_LEVEL_MASK 0x01ff0000
3260 # define TV_BLACK_LEVEL_SHIFT 16
3261 /* Controls the DAC level for blanking */
3262 # define TV_BLANK_LEVEL_MASK 0x000001ff
3263 # define TV_BLANK_LEVEL_SHIFT 0
3265 #define TV_H_CTL_1 0x68030
3266 /* Number of pixels in the hsync. */
3267 # define TV_HSYNC_END_MASK 0x1fff0000
3268 # define TV_HSYNC_END_SHIFT 16
3269 /* Total number of pixels minus one in the line (display and blanking). */
3270 # define TV_HTOTAL_MASK 0x00001fff
3271 # define TV_HTOTAL_SHIFT 0
3273 #define TV_H_CTL_2 0x68034
3274 /* Enables the colorburst (needed for non-component color) */
3275 # define TV_BURST_ENA (1 << 31)
3276 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
3277 # define TV_HBURST_START_SHIFT 16
3278 # define TV_HBURST_START_MASK 0x1fff0000
3279 /* Length of the colorburst */
3280 # define TV_HBURST_LEN_SHIFT 0
3281 # define TV_HBURST_LEN_MASK 0x0001fff
3283 #define TV_H_CTL_3 0x68038
3284 /* End of hblank, measured in pixels minus one from start of hsync */
3285 # define TV_HBLANK_END_SHIFT 16
3286 # define TV_HBLANK_END_MASK 0x1fff0000
3287 /* Start of hblank, measured in pixels minus one from start of hsync */
3288 # define TV_HBLANK_START_SHIFT 0
3289 # define TV_HBLANK_START_MASK 0x0001fff
3291 #define TV_V_CTL_1 0x6803c
3293 # define TV_NBR_END_SHIFT 16
3294 # define TV_NBR_END_MASK 0x07ff0000
3296 # define TV_VI_END_F1_SHIFT 8
3297 # define TV_VI_END_F1_MASK 0x00003f00
3299 # define TV_VI_END_F2_SHIFT 0
3300 # define TV_VI_END_F2_MASK 0x0000003f
3302 #define TV_V_CTL_2 0x68040
3303 /* Length of vsync, in half lines */
3304 # define TV_VSYNC_LEN_MASK 0x07ff0000
3305 # define TV_VSYNC_LEN_SHIFT 16
3306 /* Offset of the start of vsync in field 1, measured in one less than the
3307 * number of half lines.
3309 # define TV_VSYNC_START_F1_MASK 0x00007f00
3310 # define TV_VSYNC_START_F1_SHIFT 8
3312 * Offset of the start of vsync in field 2, measured in one less than the
3313 * number of half lines.
3315 # define TV_VSYNC_START_F2_MASK 0x0000007f
3316 # define TV_VSYNC_START_F2_SHIFT 0
3318 #define TV_V_CTL_3 0x68044
3319 /* Enables generation of the equalization signal */
3320 # define TV_EQUAL_ENA (1 << 31)
3321 /* Length of vsync, in half lines */
3322 # define TV_VEQ_LEN_MASK 0x007f0000
3323 # define TV_VEQ_LEN_SHIFT 16
3324 /* Offset of the start of equalization in field 1, measured in one less than
3325 * the number of half lines.
3327 # define TV_VEQ_START_F1_MASK 0x0007f00
3328 # define TV_VEQ_START_F1_SHIFT 8
3330 * Offset of the start of equalization in field 2, measured in one less than
3331 * the number of half lines.
3333 # define TV_VEQ_START_F2_MASK 0x000007f
3334 # define TV_VEQ_START_F2_SHIFT 0
3336 #define TV_V_CTL_4 0x68048
3338 * Offset to start of vertical colorburst, measured in one less than the
3339 * number of lines from vertical start.
3341 # define TV_VBURST_START_F1_MASK 0x003f0000
3342 # define TV_VBURST_START_F1_SHIFT 16
3344 * Offset to the end of vertical colorburst, measured in one less than the
3345 * number of lines from the start of NBR.
3347 # define TV_VBURST_END_F1_MASK 0x000000ff
3348 # define TV_VBURST_END_F1_SHIFT 0
3350 #define TV_V_CTL_5 0x6804c
3352 * Offset to start of vertical colorburst, measured in one less than the
3353 * number of lines from vertical start.
3355 # define TV_VBURST_START_F2_MASK 0x003f0000
3356 # define TV_VBURST_START_F2_SHIFT 16
3358 * Offset to the end of vertical colorburst, measured in one less than the
3359 * number of lines from the start of NBR.
3361 # define TV_VBURST_END_F2_MASK 0x000000ff
3362 # define TV_VBURST_END_F2_SHIFT 0
3364 #define TV_V_CTL_6 0x68050
3366 * Offset to start of vertical colorburst, measured in one less than the
3367 * number of lines from vertical start.
3369 # define TV_VBURST_START_F3_MASK 0x003f0000
3370 # define TV_VBURST_START_F3_SHIFT 16
3372 * Offset to the end of vertical colorburst, measured in one less than the
3373 * number of lines from the start of NBR.
3375 # define TV_VBURST_END_F3_MASK 0x000000ff
3376 # define TV_VBURST_END_F3_SHIFT 0
3378 #define TV_V_CTL_7 0x68054
3380 * Offset to start of vertical colorburst, measured in one less than the
3381 * number of lines from vertical start.
3383 # define TV_VBURST_START_F4_MASK 0x003f0000
3384 # define TV_VBURST_START_F4_SHIFT 16
3386 * Offset to the end of vertical colorburst, measured in one less than the
3387 * number of lines from the start of NBR.
3389 # define TV_VBURST_END_F4_MASK 0x000000ff
3390 # define TV_VBURST_END_F4_SHIFT 0
3392 #define TV_SC_CTL_1 0x68060
3393 /* Turns on the first subcarrier phase generation DDA */
3394 # define TV_SC_DDA1_EN (1 << 31)
3395 /* Turns on the first subcarrier phase generation DDA */
3396 # define TV_SC_DDA2_EN (1 << 30)
3397 /* Turns on the first subcarrier phase generation DDA */
3398 # define TV_SC_DDA3_EN (1 << 29)
3399 /* Sets the subcarrier DDA to reset frequency every other field */
3400 # define TV_SC_RESET_EVERY_2 (0 << 24)
3401 /* Sets the subcarrier DDA to reset frequency every fourth field */
3402 # define TV_SC_RESET_EVERY_4 (1 << 24)
3403 /* Sets the subcarrier DDA to reset frequency every eighth field */
3404 # define TV_SC_RESET_EVERY_8 (2 << 24)
3405 /* Sets the subcarrier DDA to never reset the frequency */
3406 # define TV_SC_RESET_NEVER (3 << 24)
3407 /* Sets the peak amplitude of the colorburst.*/
3408 # define TV_BURST_LEVEL_MASK 0x00ff0000
3409 # define TV_BURST_LEVEL_SHIFT 16
3410 /* Sets the increment of the first subcarrier phase generation DDA */
3411 # define TV_SCDDA1_INC_MASK 0x00000fff
3412 # define TV_SCDDA1_INC_SHIFT 0
3414 #define TV_SC_CTL_2 0x68064
3415 /* Sets the rollover for the second subcarrier phase generation DDA */
3416 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
3417 # define TV_SCDDA2_SIZE_SHIFT 16
3418 /* Sets the increent of the second subcarrier phase generation DDA */
3419 # define TV_SCDDA2_INC_MASK 0x00007fff
3420 # define TV_SCDDA2_INC_SHIFT 0
3422 #define TV_SC_CTL_3 0x68068
3423 /* Sets the rollover for the third subcarrier phase generation DDA */
3424 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
3425 # define TV_SCDDA3_SIZE_SHIFT 16
3426 /* Sets the increent of the third subcarrier phase generation DDA */
3427 # define TV_SCDDA3_INC_MASK 0x00007fff
3428 # define TV_SCDDA3_INC_SHIFT 0
3430 #define TV_WIN_POS 0x68070
3431 /* X coordinate of the display from the start of horizontal active */
3432 # define TV_XPOS_MASK 0x1fff0000
3433 # define TV_XPOS_SHIFT 16
3434 /* Y coordinate of the display from the start of vertical active (NBR) */
3435 # define TV_YPOS_MASK 0x00000fff
3436 # define TV_YPOS_SHIFT 0
3438 #define TV_WIN_SIZE 0x68074
3439 /* Horizontal size of the display window, measured in pixels*/
3440 # define TV_XSIZE_MASK 0x1fff0000
3441 # define TV_XSIZE_SHIFT 16
3443 * Vertical size of the display window, measured in pixels.
3445 * Must be even for interlaced modes.
3447 # define TV_YSIZE_MASK 0x00000fff
3448 # define TV_YSIZE_SHIFT 0
3450 #define TV_FILTER_CTL_1 0x68080
3452 * Enables automatic scaling calculation.
3454 * If set, the rest of the registers are ignored, and the calculated values can
3455 * be read back from the register.
3457 # define TV_AUTO_SCALE (1 << 31)
3459 * Disables the vertical filter.
3461 * This is required on modes more than 1024 pixels wide */
3462 # define TV_V_FILTER_BYPASS (1 << 29)
3463 /* Enables adaptive vertical filtering */
3464 # define TV_VADAPT (1 << 28)
3465 # define TV_VADAPT_MODE_MASK (3 << 26)
3466 /* Selects the least adaptive vertical filtering mode */
3467 # define TV_VADAPT_MODE_LEAST (0 << 26)
3468 /* Selects the moderately adaptive vertical filtering mode */
3469 # define TV_VADAPT_MODE_MODERATE (1 << 26)
3470 /* Selects the most adaptive vertical filtering mode */
3471 # define TV_VADAPT_MODE_MOST (3 << 26)
3473 * Sets the horizontal scaling factor.
3475 * This should be the fractional part of the horizontal scaling factor divided
3476 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
3478 * (src width - 1) / ((oversample * dest width) - 1)
3480 # define TV_HSCALE_FRAC_MASK 0x00003fff
3481 # define TV_HSCALE_FRAC_SHIFT 0
3483 #define TV_FILTER_CTL_2 0x68084
3485 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3487 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
3489 # define TV_VSCALE_INT_MASK 0x00038000
3490 # define TV_VSCALE_INT_SHIFT 15
3492 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3494 * \sa TV_VSCALE_INT_MASK
3496 # define TV_VSCALE_FRAC_MASK 0x00007fff
3497 # define TV_VSCALE_FRAC_SHIFT 0
3499 #define TV_FILTER_CTL_3 0x68088
3501 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3503 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
3505 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3507 # define TV_VSCALE_IP_INT_MASK 0x00038000
3508 # define TV_VSCALE_IP_INT_SHIFT 15
3510 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3512 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3514 * \sa TV_VSCALE_IP_INT_MASK
3516 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
3517 # define TV_VSCALE_IP_FRAC_SHIFT 0
3519 #define TV_CC_CONTROL 0x68090
3520 # define TV_CC_ENABLE (1 << 31)
3522 * Specifies which field to send the CC data in.
3524 * CC data is usually sent in field 0.
3526 # define TV_CC_FID_MASK (1 << 27)
3527 # define TV_CC_FID_SHIFT 27
3528 /* Sets the horizontal position of the CC data. Usually 135. */
3529 # define TV_CC_HOFF_MASK 0x03ff0000
3530 # define TV_CC_HOFF_SHIFT 16
3531 /* Sets the vertical position of the CC data. Usually 21 */
3532 # define TV_CC_LINE_MASK 0x0000003f
3533 # define TV_CC_LINE_SHIFT 0
3535 #define TV_CC_DATA 0x68094
3536 # define TV_CC_RDY (1 << 31)
3537 /* Second word of CC data to be transmitted. */
3538 # define TV_CC_DATA_2_MASK 0x007f0000
3539 # define TV_CC_DATA_2_SHIFT 16
3540 /* First word of CC data to be transmitted. */
3541 # define TV_CC_DATA_1_MASK 0x0000007f
3542 # define TV_CC_DATA_1_SHIFT 0
3544 #define TV_H_LUMA_0 0x68100
3545 #define TV_H_LUMA_59 0x681ec
3546 #define TV_H_CHROMA_0 0x68200
3547 #define TV_H_CHROMA_59 0x682ec
3548 #define TV_V_LUMA_0 0x68300
3549 #define TV_V_LUMA_42 0x683a8
3550 #define TV_V_CHROMA_0 0x68400
3551 #define TV_V_CHROMA_42 0x684a8
3554 #define DP_A 0x64000 /* eDP */
3555 #define DP_B 0x64100
3556 #define DP_C 0x64200
3557 #define DP_D 0x64300
3559 #define DP_PORT_EN (1 << 31)
3560 #define DP_PIPEB_SELECT (1 << 30)
3561 #define DP_PIPE_MASK (1 << 30)
3562 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
3563 #define DP_PIPE_MASK_CHV (3 << 16)
3565 /* Link training mode - select a suitable mode for each stage */
3566 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
3567 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
3568 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
3569 #define DP_LINK_TRAIN_OFF (3 << 28)
3570 #define DP_LINK_TRAIN_MASK (3 << 28)
3571 #define DP_LINK_TRAIN_SHIFT 28
3572 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
3573 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
3575 /* CPT Link training mode */
3576 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
3577 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
3578 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
3579 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
3580 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
3581 #define DP_LINK_TRAIN_SHIFT_CPT 8
3583 /* Signal voltages. These are mostly controlled by the other end */
3584 #define DP_VOLTAGE_0_4 (0 << 25)
3585 #define DP_VOLTAGE_0_6 (1 << 25)
3586 #define DP_VOLTAGE_0_8 (2 << 25)
3587 #define DP_VOLTAGE_1_2 (3 << 25)
3588 #define DP_VOLTAGE_MASK (7 << 25)
3589 #define DP_VOLTAGE_SHIFT 25
3591 /* Signal pre-emphasis levels, like voltages, the other end tells us what
3594 #define DP_PRE_EMPHASIS_0 (0 << 22)
3595 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
3596 #define DP_PRE_EMPHASIS_6 (2 << 22)
3597 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
3598 #define DP_PRE_EMPHASIS_MASK (7 << 22)
3599 #define DP_PRE_EMPHASIS_SHIFT 22
3601 /* How many wires to use. I guess 3 was too hard */
3602 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
3603 #define DP_PORT_WIDTH_MASK (7 << 19)
3605 /* Mystic DPCD version 1.1 special mode */
3606 #define DP_ENHANCED_FRAMING (1 << 18)
3609 #define DP_PLL_FREQ_270MHZ (0 << 16)
3610 #define DP_PLL_FREQ_160MHZ (1 << 16)
3611 #define DP_PLL_FREQ_MASK (3 << 16)
3613 /* locked once port is enabled */
3614 #define DP_PORT_REVERSAL (1 << 15)
3617 #define DP_PLL_ENABLE (1 << 14)
3619 /* sends the clock on lane 15 of the PEG for debug */
3620 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3622 #define DP_SCRAMBLING_DISABLE (1 << 12)
3623 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
3625 /* limit RGB values to avoid confusing TVs */
3626 #define DP_COLOR_RANGE_16_235 (1 << 8)
3628 /* Turn on the audio link */
3629 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3631 /* vs and hs sync polarity */
3632 #define DP_SYNC_VS_HIGH (1 << 4)
3633 #define DP_SYNC_HS_HIGH (1 << 3)
3636 #define DP_DETECTED (1 << 2)
3638 /* The aux channel provides a way to talk to the
3639 * signal sink for DDC etc. Max packet size supported
3640 * is 20 bytes in each direction, hence the 5 fixed
3643 #define DPA_AUX_CH_CTL 0x64010
3644 #define DPA_AUX_CH_DATA1 0x64014
3645 #define DPA_AUX_CH_DATA2 0x64018
3646 #define DPA_AUX_CH_DATA3 0x6401c
3647 #define DPA_AUX_CH_DATA4 0x64020
3648 #define DPA_AUX_CH_DATA5 0x64024
3650 #define DPB_AUX_CH_CTL 0x64110
3651 #define DPB_AUX_CH_DATA1 0x64114
3652 #define DPB_AUX_CH_DATA2 0x64118
3653 #define DPB_AUX_CH_DATA3 0x6411c
3654 #define DPB_AUX_CH_DATA4 0x64120
3655 #define DPB_AUX_CH_DATA5 0x64124
3657 #define DPC_AUX_CH_CTL 0x64210
3658 #define DPC_AUX_CH_DATA1 0x64214
3659 #define DPC_AUX_CH_DATA2 0x64218
3660 #define DPC_AUX_CH_DATA3 0x6421c
3661 #define DPC_AUX_CH_DATA4 0x64220
3662 #define DPC_AUX_CH_DATA5 0x64224
3664 #define DPD_AUX_CH_CTL 0x64310
3665 #define DPD_AUX_CH_DATA1 0x64314
3666 #define DPD_AUX_CH_DATA2 0x64318
3667 #define DPD_AUX_CH_DATA3 0x6431c
3668 #define DPD_AUX_CH_DATA4 0x64320
3669 #define DPD_AUX_CH_DATA5 0x64324
3671 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3672 #define DP_AUX_CH_CTL_DONE (1 << 30)
3673 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3674 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3675 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3676 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3677 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3678 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
3679 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3680 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3681 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3682 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3683 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3684 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3685 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3686 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3687 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3688 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3689 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3690 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3691 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3692 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
3695 * Computing GMCH M and N values for the Display Port link
3697 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
3699 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3701 * The GMCH value is used internally
3703 * bytes_per_pixel is the number of bytes coming out of the plane,
3704 * which is after the LUTs, so we want the bytes for our color format.
3705 * For our current usage, this is always 3, one byte for R, G and B.
3707 #define _PIPEA_DATA_M_G4X 0x70050
3708 #define _PIPEB_DATA_M_G4X 0x71050
3710 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
3711 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
3712 #define TU_SIZE_SHIFT 25
3713 #define TU_SIZE_MASK (0x3f << 25)
3715 #define DATA_LINK_M_N_MASK (0xffffff)
3716 #define DATA_LINK_N_MAX (0x800000)
3718 #define _PIPEA_DATA_N_G4X 0x70054
3719 #define _PIPEB_DATA_N_G4X 0x71054
3720 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
3723 * Computing Link M and N values for the Display Port link
3725 * Link M / N = pixel_clock / ls_clk
3727 * (the DP spec calls pixel_clock the 'strm_clk')
3729 * The Link value is transmitted in the Main Stream
3730 * Attributes and VB-ID.
3733 #define _PIPEA_LINK_M_G4X 0x70060
3734 #define _PIPEB_LINK_M_G4X 0x71060
3735 #define PIPEA_DP_LINK_M_MASK (0xffffff)
3737 #define _PIPEA_LINK_N_G4X 0x70064
3738 #define _PIPEB_LINK_N_G4X 0x71064
3739 #define PIPEA_DP_LINK_N_MASK (0xffffff)
3741 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3742 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3743 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3744 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
3746 /* Display & cursor control */
3749 #define _PIPEADSL 0x70000
3750 #define DSL_LINEMASK_GEN2 0x00000fff
3751 #define DSL_LINEMASK_GEN3 0x00001fff
3752 #define _PIPEACONF 0x70008
3753 #define PIPECONF_ENABLE (1<<31)
3754 #define PIPECONF_DISABLE 0
3755 #define PIPECONF_DOUBLE_WIDE (1<<30)
3756 #define I965_PIPECONF_ACTIVE (1<<30)
3757 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
3758 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
3759 #define PIPECONF_SINGLE_WIDE 0
3760 #define PIPECONF_PIPE_UNLOCKED 0
3761 #define PIPECONF_PIPE_LOCKED (1<<25)
3762 #define PIPECONF_PALETTE 0
3763 #define PIPECONF_GAMMA (1<<24)
3764 #define PIPECONF_FORCE_BORDER (1<<25)
3765 #define PIPECONF_INTERLACE_MASK (7 << 21)
3766 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
3767 /* Note that pre-gen3 does not support interlaced display directly. Panel
3768 * fitting must be disabled on pre-ilk for interlaced. */
3769 #define PIPECONF_PROGRESSIVE (0 << 21)
3770 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
3771 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
3772 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
3773 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
3774 /* Ironlake and later have a complete new set of values for interlaced. PFIT
3775 * means panel fitter required, PF means progressive fetch, DBL means power
3776 * saving pixel doubling. */
3777 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
3778 #define PIPECONF_INTERLACED_ILK (3 << 21)
3779 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
3780 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
3781 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
3782 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
3783 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
3784 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
3785 #define PIPECONF_BPC_MASK (0x7 << 5)
3786 #define PIPECONF_8BPC (0<<5)
3787 #define PIPECONF_10BPC (1<<5)
3788 #define PIPECONF_6BPC (2<<5)
3789 #define PIPECONF_12BPC (3<<5)
3790 #define PIPECONF_DITHER_EN (1<<4)
3791 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3792 #define PIPECONF_DITHER_TYPE_SP (0<<2)
3793 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3794 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3795 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
3796 #define _PIPEASTAT 0x70024
3797 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
3798 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
3799 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
3800 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
3801 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
3802 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
3803 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
3804 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
3805 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
3806 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
3807 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
3808 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
3809 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3810 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3811 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
3812 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
3813 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
3814 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
3815 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
3816 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
3817 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
3818 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
3819 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
3820 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
3821 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
3822 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
3823 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
3824 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
3825 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
3826 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
3827 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
3828 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3829 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3830 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
3831 #define PIPE_A_PSR_STATUS_VLV (1UL<<6)
3832 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
3833 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
3834 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
3835 #define PIPE_B_PSR_STATUS_VLV (1UL<<3)
3836 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
3837 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
3838 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
3839 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
3840 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
3841 #define PIPE_HBLANK_INT_STATUS (1UL<<0)
3842 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3844 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
3845 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
3847 #define PIPE_A_OFFSET 0x70000
3848 #define PIPE_B_OFFSET 0x71000
3849 #define PIPE_C_OFFSET 0x72000
3850 #define CHV_PIPE_C_OFFSET 0x74000
3852 * There's actually no pipe EDP. Some pipe registers have
3853 * simply shifted from the pipe to the transcoder, while
3854 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
3855 * to access such registers in transcoder EDP.
3857 #define PIPE_EDP_OFFSET 0x7f000
3859 #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
3860 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
3861 dev_priv->info.display_mmio_offset)
3863 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
3864 #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
3865 #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
3866 #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
3867 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
3869 #define _PIPE_MISC_A 0x70030
3870 #define _PIPE_MISC_B 0x71030
3871 #define PIPEMISC_DITHER_BPC_MASK (7<<5)
3872 #define PIPEMISC_DITHER_8_BPC (0<<5)
3873 #define PIPEMISC_DITHER_10_BPC (1<<5)
3874 #define PIPEMISC_DITHER_6_BPC (2<<5)
3875 #define PIPEMISC_DITHER_12_BPC (3<<5)
3876 #define PIPEMISC_DITHER_ENABLE (1<<4)
3877 #define PIPEMISC_DITHER_TYPE_MASK (3<<2)
3878 #define PIPEMISC_DITHER_TYPE_SP (0<<2)
3879 #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
3881 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
3882 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
3883 #define PIPEB_HLINE_INT_EN (1<<28)
3884 #define PIPEB_VBLANK_INT_EN (1<<27)
3885 #define SPRITED_FLIP_DONE_INT_EN (1<<26)
3886 #define SPRITEC_FLIP_DONE_INT_EN (1<<25)
3887 #define PLANEB_FLIP_DONE_INT_EN (1<<24)
3888 #define PIPE_PSR_INT_EN (1<<22)
3889 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
3890 #define PIPEA_HLINE_INT_EN (1<<20)
3891 #define PIPEA_VBLANK_INT_EN (1<<19)
3892 #define SPRITEB_FLIP_DONE_INT_EN (1<<18)
3893 #define SPRITEA_FLIP_DONE_INT_EN (1<<17)
3894 #define PLANEA_FLIPDONE_INT_EN (1<<16)
3895 #define PIPEC_LINE_COMPARE_INT_EN (1<<13)
3896 #define PIPEC_HLINE_INT_EN (1<<12)
3897 #define PIPEC_VBLANK_INT_EN (1<<11)
3898 #define SPRITEF_FLIPDONE_INT_EN (1<<10)
3899 #define SPRITEE_FLIPDONE_INT_EN (1<<9)
3900 #define PLANEC_FLIPDONE_INT_EN (1<<8)
3902 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
3903 #define SPRITEF_INVALID_GTT_INT_EN (1<<27)
3904 #define SPRITEE_INVALID_GTT_INT_EN (1<<26)
3905 #define PLANEC_INVALID_GTT_INT_EN (1<<25)
3906 #define CURSORC_INVALID_GTT_INT_EN (1<<24)
3907 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
3908 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
3909 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
3910 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
3911 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
3912 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
3913 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
3914 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
3915 #define DPINVGTT_EN_MASK 0xff0000
3916 #define DPINVGTT_EN_MASK_CHV 0xfff0000
3917 #define SPRITEF_INVALID_GTT_STATUS (1<<11)
3918 #define SPRITEE_INVALID_GTT_STATUS (1<<10)
3919 #define PLANEC_INVALID_GTT_STATUS (1<<9)
3920 #define CURSORC_INVALID_GTT_STATUS (1<<8)
3921 #define CURSORB_INVALID_GTT_STATUS (1<<7)
3922 #define CURSORA_INVALID_GTT_STATUS (1<<6)
3923 #define SPRITED_INVALID_GTT_STATUS (1<<5)
3924 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
3925 #define PLANEB_INVALID_GTT_STATUS (1<<3)
3926 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
3927 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
3928 #define PLANEA_INVALID_GTT_STATUS (1<<0)
3929 #define DPINVGTT_STATUS_MASK 0xff
3930 #define DPINVGTT_STATUS_MASK_CHV 0xfff
3932 #define DSPARB 0x70030
3933 #define DSPARB_CSTART_MASK (0x7f << 7)
3934 #define DSPARB_CSTART_SHIFT 7
3935 #define DSPARB_BSTART_MASK (0x7f)
3936 #define DSPARB_BSTART_SHIFT 0
3937 #define DSPARB_BEND_SHIFT 9 /* on 855 */
3938 #define DSPARB_AEND_SHIFT 0
3940 /* pnv/gen4/g4x/vlv/chv */
3941 #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
3942 #define DSPFW_SR_SHIFT 23
3943 #define DSPFW_SR_MASK (0x1ff<<23)
3944 #define DSPFW_CURSORB_SHIFT 16
3945 #define DSPFW_CURSORB_MASK (0x3f<<16)
3946 #define DSPFW_PLANEB_SHIFT 8
3947 #define DSPFW_PLANEB_MASK (0x7f<<8)
3948 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
3949 #define DSPFW_PLANEA_SHIFT 0
3950 #define DSPFW_PLANEA_MASK (0x7f<<0)
3951 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
3952 #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
3953 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */
3954 #define DSPFW_FBC_SR_SHIFT 28
3955 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
3956 #define DSPFW_FBC_HPLL_SR_SHIFT 24
3957 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
3958 #define DSPFW_SPRITEB_SHIFT (16)
3959 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
3960 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
3961 #define DSPFW_CURSORA_SHIFT 8
3962 #define DSPFW_CURSORA_MASK (0x3f<<8)
3963 #define DSPFW_PLANEC_SHIFT_OLD 0
3964 #define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */
3965 #define DSPFW_SPRITEA_SHIFT 0
3966 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
3967 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
3968 #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
3969 #define DSPFW_HPLL_SR_EN (1<<31)
3970 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
3971 #define DSPFW_CURSOR_SR_SHIFT 24
3972 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
3973 #define DSPFW_HPLL_CURSOR_SHIFT 16
3974 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
3975 #define DSPFW_HPLL_SR_SHIFT 0
3976 #define DSPFW_HPLL_SR_MASK (0x1ff<<0)
3979 #define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)
3980 #define DSPFW_SPRITEB_WM1_SHIFT 16
3981 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
3982 #define DSPFW_CURSORA_WM1_SHIFT 8
3983 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
3984 #define DSPFW_SPRITEA_WM1_SHIFT 0
3985 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
3986 #define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)
3987 #define DSPFW_PLANEB_WM1_SHIFT 24
3988 #define DSPFW_PLANEB_WM1_MASK (0xff<<24)
3989 #define DSPFW_PLANEA_WM1_SHIFT 16
3990 #define DSPFW_PLANEA_WM1_MASK (0xff<<16)
3991 #define DSPFW_CURSORB_WM1_SHIFT 8
3992 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
3993 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
3994 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
3995 #define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)
3996 #define DSPFW_SR_WM1_SHIFT 0
3997 #define DSPFW_SR_WM1_MASK (0x1ff<<0)
3998 #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)
3999 #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
4000 #define DSPFW_SPRITED_WM1_SHIFT 24
4001 #define DSPFW_SPRITED_WM1_MASK (0xff<<24)
4002 #define DSPFW_SPRITED_SHIFT 16
4003 #define DSPFW_SPRITED_MASK (0xff<<16)
4004 #define DSPFW_SPRITEC_WM1_SHIFT 8
4005 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
4006 #define DSPFW_SPRITEC_SHIFT 0
4007 #define DSPFW_SPRITEC_MASK (0xff<<0)
4008 #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8)
4009 #define DSPFW_SPRITEF_WM1_SHIFT 24
4010 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
4011 #define DSPFW_SPRITEF_SHIFT 16
4012 #define DSPFW_SPRITEF_MASK (0xff<<16)
4013 #define DSPFW_SPRITEE_WM1_SHIFT 8
4014 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
4015 #define DSPFW_SPRITEE_SHIFT 0
4016 #define DSPFW_SPRITEE_MASK (0xff<<0)
4017 #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
4018 #define DSPFW_PLANEC_WM1_SHIFT 24
4019 #define DSPFW_PLANEC_WM1_MASK (0xff<<24)
4020 #define DSPFW_PLANEC_SHIFT 16
4021 #define DSPFW_PLANEC_MASK (0xff<<16)
4022 #define DSPFW_CURSORC_WM1_SHIFT 8
4023 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
4024 #define DSPFW_CURSORC_SHIFT 0
4025 #define DSPFW_CURSORC_MASK (0x3f<<0)
4027 /* vlv/chv high order bits */
4028 #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064)
4029 #define DSPFW_SR_HI_SHIFT 24
4030 #define DSPFW_SR_HI_MASK (1<<24)
4031 #define DSPFW_SPRITEF_HI_SHIFT 23
4032 #define DSPFW_SPRITEF_HI_MASK (1<<23)
4033 #define DSPFW_SPRITEE_HI_SHIFT 22
4034 #define DSPFW_SPRITEE_HI_MASK (1<<22)
4035 #define DSPFW_PLANEC_HI_SHIFT 21
4036 #define DSPFW_PLANEC_HI_MASK (1<<21)
4037 #define DSPFW_SPRITED_HI_SHIFT 20
4038 #define DSPFW_SPRITED_HI_MASK (1<<20)
4039 #define DSPFW_SPRITEC_HI_SHIFT 16
4040 #define DSPFW_SPRITEC_HI_MASK (1<<16)
4041 #define DSPFW_PLANEB_HI_SHIFT 12
4042 #define DSPFW_PLANEB_HI_MASK (1<<12)
4043 #define DSPFW_SPRITEB_HI_SHIFT 8
4044 #define DSPFW_SPRITEB_HI_MASK (1<<8)
4045 #define DSPFW_SPRITEA_HI_SHIFT 4
4046 #define DSPFW_SPRITEA_HI_MASK (1<<4)
4047 #define DSPFW_PLANEA_HI_SHIFT 0
4048 #define DSPFW_PLANEA_HI_MASK (1<<0)
4049 #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068)
4050 #define DSPFW_SR_WM1_HI_SHIFT 24
4051 #define DSPFW_SR_WM1_HI_MASK (1<<24)
4052 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
4053 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
4054 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
4055 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
4056 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
4057 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
4058 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
4059 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
4060 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
4061 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
4062 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
4063 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
4064 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
4065 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
4066 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
4067 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
4068 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
4069 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
4071 /* drain latency register values*/
4072 #define DRAIN_LATENCY_PRECISION_16 16
4073 #define DRAIN_LATENCY_PRECISION_32 32
4074 #define DRAIN_LATENCY_PRECISION_64 64
4075 #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
4076 #define DDL_CURSOR_PRECISION_HIGH (1<<31)
4077 #define DDL_CURSOR_PRECISION_LOW (0<<31)
4078 #define DDL_CURSOR_SHIFT 24
4079 #define DDL_SPRITE_PRECISION_HIGH(sprite) (1<<(15+8*(sprite)))
4080 #define DDL_SPRITE_PRECISION_LOW(sprite) (0<<(15+8*(sprite)))
4081 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
4082 #define DDL_PLANE_PRECISION_HIGH (1<<7)
4083 #define DDL_PLANE_PRECISION_LOW (0<<7)
4084 #define DDL_PLANE_SHIFT 0
4085 #define DRAIN_LATENCY_MASK 0x7f
4087 /* FIFO watermark sizes etc */
4088 #define G4X_FIFO_LINE_SIZE 64
4089 #define I915_FIFO_LINE_SIZE 64
4090 #define I830_FIFO_LINE_SIZE 32
4092 #define VALLEYVIEW_FIFO_SIZE 255
4093 #define G4X_FIFO_SIZE 127
4094 #define I965_FIFO_SIZE 512
4095 #define I945_FIFO_SIZE 127
4096 #define I915_FIFO_SIZE 95
4097 #define I855GM_FIFO_SIZE 127 /* In cachelines */
4098 #define I830_FIFO_SIZE 95
4100 #define VALLEYVIEW_MAX_WM 0xff
4101 #define G4X_MAX_WM 0x3f
4102 #define I915_MAX_WM 0x3f
4104 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
4105 #define PINEVIEW_FIFO_LINE_SIZE 64
4106 #define PINEVIEW_MAX_WM 0x1ff
4107 #define PINEVIEW_DFT_WM 0x3f
4108 #define PINEVIEW_DFT_HPLLOFF_WM 0
4109 #define PINEVIEW_GUARD_WM 10
4110 #define PINEVIEW_CURSOR_FIFO 64
4111 #define PINEVIEW_CURSOR_MAX_WM 0x3f
4112 #define PINEVIEW_CURSOR_DFT_WM 0
4113 #define PINEVIEW_CURSOR_GUARD_WM 5
4115 #define VALLEYVIEW_CURSOR_MAX_WM 64
4116 #define I965_CURSOR_FIFO 64
4117 #define I965_CURSOR_MAX_WM 32
4118 #define I965_CURSOR_DFT_WM 8
4120 /* Watermark register definitions for SKL */
4121 #define CUR_WM_A_0 0x70140
4122 #define CUR_WM_B_0 0x71140
4123 #define PLANE_WM_1_A_0 0x70240
4124 #define PLANE_WM_1_B_0 0x71240
4125 #define PLANE_WM_2_A_0 0x70340
4126 #define PLANE_WM_2_B_0 0x71340
4127 #define PLANE_WM_TRANS_1_A_0 0x70268
4128 #define PLANE_WM_TRANS_1_B_0 0x71268
4129 #define PLANE_WM_TRANS_2_A_0 0x70368
4130 #define PLANE_WM_TRANS_2_B_0 0x71368
4131 #define CUR_WM_TRANS_A_0 0x70168
4132 #define CUR_WM_TRANS_B_0 0x71168
4133 #define PLANE_WM_EN (1 << 31)
4134 #define PLANE_WM_LINES_SHIFT 14
4135 #define PLANE_WM_LINES_MASK 0x1f
4136 #define PLANE_WM_BLOCKS_MASK 0x3ff
4138 #define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0)
4139 #define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level)))
4140 #define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0)
4142 #define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0)
4143 #define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0)
4144 #define _PLANE_WM_BASE(pipe, plane) \
4145 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4146 #define PLANE_WM(pipe, plane, level) \
4147 (_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4148 #define _PLANE_WM_TRANS_1(pipe) \
4149 _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)
4150 #define _PLANE_WM_TRANS_2(pipe) \
4151 _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0)
4152 #define PLANE_WM_TRANS(pipe, plane) \
4153 _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
4155 /* define the Watermark register on Ironlake */
4156 #define WM0_PIPEA_ILK 0x45100
4157 #define WM0_PIPE_PLANE_MASK (0xffff<<16)
4158 #define WM0_PIPE_PLANE_SHIFT 16
4159 #define WM0_PIPE_SPRITE_MASK (0xff<<8)
4160 #define WM0_PIPE_SPRITE_SHIFT 8
4161 #define WM0_PIPE_CURSOR_MASK (0xff)
4163 #define WM0_PIPEB_ILK 0x45104
4164 #define WM0_PIPEC_IVB 0x45200
4165 #define WM1_LP_ILK 0x45108
4166 #define WM1_LP_SR_EN (1<<31)
4167 #define WM1_LP_LATENCY_SHIFT 24
4168 #define WM1_LP_LATENCY_MASK (0x7f<<24)
4169 #define WM1_LP_FBC_MASK (0xf<<20)
4170 #define WM1_LP_FBC_SHIFT 20
4171 #define WM1_LP_FBC_SHIFT_BDW 19
4172 #define WM1_LP_SR_MASK (0x7ff<<8)
4173 #define WM1_LP_SR_SHIFT 8
4174 #define WM1_LP_CURSOR_MASK (0xff)
4175 #define WM2_LP_ILK 0x4510c
4176 #define WM2_LP_EN (1<<31)
4177 #define WM3_LP_ILK 0x45110
4178 #define WM3_LP_EN (1<<31)
4179 #define WM1S_LP_ILK 0x45120
4180 #define WM2S_LP_IVB 0x45124
4181 #define WM3S_LP_IVB 0x45128
4182 #define WM1S_LP_EN (1<<31)
4184 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
4185 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
4186 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
4188 /* Memory latency timer register */
4189 #define MLTR_ILK 0x11222
4190 #define MLTR_WM1_SHIFT 0
4191 #define MLTR_WM2_SHIFT 8
4192 /* the unit of memory self-refresh latency time is 0.5us */
4193 #define ILK_SRLT_MASK 0x3f
4196 /* the address where we get all kinds of latency value */
4197 #define SSKPD 0x5d10
4198 #define SSKPD_WM_MASK 0x3f
4199 #define SSKPD_WM0_SHIFT 0
4200 #define SSKPD_WM1_SHIFT 8
4201 #define SSKPD_WM2_SHIFT 16
4202 #define SSKPD_WM3_SHIFT 24
4205 * The two pipe frame counter registers are not synchronized, so
4206 * reading a stable value is somewhat tricky. The following code
4210 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4211 * PIPE_FRAME_HIGH_SHIFT;
4212 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4213 * PIPE_FRAME_LOW_SHIFT);
4214 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4215 * PIPE_FRAME_HIGH_SHIFT);
4216 * } while (high1 != high2);
4217 * frame = (high1 << 8) | low1;
4219 #define _PIPEAFRAMEHIGH 0x70040
4220 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
4221 #define PIPE_FRAME_HIGH_SHIFT 0
4222 #define _PIPEAFRAMEPIXEL 0x70044
4223 #define PIPE_FRAME_LOW_MASK 0xff000000
4224 #define PIPE_FRAME_LOW_SHIFT 24
4225 #define PIPE_PIXEL_MASK 0x00ffffff
4226 #define PIPE_PIXEL_SHIFT 0
4227 /* GM45+ just has to be different */
4228 #define _PIPEA_FRMCOUNT_GM45 0x70040
4229 #define _PIPEA_FLIPCOUNT_GM45 0x70044
4230 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
4231 #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
4233 /* Cursor A & B regs */
4234 #define _CURACNTR 0x70080
4235 /* Old style CUR*CNTR flags (desktop 8xx) */
4236 #define CURSOR_ENABLE 0x80000000
4237 #define CURSOR_GAMMA_ENABLE 0x40000000
4238 #define CURSOR_STRIDE_SHIFT 28
4239 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
4240 #define CURSOR_PIPE_CSC_ENABLE (1<<24)
4241 #define CURSOR_FORMAT_SHIFT 24
4242 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
4243 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
4244 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
4245 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
4246 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
4247 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
4248 /* New style CUR*CNTR flags */
4249 #define CURSOR_MODE 0x27
4250 #define CURSOR_MODE_DISABLE 0x00
4251 #define CURSOR_MODE_128_32B_AX 0x02
4252 #define CURSOR_MODE_256_32B_AX 0x03
4253 #define CURSOR_MODE_64_32B_AX 0x07
4254 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
4255 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
4256 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
4257 #define MCURSOR_PIPE_SELECT (1 << 28)
4258 #define MCURSOR_PIPE_A 0x00
4259 #define MCURSOR_PIPE_B (1 << 28)
4260 #define MCURSOR_GAMMA_ENABLE (1 << 26)
4261 #define CURSOR_ROTATE_180 (1<<15)
4262 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
4263 #define _CURABASE 0x70084
4264 #define _CURAPOS 0x70088
4265 #define CURSOR_POS_MASK 0x007FF
4266 #define CURSOR_POS_SIGN 0x8000
4267 #define CURSOR_X_SHIFT 0
4268 #define CURSOR_Y_SHIFT 16
4269 #define CURSIZE 0x700a0
4270 #define _CURBCNTR 0x700c0
4271 #define _CURBBASE 0x700c4
4272 #define _CURBPOS 0x700c8
4274 #define _CURBCNTR_IVB 0x71080
4275 #define _CURBBASE_IVB 0x71084
4276 #define _CURBPOS_IVB 0x71088
4278 #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4279 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4280 dev_priv->info.display_mmio_offset)
4282 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4283 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4284 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4286 #define CURSOR_A_OFFSET 0x70080
4287 #define CURSOR_B_OFFSET 0x700c0
4288 #define CHV_CURSOR_C_OFFSET 0x700e0
4289 #define IVB_CURSOR_B_OFFSET 0x71080
4290 #define IVB_CURSOR_C_OFFSET 0x72080
4292 /* Display A control */
4293 #define _DSPACNTR 0x70180
4294 #define DISPLAY_PLANE_ENABLE (1<<31)
4295 #define DISPLAY_PLANE_DISABLE 0
4296 #define DISPPLANE_GAMMA_ENABLE (1<<30)
4297 #define DISPPLANE_GAMMA_DISABLE 0
4298 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
4299 #define DISPPLANE_YUV422 (0x0<<26)
4300 #define DISPPLANE_8BPP (0x2<<26)
4301 #define DISPPLANE_BGRA555 (0x3<<26)
4302 #define DISPPLANE_BGRX555 (0x4<<26)
4303 #define DISPPLANE_BGRX565 (0x5<<26)
4304 #define DISPPLANE_BGRX888 (0x6<<26)
4305 #define DISPPLANE_BGRA888 (0x7<<26)
4306 #define DISPPLANE_RGBX101010 (0x8<<26)
4307 #define DISPPLANE_RGBA101010 (0x9<<26)
4308 #define DISPPLANE_BGRX101010 (0xa<<26)
4309 #define DISPPLANE_RGBX161616 (0xc<<26)
4310 #define DISPPLANE_RGBX888 (0xe<<26)
4311 #define DISPPLANE_RGBA888 (0xf<<26)
4312 #define DISPPLANE_STEREO_ENABLE (1<<25)
4313 #define DISPPLANE_STEREO_DISABLE 0
4314 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
4315 #define DISPPLANE_SEL_PIPE_SHIFT 24
4316 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
4317 #define DISPPLANE_SEL_PIPE_A 0
4318 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
4319 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
4320 #define DISPPLANE_SRC_KEY_DISABLE 0
4321 #define DISPPLANE_LINE_DOUBLE (1<<20)
4322 #define DISPPLANE_NO_LINE_DOUBLE 0
4323 #define DISPPLANE_STEREO_POLARITY_FIRST 0
4324 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
4325 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
4326 #define DISPPLANE_ROTATE_180 (1<<15)
4327 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
4328 #define DISPPLANE_TILED (1<<10)
4329 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
4330 #define _DSPAADDR 0x70184
4331 #define _DSPASTRIDE 0x70188
4332 #define _DSPAPOS 0x7018C /* reserved */
4333 #define _DSPASIZE 0x70190
4334 #define _DSPASURF 0x7019C /* 965+ only */
4335 #define _DSPATILEOFF 0x701A4 /* 965+ only */
4336 #define _DSPAOFFSET 0x701A4 /* HSW */
4337 #define _DSPASURFLIVE 0x701AC
4339 #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
4340 #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
4341 #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
4342 #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
4343 #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
4344 #define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
4345 #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
4346 #define DSPLINOFF(plane) DSPADDR(plane)
4347 #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
4348 #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
4350 /* CHV pipe B blender and primary plane */
4351 #define _CHV_BLEND_A 0x60a00
4352 #define CHV_BLEND_LEGACY (0<<30)
4353 #define CHV_BLEND_ANDROID (1<<30)
4354 #define CHV_BLEND_MPO (2<<30)
4355 #define CHV_BLEND_MASK (3<<30)
4356 #define _CHV_CANVAS_A 0x60a04
4357 #define _PRIMPOS_A 0x60a08
4358 #define _PRIMSIZE_A 0x60a0c
4359 #define _PRIMCNSTALPHA_A 0x60a10
4360 #define PRIM_CONST_ALPHA_ENABLE (1<<31)
4362 #define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
4363 #define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
4364 #define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
4365 #define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
4366 #define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
4368 /* Display/Sprite base address macros */
4369 #define DISP_BASEADDR_MASK (0xfffff000)
4370 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
4371 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
4374 #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
4375 #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
4376 #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
4377 #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
4378 #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
4379 #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
4380 #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
4381 #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
4382 #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
4383 #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
4384 #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
4385 #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
4386 #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
4389 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
4390 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
4391 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
4392 #define _PIPEBFRAMEHIGH 0x71040
4393 #define _PIPEBFRAMEPIXEL 0x71044
4394 #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
4395 #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
4398 /* Display B control */
4399 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
4400 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
4401 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
4402 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
4403 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
4404 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
4405 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
4406 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
4407 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
4408 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
4409 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
4410 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
4411 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
4413 /* Sprite A control */
4414 #define _DVSACNTR 0x72180
4415 #define DVS_ENABLE (1<<31)
4416 #define DVS_GAMMA_ENABLE (1<<30)
4417 #define DVS_PIXFORMAT_MASK (3<<25)
4418 #define DVS_FORMAT_YUV422 (0<<25)
4419 #define DVS_FORMAT_RGBX101010 (1<<25)
4420 #define DVS_FORMAT_RGBX888 (2<<25)
4421 #define DVS_FORMAT_RGBX161616 (3<<25)
4422 #define DVS_PIPE_CSC_ENABLE (1<<24)
4423 #define DVS_SOURCE_KEY (1<<22)
4424 #define DVS_RGB_ORDER_XBGR (1<<20)
4425 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
4426 #define DVS_YUV_ORDER_YUYV (0<<16)
4427 #define DVS_YUV_ORDER_UYVY (1<<16)
4428 #define DVS_YUV_ORDER_YVYU (2<<16)
4429 #define DVS_YUV_ORDER_VYUY (3<<16)
4430 #define DVS_ROTATE_180 (1<<15)
4431 #define DVS_DEST_KEY (1<<2)
4432 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
4433 #define DVS_TILED (1<<10)
4434 #define _DVSALINOFF 0x72184
4435 #define _DVSASTRIDE 0x72188
4436 #define _DVSAPOS 0x7218c
4437 #define _DVSASIZE 0x72190
4438 #define _DVSAKEYVAL 0x72194
4439 #define _DVSAKEYMSK 0x72198
4440 #define _DVSASURF 0x7219c
4441 #define _DVSAKEYMAXVAL 0x721a0
4442 #define _DVSATILEOFF 0x721a4
4443 #define _DVSASURFLIVE 0x721ac
4444 #define _DVSASCALE 0x72204
4445 #define DVS_SCALE_ENABLE (1<<31)
4446 #define DVS_FILTER_MASK (3<<29)
4447 #define DVS_FILTER_MEDIUM (0<<29)
4448 #define DVS_FILTER_ENHANCING (1<<29)
4449 #define DVS_FILTER_SOFTENING (2<<29)
4450 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4451 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
4452 #define _DVSAGAMC 0x72300
4454 #define _DVSBCNTR 0x73180
4455 #define _DVSBLINOFF 0x73184
4456 #define _DVSBSTRIDE 0x73188
4457 #define _DVSBPOS 0x7318c
4458 #define _DVSBSIZE 0x73190
4459 #define _DVSBKEYVAL 0x73194
4460 #define _DVSBKEYMSK 0x73198
4461 #define _DVSBSURF 0x7319c
4462 #define _DVSBKEYMAXVAL 0x731a0
4463 #define _DVSBTILEOFF 0x731a4
4464 #define _DVSBSURFLIVE 0x731ac
4465 #define _DVSBSCALE 0x73204
4466 #define _DVSBGAMC 0x73300
4468 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
4469 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
4470 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
4471 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
4472 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
4473 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
4474 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
4475 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
4476 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
4477 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
4478 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
4479 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
4481 #define _SPRA_CTL 0x70280
4482 #define SPRITE_ENABLE (1<<31)
4483 #define SPRITE_GAMMA_ENABLE (1<<30)
4484 #define SPRITE_PIXFORMAT_MASK (7<<25)
4485 #define SPRITE_FORMAT_YUV422 (0<<25)
4486 #define SPRITE_FORMAT_RGBX101010 (1<<25)
4487 #define SPRITE_FORMAT_RGBX888 (2<<25)
4488 #define SPRITE_FORMAT_RGBX161616 (3<<25)
4489 #define SPRITE_FORMAT_YUV444 (4<<25)
4490 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
4491 #define SPRITE_PIPE_CSC_ENABLE (1<<24)
4492 #define SPRITE_SOURCE_KEY (1<<22)
4493 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
4494 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
4495 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
4496 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
4497 #define SPRITE_YUV_ORDER_YUYV (0<<16)
4498 #define SPRITE_YUV_ORDER_UYVY (1<<16)
4499 #define SPRITE_YUV_ORDER_YVYU (2<<16)
4500 #define SPRITE_YUV_ORDER_VYUY (3<<16)
4501 #define SPRITE_ROTATE_180 (1<<15)
4502 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
4503 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
4504 #define SPRITE_TILED (1<<10)
4505 #define SPRITE_DEST_KEY (1<<2)
4506 #define _SPRA_LINOFF 0x70284
4507 #define _SPRA_STRIDE 0x70288
4508 #define _SPRA_POS 0x7028c
4509 #define _SPRA_SIZE 0x70290
4510 #define _SPRA_KEYVAL 0x70294
4511 #define _SPRA_KEYMSK 0x70298
4512 #define _SPRA_SURF 0x7029c
4513 #define _SPRA_KEYMAX 0x702a0
4514 #define _SPRA_TILEOFF 0x702a4
4515 #define _SPRA_OFFSET 0x702a4
4516 #define _SPRA_SURFLIVE 0x702ac
4517 #define _SPRA_SCALE 0x70304
4518 #define SPRITE_SCALE_ENABLE (1<<31)
4519 #define SPRITE_FILTER_MASK (3<<29)
4520 #define SPRITE_FILTER_MEDIUM (0<<29)
4521 #define SPRITE_FILTER_ENHANCING (1<<29)
4522 #define SPRITE_FILTER_SOFTENING (2<<29)
4523 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4524 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
4525 #define _SPRA_GAMC 0x70400
4527 #define _SPRB_CTL 0x71280
4528 #define _SPRB_LINOFF 0x71284
4529 #define _SPRB_STRIDE 0x71288
4530 #define _SPRB_POS 0x7128c
4531 #define _SPRB_SIZE 0x71290
4532 #define _SPRB_KEYVAL 0x71294
4533 #define _SPRB_KEYMSK 0x71298
4534 #define _SPRB_SURF 0x7129c
4535 #define _SPRB_KEYMAX 0x712a0
4536 #define _SPRB_TILEOFF 0x712a4
4537 #define _SPRB_OFFSET 0x712a4
4538 #define _SPRB_SURFLIVE 0x712ac
4539 #define _SPRB_SCALE 0x71304
4540 #define _SPRB_GAMC 0x71400
4542 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
4543 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
4544 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
4545 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
4546 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
4547 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
4548 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
4549 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
4550 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
4551 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
4552 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
4553 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
4554 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
4555 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
4557 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
4558 #define SP_ENABLE (1<<31)
4559 #define SP_GAMMA_ENABLE (1<<30)
4560 #define SP_PIXFORMAT_MASK (0xf<<26)
4561 #define SP_FORMAT_YUV422 (0<<26)
4562 #define SP_FORMAT_BGR565 (5<<26)
4563 #define SP_FORMAT_BGRX8888 (6<<26)
4564 #define SP_FORMAT_BGRA8888 (7<<26)
4565 #define SP_FORMAT_RGBX1010102 (8<<26)
4566 #define SP_FORMAT_RGBA1010102 (9<<26)
4567 #define SP_FORMAT_RGBX8888 (0xe<<26)
4568 #define SP_FORMAT_RGBA8888 (0xf<<26)
4569 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
4570 #define SP_SOURCE_KEY (1<<22)
4571 #define SP_YUV_BYTE_ORDER_MASK (3<<16)
4572 #define SP_YUV_ORDER_YUYV (0<<16)
4573 #define SP_YUV_ORDER_UYVY (1<<16)
4574 #define SP_YUV_ORDER_YVYU (2<<16)
4575 #define SP_YUV_ORDER_VYUY (3<<16)
4576 #define SP_ROTATE_180 (1<<15)
4577 #define SP_TILED (1<<10)
4578 #define SP_MIRROR (1<<8) /* CHV pipe B */
4579 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
4580 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
4581 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
4582 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
4583 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
4584 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
4585 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
4586 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
4587 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
4588 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
4589 #define SP_CONST_ALPHA_ENABLE (1<<31)
4590 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
4592 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
4593 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
4594 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
4595 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
4596 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
4597 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
4598 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
4599 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
4600 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
4601 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
4602 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
4603 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
4605 #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
4606 #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
4607 #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
4608 #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
4609 #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
4610 #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
4611 #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
4612 #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
4613 #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
4614 #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
4615 #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
4616 #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
4619 * CHV pipe B sprite CSC
4621 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
4622 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
4623 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
4625 #define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
4626 #define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
4627 #define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
4628 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
4629 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
4631 #define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
4632 #define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
4633 #define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
4634 #define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
4635 #define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
4636 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
4637 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
4639 #define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
4640 #define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
4641 #define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
4642 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
4643 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
4645 #define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
4646 #define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
4647 #define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
4648 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */
4649 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */
4651 /* Skylake plane registers */
4653 #define _PLANE_CTL_1_A 0x70180
4654 #define _PLANE_CTL_2_A 0x70280
4655 #define _PLANE_CTL_3_A 0x70380
4656 #define PLANE_CTL_ENABLE (1 << 31)
4657 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
4658 #define PLANE_CTL_FORMAT_MASK (0xf << 24)
4659 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
4660 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
4661 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
4662 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
4663 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
4664 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
4665 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
4666 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
4667 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
4668 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
4669 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
4670 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
4671 #define PLANE_CTL_ORDER_BGRX (0 << 20)
4672 #define PLANE_CTL_ORDER_RGBX (1 << 20)
4673 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
4674 #define PLANE_CTL_YUV422_YUYV ( 0 << 16)
4675 #define PLANE_CTL_YUV422_UYVY ( 1 << 16)
4676 #define PLANE_CTL_YUV422_YVYU ( 2 << 16)
4677 #define PLANE_CTL_YUV422_VYUY ( 3 << 16)
4678 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
4679 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
4680 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
4681 #define PLANE_CTL_TILED_MASK (0x7 << 10)
4682 #define PLANE_CTL_TILED_LINEAR ( 0 << 10)
4683 #define PLANE_CTL_TILED_X ( 1 << 10)
4684 #define PLANE_CTL_TILED_Y ( 4 << 10)
4685 #define PLANE_CTL_TILED_YF ( 5 << 10)
4686 #define PLANE_CTL_ALPHA_MASK (0x3 << 4)
4687 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
4688 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
4689 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
4690 #define PLANE_CTL_ROTATE_MASK 0x3
4691 #define PLANE_CTL_ROTATE_0 0x0
4692 #define PLANE_CTL_ROTATE_180 0x2
4693 #define _PLANE_STRIDE_1_A 0x70188
4694 #define _PLANE_STRIDE_2_A 0x70288
4695 #define _PLANE_STRIDE_3_A 0x70388
4696 #define _PLANE_POS_1_A 0x7018c
4697 #define _PLANE_POS_2_A 0x7028c
4698 #define _PLANE_POS_3_A 0x7038c
4699 #define _PLANE_SIZE_1_A 0x70190
4700 #define _PLANE_SIZE_2_A 0x70290
4701 #define _PLANE_SIZE_3_A 0x70390
4702 #define _PLANE_SURF_1_A 0x7019c
4703 #define _PLANE_SURF_2_A 0x7029c
4704 #define _PLANE_SURF_3_A 0x7039c
4705 #define _PLANE_OFFSET_1_A 0x701a4
4706 #define _PLANE_OFFSET_2_A 0x702a4
4707 #define _PLANE_OFFSET_3_A 0x703a4
4708 #define _PLANE_KEYVAL_1_A 0x70194
4709 #define _PLANE_KEYVAL_2_A 0x70294
4710 #define _PLANE_KEYMSK_1_A 0x70198
4711 #define _PLANE_KEYMSK_2_A 0x70298
4712 #define _PLANE_KEYMAX_1_A 0x701a0
4713 #define _PLANE_KEYMAX_2_A 0x702a0
4714 #define _PLANE_BUF_CFG_1_A 0x7027c
4715 #define _PLANE_BUF_CFG_2_A 0x7037c
4717 #define _PLANE_CTL_1_B 0x71180
4718 #define _PLANE_CTL_2_B 0x71280
4719 #define _PLANE_CTL_3_B 0x71380
4720 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
4721 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
4722 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
4723 #define PLANE_CTL(pipe, plane) \
4724 _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
4726 #define _PLANE_STRIDE_1_B 0x71188
4727 #define _PLANE_STRIDE_2_B 0x71288
4728 #define _PLANE_STRIDE_3_B 0x71388
4729 #define _PLANE_STRIDE_1(pipe) \
4730 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
4731 #define _PLANE_STRIDE_2(pipe) \
4732 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
4733 #define _PLANE_STRIDE_3(pipe) \
4734 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
4735 #define PLANE_STRIDE(pipe, plane) \
4736 _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
4738 #define _PLANE_POS_1_B 0x7118c
4739 #define _PLANE_POS_2_B 0x7128c
4740 #define _PLANE_POS_3_B 0x7138c
4741 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
4742 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
4743 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
4744 #define PLANE_POS(pipe, plane) \
4745 _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
4747 #define _PLANE_SIZE_1_B 0x71190
4748 #define _PLANE_SIZE_2_B 0x71290
4749 #define _PLANE_SIZE_3_B 0x71390
4750 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
4751 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
4752 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
4753 #define PLANE_SIZE(pipe, plane) \
4754 _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
4756 #define _PLANE_SURF_1_B 0x7119c
4757 #define _PLANE_SURF_2_B 0x7129c
4758 #define _PLANE_SURF_3_B 0x7139c
4759 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
4760 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
4761 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
4762 #define PLANE_SURF(pipe, plane) \
4763 _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
4765 #define _PLANE_OFFSET_1_B 0x711a4
4766 #define _PLANE_OFFSET_2_B 0x712a4
4767 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
4768 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
4769 #define PLANE_OFFSET(pipe, plane) \
4770 _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
4772 #define _PLANE_KEYVAL_1_B 0x71194
4773 #define _PLANE_KEYVAL_2_B 0x71294
4774 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
4775 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
4776 #define PLANE_KEYVAL(pipe, plane) \
4777 _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
4779 #define _PLANE_KEYMSK_1_B 0x71198
4780 #define _PLANE_KEYMSK_2_B 0x71298
4781 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
4782 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
4783 #define PLANE_KEYMSK(pipe, plane) \
4784 _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
4786 #define _PLANE_KEYMAX_1_B 0x711a0
4787 #define _PLANE_KEYMAX_2_B 0x712a0
4788 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
4789 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
4790 #define PLANE_KEYMAX(pipe, plane) \
4791 _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
4793 #define _PLANE_BUF_CFG_1_B 0x7127c
4794 #define _PLANE_BUF_CFG_2_B 0x7137c
4795 #define _PLANE_BUF_CFG_1(pipe) \
4796 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
4797 #define _PLANE_BUF_CFG_2(pipe) \
4798 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
4799 #define PLANE_BUF_CFG(pipe, plane) \
4800 _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
4802 /* SKL new cursor registers */
4803 #define _CUR_BUF_CFG_A 0x7017c
4804 #define _CUR_BUF_CFG_B 0x7117c
4805 #define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
4808 #define VGACNTRL 0x71400
4809 # define VGA_DISP_DISABLE (1 << 31)
4810 # define VGA_2X_MODE (1 << 30)
4811 # define VGA_PIPE_B_SELECT (1 << 29)
4813 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
4817 #define CPU_VGACNTRL 0x41000
4819 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
4820 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
4821 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
4822 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
4823 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
4824 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
4825 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
4826 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
4827 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
4829 /* refresh rate hardware control */
4830 #define RR_HW_CTL 0x45300
4831 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
4832 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
4834 #define FDI_PLL_BIOS_0 0x46000
4835 #define FDI_PLL_FB_CLOCK_MASK 0xff
4836 #define FDI_PLL_BIOS_1 0x46004
4837 #define FDI_PLL_BIOS_2 0x46008
4838 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
4839 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
4840 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
4842 #define PCH_3DCGDIS0 0x46020
4843 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
4844 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
4846 #define PCH_3DCGDIS1 0x46024
4847 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
4849 #define FDI_PLL_FREQ_CTL 0x46030
4850 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
4851 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
4852 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
4855 #define _PIPEA_DATA_M1 0x60030
4856 #define PIPE_DATA_M1_OFFSET 0
4857 #define _PIPEA_DATA_N1 0x60034
4858 #define PIPE_DATA_N1_OFFSET 0
4860 #define _PIPEA_DATA_M2 0x60038
4861 #define PIPE_DATA_M2_OFFSET 0
4862 #define _PIPEA_DATA_N2 0x6003c
4863 #define PIPE_DATA_N2_OFFSET 0
4865 #define _PIPEA_LINK_M1 0x60040
4866 #define PIPE_LINK_M1_OFFSET 0
4867 #define _PIPEA_LINK_N1 0x60044
4868 #define PIPE_LINK_N1_OFFSET 0
4870 #define _PIPEA_LINK_M2 0x60048
4871 #define PIPE_LINK_M2_OFFSET 0
4872 #define _PIPEA_LINK_N2 0x6004c
4873 #define PIPE_LINK_N2_OFFSET 0
4875 /* PIPEB timing regs are same start from 0x61000 */
4877 #define _PIPEB_DATA_M1 0x61030
4878 #define _PIPEB_DATA_N1 0x61034
4879 #define _PIPEB_DATA_M2 0x61038
4880 #define _PIPEB_DATA_N2 0x6103c
4881 #define _PIPEB_LINK_M1 0x61040
4882 #define _PIPEB_LINK_N1 0x61044
4883 #define _PIPEB_LINK_M2 0x61048
4884 #define _PIPEB_LINK_N2 0x6104c
4886 #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
4887 #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
4888 #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
4889 #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
4890 #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
4891 #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
4892 #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
4893 #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
4895 /* CPU panel fitter */
4896 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
4897 #define _PFA_CTL_1 0x68080
4898 #define _PFB_CTL_1 0x68880
4899 #define PF_ENABLE (1<<31)
4900 #define PF_PIPE_SEL_MASK_IVB (3<<29)
4901 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
4902 #define PF_FILTER_MASK (3<<23)
4903 #define PF_FILTER_PROGRAMMED (0<<23)
4904 #define PF_FILTER_MED_3x3 (1<<23)
4905 #define PF_FILTER_EDGE_ENHANCE (2<<23)
4906 #define PF_FILTER_EDGE_SOFTEN (3<<23)
4907 #define _PFA_WIN_SZ 0x68074
4908 #define _PFB_WIN_SZ 0x68874
4909 #define _PFA_WIN_POS 0x68070
4910 #define _PFB_WIN_POS 0x68870
4911 #define _PFA_VSCALE 0x68084
4912 #define _PFB_VSCALE 0x68884
4913 #define _PFA_HSCALE 0x68090
4914 #define _PFB_HSCALE 0x68890
4916 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
4917 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
4918 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
4919 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
4920 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
4922 #define _PSA_CTL 0x68180
4923 #define _PSB_CTL 0x68980
4924 #define PS_ENABLE (1<<31)
4925 #define _PSA_WIN_SZ 0x68174
4926 #define _PSB_WIN_SZ 0x68974
4927 #define _PSA_WIN_POS 0x68170
4928 #define _PSB_WIN_POS 0x68970
4930 #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL)
4931 #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
4932 #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
4934 /* legacy palette */
4935 #define _LGC_PALETTE_A 0x4a000
4936 #define _LGC_PALETTE_B 0x4a800
4937 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
4939 #define _GAMMA_MODE_A 0x4a480
4940 #define _GAMMA_MODE_B 0x4ac80
4941 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
4942 #define GAMMA_MODE_MODE_MASK (3 << 0)
4943 #define GAMMA_MODE_MODE_8BIT (0 << 0)
4944 #define GAMMA_MODE_MODE_10BIT (1 << 0)
4945 #define GAMMA_MODE_MODE_12BIT (2 << 0)
4946 #define GAMMA_MODE_MODE_SPLIT (3 << 0)
4949 #define DE_MASTER_IRQ_CONTROL (1 << 31)
4950 #define DE_SPRITEB_FLIP_DONE (1 << 29)
4951 #define DE_SPRITEA_FLIP_DONE (1 << 28)
4952 #define DE_PLANEB_FLIP_DONE (1 << 27)
4953 #define DE_PLANEA_FLIP_DONE (1 << 26)
4954 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
4955 #define DE_PCU_EVENT (1 << 25)
4956 #define DE_GTT_FAULT (1 << 24)
4957 #define DE_POISON (1 << 23)
4958 #define DE_PERFORM_COUNTER (1 << 22)
4959 #define DE_PCH_EVENT (1 << 21)
4960 #define DE_AUX_CHANNEL_A (1 << 20)
4961 #define DE_DP_A_HOTPLUG (1 << 19)
4962 #define DE_GSE (1 << 18)
4963 #define DE_PIPEB_VBLANK (1 << 15)
4964 #define DE_PIPEB_EVEN_FIELD (1 << 14)
4965 #define DE_PIPEB_ODD_FIELD (1 << 13)
4966 #define DE_PIPEB_LINE_COMPARE (1 << 12)
4967 #define DE_PIPEB_VSYNC (1 << 11)
4968 #define DE_PIPEB_CRC_DONE (1 << 10)
4969 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
4970 #define DE_PIPEA_VBLANK (1 << 7)
4971 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
4972 #define DE_PIPEA_EVEN_FIELD (1 << 6)
4973 #define DE_PIPEA_ODD_FIELD (1 << 5)
4974 #define DE_PIPEA_LINE_COMPARE (1 << 4)
4975 #define DE_PIPEA_VSYNC (1 << 3)
4976 #define DE_PIPEA_CRC_DONE (1 << 2)
4977 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
4978 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
4979 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
4981 /* More Ivybridge lolz */
4982 #define DE_ERR_INT_IVB (1<<30)
4983 #define DE_GSE_IVB (1<<29)
4984 #define DE_PCH_EVENT_IVB (1<<28)
4985 #define DE_DP_A_HOTPLUG_IVB (1<<27)
4986 #define DE_AUX_CHANNEL_A_IVB (1<<26)
4987 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
4988 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
4989 #define DE_PIPEC_VBLANK_IVB (1<<10)
4990 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
4991 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
4992 #define DE_PIPEB_VBLANK_IVB (1<<5)
4993 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
4994 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
4995 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
4996 #define DE_PIPEA_VBLANK_IVB (1<<0)
4997 #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
4999 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */
5000 #define MASTER_INTERRUPT_ENABLE (1<<31)
5002 #define DEISR 0x44000
5003 #define DEIMR 0x44004
5004 #define DEIIR 0x44008
5005 #define DEIER 0x4400c
5007 #define GTISR 0x44010
5008 #define GTIMR 0x44014
5009 #define GTIIR 0x44018
5010 #define GTIER 0x4401c
5012 #define GEN8_MASTER_IRQ 0x44200
5013 #define GEN8_MASTER_IRQ_CONTROL (1<<31)
5014 #define GEN8_PCU_IRQ (1<<30)
5015 #define GEN8_DE_PCH_IRQ (1<<23)
5016 #define GEN8_DE_MISC_IRQ (1<<22)
5017 #define GEN8_DE_PORT_IRQ (1<<20)
5018 #define GEN8_DE_PIPE_C_IRQ (1<<18)
5019 #define GEN8_DE_PIPE_B_IRQ (1<<17)
5020 #define GEN8_DE_PIPE_A_IRQ (1<<16)
5021 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
5022 #define GEN8_GT_VECS_IRQ (1<<6)
5023 #define GEN8_GT_PM_IRQ (1<<4)
5024 #define GEN8_GT_VCS2_IRQ (1<<3)
5025 #define GEN8_GT_VCS1_IRQ (1<<2)
5026 #define GEN8_GT_BCS_IRQ (1<<1)
5027 #define GEN8_GT_RCS_IRQ (1<<0)
5029 #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
5030 #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
5031 #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
5032 #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
5034 #define GEN8_BCS_IRQ_SHIFT 16
5035 #define GEN8_RCS_IRQ_SHIFT 0
5036 #define GEN8_VCS2_IRQ_SHIFT 16
5037 #define GEN8_VCS1_IRQ_SHIFT 0
5038 #define GEN8_VECS_IRQ_SHIFT 0
5040 #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
5041 #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
5042 #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
5043 #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
5044 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
5045 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
5046 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
5047 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
5048 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
5049 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
5050 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
5051 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
5052 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
5053 #define GEN8_PIPE_VSYNC (1 << 1)
5054 #define GEN8_PIPE_VBLANK (1 << 0)
5055 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
5056 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
5057 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
5058 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
5059 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
5060 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
5061 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
5062 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p))
5063 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5064 (GEN8_PIPE_CURSOR_FAULT | \
5065 GEN8_PIPE_SPRITE_FAULT | \
5066 GEN8_PIPE_PRIMARY_FAULT)
5067 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5068 (GEN9_PIPE_CURSOR_FAULT | \
5069 GEN9_PIPE_PLANE3_FAULT | \
5070 GEN9_PIPE_PLANE2_FAULT | \
5071 GEN9_PIPE_PLANE1_FAULT)
5073 #define GEN8_DE_PORT_ISR 0x44440
5074 #define GEN8_DE_PORT_IMR 0x44444
5075 #define GEN8_DE_PORT_IIR 0x44448
5076 #define GEN8_DE_PORT_IER 0x4444c
5077 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
5078 #define GEN9_AUX_CHANNEL_D (1 << 27)
5079 #define GEN9_AUX_CHANNEL_C (1 << 26)
5080 #define GEN9_AUX_CHANNEL_B (1 << 25)
5081 #define GEN8_AUX_CHANNEL_A (1 << 0)
5083 #define GEN8_DE_MISC_ISR 0x44460
5084 #define GEN8_DE_MISC_IMR 0x44464
5085 #define GEN8_DE_MISC_IIR 0x44468
5086 #define GEN8_DE_MISC_IER 0x4446c
5087 #define GEN8_DE_MISC_GSE (1 << 27)
5089 #define GEN8_PCU_ISR 0x444e0
5090 #define GEN8_PCU_IMR 0x444e4
5091 #define GEN8_PCU_IIR 0x444e8
5092 #define GEN8_PCU_IER 0x444ec
5094 #define ILK_DISPLAY_CHICKEN2 0x42004
5095 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
5096 #define ILK_ELPIN_409_SELECT (1 << 25)
5097 #define ILK_DPARB_GATE (1<<22)
5098 #define ILK_VSDPFD_FULL (1<<21)
5099 #define FUSE_STRAP 0x42014
5100 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
5101 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
5102 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
5103 #define ILK_HDCP_DISABLE (1 << 25)
5104 #define ILK_eDP_A_DISABLE (1 << 24)
5105 #define HSW_CDCLK_LIMIT (1 << 24)
5106 #define ILK_DESKTOP (1 << 23)
5108 #define ILK_DSPCLK_GATE_D 0x42020
5109 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
5110 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
5111 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
5112 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
5113 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
5115 #define IVB_CHICKEN3 0x4200c
5116 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
5117 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
5119 #define CHICKEN_PAR1_1 0x42080
5120 #define DPA_MASK_VBLANK_SRD (1 << 15)
5121 #define FORCE_ARB_IDLE_PLANES (1 << 14)
5123 #define _CHICKEN_PIPESL_1_A 0x420b0
5124 #define _CHICKEN_PIPESL_1_B 0x420b4
5125 #define HSW_FBCQ_DIS (1 << 22)
5126 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
5127 #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
5129 #define DISP_ARB_CTL 0x45000
5130 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
5131 #define DISP_FBC_WM_DIS (1<<15)
5132 #define DISP_ARB_CTL2 0x45004
5133 #define DISP_DATA_PARTITION_5_6 (1<<6)
5134 #define GEN7_MSG_CTL 0x45010
5135 #define WAIT_FOR_PCH_RESET_ACK (1<<1)
5136 #define WAIT_FOR_PCH_FLR_ACK (1<<0)
5137 #define HSW_NDE_RSTWRN_OPT 0x46408
5138 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
5141 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
5142 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
5143 #define COMMON_SLICE_CHICKEN2 0x7014
5144 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
5146 #define GEN7_L3SQCREG1 0xB010
5147 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
5149 #define GEN7_L3CNTLREG1 0xB01C
5150 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
5151 #define GEN7_L3AGDIS (1<<19)
5152 #define GEN7_L3CNTLREG2 0xB020
5153 #define GEN7_L3CNTLREG3 0xB024
5155 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
5156 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
5158 #define GEN7_L3SQCREG4 0xb034
5159 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
5162 #define HDC_CHICKEN0 0x7300
5163 #define HDC_FORCE_NON_COHERENT (1<<4)
5164 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
5165 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
5167 /* WaCatErrorRejectionIssue */
5168 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
5169 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
5171 #define HSW_SCRATCH1 0xb038
5172 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
5176 /* south display engine interrupt: IBX */
5177 #define SDE_AUDIO_POWER_D (1 << 27)
5178 #define SDE_AUDIO_POWER_C (1 << 26)
5179 #define SDE_AUDIO_POWER_B (1 << 25)
5180 #define SDE_AUDIO_POWER_SHIFT (25)
5181 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
5182 #define SDE_GMBUS (1 << 24)
5183 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
5184 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
5185 #define SDE_AUDIO_HDCP_MASK (3 << 22)
5186 #define SDE_AUDIO_TRANSB (1 << 21)
5187 #define SDE_AUDIO_TRANSA (1 << 20)
5188 #define SDE_AUDIO_TRANS_MASK (3 << 20)
5189 #define SDE_POISON (1 << 19)
5191 #define SDE_FDI_RXB (1 << 17)
5192 #define SDE_FDI_RXA (1 << 16)
5193 #define SDE_FDI_MASK (3 << 16)
5194 #define SDE_AUXD (1 << 15)
5195 #define SDE_AUXC (1 << 14)
5196 #define SDE_AUXB (1 << 13)
5197 #define SDE_AUX_MASK (7 << 13)
5199 #define SDE_CRT_HOTPLUG (1 << 11)
5200 #define SDE_PORTD_HOTPLUG (1 << 10)
5201 #define SDE_PORTC_HOTPLUG (1 << 9)
5202 #define SDE_PORTB_HOTPLUG (1 << 8)
5203 #define SDE_SDVOB_HOTPLUG (1 << 6)
5204 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
5205 SDE_SDVOB_HOTPLUG | \
5206 SDE_PORTB_HOTPLUG | \
5207 SDE_PORTC_HOTPLUG | \
5209 #define SDE_TRANSB_CRC_DONE (1 << 5)
5210 #define SDE_TRANSB_CRC_ERR (1 << 4)
5211 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
5212 #define SDE_TRANSA_CRC_DONE (1 << 2)
5213 #define SDE_TRANSA_CRC_ERR (1 << 1)
5214 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
5215 #define SDE_TRANS_MASK (0x3f)
5217 /* south display engine interrupt: CPT/PPT */
5218 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
5219 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
5220 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
5221 #define SDE_AUDIO_POWER_SHIFT_CPT 29
5222 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
5223 #define SDE_AUXD_CPT (1 << 27)
5224 #define SDE_AUXC_CPT (1 << 26)
5225 #define SDE_AUXB_CPT (1 << 25)
5226 #define SDE_AUX_MASK_CPT (7 << 25)
5227 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
5228 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
5229 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
5230 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
5231 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
5232 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
5233 SDE_SDVOB_HOTPLUG_CPT | \
5234 SDE_PORTD_HOTPLUG_CPT | \
5235 SDE_PORTC_HOTPLUG_CPT | \
5236 SDE_PORTB_HOTPLUG_CPT)
5237 #define SDE_GMBUS_CPT (1 << 17)
5238 #define SDE_ERROR_CPT (1 << 16)
5239 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
5240 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
5241 #define SDE_FDI_RXC_CPT (1 << 8)
5242 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
5243 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
5244 #define SDE_FDI_RXB_CPT (1 << 4)
5245 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
5246 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
5247 #define SDE_FDI_RXA_CPT (1 << 0)
5248 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
5249 SDE_AUDIO_CP_REQ_B_CPT | \
5250 SDE_AUDIO_CP_REQ_A_CPT)
5251 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
5252 SDE_AUDIO_CP_CHG_B_CPT | \
5253 SDE_AUDIO_CP_CHG_A_CPT)
5254 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
5258 #define SDEISR 0xc4000
5259 #define SDEIMR 0xc4004
5260 #define SDEIIR 0xc4008
5261 #define SDEIER 0xc400c
5263 #define SERR_INT 0xc4040
5264 #define SERR_INT_POISON (1<<31)
5265 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
5266 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
5267 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
5268 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
5270 /* digital port hotplug */
5271 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
5272 #define PORTD_HOTPLUG_ENABLE (1 << 20)
5273 #define PORTD_PULSE_DURATION_2ms (0)
5274 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
5275 #define PORTD_PULSE_DURATION_6ms (2 << 18)
5276 #define PORTD_PULSE_DURATION_100ms (3 << 18)
5277 #define PORTD_PULSE_DURATION_MASK (3 << 18)
5278 #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
5279 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
5280 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
5281 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
5282 #define PORTC_HOTPLUG_ENABLE (1 << 12)
5283 #define PORTC_PULSE_DURATION_2ms (0)
5284 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
5285 #define PORTC_PULSE_DURATION_6ms (2 << 10)
5286 #define PORTC_PULSE_DURATION_100ms (3 << 10)
5287 #define PORTC_PULSE_DURATION_MASK (3 << 10)
5288 #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
5289 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
5290 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
5291 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
5292 #define PORTB_HOTPLUG_ENABLE (1 << 4)
5293 #define PORTB_PULSE_DURATION_2ms (0)
5294 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
5295 #define PORTB_PULSE_DURATION_6ms (2 << 2)
5296 #define PORTB_PULSE_DURATION_100ms (3 << 2)
5297 #define PORTB_PULSE_DURATION_MASK (3 << 2)
5298 #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
5299 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
5300 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
5301 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
5303 #define PCH_GPIOA 0xc5010
5304 #define PCH_GPIOB 0xc5014
5305 #define PCH_GPIOC 0xc5018
5306 #define PCH_GPIOD 0xc501c
5307 #define PCH_GPIOE 0xc5020
5308 #define PCH_GPIOF 0xc5024
5310 #define PCH_GMBUS0 0xc5100
5311 #define PCH_GMBUS1 0xc5104
5312 #define PCH_GMBUS2 0xc5108
5313 #define PCH_GMBUS3 0xc510c
5314 #define PCH_GMBUS4 0xc5110
5315 #define PCH_GMBUS5 0xc5120
5317 #define _PCH_DPLL_A 0xc6014
5318 #define _PCH_DPLL_B 0xc6018
5319 #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
5321 #define _PCH_FPA0 0xc6040
5322 #define FP_CB_TUNE (0x3<<22)
5323 #define _PCH_FPA1 0xc6044
5324 #define _PCH_FPB0 0xc6048
5325 #define _PCH_FPB1 0xc604c
5326 #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
5327 #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
5329 #define PCH_DPLL_TEST 0xc606c
5331 #define PCH_DREF_CONTROL 0xC6200
5332 #define DREF_CONTROL_MASK 0x7fc3
5333 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
5334 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
5335 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
5336 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
5337 #define DREF_SSC_SOURCE_DISABLE (0<<11)
5338 #define DREF_SSC_SOURCE_ENABLE (2<<11)
5339 #define DREF_SSC_SOURCE_MASK (3<<11)
5340 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
5341 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
5342 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
5343 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
5344 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
5345 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
5346 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
5347 #define DREF_SSC4_DOWNSPREAD (0<<6)
5348 #define DREF_SSC4_CENTERSPREAD (1<<6)
5349 #define DREF_SSC1_DISABLE (0<<1)
5350 #define DREF_SSC1_ENABLE (1<<1)
5351 #define DREF_SSC4_DISABLE (0)
5352 #define DREF_SSC4_ENABLE (1)
5354 #define PCH_RAWCLK_FREQ 0xc6204
5355 #define FDL_TP1_TIMER_SHIFT 12
5356 #define FDL_TP1_TIMER_MASK (3<<12)
5357 #define FDL_TP2_TIMER_SHIFT 10
5358 #define FDL_TP2_TIMER_MASK (3<<10)
5359 #define RAWCLK_FREQ_MASK 0x3ff
5361 #define PCH_DPLL_TMR_CFG 0xc6208
5363 #define PCH_SSC4_PARMS 0xc6210
5364 #define PCH_SSC4_AUX_PARMS 0xc6214
5366 #define PCH_DPLL_SEL 0xc7000
5367 #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
5368 #define TRANS_DPLLA_SEL(pipe) 0
5369 #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
5373 #define _PCH_TRANS_HTOTAL_A 0xe0000
5374 #define TRANS_HTOTAL_SHIFT 16
5375 #define TRANS_HACTIVE_SHIFT 0
5376 #define _PCH_TRANS_HBLANK_A 0xe0004
5377 #define TRANS_HBLANK_END_SHIFT 16
5378 #define TRANS_HBLANK_START_SHIFT 0
5379 #define _PCH_TRANS_HSYNC_A 0xe0008
5380 #define TRANS_HSYNC_END_SHIFT 16
5381 #define TRANS_HSYNC_START_SHIFT 0
5382 #define _PCH_TRANS_VTOTAL_A 0xe000c
5383 #define TRANS_VTOTAL_SHIFT 16
5384 #define TRANS_VACTIVE_SHIFT 0
5385 #define _PCH_TRANS_VBLANK_A 0xe0010
5386 #define TRANS_VBLANK_END_SHIFT 16
5387 #define TRANS_VBLANK_START_SHIFT 0
5388 #define _PCH_TRANS_VSYNC_A 0xe0014
5389 #define TRANS_VSYNC_END_SHIFT 16
5390 #define TRANS_VSYNC_START_SHIFT 0
5391 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
5393 #define _PCH_TRANSA_DATA_M1 0xe0030
5394 #define _PCH_TRANSA_DATA_N1 0xe0034
5395 #define _PCH_TRANSA_DATA_M2 0xe0038
5396 #define _PCH_TRANSA_DATA_N2 0xe003c
5397 #define _PCH_TRANSA_LINK_M1 0xe0040
5398 #define _PCH_TRANSA_LINK_N1 0xe0044
5399 #define _PCH_TRANSA_LINK_M2 0xe0048
5400 #define _PCH_TRANSA_LINK_N2 0xe004c
5402 /* Per-transcoder DIP controls (PCH) */
5403 #define _VIDEO_DIP_CTL_A 0xe0200
5404 #define _VIDEO_DIP_DATA_A 0xe0208
5405 #define _VIDEO_DIP_GCP_A 0xe0210
5407 #define _VIDEO_DIP_CTL_B 0xe1200
5408 #define _VIDEO_DIP_DATA_B 0xe1208
5409 #define _VIDEO_DIP_GCP_B 0xe1210
5411 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
5412 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
5413 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
5415 /* Per-transcoder DIP controls (VLV) */
5416 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
5417 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
5418 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
5420 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
5421 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
5422 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
5424 #define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
5425 #define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
5426 #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
5428 #define VLV_TVIDEO_DIP_CTL(pipe) \
5429 _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
5430 VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
5431 #define VLV_TVIDEO_DIP_DATA(pipe) \
5432 _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
5433 VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
5434 #define VLV_TVIDEO_DIP_GCP(pipe) \
5435 _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
5436 VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
5438 /* Haswell DIP controls */
5439 #define HSW_VIDEO_DIP_CTL_A 0x60200
5440 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
5441 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260
5442 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
5443 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
5444 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
5445 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
5446 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280
5447 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
5448 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
5449 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
5450 #define HSW_VIDEO_DIP_GCP_A 0x60210
5452 #define HSW_VIDEO_DIP_CTL_B 0x61200
5453 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
5454 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260
5455 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
5456 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
5457 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
5458 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
5459 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280
5460 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
5461 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
5462 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
5463 #define HSW_VIDEO_DIP_GCP_B 0x61210
5465 #define HSW_TVIDEO_DIP_CTL(trans) \
5466 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
5467 #define HSW_TVIDEO_DIP_AVI_DATA(trans) \
5468 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
5469 #define HSW_TVIDEO_DIP_VS_DATA(trans) \
5470 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
5471 #define HSW_TVIDEO_DIP_SPD_DATA(trans) \
5472 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
5473 #define HSW_TVIDEO_DIP_GCP(trans) \
5474 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
5475 #define HSW_TVIDEO_DIP_VSC_DATA(trans) \
5476 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
5478 #define HSW_STEREO_3D_CTL_A 0x70020
5479 #define S3D_ENABLE (1<<31)
5480 #define HSW_STEREO_3D_CTL_B 0x71020
5482 #define HSW_STEREO_3D_CTL(trans) \
5483 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
5485 #define _PCH_TRANS_HTOTAL_B 0xe1000
5486 #define _PCH_TRANS_HBLANK_B 0xe1004
5487 #define _PCH_TRANS_HSYNC_B 0xe1008
5488 #define _PCH_TRANS_VTOTAL_B 0xe100c
5489 #define _PCH_TRANS_VBLANK_B 0xe1010
5490 #define _PCH_TRANS_VSYNC_B 0xe1014
5491 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
5493 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
5494 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
5495 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
5496 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
5497 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
5498 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
5499 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
5500 _PCH_TRANS_VSYNCSHIFT_B)
5502 #define _PCH_TRANSB_DATA_M1 0xe1030
5503 #define _PCH_TRANSB_DATA_N1 0xe1034
5504 #define _PCH_TRANSB_DATA_M2 0xe1038
5505 #define _PCH_TRANSB_DATA_N2 0xe103c
5506 #define _PCH_TRANSB_LINK_M1 0xe1040
5507 #define _PCH_TRANSB_LINK_N1 0xe1044
5508 #define _PCH_TRANSB_LINK_M2 0xe1048
5509 #define _PCH_TRANSB_LINK_N2 0xe104c
5511 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
5512 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
5513 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
5514 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
5515 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
5516 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
5517 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
5518 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
5520 #define _PCH_TRANSACONF 0xf0008
5521 #define _PCH_TRANSBCONF 0xf1008
5522 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
5523 #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
5524 #define TRANS_DISABLE (0<<31)
5525 #define TRANS_ENABLE (1<<31)
5526 #define TRANS_STATE_MASK (1<<30)
5527 #define TRANS_STATE_DISABLE (0<<30)
5528 #define TRANS_STATE_ENABLE (1<<30)
5529 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
5530 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
5531 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
5532 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
5533 #define TRANS_INTERLACE_MASK (7<<21)
5534 #define TRANS_PROGRESSIVE (0<<21)
5535 #define TRANS_INTERLACED (3<<21)
5536 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
5537 #define TRANS_8BPC (0<<5)
5538 #define TRANS_10BPC (1<<5)
5539 #define TRANS_6BPC (2<<5)
5540 #define TRANS_12BPC (3<<5)
5542 #define _TRANSA_CHICKEN1 0xf0060
5543 #define _TRANSB_CHICKEN1 0xf1060
5544 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
5545 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
5546 #define _TRANSA_CHICKEN2 0xf0064
5547 #define _TRANSB_CHICKEN2 0xf1064
5548 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
5549 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
5550 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
5551 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
5552 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
5553 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
5555 #define SOUTH_CHICKEN1 0xc2000
5556 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
5557 #define FDIA_PHASE_SYNC_SHIFT_EN 18
5558 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
5559 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
5560 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
5561 #define SOUTH_CHICKEN2 0xc2004
5562 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
5563 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
5564 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
5566 #define _FDI_RXA_CHICKEN 0xc200c
5567 #define _FDI_RXB_CHICKEN 0xc2010
5568 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
5569 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
5570 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
5572 #define SOUTH_DSPCLK_GATE_D 0xc2020
5573 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
5574 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
5575 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
5576 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
5579 #define _FDI_TXA_CTL 0x60100
5580 #define _FDI_TXB_CTL 0x61100
5581 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
5582 #define FDI_TX_DISABLE (0<<31)
5583 #define FDI_TX_ENABLE (1<<31)
5584 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
5585 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
5586 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
5587 #define FDI_LINK_TRAIN_NONE (3<<28)
5588 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
5589 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
5590 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
5591 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
5592 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
5593 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
5594 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
5595 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
5596 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
5597 SNB has different settings. */
5598 /* SNB A-stepping */
5599 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
5600 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
5601 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
5602 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
5603 /* SNB B-stepping */
5604 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
5605 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
5606 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
5607 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
5608 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
5609 #define FDI_DP_PORT_WIDTH_SHIFT 19
5610 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
5611 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
5612 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
5613 /* Ironlake: hardwired to 1 */
5614 #define FDI_TX_PLL_ENABLE (1<<14)
5616 /* Ivybridge has different bits for lolz */
5617 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
5618 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
5619 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
5620 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
5622 /* both Tx and Rx */
5623 #define FDI_COMPOSITE_SYNC (1<<11)
5624 #define FDI_LINK_TRAIN_AUTO (1<<10)
5625 #define FDI_SCRAMBLING_ENABLE (0<<7)
5626 #define FDI_SCRAMBLING_DISABLE (1<<7)
5628 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
5629 #define _FDI_RXA_CTL 0xf000c
5630 #define _FDI_RXB_CTL 0xf100c
5631 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
5632 #define FDI_RX_ENABLE (1<<31)
5633 /* train, dp width same as FDI_TX */
5634 #define FDI_FS_ERRC_ENABLE (1<<27)
5635 #define FDI_FE_ERRC_ENABLE (1<<26)
5636 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
5637 #define FDI_8BPC (0<<16)
5638 #define FDI_10BPC (1<<16)
5639 #define FDI_6BPC (2<<16)
5640 #define FDI_12BPC (3<<16)
5641 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
5642 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
5643 #define FDI_RX_PLL_ENABLE (1<<13)
5644 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
5645 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
5646 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
5647 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
5648 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
5649 #define FDI_PCDCLK (1<<4)
5651 #define FDI_AUTO_TRAINING (1<<10)
5652 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
5653 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
5654 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
5655 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
5656 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
5658 #define _FDI_RXA_MISC 0xf0010
5659 #define _FDI_RXB_MISC 0xf1010
5660 #define FDI_RX_PWRDN_LANE1_MASK (3<<26)
5661 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
5662 #define FDI_RX_PWRDN_LANE0_MASK (3<<24)
5663 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
5664 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
5665 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
5666 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
5667 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
5669 #define _FDI_RXA_TUSIZE1 0xf0030
5670 #define _FDI_RXA_TUSIZE2 0xf0038
5671 #define _FDI_RXB_TUSIZE1 0xf1030
5672 #define _FDI_RXB_TUSIZE2 0xf1038
5673 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
5674 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
5676 /* FDI_RX interrupt register format */
5677 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
5678 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
5679 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
5680 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
5681 #define FDI_RX_FS_CODE_ERR (1<<6)
5682 #define FDI_RX_FE_CODE_ERR (1<<5)
5683 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
5684 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
5685 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
5686 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
5687 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
5689 #define _FDI_RXA_IIR 0xf0014
5690 #define _FDI_RXA_IMR 0xf0018
5691 #define _FDI_RXB_IIR 0xf1014
5692 #define _FDI_RXB_IMR 0xf1018
5693 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
5694 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
5696 #define FDI_PLL_CTL_1 0xfe000
5697 #define FDI_PLL_CTL_2 0xfe004
5699 #define PCH_LVDS 0xe1180
5700 #define LVDS_DETECTED (1 << 1)
5702 /* vlv has 2 sets of panel control regs. */
5703 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
5704 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
5705 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
5706 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
5707 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
5708 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
5710 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
5711 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
5712 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
5713 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
5714 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
5716 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
5717 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
5718 #define VLV_PIPE_PP_ON_DELAYS(pipe) \
5719 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
5720 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \
5721 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
5722 #define VLV_PIPE_PP_DIVISOR(pipe) \
5723 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
5725 #define PCH_PP_STATUS 0xc7200
5726 #define PCH_PP_CONTROL 0xc7204
5727 #define PANEL_UNLOCK_REGS (0xabcd << 16)
5728 #define PANEL_UNLOCK_MASK (0xffff << 16)
5729 #define EDP_FORCE_VDD (1 << 3)
5730 #define EDP_BLC_ENABLE (1 << 2)
5731 #define PANEL_POWER_RESET (1 << 1)
5732 #define PANEL_POWER_OFF (0 << 0)
5733 #define PANEL_POWER_ON (1 << 0)
5734 #define PCH_PP_ON_DELAYS 0xc7208
5735 #define PANEL_PORT_SELECT_MASK (3 << 30)
5736 #define PANEL_PORT_SELECT_LVDS (0 << 30)
5737 #define PANEL_PORT_SELECT_DPA (1 << 30)
5738 #define PANEL_PORT_SELECT_DPC (2 << 30)
5739 #define PANEL_PORT_SELECT_DPD (3 << 30)
5740 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
5741 #define PANEL_POWER_UP_DELAY_SHIFT 16
5742 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
5743 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
5745 #define PCH_PP_OFF_DELAYS 0xc720c
5746 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
5747 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
5748 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
5749 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
5751 #define PCH_PP_DIVISOR 0xc7210
5752 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
5753 #define PP_REFERENCE_DIVIDER_SHIFT 8
5754 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
5755 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
5757 #define PCH_DP_B 0xe4100
5758 #define PCH_DPB_AUX_CH_CTL 0xe4110
5759 #define PCH_DPB_AUX_CH_DATA1 0xe4114
5760 #define PCH_DPB_AUX_CH_DATA2 0xe4118
5761 #define PCH_DPB_AUX_CH_DATA3 0xe411c
5762 #define PCH_DPB_AUX_CH_DATA4 0xe4120
5763 #define PCH_DPB_AUX_CH_DATA5 0xe4124
5765 #define PCH_DP_C 0xe4200
5766 #define PCH_DPC_AUX_CH_CTL 0xe4210
5767 #define PCH_DPC_AUX_CH_DATA1 0xe4214
5768 #define PCH_DPC_AUX_CH_DATA2 0xe4218
5769 #define PCH_DPC_AUX_CH_DATA3 0xe421c
5770 #define PCH_DPC_AUX_CH_DATA4 0xe4220
5771 #define PCH_DPC_AUX_CH_DATA5 0xe4224
5773 #define PCH_DP_D 0xe4300
5774 #define PCH_DPD_AUX_CH_CTL 0xe4310
5775 #define PCH_DPD_AUX_CH_DATA1 0xe4314
5776 #define PCH_DPD_AUX_CH_DATA2 0xe4318
5777 #define PCH_DPD_AUX_CH_DATA3 0xe431c
5778 #define PCH_DPD_AUX_CH_DATA4 0xe4320
5779 #define PCH_DPD_AUX_CH_DATA5 0xe4324
5782 #define PORT_TRANS_A_SEL_CPT 0
5783 #define PORT_TRANS_B_SEL_CPT (1<<29)
5784 #define PORT_TRANS_C_SEL_CPT (2<<29)
5785 #define PORT_TRANS_SEL_MASK (3<<29)
5786 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
5787 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
5788 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
5789 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
5790 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
5792 #define TRANS_DP_CTL_A 0xe0300
5793 #define TRANS_DP_CTL_B 0xe1300
5794 #define TRANS_DP_CTL_C 0xe2300
5795 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
5796 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
5797 #define TRANS_DP_PORT_SEL_B (0<<29)
5798 #define TRANS_DP_PORT_SEL_C (1<<29)
5799 #define TRANS_DP_PORT_SEL_D (2<<29)
5800 #define TRANS_DP_PORT_SEL_NONE (3<<29)
5801 #define TRANS_DP_PORT_SEL_MASK (3<<29)
5802 #define TRANS_DP_AUDIO_ONLY (1<<26)
5803 #define TRANS_DP_ENH_FRAMING (1<<18)
5804 #define TRANS_DP_8BPC (0<<9)
5805 #define TRANS_DP_10BPC (1<<9)
5806 #define TRANS_DP_6BPC (2<<9)
5807 #define TRANS_DP_12BPC (3<<9)
5808 #define TRANS_DP_BPC_MASK (3<<9)
5809 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
5810 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
5811 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
5812 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
5813 #define TRANS_DP_SYNC_MASK (3<<3)
5815 /* SNB eDP training params */
5816 /* SNB A-stepping */
5817 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
5818 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
5819 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
5820 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
5821 /* SNB B-stepping */
5822 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
5823 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
5824 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
5825 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
5826 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
5827 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
5830 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
5831 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
5832 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
5833 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
5834 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
5835 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
5836 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
5839 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
5840 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
5841 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
5842 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
5843 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
5845 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
5847 #define VLV_PMWGICZ 0x1300a4
5849 #define FORCEWAKE 0xA18C
5850 #define FORCEWAKE_VLV 0x1300b0
5851 #define FORCEWAKE_ACK_VLV 0x1300b4
5852 #define FORCEWAKE_MEDIA_VLV 0x1300b8
5853 #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
5854 #define FORCEWAKE_ACK_HSW 0x130044
5855 #define FORCEWAKE_ACK 0x130090
5856 #define VLV_GTLC_WAKE_CTRL 0x130090
5857 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
5858 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
5859 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
5861 #define VLV_GTLC_PW_STATUS 0x130094
5862 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
5863 #define VLV_GTLC_ALLOWWAKEERR (1 << 1)
5864 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
5865 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
5866 #define FORCEWAKE_MT 0xa188 /* multi-threaded */
5867 #define FORCEWAKE_MEDIA_GEN9 0xa270
5868 #define FORCEWAKE_RENDER_GEN9 0xa278
5869 #define FORCEWAKE_BLITTER_GEN9 0xa188
5870 #define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88
5871 #define FORCEWAKE_ACK_RENDER_GEN9 0x0D84
5872 #define FORCEWAKE_ACK_BLITTER_GEN9 0x130044
5873 #define FORCEWAKE_KERNEL 0x1
5874 #define FORCEWAKE_USER 0x2
5875 #define FORCEWAKE_MT_ACK 0x130040
5876 #define ECOBUS 0xa180
5877 #define FORCEWAKE_MT_ENABLE (1<<5)
5878 #define VLV_SPAREG2H 0xA194
5880 #define GTFIFODBG 0x120000
5881 #define GT_FIFO_SBDROPERR (1<<6)
5882 #define GT_FIFO_BLOBDROPERR (1<<5)
5883 #define GT_FIFO_SB_READ_ABORTERR (1<<4)
5884 #define GT_FIFO_DROPERR (1<<3)
5885 #define GT_FIFO_OVFERR (1<<2)
5886 #define GT_FIFO_IAWRERR (1<<1)
5887 #define GT_FIFO_IARDERR (1<<0)
5889 #define GTFIFOCTL 0x120008
5890 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
5891 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
5893 #define HSW_IDICR 0x9008
5894 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
5895 #define HSW_EDRAM_PRESENT 0x120010
5897 #define GEN6_UCGCTL1 0x9400
5898 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
5899 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
5900 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
5902 #define GEN6_UCGCTL2 0x9404
5903 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
5904 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
5905 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
5906 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
5907 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
5909 #define GEN6_UCGCTL3 0x9408
5911 #define GEN7_UCGCTL4 0x940c
5912 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
5914 #define GEN6_RCGCTL1 0x9410
5915 #define GEN6_RCGCTL2 0x9414
5916 #define GEN6_RSTCTL 0x9420
5918 #define GEN8_UCGCTL6 0x9430
5919 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
5921 #define GEN6_GFXPAUSE 0xA000
5922 #define GEN6_RPNSWREQ 0xA008
5923 #define GEN6_TURBO_DISABLE (1<<31)
5924 #define GEN6_FREQUENCY(x) ((x)<<25)
5925 #define HSW_FREQUENCY(x) ((x)<<24)
5926 #define GEN6_OFFSET(x) ((x)<<19)
5927 #define GEN6_AGGRESSIVE_TURBO (0<<15)
5928 #define GEN6_RC_VIDEO_FREQ 0xA00C
5929 #define GEN6_RC_CONTROL 0xA090
5930 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
5931 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
5932 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
5933 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
5934 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
5935 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
5936 #define GEN7_RC_CTL_TO_MODE (1<<28)
5937 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
5938 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
5939 #define GEN6_RP_DOWN_TIMEOUT 0xA010
5940 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
5941 #define GEN6_RPSTAT1 0xA01C
5942 #define GEN6_CAGF_SHIFT 8
5943 #define HSW_CAGF_SHIFT 7
5944 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
5945 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
5946 #define GEN6_RP_CONTROL 0xA024
5947 #define GEN6_RP_MEDIA_TURBO (1<<11)
5948 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
5949 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
5950 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
5951 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
5952 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
5953 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
5954 #define GEN6_RP_ENABLE (1<<7)
5955 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
5956 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
5957 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
5958 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
5959 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
5960 #define GEN6_RP_UP_THRESHOLD 0xA02C
5961 #define GEN6_RP_DOWN_THRESHOLD 0xA030
5962 #define GEN6_RP_CUR_UP_EI 0xA050
5963 #define GEN6_CURICONT_MASK 0xffffff
5964 #define GEN6_RP_CUR_UP 0xA054
5965 #define GEN6_CURBSYTAVG_MASK 0xffffff
5966 #define GEN6_RP_PREV_UP 0xA058
5967 #define GEN6_RP_CUR_DOWN_EI 0xA05C
5968 #define GEN6_CURIAVG_MASK 0xffffff
5969 #define GEN6_RP_CUR_DOWN 0xA060
5970 #define GEN6_RP_PREV_DOWN 0xA064
5971 #define GEN6_RP_UP_EI 0xA068
5972 #define GEN6_RP_DOWN_EI 0xA06C
5973 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
5974 #define GEN6_RPDEUHWTC 0xA080
5975 #define GEN6_RPDEUC 0xA084
5976 #define GEN6_RPDEUCSW 0xA088
5977 #define GEN6_RC_STATE 0xA094
5978 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
5979 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
5980 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
5981 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
5982 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
5983 #define GEN6_RC_SLEEP 0xA0B0
5984 #define GEN6_RCUBMABDTMR 0xA0B0
5985 #define GEN6_RC1e_THRESHOLD 0xA0B4
5986 #define GEN6_RC6_THRESHOLD 0xA0B8
5987 #define GEN6_RC6p_THRESHOLD 0xA0BC
5988 #define VLV_RCEDATA 0xA0BC
5989 #define GEN6_RC6pp_THRESHOLD 0xA0C0
5990 #define GEN6_PMINTRMSK 0xA168
5991 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
5992 #define VLV_PWRDWNUPCTL 0xA294
5994 #define GEN6_PMISR 0x44020
5995 #define GEN6_PMIMR 0x44024 /* rps_lock */
5996 #define GEN6_PMIIR 0x44028
5997 #define GEN6_PMIER 0x4402C
5998 #define GEN6_PM_MBOX_EVENT (1<<25)
5999 #define GEN6_PM_THERMAL_EVENT (1<<24)
6000 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
6001 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
6002 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
6003 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
6004 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
6005 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
6006 GEN6_PM_RP_DOWN_THRESHOLD | \
6007 GEN6_PM_RP_DOWN_TIMEOUT)
6009 #define GEN7_GT_SCRATCH_BASE 0x4F100
6010 #define GEN7_GT_SCRATCH_REG_NUM 8
6012 #define VLV_GTLC_SURVIVABILITY_REG 0x130098
6013 #define VLV_GFX_CLK_STATUS_BIT (1<<3)
6014 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
6016 #define GEN6_GT_GFX_RC6_LOCKED 0x138104
6017 #define VLV_COUNTER_CONTROL 0x138104
6018 #define VLV_COUNT_RANGE_HIGH (1<<15)
6019 #define VLV_MEDIA_RC0_COUNT_EN (1<<5)
6020 #define VLV_RENDER_RC0_COUNT_EN (1<<4)
6021 #define VLV_MEDIA_RC6_COUNT_EN (1<<1)
6022 #define VLV_RENDER_RC6_COUNT_EN (1<<0)
6023 #define GEN6_GT_GFX_RC6 0x138108
6024 #define VLV_GT_RENDER_RC6 0x138108
6025 #define VLV_GT_MEDIA_RC6 0x13810C
6027 #define GEN6_GT_GFX_RC6p 0x13810C
6028 #define GEN6_GT_GFX_RC6pp 0x138110
6029 #define VLV_RENDER_C0_COUNT_REG 0x138118
6030 #define VLV_MEDIA_C0_COUNT_REG 0x13811C
6032 #define GEN6_PCODE_MAILBOX 0x138124
6033 #define GEN6_PCODE_READY (1<<31)
6034 #define GEN6_READ_OC_PARAMS 0xc
6035 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
6036 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
6037 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
6038 #define GEN6_PCODE_READ_RC6VIDS 0x5
6039 #define GEN6_PCODE_READ_D_COMP 0x10
6040 #define GEN6_PCODE_WRITE_D_COMP 0x11
6041 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
6042 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
6043 #define DISPLAY_IPS_CONTROL 0x19
6044 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
6045 #define GEN6_PCODE_DATA 0x138128
6046 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
6047 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
6048 #define GEN6_PCODE_DATA1 0x13812C
6050 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
6051 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
6052 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
6053 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
6054 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
6056 #define GEN6_GT_CORE_STATUS 0x138060
6057 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
6058 #define GEN6_RCn_MASK 7
6064 #define GEN7_MISCCPCTL (0x9424)
6065 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
6068 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
6069 #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
6070 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
6071 #define GEN7_PARITY_ERROR_VALID (1<<13)
6072 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
6073 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
6074 #define GEN7_PARITY_ERROR_ROW(reg) \
6075 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
6076 #define GEN7_PARITY_ERROR_BANK(reg) \
6077 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
6078 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
6079 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
6080 #define GEN7_L3CDERRST1_ENABLE (1<<7)
6082 #define GEN7_L3LOG_BASE 0xB070
6083 #define HSW_L3LOG_BASE_SLICE1 0xB270
6084 #define GEN7_L3LOG_SIZE 0x80
6086 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
6087 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
6088 #define GEN7_MAX_PS_THREAD_DEP (8<<12)
6089 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
6090 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
6092 #define GEN9_HALF_SLICE_CHICKEN5 0xe188
6093 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
6095 #define GEN8_ROW_CHICKEN 0xe4f0
6096 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
6097 #define STALL_DOP_GATING_DISABLE (1<<5)
6099 #define GEN7_ROW_CHICKEN2 0xe4f4
6100 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
6101 #define DOP_CLOCK_GATING_DISABLE (1<<0)
6103 #define HSW_ROW_CHICKEN3 0xe49c
6104 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
6106 #define HALF_SLICE_CHICKEN3 0xe184
6107 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
6108 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
6111 #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
6112 #define INTEL_AUDIO_DEVCL 0x808629FB
6113 #define INTEL_AUDIO_DEVBLC 0x80862801
6114 #define INTEL_AUDIO_DEVCTG 0x80862802
6116 #define G4X_AUD_CNTL_ST 0x620B4
6117 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
6118 #define G4X_ELDV_DEVCTG (1 << 14)
6119 #define G4X_ELD_ADDR_MASK (0xf << 5)
6120 #define G4X_ELD_ACK (1 << 4)
6121 #define G4X_HDMIW_HDMIEDID 0x6210C
6123 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
6124 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
6125 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6126 _IBX_HDMIW_HDMIEDID_A, \
6127 _IBX_HDMIW_HDMIEDID_B)
6128 #define _IBX_AUD_CNTL_ST_A 0xE20B4
6129 #define _IBX_AUD_CNTL_ST_B 0xE21B4
6130 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6131 _IBX_AUD_CNTL_ST_A, \
6133 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
6134 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
6135 #define IBX_ELD_ACK (1 << 4)
6136 #define IBX_AUD_CNTL_ST2 0xE20C0
6137 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
6138 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
6140 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
6141 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
6142 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6143 _CPT_HDMIW_HDMIEDID_A, \
6144 _CPT_HDMIW_HDMIEDID_B)
6145 #define _CPT_AUD_CNTL_ST_A 0xE50B4
6146 #define _CPT_AUD_CNTL_ST_B 0xE51B4
6147 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6148 _CPT_AUD_CNTL_ST_A, \
6150 #define CPT_AUD_CNTRL_ST2 0xE50C0
6152 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
6153 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
6154 #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6155 _VLV_HDMIW_HDMIEDID_A, \
6156 _VLV_HDMIW_HDMIEDID_B)
6157 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
6158 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
6159 #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6160 _VLV_AUD_CNTL_ST_A, \
6162 #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
6164 /* These are the 4 32-bit write offset registers for each stream
6165 * output buffer. It determines the offset from the
6166 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
6168 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
6170 #define _IBX_AUD_CONFIG_A 0xe2000
6171 #define _IBX_AUD_CONFIG_B 0xe2100
6172 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
6173 _IBX_AUD_CONFIG_A, \
6175 #define _CPT_AUD_CONFIG_A 0xe5000
6176 #define _CPT_AUD_CONFIG_B 0xe5100
6177 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
6178 _CPT_AUD_CONFIG_A, \
6180 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
6181 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
6182 #define VLV_AUD_CFG(pipe) _PIPE(pipe, \
6183 _VLV_AUD_CONFIG_A, \
6186 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
6187 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
6188 #define AUD_CONFIG_UPPER_N_SHIFT 20
6189 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
6190 #define AUD_CONFIG_LOWER_N_SHIFT 4
6191 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
6192 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
6193 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
6194 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
6195 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
6196 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
6197 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
6198 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
6199 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
6200 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
6201 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
6202 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
6203 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
6204 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
6207 #define _HSW_AUD_CONFIG_A 0x65000
6208 #define _HSW_AUD_CONFIG_B 0x65100
6209 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \
6210 _HSW_AUD_CONFIG_A, \
6213 #define _HSW_AUD_MISC_CTRL_A 0x65010
6214 #define _HSW_AUD_MISC_CTRL_B 0x65110
6215 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
6216 _HSW_AUD_MISC_CTRL_A, \
6217 _HSW_AUD_MISC_CTRL_B)
6219 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
6220 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
6221 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
6222 _HSW_AUD_DIP_ELD_CTRL_ST_A, \
6223 _HSW_AUD_DIP_ELD_CTRL_ST_B)
6225 /* Audio Digital Converter */
6226 #define _HSW_AUD_DIG_CNVT_1 0x65080
6227 #define _HSW_AUD_DIG_CNVT_2 0x65180
6228 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
6229 _HSW_AUD_DIG_CNVT_1, \
6230 _HSW_AUD_DIG_CNVT_2)
6231 #define DIP_PORT_SEL_MASK 0x3
6233 #define _HSW_AUD_EDID_DATA_A 0x65050
6234 #define _HSW_AUD_EDID_DATA_B 0x65150
6235 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
6236 _HSW_AUD_EDID_DATA_A, \
6237 _HSW_AUD_EDID_DATA_B)
6239 #define HSW_AUD_PIPE_CONV_CFG 0x6507c
6240 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0
6241 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
6242 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
6243 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
6244 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
6246 /* HSW Power Wells */
6247 #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
6248 #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
6249 #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
6250 #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
6251 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
6252 #define HSW_PWR_WELL_STATE_ENABLED (1<<30)
6253 #define HSW_PWR_WELL_CTL5 0x45410
6254 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
6255 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
6256 #define HSW_PWR_WELL_FORCE_ON (1<<19)
6257 #define HSW_PWR_WELL_CTL6 0x45414
6259 /* Per-pipe DDI Function Control */
6260 #define TRANS_DDI_FUNC_CTL_A 0x60400
6261 #define TRANS_DDI_FUNC_CTL_B 0x61400
6262 #define TRANS_DDI_FUNC_CTL_C 0x62400
6263 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400
6264 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
6266 #define TRANS_DDI_FUNC_ENABLE (1<<31)
6267 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
6268 #define TRANS_DDI_PORT_MASK (7<<28)
6269 #define TRANS_DDI_PORT_SHIFT 28
6270 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
6271 #define TRANS_DDI_PORT_NONE (0<<28)
6272 #define TRANS_DDI_MODE_SELECT_MASK (7<<24)
6273 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
6274 #define TRANS_DDI_MODE_SELECT_DVI (1<<24)
6275 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
6276 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
6277 #define TRANS_DDI_MODE_SELECT_FDI (4<<24)
6278 #define TRANS_DDI_BPC_MASK (7<<20)
6279 #define TRANS_DDI_BPC_8 (0<<20)
6280 #define TRANS_DDI_BPC_10 (1<<20)
6281 #define TRANS_DDI_BPC_6 (2<<20)
6282 #define TRANS_DDI_BPC_12 (3<<20)
6283 #define TRANS_DDI_PVSYNC (1<<17)
6284 #define TRANS_DDI_PHSYNC (1<<16)
6285 #define TRANS_DDI_EDP_INPUT_MASK (7<<12)
6286 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
6287 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
6288 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
6289 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
6290 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
6291 #define TRANS_DDI_BFI_ENABLE (1<<4)
6293 /* DisplayPort Transport Control */
6294 #define DP_TP_CTL_A 0x64040
6295 #define DP_TP_CTL_B 0x64140
6296 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
6297 #define DP_TP_CTL_ENABLE (1<<31)
6298 #define DP_TP_CTL_MODE_SST (0<<27)
6299 #define DP_TP_CTL_MODE_MST (1<<27)
6300 #define DP_TP_CTL_FORCE_ACT (1<<25)
6301 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
6302 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
6303 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
6304 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
6305 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
6306 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
6307 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
6308 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
6309 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
6311 /* DisplayPort Transport Status */
6312 #define DP_TP_STATUS_A 0x64044
6313 #define DP_TP_STATUS_B 0x64144
6314 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
6315 #define DP_TP_STATUS_IDLE_DONE (1<<25)
6316 #define DP_TP_STATUS_ACT_SENT (1<<24)
6317 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
6318 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
6319 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
6320 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
6321 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
6323 /* DDI Buffer Control */
6324 #define DDI_BUF_CTL_A 0x64000
6325 #define DDI_BUF_CTL_B 0x64100
6326 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
6327 #define DDI_BUF_CTL_ENABLE (1<<31)
6328 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
6329 #define DDI_BUF_EMP_MASK (0xf<<24)
6330 #define DDI_BUF_PORT_REVERSAL (1<<16)
6331 #define DDI_BUF_IS_IDLE (1<<7)
6332 #define DDI_A_4_LANES (1<<4)
6333 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
6334 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
6336 /* DDI Buffer Translations */
6337 #define DDI_BUF_TRANS_A 0x64E00
6338 #define DDI_BUF_TRANS_B 0x64E60
6339 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
6341 /* Sideband Interface (SBI) is programmed indirectly, via
6342 * SBI_ADDR, which contains the register offset; and SBI_DATA,
6343 * which contains the payload */
6344 #define SBI_ADDR 0xC6000
6345 #define SBI_DATA 0xC6004
6346 #define SBI_CTL_STAT 0xC6008
6347 #define SBI_CTL_DEST_ICLK (0x0<<16)
6348 #define SBI_CTL_DEST_MPHY (0x1<<16)
6349 #define SBI_CTL_OP_IORD (0x2<<8)
6350 #define SBI_CTL_OP_IOWR (0x3<<8)
6351 #define SBI_CTL_OP_CRRD (0x6<<8)
6352 #define SBI_CTL_OP_CRWR (0x7<<8)
6353 #define SBI_RESPONSE_FAIL (0x1<<1)
6354 #define SBI_RESPONSE_SUCCESS (0x0<<1)
6355 #define SBI_BUSY (0x1<<0)
6356 #define SBI_READY (0x0<<0)
6359 #define SBI_SSCDIVINTPHASE6 0x0600
6360 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
6361 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
6362 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
6363 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
6364 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
6365 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
6366 #define SBI_SSCCTL 0x020c
6367 #define SBI_SSCCTL6 0x060C
6368 #define SBI_SSCCTL_PATHALT (1<<3)
6369 #define SBI_SSCCTL_DISABLE (1<<0)
6370 #define SBI_SSCAUXDIV6 0x0610
6371 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
6372 #define SBI_DBUFF0 0x2a00
6373 #define SBI_GEN0 0x1f00
6374 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
6376 /* LPT PIXCLK_GATE */
6377 #define PIXCLK_GATE 0xC6020
6378 #define PIXCLK_GATE_UNGATE (1<<0)
6379 #define PIXCLK_GATE_GATE (0<<0)
6382 #define SPLL_CTL 0x46020
6383 #define SPLL_PLL_ENABLE (1<<31)
6384 #define SPLL_PLL_SSC (1<<28)
6385 #define SPLL_PLL_NON_SSC (2<<28)
6386 #define SPLL_PLL_LCPLL (3<<28)
6387 #define SPLL_PLL_REF_MASK (3<<28)
6388 #define SPLL_PLL_FREQ_810MHz (0<<26)
6389 #define SPLL_PLL_FREQ_1350MHz (1<<26)
6390 #define SPLL_PLL_FREQ_2700MHz (2<<26)
6391 #define SPLL_PLL_FREQ_MASK (3<<26)
6394 #define WRPLL_CTL1 0x46040
6395 #define WRPLL_CTL2 0x46060
6396 #define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
6397 #define WRPLL_PLL_ENABLE (1<<31)
6398 #define WRPLL_PLL_SSC (1<<28)
6399 #define WRPLL_PLL_NON_SSC (2<<28)
6400 #define WRPLL_PLL_LCPLL (3<<28)
6401 #define WRPLL_PLL_REF_MASK (3<<28)
6402 /* WRPLL divider programming */
6403 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
6404 #define WRPLL_DIVIDER_REF_MASK (0xff)
6405 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
6406 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
6407 #define WRPLL_DIVIDER_POST_SHIFT 8
6408 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
6409 #define WRPLL_DIVIDER_FB_SHIFT 16
6410 #define WRPLL_DIVIDER_FB_MASK (0xff<<16)
6412 /* Port clock selection */
6413 #define PORT_CLK_SEL_A 0x46100
6414 #define PORT_CLK_SEL_B 0x46104
6415 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
6416 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
6417 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
6418 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
6419 #define PORT_CLK_SEL_SPLL (3<<29)
6420 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
6421 #define PORT_CLK_SEL_WRPLL1 (4<<29)
6422 #define PORT_CLK_SEL_WRPLL2 (5<<29)
6423 #define PORT_CLK_SEL_NONE (7<<29)
6424 #define PORT_CLK_SEL_MASK (7<<29)
6426 /* Transcoder clock selection */
6427 #define TRANS_CLK_SEL_A 0x46140
6428 #define TRANS_CLK_SEL_B 0x46144
6429 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
6430 /* For each transcoder, we need to select the corresponding port clock */
6431 #define TRANS_CLK_SEL_DISABLED (0x0<<29)
6432 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
6434 #define TRANSA_MSA_MISC 0x60410
6435 #define TRANSB_MSA_MISC 0x61410
6436 #define TRANSC_MSA_MISC 0x62410
6437 #define TRANS_EDP_MSA_MISC 0x6f410
6438 #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
6440 #define TRANS_MSA_SYNC_CLK (1<<0)
6441 #define TRANS_MSA_6_BPC (0<<5)
6442 #define TRANS_MSA_8_BPC (1<<5)
6443 #define TRANS_MSA_10_BPC (2<<5)
6444 #define TRANS_MSA_12_BPC (3<<5)
6445 #define TRANS_MSA_16_BPC (4<<5)
6448 #define LCPLL_CTL 0x130040
6449 #define LCPLL_PLL_DISABLE (1<<31)
6450 #define LCPLL_PLL_LOCK (1<<30)
6451 #define LCPLL_CLK_FREQ_MASK (3<<26)
6452 #define LCPLL_CLK_FREQ_450 (0<<26)
6453 #define LCPLL_CLK_FREQ_54O_BDW (1<<26)
6454 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
6455 #define LCPLL_CLK_FREQ_675_BDW (3<<26)
6456 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
6457 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
6458 #define LCPLL_POWER_DOWN_ALLOW (1<<22)
6459 #define LCPLL_CD_SOURCE_FCLK (1<<21)
6460 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
6467 #define CDCLK_CTL 0x46000
6468 #define CDCLK_FREQ_SEL_MASK (3<<26)
6469 #define CDCLK_FREQ_450_432 (0<<26)
6470 #define CDCLK_FREQ_540 (1<<26)
6471 #define CDCLK_FREQ_337_308 (2<<26)
6472 #define CDCLK_FREQ_675_617 (3<<26)
6473 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
6476 #define LCPLL1_CTL 0x46010
6477 #define LCPLL2_CTL 0x46014
6478 #define LCPLL_PLL_ENABLE (1<<31)
6481 #define DPLL_CTRL1 0x6C058
6482 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
6483 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
6484 #define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
6485 #define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1)
6486 #define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
6487 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
6488 #define DPLL_CRTL1_LINK_RATE_2700 0
6489 #define DPLL_CRTL1_LINK_RATE_1350 1
6490 #define DPLL_CRTL1_LINK_RATE_810 2
6491 #define DPLL_CRTL1_LINK_RATE_1620 3
6492 #define DPLL_CRTL1_LINK_RATE_1080 4
6493 #define DPLL_CRTL1_LINK_RATE_2160 5
6496 #define DPLL_CTRL2 0x6C05C
6497 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15))
6498 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
6499 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
6500 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1))
6501 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
6504 #define DPLL_STATUS 0x6C060
6505 #define DPLL_LOCK(id) (1<<((id)*8))
6508 #define DPLL1_CFGCR1 0x6C040
6509 #define DPLL2_CFGCR1 0x6C048
6510 #define DPLL3_CFGCR1 0x6C050
6511 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
6512 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
6513 #define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9)
6514 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
6516 #define DPLL1_CFGCR2 0x6C044
6517 #define DPLL2_CFGCR2 0x6C04C
6518 #define DPLL3_CFGCR2 0x6C054
6519 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
6520 #define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8)
6521 #define DPLL_CFGCR2_QDIV_MODE(x) (x<<7)
6522 #define DPLL_CFGCR2_KDIV_MASK (3<<5)
6523 #define DPLL_CFGCR2_KDIV(x) (x<<5)
6524 #define DPLL_CFGCR2_KDIV_5 (0<<5)
6525 #define DPLL_CFGCR2_KDIV_2 (1<<5)
6526 #define DPLL_CFGCR2_KDIV_3 (2<<5)
6527 #define DPLL_CFGCR2_KDIV_1 (3<<5)
6528 #define DPLL_CFGCR2_PDIV_MASK (7<<2)
6529 #define DPLL_CFGCR2_PDIV(x) (x<<2)
6530 #define DPLL_CFGCR2_PDIV_1 (0<<2)
6531 #define DPLL_CFGCR2_PDIV_2 (1<<2)
6532 #define DPLL_CFGCR2_PDIV_3 (2<<2)
6533 #define DPLL_CFGCR2_PDIV_7 (4<<2)
6534 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
6536 #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
6537 #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
6539 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
6540 * since on HSW we can't write to it using I915_WRITE. */
6541 #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
6542 #define D_COMP_BDW 0x138144
6543 #define D_COMP_RCOMP_IN_PROGRESS (1<<9)
6544 #define D_COMP_COMP_FORCE (1<<8)
6545 #define D_COMP_COMP_DISABLE (1<<0)
6547 /* Pipe WM_LINETIME - watermark line time */
6548 #define PIPE_WM_LINETIME_A 0x45270
6549 #define PIPE_WM_LINETIME_B 0x45274
6550 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
6552 #define PIPE_WM_LINETIME_MASK (0x1ff)
6553 #define PIPE_WM_LINETIME_TIME(x) ((x))
6554 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
6555 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
6558 #define SFUSE_STRAP 0xc2014
6559 #define SFUSE_STRAP_FUSE_LOCK (1<<13)
6560 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
6561 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
6562 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
6563 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
6565 #define WM_MISC 0x45260
6566 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
6568 #define WM_DBG 0x45280
6569 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
6570 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
6571 #define WM_DBG_DISALLOW_SPRITE (1<<2)
6574 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
6575 #define _PIPE_A_CSC_COEFF_BY 0x49014
6576 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
6577 #define _PIPE_A_CSC_COEFF_BU 0x4901c
6578 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
6579 #define _PIPE_A_CSC_COEFF_BV 0x49024
6580 #define _PIPE_A_CSC_MODE 0x49028
6581 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
6582 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
6583 #define CSC_MODE_YUV_TO_RGB (1 << 0)
6584 #define _PIPE_A_CSC_PREOFF_HI 0x49030
6585 #define _PIPE_A_CSC_PREOFF_ME 0x49034
6586 #define _PIPE_A_CSC_PREOFF_LO 0x49038
6587 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
6588 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
6589 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
6591 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
6592 #define _PIPE_B_CSC_COEFF_BY 0x49114
6593 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
6594 #define _PIPE_B_CSC_COEFF_BU 0x4911c
6595 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
6596 #define _PIPE_B_CSC_COEFF_BV 0x49124
6597 #define _PIPE_B_CSC_MODE 0x49128
6598 #define _PIPE_B_CSC_PREOFF_HI 0x49130
6599 #define _PIPE_B_CSC_PREOFF_ME 0x49134
6600 #define _PIPE_B_CSC_PREOFF_LO 0x49138
6601 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
6602 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
6603 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
6605 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
6606 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
6607 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
6608 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
6609 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
6610 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
6611 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
6612 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
6613 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
6614 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
6615 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
6616 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
6617 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
6619 /* VLV MIPI registers */
6621 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
6622 #define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
6623 #define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \
6625 #define DPI_ENABLE (1 << 31) /* A + B */
6626 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
6627 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
6628 #define DUAL_LINK_MODE_MASK (1 << 26)
6629 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
6630 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
6631 #define DITHERING_ENABLE (1 << 25) /* A + B */
6632 #define FLOPPED_HSTX (1 << 23)
6633 #define DE_INVERT (1 << 19) /* XXX */
6634 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
6635 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
6636 #define AFE_LATCHOUT (1 << 17)
6637 #define LP_OUTPUT_HOLD (1 << 16)
6638 #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
6639 #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
6640 #define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11
6641 #define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
6643 #define CSB_MASK (3 << 9)
6644 #define CSB_20MHZ (0 << 9)
6645 #define CSB_10MHZ (1 << 9)
6646 #define CSB_40MHZ (2 << 9)
6647 #define BANDGAP_MASK (1 << 8)
6648 #define BANDGAP_PNW_CIRCUIT (0 << 8)
6649 #define BANDGAP_LNC_CIRCUIT (1 << 8)
6650 #define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
6651 #define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
6652 #define TEARING_EFFECT_DELAY (1 << 4) /* A + B */
6653 #define TEARING_EFFECT_SHIFT 2 /* A + B */
6654 #define TEARING_EFFECT_MASK (3 << 2)
6655 #define TEARING_EFFECT_OFF (0 << 2)
6656 #define TEARING_EFFECT_DSI (1 << 2)
6657 #define TEARING_EFFECT_GPIO (2 << 2)
6658 #define LANE_CONFIGURATION_SHIFT 0
6659 #define LANE_CONFIGURATION_MASK (3 << 0)
6660 #define LANE_CONFIGURATION_4LANE (0 << 0)
6661 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
6662 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
6664 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
6665 #define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
6666 #define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \
6667 _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
6668 #define TEARING_EFFECT_DELAY_SHIFT 0
6669 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
6671 /* XXX: all bits reserved */
6672 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
6674 /* MIPI DSI Controller and D-PHY registers */
6676 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
6677 #define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
6678 #define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \
6679 _MIPIB_DEVICE_READY)
6680 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
6681 #define ULPS_STATE_MASK (3 << 1)
6682 #define ULPS_STATE_ENTER (2 << 1)
6683 #define ULPS_STATE_EXIT (1 << 1)
6684 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
6685 #define DEVICE_READY (1 << 0)
6687 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
6688 #define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
6689 #define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \
6691 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
6692 #define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
6693 #define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \
6695 #define TEARING_EFFECT (1 << 31)
6696 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
6697 #define GEN_READ_DATA_AVAIL (1 << 29)
6698 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
6699 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
6700 #define RX_PROT_VIOLATION (1 << 26)
6701 #define RX_INVALID_TX_LENGTH (1 << 25)
6702 #define ACK_WITH_NO_ERROR (1 << 24)
6703 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
6704 #define LP_RX_TIMEOUT (1 << 22)
6705 #define HS_TX_TIMEOUT (1 << 21)
6706 #define DPI_FIFO_UNDERRUN (1 << 20)
6707 #define LOW_CONTENTION (1 << 19)
6708 #define HIGH_CONTENTION (1 << 18)
6709 #define TXDSI_VC_ID_INVALID (1 << 17)
6710 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
6711 #define TXCHECKSUM_ERROR (1 << 15)
6712 #define TXECC_MULTIBIT_ERROR (1 << 14)
6713 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
6714 #define TXFALSE_CONTROL_ERROR (1 << 12)
6715 #define RXDSI_VC_ID_INVALID (1 << 11)
6716 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
6717 #define RXCHECKSUM_ERROR (1 << 9)
6718 #define RXECC_MULTIBIT_ERROR (1 << 8)
6719 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
6720 #define RXFALSE_CONTROL_ERROR (1 << 6)
6721 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
6722 #define RX_LP_TX_SYNC_ERROR (1 << 4)
6723 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
6724 #define RXEOT_SYNC_ERROR (1 << 2)
6725 #define RXSOT_SYNC_ERROR (1 << 1)
6726 #define RXSOT_ERROR (1 << 0)
6728 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
6729 #define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
6730 #define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \
6731 _MIPIB_DSI_FUNC_PRG)
6732 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
6733 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
6734 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
6735 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
6736 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
6737 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
6738 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
6739 #define VID_MODE_FORMAT_MASK (0xf << 7)
6740 #define VID_MODE_NOT_SUPPORTED (0 << 7)
6741 #define VID_MODE_FORMAT_RGB565 (1 << 7)
6742 #define VID_MODE_FORMAT_RGB666 (2 << 7)
6743 #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
6744 #define VID_MODE_FORMAT_RGB888 (4 << 7)
6745 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
6746 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
6747 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
6748 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
6749 #define DATA_LANES_PRG_REG_SHIFT 0
6750 #define DATA_LANES_PRG_REG_MASK (7 << 0)
6752 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
6753 #define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
6754 #define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \
6755 _MIPIB_HS_TX_TIMEOUT)
6756 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
6758 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
6759 #define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
6760 #define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \
6761 _MIPIB_LP_RX_TIMEOUT)
6762 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
6764 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
6765 #define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
6766 #define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \
6767 _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
6768 #define TURN_AROUND_TIMEOUT_MASK 0x3f
6770 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
6771 #define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
6772 #define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \
6773 _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
6774 #define DEVICE_RESET_TIMER_MASK 0xffff
6776 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
6777 #define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
6778 #define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \
6779 _MIPIB_DPI_RESOLUTION)
6780 #define VERTICAL_ADDRESS_SHIFT 16
6781 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
6782 #define HORIZONTAL_ADDRESS_SHIFT 0
6783 #define HORIZONTAL_ADDRESS_MASK 0xffff
6785 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
6786 #define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
6787 #define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \
6788 _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
6789 #define DBI_FIFO_EMPTY_HALF (0 << 0)
6790 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
6791 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
6793 /* regs below are bits 15:0 */
6794 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
6795 #define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
6796 #define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \
6797 _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
6799 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
6800 #define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
6801 #define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \
6804 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
6805 #define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
6806 #define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \
6809 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
6810 #define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
6811 #define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \
6812 _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
6814 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
6815 #define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
6816 #define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \
6817 _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
6819 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
6820 #define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
6821 #define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \
6824 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
6825 #define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
6826 #define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \
6829 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
6830 #define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
6831 #define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \
6832 _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
6834 /* regs above are bits 15:0 */
6836 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
6837 #define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
6838 #define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \
6840 #define DPI_LP_MODE (1 << 6)
6841 #define BACKLIGHT_OFF (1 << 5)
6842 #define BACKLIGHT_ON (1 << 4)
6843 #define COLOR_MODE_OFF (1 << 3)
6844 #define COLOR_MODE_ON (1 << 2)
6845 #define TURN_ON (1 << 1)
6846 #define SHUTDOWN (1 << 0)
6848 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
6849 #define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
6850 #define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \
6852 #define COMMAND_BYTE_SHIFT 0
6853 #define COMMAND_BYTE_MASK (0x3f << 0)
6855 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
6856 #define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
6857 #define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \
6859 #define MASTER_INIT_TIMER_SHIFT 0
6860 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
6862 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
6863 #define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
6864 #define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \
6865 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
6866 #define MAX_RETURN_PKT_SIZE_SHIFT 0
6867 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
6869 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
6870 #define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
6871 #define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \
6872 _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
6873 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
6874 #define DISABLE_VIDEO_BTA (1 << 3)
6875 #define IP_TG_CONFIG (1 << 2)
6876 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
6877 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
6878 #define VIDEO_MODE_BURST (3 << 0)
6880 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
6881 #define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
6882 #define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \
6884 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
6885 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
6886 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
6887 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
6888 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
6889 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
6890 #define CLOCKSTOP (1 << 1)
6891 #define EOT_DISABLE (1 << 0)
6893 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
6894 #define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
6895 #define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \
6897 #define LP_BYTECLK_SHIFT 0
6898 #define LP_BYTECLK_MASK (0xffff << 0)
6901 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
6902 #define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
6903 #define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \
6907 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
6908 #define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
6909 #define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \
6912 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
6913 #define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
6914 #define MIPI_LP_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \
6916 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
6917 #define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
6918 #define MIPI_HS_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \
6920 #define LONG_PACKET_WORD_COUNT_SHIFT 8
6921 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
6922 #define SHORT_PACKET_PARAM_SHIFT 8
6923 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
6924 #define VIRTUAL_CHANNEL_SHIFT 6
6925 #define VIRTUAL_CHANNEL_MASK (3 << 6)
6926 #define DATA_TYPE_SHIFT 0
6927 #define DATA_TYPE_MASK (3f << 0)
6928 /* data type values, see include/video/mipi_display.h */
6930 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
6931 #define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
6932 #define MIPI_GEN_FIFO_STAT(tc) _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \
6933 _MIPIB_GEN_FIFO_STAT)
6934 #define DPI_FIFO_EMPTY (1 << 28)
6935 #define DBI_FIFO_EMPTY (1 << 27)
6936 #define LP_CTRL_FIFO_EMPTY (1 << 26)
6937 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
6938 #define LP_CTRL_FIFO_FULL (1 << 24)
6939 #define HS_CTRL_FIFO_EMPTY (1 << 18)
6940 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
6941 #define HS_CTRL_FIFO_FULL (1 << 16)
6942 #define LP_DATA_FIFO_EMPTY (1 << 10)
6943 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
6944 #define LP_DATA_FIFO_FULL (1 << 8)
6945 #define HS_DATA_FIFO_EMPTY (1 << 2)
6946 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
6947 #define HS_DATA_FIFO_FULL (1 << 0)
6949 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
6950 #define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
6951 #define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \
6952 _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
6953 #define DBI_HS_LP_MODE_MASK (1 << 0)
6954 #define DBI_LP_MODE (1 << 0)
6955 #define DBI_HS_MODE (0 << 0)
6957 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
6958 #define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
6959 #define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \
6961 #define EXIT_ZERO_COUNT_SHIFT 24
6962 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
6963 #define TRAIL_COUNT_SHIFT 16
6964 #define TRAIL_COUNT_MASK (0x1f << 16)
6965 #define CLK_ZERO_COUNT_SHIFT 8
6966 #define CLK_ZERO_COUNT_MASK (0xff << 8)
6967 #define PREPARE_COUNT_SHIFT 0
6968 #define PREPARE_COUNT_MASK (0x3f << 0)
6971 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
6972 #define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
6973 #define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \
6976 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
6978 #define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
6980 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \
6981 _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
6982 #define LP_HS_SSW_CNT_SHIFT 16
6983 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
6984 #define HS_LP_PWR_SW_CNT_SHIFT 0
6985 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
6987 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
6988 #define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
6989 #define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \
6990 _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
6991 #define STOP_STATE_STALL_COUNTER_SHIFT 0
6992 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
6994 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
6995 #define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
6996 #define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \
6997 _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
6998 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
6999 #define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
7000 #define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \
7001 _MIPIB_INTR_EN_REG_1)
7002 #define RX_CONTENTION_DETECTED (1 << 0)
7004 /* XXX: only pipe A ?!? */
7005 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
7006 #define DBI_TYPEC_ENABLE (1 << 31)
7007 #define DBI_TYPEC_WIP (1 << 30)
7008 #define DBI_TYPEC_OPTION_SHIFT 28
7009 #define DBI_TYPEC_OPTION_MASK (3 << 28)
7010 #define DBI_TYPEC_FREQ_SHIFT 24
7011 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
7012 #define DBI_TYPEC_OVERRIDE (1 << 8)
7013 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
7014 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
7017 /* MIPI adapter registers */
7019 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
7020 #define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904)
7021 #define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \
7023 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
7024 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
7025 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
7026 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
7027 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
7028 #define READ_REQUEST_PRIORITY_SHIFT 3
7029 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
7030 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
7031 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
7032 #define RGB_FLIP_TO_BGR (1 << 2)
7034 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
7035 #define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
7036 #define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \
7037 _MIPIB_DATA_ADDRESS)
7038 #define DATA_MEM_ADDRESS_SHIFT 5
7039 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
7040 #define DATA_VALID (1 << 0)
7042 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
7043 #define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
7044 #define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \
7046 #define DATA_LENGTH_SHIFT 0
7047 #define DATA_LENGTH_MASK (0xfffff << 0)
7049 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
7050 #define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
7051 #define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \
7052 _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
7053 #define COMMAND_MEM_ADDRESS_SHIFT 5
7054 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
7055 #define AUTO_PWG_ENABLE (1 << 2)
7056 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
7057 #define COMMAND_VALID (1 << 0)
7059 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
7060 #define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
7061 #define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \
7062 _MIPIB_COMMAND_LENGTH)
7063 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
7064 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
7066 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
7067 #define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
7068 #define MIPI_READ_DATA_RETURN(tc, n) \
7069 (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \
7070 + 4 * (n)) /* n: 0...7 */
7072 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
7073 #define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
7074 #define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \
7075 _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
7076 #define READ_DATA_VALID(n) (1 << (n))
7078 /* For UMS only (deprecated): */
7079 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
7080 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
7082 #endif /* _I915_REG_H_ */
projects / cascardo / linux.git / blob