drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  *
  36  * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
  37  * FW_LOADED, FW_FAILED.
  38  *
  39  * Once the firmware is written into the registers status will be moved from
  40  * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
  41  * be moved to FW_FAILED.
  42  */
  43
  44 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
  45 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
  46
  47 #define FIRMWARE_URL  "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
  48
  49 MODULE_FIRMWARE(I915_CSR_SKL);
  50 MODULE_FIRMWARE(I915_CSR_BXT);
  51
  52 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 23)
  53
  54 #define CSR_MAX_FW_SIZE                 0x2FFF
  55 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  56
  57 struct intel_css_header {
  58         /* 0x09 for DMC */
  59         uint32_t module_type;
  60
  61         /* Includes the DMC specific header in dwords */
  62         uint32_t header_len;
  63
  64         /* always value would be 0x10000 */
  65         uint32_t header_ver;
  66
  67         /* Not used */
  68         uint32_t module_id;
  69
  70         /* Not used */
  71         uint32_t module_vendor;
  72
  73         /* in YYYYMMDD format */
  74         uint32_t date;
  75
  76         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  77         uint32_t size;
  78
  79         /* Not used */
  80         uint32_t key_size;
  81
  82         /* Not used */
  83         uint32_t modulus_size;
  84
  85         /* Not used */
  86         uint32_t exponent_size;
  87
  88         /* Not used */
  89         uint32_t reserved1[12];
  90
  91         /* Major Minor */
  92         uint32_t version;
  93
  94         /* Not used */
  95         uint32_t reserved2[8];
  96
  97         /* Not used */
  98         uint32_t kernel_header_info;
  99 } __packed;
 100
 101 struct intel_fw_info {
 102         uint16_t reserved1;
 103
 104         /* Stepping (A, B, C, ..., *). * is a wildcard */
 105         char stepping;
 106
 107         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 108         char substepping;
 109
 110         uint32_t offset;
 111         uint32_t reserved2;
 112 } __packed;
 113
 114 struct intel_package_header {
 115         /* DMC container header length in dwords */
 116         unsigned char header_len;
 117
 118         /* always value would be 0x01 */
 119         unsigned char header_ver;
 120
 121         unsigned char reserved[10];
 122
 123         /* Number of valid entries in the FWInfo array below */
 124         uint32_t num_entries;
 125
 126         struct intel_fw_info fw_info[20];
 127 } __packed;
 128
 129 struct intel_dmc_header {
 130         /* always value would be 0x40403E3E */
 131         uint32_t signature;
 132
 133         /* DMC binary header length */
 134         unsigned char header_len;
 135
 136         /* 0x01 */
 137         unsigned char header_ver;
 138
 139         /* Reserved */
 140         uint16_t dmcc_ver;
 141
 142         /* Major, Minor */
 143         uint32_t        project;
 144
 145         /* Firmware program size (excluding header) in dwords */
 146         uint32_t        fw_size;
 147
 148         /* Major Minor version */
 149         uint32_t fw_version;
 150
 151         /* Number of valid MMIO cycles present. */
 152         uint32_t mmio_count;
 153
 154         /* MMIO address */
 155         uint32_t mmioaddr[8];
 156
 157         /* MMIO data */
 158         uint32_t mmiodata[8];
 159
 160         /* FW filename  */
 161         unsigned char dfile[32];
 162
 163         uint32_t reserved1[2];
 164 } __packed;
 165
 166 struct stepping_info {
 167         char stepping;
 168         char substepping;
 169 };
 170
 171 /*
 172  * Kabylake derivated from Skylake H0, so SKL H0
 173  * is the right firmware for KBL A0 (revid 0).
 174  */
 175 static const struct stepping_info kbl_stepping_info[] = {
 176         {'H', '0'}, {'I', '0'}
 177 };
 178
 179 static const struct stepping_info skl_stepping_info[] = {
 180         {'A', '0'}, {'B', '0'}, {'C', '0'},
 181         {'D', '0'}, {'E', '0'}, {'F', '0'},
 182         {'G', '0'}, {'H', '0'}, {'I', '0'},
 183         {'J', '0'}, {'K', '0'}
 184 };
 185
 186 static const struct stepping_info bxt_stepping_info[] = {
 187         {'A', '0'}, {'A', '1'}, {'A', '2'},
 188         {'B', '0'}, {'B', '1'}, {'B', '2'}
 189 };
 190
 191 static const struct stepping_info *intel_get_stepping_info(struct drm_device *dev)
 192 {
 193         const struct stepping_info *si;
 194         unsigned int size;
 195
 196         if (IS_KABYLAKE(dev)) {
 197                 size = ARRAY_SIZE(kbl_stepping_info);
 198                 si = kbl_stepping_info;
 199         } else if (IS_SKYLAKE(dev)) {
 200                 size = ARRAY_SIZE(skl_stepping_info);
 201                 si = skl_stepping_info;
 202         } else if (IS_BROXTON(dev)) {
 203                 size = ARRAY_SIZE(bxt_stepping_info);
 204                 si = bxt_stepping_info;
 205         } else {
 206                 return NULL;
 207         }
 208
 209         if (INTEL_REVID(dev) < size)
 210                 return si + INTEL_REVID(dev);
 211
 212         return NULL;
 213 }
 214
 215 /**
 216  * intel_csr_load_program() - write the firmware from memory to register.
 217  * @dev_priv: i915 drm device.
 218  *
 219  * CSR firmware is read from a .bin file and kept in internal memory one time.
 220  * Everytime display comes back from low power state this function is called to
 221  * copy the firmware from internal memory to registers.
 222  */
 223 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 224 {
 225         u32 *payload = dev_priv->csr.dmc_payload;
 226         uint32_t i, fw_size;
 227
 228         if (!IS_GEN9(dev_priv)) {
 229                 DRM_ERROR("No CSR support available for this platform\n");
 230                 return;
 231         }
 232
 233         if (!dev_priv->csr.dmc_payload) {
 234                 DRM_ERROR("Tried to program CSR with empty payload\n");
 235                 return;
 236         }
 237
 238         fw_size = dev_priv->csr.dmc_fw_size;
 239         for (i = 0; i < fw_size; i++)
 240                 I915_WRITE(CSR_PROGRAM(i), payload[i]);
 241
 242         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 243                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 244                            dev_priv->csr.mmiodata[i]);
 245         }
 246 }
 247
 248 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 249                               const struct firmware *fw)
 250 {
 251         struct drm_device *dev = dev_priv->dev;
 252         struct intel_css_header *css_header;
 253         struct intel_package_header *package_header;
 254         struct intel_dmc_header *dmc_header;
 255         struct intel_csr *csr = &dev_priv->csr;
 256         const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
 257         char stepping, substepping;
 258         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 259         uint32_t i;
 260         uint32_t *dmc_payload;
 261
 262         if (!fw)
 263                 return NULL;
 264
 265         if (!stepping_info) {
 266                 DRM_ERROR("Unknown stepping info, firmware loading failed\n");
 267                 return NULL;
 268         }
 269
 270         stepping = stepping_info->stepping;
 271         substepping = stepping_info->substepping;
 272
 273         /* Extract CSS Header information*/
 274         css_header = (struct intel_css_header *)fw->data;
 275         if (sizeof(struct intel_css_header) !=
 276             (css_header->header_len * 4)) {
 277                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
 278                           (css_header->header_len * 4));
 279                 return NULL;
 280         }
 281
 282         csr->version = css_header->version;
 283
 284         if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
 285             csr->version < SKL_CSR_VERSION_REQUIRED) {
 286                 DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
 287                          " please upgrade to v%u.%u or later"
 288                            " [" FIRMWARE_URL "].\n",
 289                          CSR_VERSION_MAJOR(csr->version),
 290                          CSR_VERSION_MINOR(csr->version),
 291                          CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
 292                          CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
 293                 return NULL;
 294         }
 295
 296         readcount += sizeof(struct intel_css_header);
 297
 298         /* Extract Package Header information*/
 299         package_header = (struct intel_package_header *)
 300                 &fw->data[readcount];
 301         if (sizeof(struct intel_package_header) !=
 302             (package_header->header_len * 4)) {
 303                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
 304                           (package_header->header_len * 4));
 305                 return NULL;
 306         }
 307         readcount += sizeof(struct intel_package_header);
 308
 309         /* Search for dmc_offset to find firware binary. */
 310         for (i = 0; i < package_header->num_entries; i++) {
 311                 if (package_header->fw_info[i].substepping == '*' &&
 312                     stepping == package_header->fw_info[i].stepping) {
 313                         dmc_offset = package_header->fw_info[i].offset;
 314                         break;
 315                 } else if (stepping == package_header->fw_info[i].stepping &&
 316                         substepping == package_header->fw_info[i].substepping) {
 317                         dmc_offset = package_header->fw_info[i].offset;
 318                         break;
 319                 } else if (package_header->fw_info[i].stepping == '*' &&
 320                            package_header->fw_info[i].substepping == '*')
 321                         dmc_offset = package_header->fw_info[i].offset;
 322         }
 323         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 324                 DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
 325                 return NULL;
 326         }
 327         readcount += dmc_offset;
 328
 329         /* Extract dmc_header information. */
 330         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 331         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 332                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
 333                           (dmc_header->header_len));
 334                 return NULL;
 335         }
 336         readcount += sizeof(struct intel_dmc_header);
 337
 338         /* Cache the dmc header info. */
 339         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 340                 DRM_ERROR("Firmware has wrong mmio count %u\n",
 341                           dmc_header->mmio_count);
 342                 return NULL;
 343         }
 344         csr->mmio_count = dmc_header->mmio_count;
 345         for (i = 0; i < dmc_header->mmio_count; i++) {
 346                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 347                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 348                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
 349                                   dmc_header->mmioaddr[i]);
 350                         return NULL;
 351                 }
 352                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 353                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 354         }
 355
 356         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 357         nbytes = dmc_header->fw_size * 4;
 358         if (nbytes > CSR_MAX_FW_SIZE) {
 359                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
 360                 return NULL;
 361         }
 362         csr->dmc_fw_size = dmc_header->fw_size;
 363
 364         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 365         if (!dmc_payload) {
 366                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 367                 return NULL;
 368         }
 369
 370         memcpy(dmc_payload, &fw->data[readcount], nbytes);
 371
 372         return dmc_payload;
 373 }
 374
 375 static void csr_load_work_fn(struct work_struct *work)
 376 {
 377         struct drm_i915_private *dev_priv;
 378         struct intel_csr *csr;
 379         const struct firmware *fw;
 380         int ret;
 381
 382         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 383         csr = &dev_priv->csr;
 384
 385         ret = request_firmware(&fw, dev_priv->csr.fw_path,
 386                                &dev_priv->dev->pdev->dev);
 387         if (!fw)
 388                 goto out;
 389
 390         dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 391         if (!dev_priv->csr.dmc_payload)
 392                 goto out;
 393
 394         /* load csr program during system boot, as needed for DC states */
 395         intel_csr_load_program(dev_priv);
 396
 397 out:
 398         if (dev_priv->csr.dmc_payload) {
 399                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 400
 401                 DRM_INFO("Finished loading %s (v%u.%u)\n",
 402                          dev_priv->csr.fw_path,
 403                          CSR_VERSION_MAJOR(csr->version),
 404                          CSR_VERSION_MINOR(csr->version));
 405         } else {
 406                 dev_notice(dev_priv->dev->dev,
 407                            "Failed to load DMC firmware"
 408                            " [" FIRMWARE_URL "],"
 409                            " disabling runtime power management.\n");
 410         }
 411
 412         release_firmware(fw);
 413 }
 414
 415 /**
 416  * intel_csr_ucode_init() - initialize the firmware loading.
 417  * @dev_priv: i915 drm device.
 418  *
 419  * This function is called at the time of loading the display driver to read
 420  * firmware from a .bin file and copied into a internal memory.
 421  */
 422 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 423 {
 424         struct intel_csr *csr = &dev_priv->csr;
 425
 426         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 427
 428         if (!HAS_CSR(dev_priv))
 429                 return;
 430
 431         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 432                 csr->fw_path = I915_CSR_SKL;
 433         else if (IS_BROXTON(dev_priv))
 434                 csr->fw_path = I915_CSR_BXT;
 435         else {
 436                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 437                 return;
 438         }
 439
 440         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 441
 442         /*
 443          * Obtain a runtime pm reference, until CSR is loaded,
 444          * to avoid entering runtime-suspend.
 445          */
 446         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 447
 448         schedule_work(&dev_priv->csr.work);
 449 }
 450
 451 /**
 452  * intel_csr_ucode_fini() - unload the CSR firmware.
 453  * @dev_priv: i915 drm device.
 454  *
 455  * Firmmware unloading includes freeing the internal momory and reset the
 456  * firmware loading status.
 457  */
 458 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 459 {
 460         if (!HAS_CSR(dev_priv))
 461                 return;
 462
 463         flush_work(&dev_priv->csr.work);
 464
 465         kfree(dev_priv->csr.dmc_payload);
 466 }