drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  *
  36  * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
  37  * FW_LOADED, FW_FAILED.
  38  *
  39  * Once the firmware is written into the registers status will be moved from
  40  * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
  41  * be moved to FW_FAILED.
  42  */
  43
  44 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
  45 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
  46
  47 MODULE_FIRMWARE(I915_CSR_SKL);
  48 MODULE_FIRMWARE(I915_CSR_BXT);
  49
  50 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 23)
  51
  52 #define CSR_MAX_FW_SIZE                 0x2FFF
  53 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  54
  55 struct intel_css_header {
  56         /* 0x09 for DMC */
  57         uint32_t module_type;
  58
  59         /* Includes the DMC specific header in dwords */
  60         uint32_t header_len;
  61
  62         /* always value would be 0x10000 */
  63         uint32_t header_ver;
  64
  65         /* Not used */
  66         uint32_t module_id;
  67
  68         /* Not used */
  69         uint32_t module_vendor;
  70
  71         /* in YYYYMMDD format */
  72         uint32_t date;
  73
  74         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  75         uint32_t size;
  76
  77         /* Not used */
  78         uint32_t key_size;
  79
  80         /* Not used */
  81         uint32_t modulus_size;
  82
  83         /* Not used */
  84         uint32_t exponent_size;
  85
  86         /* Not used */
  87         uint32_t reserved1[12];
  88
  89         /* Major Minor */
  90         uint32_t version;
  91
  92         /* Not used */
  93         uint32_t reserved2[8];
  94
  95         /* Not used */
  96         uint32_t kernel_header_info;
  97 } __packed;
  98
  99 struct intel_fw_info {
 100         uint16_t reserved1;
 101
 102         /* Stepping (A, B, C, ..., *). * is a wildcard */
 103         char stepping;
 104
 105         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 106         char substepping;
 107
 108         uint32_t offset;
 109         uint32_t reserved2;
 110 } __packed;
 111
 112 struct intel_package_header {
 113         /* DMC container header length in dwords */
 114         unsigned char header_len;
 115
 116         /* always value would be 0x01 */
 117         unsigned char header_ver;
 118
 119         unsigned char reserved[10];
 120
 121         /* Number of valid entries in the FWInfo array below */
 122         uint32_t num_entries;
 123
 124         struct intel_fw_info fw_info[20];
 125 } __packed;
 126
 127 struct intel_dmc_header {
 128         /* always value would be 0x40403E3E */
 129         uint32_t signature;
 130
 131         /* DMC binary header length */
 132         unsigned char header_len;
 133
 134         /* 0x01 */
 135         unsigned char header_ver;
 136
 137         /* Reserved */
 138         uint16_t dmcc_ver;
 139
 140         /* Major, Minor */
 141         uint32_t        project;
 142
 143         /* Firmware program size (excluding header) in dwords */
 144         uint32_t        fw_size;
 145
 146         /* Major Minor version */
 147         uint32_t fw_version;
 148
 149         /* Number of valid MMIO cycles present. */
 150         uint32_t mmio_count;
 151
 152         /* MMIO address */
 153         uint32_t mmioaddr[8];
 154
 155         /* MMIO data */
 156         uint32_t mmiodata[8];
 157
 158         /* FW filename  */
 159         unsigned char dfile[32];
 160
 161         uint32_t reserved1[2];
 162 } __packed;
 163
 164 struct stepping_info {
 165         char stepping;
 166         char substepping;
 167 };
 168
 169 /*
 170  * Kabylake derivated from Skylake H0, so SKL H0
 171  * is the right firmware for KBL A0 (revid 0).
 172  */
 173 static const struct stepping_info kbl_stepping_info[] = {
 174         {'H', '0'}, {'I', '0'}
 175 };
 176
 177 static const struct stepping_info skl_stepping_info[] = {
 178         {'A', '0'}, {'B', '0'}, {'C', '0'},
 179         {'D', '0'}, {'E', '0'}, {'F', '0'},
 180         {'G', '0'}, {'H', '0'}, {'I', '0'}
 181 };
 182
 183 static const struct stepping_info bxt_stepping_info[] = {
 184         {'A', '0'}, {'A', '1'}, {'A', '2'},
 185         {'B', '0'}, {'B', '1'}, {'B', '2'}
 186 };
 187
 188 static const struct stepping_info *intel_get_stepping_info(struct drm_device *dev)
 189 {
 190         const struct stepping_info *si;
 191         unsigned int size;
 192
 193         if (IS_KABYLAKE(dev)) {
 194                 size = ARRAY_SIZE(kbl_stepping_info);
 195                 si = kbl_stepping_info;
 196         } else if (IS_SKYLAKE(dev)) {
 197                 size = ARRAY_SIZE(skl_stepping_info);
 198                 si = skl_stepping_info;
 199         } else if (IS_BROXTON(dev)) {
 200                 size = ARRAY_SIZE(bxt_stepping_info);
 201                 si = bxt_stepping_info;
 202         } else {
 203                 return NULL;
 204         }
 205
 206         if (INTEL_REVID(dev) < size)
 207                 return si + INTEL_REVID(dev);
 208
 209         return NULL;
 210 }
 211
 212 /**
 213  * intel_csr_load_program() - write the firmware from memory to register.
 214  * @dev_priv: i915 drm device.
 215  *
 216  * CSR firmware is read from a .bin file and kept in internal memory one time.
 217  * Everytime display comes back from low power state this function is called to
 218  * copy the firmware from internal memory to registers.
 219  */
 220 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 221 {
 222         u32 *payload = dev_priv->csr.dmc_payload;
 223         uint32_t i, fw_size;
 224
 225         if (!IS_GEN9(dev_priv)) {
 226                 DRM_ERROR("No CSR support available for this platform\n");
 227                 return;
 228         }
 229
 230         if (!dev_priv->csr.dmc_payload) {
 231                 DRM_ERROR("Tried to program CSR with empty payload\n");
 232                 return;
 233         }
 234
 235         fw_size = dev_priv->csr.dmc_fw_size;
 236         for (i = 0; i < fw_size; i++)
 237                 I915_WRITE(CSR_PROGRAM(i), payload[i]);
 238
 239         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 240                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 241                            dev_priv->csr.mmiodata[i]);
 242         }
 243 }
 244
 245 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 246                               const struct firmware *fw)
 247 {
 248         struct drm_device *dev = dev_priv->dev;
 249         struct intel_css_header *css_header;
 250         struct intel_package_header *package_header;
 251         struct intel_dmc_header *dmc_header;
 252         struct intel_csr *csr = &dev_priv->csr;
 253         const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
 254         char stepping, substepping;
 255         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 256         uint32_t i;
 257         uint32_t *dmc_payload;
 258
 259         if (!fw)
 260                 return NULL;
 261
 262         if (!stepping_info) {
 263                 DRM_ERROR("Unknown stepping info, firmware loading failed\n");
 264                 return NULL;
 265         }
 266
 267         stepping = stepping_info->stepping;
 268         substepping = stepping_info->substepping;
 269
 270         /* Extract CSS Header information*/
 271         css_header = (struct intel_css_header *)fw->data;
 272         if (sizeof(struct intel_css_header) !=
 273             (css_header->header_len * 4)) {
 274                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
 275                           (css_header->header_len * 4));
 276                 return NULL;
 277         }
 278
 279         csr->version = css_header->version;
 280
 281         if (IS_SKYLAKE(dev) && csr->version < SKL_CSR_VERSION_REQUIRED) {
 282                 DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
 283                          " please upgrade to v%u.%u or later"
 284                          " [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n",
 285                          CSR_VERSION_MAJOR(csr->version),
 286                          CSR_VERSION_MINOR(csr->version),
 287                          CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
 288                          CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
 289                 return NULL;
 290         }
 291
 292         readcount += sizeof(struct intel_css_header);
 293
 294         /* Extract Package Header information*/
 295         package_header = (struct intel_package_header *)
 296                 &fw->data[readcount];
 297         if (sizeof(struct intel_package_header) !=
 298             (package_header->header_len * 4)) {
 299                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
 300                           (package_header->header_len * 4));
 301                 return NULL;
 302         }
 303         readcount += sizeof(struct intel_package_header);
 304
 305         /* Search for dmc_offset to find firware binary. */
 306         for (i = 0; i < package_header->num_entries; i++) {
 307                 if (package_header->fw_info[i].substepping == '*' &&
 308                     stepping == package_header->fw_info[i].stepping) {
 309                         dmc_offset = package_header->fw_info[i].offset;
 310                         break;
 311                 } else if (stepping == package_header->fw_info[i].stepping &&
 312                         substepping == package_header->fw_info[i].substepping) {
 313                         dmc_offset = package_header->fw_info[i].offset;
 314                         break;
 315                 } else if (package_header->fw_info[i].stepping == '*' &&
 316                            package_header->fw_info[i].substepping == '*')
 317                         dmc_offset = package_header->fw_info[i].offset;
 318         }
 319         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 320                 DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
 321                 return NULL;
 322         }
 323         readcount += dmc_offset;
 324
 325         /* Extract dmc_header information. */
 326         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 327         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 328                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
 329                           (dmc_header->header_len));
 330                 return NULL;
 331         }
 332         readcount += sizeof(struct intel_dmc_header);
 333
 334         /* Cache the dmc header info. */
 335         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 336                 DRM_ERROR("Firmware has wrong mmio count %u\n",
 337                           dmc_header->mmio_count);
 338                 return NULL;
 339         }
 340         csr->mmio_count = dmc_header->mmio_count;
 341         for (i = 0; i < dmc_header->mmio_count; i++) {
 342                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 343                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 344                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
 345                                   dmc_header->mmioaddr[i]);
 346                         return NULL;
 347                 }
 348                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 349                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 350         }
 351
 352         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 353         nbytes = dmc_header->fw_size * 4;
 354         if (nbytes > CSR_MAX_FW_SIZE) {
 355                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
 356                 return NULL;
 357         }
 358         csr->dmc_fw_size = dmc_header->fw_size;
 359
 360         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 361         if (!dmc_payload) {
 362                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 363                 return NULL;
 364         }
 365
 366         memcpy(dmc_payload, &fw->data[readcount], nbytes);
 367
 368         return dmc_payload;
 369 }
 370
 371 static void csr_load_work_fn(struct work_struct *work)
 372 {
 373         struct drm_i915_private *dev_priv;
 374         struct intel_csr *csr;
 375         const struct firmware *fw;
 376         int ret;
 377
 378         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 379         csr = &dev_priv->csr;
 380
 381         ret = request_firmware(&fw, dev_priv->csr.fw_path,
 382                                &dev_priv->dev->pdev->dev);
 383         if (!fw)
 384                 goto out;
 385
 386         dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 387         if (!dev_priv->csr.dmc_payload)
 388                 goto out;
 389
 390         /* load csr program during system boot, as needed for DC states */
 391         intel_csr_load_program(dev_priv);
 392
 393 out:
 394         if (dev_priv->csr.dmc_payload) {
 395                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 396
 397                 DRM_INFO("Finished loading %s (v%u.%u)\n",
 398                          dev_priv->csr.fw_path,
 399                          CSR_VERSION_MAJOR(csr->version),
 400                          CSR_VERSION_MINOR(csr->version));
 401         } else {
 402                 DRM_ERROR("Failed to load DMC firmware, disabling rpm\n");
 403         }
 404
 405         release_firmware(fw);
 406 }
 407
 408 /**
 409  * intel_csr_ucode_init() - initialize the firmware loading.
 410  * @dev_priv: i915 drm device.
 411  *
 412  * This function is called at the time of loading the display driver to read
 413  * firmware from a .bin file and copied into a internal memory.
 414  */
 415 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 416 {
 417         struct intel_csr *csr = &dev_priv->csr;
 418
 419         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 420
 421         if (!HAS_CSR(dev_priv))
 422                 return;
 423
 424         if (IS_SKYLAKE(dev_priv))
 425                 csr->fw_path = I915_CSR_SKL;
 426         else if (IS_BROXTON(dev_priv))
 427                 csr->fw_path = I915_CSR_BXT;
 428         else {
 429                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 430                 return;
 431         }
 432
 433         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 434
 435         /*
 436          * Obtain a runtime pm reference, until CSR is loaded,
 437          * to avoid entering runtime-suspend.
 438          */
 439         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 440
 441         schedule_work(&dev_priv->csr.work);
 442 }
 443
 444 /**
 445  * intel_csr_ucode_fini() - unload the CSR firmware.
 446  * @dev_priv: i915 drm device.
 447  *
 448  * Firmmware unloading includes freeing the internal momory and reset the
 449  * firmware loading status.
 450  */
 451 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 452 {
 453         if (!HAS_CSR(dev_priv))
 454                 return;
 455
 456         flush_work(&dev_priv->csr.work);
 457
 458         kfree(dev_priv->csr.dmc_payload);
 459 }