drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 /* returns HPLL frequency in kHz */
 137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 138 {
 139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 140
 141         /* Obtain SKU information */
 142         mutex_lock(&dev_priv->sb_lock);
 143         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 144                 CCK_FUSE_HPLL_FREQ_MASK;
 145         mutex_unlock(&dev_priv->sb_lock);
 146
 147         return vco_freq[hpll_freq] * 1000;
 148 }
 149
 150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 151                                   const char *name, u32 reg)
 152 {
 153         u32 val;
 154         int divider;
 155
 156         if (dev_priv->hpll_freq == 0)
 157                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 170 }
 171
 172 int
 173 intel_pch_rawclk(struct drm_device *dev)
 174 {
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176
 177         WARN_ON(!HAS_PCH_SPLIT(dev));
 178
 179         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 180 }
 181
 182 /* hrawclock is 1/4 the FSB frequency */
 183 int intel_hrawclk(struct drm_device *dev)
 184 {
 185         struct drm_i915_private *dev_priv = dev->dev_private;
 186         uint32_t clkcfg;
 187
 188         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 189         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 190                 return 200;
 191
 192         clkcfg = I915_READ(CLKCFG);
 193         switch (clkcfg & CLKCFG_FSB_MASK) {
 194         case CLKCFG_FSB_400:
 195                 return 100;
 196         case CLKCFG_FSB_533:
 197                 return 133;
 198         case CLKCFG_FSB_667:
 199                 return 166;
 200         case CLKCFG_FSB_800:
 201                 return 200;
 202         case CLKCFG_FSB_1067:
 203                 return 266;
 204         case CLKCFG_FSB_1333:
 205                 return 333;
 206         /* these two are just a guess; one of them might be right */
 207         case CLKCFG_FSB_1600:
 208         case CLKCFG_FSB_1600_ALT:
 209                 return 400;
 210         default:
 211                 return 133;
 212         }
 213 }
 214
 215 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 216 {
 217         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 218                 return;
 219
 220         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 221                                                       CCK_CZ_CLOCK_CONTROL);
 222
 223         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 224 }
 225
 226 static inline u32 /* units of 100MHz */
 227 intel_fdi_link_freq(struct drm_device *dev)
 228 {
 229         if (IS_GEN5(dev)) {
 230                 struct drm_i915_private *dev_priv = dev->dev_private;
 231                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 232         } else
 233                 return 27;
 234 }
 235
 236 static const intel_limit_t intel_limits_i8xx_dac = {
 237         .dot = { .min = 25000, .max = 350000 },
 238         .vco = { .min = 908000, .max = 1512000 },
 239         .n = { .min = 2, .max = 16 },
 240         .m = { .min = 96, .max = 140 },
 241         .m1 = { .min = 18, .max = 26 },
 242         .m2 = { .min = 6, .max = 16 },
 243         .p = { .min = 4, .max = 128 },
 244         .p1 = { .min = 2, .max = 33 },
 245         .p2 = { .dot_limit = 165000,
 246                 .p2_slow = 4, .p2_fast = 2 },
 247 };
 248
 249 static const intel_limit_t intel_limits_i8xx_dvo = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 908000, .max = 1512000 },
 252         .n = { .min = 2, .max = 16 },
 253         .m = { .min = 96, .max = 140 },
 254         .m1 = { .min = 18, .max = 26 },
 255         .m2 = { .min = 6, .max = 16 },
 256         .p = { .min = 4, .max = 128 },
 257         .p1 = { .min = 2, .max = 33 },
 258         .p2 = { .dot_limit = 165000,
 259                 .p2_slow = 4, .p2_fast = 4 },
 260 };
 261
 262 static const intel_limit_t intel_limits_i8xx_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 908000, .max = 1512000 },
 265         .n = { .min = 2, .max = 16 },
 266         .m = { .min = 96, .max = 140 },
 267         .m1 = { .min = 18, .max = 26 },
 268         .m2 = { .min = 6, .max = 16 },
 269         .p = { .min = 4, .max = 128 },
 270         .p1 = { .min = 1, .max = 6 },
 271         .p2 = { .dot_limit = 165000,
 272                 .p2_slow = 14, .p2_fast = 7 },
 273 };
 274
 275 static const intel_limit_t intel_limits_i9xx_sdvo = {
 276         .dot = { .min = 20000, .max = 400000 },
 277         .vco = { .min = 1400000, .max = 2800000 },
 278         .n = { .min = 1, .max = 6 },
 279         .m = { .min = 70, .max = 120 },
 280         .m1 = { .min = 8, .max = 18 },
 281         .m2 = { .min = 3, .max = 7 },
 282         .p = { .min = 5, .max = 80 },
 283         .p1 = { .min = 1, .max = 8 },
 284         .p2 = { .dot_limit = 200000,
 285                 .p2_slow = 10, .p2_fast = 5 },
 286 };
 287
 288 static const intel_limit_t intel_limits_i9xx_lvds = {
 289         .dot = { .min = 20000, .max = 400000 },
 290         .vco = { .min = 1400000, .max = 2800000 },
 291         .n = { .min = 1, .max = 6 },
 292         .m = { .min = 70, .max = 120 },
 293         .m1 = { .min = 8, .max = 18 },
 294         .m2 = { .min = 3, .max = 7 },
 295         .p = { .min = 7, .max = 98 },
 296         .p1 = { .min = 1, .max = 8 },
 297         .p2 = { .dot_limit = 112000,
 298                 .p2_slow = 14, .p2_fast = 7 },
 299 };
 300
 301
 302 static const intel_limit_t intel_limits_g4x_sdvo = {
 303         .dot = { .min = 25000, .max = 270000 },
 304         .vco = { .min = 1750000, .max = 3500000},
 305         .n = { .min = 1, .max = 4 },
 306         .m = { .min = 104, .max = 138 },
 307         .m1 = { .min = 17, .max = 23 },
 308         .m2 = { .min = 5, .max = 11 },
 309         .p = { .min = 10, .max = 30 },
 310         .p1 = { .min = 1, .max = 3},
 311         .p2 = { .dot_limit = 270000,
 312                 .p2_slow = 10,
 313                 .p2_fast = 10
 314         },
 315 };
 316
 317 static const intel_limit_t intel_limits_g4x_hdmi = {
 318         .dot = { .min = 22000, .max = 400000 },
 319         .vco = { .min = 1750000, .max = 3500000},
 320         .n = { .min = 1, .max = 4 },
 321         .m = { .min = 104, .max = 138 },
 322         .m1 = { .min = 16, .max = 23 },
 323         .m2 = { .min = 5, .max = 11 },
 324         .p = { .min = 5, .max = 80 },
 325         .p1 = { .min = 1, .max = 8},
 326         .p2 = { .dot_limit = 165000,
 327                 .p2_slow = 10, .p2_fast = 5 },
 328 };
 329
 330 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 331         .dot = { .min = 20000, .max = 115000 },
 332         .vco = { .min = 1750000, .max = 3500000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 104, .max = 138 },
 335         .m1 = { .min = 17, .max = 23 },
 336         .m2 = { .min = 5, .max = 11 },
 337         .p = { .min = 28, .max = 112 },
 338         .p1 = { .min = 2, .max = 8 },
 339         .p2 = { .dot_limit = 0,
 340                 .p2_slow = 14, .p2_fast = 14
 341         },
 342 };
 343
 344 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 345         .dot = { .min = 80000, .max = 224000 },
 346         .vco = { .min = 1750000, .max = 3500000 },
 347         .n = { .min = 1, .max = 3 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 17, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 14, .max = 42 },
 352         .p1 = { .min = 2, .max = 6 },
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 7, .p2_fast = 7
 355         },
 356 };
 357
 358 static const intel_limit_t intel_limits_pineview_sdvo = {
 359         .dot = { .min = 20000, .max = 400000},
 360         .vco = { .min = 1700000, .max = 3500000 },
 361         /* Pineview's Ncounter is a ring counter */
 362         .n = { .min = 3, .max = 6 },
 363         .m = { .min = 2, .max = 256 },
 364         /* Pineview only has one combined m divider, which we treat as m2. */
 365         .m1 = { .min = 0, .max = 0 },
 366         .m2 = { .min = 0, .max = 254 },
 367         .p = { .min = 5, .max = 80 },
 368         .p1 = { .min = 1, .max = 8 },
 369         .p2 = { .dot_limit = 200000,
 370                 .p2_slow = 10, .p2_fast = 5 },
 371 };
 372
 373 static const intel_limit_t intel_limits_pineview_lvds = {
 374         .dot = { .min = 20000, .max = 400000 },
 375         .vco = { .min = 1700000, .max = 3500000 },
 376         .n = { .min = 3, .max = 6 },
 377         .m = { .min = 2, .max = 256 },
 378         .m1 = { .min = 0, .max = 0 },
 379         .m2 = { .min = 0, .max = 254 },
 380         .p = { .min = 7, .max = 112 },
 381         .p1 = { .min = 1, .max = 8 },
 382         .p2 = { .dot_limit = 112000,
 383                 .p2_slow = 14, .p2_fast = 14 },
 384 };
 385
 386 /* Ironlake / Sandybridge
 387  *
 388  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 389  * the range value for them is (actual_value - 2).
 390  */
 391 static const intel_limit_t intel_limits_ironlake_dac = {
 392         .dot = { .min = 25000, .max = 350000 },
 393         .vco = { .min = 1760000, .max = 3510000 },
 394         .n = { .min = 1, .max = 5 },
 395         .m = { .min = 79, .max = 127 },
 396         .m1 = { .min = 12, .max = 22 },
 397         .m2 = { .min = 5, .max = 9 },
 398         .p = { .min = 5, .max = 80 },
 399         .p1 = { .min = 1, .max = 8 },
 400         .p2 = { .dot_limit = 225000,
 401                 .p2_slow = 10, .p2_fast = 5 },
 402 };
 403
 404 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 405         .dot = { .min = 25000, .max = 350000 },
 406         .vco = { .min = 1760000, .max = 3510000 },
 407         .n = { .min = 1, .max = 3 },
 408         .m = { .min = 79, .max = 118 },
 409         .m1 = { .min = 12, .max = 22 },
 410         .m2 = { .min = 5, .max = 9 },
 411         .p = { .min = 28, .max = 112 },
 412         .p1 = { .min = 2, .max = 8 },
 413         .p2 = { .dot_limit = 225000,
 414                 .p2_slow = 14, .p2_fast = 14 },
 415 };
 416
 417 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 418         .dot = { .min = 25000, .max = 350000 },
 419         .vco = { .min = 1760000, .max = 3510000 },
 420         .n = { .min = 1, .max = 3 },
 421         .m = { .min = 79, .max = 127 },
 422         .m1 = { .min = 12, .max = 22 },
 423         .m2 = { .min = 5, .max = 9 },
 424         .p = { .min = 14, .max = 56 },
 425         .p1 = { .min = 2, .max = 8 },
 426         .p2 = { .dot_limit = 225000,
 427                 .p2_slow = 7, .p2_fast = 7 },
 428 };
 429
 430 /* LVDS 100mhz refclk limits. */
 431 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 2 },
 435         .m = { .min = 79, .max = 126 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 126 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 42 },
 452         .p1 = { .min = 2, .max = 6 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 static const intel_limit_t intel_limits_vlv = {
 458          /*
 459           * These are the data rate limits (measured in fast clocks)
 460           * since those are the strictest limits we have. The fast
 461           * clock and actual rate limits are more relaxed, so checking
 462           * them would make no difference.
 463           */
 464         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 465         .vco = { .min = 4000000, .max = 6000000 },
 466         .n = { .min = 1, .max = 7 },
 467         .m1 = { .min = 2, .max = 3 },
 468         .m2 = { .min = 11, .max = 156 },
 469         .p1 = { .min = 2, .max = 3 },
 470         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 471 };
 472
 473 static const intel_limit_t intel_limits_chv = {
 474         /*
 475          * These are the data rate limits (measured in fast clocks)
 476          * since those are the strictest limits we have.  The fast
 477          * clock and actual rate limits are more relaxed, so checking
 478          * them would make no difference.
 479          */
 480         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 481         .vco = { .min = 4800000, .max = 6480000 },
 482         .n = { .min = 1, .max = 1 },
 483         .m1 = { .min = 2, .max = 2 },
 484         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 485         .p1 = { .min = 2, .max = 4 },
 486         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 487 };
 488
 489 static const intel_limit_t intel_limits_bxt = {
 490         /* FIXME: find real dot limits */
 491         .dot = { .min = 0, .max = INT_MAX },
 492         .vco = { .min = 4800000, .max = 6700000 },
 493         .n = { .min = 1, .max = 1 },
 494         .m1 = { .min = 2, .max = 2 },
 495         /* FIXME: find real m2 limits */
 496         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 497         .p1 = { .min = 2, .max = 4 },
 498         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 499 };
 500
 501 static bool
 502 needs_modeset(struct drm_crtc_state *state)
 503 {
 504         return drm_atomic_crtc_needs_modeset(state);
 505 }
 506
 507 /**
 508  * Returns whether any output on the specified pipe is of the specified type
 509  */
 510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 511 {
 512         struct drm_device *dev = crtc->base.dev;
 513         struct intel_encoder *encoder;
 514
 515         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 516                 if (encoder->type == type)
 517                         return true;
 518
 519         return false;
 520 }
 521
 522 /**
 523  * Returns whether any output on the specified pipe will have the specified
 524  * type after a staged modeset is complete, i.e., the same as
 525  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 526  * encoder->crtc.
 527  */
 528 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 529                                       int type)
 530 {
 531         struct drm_atomic_state *state = crtc_state->base.state;
 532         struct drm_connector *connector;
 533         struct drm_connector_state *connector_state;
 534         struct intel_encoder *encoder;
 535         int i, num_connectors = 0;
 536
 537         for_each_connector_in_state(state, connector, connector_state, i) {
 538                 if (connector_state->crtc != crtc_state->base.crtc)
 539                         continue;
 540
 541                 num_connectors++;
 542
 543                 encoder = to_intel_encoder(connector_state->best_encoder);
 544                 if (encoder->type == type)
 545                         return true;
 546         }
 547
 548         WARN_ON(num_connectors == 0);
 549
 550         return false;
 551 }
 552
 553 static const intel_limit_t *
 554 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 555 {
 556         struct drm_device *dev = crtc_state->base.crtc->dev;
 557         const intel_limit_t *limit;
 558
 559         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 560                 if (intel_is_dual_link_lvds(dev)) {
 561                         if (refclk == 100000)
 562                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 563                         else
 564                                 limit = &intel_limits_ironlake_dual_lvds;
 565                 } else {
 566                         if (refclk == 100000)
 567                                 limit = &intel_limits_ironlake_single_lvds_100m;
 568                         else
 569                                 limit = &intel_limits_ironlake_single_lvds;
 570                 }
 571         } else
 572                 limit = &intel_limits_ironlake_dac;
 573
 574         return limit;
 575 }
 576
 577 static const intel_limit_t *
 578 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 579 {
 580         struct drm_device *dev = crtc_state->base.crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 584                 if (intel_is_dual_link_lvds(dev))
 585                         limit = &intel_limits_g4x_dual_channel_lvds;
 586                 else
 587                         limit = &intel_limits_g4x_single_channel_lvds;
 588         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 589                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 590                 limit = &intel_limits_g4x_hdmi;
 591         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 592                 limit = &intel_limits_g4x_sdvo;
 593         } else /* The option is for other outputs */
 594                 limit = &intel_limits_i9xx_sdvo;
 595
 596         return limit;
 597 }
 598
 599 static const intel_limit_t *
 600 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 601 {
 602         struct drm_device *dev = crtc_state->base.crtc->dev;
 603         const intel_limit_t *limit;
 604
 605         if (IS_BROXTON(dev))
 606                 limit = &intel_limits_bxt;
 607         else if (HAS_PCH_SPLIT(dev))
 608                 limit = intel_ironlake_limit(crtc_state, refclk);
 609         else if (IS_G4X(dev)) {
 610                 limit = intel_g4x_limit(crtc_state);
 611         } else if (IS_PINEVIEW(dev)) {
 612                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 613                         limit = &intel_limits_pineview_lvds;
 614                 else
 615                         limit = &intel_limits_pineview_sdvo;
 616         } else if (IS_CHERRYVIEW(dev)) {
 617                 limit = &intel_limits_chv;
 618         } else if (IS_VALLEYVIEW(dev)) {
 619                 limit = &intel_limits_vlv;
 620         } else if (!IS_GEN2(dev)) {
 621                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 622                         limit = &intel_limits_i9xx_lvds;
 623                 else
 624                         limit = &intel_limits_i9xx_sdvo;
 625         } else {
 626                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 627                         limit = &intel_limits_i8xx_lvds;
 628                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 629                         limit = &intel_limits_i8xx_dvo;
 630                 else
 631                         limit = &intel_limits_i8xx_dac;
 632         }
 633         return limit;
 634 }
 635
 636 /*
 637  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 638  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 639  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 640  * The helpers' return value is the rate of the clock that is fed to the
 641  * display engine's pipe which can be the above fast dot clock rate or a
 642  * divided-down version of it.
 643  */
 644 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 645 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 646 {
 647         clock->m = clock->m2 + 2;
 648         clock->p = clock->p1 * clock->p2;
 649         if (WARN_ON(clock->n == 0 || clock->p == 0))
 650                 return 0;
 651         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 652         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 653
 654         return clock->dot;
 655 }
 656
 657 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 658 {
 659         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 660 }
 661
 662 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 663 {
 664         clock->m = i9xx_dpll_compute_m(clock);
 665         clock->p = clock->p1 * clock->p2;
 666         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 667                 return 0;
 668         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 669         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 670
 671         return clock->dot;
 672 }
 673
 674 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 675 {
 676         clock->m = clock->m1 * clock->m2;
 677         clock->p = clock->p1 * clock->p2;
 678         if (WARN_ON(clock->n == 0 || clock->p == 0))
 679                 return 0;
 680         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 681         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 682
 683         return clock->dot / 5;
 684 }
 685
 686 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 687 {
 688         clock->m = clock->m1 * clock->m2;
 689         clock->p = clock->p1 * clock->p2;
 690         if (WARN_ON(clock->n == 0 || clock->p == 0))
 691                 return 0;
 692         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 693                         clock->n << 22);
 694         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 695
 696         return clock->dot / 5;
 697 }
 698
 699 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 700 /**
 701  * Returns whether the given set of divisors are valid for a given refclk with
 702  * the given connectors.
 703  */
 704
 705 static bool intel_PLL_is_valid(struct drm_device *dev,
 706                                const intel_limit_t *limit,
 707                                const intel_clock_t *clock)
 708 {
 709         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 710                 INTELPllInvalid("n out of range\n");
 711         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 712                 INTELPllInvalid("p1 out of range\n");
 713         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 714                 INTELPllInvalid("m2 out of range\n");
 715         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 716                 INTELPllInvalid("m1 out of range\n");
 717
 718         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 719             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 720                 if (clock->m1 <= clock->m2)
 721                         INTELPllInvalid("m1 <= m2\n");
 722
 723         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 724                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 725                         INTELPllInvalid("p out of range\n");
 726                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 727                         INTELPllInvalid("m out of range\n");
 728         }
 729
 730         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 731                 INTELPllInvalid("vco out of range\n");
 732         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 733          * connector, etc., rather than just a single range.
 734          */
 735         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 736                 INTELPllInvalid("dot out of range\n");
 737
 738         return true;
 739 }
 740
 741 static int
 742 i9xx_select_p2_div(const intel_limit_t *limit,
 743                    const struct intel_crtc_state *crtc_state,
 744                    int target)
 745 {
 746         struct drm_device *dev = crtc_state->base.crtc->dev;
 747
 748         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 749                 /*
 750                  * For LVDS just rely on its current settings for dual-channel.
 751                  * We haven't figured out how to reliably set up different
 752                  * single/dual channel state, if we even can.
 753                  */
 754                 if (intel_is_dual_link_lvds(dev))
 755                         return limit->p2.p2_fast;
 756                 else
 757                         return limit->p2.p2_slow;
 758         } else {
 759                 if (target < limit->p2.dot_limit)
 760                         return limit->p2.p2_slow;
 761                 else
 762                         return limit->p2.p2_fast;
 763         }
 764 }
 765
 766 static bool
 767 i9xx_find_best_dpll(const intel_limit_t *limit,
 768                     struct intel_crtc_state *crtc_state,
 769                     int target, int refclk, intel_clock_t *match_clock,
 770                     intel_clock_t *best_clock)
 771 {
 772         struct drm_device *dev = crtc_state->base.crtc->dev;
 773         intel_clock_t clock;
 774         int err = target;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 779
 780         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 781              clock.m1++) {
 782                 for (clock.m2 = limit->m2.min;
 783                      clock.m2 <= limit->m2.max; clock.m2++) {
 784                         if (clock.m2 >= clock.m1)
 785                                 break;
 786                         for (clock.n = limit->n.min;
 787                              clock.n <= limit->n.max; clock.n++) {
 788                                 for (clock.p1 = limit->p1.min;
 789                                         clock.p1 <= limit->p1.max; clock.p1++) {
 790                                         int this_err;
 791
 792                                         i9xx_calc_dpll_params(refclk, &clock);
 793                                         if (!intel_PLL_is_valid(dev, limit,
 794                                                                 &clock))
 795                                                 continue;
 796                                         if (match_clock &&
 797                                             clock.p != match_clock->p)
 798                                                 continue;
 799
 800                                         this_err = abs(clock.dot - target);
 801                                         if (this_err < err) {
 802                                                 *best_clock = clock;
 803                                                 err = this_err;
 804                                         }
 805                                 }
 806                         }
 807                 }
 808         }
 809
 810         return (err != target);
 811 }
 812
 813 static bool
 814 pnv_find_best_dpll(const intel_limit_t *limit,
 815                    struct intel_crtc_state *crtc_state,
 816                    int target, int refclk, intel_clock_t *match_clock,
 817                    intel_clock_t *best_clock)
 818 {
 819         struct drm_device *dev = crtc_state->base.crtc->dev;
 820         intel_clock_t clock;
 821         int err = target;
 822
 823         memset(best_clock, 0, sizeof(*best_clock));
 824
 825         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 826
 827         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 828              clock.m1++) {
 829                 for (clock.m2 = limit->m2.min;
 830                      clock.m2 <= limit->m2.max; clock.m2++) {
 831                         for (clock.n = limit->n.min;
 832                              clock.n <= limit->n.max; clock.n++) {
 833                                 for (clock.p1 = limit->p1.min;
 834                                         clock.p1 <= limit->p1.max; clock.p1++) {
 835                                         int this_err;
 836
 837                                         pnv_calc_dpll_params(refclk, &clock);
 838                                         if (!intel_PLL_is_valid(dev, limit,
 839                                                                 &clock))
 840                                                 continue;
 841                                         if (match_clock &&
 842                                             clock.p != match_clock->p)
 843                                                 continue;
 844
 845                                         this_err = abs(clock.dot - target);
 846                                         if (this_err < err) {
 847                                                 *best_clock = clock;
 848                                                 err = this_err;
 849                                         }
 850                                 }
 851                         }
 852                 }
 853         }
 854
 855         return (err != target);
 856 }
 857
 858 static bool
 859 g4x_find_best_dpll(const intel_limit_t *limit,
 860                    struct intel_crtc_state *crtc_state,
 861                    int target, int refclk, intel_clock_t *match_clock,
 862                    intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc_state->base.crtc->dev;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found = false;
 868         /* approximately equals target * 0.00585 */
 869         int err_most = (target >> 8) + (target >> 9);
 870
 871         memset(best_clock, 0, sizeof(*best_clock));
 872
 873         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 874
 875         max_n = limit->n.max;
 876         /* based on hardware requirement, prefer smaller n to precision */
 877         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 878                 /* based on hardware requirement, prefere larger m1,m2 */
 879                 for (clock.m1 = limit->m1.max;
 880                      clock.m1 >= limit->m1.min; clock.m1--) {
 881                         for (clock.m2 = limit->m2.max;
 882                              clock.m2 >= limit->m2.min; clock.m2--) {
 883                                 for (clock.p1 = limit->p1.max;
 884                                      clock.p1 >= limit->p1.min; clock.p1--) {
 885                                         int this_err;
 886
 887                                         i9xx_calc_dpll_params(refclk, &clock);
 888                                         if (!intel_PLL_is_valid(dev, limit,
 889                                                                 &clock))
 890                                                 continue;
 891
 892                                         this_err = abs(clock.dot - target);
 893                                         if (this_err < err_most) {
 894                                                 *best_clock = clock;
 895                                                 err_most = this_err;
 896                                                 max_n = clock.n;
 897                                                 found = true;
 898                                         }
 899                                 }
 900                         }
 901                 }
 902         }
 903         return found;
 904 }
 905
 906 /*
 907  * Check if the calculated PLL configuration is more optimal compared to the
 908  * best configuration and error found so far. Return the calculated error.
 909  */
 910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 911                                const intel_clock_t *calculated_clock,
 912                                const intel_clock_t *best_clock,
 913                                unsigned int best_error_ppm,
 914                                unsigned int *error_ppm)
 915 {
 916         /*
 917          * For CHV ignore the error and consider only the P value.
 918          * Prefer a bigger P value based on HW requirements.
 919          */
 920         if (IS_CHERRYVIEW(dev)) {
 921                 *error_ppm = 0;
 922
 923                 return calculated_clock->p > best_clock->p;
 924         }
 925
 926         if (WARN_ON_ONCE(!target_freq))
 927                 return false;
 928
 929         *error_ppm = div_u64(1000000ULL *
 930                                 abs(target_freq - calculated_clock->dot),
 931                              target_freq);
 932         /*
 933          * Prefer a better P value over a better (smaller) error if the error
 934          * is small. Ensure this preference for future configurations too by
 935          * setting the error to 0.
 936          */
 937         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 938                 *error_ppm = 0;
 939
 940                 return true;
 941         }
 942
 943         return *error_ppm + 10 < best_error_ppm;
 944 }
 945
 946 static bool
 947 vlv_find_best_dpll(const intel_limit_t *limit,
 948                    struct intel_crtc_state *crtc_state,
 949                    int target, int refclk, intel_clock_t *match_clock,
 950                    intel_clock_t *best_clock)
 951 {
 952         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 953         struct drm_device *dev = crtc->base.dev;
 954         intel_clock_t clock;
 955         unsigned int bestppm = 1000000;
 956         /* min update 19.2 MHz */
 957         int max_n = min(limit->n.max, refclk / 19200);
 958         bool found = false;
 959
 960         target *= 5; /* fast clock */
 961
 962         memset(best_clock, 0, sizeof(*best_clock));
 963
 964         /* based on hardware requirement, prefer smaller n to precision */
 965         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 966                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 967                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 968                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 969                                 clock.p = clock.p1 * clock.p2;
 970                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 971                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 972                                         unsigned int ppm;
 973
 974                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 975                                                                      refclk * clock.m1);
 976
 977                                         vlv_calc_dpll_params(refclk, &clock);
 978
 979                                         if (!intel_PLL_is_valid(dev, limit,
 980                                                                 &clock))
 981                                                 continue;
 982
 983                                         if (!vlv_PLL_is_optimal(dev, target,
 984                                                                 &clock,
 985                                                                 best_clock,
 986                                                                 bestppm, &ppm))
 987                                                 continue;
 988
 989                                         *best_clock = clock;
 990                                         bestppm = ppm;
 991                                         found = true;
 992                                 }
 993                         }
 994                 }
 995         }
 996
 997         return found;
 998 }
 999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002                    struct intel_crtc_state *crtc_state,
1003                    int target, int refclk, intel_clock_t *match_clock,
1004                    intel_clock_t *best_clock)
1005 {
1006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007         struct drm_device *dev = crtc->base.dev;
1008         unsigned int best_error_ppm;
1009         intel_clock_t clock;
1010         uint64_t m2;
1011         int found = false;
1012
1013         memset(best_clock, 0, sizeof(*best_clock));
1014         best_error_ppm = 1000000;
1015
1016         /*
1017          * Based on hardware doc, the n always set to 1, and m1 always
1018          * set to 2.  If requires to support 200Mhz refclk, we need to
1019          * revisit this because n may not 1 anymore.
1020          */
1021         clock.n = 1, clock.m1 = 2;
1022         target *= 5;    /* fast clock */
1023
1024         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025                 for (clock.p2 = limit->p2.p2_fast;
1026                                 clock.p2 >= limit->p2.p2_slow;
1027                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028                         unsigned int error_ppm;
1029
1030                         clock.p = clock.p1 * clock.p2;
1031
1032                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033                                         clock.n) << 22, refclk * clock.m1);
1034
1035                         if (m2 > INT_MAX/clock.m1)
1036                                 continue;
1037
1038                         clock.m2 = m2;
1039
1040                         chv_calc_dpll_params(refclk, &clock);
1041
1042                         if (!intel_PLL_is_valid(dev, limit, &clock))
1043                                 continue;
1044
1045                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046                                                 best_error_ppm, &error_ppm))
1047                                 continue;
1048
1049                         *best_clock = clock;
1050                         best_error_ppm = error_ppm;
1051                         found = true;
1052                 }
1053         }
1054
1055         return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059                         intel_clock_t *best_clock)
1060 {
1061         int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064                                   target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071         /* Be paranoid as we can arrive here with only partial
1072          * state retrieved from the hardware during setup.
1073          *
1074          * We can ditch the adjusted_mode.crtc_clock check as soon
1075          * as Haswell has gained clock readout/fastboot support.
1076          *
1077          * We can ditch the crtc->primary->fb check as soon as we can
1078          * properly reconstruct framebuffers.
1079          *
1080          * FIXME: The intel_crtc->active here should be switched to
1081          * crtc->state->active once we have proper CRTC states wired up
1082          * for atomic.
1083          */
1084         return intel_crtc->active && crtc->primary->state->fb &&
1085                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089                                              enum pipe pipe)
1090 {
1091         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094         return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099         struct drm_i915_private *dev_priv = dev->dev_private;
1100         i915_reg_t reg = PIPEDSL(pipe);
1101         u32 line1, line2;
1102         u32 line_mask;
1103
1104         if (IS_GEN2(dev))
1105                 line_mask = DSL_LINEMASK_GEN2;
1106         else
1107                 line_mask = DSL_LINEMASK_GEN3;
1108
1109         line1 = I915_READ(reg) & line_mask;
1110         msleep(5);
1111         line2 = I915_READ(reg) & line_mask;
1112
1113         return line1 == line2;
1114 }
1115
1116 /*
1117  * intel_wait_for_pipe_off - wait for pipe to turn off
1118  * @crtc: crtc whose pipe to wait for
1119  *
1120  * After disabling a pipe, we can't wait for vblank in the usual way,
1121  * spinning on the vblank interrupt status bit, since we won't actually
1122  * see an interrupt when the pipe is disabled.
1123  *
1124  * On Gen4 and above:
1125  *   wait for the pipe register state bit to turn off
1126  *
1127  * Otherwise:
1128  *   wait for the display line value to settle (it usually
1129  *   ends up stopping at the start of the next frame).
1130  *
1131  */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134         struct drm_device *dev = crtc->base.dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137         enum pipe pipe = crtc->pipe;
1138
1139         if (INTEL_INFO(dev)->gen >= 4) {
1140                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142                 /* Wait for the Pipe State to go off */
1143                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144                              100))
1145                         WARN(1, "pipe_off wait timed out\n");
1146         } else {
1147                 /* Wait for the display line to settle */
1148                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149                         WARN(1, "pipe_off wait timed out\n");
1150         }
1151 }
1152
1153 /* Only for pre-ILK configs */
1154 void assert_pll(struct drm_i915_private *dev_priv,
1155                 enum pipe pipe, bool state)
1156 {
1157         u32 val;
1158         bool cur_state;
1159
1160         val = I915_READ(DPLL(pipe));
1161         cur_state = !!(val & DPLL_VCO_ENABLE);
1162         I915_STATE_WARN(cur_state != state,
1163              "PLL state assertion failure (expected %s, current %s)\n",
1164                         onoff(state), onoff(cur_state));
1165 }
1166
1167 /* XXX: the dsi pll is shared between MIPI DSI ports */
1168 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1169 {
1170         u32 val;
1171         bool cur_state;
1172
1173         mutex_lock(&dev_priv->sb_lock);
1174         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1175         mutex_unlock(&dev_priv->sb_lock);
1176
1177         cur_state = val & DSI_PLL_VCO_EN;
1178         I915_STATE_WARN(cur_state != state,
1179              "DSI PLL state assertion failure (expected %s, current %s)\n",
1180                         onoff(state), onoff(cur_state));
1181 }
1182 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1183 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1184
1185 struct intel_shared_dpll *
1186 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1187 {
1188         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1189
1190         if (crtc->config->shared_dpll < 0)
1191                 return NULL;
1192
1193         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1194 }
1195
1196 /* For ILK+ */
1197 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1198                         struct intel_shared_dpll *pll,
1199                         bool state)
1200 {
1201         bool cur_state;
1202         struct intel_dpll_hw_state hw_state;
1203
1204         if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
1205                 return;
1206
1207         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1208         I915_STATE_WARN(cur_state != state,
1209              "%s assertion failure (expected %s, current %s)\n",
1210                         pll->name, onoff(state), onoff(cur_state));
1211 }
1212
1213 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1214                           enum pipe pipe, bool state)
1215 {
1216         bool cur_state;
1217         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1218                                                                       pipe);
1219
1220         if (HAS_DDI(dev_priv->dev)) {
1221                 /* DDI does not have a specific FDI_TX register */
1222                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1223                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1224         } else {
1225                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1226                 cur_state = !!(val & FDI_TX_ENABLE);
1227         }
1228         I915_STATE_WARN(cur_state != state,
1229              "FDI TX state assertion failure (expected %s, current %s)\n",
1230                         onoff(state), onoff(cur_state));
1231 }
1232 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1233 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1234
1235 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1236                           enum pipe pipe, bool state)
1237 {
1238         u32 val;
1239         bool cur_state;
1240
1241         val = I915_READ(FDI_RX_CTL(pipe));
1242         cur_state = !!(val & FDI_RX_ENABLE);
1243         I915_STATE_WARN(cur_state != state,
1244              "FDI RX state assertion failure (expected %s, current %s)\n",
1245                         onoff(state), onoff(cur_state));
1246 }
1247 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1248 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1249
1250 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1251                                       enum pipe pipe)
1252 {
1253         u32 val;
1254
1255         /* ILK FDI PLL is always enabled */
1256         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1257                 return;
1258
1259         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1260         if (HAS_DDI(dev_priv->dev))
1261                 return;
1262
1263         val = I915_READ(FDI_TX_CTL(pipe));
1264         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1265 }
1266
1267 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1268                        enum pipe pipe, bool state)
1269 {
1270         u32 val;
1271         bool cur_state;
1272
1273         val = I915_READ(FDI_RX_CTL(pipe));
1274         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1275         I915_STATE_WARN(cur_state != state,
1276              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1277                         onoff(state), onoff(cur_state));
1278 }
1279
1280 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1281                            enum pipe pipe)
1282 {
1283         struct drm_device *dev = dev_priv->dev;
1284         i915_reg_t pp_reg;
1285         u32 val;
1286         enum pipe panel_pipe = PIPE_A;
1287         bool locked = true;
1288
1289         if (WARN_ON(HAS_DDI(dev)))
1290                 return;
1291
1292         if (HAS_PCH_SPLIT(dev)) {
1293                 u32 port_sel;
1294
1295                 pp_reg = PCH_PP_CONTROL;
1296                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1297
1298                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1299                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1300                         panel_pipe = PIPE_B;
1301                 /* XXX: else fix for eDP */
1302         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1303                 /* presumably write lock depends on pipe, not port select */
1304                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1305                 panel_pipe = pipe;
1306         } else {
1307                 pp_reg = PP_CONTROL;
1308                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1309                         panel_pipe = PIPE_B;
1310         }
1311
1312         val = I915_READ(pp_reg);
1313         if (!(val & PANEL_POWER_ON) ||
1314             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1315                 locked = false;
1316
1317         I915_STATE_WARN(panel_pipe == pipe && locked,
1318              "panel assertion failure, pipe %c regs locked\n",
1319              pipe_name(pipe));
1320 }
1321
1322 static void assert_cursor(struct drm_i915_private *dev_priv,
1323                           enum pipe pipe, bool state)
1324 {
1325         struct drm_device *dev = dev_priv->dev;
1326         bool cur_state;
1327
1328         if (IS_845G(dev) || IS_I865G(dev))
1329                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1330         else
1331                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1332
1333         I915_STATE_WARN(cur_state != state,
1334              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1335                         pipe_name(pipe), onoff(state), onoff(cur_state));
1336 }
1337 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1338 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1339
1340 void assert_pipe(struct drm_i915_private *dev_priv,
1341                  enum pipe pipe, bool state)
1342 {
1343         bool cur_state;
1344         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1345                                                                       pipe);
1346
1347         /* if we need the pipe quirk it must be always on */
1348         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1349             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1350                 state = true;
1351
1352         if (!intel_display_power_is_enabled(dev_priv,
1353                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1354                 cur_state = false;
1355         } else {
1356                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1357                 cur_state = !!(val & PIPECONF_ENABLE);
1358         }
1359
1360         I915_STATE_WARN(cur_state != state,
1361              "pipe %c assertion failure (expected %s, current %s)\n",
1362                         pipe_name(pipe), onoff(state), onoff(cur_state));
1363 }
1364
1365 static void assert_plane(struct drm_i915_private *dev_priv,
1366                          enum plane plane, bool state)
1367 {
1368         u32 val;
1369         bool cur_state;
1370
1371         val = I915_READ(DSPCNTR(plane));
1372         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1373         I915_STATE_WARN(cur_state != state,
1374              "plane %c assertion failure (expected %s, current %s)\n",
1375                         plane_name(plane), onoff(state), onoff(cur_state));
1376 }
1377
1378 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1379 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1380
1381 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1382                                    enum pipe pipe)
1383 {
1384         struct drm_device *dev = dev_priv->dev;
1385         int i;
1386
1387         /* Primary planes are fixed to pipes on gen4+ */
1388         if (INTEL_INFO(dev)->gen >= 4) {
1389                 u32 val = I915_READ(DSPCNTR(pipe));
1390                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1391                      "plane %c assertion failure, should be disabled but not\n",
1392                      plane_name(pipe));
1393                 return;
1394         }
1395
1396         /* Need to check both planes against the pipe */
1397         for_each_pipe(dev_priv, i) {
1398                 u32 val = I915_READ(DSPCNTR(i));
1399                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1400                         DISPPLANE_SEL_PIPE_SHIFT;
1401                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1402                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1403                      plane_name(i), pipe_name(pipe));
1404         }
1405 }
1406
1407 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1408                                     enum pipe pipe)
1409 {
1410         struct drm_device *dev = dev_priv->dev;
1411         int sprite;
1412
1413         if (INTEL_INFO(dev)->gen >= 9) {
1414                 for_each_sprite(dev_priv, pipe, sprite) {
1415                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1416                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1417                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1418                              sprite, pipe_name(pipe));
1419                 }
1420         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1421                 for_each_sprite(dev_priv, pipe, sprite) {
1422                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1423                         I915_STATE_WARN(val & SP_ENABLE,
1424                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425                              sprite_name(pipe, sprite), pipe_name(pipe));
1426                 }
1427         } else if (INTEL_INFO(dev)->gen >= 7) {
1428                 u32 val = I915_READ(SPRCTL(pipe));
1429                 I915_STATE_WARN(val & SPRITE_ENABLE,
1430                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431                      plane_name(pipe), pipe_name(pipe));
1432         } else if (INTEL_INFO(dev)->gen >= 5) {
1433                 u32 val = I915_READ(DVSCNTR(pipe));
1434                 I915_STATE_WARN(val & DVS_ENABLE,
1435                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1436                      plane_name(pipe), pipe_name(pipe));
1437         }
1438 }
1439
1440 static void assert_vblank_disabled(struct drm_crtc *crtc)
1441 {
1442         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1443                 drm_crtc_vblank_put(crtc);
1444 }
1445
1446 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1447 {
1448         u32 val;
1449         bool enabled;
1450
1451         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1452
1453         val = I915_READ(PCH_DREF_CONTROL);
1454         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1455                             DREF_SUPERSPREAD_SOURCE_MASK));
1456         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1457 }
1458
1459 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1460                                            enum pipe pipe)
1461 {
1462         u32 val;
1463         bool enabled;
1464
1465         val = I915_READ(PCH_TRANSCONF(pipe));
1466         enabled = !!(val & TRANS_ENABLE);
1467         I915_STATE_WARN(enabled,
1468              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1469              pipe_name(pipe));
1470 }
1471
1472 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1473                             enum pipe pipe, u32 port_sel, u32 val)
1474 {
1475         if ((val & DP_PORT_EN) == 0)
1476                 return false;
1477
1478         if (HAS_PCH_CPT(dev_priv->dev)) {
1479                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1480                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1481                         return false;
1482         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1483                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1484                         return false;
1485         } else {
1486                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1487                         return false;
1488         }
1489         return true;
1490 }
1491
1492 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1493                               enum pipe pipe, u32 val)
1494 {
1495         if ((val & SDVO_ENABLE) == 0)
1496                 return false;
1497
1498         if (HAS_PCH_CPT(dev_priv->dev)) {
1499                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1500                         return false;
1501         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1502                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1503                         return false;
1504         } else {
1505                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1506                         return false;
1507         }
1508         return true;
1509 }
1510
1511 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1512                               enum pipe pipe, u32 val)
1513 {
1514         if ((val & LVDS_PORT_EN) == 0)
1515                 return false;
1516
1517         if (HAS_PCH_CPT(dev_priv->dev)) {
1518                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1519                         return false;
1520         } else {
1521                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1522                         return false;
1523         }
1524         return true;
1525 }
1526
1527 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1528                               enum pipe pipe, u32 val)
1529 {
1530         if ((val & ADPA_DAC_ENABLE) == 0)
1531                 return false;
1532         if (HAS_PCH_CPT(dev_priv->dev)) {
1533                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1534                         return false;
1535         } else {
1536                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1537                         return false;
1538         }
1539         return true;
1540 }
1541
1542 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1543                                    enum pipe pipe, i915_reg_t reg,
1544                                    u32 port_sel)
1545 {
1546         u32 val = I915_READ(reg);
1547         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1548              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1549              i915_mmio_reg_offset(reg), pipe_name(pipe));
1550
1551         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1552              && (val & DP_PIPEB_SELECT),
1553              "IBX PCH dp port still using transcoder B\n");
1554 }
1555
1556 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1557                                      enum pipe pipe, i915_reg_t reg)
1558 {
1559         u32 val = I915_READ(reg);
1560         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1561              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1562              i915_mmio_reg_offset(reg), pipe_name(pipe));
1563
1564         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1565              && (val & SDVO_PIPE_B_SELECT),
1566              "IBX PCH hdmi port still using transcoder B\n");
1567 }
1568
1569 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1570                                       enum pipe pipe)
1571 {
1572         u32 val;
1573
1574         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1575         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1576         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1577
1578         val = I915_READ(PCH_ADPA);
1579         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1580              "PCH VGA enabled on transcoder %c, should be disabled\n",
1581              pipe_name(pipe));
1582
1583         val = I915_READ(PCH_LVDS);
1584         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1585              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1586              pipe_name(pipe));
1587
1588         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1591 }
1592
1593 static void vlv_enable_pll(struct intel_crtc *crtc,
1594                            const struct intel_crtc_state *pipe_config)
1595 {
1596         struct drm_device *dev = crtc->base.dev;
1597         struct drm_i915_private *dev_priv = dev->dev_private;
1598         i915_reg_t reg = DPLL(crtc->pipe);
1599         u32 dpll = pipe_config->dpll_hw_state.dpll;
1600
1601         assert_pipe_disabled(dev_priv, crtc->pipe);
1602
1603         /* PLL is protected by panel, make sure we can write it */
1604         if (IS_MOBILE(dev_priv->dev))
1605                 assert_panel_unlocked(dev_priv, crtc->pipe);
1606
1607         I915_WRITE(reg, dpll);
1608         POSTING_READ(reg);
1609         udelay(150);
1610
1611         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1612                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1613
1614         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1615         POSTING_READ(DPLL_MD(crtc->pipe));
1616
1617         /* We do this three times for luck */
1618         I915_WRITE(reg, dpll);
1619         POSTING_READ(reg);
1620         udelay(150); /* wait for warmup */
1621         I915_WRITE(reg, dpll);
1622         POSTING_READ(reg);
1623         udelay(150); /* wait for warmup */
1624         I915_WRITE(reg, dpll);
1625         POSTING_READ(reg);
1626         udelay(150); /* wait for warmup */
1627 }
1628
1629 static void chv_enable_pll(struct intel_crtc *crtc,
1630                            const struct intel_crtc_state *pipe_config)
1631 {
1632         struct drm_device *dev = crtc->base.dev;
1633         struct drm_i915_private *dev_priv = dev->dev_private;
1634         int pipe = crtc->pipe;
1635         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1636         u32 tmp;
1637
1638         assert_pipe_disabled(dev_priv, crtc->pipe);
1639
1640         mutex_lock(&dev_priv->sb_lock);
1641
1642         /* Enable back the 10bit clock to display controller */
1643         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1644         tmp |= DPIO_DCLKP_EN;
1645         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1646
1647         mutex_unlock(&dev_priv->sb_lock);
1648
1649         /*
1650          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1651          */
1652         udelay(1);
1653
1654         /* Enable PLL */
1655         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1656
1657         /* Check PLL is locked */
1658         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1659                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1660
1661         /* not sure when this should be written */
1662         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1663         POSTING_READ(DPLL_MD(pipe));
1664 }
1665
1666 static int intel_num_dvo_pipes(struct drm_device *dev)
1667 {
1668         struct intel_crtc *crtc;
1669         int count = 0;
1670
1671         for_each_intel_crtc(dev, crtc)
1672                 count += crtc->base.state->active &&
1673                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1674
1675         return count;
1676 }
1677
1678 static void i9xx_enable_pll(struct intel_crtc *crtc)
1679 {
1680         struct drm_device *dev = crtc->base.dev;
1681         struct drm_i915_private *dev_priv = dev->dev_private;
1682         i915_reg_t reg = DPLL(crtc->pipe);
1683         u32 dpll = crtc->config->dpll_hw_state.dpll;
1684
1685         assert_pipe_disabled(dev_priv, crtc->pipe);
1686
1687         /* No really, not for ILK+ */
1688         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1689
1690         /* PLL is protected by panel, make sure we can write it */
1691         if (IS_MOBILE(dev) && !IS_I830(dev))
1692                 assert_panel_unlocked(dev_priv, crtc->pipe);
1693
1694         /* Enable DVO 2x clock on both PLLs if necessary */
1695         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1696                 /*
1697                  * It appears to be important that we don't enable this
1698                  * for the current pipe before otherwise configuring the
1699                  * PLL. No idea how this should be handled if multiple
1700                  * DVO outputs are enabled simultaneosly.
1701                  */
1702                 dpll |= DPLL_DVO_2X_MODE;
1703                 I915_WRITE(DPLL(!crtc->pipe),
1704                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1705         }
1706
1707         /*
1708          * Apparently we need to have VGA mode enabled prior to changing
1709          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1710          * dividers, even though the register value does change.
1711          */
1712         I915_WRITE(reg, 0);
1713
1714         I915_WRITE(reg, dpll);
1715
1716         /* Wait for the clocks to stabilize. */
1717         POSTING_READ(reg);
1718         udelay(150);
1719
1720         if (INTEL_INFO(dev)->gen >= 4) {
1721                 I915_WRITE(DPLL_MD(crtc->pipe),
1722                            crtc->config->dpll_hw_state.dpll_md);
1723         } else {
1724                 /* The pixel multiplier can only be updated once the
1725                  * DPLL is enabled and the clocks are stable.
1726                  *
1727                  * So write it again.
1728                  */
1729                 I915_WRITE(reg, dpll);
1730         }
1731
1732         /* We do this three times for luck */
1733         I915_WRITE(reg, dpll);
1734         POSTING_READ(reg);
1735         udelay(150); /* wait for warmup */
1736         I915_WRITE(reg, dpll);
1737         POSTING_READ(reg);
1738         udelay(150); /* wait for warmup */
1739         I915_WRITE(reg, dpll);
1740         POSTING_READ(reg);
1741         udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745  * i9xx_disable_pll - disable a PLL
1746  * @dev_priv: i915 private structure
1747  * @pipe: pipe PLL to disable
1748  *
1749  * Disable the PLL for @pipe, making sure the pipe is off first.
1750  *
1751  * Note!  This is for pre-ILK only.
1752  */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755         struct drm_device *dev = crtc->base.dev;
1756         struct drm_i915_private *dev_priv = dev->dev_private;
1757         enum pipe pipe = crtc->pipe;
1758
1759         /* Disable DVO 2x clock on both PLLs if necessary */
1760         if (IS_I830(dev) &&
1761             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762             !intel_num_dvo_pipes(dev)) {
1763                 I915_WRITE(DPLL(PIPE_B),
1764                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765                 I915_WRITE(DPLL(PIPE_A),
1766                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767         }
1768
1769         /* Don't disable pipe or pipe PLLs if needed */
1770         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772                 return;
1773
1774         /* Make sure the pipe isn't still relying on us */
1775         assert_pipe_disabled(dev_priv, pipe);
1776
1777         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1778         POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783         u32 val;
1784
1785         /* Make sure the pipe isn't still relying on us */
1786         assert_pipe_disabled(dev_priv, pipe);
1787
1788         /*
1789          * Leave integrated clock source and reference clock enabled for pipe B.
1790          * The latter is needed for VGA hotplug / manual detection.
1791          */
1792         val = DPLL_VGA_MODE_DIS;
1793         if (pipe == PIPE_B)
1794                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1795         I915_WRITE(DPLL(pipe), val);
1796         POSTING_READ(DPLL(pipe));
1797
1798 }
1799
1800 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801 {
1802         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1803         u32 val;
1804
1805         /* Make sure the pipe isn't still relying on us */
1806         assert_pipe_disabled(dev_priv, pipe);
1807
1808         /* Set PLL en = 0 */
1809         val = DPLL_SSC_REF_CLK_CHV |
1810                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1811         if (pipe != PIPE_A)
1812                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813         I915_WRITE(DPLL(pipe), val);
1814         POSTING_READ(DPLL(pipe));
1815
1816         mutex_lock(&dev_priv->sb_lock);
1817
1818         /* Disable 10bit clock to display controller */
1819         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820         val &= ~DPIO_DCLKP_EN;
1821         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
1823         mutex_unlock(&dev_priv->sb_lock);
1824 }
1825
1826 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1827                          struct intel_digital_port *dport,
1828                          unsigned int expected_mask)
1829 {
1830         u32 port_mask;
1831         i915_reg_t dpll_reg;
1832
1833         switch (dport->port) {
1834         case PORT_B:
1835                 port_mask = DPLL_PORTB_READY_MASK;
1836                 dpll_reg = DPLL(0);
1837                 break;
1838         case PORT_C:
1839                 port_mask = DPLL_PORTC_READY_MASK;
1840                 dpll_reg = DPLL(0);
1841                 expected_mask <<= 4;
1842                 break;
1843         case PORT_D:
1844                 port_mask = DPLL_PORTD_READY_MASK;
1845                 dpll_reg = DPIO_PHY_STATUS;
1846                 break;
1847         default:
1848                 BUG();
1849         }
1850
1851         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1854 }
1855
1856 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857 {
1858         struct drm_device *dev = crtc->base.dev;
1859         struct drm_i915_private *dev_priv = dev->dev_private;
1860         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
1862         if (WARN_ON(pll == NULL))
1863                 return;
1864
1865         WARN_ON(!pll->config.crtc_mask);
1866         if (pll->active == 0) {
1867                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868                 WARN_ON(pll->on);
1869                 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871                 pll->mode_set(dev_priv, pll);
1872         }
1873 }
1874
1875 /**
1876  * intel_enable_shared_dpll - enable PCH PLL
1877  * @dev_priv: i915 private structure
1878  * @pipe: pipe PLL to enable
1879  *
1880  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881  * drives the transcoder clock.
1882  */
1883 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1884 {
1885         struct drm_device *dev = crtc->base.dev;
1886         struct drm_i915_private *dev_priv = dev->dev_private;
1887         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
1889         if (WARN_ON(pll == NULL))
1890                 return;
1891
1892         if (WARN_ON(pll->config.crtc_mask == 0))
1893                 return;
1894
1895         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1896                       pll->name, pll->active, pll->on,
1897                       crtc->base.base.id);
1898
1899         if (pll->active++) {
1900                 WARN_ON(!pll->on);
1901                 assert_shared_dpll_enabled(dev_priv, pll);
1902                 return;
1903         }
1904         WARN_ON(pll->on);
1905
1906         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
1908         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1909         pll->enable(dev_priv, pll);
1910         pll->on = true;
1911 }
1912
1913 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1914 {
1915         struct drm_device *dev = crtc->base.dev;
1916         struct drm_i915_private *dev_priv = dev->dev_private;
1917         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918
1919         /* PCH only available on ILK+ */
1920         if (INTEL_INFO(dev)->gen < 5)
1921                 return;
1922
1923         if (pll == NULL)
1924                 return;
1925
1926         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1927                 return;
1928
1929         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930                       pll->name, pll->active, pll->on,
1931                       crtc->base.base.id);
1932
1933         if (WARN_ON(pll->active == 0)) {
1934                 assert_shared_dpll_disabled(dev_priv, pll);
1935                 return;
1936         }
1937
1938         assert_shared_dpll_enabled(dev_priv, pll);
1939         WARN_ON(!pll->on);
1940         if (--pll->active)
1941                 return;
1942
1943         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1944         pll->disable(dev_priv, pll);
1945         pll->on = false;
1946
1947         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1948 }
1949
1950 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951                                            enum pipe pipe)
1952 {
1953         struct drm_device *dev = dev_priv->dev;
1954         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1956         i915_reg_t reg;
1957         uint32_t val, pipeconf_val;
1958
1959         /* PCH only available on ILK+ */
1960         BUG_ON(!HAS_PCH_SPLIT(dev));
1961
1962         /* Make sure PCH DPLL is enabled */
1963         assert_shared_dpll_enabled(dev_priv,
1964                                    intel_crtc_to_shared_dpll(intel_crtc));
1965
1966         /* FDI must be feeding us bits for PCH ports */
1967         assert_fdi_tx_enabled(dev_priv, pipe);
1968         assert_fdi_rx_enabled(dev_priv, pipe);
1969
1970         if (HAS_PCH_CPT(dev)) {
1971                 /* Workaround: Set the timing override bit before enabling the
1972                  * pch transcoder. */
1973                 reg = TRANS_CHICKEN2(pipe);
1974                 val = I915_READ(reg);
1975                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1976                 I915_WRITE(reg, val);
1977         }
1978
1979         reg = PCH_TRANSCONF(pipe);
1980         val = I915_READ(reg);
1981         pipeconf_val = I915_READ(PIPECONF(pipe));
1982
1983         if (HAS_PCH_IBX(dev_priv->dev)) {
1984                 /*
1985                  * Make the BPC in transcoder be consistent with
1986                  * that in pipeconf reg. For HDMI we must use 8bpc
1987                  * here for both 8bpc and 12bpc.
1988                  */
1989                 val &= ~PIPECONF_BPC_MASK;
1990                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1991                         val |= PIPECONF_8BPC;
1992                 else
1993                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1994         }
1995
1996         val &= ~TRANS_INTERLACE_MASK;
1997         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1998                 if (HAS_PCH_IBX(dev_priv->dev) &&
1999                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2000                         val |= TRANS_LEGACY_INTERLACED_ILK;
2001                 else
2002                         val |= TRANS_INTERLACED;
2003         else
2004                 val |= TRANS_PROGRESSIVE;
2005
2006         I915_WRITE(reg, val | TRANS_ENABLE);
2007         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2008                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2009 }
2010
2011 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2012                                       enum transcoder cpu_transcoder)
2013 {
2014         u32 val, pipeconf_val;
2015
2016         /* PCH only available on ILK+ */
2017         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2018
2019         /* FDI must be feeding us bits for PCH ports */
2020         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2021         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2022
2023         /* Workaround: set timing override bit. */
2024         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2025         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2026         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2027
2028         val = TRANS_ENABLE;
2029         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2030
2031         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2032             PIPECONF_INTERLACED_ILK)
2033                 val |= TRANS_INTERLACED;
2034         else
2035                 val |= TRANS_PROGRESSIVE;
2036
2037         I915_WRITE(LPT_TRANSCONF, val);
2038         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2039                 DRM_ERROR("Failed to enable PCH transcoder\n");
2040 }
2041
2042 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2043                                             enum pipe pipe)
2044 {
2045         struct drm_device *dev = dev_priv->dev;
2046         i915_reg_t reg;
2047         uint32_t val;
2048
2049         /* FDI relies on the transcoder */
2050         assert_fdi_tx_disabled(dev_priv, pipe);
2051         assert_fdi_rx_disabled(dev_priv, pipe);
2052
2053         /* Ports must be off as well */
2054         assert_pch_ports_disabled(dev_priv, pipe);
2055
2056         reg = PCH_TRANSCONF(pipe);
2057         val = I915_READ(reg);
2058         val &= ~TRANS_ENABLE;
2059         I915_WRITE(reg, val);
2060         /* wait for PCH transcoder off, transcoder state */
2061         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2062                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2063
2064         if (HAS_PCH_CPT(dev)) {
2065                 /* Workaround: Clear the timing override chicken bit again. */
2066                 reg = TRANS_CHICKEN2(pipe);
2067                 val = I915_READ(reg);
2068                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2069                 I915_WRITE(reg, val);
2070         }
2071 }
2072
2073 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2074 {
2075         u32 val;
2076
2077         val = I915_READ(LPT_TRANSCONF);
2078         val &= ~TRANS_ENABLE;
2079         I915_WRITE(LPT_TRANSCONF, val);
2080         /* wait for PCH transcoder off, transcoder state */
2081         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2082                 DRM_ERROR("Failed to disable PCH transcoder\n");
2083
2084         /* Workaround: clear timing override bit. */
2085         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2086         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2087         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2088 }
2089
2090 /**
2091  * intel_enable_pipe - enable a pipe, asserting requirements
2092  * @crtc: crtc responsible for the pipe
2093  *
2094  * Enable @crtc's pipe, making sure that various hardware specific requirements
2095  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2096  */
2097 static void intel_enable_pipe(struct intel_crtc *crtc)
2098 {
2099         struct drm_device *dev = crtc->base.dev;
2100         struct drm_i915_private *dev_priv = dev->dev_private;
2101         enum pipe pipe = crtc->pipe;
2102         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2103         enum pipe pch_transcoder;
2104         i915_reg_t reg;
2105         u32 val;
2106
2107         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2108
2109         assert_planes_disabled(dev_priv, pipe);
2110         assert_cursor_disabled(dev_priv, pipe);
2111         assert_sprites_disabled(dev_priv, pipe);
2112
2113         if (HAS_PCH_LPT(dev_priv->dev))
2114                 pch_transcoder = TRANSCODER_A;
2115         else
2116                 pch_transcoder = pipe;
2117
2118         /*
2119          * A pipe without a PLL won't actually be able to drive bits from
2120          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2121          * need the check.
2122          */
2123         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2124                 if (crtc->config->has_dsi_encoder)
2125                         assert_dsi_pll_enabled(dev_priv);
2126                 else
2127                         assert_pll_enabled(dev_priv, pipe);
2128         else {
2129                 if (crtc->config->has_pch_encoder) {
2130                         /* if driving the PCH, we need FDI enabled */
2131                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2132                         assert_fdi_tx_pll_enabled(dev_priv,
2133                                                   (enum pipe) cpu_transcoder);
2134                 }
2135                 /* FIXME: assert CPU port conditions for SNB+ */
2136         }
2137
2138         reg = PIPECONF(cpu_transcoder);
2139         val = I915_READ(reg);
2140         if (val & PIPECONF_ENABLE) {
2141                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2142                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2143                 return;
2144         }
2145
2146         I915_WRITE(reg, val | PIPECONF_ENABLE);
2147         POSTING_READ(reg);
2148
2149         /*
2150          * Until the pipe starts DSL will read as 0, which would cause
2151          * an apparent vblank timestamp jump, which messes up also the
2152          * frame count when it's derived from the timestamps. So let's
2153          * wait for the pipe to start properly before we call
2154          * drm_crtc_vblank_on()
2155          */
2156         if (dev->max_vblank_count == 0 &&
2157             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2158                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2159 }
2160
2161 /**
2162  * intel_disable_pipe - disable a pipe, asserting requirements
2163  * @crtc: crtc whose pipes is to be disabled
2164  *
2165  * Disable the pipe of @crtc, making sure that various hardware
2166  * specific requirements are met, if applicable, e.g. plane
2167  * disabled, panel fitter off, etc.
2168  *
2169  * Will wait until the pipe has shut down before returning.
2170  */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175         enum pipe pipe = crtc->pipe;
2176         i915_reg_t reg;
2177         u32 val;
2178
2179         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2180
2181         /*
2182          * Make sure planes won't keep trying to pump pixels to us,
2183          * or we might hang the display.
2184          */
2185         assert_planes_disabled(dev_priv, pipe);
2186         assert_cursor_disabled(dev_priv, pipe);
2187         assert_sprites_disabled(dev_priv, pipe);
2188
2189         reg = PIPECONF(cpu_transcoder);
2190         val = I915_READ(reg);
2191         if ((val & PIPECONF_ENABLE) == 0)
2192                 return;
2193
2194         /*
2195          * Double wide has implications for planes
2196          * so best keep it disabled when not needed.
2197          */
2198         if (crtc->config->double_wide)
2199                 val &= ~PIPECONF_DOUBLE_WIDE;
2200
2201         /* Don't disable pipe or pipe PLLs if needed */
2202         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2203             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2204                 val &= ~PIPECONF_ENABLE;
2205
2206         I915_WRITE(reg, val);
2207         if ((val & PIPECONF_ENABLE) == 0)
2208                 intel_wait_for_pipe_off(crtc);
2209 }
2210
2211 static bool need_vtd_wa(struct drm_device *dev)
2212 {
2213 #ifdef CONFIG_INTEL_IOMMU
2214         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2215                 return true;
2216 #endif
2217         return false;
2218 }
2219
2220 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2221 {
2222         return IS_GEN2(dev_priv) ? 2048 : 4096;
2223 }
2224
2225 static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv,
2226                                      uint64_t fb_modifier, unsigned int cpp)
2227 {
2228         switch (fb_modifier) {
2229         case DRM_FORMAT_MOD_NONE:
2230                 return cpp;
2231         case I915_FORMAT_MOD_X_TILED:
2232                 if (IS_GEN2(dev_priv))
2233                         return 128;
2234                 else
2235                         return 512;
2236         case I915_FORMAT_MOD_Y_TILED:
2237                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2238                         return 128;
2239                 else
2240                         return 512;
2241         case I915_FORMAT_MOD_Yf_TILED:
2242                 switch (cpp) {
2243                 case 1:
2244                         return 64;
2245                 case 2:
2246                 case 4:
2247                         return 128;
2248                 case 8:
2249                 case 16:
2250                         return 256;
2251                 default:
2252                         MISSING_CASE(cpp);
2253                         return cpp;
2254                 }
2255                 break;
2256         default:
2257                 MISSING_CASE(fb_modifier);
2258                 return cpp;
2259         }
2260 }
2261
2262 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2263                                uint64_t fb_modifier, unsigned int cpp)
2264 {
2265         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2266                 return 1;
2267         else
2268                 return intel_tile_size(dev_priv) /
2269                         intel_tile_width(dev_priv, fb_modifier, cpp);
2270 }
2271
2272 unsigned int
2273 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2274                       uint32_t pixel_format, uint64_t fb_modifier)
2275 {
2276         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2277         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2278
2279         return ALIGN(height, tile_height);
2280 }
2281
2282 static void
2283 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284                         const struct drm_plane_state *plane_state)
2285 {
2286         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2287         struct intel_rotation_info *info = &view->params.rotation_info;
2288         unsigned int tile_size, tile_width, tile_height, cpp;
2289
2290         *view = i915_ggtt_view_normal;
2291
2292         if (!plane_state)
2293                 return;
2294
2295         if (!intel_rotation_90_or_270(plane_state->rotation))
2296                 return;
2297
2298         *view = i915_ggtt_view_rotated;
2299
2300         info->height = fb->height;
2301         info->pixel_format = fb->pixel_format;
2302         info->pitch = fb->pitches[0];
2303         info->uv_offset = fb->offsets[1];
2304         info->fb_modifier = fb->modifier[0];
2305
2306         tile_size = intel_tile_size(dev_priv);
2307
2308         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2309         tile_width = intel_tile_width(dev_priv, cpp, fb->modifier[0]);
2310         tile_height = tile_size / tile_width;
2311
2312         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
2313         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2314         info->size = info->width_pages * info->height_pages * tile_size;
2315
2316         if (info->pixel_format == DRM_FORMAT_NV12) {
2317                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2318                 tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
2319                 tile_height = tile_size / tile_width;
2320
2321                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
2322                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
2323                 info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
2324         }
2325 }
2326
2327 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2328 {
2329         if (INTEL_INFO(dev_priv)->gen >= 9)
2330                 return 256 * 1024;
2331         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2332                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2333                 return 128 * 1024;
2334         else if (INTEL_INFO(dev_priv)->gen >= 4)
2335                 return 4 * 1024;
2336         else
2337                 return 0;
2338 }
2339
2340 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2341                                          uint64_t fb_modifier)
2342 {
2343         switch (fb_modifier) {
2344         case DRM_FORMAT_MOD_NONE:
2345                 return intel_linear_alignment(dev_priv);
2346         case I915_FORMAT_MOD_X_TILED:
2347                 if (INTEL_INFO(dev_priv)->gen >= 9)
2348                         return 256 * 1024;
2349                 return 0;
2350         case I915_FORMAT_MOD_Y_TILED:
2351         case I915_FORMAT_MOD_Yf_TILED:
2352                 return 1 * 1024 * 1024;
2353         default:
2354                 MISSING_CASE(fb_modifier);
2355                 return 0;
2356         }
2357 }
2358
2359 int
2360 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2361                            struct drm_framebuffer *fb,
2362                            const struct drm_plane_state *plane_state)
2363 {
2364         struct drm_device *dev = fb->dev;
2365         struct drm_i915_private *dev_priv = dev->dev_private;
2366         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2367         struct i915_ggtt_view view;
2368         u32 alignment;
2369         int ret;
2370
2371         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2372
2373         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2374
2375         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2376
2377         /* Note that the w/a also requires 64 PTE of padding following the
2378          * bo. We currently fill all unused PTE with the shadow page and so
2379          * we should always have valid PTE following the scanout preventing
2380          * the VT-d warning.
2381          */
2382         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2383                 alignment = 256 * 1024;
2384
2385         /*
2386          * Global gtt pte registers are special registers which actually forward
2387          * writes to a chunk of system memory. Which means that there is no risk
2388          * that the register values disappear as soon as we call
2389          * intel_runtime_pm_put(), so it is correct to wrap only the
2390          * pin/unpin/fence and not more.
2391          */
2392         intel_runtime_pm_get(dev_priv);
2393
2394         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2395                                                    &view);
2396         if (ret)
2397                 goto err_pm;
2398
2399         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2400          * fence, whereas 965+ only requires a fence if using
2401          * framebuffer compression.  For simplicity, we always install
2402          * a fence as the cost is not that onerous.
2403          */
2404         if (view.type == I915_GGTT_VIEW_NORMAL) {
2405                 ret = i915_gem_object_get_fence(obj);
2406                 if (ret == -EDEADLK) {
2407                         /*
2408                          * -EDEADLK means there are no free fences
2409                          * no pending flips.
2410                          *
2411                          * This is propagated to atomic, but it uses
2412                          * -EDEADLK to force a locking recovery, so
2413                          * change the returned error to -EBUSY.
2414                          */
2415                         ret = -EBUSY;
2416                         goto err_unpin;
2417                 } else if (ret)
2418                         goto err_unpin;
2419
2420                 i915_gem_object_pin_fence(obj);
2421         }
2422
2423         intel_runtime_pm_put(dev_priv);
2424         return 0;
2425
2426 err_unpin:
2427         i915_gem_object_unpin_from_display_plane(obj, &view);
2428 err_pm:
2429         intel_runtime_pm_put(dev_priv);
2430         return ret;
2431 }
2432
2433 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434                                const struct drm_plane_state *plane_state)
2435 {
2436         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2437         struct i915_ggtt_view view;
2438
2439         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2440
2441         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2442
2443         if (view.type == I915_GGTT_VIEW_NORMAL)
2444                 i915_gem_object_unpin_fence(obj);
2445
2446         i915_gem_object_unpin_from_display_plane(obj, &view);
2447 }
2448
2449 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2450  * is assumed to be a power-of-two. */
2451 unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
2452                                         int *x, int *y,
2453                                         uint64_t fb_modifier,
2454                                         unsigned int cpp,
2455                                         unsigned int pitch)
2456 {
2457         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2458                 unsigned int tile_size, tile_width, tile_height;
2459                 unsigned int tile_rows, tiles;
2460
2461                 tile_size = intel_tile_size(dev_priv);
2462                 tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
2463                 tile_height = tile_size / tile_width;
2464
2465                 tile_rows = *y / tile_height;
2466                 *y %= tile_height;
2467
2468                 tiles = *x / (tile_width/cpp);
2469                 *x %= tile_width/cpp;
2470
2471                 return tile_rows * pitch * tile_height + tiles * tile_size;
2472         } else {
2473                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2474                 unsigned int offset;
2475
2476                 offset = *y * pitch + *x * cpp;
2477                 *y = (offset & alignment) / pitch;
2478                 *x = ((offset & alignment) - *y * pitch) / cpp;
2479                 return offset & ~alignment;
2480         }
2481 }
2482
2483 static int i9xx_format_to_fourcc(int format)
2484 {
2485         switch (format) {
2486         case DISPPLANE_8BPP:
2487                 return DRM_FORMAT_C8;
2488         case DISPPLANE_BGRX555:
2489                 return DRM_FORMAT_XRGB1555;
2490         case DISPPLANE_BGRX565:
2491                 return DRM_FORMAT_RGB565;
2492         default:
2493         case DISPPLANE_BGRX888:
2494                 return DRM_FORMAT_XRGB8888;
2495         case DISPPLANE_RGBX888:
2496                 return DRM_FORMAT_XBGR8888;
2497         case DISPPLANE_BGRX101010:
2498                 return DRM_FORMAT_XRGB2101010;
2499         case DISPPLANE_RGBX101010:
2500                 return DRM_FORMAT_XBGR2101010;
2501         }
2502 }
2503
2504 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2505 {
2506         switch (format) {
2507         case PLANE_CTL_FORMAT_RGB_565:
2508                 return DRM_FORMAT_RGB565;
2509         default:
2510         case PLANE_CTL_FORMAT_XRGB_8888:
2511                 if (rgb_order) {
2512                         if (alpha)
2513                                 return DRM_FORMAT_ABGR8888;
2514                         else
2515                                 return DRM_FORMAT_XBGR8888;
2516                 } else {
2517                         if (alpha)
2518                                 return DRM_FORMAT_ARGB8888;
2519                         else
2520                                 return DRM_FORMAT_XRGB8888;
2521                 }
2522         case PLANE_CTL_FORMAT_XRGB_2101010:
2523                 if (rgb_order)
2524                         return DRM_FORMAT_XBGR2101010;
2525                 else
2526                         return DRM_FORMAT_XRGB2101010;
2527         }
2528 }
2529
2530 static bool
2531 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2532                               struct intel_initial_plane_config *plane_config)
2533 {
2534         struct drm_device *dev = crtc->base.dev;
2535         struct drm_i915_private *dev_priv = to_i915(dev);
2536         struct drm_i915_gem_object *obj = NULL;
2537         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2538         struct drm_framebuffer *fb = &plane_config->fb->base;
2539         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2540         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2541                                     PAGE_SIZE);
2542
2543         size_aligned -= base_aligned;
2544
2545         if (plane_config->size == 0)
2546                 return false;
2547
2548         /* If the FB is too big, just don't use it since fbdev is not very
2549          * important and we should probably use that space with FBC or other
2550          * features. */
2551         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2552                 return false;
2553
2554         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2555                                                              base_aligned,
2556                                                              base_aligned,
2557                                                              size_aligned);
2558         if (!obj)
2559                 return false;
2560
2561         obj->tiling_mode = plane_config->tiling;
2562         if (obj->tiling_mode == I915_TILING_X)
2563                 obj->stride = fb->pitches[0];
2564
2565         mode_cmd.pixel_format = fb->pixel_format;
2566         mode_cmd.width = fb->width;
2567         mode_cmd.height = fb->height;
2568         mode_cmd.pitches[0] = fb->pitches[0];
2569         mode_cmd.modifier[0] = fb->modifier[0];
2570         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2571
2572         mutex_lock(&dev->struct_mutex);
2573         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2574                                    &mode_cmd, obj)) {
2575                 DRM_DEBUG_KMS("intel fb init failed\n");
2576                 goto out_unref_obj;
2577         }
2578         mutex_unlock(&dev->struct_mutex);
2579
2580         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2581         return true;
2582
2583 out_unref_obj:
2584         drm_gem_object_unreference(&obj->base);
2585         mutex_unlock(&dev->struct_mutex);
2586         return false;
2587 }
2588
2589 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2590 static void
2591 update_state_fb(struct drm_plane *plane)
2592 {
2593         if (plane->fb == plane->state->fb)
2594                 return;
2595
2596         if (plane->state->fb)
2597                 drm_framebuffer_unreference(plane->state->fb);
2598         plane->state->fb = plane->fb;
2599         if (plane->state->fb)
2600                 drm_framebuffer_reference(plane->state->fb);
2601 }
2602
2603 static void
2604 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2605                              struct intel_initial_plane_config *plane_config)
2606 {
2607         struct drm_device *dev = intel_crtc->base.dev;
2608         struct drm_i915_private *dev_priv = dev->dev_private;
2609         struct drm_crtc *c;
2610         struct intel_crtc *i;
2611         struct drm_i915_gem_object *obj;
2612         struct drm_plane *primary = intel_crtc->base.primary;
2613         struct drm_plane_state *plane_state = primary->state;
2614         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2615         struct intel_plane *intel_plane = to_intel_plane(primary);
2616         struct intel_plane_state *intel_state =
2617                 to_intel_plane_state(plane_state);
2618         struct drm_framebuffer *fb;
2619
2620         if (!plane_config->fb)
2621                 return;
2622
2623         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2624                 fb = &plane_config->fb->base;
2625                 goto valid_fb;
2626         }
2627
2628         kfree(plane_config->fb);
2629
2630         /*
2631          * Failed to alloc the obj, check to see if we should share
2632          * an fb with another CRTC instead
2633          */
2634         for_each_crtc(dev, c) {
2635                 i = to_intel_crtc(c);
2636
2637                 if (c == &intel_crtc->base)
2638                         continue;
2639
2640                 if (!i->active)
2641                         continue;
2642
2643                 fb = c->primary->fb;
2644                 if (!fb)
2645                         continue;
2646
2647                 obj = intel_fb_obj(fb);
2648                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2649                         drm_framebuffer_reference(fb);
2650                         goto valid_fb;
2651                 }
2652         }
2653
2654         /*
2655          * We've failed to reconstruct the BIOS FB.  Current display state
2656          * indicates that the primary plane is visible, but has a NULL FB,
2657          * which will lead to problems later if we don't fix it up.  The
2658          * simplest solution is to just disable the primary plane now and
2659          * pretend the BIOS never had it enabled.
2660          */
2661         to_intel_plane_state(plane_state)->visible = false;
2662         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2663         intel_pre_disable_primary(&intel_crtc->base);
2664         intel_plane->disable_plane(primary, &intel_crtc->base);
2665
2666         return;
2667
2668 valid_fb:
2669         plane_state->src_x = 0;
2670         plane_state->src_y = 0;
2671         plane_state->src_w = fb->width << 16;
2672         plane_state->src_h = fb->height << 16;
2673
2674         plane_state->crtc_x = 0;
2675         plane_state->crtc_y = 0;
2676         plane_state->crtc_w = fb->width;
2677         plane_state->crtc_h = fb->height;
2678
2679         intel_state->src.x1 = plane_state->src_x;
2680         intel_state->src.y1 = plane_state->src_y;
2681         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2682         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2683         intel_state->dst.x1 = plane_state->crtc_x;
2684         intel_state->dst.y1 = plane_state->crtc_y;
2685         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2686         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2687
2688         obj = intel_fb_obj(fb);
2689         if (obj->tiling_mode != I915_TILING_NONE)
2690                 dev_priv->preserve_bios_swizzle = true;
2691
2692         drm_framebuffer_reference(fb);
2693         primary->fb = primary->state->fb = fb;
2694         primary->crtc = primary->state->crtc = &intel_crtc->base;
2695         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2696         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2697 }
2698
2699 static void i9xx_update_primary_plane(struct drm_plane *primary,
2700                                       const struct intel_crtc_state *crtc_state,
2701                                       const struct intel_plane_state *plane_state)
2702 {
2703         struct drm_device *dev = primary->dev;
2704         struct drm_i915_private *dev_priv = dev->dev_private;
2705         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2706         struct drm_framebuffer *fb = plane_state->base.fb;
2707         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2708         int plane = intel_crtc->plane;
2709         unsigned long linear_offset;
2710         int x = plane_state->src.x1 >> 16;
2711         int y = plane_state->src.y1 >> 16;
2712         u32 dspcntr;
2713         i915_reg_t reg = DSPCNTR(plane);
2714         int pixel_size;
2715
2716         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2717
2718         dspcntr = DISPPLANE_GAMMA_ENABLE;
2719
2720         dspcntr |= DISPLAY_PLANE_ENABLE;
2721
2722         if (INTEL_INFO(dev)->gen < 4) {
2723                 if (intel_crtc->pipe == PIPE_B)
2724                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2725
2726                 /* pipesrc and dspsize control the size that is scaled from,
2727                  * which should always be the user's requested size.
2728                  */
2729                 I915_WRITE(DSPSIZE(plane),
2730                            ((crtc_state->pipe_src_h - 1) << 16) |
2731                            (crtc_state->pipe_src_w - 1));
2732                 I915_WRITE(DSPPOS(plane), 0);
2733         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2734                 I915_WRITE(PRIMSIZE(plane),
2735                            ((crtc_state->pipe_src_h - 1) << 16) |
2736                            (crtc_state->pipe_src_w - 1));
2737                 I915_WRITE(PRIMPOS(plane), 0);
2738                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2739         }
2740
2741         switch (fb->pixel_format) {
2742         case DRM_FORMAT_C8:
2743                 dspcntr |= DISPPLANE_8BPP;
2744                 break;
2745         case DRM_FORMAT_XRGB1555:
2746                 dspcntr |= DISPPLANE_BGRX555;
2747                 break;
2748         case DRM_FORMAT_RGB565:
2749                 dspcntr |= DISPPLANE_BGRX565;
2750                 break;
2751         case DRM_FORMAT_XRGB8888:
2752                 dspcntr |= DISPPLANE_BGRX888;
2753                 break;
2754         case DRM_FORMAT_XBGR8888:
2755                 dspcntr |= DISPPLANE_RGBX888;
2756                 break;
2757         case DRM_FORMAT_XRGB2101010:
2758                 dspcntr |= DISPPLANE_BGRX101010;
2759                 break;
2760         case DRM_FORMAT_XBGR2101010:
2761                 dspcntr |= DISPPLANE_RGBX101010;
2762                 break;
2763         default:
2764                 BUG();
2765         }
2766
2767         if (INTEL_INFO(dev)->gen >= 4 &&
2768             obj->tiling_mode != I915_TILING_NONE)
2769                 dspcntr |= DISPPLANE_TILED;
2770
2771         if (IS_G4X(dev))
2772                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2773
2774         linear_offset = y * fb->pitches[0] + x * pixel_size;
2775
2776         if (INTEL_INFO(dev)->gen >= 4) {
2777                 intel_crtc->dspaddr_offset =
2778                         intel_compute_tile_offset(dev_priv, &x, &y,
2779                                                   fb->modifier[0],
2780                                                   pixel_size,
2781                                                   fb->pitches[0]);
2782                 linear_offset -= intel_crtc->dspaddr_offset;
2783         } else {
2784                 intel_crtc->dspaddr_offset = linear_offset;
2785         }
2786
2787         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2788                 dspcntr |= DISPPLANE_ROTATE_180;
2789
2790                 x += (crtc_state->pipe_src_w - 1);
2791                 y += (crtc_state->pipe_src_h - 1);
2792
2793                 /* Finding the last pixel of the last line of the display
2794                 data and adding to linear_offset*/
2795                 linear_offset +=
2796                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2797                         (crtc_state->pipe_src_w - 1) * pixel_size;
2798         }
2799
2800         intel_crtc->adjusted_x = x;
2801         intel_crtc->adjusted_y = y;
2802
2803         I915_WRITE(reg, dspcntr);
2804
2805         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2806         if (INTEL_INFO(dev)->gen >= 4) {
2807                 I915_WRITE(DSPSURF(plane),
2808                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2809                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2810                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2811         } else
2812                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2813         POSTING_READ(reg);
2814 }
2815
2816 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2817                                        struct drm_crtc *crtc)
2818 {
2819         struct drm_device *dev = crtc->dev;
2820         struct drm_i915_private *dev_priv = dev->dev_private;
2821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2822         int plane = intel_crtc->plane;
2823
2824         I915_WRITE(DSPCNTR(plane), 0);
2825         if (INTEL_INFO(dev_priv)->gen >= 4)
2826                 I915_WRITE(DSPSURF(plane), 0);
2827         else
2828                 I915_WRITE(DSPADDR(plane), 0);
2829         POSTING_READ(DSPCNTR(plane));
2830 }
2831
2832 static void ironlake_update_primary_plane(struct drm_plane *primary,
2833                                           const struct intel_crtc_state *crtc_state,
2834                                           const struct intel_plane_state *plane_state)
2835 {
2836         struct drm_device *dev = primary->dev;
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2839         struct drm_framebuffer *fb = plane_state->base.fb;
2840         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2841         int plane = intel_crtc->plane;
2842         unsigned long linear_offset;
2843         u32 dspcntr;
2844         i915_reg_t reg = DSPCNTR(plane);
2845         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2846         int x = plane_state->src.x1 >> 16;
2847         int y = plane_state->src.y1 >> 16;
2848
2849         dspcntr = DISPPLANE_GAMMA_ENABLE;
2850         dspcntr |= DISPLAY_PLANE_ENABLE;
2851
2852         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2853                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2854
2855         switch (fb->pixel_format) {
2856         case DRM_FORMAT_C8:
2857                 dspcntr |= DISPPLANE_8BPP;
2858                 break;
2859         case DRM_FORMAT_RGB565:
2860                 dspcntr |= DISPPLANE_BGRX565;
2861                 break;
2862         case DRM_FORMAT_XRGB8888:
2863                 dspcntr |= DISPPLANE_BGRX888;
2864                 break;
2865         case DRM_FORMAT_XBGR8888:
2866                 dspcntr |= DISPPLANE_RGBX888;
2867                 break;
2868         case DRM_FORMAT_XRGB2101010:
2869                 dspcntr |= DISPPLANE_BGRX101010;
2870                 break;
2871         case DRM_FORMAT_XBGR2101010:
2872                 dspcntr |= DISPPLANE_RGBX101010;
2873                 break;
2874         default:
2875                 BUG();
2876         }
2877
2878         if (obj->tiling_mode != I915_TILING_NONE)
2879                 dspcntr |= DISPPLANE_TILED;
2880
2881         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2882                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2883
2884         linear_offset = y * fb->pitches[0] + x * pixel_size;
2885         intel_crtc->dspaddr_offset =
2886                 intel_compute_tile_offset(dev_priv, &x, &y,
2887                                           fb->modifier[0],
2888                                           pixel_size,
2889                                           fb->pitches[0]);
2890         linear_offset -= intel_crtc->dspaddr_offset;
2891         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2892                 dspcntr |= DISPPLANE_ROTATE_180;
2893
2894                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2895                         x += (crtc_state->pipe_src_w - 1);
2896                         y += (crtc_state->pipe_src_h - 1);
2897
2898                         /* Finding the last pixel of the last line of the display
2899                         data and adding to linear_offset*/
2900                         linear_offset +=
2901                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2902                                 (crtc_state->pipe_src_w - 1) * pixel_size;
2903                 }
2904         }
2905
2906         intel_crtc->adjusted_x = x;
2907         intel_crtc->adjusted_y = y;
2908
2909         I915_WRITE(reg, dspcntr);
2910
2911         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2912         I915_WRITE(DSPSURF(plane),
2913                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2914         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2915                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2916         } else {
2917                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2918                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2919         }
2920         POSTING_READ(reg);
2921 }
2922
2923 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2924                               uint64_t fb_modifier, uint32_t pixel_format)
2925 {
2926         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2927                 return 64;
2928         } else {
2929                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2930
2931                 return intel_tile_width(dev_priv, fb_modifier, cpp);
2932         }
2933 }
2934
2935 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2936                            struct drm_i915_gem_object *obj,
2937                            unsigned int plane)
2938 {
2939         struct i915_ggtt_view view;
2940         struct i915_vma *vma;
2941         u64 offset;
2942
2943         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2944                                 intel_plane->base.state);
2945
2946         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2947         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2948                 view.type))
2949                 return -1;
2950
2951         offset = vma->node.start;
2952
2953         if (plane == 1) {
2954                 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2955                           PAGE_SIZE;
2956         }
2957
2958         WARN_ON(upper_32_bits(offset));
2959
2960         return lower_32_bits(offset);
2961 }
2962
2963 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2964 {
2965         struct drm_device *dev = intel_crtc->base.dev;
2966         struct drm_i915_private *dev_priv = dev->dev_private;
2967
2968         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2969         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2970         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2971 }
2972
2973 /*
2974  * This function detaches (aka. unbinds) unused scalers in hardware
2975  */
2976 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2977 {
2978         struct intel_crtc_scaler_state *scaler_state;
2979         int i;
2980
2981         scaler_state = &intel_crtc->config->scaler_state;
2982
2983         /* loop through and disable scalers that aren't in use */
2984         for (i = 0; i < intel_crtc->num_scalers; i++) {
2985                 if (!scaler_state->scalers[i].in_use)
2986                         skl_detach_scaler(intel_crtc, i);
2987         }
2988 }
2989
2990 u32 skl_plane_ctl_format(uint32_t pixel_format)
2991 {
2992         switch (pixel_format) {
2993         case DRM_FORMAT_C8:
2994                 return PLANE_CTL_FORMAT_INDEXED;
2995         case DRM_FORMAT_RGB565:
2996                 return PLANE_CTL_FORMAT_RGB_565;
2997         case DRM_FORMAT_XBGR8888:
2998                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2999         case DRM_FORMAT_XRGB8888:
3000                 return PLANE_CTL_FORMAT_XRGB_8888;
3001         /*
3002          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3003          * to be already pre-multiplied. We need to add a knob (or a different
3004          * DRM_FORMAT) for user-space to configure that.
3005          */
3006         case DRM_FORMAT_ABGR8888:
3007                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3008                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3009         case DRM_FORMAT_ARGB8888:
3010                 return PLANE_CTL_FORMAT_XRGB_8888 |
3011                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3012         case DRM_FORMAT_XRGB2101010:
3013                 return PLANE_CTL_FORMAT_XRGB_2101010;
3014         case DRM_FORMAT_XBGR2101010:
3015                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3016         case DRM_FORMAT_YUYV:
3017                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3018         case DRM_FORMAT_YVYU:
3019                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3020         case DRM_FORMAT_UYVY:
3021                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3022         case DRM_FORMAT_VYUY:
3023                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3024         default:
3025                 MISSING_CASE(pixel_format);
3026         }
3027
3028         return 0;
3029 }
3030
3031 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3032 {
3033         switch (fb_modifier) {
3034         case DRM_FORMAT_MOD_NONE:
3035                 break;
3036         case I915_FORMAT_MOD_X_TILED:
3037                 return PLANE_CTL_TILED_X;
3038         case I915_FORMAT_MOD_Y_TILED:
3039                 return PLANE_CTL_TILED_Y;
3040         case I915_FORMAT_MOD_Yf_TILED:
3041                 return PLANE_CTL_TILED_YF;
3042         default:
3043                 MISSING_CASE(fb_modifier);
3044         }
3045
3046         return 0;
3047 }
3048
3049 u32 skl_plane_ctl_rotation(unsigned int rotation)
3050 {
3051         switch (rotation) {
3052         case BIT(DRM_ROTATE_0):
3053                 break;
3054         /*
3055          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3056          * while i915 HW rotation is clockwise, thats why this swapping.
3057          */
3058         case BIT(DRM_ROTATE_90):
3059                 return PLANE_CTL_ROTATE_270;
3060         case BIT(DRM_ROTATE_180):
3061                 return PLANE_CTL_ROTATE_180;
3062         case BIT(DRM_ROTATE_270):
3063                 return PLANE_CTL_ROTATE_90;
3064         default:
3065                 MISSING_CASE(rotation);
3066         }
3067
3068         return 0;
3069 }
3070
3071 static void skylake_update_primary_plane(struct drm_plane *plane,
3072                                          const struct intel_crtc_state *crtc_state,
3073                                          const struct intel_plane_state *plane_state)
3074 {
3075         struct drm_device *dev = plane->dev;
3076         struct drm_i915_private *dev_priv = dev->dev_private;
3077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3078         struct drm_framebuffer *fb = plane_state->base.fb;
3079         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3080         int pipe = intel_crtc->pipe;
3081         u32 plane_ctl, stride_div, stride;
3082         u32 tile_height, plane_offset, plane_size;
3083         unsigned int rotation = plane_state->base.rotation;
3084         int x_offset, y_offset;
3085         u32 surf_addr;
3086         int scaler_id = plane_state->scaler_id;
3087         int src_x = plane_state->src.x1 >> 16;
3088         int src_y = plane_state->src.y1 >> 16;
3089         int src_w = drm_rect_width(&plane_state->src) >> 16;
3090         int src_h = drm_rect_height(&plane_state->src) >> 16;
3091         int dst_x = plane_state->dst.x1;
3092         int dst_y = plane_state->dst.y1;
3093         int dst_w = drm_rect_width(&plane_state->dst);
3094         int dst_h = drm_rect_height(&plane_state->dst);
3095
3096         plane_ctl = PLANE_CTL_ENABLE |
3097                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3098                     PLANE_CTL_PIPE_CSC_ENABLE;
3099
3100         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3101         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3102         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3103         plane_ctl |= skl_plane_ctl_rotation(rotation);
3104
3105         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3106                                                fb->pixel_format);
3107         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3108
3109         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3110
3111         if (intel_rotation_90_or_270(rotation)) {
3112                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3113
3114                 /* stride = Surface height in tiles */
3115                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3116                 stride = DIV_ROUND_UP(fb->height, tile_height);
3117                 x_offset = stride * tile_height - src_y - src_h;
3118                 y_offset = src_x;
3119                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3120         } else {
3121                 stride = fb->pitches[0] / stride_div;
3122                 x_offset = src_x;
3123                 y_offset = src_y;
3124                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3125         }
3126         plane_offset = y_offset << 16 | x_offset;
3127
3128         intel_crtc->adjusted_x = x_offset;
3129         intel_crtc->adjusted_y = y_offset;
3130
3131         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3132         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3133         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3134         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3135
3136         if (scaler_id >= 0) {
3137                 uint32_t ps_ctrl = 0;
3138
3139                 WARN_ON(!dst_w || !dst_h);
3140                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3141                         crtc_state->scaler_state.scalers[scaler_id].mode;
3142                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3143                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3144                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3145                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3146                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3147         } else {
3148                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3149         }
3150
3151         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3152
3153         POSTING_READ(PLANE_SURF(pipe, 0));
3154 }
3155
3156 static void skylake_disable_primary_plane(struct drm_plane *primary,
3157                                           struct drm_crtc *crtc)
3158 {
3159         struct drm_device *dev = crtc->dev;
3160         struct drm_i915_private *dev_priv = dev->dev_private;
3161         int pipe = to_intel_crtc(crtc)->pipe;
3162
3163         if (dev_priv->fbc.deactivate)
3164                 dev_priv->fbc.deactivate(dev_priv);
3165
3166         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3167         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3168         POSTING_READ(PLANE_SURF(pipe, 0));
3169 }
3170
3171 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3172 static int
3173 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3174                            int x, int y, enum mode_set_atomic state)
3175 {
3176         /* Support for kgdboc is disabled, this needs a major rework. */
3177         DRM_ERROR("legacy panic handler not supported any more.\n");
3178
3179         return -ENODEV;
3180 }
3181
3182 static void intel_complete_page_flips(struct drm_device *dev)
3183 {
3184         struct drm_crtc *crtc;
3185
3186         for_each_crtc(dev, crtc) {
3187                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188                 enum plane plane = intel_crtc->plane;
3189
3190                 intel_prepare_page_flip(dev, plane);
3191                 intel_finish_page_flip_plane(dev, plane);
3192         }
3193 }
3194
3195 static void intel_update_primary_planes(struct drm_device *dev)
3196 {
3197         struct drm_crtc *crtc;
3198
3199         for_each_crtc(dev, crtc) {
3200                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3201                 struct intel_plane_state *plane_state;
3202
3203                 drm_modeset_lock_crtc(crtc, &plane->base);
3204                 plane_state = to_intel_plane_state(plane->base.state);
3205
3206                 if (plane_state->visible)
3207                         plane->update_plane(&plane->base,
3208                                             to_intel_crtc_state(crtc->state),
3209                                             plane_state);
3210
3211                 drm_modeset_unlock_crtc(crtc);
3212         }
3213 }
3214
3215 void intel_prepare_reset(struct drm_device *dev)
3216 {
3217         /* no reset support for gen2 */
3218         if (IS_GEN2(dev))
3219                 return;
3220
3221         /* reset doesn't touch the display */
3222         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3223                 return;
3224
3225         drm_modeset_lock_all(dev);
3226         /*
3227          * Disabling the crtcs gracefully seems nicer. Also the
3228          * g33 docs say we should at least disable all the planes.
3229          */
3230         intel_display_suspend(dev);
3231 }
3232
3233 void intel_finish_reset(struct drm_device *dev)
3234 {
3235         struct drm_i915_private *dev_priv = to_i915(dev);
3236
3237         /*
3238          * Flips in the rings will be nuked by the reset,
3239          * so complete all pending flips so that user space
3240          * will get its events and not get stuck.
3241          */
3242         intel_complete_page_flips(dev);
3243
3244         /* no reset support for gen2 */
3245         if (IS_GEN2(dev))
3246                 return;
3247
3248         /* reset doesn't touch the display */
3249         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3250                 /*
3251                  * Flips in the rings have been nuked by the reset,
3252                  * so update the base address of all primary
3253                  * planes to the the last fb to make sure we're
3254                  * showing the correct fb after a reset.
3255                  *
3256                  * FIXME: Atomic will make this obsolete since we won't schedule
3257                  * CS-based flips (which might get lost in gpu resets) any more.
3258                  */
3259                 intel_update_primary_planes(dev);
3260                 return;
3261         }
3262
3263         /*
3264          * The display has been reset as well,
3265          * so need a full re-initialization.
3266          */
3267         intel_runtime_pm_disable_interrupts(dev_priv);
3268         intel_runtime_pm_enable_interrupts(dev_priv);
3269
3270         intel_modeset_init_hw(dev);
3271
3272         spin_lock_irq(&dev_priv->irq_lock);
3273         if (dev_priv->display.hpd_irq_setup)
3274                 dev_priv->display.hpd_irq_setup(dev);
3275         spin_unlock_irq(&dev_priv->irq_lock);
3276
3277         intel_display_resume(dev);
3278
3279         intel_hpd_init(dev_priv);
3280
3281         drm_modeset_unlock_all(dev);
3282 }
3283
3284 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3285 {
3286         struct drm_device *dev = crtc->dev;
3287         struct drm_i915_private *dev_priv = dev->dev_private;
3288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3289         bool pending;
3290
3291         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3292             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3293                 return false;
3294
3295         spin_lock_irq(&dev->event_lock);
3296         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3297         spin_unlock_irq(&dev->event_lock);
3298
3299         return pending;
3300 }
3301
3302 static void intel_update_pipe_config(struct intel_crtc *crtc,
3303                                      struct intel_crtc_state *old_crtc_state)
3304 {
3305         struct drm_device *dev = crtc->base.dev;
3306         struct drm_i915_private *dev_priv = dev->dev_private;
3307         struct intel_crtc_state *pipe_config =
3308                 to_intel_crtc_state(crtc->base.state);
3309
3310         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3311         crtc->base.mode = crtc->base.state->mode;
3312
3313         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3314                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3315                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3316
3317         if (HAS_DDI(dev))
3318                 intel_set_pipe_csc(&crtc->base);
3319
3320         /*
3321          * Update pipe size and adjust fitter if needed: the reason for this is
3322          * that in compute_mode_changes we check the native mode (not the pfit
3323          * mode) to see if we can flip rather than do a full mode set. In the
3324          * fastboot case, we'll flip, but if we don't update the pipesrc and
3325          * pfit state, we'll end up with a big fb scanned out into the wrong
3326          * sized surface.
3327          */
3328
3329         I915_WRITE(PIPESRC(crtc->pipe),
3330                    ((pipe_config->pipe_src_w - 1) << 16) |
3331                    (pipe_config->pipe_src_h - 1));
3332
3333         /* on skylake this is done by detaching scalers */
3334         if (INTEL_INFO(dev)->gen >= 9) {
3335                 skl_detach_scalers(crtc);
3336
3337                 if (pipe_config->pch_pfit.enabled)
3338                         skylake_pfit_enable(crtc);
3339         } else if (HAS_PCH_SPLIT(dev)) {
3340                 if (pipe_config->pch_pfit.enabled)
3341                         ironlake_pfit_enable(crtc);
3342                 else if (old_crtc_state->pch_pfit.enabled)
3343                         ironlake_pfit_disable(crtc, true);
3344         }
3345 }
3346
3347 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3348 {
3349         struct drm_device *dev = crtc->dev;
3350         struct drm_i915_private *dev_priv = dev->dev_private;
3351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3352         int pipe = intel_crtc->pipe;
3353         i915_reg_t reg;
3354         u32 temp;
3355
3356         /* enable normal train */
3357         reg = FDI_TX_CTL(pipe);
3358         temp = I915_READ(reg);
3359         if (IS_IVYBRIDGE(dev)) {
3360                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3361                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3362         } else {
3363                 temp &= ~FDI_LINK_TRAIN_NONE;
3364                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3365         }
3366         I915_WRITE(reg, temp);
3367
3368         reg = FDI_RX_CTL(pipe);
3369         temp = I915_READ(reg);
3370         if (HAS_PCH_CPT(dev)) {
3371                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3372                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3373         } else {
3374                 temp &= ~FDI_LINK_TRAIN_NONE;
3375                 temp |= FDI_LINK_TRAIN_NONE;
3376         }
3377         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3378
3379         /* wait one idle pattern time */
3380         POSTING_READ(reg);
3381         udelay(1000);
3382
3383         /* IVB wants error correction enabled */
3384         if (IS_IVYBRIDGE(dev))
3385                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3386                            FDI_FE_ERRC_ENABLE);
3387 }
3388
3389 /* The FDI link training functions for ILK/Ibexpeak. */
3390 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3391 {
3392         struct drm_device *dev = crtc->dev;
3393         struct drm_i915_private *dev_priv = dev->dev_private;
3394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3395         int pipe = intel_crtc->pipe;
3396         i915_reg_t reg;
3397         u32 temp, tries;
3398
3399         /* FDI needs bits from pipe first */
3400         assert_pipe_enabled(dev_priv, pipe);
3401
3402         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3403            for train result */
3404         reg = FDI_RX_IMR(pipe);
3405         temp = I915_READ(reg);
3406         temp &= ~FDI_RX_SYMBOL_LOCK;
3407         temp &= ~FDI_RX_BIT_LOCK;
3408         I915_WRITE(reg, temp);
3409         I915_READ(reg);
3410         udelay(150);
3411
3412         /* enable CPU FDI TX and PCH FDI RX */
3413         reg = FDI_TX_CTL(pipe);
3414         temp = I915_READ(reg);
3415         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3416         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3417         temp &= ~FDI_LINK_TRAIN_NONE;
3418         temp |= FDI_LINK_TRAIN_PATTERN_1;
3419         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3420
3421         reg = FDI_RX_CTL(pipe);
3422         temp = I915_READ(reg);
3423         temp &= ~FDI_LINK_TRAIN_NONE;
3424         temp |= FDI_LINK_TRAIN_PATTERN_1;
3425         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3426
3427         POSTING_READ(reg);
3428         udelay(150);
3429
3430         /* Ironlake workaround, enable clock pointer after FDI enable*/
3431         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3432         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3433                    FDI_RX_PHASE_SYNC_POINTER_EN);
3434
3435         reg = FDI_RX_IIR(pipe);
3436         for (tries = 0; tries < 5; tries++) {
3437                 temp = I915_READ(reg);
3438                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439
3440                 if ((temp & FDI_RX_BIT_LOCK)) {
3441                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3442                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3443                         break;
3444                 }
3445         }
3446         if (tries == 5)
3447                 DRM_ERROR("FDI train 1 fail!\n");
3448
3449         /* Train 2 */
3450         reg = FDI_TX_CTL(pipe);
3451         temp = I915_READ(reg);
3452         temp &= ~FDI_LINK_TRAIN_NONE;
3453         temp |= FDI_LINK_TRAIN_PATTERN_2;
3454         I915_WRITE(reg, temp);
3455
3456         reg = FDI_RX_CTL(pipe);
3457         temp = I915_READ(reg);
3458         temp &= ~FDI_LINK_TRAIN_NONE;
3459         temp |= FDI_LINK_TRAIN_PATTERN_2;
3460         I915_WRITE(reg, temp);
3461
3462         POSTING_READ(reg);
3463         udelay(150);
3464
3465         reg = FDI_RX_IIR(pipe);
3466         for (tries = 0; tries < 5; tries++) {
3467                 temp = I915_READ(reg);
3468                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3469
3470                 if (temp & FDI_RX_SYMBOL_LOCK) {
3471                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3472                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3473                         break;
3474                 }
3475         }
3476         if (tries == 5)
3477                 DRM_ERROR("FDI train 2 fail!\n");
3478
3479         DRM_DEBUG_KMS("FDI train done\n");
3480
3481 }
3482
3483 static const int snb_b_fdi_train_param[] = {
3484         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3485         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3486         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3487         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3488 };
3489
3490 /* The FDI link training functions for SNB/Cougarpoint. */
3491 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3492 {
3493         struct drm_device *dev = crtc->dev;
3494         struct drm_i915_private *dev_priv = dev->dev_private;
3495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496         int pipe = intel_crtc->pipe;
3497         i915_reg_t reg;
3498         u32 temp, i, retry;
3499
3500         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3501            for train result */
3502         reg = FDI_RX_IMR(pipe);
3503         temp = I915_READ(reg);
3504         temp &= ~FDI_RX_SYMBOL_LOCK;
3505         temp &= ~FDI_RX_BIT_LOCK;
3506         I915_WRITE(reg, temp);
3507
3508         POSTING_READ(reg);
3509         udelay(150);
3510
3511         /* enable CPU FDI TX and PCH FDI RX */
3512         reg = FDI_TX_CTL(pipe);
3513         temp = I915_READ(reg);
3514         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3515         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3516         temp &= ~FDI_LINK_TRAIN_NONE;
3517         temp |= FDI_LINK_TRAIN_PATTERN_1;
3518         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3519         /* SNB-B */
3520         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3521         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3522
3523         I915_WRITE(FDI_RX_MISC(pipe),
3524                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3525
3526         reg = FDI_RX_CTL(pipe);
3527         temp = I915_READ(reg);
3528         if (HAS_PCH_CPT(dev)) {
3529                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3530                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3531         } else {
3532                 temp &= ~FDI_LINK_TRAIN_NONE;
3533                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3534         }
3535         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536
3537         POSTING_READ(reg);
3538         udelay(150);
3539
3540         for (i = 0; i < 4; i++) {
3541                 reg = FDI_TX_CTL(pipe);
3542                 temp = I915_READ(reg);
3543                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3544                 temp |= snb_b_fdi_train_param[i];
3545                 I915_WRITE(reg, temp);
3546
3547                 POSTING_READ(reg);
3548                 udelay(500);
3549
3550                 for (retry = 0; retry < 5; retry++) {
3551                         reg = FDI_RX_IIR(pipe);
3552                         temp = I915_READ(reg);
3553                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3554                         if (temp & FDI_RX_BIT_LOCK) {
3555                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3556                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3557                                 break;
3558                         }
3559                         udelay(50);
3560                 }
3561                 if (retry < 5)
3562                         break;
3563         }
3564         if (i == 4)
3565                 DRM_ERROR("FDI train 1 fail!\n");
3566
3567         /* Train 2 */
3568         reg = FDI_TX_CTL(pipe);
3569         temp = I915_READ(reg);
3570         temp &= ~FDI_LINK_TRAIN_NONE;
3571         temp |= FDI_LINK_TRAIN_PATTERN_2;
3572         if (IS_GEN6(dev)) {
3573                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574                 /* SNB-B */
3575                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3576         }
3577         I915_WRITE(reg, temp);
3578
3579         reg = FDI_RX_CTL(pipe);
3580         temp = I915_READ(reg);
3581         if (HAS_PCH_CPT(dev)) {
3582                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3584         } else {
3585                 temp &= ~FDI_LINK_TRAIN_NONE;
3586                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587         }
3588         I915_WRITE(reg, temp);
3589
3590         POSTING_READ(reg);
3591         udelay(150);
3592
3593         for (i = 0; i < 4; i++) {
3594                 reg = FDI_TX_CTL(pipe);
3595                 temp = I915_READ(reg);
3596                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597                 temp |= snb_b_fdi_train_param[i];
3598                 I915_WRITE(reg, temp);
3599
3600                 POSTING_READ(reg);
3601                 udelay(500);
3602
3603                 for (retry = 0; retry < 5; retry++) {
3604                         reg = FDI_RX_IIR(pipe);
3605                         temp = I915_READ(reg);
3606                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3607                         if (temp & FDI_RX_SYMBOL_LOCK) {
3608                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3609                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3610                                 break;
3611                         }
3612                         udelay(50);
3613                 }
3614                 if (retry < 5)
3615                         break;
3616         }
3617         if (i == 4)
3618                 DRM_ERROR("FDI train 2 fail!\n");
3619
3620         DRM_DEBUG_KMS("FDI train done.\n");
3621 }
3622
3623 /* Manual link training for Ivy Bridge A0 parts */
3624 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3625 {
3626         struct drm_device *dev = crtc->dev;
3627         struct drm_i915_private *dev_priv = dev->dev_private;
3628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629         int pipe = intel_crtc->pipe;
3630         i915_reg_t reg;
3631         u32 temp, i, j;
3632
3633         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3634            for train result */
3635         reg = FDI_RX_IMR(pipe);
3636         temp = I915_READ(reg);
3637         temp &= ~FDI_RX_SYMBOL_LOCK;
3638         temp &= ~FDI_RX_BIT_LOCK;
3639         I915_WRITE(reg, temp);
3640
3641         POSTING_READ(reg);
3642         udelay(150);
3643
3644         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3645                       I915_READ(FDI_RX_IIR(pipe)));
3646
3647         /* Try each vswing and preemphasis setting twice before moving on */
3648         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3649                 /* disable first in case we need to retry */
3650                 reg = FDI_TX_CTL(pipe);
3651                 temp = I915_READ(reg);
3652                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3653                 temp &= ~FDI_TX_ENABLE;
3654                 I915_WRITE(reg, temp);
3655
3656                 reg = FDI_RX_CTL(pipe);
3657                 temp = I915_READ(reg);
3658                 temp &= ~FDI_LINK_TRAIN_AUTO;
3659                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3660                 temp &= ~FDI_RX_ENABLE;
3661                 I915_WRITE(reg, temp);
3662
3663                 /* enable CPU FDI TX and PCH FDI RX */
3664                 reg = FDI_TX_CTL(pipe);
3665                 temp = I915_READ(reg);
3666                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3667                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3668                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3669                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3670                 temp |= snb_b_fdi_train_param[j/2];
3671                 temp |= FDI_COMPOSITE_SYNC;
3672                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3673
3674                 I915_WRITE(FDI_RX_MISC(pipe),
3675                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3676
3677                 reg = FDI_RX_CTL(pipe);
3678                 temp = I915_READ(reg);
3679                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3680                 temp |= FDI_COMPOSITE_SYNC;
3681                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3682
3683                 POSTING_READ(reg);
3684                 udelay(1); /* should be 0.5us */
3685
3686                 for (i = 0; i < 4; i++) {
3687                         reg = FDI_RX_IIR(pipe);
3688                         temp = I915_READ(reg);
3689                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3690
3691                         if (temp & FDI_RX_BIT_LOCK ||
3692                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3693                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3694                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3695                                               i);
3696                                 break;
3697                         }
3698                         udelay(1); /* should be 0.5us */
3699                 }
3700                 if (i == 4) {
3701                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3702                         continue;
3703                 }
3704
3705                 /* Train 2 */
3706                 reg = FDI_TX_CTL(pipe);
3707                 temp = I915_READ(reg);
3708                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3709                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3710                 I915_WRITE(reg, temp);
3711
3712                 reg = FDI_RX_CTL(pipe);
3713                 temp = I915_READ(reg);
3714                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3715                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3716                 I915_WRITE(reg, temp);
3717
3718                 POSTING_READ(reg);
3719                 udelay(2); /* should be 1.5us */
3720
3721                 for (i = 0; i < 4; i++) {
3722                         reg = FDI_RX_IIR(pipe);
3723                         temp = I915_READ(reg);
3724                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3725
3726                         if (temp & FDI_RX_SYMBOL_LOCK ||
3727                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3728                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3729                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3730                                               i);
3731                                 goto train_done;
3732                         }
3733                         udelay(2); /* should be 1.5us */
3734                 }
3735                 if (i == 4)
3736                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3737         }
3738
3739 train_done:
3740         DRM_DEBUG_KMS("FDI train done.\n");
3741 }
3742
3743 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3744 {
3745         struct drm_device *dev = intel_crtc->base.dev;
3746         struct drm_i915_private *dev_priv = dev->dev_private;
3747         int pipe = intel_crtc->pipe;
3748         i915_reg_t reg;
3749         u32 temp;
3750
3751         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3752         reg = FDI_RX_CTL(pipe);
3753         temp = I915_READ(reg);
3754         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3755         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3756         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3757         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3758
3759         POSTING_READ(reg);
3760         udelay(200);
3761
3762         /* Switch from Rawclk to PCDclk */
3763         temp = I915_READ(reg);
3764         I915_WRITE(reg, temp | FDI_PCDCLK);
3765
3766         POSTING_READ(reg);
3767         udelay(200);
3768
3769         /* Enable CPU FDI TX PLL, always on for Ironlake */
3770         reg = FDI_TX_CTL(pipe);
3771         temp = I915_READ(reg);
3772         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3773                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3774
3775                 POSTING_READ(reg);
3776                 udelay(100);
3777         }
3778 }
3779
3780 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3781 {
3782         struct drm_device *dev = intel_crtc->base.dev;
3783         struct drm_i915_private *dev_priv = dev->dev_private;
3784         int pipe = intel_crtc->pipe;
3785         i915_reg_t reg;
3786         u32 temp;
3787
3788         /* Switch from PCDclk to Rawclk */
3789         reg = FDI_RX_CTL(pipe);
3790         temp = I915_READ(reg);
3791         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3792
3793         /* Disable CPU FDI TX PLL */
3794         reg = FDI_TX_CTL(pipe);
3795         temp = I915_READ(reg);
3796         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3797
3798         POSTING_READ(reg);
3799         udelay(100);
3800
3801         reg = FDI_RX_CTL(pipe);
3802         temp = I915_READ(reg);
3803         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3804
3805         /* Wait for the clocks to turn off. */
3806         POSTING_READ(reg);
3807         udelay(100);
3808 }
3809
3810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3811 {
3812         struct drm_device *dev = crtc->dev;
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815         int pipe = intel_crtc->pipe;
3816         i915_reg_t reg;
3817         u32 temp;
3818
3819         /* disable CPU FDI tx and PCH FDI rx */
3820         reg = FDI_TX_CTL(pipe);
3821         temp = I915_READ(reg);
3822         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3823         POSTING_READ(reg);
3824
3825         reg = FDI_RX_CTL(pipe);
3826         temp = I915_READ(reg);
3827         temp &= ~(0x7 << 16);
3828         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3829         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3830
3831         POSTING_READ(reg);
3832         udelay(100);
3833
3834         /* Ironlake workaround, disable clock pointer after downing FDI */
3835         if (HAS_PCH_IBX(dev))
3836                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3837
3838         /* still set train pattern 1 */
3839         reg = FDI_TX_CTL(pipe);
3840         temp = I915_READ(reg);
3841         temp &= ~FDI_LINK_TRAIN_NONE;
3842         temp |= FDI_LINK_TRAIN_PATTERN_1;
3843         I915_WRITE(reg, temp);
3844
3845         reg = FDI_RX_CTL(pipe);
3846         temp = I915_READ(reg);
3847         if (HAS_PCH_CPT(dev)) {
3848                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3849                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3850         } else {
3851                 temp &= ~FDI_LINK_TRAIN_NONE;
3852                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3853         }
3854         /* BPC in FDI rx is consistent with that in PIPECONF */
3855         temp &= ~(0x07 << 16);
3856         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3857         I915_WRITE(reg, temp);
3858
3859         POSTING_READ(reg);
3860         udelay(100);
3861 }
3862
3863 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3864 {
3865         struct intel_crtc *crtc;
3866
3867         /* Note that we don't need to be called with mode_config.lock here
3868          * as our list of CRTC objects is static for the lifetime of the
3869          * device and so cannot disappear as we iterate. Similarly, we can
3870          * happily treat the predicates as racy, atomic checks as userspace
3871          * cannot claim and pin a new fb without at least acquring the
3872          * struct_mutex and so serialising with us.
3873          */
3874         for_each_intel_crtc(dev, crtc) {
3875                 if (atomic_read(&crtc->unpin_work_count) == 0)
3876                         continue;
3877
3878                 if (crtc->unpin_work)
3879                         intel_wait_for_vblank(dev, crtc->pipe);
3880
3881                 return true;
3882         }
3883
3884         return false;
3885 }
3886
3887 static void page_flip_completed(struct intel_crtc *intel_crtc)
3888 {
3889         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3890         struct intel_unpin_work *work = intel_crtc->unpin_work;
3891
3892         /* ensure that the unpin work is consistent wrt ->pending. */
3893         smp_rmb();
3894         intel_crtc->unpin_work = NULL;
3895
3896         if (work->event)
3897                 drm_send_vblank_event(intel_crtc->base.dev,
3898                                       intel_crtc->pipe,
3899                                       work->event);
3900
3901         drm_crtc_vblank_put(&intel_crtc->base);
3902
3903         wake_up_all(&dev_priv->pending_flip_queue);
3904         queue_work(dev_priv->wq, &work->work);
3905
3906         trace_i915_flip_complete(intel_crtc->plane,
3907                                  work->pending_flip_obj);
3908 }
3909
3910 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3911 {
3912         struct drm_device *dev = crtc->dev;
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         long ret;
3915
3916         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3917
3918         ret = wait_event_interruptible_timeout(
3919                                         dev_priv->pending_flip_queue,
3920                                         !intel_crtc_has_pending_flip(crtc),
3921                                         60*HZ);
3922
3923         if (ret < 0)
3924                 return ret;
3925
3926         if (ret == 0) {
3927                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3928
3929                 spin_lock_irq(&dev->event_lock);
3930                 if (intel_crtc->unpin_work) {
3931                         WARN_ONCE(1, "Removing stuck page flip\n");
3932                         page_flip_completed(intel_crtc);
3933                 }
3934                 spin_unlock_irq(&dev->event_lock);
3935         }
3936
3937         return 0;
3938 }
3939
3940 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3941 {
3942         u32 temp;
3943
3944         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3945
3946         mutex_lock(&dev_priv->sb_lock);
3947
3948         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3949         temp |= SBI_SSCCTL_DISABLE;
3950         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3951
3952         mutex_unlock(&dev_priv->sb_lock);
3953 }
3954
3955 /* Program iCLKIP clock to the desired frequency */
3956 static void lpt_program_iclkip(struct drm_crtc *crtc)
3957 {
3958         struct drm_device *dev = crtc->dev;
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3961         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3962         u32 temp;
3963
3964         lpt_disable_iclkip(dev_priv);
3965
3966         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3967         if (clock == 20000) {
3968                 auxdiv = 1;
3969                 divsel = 0x41;
3970                 phaseinc = 0x20;
3971         } else {
3972                 /* The iCLK virtual clock root frequency is in MHz,
3973                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3974                  * divisors, it is necessary to divide one by another, so we
3975                  * convert the virtual clock precision to KHz here for higher
3976                  * precision.
3977                  */
3978                 u32 iclk_virtual_root_freq = 172800 * 1000;
3979                 u32 iclk_pi_range = 64;
3980                 u32 desired_divisor, msb_divisor_value, pi_value;
3981
3982                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
3983                 msb_divisor_value = desired_divisor / iclk_pi_range;
3984                 pi_value = desired_divisor % iclk_pi_range;
3985
3986                 auxdiv = 0;
3987                 divsel = msb_divisor_value - 2;
3988                 phaseinc = pi_value;
3989         }
3990
3991         /* This should not happen with any sane values */
3992         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3993                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3994         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3995                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3996
3997         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3998                         clock,
3999                         auxdiv,
4000                         divsel,
4001                         phasedir,
4002                         phaseinc);
4003
4004         mutex_lock(&dev_priv->sb_lock);
4005
4006         /* Program SSCDIVINTPHASE6 */
4007         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4008         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4009         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4010         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4011         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4012         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4013         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4014         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4015
4016         /* Program SSCAUXDIV */
4017         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4018         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4019         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4020         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4021
4022         /* Enable modulator and associated divider */
4023         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4024         temp &= ~SBI_SSCCTL_DISABLE;
4025         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4026
4027         mutex_unlock(&dev_priv->sb_lock);
4028
4029         /* Wait for initialization time */
4030         udelay(24);
4031
4032         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4033 }
4034
4035 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4036                                                 enum pipe pch_transcoder)
4037 {
4038         struct drm_device *dev = crtc->base.dev;
4039         struct drm_i915_private *dev_priv = dev->dev_private;
4040         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4041
4042         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4043                    I915_READ(HTOTAL(cpu_transcoder)));
4044         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4045                    I915_READ(HBLANK(cpu_transcoder)));
4046         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4047                    I915_READ(HSYNC(cpu_transcoder)));
4048
4049         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4050                    I915_READ(VTOTAL(cpu_transcoder)));
4051         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4052                    I915_READ(VBLANK(cpu_transcoder)));
4053         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4054                    I915_READ(VSYNC(cpu_transcoder)));
4055         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4056                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4057 }
4058
4059 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4060 {
4061         struct drm_i915_private *dev_priv = dev->dev_private;
4062         uint32_t temp;
4063
4064         temp = I915_READ(SOUTH_CHICKEN1);
4065         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4066                 return;
4067
4068         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4069         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4070
4071         temp &= ~FDI_BC_BIFURCATION_SELECT;
4072         if (enable)
4073                 temp |= FDI_BC_BIFURCATION_SELECT;
4074
4075         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4076         I915_WRITE(SOUTH_CHICKEN1, temp);
4077         POSTING_READ(SOUTH_CHICKEN1);
4078 }
4079
4080 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4081 {
4082         struct drm_device *dev = intel_crtc->base.dev;
4083
4084         switch (intel_crtc->pipe) {
4085         case PIPE_A:
4086                 break;
4087         case PIPE_B:
4088                 if (intel_crtc->config->fdi_lanes > 2)
4089                         cpt_set_fdi_bc_bifurcation(dev, false);
4090                 else
4091                         cpt_set_fdi_bc_bifurcation(dev, true);
4092
4093                 break;
4094         case PIPE_C:
4095                 cpt_set_fdi_bc_bifurcation(dev, true);
4096
4097                 break;
4098         default:
4099                 BUG();
4100         }
4101 }
4102
4103 /* Return which DP Port should be selected for Transcoder DP control */
4104 static enum port
4105 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4106 {
4107         struct drm_device *dev = crtc->dev;
4108         struct intel_encoder *encoder;
4109
4110         for_each_encoder_on_crtc(dev, crtc, encoder) {
4111                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4112                     encoder->type == INTEL_OUTPUT_EDP)
4113                         return enc_to_dig_port(&encoder->base)->port;
4114         }
4115
4116         return -1;
4117 }
4118
4119 /*
4120  * Enable PCH resources required for PCH ports:
4121  *   - PCH PLLs
4122  *   - FDI training & RX/TX
4123  *   - update transcoder timings
4124  *   - DP transcoding bits
4125  *   - transcoder
4126  */
4127 static void ironlake_pch_enable(struct drm_crtc *crtc)
4128 {
4129         struct drm_device *dev = crtc->dev;
4130         struct drm_i915_private *dev_priv = dev->dev_private;
4131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4132         int pipe = intel_crtc->pipe;
4133         u32 temp;
4134
4135         assert_pch_transcoder_disabled(dev_priv, pipe);
4136
4137         if (IS_IVYBRIDGE(dev))
4138                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4139
4140         /* Write the TU size bits before fdi link training, so that error
4141          * detection works. */
4142         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4143                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4144
4145         /*
4146          * Sometimes spurious CPU pipe underruns happen during FDI
4147          * training, at least with VGA+HDMI cloning. Suppress them.
4148          */
4149         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4150
4151         /* For PCH output, training FDI link */
4152         dev_priv->display.fdi_link_train(crtc);
4153
4154         /* We need to program the right clock selection before writing the pixel
4155          * mutliplier into the DPLL. */
4156         if (HAS_PCH_CPT(dev)) {
4157                 u32 sel;
4158
4159                 temp = I915_READ(PCH_DPLL_SEL);
4160                 temp |= TRANS_DPLL_ENABLE(pipe);
4161                 sel = TRANS_DPLLB_SEL(pipe);
4162                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4163                         temp |= sel;
4164                 else
4165                         temp &= ~sel;
4166                 I915_WRITE(PCH_DPLL_SEL, temp);
4167         }
4168
4169         /* XXX: pch pll's can be enabled any time before we enable the PCH
4170          * transcoder, and we actually should do this to not upset any PCH
4171          * transcoder that already use the clock when we share it.
4172          *
4173          * Note that enable_shared_dpll tries to do the right thing, but
4174          * get_shared_dpll unconditionally resets the pll - we need that to have
4175          * the right LVDS enable sequence. */
4176         intel_enable_shared_dpll(intel_crtc);
4177
4178         /* set transcoder timing, panel must allow it */
4179         assert_panel_unlocked(dev_priv, pipe);
4180         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4181
4182         intel_fdi_normal_train(crtc);
4183
4184         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4185
4186         /* For PCH DP, enable TRANS_DP_CTL */
4187         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4188                 const struct drm_display_mode *adjusted_mode =
4189                         &intel_crtc->config->base.adjusted_mode;
4190                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4191                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4192                 temp = I915_READ(reg);
4193                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4194                           TRANS_DP_SYNC_MASK |
4195                           TRANS_DP_BPC_MASK);
4196                 temp |= TRANS_DP_OUTPUT_ENABLE;
4197                 temp |= bpc << 9; /* same format but at 11:9 */
4198
4199                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4200                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4201                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4202                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4203
4204                 switch (intel_trans_dp_port_sel(crtc)) {
4205                 case PORT_B:
4206                         temp |= TRANS_DP_PORT_SEL_B;
4207                         break;
4208                 case PORT_C:
4209                         temp |= TRANS_DP_PORT_SEL_C;
4210                         break;
4211                 case PORT_D:
4212                         temp |= TRANS_DP_PORT_SEL_D;
4213                         break;
4214                 default:
4215                         BUG();
4216                 }
4217
4218                 I915_WRITE(reg, temp);
4219         }
4220
4221         ironlake_enable_pch_transcoder(dev_priv, pipe);
4222 }
4223
4224 static void lpt_pch_enable(struct drm_crtc *crtc)
4225 {
4226         struct drm_device *dev = crtc->dev;
4227         struct drm_i915_private *dev_priv = dev->dev_private;
4228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4229         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4230
4231         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4232
4233         lpt_program_iclkip(crtc);
4234
4235         /* Set transcoder timing. */
4236         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4237
4238         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4239 }
4240
4241 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4242                                                 struct intel_crtc_state *crtc_state)
4243 {
4244         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4245         struct intel_shared_dpll *pll;
4246         struct intel_shared_dpll_config *shared_dpll;
4247         enum intel_dpll_id i;
4248         int max = dev_priv->num_shared_dpll;
4249
4250         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4251
4252         if (HAS_PCH_IBX(dev_priv->dev)) {
4253                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4254                 i = (enum intel_dpll_id) crtc->pipe;
4255                 pll = &dev_priv->shared_dplls[i];
4256
4257                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4258                               crtc->base.base.id, pll->name);
4259
4260                 WARN_ON(shared_dpll[i].crtc_mask);
4261
4262                 goto found;
4263         }
4264
4265         if (IS_BROXTON(dev_priv->dev)) {
4266                 /* PLL is attached to port in bxt */
4267                 struct intel_encoder *encoder;
4268                 struct intel_digital_port *intel_dig_port;
4269
4270                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4271                 if (WARN_ON(!encoder))
4272                         return NULL;
4273
4274                 intel_dig_port = enc_to_dig_port(&encoder->base);
4275                 /* 1:1 mapping between ports and PLLs */
4276                 i = (enum intel_dpll_id)intel_dig_port->port;
4277                 pll = &dev_priv->shared_dplls[i];
4278                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4279                         crtc->base.base.id, pll->name);
4280                 WARN_ON(shared_dpll[i].crtc_mask);
4281
4282                 goto found;
4283         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4284                 /* Do not consider SPLL */
4285                 max = 2;
4286
4287         for (i = 0; i < max; i++) {
4288                 pll = &dev_priv->shared_dplls[i];
4289
4290                 /* Only want to check enabled timings first */
4291                 if (shared_dpll[i].crtc_mask == 0)
4292                         continue;
4293
4294                 if (memcmp(&crtc_state->dpll_hw_state,
4295                            &shared_dpll[i].hw_state,
4296                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4297                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4298                                       crtc->base.base.id, pll->name,
4299                                       shared_dpll[i].crtc_mask,
4300                                       pll->active);
4301                         goto found;
4302                 }
4303         }
4304
4305         /* Ok no matching timings, maybe there's a free one? */
4306         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4307                 pll = &dev_priv->shared_dplls[i];
4308                 if (shared_dpll[i].crtc_mask == 0) {
4309                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4310                                       crtc->base.base.id, pll->name);
4311                         goto found;
4312                 }
4313         }
4314
4315         return NULL;
4316
4317 found:
4318         if (shared_dpll[i].crtc_mask == 0)
4319                 shared_dpll[i].hw_state =
4320                         crtc_state->dpll_hw_state;
4321
4322         crtc_state->shared_dpll = i;
4323         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4324                          pipe_name(crtc->pipe));
4325
4326         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4327
4328         return pll;
4329 }
4330
4331 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4332 {
4333         struct drm_i915_private *dev_priv = to_i915(state->dev);
4334         struct intel_shared_dpll_config *shared_dpll;
4335         struct intel_shared_dpll *pll;
4336         enum intel_dpll_id i;
4337
4338         if (!to_intel_atomic_state(state)->dpll_set)
4339                 return;
4340
4341         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4342         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4343                 pll = &dev_priv->shared_dplls[i];
4344                 pll->config = shared_dpll[i];
4345         }
4346 }
4347
4348 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4349 {
4350         struct drm_i915_private *dev_priv = dev->dev_private;
4351         i915_reg_t dslreg = PIPEDSL(pipe);
4352         u32 temp;
4353
4354         temp = I915_READ(dslreg);
4355         udelay(500);
4356         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4357                 if (wait_for(I915_READ(dslreg) != temp, 5))
4358                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4359         }
4360 }
4361
4362 static int
4363 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4364                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4365                   int src_w, int src_h, int dst_w, int dst_h)
4366 {
4367         struct intel_crtc_scaler_state *scaler_state =
4368                 &crtc_state->scaler_state;
4369         struct intel_crtc *intel_crtc =
4370                 to_intel_crtc(crtc_state->base.crtc);
4371         int need_scaling;
4372
4373         need_scaling = intel_rotation_90_or_270(rotation) ?
4374                 (src_h != dst_w || src_w != dst_h):
4375                 (src_w != dst_w || src_h != dst_h);
4376
4377         /*
4378          * if plane is being disabled or scaler is no more required or force detach
4379          *  - free scaler binded to this plane/crtc
4380          *  - in order to do this, update crtc->scaler_usage
4381          *
4382          * Here scaler state in crtc_state is set free so that
4383          * scaler can be assigned to other user. Actual register
4384          * update to free the scaler is done in plane/panel-fit programming.
4385          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4386          */
4387         if (force_detach || !need_scaling) {
4388                 if (*scaler_id >= 0) {
4389                         scaler_state->scaler_users &= ~(1 << scaler_user);
4390                         scaler_state->scalers[*scaler_id].in_use = 0;
4391
4392                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4393                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4394                                 intel_crtc->pipe, scaler_user, *scaler_id,
4395                                 scaler_state->scaler_users);
4396                         *scaler_id = -1;
4397                 }
4398                 return 0;
4399         }
4400
4401         /* range checks */
4402         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4403                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4404
4405                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4406                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4407                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4408                         "size is out of scaler range\n",
4409                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4410                 return -EINVAL;
4411         }
4412
4413         /* mark this plane as a scaler user in crtc_state */
4414         scaler_state->scaler_users |= (1 << scaler_user);
4415         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4416                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4417                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4418                 scaler_state->scaler_users);
4419
4420         return 0;
4421 }
4422
4423 /**
4424  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4425  *
4426  * @state: crtc's scaler state
4427  *
4428  * Return
4429  *     0 - scaler_usage updated successfully
4430  *    error - requested scaling cannot be supported or other error condition
4431  */
4432 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4433 {
4434         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4435         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4436
4437         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4438                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4439
4440         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4441                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4442                 state->pipe_src_w, state->pipe_src_h,
4443                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4444 }
4445
4446 /**
4447  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4448  *
4449  * @state: crtc's scaler state
4450  * @plane_state: atomic plane state to update
4451  *
4452  * Return
4453  *     0 - scaler_usage updated successfully
4454  *    error - requested scaling cannot be supported or other error condition
4455  */
4456 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4457                                    struct intel_plane_state *plane_state)
4458 {
4459
4460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4461         struct intel_plane *intel_plane =
4462                 to_intel_plane(plane_state->base.plane);
4463         struct drm_framebuffer *fb = plane_state->base.fb;
4464         int ret;
4465
4466         bool force_detach = !fb || !plane_state->visible;
4467
4468         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4469                       intel_plane->base.base.id, intel_crtc->pipe,
4470                       drm_plane_index(&intel_plane->base));
4471
4472         ret = skl_update_scaler(crtc_state, force_detach,
4473                                 drm_plane_index(&intel_plane->base),
4474                                 &plane_state->scaler_id,
4475                                 plane_state->base.rotation,
4476                                 drm_rect_width(&plane_state->src) >> 16,
4477                                 drm_rect_height(&plane_state->src) >> 16,
4478                                 drm_rect_width(&plane_state->dst),
4479                                 drm_rect_height(&plane_state->dst));
4480
4481         if (ret || plane_state->scaler_id < 0)
4482                 return ret;
4483
4484         /* check colorkey */
4485         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4486                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4487                               intel_plane->base.base.id);
4488                 return -EINVAL;
4489         }
4490
4491         /* Check src format */
4492         switch (fb->pixel_format) {
4493         case DRM_FORMAT_RGB565:
4494         case DRM_FORMAT_XBGR8888:
4495         case DRM_FORMAT_XRGB8888:
4496         case DRM_FORMAT_ABGR8888:
4497         case DRM_FORMAT_ARGB8888:
4498         case DRM_FORMAT_XRGB2101010:
4499         case DRM_FORMAT_XBGR2101010:
4500         case DRM_FORMAT_YUYV:
4501         case DRM_FORMAT_YVYU:
4502         case DRM_FORMAT_UYVY:
4503         case DRM_FORMAT_VYUY:
4504                 break;
4505         default:
4506                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4507                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4508                 return -EINVAL;
4509         }
4510
4511         return 0;
4512 }
4513
4514 static void skylake_scaler_disable(struct intel_crtc *crtc)
4515 {
4516         int i;
4517
4518         for (i = 0; i < crtc->num_scalers; i++)
4519                 skl_detach_scaler(crtc, i);
4520 }
4521
4522 static void skylake_pfit_enable(struct intel_crtc *crtc)
4523 {
4524         struct drm_device *dev = crtc->base.dev;
4525         struct drm_i915_private *dev_priv = dev->dev_private;
4526         int pipe = crtc->pipe;
4527         struct intel_crtc_scaler_state *scaler_state =
4528                 &crtc->config->scaler_state;
4529
4530         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4531
4532         if (crtc->config->pch_pfit.enabled) {
4533                 int id;
4534
4535                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4536                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4537                         return;
4538                 }
4539
4540                 id = scaler_state->scaler_id;
4541                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4542                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4543                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4544                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4545
4546                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4547         }
4548 }
4549
4550 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4551 {
4552         struct drm_device *dev = crtc->base.dev;
4553         struct drm_i915_private *dev_priv = dev->dev_private;
4554         int pipe = crtc->pipe;
4555
4556         if (crtc->config->pch_pfit.enabled) {
4557                 /* Force use of hard-coded filter coefficients
4558                  * as some pre-programmed values are broken,
4559                  * e.g. x201.
4560                  */
4561                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4562                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4563                                                  PF_PIPE_SEL_IVB(pipe));
4564                 else
4565                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4566                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4567                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4568         }
4569 }
4570
4571 void hsw_enable_ips(struct intel_crtc *crtc)
4572 {
4573         struct drm_device *dev = crtc->base.dev;
4574         struct drm_i915_private *dev_priv = dev->dev_private;
4575
4576         if (!crtc->config->ips_enabled)
4577                 return;
4578
4579         /* We can only enable IPS after we enable a plane and wait for a vblank */
4580         intel_wait_for_vblank(dev, crtc->pipe);
4581
4582         assert_plane_enabled(dev_priv, crtc->plane);
4583         if (IS_BROADWELL(dev)) {
4584                 mutex_lock(&dev_priv->rps.hw_lock);
4585                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4586                 mutex_unlock(&dev_priv->rps.hw_lock);
4587                 /* Quoting Art Runyan: "its not safe to expect any particular
4588                  * value in IPS_CTL bit 31 after enabling IPS through the
4589                  * mailbox." Moreover, the mailbox may return a bogus state,
4590                  * so we need to just enable it and continue on.
4591                  */
4592         } else {
4593                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4594                 /* The bit only becomes 1 in the next vblank, so this wait here
4595                  * is essentially intel_wait_for_vblank. If we don't have this
4596                  * and don't wait for vblanks until the end of crtc_enable, then
4597                  * the HW state readout code will complain that the expected
4598                  * IPS_CTL value is not the one we read. */
4599                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4600                         DRM_ERROR("Timed out waiting for IPS enable\n");
4601         }
4602 }
4603
4604 void hsw_disable_ips(struct intel_crtc *crtc)
4605 {
4606         struct drm_device *dev = crtc->base.dev;
4607         struct drm_i915_private *dev_priv = dev->dev_private;
4608
4609         if (!crtc->config->ips_enabled)
4610                 return;
4611
4612         assert_plane_enabled(dev_priv, crtc->plane);
4613         if (IS_BROADWELL(dev)) {
4614                 mutex_lock(&dev_priv->rps.hw_lock);
4615                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4616                 mutex_unlock(&dev_priv->rps.hw_lock);
4617                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4618                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4619                         DRM_ERROR("Timed out waiting for IPS disable\n");
4620         } else {
4621                 I915_WRITE(IPS_CTL, 0);
4622                 POSTING_READ(IPS_CTL);
4623         }
4624
4625         /* We need to wait for a vblank before we can disable the plane. */
4626         intel_wait_for_vblank(dev, crtc->pipe);
4627 }
4628
4629 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4630 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4631 {
4632         struct drm_device *dev = crtc->dev;
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4635         enum pipe pipe = intel_crtc->pipe;
4636         int i;
4637         bool reenable_ips = false;
4638
4639         /* The clocks have to be on to load the palette. */
4640         if (!crtc->state->active)
4641                 return;
4642
4643         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4644                 if (intel_crtc->config->has_dsi_encoder)
4645                         assert_dsi_pll_enabled(dev_priv);
4646                 else
4647                         assert_pll_enabled(dev_priv, pipe);
4648         }
4649
4650         /* Workaround : Do not read or write the pipe palette/gamma data while
4651          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4652          */
4653         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4654             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4655              GAMMA_MODE_MODE_SPLIT)) {
4656                 hsw_disable_ips(intel_crtc);
4657                 reenable_ips = true;
4658         }
4659
4660         for (i = 0; i < 256; i++) {
4661                 i915_reg_t palreg;
4662
4663                 if (HAS_GMCH_DISPLAY(dev))
4664                         palreg = PALETTE(pipe, i);
4665                 else
4666                         palreg = LGC_PALETTE(pipe, i);
4667
4668                 I915_WRITE(palreg,
4669                            (intel_crtc->lut_r[i] << 16) |
4670                            (intel_crtc->lut_g[i] << 8) |
4671                            intel_crtc->lut_b[i]);
4672         }
4673
4674         if (reenable_ips)
4675                 hsw_enable_ips(intel_crtc);
4676 }
4677
4678 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4679 {
4680         if (intel_crtc->overlay) {
4681                 struct drm_device *dev = intel_crtc->base.dev;
4682                 struct drm_i915_private *dev_priv = dev->dev_private;
4683
4684                 mutex_lock(&dev->struct_mutex);
4685                 dev_priv->mm.interruptible = false;
4686                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4687                 dev_priv->mm.interruptible = true;
4688                 mutex_unlock(&dev->struct_mutex);
4689         }
4690
4691         /* Let userspace switch the overlay on again. In most cases userspace
4692          * has to recompute where to put it anyway.
4693          */
4694 }
4695
4696 /**
4697  * intel_post_enable_primary - Perform operations after enabling primary plane
4698  * @crtc: the CRTC whose primary plane was just enabled
4699  *
4700  * Performs potentially sleeping operations that must be done after the primary
4701  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4702  * called due to an explicit primary plane update, or due to an implicit
4703  * re-enable that is caused when a sprite plane is updated to no longer
4704  * completely hide the primary plane.
4705  */
4706 static void
4707 intel_post_enable_primary(struct drm_crtc *crtc)
4708 {
4709         struct drm_device *dev = crtc->dev;
4710         struct drm_i915_private *dev_priv = dev->dev_private;
4711         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712         int pipe = intel_crtc->pipe;
4713
4714         /*
4715          * FIXME IPS should be fine as long as one plane is
4716          * enabled, but in practice it seems to have problems
4717          * when going from primary only to sprite only and vice
4718          * versa.
4719          */
4720         hsw_enable_ips(intel_crtc);
4721
4722         /*
4723          * Gen2 reports pipe underruns whenever all planes are disabled.
4724          * So don't enable underrun reporting before at least some planes
4725          * are enabled.
4726          * FIXME: Need to fix the logic to work when we turn off all planes
4727          * but leave the pipe running.
4728          */
4729         if (IS_GEN2(dev))
4730                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4731
4732         /* Underruns don't always raise interrupts, so check manually. */
4733         intel_check_cpu_fifo_underruns(dev_priv);
4734         intel_check_pch_fifo_underruns(dev_priv);
4735 }
4736
4737 /**
4738  * intel_pre_disable_primary - Perform operations before disabling primary plane
4739  * @crtc: the CRTC whose primary plane is to be disabled
4740  *
4741  * Performs potentially sleeping operations that must be done before the
4742  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4743  * be called due to an explicit primary plane update, or due to an implicit
4744  * disable that is caused when a sprite plane completely hides the primary
4745  * plane.
4746  */
4747 static void
4748 intel_pre_disable_primary(struct drm_crtc *crtc)
4749 {
4750         struct drm_device *dev = crtc->dev;
4751         struct drm_i915_private *dev_priv = dev->dev_private;
4752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4753         int pipe = intel_crtc->pipe;
4754
4755         /*
4756          * Gen2 reports pipe underruns whenever all planes are disabled.
4757          * So diasble underrun reporting before all the planes get disabled.
4758          * FIXME: Need to fix the logic to work when we turn off all planes
4759          * but leave the pipe running.
4760          */
4761         if (IS_GEN2(dev))
4762                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4763
4764         /*
4765          * Vblank time updates from the shadow to live plane control register
4766          * are blocked if the memory self-refresh mode is active at that
4767          * moment. So to make sure the plane gets truly disabled, disable
4768          * first the self-refresh mode. The self-refresh enable bit in turn
4769          * will be checked/applied by the HW only at the next frame start
4770          * event which is after the vblank start event, so we need to have a
4771          * wait-for-vblank between disabling the plane and the pipe.
4772          */
4773         if (HAS_GMCH_DISPLAY(dev)) {
4774                 intel_set_memory_cxsr(dev_priv, false);
4775                 dev_priv->wm.vlv.cxsr = false;
4776                 intel_wait_for_vblank(dev, pipe);
4777         }
4778
4779         /*
4780          * FIXME IPS should be fine as long as one plane is
4781          * enabled, but in practice it seems to have problems
4782          * when going from primary only to sprite only and vice
4783          * versa.
4784          */
4785         hsw_disable_ips(intel_crtc);
4786 }
4787
4788 static void intel_post_plane_update(struct intel_crtc *crtc)
4789 {
4790         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4791         struct intel_crtc_state *pipe_config =
4792                 to_intel_crtc_state(crtc->base.state);
4793         struct drm_device *dev = crtc->base.dev;
4794
4795         if (atomic->wait_vblank)
4796                 intel_wait_for_vblank(dev, crtc->pipe);
4797
4798         intel_frontbuffer_flip(dev, atomic->fb_bits);
4799
4800         crtc->wm.cxsr_allowed = true;
4801
4802         if (pipe_config->wm_changed && pipe_config->base.active)
4803                 intel_update_watermarks(&crtc->base);
4804
4805         if (atomic->update_fbc)
4806                 intel_fbc_update(crtc);
4807
4808         if (atomic->post_enable_primary)
4809                 intel_post_enable_primary(&crtc->base);
4810
4811         memset(atomic, 0, sizeof(*atomic));
4812 }
4813
4814 static void intel_pre_plane_update(struct intel_crtc *crtc)
4815 {
4816         struct drm_device *dev = crtc->base.dev;
4817         struct drm_i915_private *dev_priv = dev->dev_private;
4818         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4819         struct intel_crtc_state *pipe_config =
4820                 to_intel_crtc_state(crtc->base.state);
4821
4822         if (atomic->disable_fbc)
4823                 intel_fbc_deactivate(crtc);
4824
4825         if (crtc->atomic.disable_ips)
4826                 hsw_disable_ips(crtc);
4827
4828         if (atomic->pre_disable_primary)
4829                 intel_pre_disable_primary(&crtc->base);
4830
4831         if (pipe_config->disable_cxsr) {
4832                 crtc->wm.cxsr_allowed = false;
4833                 intel_set_memory_cxsr(dev_priv, false);
4834         }
4835
4836         if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
4837                 intel_update_watermarks(&crtc->base);
4838 }
4839
4840 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4841 {
4842         struct drm_device *dev = crtc->dev;
4843         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4844         struct drm_plane *p;
4845         int pipe = intel_crtc->pipe;
4846
4847         intel_crtc_dpms_overlay_disable(intel_crtc);
4848
4849         drm_for_each_plane_mask(p, dev, plane_mask)
4850                 to_intel_plane(p)->disable_plane(p, crtc);
4851
4852         /*
4853          * FIXME: Once we grow proper nuclear flip support out of this we need
4854          * to compute the mask of flip planes precisely. For the time being
4855          * consider this a flip to a NULL plane.
4856          */
4857         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4858 }
4859
4860 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4861 {
4862         struct drm_device *dev = crtc->dev;
4863         struct drm_i915_private *dev_priv = dev->dev_private;
4864         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4865         struct intel_encoder *encoder;
4866         int pipe = intel_crtc->pipe;
4867
4868         if (WARN_ON(intel_crtc->active))
4869                 return;
4870
4871         if (intel_crtc->config->has_pch_encoder)
4872                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4873
4874         if (intel_crtc->config->has_pch_encoder)
4875                 intel_prepare_shared_dpll(intel_crtc);
4876
4877         if (intel_crtc->config->has_dp_encoder)
4878                 intel_dp_set_m_n(intel_crtc, M1_N1);
4879
4880         intel_set_pipe_timings(intel_crtc);
4881
4882         if (intel_crtc->config->has_pch_encoder) {
4883                 intel_cpu_transcoder_set_m_n(intel_crtc,
4884                                      &intel_crtc->config->fdi_m_n, NULL);
4885         }
4886
4887         ironlake_set_pipeconf(crtc);
4888
4889         intel_crtc->active = true;
4890
4891         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4892
4893         for_each_encoder_on_crtc(dev, crtc, encoder)
4894                 if (encoder->pre_enable)
4895                         encoder->pre_enable(encoder);
4896
4897         if (intel_crtc->config->has_pch_encoder) {
4898                 /* Note: FDI PLL enabling _must_ be done before we enable the
4899                  * cpu pipes, hence this is separate from all the other fdi/pch
4900                  * enabling. */
4901                 ironlake_fdi_pll_enable(intel_crtc);
4902         } else {
4903                 assert_fdi_tx_disabled(dev_priv, pipe);
4904                 assert_fdi_rx_disabled(dev_priv, pipe);
4905         }
4906
4907         ironlake_pfit_enable(intel_crtc);
4908
4909         /*
4910          * On ILK+ LUT must be loaded before the pipe is running but with
4911          * clocks enabled
4912          */
4913         intel_crtc_load_lut(crtc);
4914
4915         intel_update_watermarks(crtc);
4916         intel_enable_pipe(intel_crtc);
4917
4918         if (intel_crtc->config->has_pch_encoder)
4919                 ironlake_pch_enable(crtc);
4920
4921         assert_vblank_disabled(crtc);
4922         drm_crtc_vblank_on(crtc);
4923
4924         for_each_encoder_on_crtc(dev, crtc, encoder)
4925                 encoder->enable(encoder);
4926
4927         if (HAS_PCH_CPT(dev))
4928                 cpt_verify_modeset(dev, intel_crtc->pipe);
4929
4930         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4931         if (intel_crtc->config->has_pch_encoder)
4932                 intel_wait_for_vblank(dev, pipe);
4933         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4934
4935         intel_fbc_enable(intel_crtc);
4936 }
4937
4938 /* IPS only exists on ULT machines and is tied to pipe A. */
4939 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4940 {
4941         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4942 }
4943
4944 static void haswell_crtc_enable(struct drm_crtc *crtc)
4945 {
4946         struct drm_device *dev = crtc->dev;
4947         struct drm_i915_private *dev_priv = dev->dev_private;
4948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4949         struct intel_encoder *encoder;
4950         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4951         struct intel_crtc_state *pipe_config =
4952                 to_intel_crtc_state(crtc->state);
4953
4954         if (WARN_ON(intel_crtc->active))
4955                 return;
4956
4957         if (intel_crtc->config->has_pch_encoder)
4958                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4959                                                       false);
4960
4961         if (intel_crtc_to_shared_dpll(intel_crtc))
4962                 intel_enable_shared_dpll(intel_crtc);
4963
4964         if (intel_crtc->config->has_dp_encoder)
4965                 intel_dp_set_m_n(intel_crtc, M1_N1);
4966
4967         intel_set_pipe_timings(intel_crtc);
4968
4969         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4970                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4971                            intel_crtc->config->pixel_multiplier - 1);
4972         }
4973
4974         if (intel_crtc->config->has_pch_encoder) {
4975                 intel_cpu_transcoder_set_m_n(intel_crtc,
4976                                      &intel_crtc->config->fdi_m_n, NULL);
4977         }
4978
4979         haswell_set_pipeconf(crtc);
4980
4981         intel_set_pipe_csc(crtc);
4982
4983         intel_crtc->active = true;
4984
4985         if (intel_crtc->config->has_pch_encoder)
4986                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4987         else
4988                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4989
4990         for_each_encoder_on_crtc(dev, crtc, encoder) {
4991                 if (encoder->pre_enable)
4992                         encoder->pre_enable(encoder);
4993         }
4994
4995         if (intel_crtc->config->has_pch_encoder)
4996                 dev_priv->display.fdi_link_train(crtc);
4997
4998         if (!intel_crtc->config->has_dsi_encoder)
4999                 intel_ddi_enable_pipe_clock(intel_crtc);
5000
5001         if (INTEL_INFO(dev)->gen >= 9)
5002                 skylake_pfit_enable(intel_crtc);
5003         else
5004                 ironlake_pfit_enable(intel_crtc);
5005
5006         /*
5007          * On ILK+ LUT must be loaded before the pipe is running but with
5008          * clocks enabled
5009          */
5010         intel_crtc_load_lut(crtc);
5011
5012         intel_ddi_set_pipe_settings(crtc);
5013         if (!intel_crtc->config->has_dsi_encoder)
5014                 intel_ddi_enable_transcoder_func(crtc);
5015
5016         intel_update_watermarks(crtc);
5017         intel_enable_pipe(intel_crtc);
5018
5019         if (intel_crtc->config->has_pch_encoder)
5020                 lpt_pch_enable(crtc);
5021
5022         if (intel_crtc->config->dp_encoder_is_mst)
5023                 intel_ddi_set_vc_payload_alloc(crtc, true);
5024
5025         assert_vblank_disabled(crtc);
5026         drm_crtc_vblank_on(crtc);
5027
5028         for_each_encoder_on_crtc(dev, crtc, encoder) {
5029                 encoder->enable(encoder);
5030                 intel_opregion_notify_encoder(encoder, true);
5031         }
5032
5033         if (intel_crtc->config->has_pch_encoder) {
5034                 intel_wait_for_vblank(dev, pipe);
5035                 intel_wait_for_vblank(dev, pipe);
5036                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5037                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5038                                                       true);
5039         }
5040
5041         /* If we change the relative order between pipe/planes enabling, we need
5042          * to change the workaround. */
5043         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5044         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5045                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5046                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5047         }
5048
5049         intel_fbc_enable(intel_crtc);
5050 }
5051
5052 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5053 {
5054         struct drm_device *dev = crtc->base.dev;
5055         struct drm_i915_private *dev_priv = dev->dev_private;
5056         int pipe = crtc->pipe;
5057
5058         /* To avoid upsetting the power well on haswell only disable the pfit if
5059          * it's in use. The hw state code will make sure we get this right. */
5060         if (force || crtc->config->pch_pfit.enabled) {
5061                 I915_WRITE(PF_CTL(pipe), 0);
5062                 I915_WRITE(PF_WIN_POS(pipe), 0);
5063                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5064         }
5065 }
5066
5067 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5068 {
5069         struct drm_device *dev = crtc->dev;
5070         struct drm_i915_private *dev_priv = dev->dev_private;
5071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5072         struct intel_encoder *encoder;
5073         int pipe = intel_crtc->pipe;
5074
5075         if (intel_crtc->config->has_pch_encoder)
5076                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5077
5078         for_each_encoder_on_crtc(dev, crtc, encoder)
5079                 encoder->disable(encoder);
5080
5081         drm_crtc_vblank_off(crtc);
5082         assert_vblank_disabled(crtc);
5083
5084         /*
5085          * Sometimes spurious CPU pipe underruns happen when the
5086          * pipe is already disabled, but FDI RX/TX is still enabled.
5087          * Happens at least with VGA+HDMI cloning. Suppress them.
5088          */
5089         if (intel_crtc->config->has_pch_encoder)
5090                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5091
5092         intel_disable_pipe(intel_crtc);
5093
5094         ironlake_pfit_disable(intel_crtc, false);
5095
5096         if (intel_crtc->config->has_pch_encoder) {
5097                 ironlake_fdi_disable(crtc);
5098                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5099         }
5100
5101         for_each_encoder_on_crtc(dev, crtc, encoder)
5102                 if (encoder->post_disable)
5103                         encoder->post_disable(encoder);
5104
5105         if (intel_crtc->config->has_pch_encoder) {
5106                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5107
5108                 if (HAS_PCH_CPT(dev)) {
5109                         i915_reg_t reg;
5110                         u32 temp;
5111
5112                         /* disable TRANS_DP_CTL */
5113                         reg = TRANS_DP_CTL(pipe);
5114                         temp = I915_READ(reg);
5115                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5116                                   TRANS_DP_PORT_SEL_MASK);
5117                         temp |= TRANS_DP_PORT_SEL_NONE;
5118                         I915_WRITE(reg, temp);
5119
5120                         /* disable DPLL_SEL */
5121                         temp = I915_READ(PCH_DPLL_SEL);
5122                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5123                         I915_WRITE(PCH_DPLL_SEL, temp);
5124                 }
5125
5126                 ironlake_fdi_pll_disable(intel_crtc);
5127         }
5128
5129         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5130
5131         intel_fbc_disable_crtc(intel_crtc);
5132 }
5133
5134 static void haswell_crtc_disable(struct drm_crtc *crtc)
5135 {
5136         struct drm_device *dev = crtc->dev;
5137         struct drm_i915_private *dev_priv = dev->dev_private;
5138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5139         struct intel_encoder *encoder;
5140         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5141
5142         if (intel_crtc->config->has_pch_encoder)
5143                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5144                                                       false);
5145
5146         for_each_encoder_on_crtc(dev, crtc, encoder) {
5147                 intel_opregion_notify_encoder(encoder, false);
5148                 encoder->disable(encoder);
5149         }
5150
5151         drm_crtc_vblank_off(crtc);
5152         assert_vblank_disabled(crtc);
5153
5154         intel_disable_pipe(intel_crtc);
5155
5156         if (intel_crtc->config->dp_encoder_is_mst)
5157                 intel_ddi_set_vc_payload_alloc(crtc, false);
5158
5159         if (!intel_crtc->config->has_dsi_encoder)
5160                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5161
5162         if (INTEL_INFO(dev)->gen >= 9)
5163                 skylake_scaler_disable(intel_crtc);
5164         else
5165                 ironlake_pfit_disable(intel_crtc, false);
5166
5167         if (!intel_crtc->config->has_dsi_encoder)
5168                 intel_ddi_disable_pipe_clock(intel_crtc);
5169
5170         for_each_encoder_on_crtc(dev, crtc, encoder)
5171                 if (encoder->post_disable)
5172                         encoder->post_disable(encoder);
5173
5174         if (intel_crtc->config->has_pch_encoder) {
5175                 lpt_disable_pch_transcoder(dev_priv);
5176                 lpt_disable_iclkip(dev_priv);
5177                 intel_ddi_fdi_disable(crtc);
5178
5179                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5180                                                       true);
5181         }
5182
5183         intel_fbc_disable_crtc(intel_crtc);
5184 }
5185
5186 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5187 {
5188         struct drm_device *dev = crtc->base.dev;
5189         struct drm_i915_private *dev_priv = dev->dev_private;
5190         struct intel_crtc_state *pipe_config = crtc->config;
5191
5192         if (!pipe_config->gmch_pfit.control)
5193                 return;
5194
5195         /*
5196          * The panel fitter should only be adjusted whilst the pipe is disabled,
5197          * according to register description and PRM.
5198          */
5199         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5200         assert_pipe_disabled(dev_priv, crtc->pipe);
5201
5202         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5203         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5204
5205         /* Border color in case we don't scale up to the full screen. Black by
5206          * default, change to something else for debugging. */
5207         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5208 }
5209
5210 static enum intel_display_power_domain port_to_power_domain(enum port port)
5211 {
5212         switch (port) {
5213         case PORT_A:
5214                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5215         case PORT_B:
5216                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5217         case PORT_C:
5218                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5219         case PORT_D:
5220                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5221         case PORT_E:
5222                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5223         default:
5224                 MISSING_CASE(port);
5225                 return POWER_DOMAIN_PORT_OTHER;
5226         }
5227 }
5228
5229 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5230 {
5231         switch (port) {
5232         case PORT_A:
5233                 return POWER_DOMAIN_AUX_A;
5234         case PORT_B:
5235                 return POWER_DOMAIN_AUX_B;
5236         case PORT_C:
5237                 return POWER_DOMAIN_AUX_C;
5238         case PORT_D:
5239                 return POWER_DOMAIN_AUX_D;
5240         case PORT_E:
5241                 /* FIXME: Check VBT for actual wiring of PORT E */
5242                 return POWER_DOMAIN_AUX_D;
5243         default:
5244                 MISSING_CASE(port);
5245                 return POWER_DOMAIN_AUX_A;
5246         }
5247 }
5248
5249 enum intel_display_power_domain
5250 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5251 {
5252         struct drm_device *dev = intel_encoder->base.dev;
5253         struct intel_digital_port *intel_dig_port;
5254
5255         switch (intel_encoder->type) {
5256         case INTEL_OUTPUT_UNKNOWN:
5257                 /* Only DDI platforms should ever use this output type */
5258                 WARN_ON_ONCE(!HAS_DDI(dev));
5259         case INTEL_OUTPUT_DISPLAYPORT:
5260         case INTEL_OUTPUT_HDMI:
5261         case INTEL_OUTPUT_EDP:
5262                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5263                 return port_to_power_domain(intel_dig_port->port);
5264         case INTEL_OUTPUT_DP_MST:
5265                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5266                 return port_to_power_domain(intel_dig_port->port);
5267         case INTEL_OUTPUT_ANALOG:
5268                 return POWER_DOMAIN_PORT_CRT;
5269         case INTEL_OUTPUT_DSI:
5270                 return POWER_DOMAIN_PORT_DSI;
5271         default:
5272                 return POWER_DOMAIN_PORT_OTHER;
5273         }
5274 }
5275
5276 enum intel_display_power_domain
5277 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5278 {
5279         struct drm_device *dev = intel_encoder->base.dev;
5280         struct intel_digital_port *intel_dig_port;
5281
5282         switch (intel_encoder->type) {
5283         case INTEL_OUTPUT_UNKNOWN:
5284         case INTEL_OUTPUT_HDMI:
5285                 /*
5286                  * Only DDI platforms should ever use these output types.
5287                  * We can get here after the HDMI detect code has already set
5288                  * the type of the shared encoder. Since we can't be sure
5289                  * what's the status of the given connectors, play safe and
5290                  * run the DP detection too.
5291                  */
5292                 WARN_ON_ONCE(!HAS_DDI(dev));
5293         case INTEL_OUTPUT_DISPLAYPORT:
5294         case INTEL_OUTPUT_EDP:
5295                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5296                 return port_to_aux_power_domain(intel_dig_port->port);
5297         case INTEL_OUTPUT_DP_MST:
5298                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5299                 return port_to_aux_power_domain(intel_dig_port->port);
5300         default:
5301                 MISSING_CASE(intel_encoder->type);
5302                 return POWER_DOMAIN_AUX_A;
5303         }
5304 }
5305
5306 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5307 {
5308         struct drm_device *dev = crtc->dev;
5309         struct intel_encoder *intel_encoder;
5310         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5311         enum pipe pipe = intel_crtc->pipe;
5312         unsigned long mask;
5313         enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5314
5315         if (!crtc->state->active)
5316                 return 0;
5317
5318         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5319         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5320         if (intel_crtc->config->pch_pfit.enabled ||
5321             intel_crtc->config->pch_pfit.force_thru)
5322                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5323
5324         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5325                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5326
5327         return mask;
5328 }
5329
5330 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5331 {
5332         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5334         enum intel_display_power_domain domain;
5335         unsigned long domains, new_domains, old_domains;
5336
5337         old_domains = intel_crtc->enabled_power_domains;
5338         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5339
5340         domains = new_domains & ~old_domains;
5341
5342         for_each_power_domain(domain, domains)
5343                 intel_display_power_get(dev_priv, domain);
5344
5345         return old_domains & ~new_domains;
5346 }
5347
5348 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5349                                       unsigned long domains)
5350 {
5351         enum intel_display_power_domain domain;
5352
5353         for_each_power_domain(domain, domains)
5354                 intel_display_power_put(dev_priv, domain);
5355 }
5356
5357 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5358 {
5359         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5360         struct drm_device *dev = state->dev;
5361         struct drm_i915_private *dev_priv = dev->dev_private;
5362         unsigned long put_domains[I915_MAX_PIPES] = {};
5363         struct drm_crtc_state *crtc_state;
5364         struct drm_crtc *crtc;
5365         int i;
5366
5367         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5368                 if (needs_modeset(crtc->state))
5369                         put_domains[to_intel_crtc(crtc)->pipe] =
5370                                 modeset_get_crtc_power_domains(crtc);
5371         }
5372
5373         if (dev_priv->display.modeset_commit_cdclk &&
5374             intel_state->dev_cdclk != dev_priv->cdclk_freq)
5375                 dev_priv->display.modeset_commit_cdclk(state);
5376
5377         for (i = 0; i < I915_MAX_PIPES; i++)
5378                 if (put_domains[i])
5379                         modeset_put_power_domains(dev_priv, put_domains[i]);
5380 }
5381
5382 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5383 {
5384         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5385
5386         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5387             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5388                 return max_cdclk_freq;
5389         else if (IS_CHERRYVIEW(dev_priv))
5390                 return max_cdclk_freq*95/100;
5391         else if (INTEL_INFO(dev_priv)->gen < 4)
5392                 return 2*max_cdclk_freq*90/100;
5393         else
5394                 return max_cdclk_freq*90/100;
5395 }
5396
5397 static void intel_update_max_cdclk(struct drm_device *dev)
5398 {
5399         struct drm_i915_private *dev_priv = dev->dev_private;
5400
5401         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5402                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5403
5404                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5405                         dev_priv->max_cdclk_freq = 675000;
5406                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5407                         dev_priv->max_cdclk_freq = 540000;
5408                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5409                         dev_priv->max_cdclk_freq = 450000;
5410                 else
5411                         dev_priv->max_cdclk_freq = 337500;
5412         } else if (IS_BROADWELL(dev))  {
5413                 /*
5414                  * FIXME with extra cooling we can allow
5415                  * 540 MHz for ULX and 675 Mhz for ULT.
5416                  * How can we know if extra cooling is
5417                  * available? PCI ID, VTB, something else?
5418                  */
5419                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5420                         dev_priv->max_cdclk_freq = 450000;
5421                 else if (IS_BDW_ULX(dev))
5422                         dev_priv->max_cdclk_freq = 450000;
5423                 else if (IS_BDW_ULT(dev))
5424                         dev_priv->max_cdclk_freq = 540000;
5425                 else
5426                         dev_priv->max_cdclk_freq = 675000;
5427         } else if (IS_CHERRYVIEW(dev)) {
5428                 dev_priv->max_cdclk_freq = 320000;
5429         } else if (IS_VALLEYVIEW(dev)) {
5430                 dev_priv->max_cdclk_freq = 400000;
5431         } else {
5432                 /* otherwise assume cdclk is fixed */
5433                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5434         }
5435
5436         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5437
5438         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5439                          dev_priv->max_cdclk_freq);
5440
5441         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5442                          dev_priv->max_dotclk_freq);
5443 }
5444
5445 static void intel_update_cdclk(struct drm_device *dev)
5446 {
5447         struct drm_i915_private *dev_priv = dev->dev_private;
5448
5449         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5450         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5451                          dev_priv->cdclk_freq);
5452
5453         /*
5454          * Program the gmbus_freq based on the cdclk frequency.
5455          * BSpec erroneously claims we should aim for 4MHz, but
5456          * in fact 1MHz is the correct frequency.
5457          */
5458         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5459                 /*
5460                  * Program the gmbus_freq based on the cdclk frequency.
5461                  * BSpec erroneously claims we should aim for 4MHz, but
5462                  * in fact 1MHz is the correct frequency.
5463                  */
5464                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5465         }
5466
5467         if (dev_priv->max_cdclk_freq == 0)
5468                 intel_update_max_cdclk(dev);
5469 }
5470
5471 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5472 {
5473         struct drm_i915_private *dev_priv = dev->dev_private;
5474         uint32_t divider;
5475         uint32_t ratio;
5476         uint32_t current_freq;
5477         int ret;
5478
5479         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5480         switch (frequency) {
5481         case 144000:
5482                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5483                 ratio = BXT_DE_PLL_RATIO(60);
5484                 break;
5485         case 288000:
5486                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5487                 ratio = BXT_DE_PLL_RATIO(60);
5488                 break;
5489         case 384000:
5490                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5491                 ratio = BXT_DE_PLL_RATIO(60);
5492                 break;
5493         case 576000:
5494                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5495                 ratio = BXT_DE_PLL_RATIO(60);
5496                 break;
5497         case 624000:
5498                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5499                 ratio = BXT_DE_PLL_RATIO(65);
5500                 break;
5501         case 19200:
5502                 /*
5503                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5504                  * to suppress GCC warning.
5505                  */
5506                 ratio = 0;
5507                 divider = 0;
5508                 break;
5509         default:
5510                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5511
5512                 return;
5513         }
5514
5515         mutex_lock(&dev_priv->rps.hw_lock);
5516         /* Inform power controller of upcoming frequency change */
5517         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5518                                       0x80000000);
5519         mutex_unlock(&dev_priv->rps.hw_lock);
5520
5521         if (ret) {
5522                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5523                           ret, frequency);
5524                 return;
5525         }
5526
5527         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5528         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5529         current_freq = current_freq * 500 + 1000;
5530
5531         /*
5532          * DE PLL has to be disabled when
5533          * - setting to 19.2MHz (bypass, PLL isn't used)
5534          * - before setting to 624MHz (PLL needs toggling)
5535          * - before setting to any frequency from 624MHz (PLL needs toggling)
5536          */
5537         if (frequency == 19200 || frequency == 624000 ||
5538             current_freq == 624000) {
5539                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5540                 /* Timeout 200us */
5541                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5542                              1))
5543                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5544         }
5545
5546         if (frequency != 19200) {
5547                 uint32_t val;
5548
5549                 val = I915_READ(BXT_DE_PLL_CTL);
5550                 val &= ~BXT_DE_PLL_RATIO_MASK;
5551                 val |= ratio;
5552                 I915_WRITE(BXT_DE_PLL_CTL, val);
5553
5554                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5555                 /* Timeout 200us */
5556                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5557                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5558
5559                 val = I915_READ(CDCLK_CTL);
5560                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5561                 val |= divider;
5562                 /*
5563                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5564                  * enable otherwise.
5565                  */
5566                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5567                 if (frequency >= 500000)
5568                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5569
5570                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5571                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5572                 val |= (frequency - 1000) / 500;
5573                 I915_WRITE(CDCLK_CTL, val);
5574         }
5575
5576         mutex_lock(&dev_priv->rps.hw_lock);
5577         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5578                                       DIV_ROUND_UP(frequency, 25000));
5579         mutex_unlock(&dev_priv->rps.hw_lock);
5580
5581         if (ret) {
5582                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5583                           ret, frequency);
5584                 return;
5585         }
5586
5587         intel_update_cdclk(dev);
5588 }
5589
5590 void broxton_init_cdclk(struct drm_device *dev)
5591 {
5592         struct drm_i915_private *dev_priv = dev->dev_private;
5593         uint32_t val;
5594
5595         /*
5596          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5597          * or else the reset will hang because there is no PCH to respond.
5598          * Move the handshake programming to initialization sequence.
5599          * Previously was left up to BIOS.
5600          */
5601         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5602         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5603         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5604
5605         /* Enable PG1 for cdclk */
5606         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5607
5608         /* check if cd clock is enabled */
5609         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5610                 DRM_DEBUG_KMS("Display already initialized\n");
5611                 return;
5612         }
5613
5614         /*
5615          * FIXME:
5616          * - The initial CDCLK needs to be read from VBT.
5617          *   Need to make this change after VBT has changes for BXT.
5618          * - check if setting the max (or any) cdclk freq is really necessary
5619          *   here, it belongs to modeset time
5620          */
5621         broxton_set_cdclk(dev, 624000);
5622
5623         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5624         POSTING_READ(DBUF_CTL);
5625
5626         udelay(10);
5627
5628         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5629                 DRM_ERROR("DBuf power enable timeout!\n");
5630 }
5631
5632 void broxton_uninit_cdclk(struct drm_device *dev)
5633 {
5634         struct drm_i915_private *dev_priv = dev->dev_private;
5635
5636         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5637         POSTING_READ(DBUF_CTL);
5638
5639         udelay(10);
5640
5641         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5642                 DRM_ERROR("DBuf power disable timeout!\n");
5643
5644         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5645         broxton_set_cdclk(dev, 19200);
5646
5647         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5648 }
5649
5650 static const struct skl_cdclk_entry {
5651         unsigned int freq;
5652         unsigned int vco;
5653 } skl_cdclk_frequencies[] = {
5654         { .freq = 308570, .vco = 8640 },
5655         { .freq = 337500, .vco = 8100 },
5656         { .freq = 432000, .vco = 8640 },
5657         { .freq = 450000, .vco = 8100 },
5658         { .freq = 540000, .vco = 8100 },
5659         { .freq = 617140, .vco = 8640 },
5660         { .freq = 675000, .vco = 8100 },
5661 };
5662
5663 static unsigned int skl_cdclk_decimal(unsigned int freq)
5664 {
5665         return (freq - 1000) / 500;
5666 }
5667
5668 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5669 {
5670         unsigned int i;
5671
5672         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5673                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5674
5675                 if (e->freq == freq)
5676                         return e->vco;
5677         }
5678
5679         return 8100;
5680 }
5681
5682 static void
5683 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5684 {
5685         unsigned int min_freq;
5686         u32 val;
5687
5688         /* select the minimum CDCLK before enabling DPLL 0 */
5689         val = I915_READ(CDCLK_CTL);
5690         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5691         val |= CDCLK_FREQ_337_308;
5692
5693         if (required_vco == 8640)
5694                 min_freq = 308570;
5695         else
5696                 min_freq = 337500;
5697
5698         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5699
5700         I915_WRITE(CDCLK_CTL, val);
5701         POSTING_READ(CDCLK_CTL);
5702
5703         /*
5704          * We always enable DPLL0 with the lowest link rate possible, but still
5705          * taking into account the VCO required to operate the eDP panel at the
5706          * desired frequency. The usual DP link rates operate with a VCO of
5707          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5708          * The modeset code is responsible for the selection of the exact link
5709          * rate later on, with the constraint of choosing a frequency that
5710          * works with required_vco.
5711          */
5712         val = I915_READ(DPLL_CTRL1);
5713
5714         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5715                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5716         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5717         if (required_vco == 8640)
5718                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5719                                             SKL_DPLL0);
5720         else
5721                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5722                                             SKL_DPLL0);
5723
5724         I915_WRITE(DPLL_CTRL1, val);
5725         POSTING_READ(DPLL_CTRL1);
5726
5727         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5728
5729         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5730                 DRM_ERROR("DPLL0 not locked\n");
5731 }
5732
5733 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5734 {
5735         int ret;
5736         u32 val;
5737
5738         /* inform PCU we want to change CDCLK */
5739         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5740         mutex_lock(&dev_priv->rps.hw_lock);
5741         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5742         mutex_unlock(&dev_priv->rps.hw_lock);
5743
5744         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5745 }
5746
5747 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5748 {
5749         unsigned int i;
5750
5751         for (i = 0; i < 15; i++) {
5752                 if (skl_cdclk_pcu_ready(dev_priv))
5753                         return true;
5754                 udelay(10);
5755         }
5756
5757         return false;
5758 }
5759
5760 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5761 {
5762         struct drm_device *dev = dev_priv->dev;
5763         u32 freq_select, pcu_ack;
5764
5765         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5766
5767         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5768                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5769                 return;
5770         }
5771
5772         /* set CDCLK_CTL */
5773         switch(freq) {
5774         case 450000:
5775         case 432000:
5776                 freq_select = CDCLK_FREQ_450_432;
5777                 pcu_ack = 1;
5778                 break;
5779         case 540000:
5780                 freq_select = CDCLK_FREQ_540;
5781                 pcu_ack = 2;
5782                 break;
5783         case 308570:
5784         case 337500:
5785         default:
5786                 freq_select = CDCLK_FREQ_337_308;
5787                 pcu_ack = 0;
5788                 break;
5789         case 617140:
5790         case 675000:
5791                 freq_select = CDCLK_FREQ_675_617;
5792                 pcu_ack = 3;
5793                 break;
5794         }
5795
5796         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5797         POSTING_READ(CDCLK_CTL);
5798
5799         /* inform PCU of the change */
5800         mutex_lock(&dev_priv->rps.hw_lock);
5801         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5802         mutex_unlock(&dev_priv->rps.hw_lock);
5803
5804         intel_update_cdclk(dev);
5805 }
5806
5807 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5808 {
5809         /* disable DBUF power */
5810         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5811         POSTING_READ(DBUF_CTL);
5812
5813         udelay(10);
5814
5815         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5816                 DRM_ERROR("DBuf power disable timeout\n");
5817
5818         /* disable DPLL0 */
5819         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5820         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5821                 DRM_ERROR("Couldn't disable DPLL0\n");
5822 }
5823
5824 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5825 {
5826         unsigned int required_vco;
5827
5828         /* DPLL0 not enabled (happens on early BIOS versions) */
5829         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5830                 /* enable DPLL0 */
5831                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5832                 skl_dpll0_enable(dev_priv, required_vco);
5833         }
5834
5835         /* set CDCLK to the frequency the BIOS chose */
5836         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5837
5838         /* enable DBUF power */
5839         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5840         POSTING_READ(DBUF_CTL);
5841
5842         udelay(10);
5843
5844         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5845                 DRM_ERROR("DBuf power enable timeout\n");
5846 }
5847
5848 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5849 {
5850         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5851         uint32_t cdctl = I915_READ(CDCLK_CTL);
5852         int freq = dev_priv->skl_boot_cdclk;
5853
5854         /*
5855          * check if the pre-os intialized the display
5856          * There is SWF18 scratchpad register defined which is set by the
5857          * pre-os which can be used by the OS drivers to check the status
5858          */
5859         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5860                 goto sanitize;
5861
5862         /* Is PLL enabled and locked ? */
5863         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5864                 goto sanitize;
5865
5866         /* DPLL okay; verify the cdclock
5867          *
5868          * Noticed in some instances that the freq selection is correct but
5869          * decimal part is programmed wrong from BIOS where pre-os does not
5870          * enable display. Verify the same as well.
5871          */
5872         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5873                 /* All well; nothing to sanitize */
5874                 return false;
5875 sanitize:
5876         /*
5877          * As of now initialize with max cdclk till
5878          * we get dynamic cdclk support
5879          * */
5880         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5881         skl_init_cdclk(dev_priv);
5882
5883         /* we did have to sanitize */
5884         return true;
5885 }
5886
5887 /* Adjust CDclk dividers to allow high res or save power if possible */
5888 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5889 {
5890         struct drm_i915_private *dev_priv = dev->dev_private;
5891         u32 val, cmd;
5892
5893         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5894                                         != dev_priv->cdclk_freq);
5895
5896         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5897                 cmd = 2;
5898         else if (cdclk == 266667)
5899                 cmd = 1;
5900         else
5901                 cmd = 0;
5902
5903         mutex_lock(&dev_priv->rps.hw_lock);
5904         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5905         val &= ~DSPFREQGUAR_MASK;
5906         val |= (cmd << DSPFREQGUAR_SHIFT);
5907         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5908         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5909                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5910                      50)) {
5911                 DRM_ERROR("timed out waiting for CDclk change\n");
5912         }
5913         mutex_unlock(&dev_priv->rps.hw_lock);
5914
5915         mutex_lock(&dev_priv->sb_lock);
5916
5917         if (cdclk == 400000) {
5918                 u32 divider;
5919
5920                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5921
5922                 /* adjust cdclk divider */
5923                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5924                 val &= ~CCK_FREQUENCY_VALUES;
5925                 val |= divider;
5926                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5927
5928                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5929                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5930                              50))
5931                         DRM_ERROR("timed out waiting for CDclk change\n");
5932         }
5933
5934         /* adjust self-refresh exit latency value */
5935         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5936         val &= ~0x7f;
5937
5938         /*
5939          * For high bandwidth configs, we set a higher latency in the bunit
5940          * so that the core display fetch happens in time to avoid underruns.
5941          */
5942         if (cdclk == 400000)
5943                 val |= 4500 / 250; /* 4.5 usec */
5944         else
5945                 val |= 3000 / 250; /* 3.0 usec */
5946         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5947
5948         mutex_unlock(&dev_priv->sb_lock);
5949
5950         intel_update_cdclk(dev);
5951 }
5952
5953 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5954 {
5955         struct drm_i915_private *dev_priv = dev->dev_private;
5956         u32 val, cmd;
5957
5958         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5959                                                 != dev_priv->cdclk_freq);
5960
5961         switch (cdclk) {
5962         case 333333:
5963         case 320000:
5964         case 266667:
5965         case 200000:
5966                 break;
5967         default:
5968                 MISSING_CASE(cdclk);
5969                 return;
5970         }
5971
5972         /*
5973          * Specs are full of misinformation, but testing on actual
5974          * hardware has shown that we just need to write the desired
5975          * CCK divider into the Punit register.
5976          */
5977         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5978
5979         mutex_lock(&dev_priv->rps.hw_lock);
5980         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5981         val &= ~DSPFREQGUAR_MASK_CHV;
5982         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5983         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5984         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5985                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5986                      50)) {
5987                 DRM_ERROR("timed out waiting for CDclk change\n");
5988         }
5989         mutex_unlock(&dev_priv->rps.hw_lock);
5990
5991         intel_update_cdclk(dev);
5992 }
5993
5994 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5995                                  int max_pixclk)
5996 {
5997         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5998         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5999
6000         /*
6001          * Really only a few cases to deal with, as only 4 CDclks are supported:
6002          *   200MHz
6003          *   267MHz
6004          *   320/333MHz (depends on HPLL freq)
6005          *   400MHz (VLV only)
6006          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6007          * of the lower bin and adjust if needed.
6008          *
6009          * We seem to get an unstable or solid color picture at 200MHz.
6010          * Not sure what's wrong. For now use 200MHz only when all pipes
6011          * are off.
6012          */
6013         if (!IS_CHERRYVIEW(dev_priv) &&
6014             max_pixclk > freq_320*limit/100)
6015                 return 400000;
6016         else if (max_pixclk > 266667*limit/100)
6017                 return freq_320;
6018         else if (max_pixclk > 0)
6019                 return 266667;
6020         else
6021                 return 200000;
6022 }
6023
6024 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6025                               int max_pixclk)
6026 {
6027         /*
6028          * FIXME:
6029          * - remove the guardband, it's not needed on BXT
6030          * - set 19.2MHz bypass frequency if there are no active pipes
6031          */
6032         if (max_pixclk > 576000*9/10)
6033                 return 624000;
6034         else if (max_pixclk > 384000*9/10)
6035                 return 576000;
6036         else if (max_pixclk > 288000*9/10)
6037                 return 384000;
6038         else if (max_pixclk > 144000*9/10)
6039                 return 288000;
6040         else
6041                 return 144000;
6042 }
6043
6044 /* Compute the max pixel clock for new configuration. Uses atomic state if
6045  * that's non-NULL, look at current state otherwise. */
6046 static int intel_mode_max_pixclk(struct drm_device *dev,
6047                                  struct drm_atomic_state *state)
6048 {
6049         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6050         struct drm_i915_private *dev_priv = dev->dev_private;
6051         struct drm_crtc *crtc;
6052         struct drm_crtc_state *crtc_state;
6053         unsigned max_pixclk = 0, i;
6054         enum pipe pipe;
6055
6056         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6057                sizeof(intel_state->min_pixclk));
6058
6059         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6060                 int pixclk = 0;
6061
6062                 if (crtc_state->enable)
6063                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6064
6065                 intel_state->min_pixclk[i] = pixclk;
6066         }
6067
6068         if (!intel_state->active_crtcs)
6069                 return 0;
6070
6071         for_each_pipe(dev_priv, pipe)
6072                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6073
6074         return max_pixclk;
6075 }
6076
6077 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6078 {
6079         struct drm_device *dev = state->dev;
6080         struct drm_i915_private *dev_priv = dev->dev_private;
6081         int max_pixclk = intel_mode_max_pixclk(dev, state);
6082         struct intel_atomic_state *intel_state =
6083                 to_intel_atomic_state(state);
6084
6085         if (max_pixclk < 0)
6086                 return max_pixclk;
6087
6088         intel_state->cdclk = intel_state->dev_cdclk =
6089                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6090
6091         if (!intel_state->active_crtcs)
6092                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6093
6094         return 0;
6095 }
6096
6097 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6098 {
6099         struct drm_device *dev = state->dev;
6100         struct drm_i915_private *dev_priv = dev->dev_private;
6101         int max_pixclk = intel_mode_max_pixclk(dev, state);
6102         struct intel_atomic_state *intel_state =
6103                 to_intel_atomic_state(state);
6104
6105         if (max_pixclk < 0)
6106                 return max_pixclk;
6107
6108         intel_state->cdclk = intel_state->dev_cdclk =
6109                 broxton_calc_cdclk(dev_priv, max_pixclk);
6110
6111         if (!intel_state->active_crtcs)
6112                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6113
6114         return 0;
6115 }
6116
6117 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6118 {
6119         unsigned int credits, default_credits;
6120
6121         if (IS_CHERRYVIEW(dev_priv))
6122                 default_credits = PFI_CREDIT(12);
6123         else
6124                 default_credits = PFI_CREDIT(8);
6125
6126         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6127                 /* CHV suggested value is 31 or 63 */
6128                 if (IS_CHERRYVIEW(dev_priv))
6129                         credits = PFI_CREDIT_63;
6130                 else
6131                         credits = PFI_CREDIT(15);
6132         } else {
6133                 credits = default_credits;
6134         }
6135
6136         /*
6137          * WA - write default credits before re-programming
6138          * FIXME: should we also set the resend bit here?
6139          */
6140         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6141                    default_credits);
6142
6143         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6144                    credits | PFI_CREDIT_RESEND);
6145
6146         /*
6147          * FIXME is this guaranteed to clear
6148          * immediately or should we poll for it?
6149          */
6150         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6151 }
6152
6153 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6154 {
6155         struct drm_device *dev = old_state->dev;
6156         struct drm_i915_private *dev_priv = dev->dev_private;
6157         struct intel_atomic_state *old_intel_state =
6158                 to_intel_atomic_state(old_state);
6159         unsigned req_cdclk = old_intel_state->dev_cdclk;
6160
6161         /*
6162          * FIXME: We can end up here with all power domains off, yet
6163          * with a CDCLK frequency other than the minimum. To account
6164          * for this take the PIPE-A power domain, which covers the HW
6165          * blocks needed for the following programming. This can be
6166          * removed once it's guaranteed that we get here either with
6167          * the minimum CDCLK set, or the required power domains
6168          * enabled.
6169          */
6170         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6171
6172         if (IS_CHERRYVIEW(dev))
6173                 cherryview_set_cdclk(dev, req_cdclk);
6174         else
6175                 valleyview_set_cdclk(dev, req_cdclk);
6176
6177         vlv_program_pfi_credits(dev_priv);
6178
6179         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6180 }
6181
6182 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6183 {
6184         struct drm_device *dev = crtc->dev;
6185         struct drm_i915_private *dev_priv = to_i915(dev);
6186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6187         struct intel_encoder *encoder;
6188         int pipe = intel_crtc->pipe;
6189
6190         if (WARN_ON(intel_crtc->active))
6191                 return;
6192
6193         if (intel_crtc->config->has_dp_encoder)
6194                 intel_dp_set_m_n(intel_crtc, M1_N1);
6195
6196         intel_set_pipe_timings(intel_crtc);
6197
6198         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6199                 struct drm_i915_private *dev_priv = dev->dev_private;
6200
6201                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6202                 I915_WRITE(CHV_CANVAS(pipe), 0);
6203         }
6204
6205         i9xx_set_pipeconf(intel_crtc);
6206
6207         intel_crtc->active = true;
6208
6209         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6210
6211         for_each_encoder_on_crtc(dev, crtc, encoder)
6212                 if (encoder->pre_pll_enable)
6213                         encoder->pre_pll_enable(encoder);
6214
6215         if (!intel_crtc->config->has_dsi_encoder) {
6216                 if (IS_CHERRYVIEW(dev)) {
6217                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6218                         chv_enable_pll(intel_crtc, intel_crtc->config);
6219                 } else {
6220                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6221                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6222                 }
6223         }
6224
6225         for_each_encoder_on_crtc(dev, crtc, encoder)
6226                 if (encoder->pre_enable)
6227                         encoder->pre_enable(encoder);
6228
6229         i9xx_pfit_enable(intel_crtc);
6230
6231         intel_crtc_load_lut(crtc);
6232
6233         intel_enable_pipe(intel_crtc);
6234
6235         assert_vblank_disabled(crtc);
6236         drm_crtc_vblank_on(crtc);
6237
6238         for_each_encoder_on_crtc(dev, crtc, encoder)
6239                 encoder->enable(encoder);
6240 }
6241
6242 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6243 {
6244         struct drm_device *dev = crtc->base.dev;
6245         struct drm_i915_private *dev_priv = dev->dev_private;
6246
6247         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6248         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6249 }
6250
6251 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6252 {
6253         struct drm_device *dev = crtc->dev;
6254         struct drm_i915_private *dev_priv = to_i915(dev);
6255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6256         struct intel_encoder *encoder;
6257         int pipe = intel_crtc->pipe;
6258
6259         if (WARN_ON(intel_crtc->active))
6260                 return;
6261
6262         i9xx_set_pll_dividers(intel_crtc);
6263
6264         if (intel_crtc->config->has_dp_encoder)
6265                 intel_dp_set_m_n(intel_crtc, M1_N1);
6266
6267         intel_set_pipe_timings(intel_crtc);
6268
6269         i9xx_set_pipeconf(intel_crtc);
6270
6271         intel_crtc->active = true;
6272
6273         if (!IS_GEN2(dev))
6274                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6275
6276         for_each_encoder_on_crtc(dev, crtc, encoder)
6277                 if (encoder->pre_enable)
6278                         encoder->pre_enable(encoder);
6279
6280         i9xx_enable_pll(intel_crtc);
6281
6282         i9xx_pfit_enable(intel_crtc);
6283
6284         intel_crtc_load_lut(crtc);
6285
6286         intel_update_watermarks(crtc);
6287         intel_enable_pipe(intel_crtc);
6288
6289         assert_vblank_disabled(crtc);
6290         drm_crtc_vblank_on(crtc);
6291
6292         for_each_encoder_on_crtc(dev, crtc, encoder)
6293                 encoder->enable(encoder);
6294
6295         intel_fbc_enable(intel_crtc);
6296 }
6297
6298 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6299 {
6300         struct drm_device *dev = crtc->base.dev;
6301         struct drm_i915_private *dev_priv = dev->dev_private;
6302
6303         if (!crtc->config->gmch_pfit.control)
6304                 return;
6305
6306         assert_pipe_disabled(dev_priv, crtc->pipe);
6307
6308         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6309                          I915_READ(PFIT_CONTROL));
6310         I915_WRITE(PFIT_CONTROL, 0);
6311 }
6312
6313 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6314 {
6315         struct drm_device *dev = crtc->dev;
6316         struct drm_i915_private *dev_priv = dev->dev_private;
6317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6318         struct intel_encoder *encoder;
6319         int pipe = intel_crtc->pipe;
6320
6321         /*
6322          * On gen2 planes are double buffered but the pipe isn't, so we must
6323          * wait for planes to fully turn off before disabling the pipe.
6324          * We also need to wait on all gmch platforms because of the
6325          * self-refresh mode constraint explained above.
6326          */
6327         intel_wait_for_vblank(dev, pipe);
6328
6329         for_each_encoder_on_crtc(dev, crtc, encoder)
6330                 encoder->disable(encoder);
6331
6332         drm_crtc_vblank_off(crtc);
6333         assert_vblank_disabled(crtc);
6334
6335         intel_disable_pipe(intel_crtc);
6336
6337         i9xx_pfit_disable(intel_crtc);
6338
6339         for_each_encoder_on_crtc(dev, crtc, encoder)
6340                 if (encoder->post_disable)
6341                         encoder->post_disable(encoder);
6342
6343         if (!intel_crtc->config->has_dsi_encoder) {
6344                 if (IS_CHERRYVIEW(dev))
6345                         chv_disable_pll(dev_priv, pipe);
6346                 else if (IS_VALLEYVIEW(dev))
6347                         vlv_disable_pll(dev_priv, pipe);
6348                 else
6349                         i9xx_disable_pll(intel_crtc);
6350         }
6351
6352         for_each_encoder_on_crtc(dev, crtc, encoder)
6353                 if (encoder->post_pll_disable)
6354                         encoder->post_pll_disable(encoder);
6355
6356         if (!IS_GEN2(dev))
6357                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6358
6359         intel_fbc_disable_crtc(intel_crtc);
6360 }
6361
6362 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6363 {
6364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6365         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6366         enum intel_display_power_domain domain;
6367         unsigned long domains;
6368
6369         if (!intel_crtc->active)
6370                 return;
6371
6372         if (to_intel_plane_state(crtc->primary->state)->visible) {
6373                 WARN_ON(intel_crtc->unpin_work);
6374
6375                 intel_pre_disable_primary(crtc);
6376
6377                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6378                 to_intel_plane_state(crtc->primary->state)->visible = false;
6379         }
6380
6381         dev_priv->display.crtc_disable(crtc);
6382         intel_crtc->active = false;
6383         intel_update_watermarks(crtc);
6384         intel_disable_shared_dpll(intel_crtc);
6385
6386         domains = intel_crtc->enabled_power_domains;
6387         for_each_power_domain(domain, domains)
6388                 intel_display_power_put(dev_priv, domain);
6389         intel_crtc->enabled_power_domains = 0;
6390
6391         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6392         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6393 }
6394
6395 /*
6396  * turn all crtc's off, but do not adjust state
6397  * This has to be paired with a call to intel_modeset_setup_hw_state.
6398  */
6399 int intel_display_suspend(struct drm_device *dev)
6400 {
6401         struct drm_mode_config *config = &dev->mode_config;
6402         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6403         struct drm_atomic_state *state;
6404         struct drm_crtc *crtc;
6405         unsigned crtc_mask = 0;
6406         int ret = 0;
6407
6408         if (WARN_ON(!ctx))
6409                 return 0;
6410
6411         lockdep_assert_held(&ctx->ww_ctx);
6412         state = drm_atomic_state_alloc(dev);
6413         if (WARN_ON(!state))
6414                 return -ENOMEM;
6415
6416         state->acquire_ctx = ctx;
6417         state->allow_modeset = true;
6418
6419         for_each_crtc(dev, crtc) {
6420                 struct drm_crtc_state *crtc_state =
6421                         drm_atomic_get_crtc_state(state, crtc);
6422
6423                 ret = PTR_ERR_OR_ZERO(crtc_state);
6424                 if (ret)
6425                         goto free;
6426
6427                 if (!crtc_state->active)
6428                         continue;
6429
6430                 crtc_state->active = false;
6431                 crtc_mask |= 1 << drm_crtc_index(crtc);
6432         }
6433
6434         if (crtc_mask) {
6435                 ret = drm_atomic_commit(state);
6436
6437                 if (!ret) {
6438                         for_each_crtc(dev, crtc)
6439                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6440                                         crtc->state->active = true;
6441
6442                         return ret;
6443                 }
6444         }
6445
6446 free:
6447         if (ret)
6448                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6449         drm_atomic_state_free(state);
6450         return ret;
6451 }
6452
6453 void intel_encoder_destroy(struct drm_encoder *encoder)
6454 {
6455         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6456
6457         drm_encoder_cleanup(encoder);
6458         kfree(intel_encoder);
6459 }
6460
6461 /* Cross check the actual hw state with our own modeset state tracking (and it's
6462  * internal consistency). */
6463 static void intel_connector_check_state(struct intel_connector *connector)
6464 {
6465         struct drm_crtc *crtc = connector->base.state->crtc;
6466
6467         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6468                       connector->base.base.id,
6469                       connector->base.name);
6470
6471         if (connector->get_hw_state(connector)) {
6472                 struct intel_encoder *encoder = connector->encoder;
6473                 struct drm_connector_state *conn_state = connector->base.state;
6474
6475                 I915_STATE_WARN(!crtc,
6476                          "connector enabled without attached crtc\n");
6477
6478                 if (!crtc)
6479                         return;
6480
6481                 I915_STATE_WARN(!crtc->state->active,
6482                       "connector is active, but attached crtc isn't\n");
6483
6484                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6485                         return;
6486
6487                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6488                         "atomic encoder doesn't match attached encoder\n");
6489
6490                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6491                         "attached encoder crtc differs from connector crtc\n");
6492         } else {
6493                 I915_STATE_WARN(crtc && crtc->state->active,
6494                         "attached crtc is active, but connector isn't\n");
6495                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6496                         "best encoder set without crtc!\n");
6497         }
6498 }
6499
6500 int intel_connector_init(struct intel_connector *connector)
6501 {
6502         drm_atomic_helper_connector_reset(&connector->base);
6503
6504         if (!connector->base.state)
6505                 return -ENOMEM;
6506
6507         return 0;
6508 }
6509
6510 struct intel_connector *intel_connector_alloc(void)
6511 {
6512         struct intel_connector *connector;
6513
6514         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6515         if (!connector)
6516                 return NULL;
6517
6518         if (intel_connector_init(connector) < 0) {
6519                 kfree(connector);
6520                 return NULL;
6521         }
6522
6523         return connector;
6524 }
6525
6526 /* Simple connector->get_hw_state implementation for encoders that support only
6527  * one connector and no cloning and hence the encoder state determines the state
6528  * of the connector. */
6529 bool intel_connector_get_hw_state(struct intel_connector *connector)
6530 {
6531         enum pipe pipe = 0;
6532         struct intel_encoder *encoder = connector->encoder;
6533
6534         return encoder->get_hw_state(encoder, &pipe);
6535 }
6536
6537 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6538 {
6539         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6540                 return crtc_state->fdi_lanes;
6541
6542         return 0;
6543 }
6544
6545 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6546                                      struct intel_crtc_state *pipe_config)
6547 {
6548         struct drm_atomic_state *state = pipe_config->base.state;
6549         struct intel_crtc *other_crtc;
6550         struct intel_crtc_state *other_crtc_state;
6551
6552         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6553                       pipe_name(pipe), pipe_config->fdi_lanes);
6554         if (pipe_config->fdi_lanes > 4) {
6555                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6556                               pipe_name(pipe), pipe_config->fdi_lanes);
6557                 return -EINVAL;
6558         }
6559
6560         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6561                 if (pipe_config->fdi_lanes > 2) {
6562                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6563                                       pipe_config->fdi_lanes);
6564                         return -EINVAL;
6565                 } else {
6566                         return 0;
6567                 }
6568         }
6569
6570         if (INTEL_INFO(dev)->num_pipes == 2)
6571                 return 0;
6572
6573         /* Ivybridge 3 pipe is really complicated */
6574         switch (pipe) {
6575         case PIPE_A:
6576                 return 0;
6577         case PIPE_B:
6578                 if (pipe_config->fdi_lanes <= 2)
6579                         return 0;
6580
6581                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6582                 other_crtc_state =
6583                         intel_atomic_get_crtc_state(state, other_crtc);
6584                 if (IS_ERR(other_crtc_state))
6585                         return PTR_ERR(other_crtc_state);
6586
6587                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6588                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6589                                       pipe_name(pipe), pipe_config->fdi_lanes);
6590                         return -EINVAL;
6591                 }
6592                 return 0;
6593         case PIPE_C:
6594                 if (pipe_config->fdi_lanes > 2) {
6595                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6596                                       pipe_name(pipe), pipe_config->fdi_lanes);
6597                         return -EINVAL;
6598                 }
6599
6600                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6601                 other_crtc_state =
6602                         intel_atomic_get_crtc_state(state, other_crtc);
6603                 if (IS_ERR(other_crtc_state))
6604                         return PTR_ERR(other_crtc_state);
6605
6606                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6607                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6608                         return -EINVAL;
6609                 }
6610                 return 0;
6611         default:
6612                 BUG();
6613         }
6614 }
6615
6616 #define RETRY 1
6617 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6618                                        struct intel_crtc_state *pipe_config)
6619 {
6620         struct drm_device *dev = intel_crtc->base.dev;
6621         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6622         int lane, link_bw, fdi_dotclock, ret;
6623         bool needs_recompute = false;
6624
6625 retry:
6626         /* FDI is a binary signal running at ~2.7GHz, encoding
6627          * each output octet as 10 bits. The actual frequency
6628          * is stored as a divider into a 100MHz clock, and the
6629          * mode pixel clock is stored in units of 1KHz.
6630          * Hence the bw of each lane in terms of the mode signal
6631          * is:
6632          */
6633         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6634
6635         fdi_dotclock = adjusted_mode->crtc_clock;
6636
6637         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6638                                            pipe_config->pipe_bpp);
6639
6640         pipe_config->fdi_lanes = lane;
6641
6642         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6643                                link_bw, &pipe_config->fdi_m_n);
6644
6645         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6646                                        intel_crtc->pipe, pipe_config);
6647         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6648                 pipe_config->pipe_bpp -= 2*3;
6649                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6650                               pipe_config->pipe_bpp);
6651                 needs_recompute = true;
6652                 pipe_config->bw_constrained = true;
6653
6654                 goto retry;
6655         }
6656
6657         if (needs_recompute)
6658                 return RETRY;
6659
6660         return ret;
6661 }
6662
6663 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6664                                      struct intel_crtc_state *pipe_config)
6665 {
6666         if (pipe_config->pipe_bpp > 24)
6667                 return false;
6668
6669         /* HSW can handle pixel rate up to cdclk? */
6670         if (IS_HASWELL(dev_priv->dev))
6671                 return true;
6672
6673         /*
6674          * We compare against max which means we must take
6675          * the increased cdclk requirement into account when
6676          * calculating the new cdclk.
6677          *
6678          * Should measure whether using a lower cdclk w/o IPS
6679          */
6680         return ilk_pipe_pixel_rate(pipe_config) <=
6681                 dev_priv->max_cdclk_freq * 95 / 100;
6682 }
6683
6684 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6685                                    struct intel_crtc_state *pipe_config)
6686 {
6687         struct drm_device *dev = crtc->base.dev;
6688         struct drm_i915_private *dev_priv = dev->dev_private;
6689
6690         pipe_config->ips_enabled = i915.enable_ips &&
6691                 hsw_crtc_supports_ips(crtc) &&
6692                 pipe_config_supports_ips(dev_priv, pipe_config);
6693 }
6694
6695 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6696 {
6697         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6698
6699         /* GDG double wide on either pipe, otherwise pipe A only */
6700         return INTEL_INFO(dev_priv)->gen < 4 &&
6701                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6702 }
6703
6704 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6705                                      struct intel_crtc_state *pipe_config)
6706 {
6707         struct drm_device *dev = crtc->base.dev;
6708         struct drm_i915_private *dev_priv = dev->dev_private;
6709         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6710
6711         /* FIXME should check pixel clock limits on all platforms */
6712         if (INTEL_INFO(dev)->gen < 4) {
6713                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6714
6715                 /*
6716                  * Enable double wide mode when the dot clock
6717                  * is > 90% of the (display) core speed.
6718                  */
6719                 if (intel_crtc_supports_double_wide(crtc) &&
6720                     adjusted_mode->crtc_clock > clock_limit) {
6721                         clock_limit *= 2;
6722                         pipe_config->double_wide = true;
6723                 }
6724
6725                 if (adjusted_mode->crtc_clock > clock_limit) {
6726                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6727                                       adjusted_mode->crtc_clock, clock_limit,
6728                                       yesno(pipe_config->double_wide));
6729                         return -EINVAL;
6730                 }
6731         }
6732
6733         /*
6734          * Pipe horizontal size must be even in:
6735          * - DVO ganged mode
6736          * - LVDS dual channel mode
6737          * - Double wide pipe
6738          */
6739         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6740              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6741                 pipe_config->pipe_src_w &= ~1;
6742
6743         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6744          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6745          */
6746         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6747                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6748                 return -EINVAL;
6749
6750         if (HAS_IPS(dev))
6751                 hsw_compute_ips_config(crtc, pipe_config);
6752
6753         if (pipe_config->has_pch_encoder)
6754                 return ironlake_fdi_compute_config(crtc, pipe_config);
6755
6756         return 0;
6757 }
6758
6759 static int skylake_get_display_clock_speed(struct drm_device *dev)
6760 {
6761         struct drm_i915_private *dev_priv = to_i915(dev);
6762         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6763         uint32_t cdctl = I915_READ(CDCLK_CTL);
6764         uint32_t linkrate;
6765
6766         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6767                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6768
6769         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6770                 return 540000;
6771
6772         linkrate = (I915_READ(DPLL_CTRL1) &
6773                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6774
6775         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6776             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6777                 /* vco 8640 */
6778                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6779                 case CDCLK_FREQ_450_432:
6780                         return 432000;
6781                 case CDCLK_FREQ_337_308:
6782                         return 308570;
6783                 case CDCLK_FREQ_675_617:
6784                         return 617140;
6785                 default:
6786                         WARN(1, "Unknown cd freq selection\n");
6787                 }
6788         } else {
6789                 /* vco 8100 */
6790                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6791                 case CDCLK_FREQ_450_432:
6792                         return 450000;
6793                 case CDCLK_FREQ_337_308:
6794                         return 337500;
6795                 case CDCLK_FREQ_675_617:
6796                         return 675000;
6797                 default:
6798                         WARN(1, "Unknown cd freq selection\n");
6799                 }
6800         }
6801
6802         /* error case, do as if DPLL0 isn't enabled */
6803         return 24000;
6804 }
6805
6806 static int broxton_get_display_clock_speed(struct drm_device *dev)
6807 {
6808         struct drm_i915_private *dev_priv = to_i915(dev);
6809         uint32_t cdctl = I915_READ(CDCLK_CTL);
6810         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6811         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6812         int cdclk;
6813
6814         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6815                 return 19200;
6816
6817         cdclk = 19200 * pll_ratio / 2;
6818
6819         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6820         case BXT_CDCLK_CD2X_DIV_SEL_1:
6821                 return cdclk;  /* 576MHz or 624MHz */
6822         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6823                 return cdclk * 2 / 3; /* 384MHz */
6824         case BXT_CDCLK_CD2X_DIV_SEL_2:
6825                 return cdclk / 2; /* 288MHz */
6826         case BXT_CDCLK_CD2X_DIV_SEL_4:
6827                 return cdclk / 4; /* 144MHz */
6828         }
6829
6830         /* error case, do as if DE PLL isn't enabled */
6831         return 19200;
6832 }
6833
6834 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6835 {
6836         struct drm_i915_private *dev_priv = dev->dev_private;
6837         uint32_t lcpll = I915_READ(LCPLL_CTL);
6838         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6839
6840         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6841                 return 800000;
6842         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6843                 return 450000;
6844         else if (freq == LCPLL_CLK_FREQ_450)
6845                 return 450000;
6846         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6847                 return 540000;
6848         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6849                 return 337500;
6850         else
6851                 return 675000;
6852 }
6853
6854 static int haswell_get_display_clock_speed(struct drm_device *dev)
6855 {
6856         struct drm_i915_private *dev_priv = dev->dev_private;
6857         uint32_t lcpll = I915_READ(LCPLL_CTL);
6858         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6859
6860         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6861                 return 800000;
6862         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6863                 return 450000;
6864         else if (freq == LCPLL_CLK_FREQ_450)
6865                 return 450000;
6866         else if (IS_HSW_ULT(dev))
6867                 return 337500;
6868         else
6869                 return 540000;
6870 }
6871
6872 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6873 {
6874         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6875                                       CCK_DISPLAY_CLOCK_CONTROL);
6876 }
6877
6878 static int ilk_get_display_clock_speed(struct drm_device *dev)
6879 {
6880         return 450000;
6881 }
6882
6883 static int i945_get_display_clock_speed(struct drm_device *dev)
6884 {
6885         return 400000;
6886 }
6887
6888 static int i915_get_display_clock_speed(struct drm_device *dev)
6889 {
6890         return 333333;
6891 }
6892
6893 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6894 {
6895         return 200000;
6896 }
6897
6898 static int pnv_get_display_clock_speed(struct drm_device *dev)
6899 {
6900         u16 gcfgc = 0;
6901
6902         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6903
6904         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6905         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6906                 return 266667;
6907         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6908                 return 333333;
6909         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6910                 return 444444;
6911         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6912                 return 200000;
6913         default:
6914                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6915         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6916                 return 133333;
6917         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6918                 return 166667;
6919         }
6920 }
6921
6922 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6923 {
6924         u16 gcfgc = 0;
6925
6926         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6927
6928         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6929                 return 133333;
6930         else {
6931                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6932                 case GC_DISPLAY_CLOCK_333_MHZ:
6933                         return 333333;
6934                 default:
6935                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6936                         return 190000;
6937                 }
6938         }
6939 }
6940
6941 static int i865_get_display_clock_speed(struct drm_device *dev)
6942 {
6943         return 266667;
6944 }
6945
6946 static int i85x_get_display_clock_speed(struct drm_device *dev)
6947 {
6948         u16 hpllcc = 0;
6949
6950         /*
6951          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6952          * encoding is different :(
6953          * FIXME is this the right way to detect 852GM/852GMV?
6954          */
6955         if (dev->pdev->revision == 0x1)
6956                 return 133333;
6957
6958         pci_bus_read_config_word(dev->pdev->bus,
6959                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6960
6961         /* Assume that the hardware is in the high speed state.  This
6962          * should be the default.
6963          */
6964         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6965         case GC_CLOCK_133_200:
6966         case GC_CLOCK_133_200_2:
6967         case GC_CLOCK_100_200:
6968                 return 200000;
6969         case GC_CLOCK_166_250:
6970                 return 250000;
6971         case GC_CLOCK_100_133:
6972                 return 133333;
6973         case GC_CLOCK_133_266:
6974         case GC_CLOCK_133_266_2:
6975         case GC_CLOCK_166_266:
6976                 return 266667;
6977         }
6978
6979         /* Shouldn't happen */
6980         return 0;
6981 }
6982
6983 static int i830_get_display_clock_speed(struct drm_device *dev)
6984 {
6985         return 133333;
6986 }
6987
6988 static unsigned int intel_hpll_vco(struct drm_device *dev)
6989 {
6990         struct drm_i915_private *dev_priv = dev->dev_private;
6991         static const unsigned int blb_vco[8] = {
6992                 [0] = 3200000,
6993                 [1] = 4000000,
6994                 [2] = 5333333,
6995                 [3] = 4800000,
6996                 [4] = 6400000,
6997         };
6998         static const unsigned int pnv_vco[8] = {
6999                 [0] = 3200000,
7000                 [1] = 4000000,
7001                 [2] = 5333333,
7002                 [3] = 4800000,
7003                 [4] = 2666667,
7004         };
7005         static const unsigned int cl_vco[8] = {
7006                 [0] = 3200000,
7007                 [1] = 4000000,
7008                 [2] = 5333333,
7009                 [3] = 6400000,
7010                 [4] = 3333333,
7011                 [5] = 3566667,
7012                 [6] = 4266667,
7013         };
7014         static const unsigned int elk_vco[8] = {
7015                 [0] = 3200000,
7016                 [1] = 4000000,
7017                 [2] = 5333333,
7018                 [3] = 4800000,
7019         };
7020         static const unsigned int ctg_vco[8] = {
7021                 [0] = 3200000,
7022                 [1] = 4000000,
7023                 [2] = 5333333,
7024                 [3] = 6400000,
7025                 [4] = 2666667,
7026                 [5] = 4266667,
7027         };
7028         const unsigned int *vco_table;
7029         unsigned int vco;
7030         uint8_t tmp = 0;
7031
7032         /* FIXME other chipsets? */
7033         if (IS_GM45(dev))
7034                 vco_table = ctg_vco;
7035         else if (IS_G4X(dev))
7036                 vco_table = elk_vco;
7037         else if (IS_CRESTLINE(dev))
7038                 vco_table = cl_vco;
7039         else if (IS_PINEVIEW(dev))
7040                 vco_table = pnv_vco;
7041         else if (IS_G33(dev))
7042                 vco_table = blb_vco;
7043         else
7044                 return 0;
7045
7046         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7047
7048         vco = vco_table[tmp & 0x7];
7049         if (vco == 0)
7050                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7051         else
7052                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7053
7054         return vco;
7055 }
7056
7057 static int gm45_get_display_clock_speed(struct drm_device *dev)
7058 {
7059         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7060         uint16_t tmp = 0;
7061
7062         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7063
7064         cdclk_sel = (tmp >> 12) & 0x1;
7065
7066         switch (vco) {
7067         case 2666667:
7068         case 4000000:
7069         case 5333333:
7070                 return cdclk_sel ? 333333 : 222222;
7071         case 3200000:
7072                 return cdclk_sel ? 320000 : 228571;
7073         default:
7074                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7075                 return 222222;
7076         }
7077 }
7078
7079 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7080 {
7081         static const uint8_t div_3200[] = { 16, 10,  8 };
7082         static const uint8_t div_4000[] = { 20, 12, 10 };
7083         static const uint8_t div_5333[] = { 24, 16, 14 };
7084         const uint8_t *div_table;
7085         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7086         uint16_t tmp = 0;
7087
7088         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7089
7090         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7091
7092         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7093                 goto fail;
7094
7095         switch (vco) {
7096         case 3200000:
7097                 div_table = div_3200;
7098                 break;
7099         case 4000000:
7100                 div_table = div_4000;
7101                 break;
7102         case 5333333:
7103                 div_table = div_5333;
7104                 break;
7105         default:
7106                 goto fail;
7107         }
7108
7109         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7110
7111 fail:
7112         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7113         return 200000;
7114 }
7115
7116 static int g33_get_display_clock_speed(struct drm_device *dev)
7117 {
7118         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7119         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7120         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7121         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7122         const uint8_t *div_table;
7123         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7124         uint16_t tmp = 0;
7125
7126         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7127
7128         cdclk_sel = (tmp >> 4) & 0x7;
7129
7130         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7131                 goto fail;
7132
7133         switch (vco) {
7134         case 3200000:
7135                 div_table = div_3200;
7136                 break;
7137         case 4000000:
7138                 div_table = div_4000;
7139                 break;
7140         case 4800000:
7141                 div_table = div_4800;
7142                 break;
7143         case 5333333:
7144                 div_table = div_5333;
7145                 break;
7146         default:
7147                 goto fail;
7148         }
7149
7150         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7151
7152 fail:
7153         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7154         return 190476;
7155 }
7156
7157 static void
7158 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7159 {
7160         while (*num > DATA_LINK_M_N_MASK ||
7161                *den > DATA_LINK_M_N_MASK) {
7162                 *num >>= 1;
7163                 *den >>= 1;
7164         }
7165 }
7166
7167 static void compute_m_n(unsigned int m, unsigned int n,
7168                         uint32_t *ret_m, uint32_t *ret_n)
7169 {
7170         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7171         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7172         intel_reduce_m_n_ratio(ret_m, ret_n);
7173 }
7174
7175 void
7176 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7177                        int pixel_clock, int link_clock,
7178                        struct intel_link_m_n *m_n)
7179 {
7180         m_n->tu = 64;
7181
7182         compute_m_n(bits_per_pixel * pixel_clock,
7183                     link_clock * nlanes * 8,
7184                     &m_n->gmch_m, &m_n->gmch_n);
7185
7186         compute_m_n(pixel_clock, link_clock,
7187                     &m_n->link_m, &m_n->link_n);
7188 }
7189
7190 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7191 {
7192         if (i915.panel_use_ssc >= 0)
7193                 return i915.panel_use_ssc != 0;
7194         return dev_priv->vbt.lvds_use_ssc
7195                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7196 }
7197
7198 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7199                            int num_connectors)
7200 {
7201         struct drm_device *dev = crtc_state->base.crtc->dev;
7202         struct drm_i915_private *dev_priv = dev->dev_private;
7203         int refclk;
7204
7205         WARN_ON(!crtc_state->base.state);
7206
7207         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7208                 refclk = 100000;
7209         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7210             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7211                 refclk = dev_priv->vbt.lvds_ssc_freq;
7212                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7213         } else if (!IS_GEN2(dev)) {
7214                 refclk = 96000;
7215         } else {
7216                 refclk = 48000;
7217         }
7218
7219         return refclk;
7220 }
7221
7222 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7223 {
7224         return (1 << dpll->n) << 16 | dpll->m2;
7225 }
7226
7227 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7228 {
7229         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7230 }
7231
7232 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7233                                      struct intel_crtc_state *crtc_state,
7234                                      intel_clock_t *reduced_clock)
7235 {
7236         struct drm_device *dev = crtc->base.dev;
7237         u32 fp, fp2 = 0;
7238
7239         if (IS_PINEVIEW(dev)) {
7240                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7241                 if (reduced_clock)
7242                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7243         } else {
7244                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7245                 if (reduced_clock)
7246                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7247         }
7248
7249         crtc_state->dpll_hw_state.fp0 = fp;
7250
7251         crtc->lowfreq_avail = false;
7252         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7253             reduced_clock) {
7254                 crtc_state->dpll_hw_state.fp1 = fp2;
7255                 crtc->lowfreq_avail = true;
7256         } else {
7257                 crtc_state->dpll_hw_state.fp1 = fp;
7258         }
7259 }
7260
7261 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7262                 pipe)
7263 {
7264         u32 reg_val;
7265
7266         /*
7267          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7268          * and set it to a reasonable value instead.
7269          */
7270         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7271         reg_val &= 0xffffff00;
7272         reg_val |= 0x00000030;
7273         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7274
7275         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7276         reg_val &= 0x8cffffff;
7277         reg_val = 0x8c000000;
7278         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7279
7280         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7281         reg_val &= 0xffffff00;
7282         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7283
7284         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7285         reg_val &= 0x00ffffff;
7286         reg_val |= 0xb0000000;
7287         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7288 }
7289
7290 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7291                                          struct intel_link_m_n *m_n)
7292 {
7293         struct drm_device *dev = crtc->base.dev;
7294         struct drm_i915_private *dev_priv = dev->dev_private;
7295         int pipe = crtc->pipe;
7296
7297         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7298         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7299         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7300         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7301 }
7302
7303 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7304                                          struct intel_link_m_n *m_n,
7305                                          struct intel_link_m_n *m2_n2)
7306 {
7307         struct drm_device *dev = crtc->base.dev;
7308         struct drm_i915_private *dev_priv = dev->dev_private;
7309         int pipe = crtc->pipe;
7310         enum transcoder transcoder = crtc->config->cpu_transcoder;
7311
7312         if (INTEL_INFO(dev)->gen >= 5) {
7313                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7314                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7315                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7316                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7317                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7318                  * for gen < 8) and if DRRS is supported (to make sure the
7319                  * registers are not unnecessarily accessed).
7320                  */
7321                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7322                         crtc->config->has_drrs) {
7323                         I915_WRITE(PIPE_DATA_M2(transcoder),
7324                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7325                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7326                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7327                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7328                 }
7329         } else {
7330                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7331                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7332                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7333                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7334         }
7335 }
7336
7337 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7338 {
7339         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7340
7341         if (m_n == M1_N1) {
7342                 dp_m_n = &crtc->config->dp_m_n;
7343                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7344         } else if (m_n == M2_N2) {
7345
7346                 /*
7347                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7348                  * needs to be programmed into M1_N1.
7349                  */
7350                 dp_m_n = &crtc->config->dp_m2_n2;
7351         } else {
7352                 DRM_ERROR("Unsupported divider value\n");
7353                 return;
7354         }
7355
7356         if (crtc->config->has_pch_encoder)
7357                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7358         else
7359                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7360 }
7361
7362 static void vlv_compute_dpll(struct intel_crtc *crtc,
7363                              struct intel_crtc_state *pipe_config)
7364 {
7365         u32 dpll, dpll_md;
7366
7367         /*
7368          * Enable DPIO clock input. We should never disable the reference
7369          * clock for pipe B, since VGA hotplug / manual detection depends
7370          * on it.
7371          */
7372         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7373                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7374         /* We should never disable this, set it here for state tracking */
7375         if (crtc->pipe == PIPE_B)
7376                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7377         dpll |= DPLL_VCO_ENABLE;
7378         pipe_config->dpll_hw_state.dpll = dpll;
7379
7380         dpll_md = (pipe_config->pixel_multiplier - 1)
7381                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7382         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7383 }
7384
7385 static void vlv_prepare_pll(struct intel_crtc *crtc,
7386                             const struct intel_crtc_state *pipe_config)
7387 {
7388         struct drm_device *dev = crtc->base.dev;
7389         struct drm_i915_private *dev_priv = dev->dev_private;
7390         int pipe = crtc->pipe;
7391         u32 mdiv;
7392         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7393         u32 coreclk, reg_val;
7394
7395         mutex_lock(&dev_priv->sb_lock);
7396
7397         bestn = pipe_config->dpll.n;
7398         bestm1 = pipe_config->dpll.m1;
7399         bestm2 = pipe_config->dpll.m2;
7400         bestp1 = pipe_config->dpll.p1;
7401         bestp2 = pipe_config->dpll.p2;
7402
7403         /* See eDP HDMI DPIO driver vbios notes doc */
7404
7405         /* PLL B needs special handling */
7406         if (pipe == PIPE_B)
7407                 vlv_pllb_recal_opamp(dev_priv, pipe);
7408
7409         /* Set up Tx target for periodic Rcomp update */
7410         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7411
7412         /* Disable target IRef on PLL */
7413         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7414         reg_val &= 0x00ffffff;
7415         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7416
7417         /* Disable fast lock */
7418         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7419
7420         /* Set idtafcrecal before PLL is enabled */
7421         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7422         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7423         mdiv |= ((bestn << DPIO_N_SHIFT));
7424         mdiv |= (1 << DPIO_K_SHIFT);
7425
7426         /*
7427          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7428          * but we don't support that).
7429          * Note: don't use the DAC post divider as it seems unstable.
7430          */
7431         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7432         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7433
7434         mdiv |= DPIO_ENABLE_CALIBRATION;
7435         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7436
7437         /* Set HBR and RBR LPF coefficients */
7438         if (pipe_config->port_clock == 162000 ||
7439             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7440             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7441                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7442                                  0x009f0003);
7443         else
7444                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7445                                  0x00d0000f);
7446
7447         if (pipe_config->has_dp_encoder) {
7448                 /* Use SSC source */
7449                 if (pipe == PIPE_A)
7450                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7451                                          0x0df40000);
7452                 else
7453                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7454                                          0x0df70000);
7455         } else { /* HDMI or VGA */
7456                 /* Use bend source */
7457                 if (pipe == PIPE_A)
7458                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7459                                          0x0df70000);
7460                 else
7461                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7462                                          0x0df40000);
7463         }
7464
7465         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7466         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7467         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7468             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7469                 coreclk |= 0x01000000;
7470         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7471
7472         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7473         mutex_unlock(&dev_priv->sb_lock);
7474 }
7475
7476 static void chv_compute_dpll(struct intel_crtc *crtc,
7477                              struct intel_crtc_state *pipe_config)
7478 {
7479         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7480                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7481                 DPLL_VCO_ENABLE;
7482         if (crtc->pipe != PIPE_A)
7483                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7484
7485         pipe_config->dpll_hw_state.dpll_md =
7486                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7487 }
7488
7489 static void chv_prepare_pll(struct intel_crtc *crtc,
7490                             const struct intel_crtc_state *pipe_config)
7491 {
7492         struct drm_device *dev = crtc->base.dev;
7493         struct drm_i915_private *dev_priv = dev->dev_private;
7494         int pipe = crtc->pipe;
7495         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7496         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7497         u32 loopfilter, tribuf_calcntr;
7498         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7499         u32 dpio_val;
7500         int vco;
7501
7502         bestn = pipe_config->dpll.n;
7503         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7504         bestm1 = pipe_config->dpll.m1;
7505         bestm2 = pipe_config->dpll.m2 >> 22;
7506         bestp1 = pipe_config->dpll.p1;
7507         bestp2 = pipe_config->dpll.p2;
7508         vco = pipe_config->dpll.vco;
7509         dpio_val = 0;
7510         loopfilter = 0;
7511
7512         /*
7513          * Enable Refclk and SSC
7514          */
7515         I915_WRITE(dpll_reg,
7516                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7517
7518         mutex_lock(&dev_priv->sb_lock);
7519
7520         /* p1 and p2 divider */
7521         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7522                         5 << DPIO_CHV_S1_DIV_SHIFT |
7523                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7524                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7525                         1 << DPIO_CHV_K_DIV_SHIFT);
7526
7527         /* Feedback post-divider - m2 */
7528         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7529
7530         /* Feedback refclk divider - n and m1 */
7531         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7532                         DPIO_CHV_M1_DIV_BY_2 |
7533                         1 << DPIO_CHV_N_DIV_SHIFT);
7534
7535         /* M2 fraction division */
7536         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7537
7538         /* M2 fraction division enable */
7539         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7540         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7541         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7542         if (bestm2_frac)
7543                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7544         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7545
7546         /* Program digital lock detect threshold */
7547         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7548         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7549                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7550         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7551         if (!bestm2_frac)
7552                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7553         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7554
7555         /* Loop filter */
7556         if (vco == 5400000) {
7557                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7558                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7559                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7560                 tribuf_calcntr = 0x9;
7561         } else if (vco <= 6200000) {
7562                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7563                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7564                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7565                 tribuf_calcntr = 0x9;
7566         } else if (vco <= 6480000) {
7567                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7568                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7569                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7570                 tribuf_calcntr = 0x8;
7571         } else {
7572                 /* Not supported. Apply the same limits as in the max case */
7573                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7574                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7575                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7576                 tribuf_calcntr = 0;
7577         }
7578         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7579
7580         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7581         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7582         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7583         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7584
7585         /* AFC Recal */
7586         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7587                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7588                         DPIO_AFC_RECAL);
7589
7590         mutex_unlock(&dev_priv->sb_lock);
7591 }
7592
7593 /**
7594  * vlv_force_pll_on - forcibly enable just the PLL
7595  * @dev_priv: i915 private structure
7596  * @pipe: pipe PLL to enable
7597  * @dpll: PLL configuration
7598  *
7599  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7600  * in cases where we need the PLL enabled even when @pipe is not going to
7601  * be enabled.
7602  */
7603 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7604                      const struct dpll *dpll)
7605 {
7606         struct intel_crtc *crtc =
7607                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7608         struct intel_crtc_state *pipe_config;
7609
7610         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7611         if (!pipe_config)
7612                 return -ENOMEM;
7613
7614         pipe_config->base.crtc = &crtc->base;
7615         pipe_config->pixel_multiplier = 1;
7616         pipe_config->dpll = *dpll;
7617
7618         if (IS_CHERRYVIEW(dev)) {
7619                 chv_compute_dpll(crtc, pipe_config);
7620                 chv_prepare_pll(crtc, pipe_config);
7621                 chv_enable_pll(crtc, pipe_config);
7622         } else {
7623                 vlv_compute_dpll(crtc, pipe_config);
7624                 vlv_prepare_pll(crtc, pipe_config);
7625                 vlv_enable_pll(crtc, pipe_config);
7626         }
7627
7628         kfree(pipe_config);
7629
7630         return 0;
7631 }
7632
7633 /**
7634  * vlv_force_pll_off - forcibly disable just the PLL
7635  * @dev_priv: i915 private structure
7636  * @pipe: pipe PLL to disable
7637  *
7638  * Disable the PLL for @pipe. To be used in cases where we need
7639  * the PLL enabled even when @pipe is not going to be enabled.
7640  */
7641 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7642 {
7643         if (IS_CHERRYVIEW(dev))
7644                 chv_disable_pll(to_i915(dev), pipe);
7645         else
7646                 vlv_disable_pll(to_i915(dev), pipe);
7647 }
7648
7649 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7650                               struct intel_crtc_state *crtc_state,
7651                               intel_clock_t *reduced_clock,
7652                               int num_connectors)
7653 {
7654         struct drm_device *dev = crtc->base.dev;
7655         struct drm_i915_private *dev_priv = dev->dev_private;
7656         u32 dpll;
7657         bool is_sdvo;
7658         struct dpll *clock = &crtc_state->dpll;
7659
7660         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7661
7662         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7663                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7664
7665         dpll = DPLL_VGA_MODE_DIS;
7666
7667         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7668                 dpll |= DPLLB_MODE_LVDS;
7669         else
7670                 dpll |= DPLLB_MODE_DAC_SERIAL;
7671
7672         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7673                 dpll |= (crtc_state->pixel_multiplier - 1)
7674                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7675         }
7676
7677         if (is_sdvo)
7678                 dpll |= DPLL_SDVO_HIGH_SPEED;
7679
7680         if (crtc_state->has_dp_encoder)
7681                 dpll |= DPLL_SDVO_HIGH_SPEED;
7682
7683         /* compute bitmask from p1 value */
7684         if (IS_PINEVIEW(dev))
7685                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7686         else {
7687                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7688                 if (IS_G4X(dev) && reduced_clock)
7689                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7690         }
7691         switch (clock->p2) {
7692         case 5:
7693                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7694                 break;
7695         case 7:
7696                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7697                 break;
7698         case 10:
7699                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7700                 break;
7701         case 14:
7702                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7703                 break;
7704         }
7705         if (INTEL_INFO(dev)->gen >= 4)
7706                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7707
7708         if (crtc_state->sdvo_tv_clock)
7709                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7710         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7711                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7712                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7713         else
7714                 dpll |= PLL_REF_INPUT_DREFCLK;
7715
7716         dpll |= DPLL_VCO_ENABLE;
7717         crtc_state->dpll_hw_state.dpll = dpll;
7718
7719         if (INTEL_INFO(dev)->gen >= 4) {
7720                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7721                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7722                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7723         }
7724 }
7725
7726 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7727                               struct intel_crtc_state *crtc_state,
7728                               intel_clock_t *reduced_clock,
7729                               int num_connectors)
7730 {
7731         struct drm_device *dev = crtc->base.dev;
7732         struct drm_i915_private *dev_priv = dev->dev_private;
7733         u32 dpll;
7734         struct dpll *clock = &crtc_state->dpll;
7735
7736         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7737
7738         dpll = DPLL_VGA_MODE_DIS;
7739
7740         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7741                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7742         } else {
7743                 if (clock->p1 == 2)
7744                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7745                 else
7746                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7747                 if (clock->p2 == 4)
7748                         dpll |= PLL_P2_DIVIDE_BY_4;
7749         }
7750
7751         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7752                 dpll |= DPLL_DVO_2X_MODE;
7753
7754         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7755                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7756                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7757         else
7758                 dpll |= PLL_REF_INPUT_DREFCLK;
7759
7760         dpll |= DPLL_VCO_ENABLE;
7761         crtc_state->dpll_hw_state.dpll = dpll;
7762 }
7763
7764 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7765 {
7766         struct drm_device *dev = intel_crtc->base.dev;
7767         struct drm_i915_private *dev_priv = dev->dev_private;
7768         enum pipe pipe = intel_crtc->pipe;
7769         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7770         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7771         uint32_t crtc_vtotal, crtc_vblank_end;
7772         int vsyncshift = 0;
7773
7774         /* We need to be careful not to changed the adjusted mode, for otherwise
7775          * the hw state checker will get angry at the mismatch. */
7776         crtc_vtotal = adjusted_mode->crtc_vtotal;
7777         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7778
7779         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7780                 /* the chip adds 2 halflines automatically */
7781                 crtc_vtotal -= 1;
7782                 crtc_vblank_end -= 1;
7783
7784                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7785                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7786                 else
7787                         vsyncshift = adjusted_mode->crtc_hsync_start -
7788                                 adjusted_mode->crtc_htotal / 2;
7789                 if (vsyncshift < 0)
7790                         vsyncshift += adjusted_mode->crtc_htotal;
7791         }
7792
7793         if (INTEL_INFO(dev)->gen > 3)
7794                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7795
7796         I915_WRITE(HTOTAL(cpu_transcoder),
7797                    (adjusted_mode->crtc_hdisplay - 1) |
7798                    ((adjusted_mode->crtc_htotal - 1) << 16));
7799         I915_WRITE(HBLANK(cpu_transcoder),
7800                    (adjusted_mode->crtc_hblank_start - 1) |
7801                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7802         I915_WRITE(HSYNC(cpu_transcoder),
7803                    (adjusted_mode->crtc_hsync_start - 1) |
7804                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7805
7806         I915_WRITE(VTOTAL(cpu_transcoder),
7807                    (adjusted_mode->crtc_vdisplay - 1) |
7808                    ((crtc_vtotal - 1) << 16));
7809         I915_WRITE(VBLANK(cpu_transcoder),
7810                    (adjusted_mode->crtc_vblank_start - 1) |
7811                    ((crtc_vblank_end - 1) << 16));
7812         I915_WRITE(VSYNC(cpu_transcoder),
7813                    (adjusted_mode->crtc_vsync_start - 1) |
7814                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7815
7816         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7817          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7818          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7819          * bits. */
7820         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7821             (pipe == PIPE_B || pipe == PIPE_C))
7822                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7823
7824         /* pipesrc controls the size that is scaled from, which should
7825          * always be the user's requested size.
7826          */
7827         I915_WRITE(PIPESRC(pipe),
7828                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7829                    (intel_crtc->config->pipe_src_h - 1));
7830 }
7831
7832 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7833                                    struct intel_crtc_state *pipe_config)
7834 {
7835         struct drm_device *dev = crtc->base.dev;
7836         struct drm_i915_private *dev_priv = dev->dev_private;
7837         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7838         uint32_t tmp;
7839
7840         tmp = I915_READ(HTOTAL(cpu_transcoder));
7841         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7842         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7843         tmp = I915_READ(HBLANK(cpu_transcoder));
7844         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7845         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7846         tmp = I915_READ(HSYNC(cpu_transcoder));
7847         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7848         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7849
7850         tmp = I915_READ(VTOTAL(cpu_transcoder));
7851         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7852         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7853         tmp = I915_READ(VBLANK(cpu_transcoder));
7854         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7855         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7856         tmp = I915_READ(VSYNC(cpu_transcoder));
7857         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7858         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7859
7860         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7861                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7862                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7863                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7864         }
7865
7866         tmp = I915_READ(PIPESRC(crtc->pipe));
7867         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7868         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7869
7870         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7871         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7872 }
7873
7874 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7875                                  struct intel_crtc_state *pipe_config)
7876 {
7877         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7878         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7879         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7880         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7881
7882         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7883         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7884         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7885         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7886
7887         mode->flags = pipe_config->base.adjusted_mode.flags;
7888         mode->type = DRM_MODE_TYPE_DRIVER;
7889
7890         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7891         mode->flags |= pipe_config->base.adjusted_mode.flags;
7892
7893         mode->hsync = drm_mode_hsync(mode);
7894         mode->vrefresh = drm_mode_vrefresh(mode);
7895         drm_mode_set_name(mode);
7896 }
7897
7898 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7899 {
7900         struct drm_device *dev = intel_crtc->base.dev;
7901         struct drm_i915_private *dev_priv = dev->dev_private;
7902         uint32_t pipeconf;
7903
7904         pipeconf = 0;
7905
7906         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7907             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7908                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7909
7910         if (intel_crtc->config->double_wide)
7911                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7912
7913         /* only g4x and later have fancy bpc/dither controls */
7914         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7915                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7916                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7917                         pipeconf |= PIPECONF_DITHER_EN |
7918                                     PIPECONF_DITHER_TYPE_SP;
7919
7920                 switch (intel_crtc->config->pipe_bpp) {
7921                 case 18:
7922                         pipeconf |= PIPECONF_6BPC;
7923                         break;
7924                 case 24:
7925                         pipeconf |= PIPECONF_8BPC;
7926                         break;
7927                 case 30:
7928                         pipeconf |= PIPECONF_10BPC;
7929                         break;
7930                 default:
7931                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7932                         BUG();
7933                 }
7934         }
7935
7936         if (HAS_PIPE_CXSR(dev)) {
7937                 if (intel_crtc->lowfreq_avail) {
7938                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7939                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7940                 } else {
7941                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7942                 }
7943         }
7944
7945         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7946                 if (INTEL_INFO(dev)->gen < 4 ||
7947                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7948                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7949                 else
7950                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7951         } else
7952                 pipeconf |= PIPECONF_PROGRESSIVE;
7953
7954         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7955              intel_crtc->config->limited_color_range)
7956                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7957
7958         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7959         POSTING_READ(PIPECONF(intel_crtc->pipe));
7960 }
7961
7962 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7963                                    struct intel_crtc_state *crtc_state)
7964 {
7965         struct drm_device *dev = crtc->base.dev;
7966         struct drm_i915_private *dev_priv = dev->dev_private;
7967         int refclk, num_connectors = 0;
7968         intel_clock_t clock;
7969         bool ok;
7970         const intel_limit_t *limit;
7971         struct drm_atomic_state *state = crtc_state->base.state;
7972         struct drm_connector *connector;
7973         struct drm_connector_state *connector_state;
7974         int i;
7975
7976         memset(&crtc_state->dpll_hw_state, 0,
7977                sizeof(crtc_state->dpll_hw_state));
7978
7979         if (crtc_state->has_dsi_encoder)
7980                 return 0;
7981
7982         for_each_connector_in_state(state, connector, connector_state, i) {
7983                 if (connector_state->crtc == &crtc->base)
7984                         num_connectors++;
7985         }
7986
7987         if (!crtc_state->clock_set) {
7988                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7989
7990                 /*
7991                  * Returns a set of divisors for the desired target clock with
7992                  * the given refclk, or FALSE.  The returned values represent
7993                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7994                  * 2) / p1 / p2.
7995                  */
7996                 limit = intel_limit(crtc_state, refclk);
7997                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7998                                                  crtc_state->port_clock,
7999                                                  refclk, NULL, &clock);
8000                 if (!ok) {
8001                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
8002                         return -EINVAL;
8003                 }
8004
8005                 /* Compat-code for transition, will disappear. */
8006                 crtc_state->dpll.n = clock.n;
8007                 crtc_state->dpll.m1 = clock.m1;
8008                 crtc_state->dpll.m2 = clock.m2;
8009                 crtc_state->dpll.p1 = clock.p1;
8010                 crtc_state->dpll.p2 = clock.p2;
8011         }
8012
8013         if (IS_GEN2(dev)) {
8014                 i8xx_compute_dpll(crtc, crtc_state, NULL,
8015                                   num_connectors);
8016         } else if (IS_CHERRYVIEW(dev)) {
8017                 chv_compute_dpll(crtc, crtc_state);
8018         } else if (IS_VALLEYVIEW(dev)) {
8019                 vlv_compute_dpll(crtc, crtc_state);
8020         } else {
8021                 i9xx_compute_dpll(crtc, crtc_state, NULL,
8022                                   num_connectors);
8023         }
8024
8025         return 0;
8026 }
8027
8028 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8029                                  struct intel_crtc_state *pipe_config)
8030 {
8031         struct drm_device *dev = crtc->base.dev;
8032         struct drm_i915_private *dev_priv = dev->dev_private;
8033         uint32_t tmp;
8034
8035         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8036                 return;
8037
8038         tmp = I915_READ(PFIT_CONTROL);
8039         if (!(tmp & PFIT_ENABLE))
8040                 return;
8041
8042         /* Check whether the pfit is attached to our pipe. */
8043         if (INTEL_INFO(dev)->gen < 4) {
8044                 if (crtc->pipe != PIPE_B)
8045                         return;
8046         } else {
8047                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8048                         return;
8049         }
8050
8051         pipe_config->gmch_pfit.control = tmp;
8052         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8053         if (INTEL_INFO(dev)->gen < 5)
8054                 pipe_config->gmch_pfit.lvds_border_bits =
8055                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8056 }
8057
8058 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8059                                struct intel_crtc_state *pipe_config)
8060 {
8061         struct drm_device *dev = crtc->base.dev;
8062         struct drm_i915_private *dev_priv = dev->dev_private;
8063         int pipe = pipe_config->cpu_transcoder;
8064         intel_clock_t clock;
8065         u32 mdiv;
8066         int refclk = 100000;
8067
8068         /* In case of MIPI DPLL will not even be used */
8069         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8070                 return;
8071
8072         mutex_lock(&dev_priv->sb_lock);
8073         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8074         mutex_unlock(&dev_priv->sb_lock);
8075
8076         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8077         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8078         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8079         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8080         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8081
8082         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8083 }
8084
8085 static void
8086 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8087                               struct intel_initial_plane_config *plane_config)
8088 {
8089         struct drm_device *dev = crtc->base.dev;
8090         struct drm_i915_private *dev_priv = dev->dev_private;
8091         u32 val, base, offset;
8092         int pipe = crtc->pipe, plane = crtc->plane;
8093         int fourcc, pixel_format;
8094         unsigned int aligned_height;
8095         struct drm_framebuffer *fb;
8096         struct intel_framebuffer *intel_fb;
8097
8098         val = I915_READ(DSPCNTR(plane));
8099         if (!(val & DISPLAY_PLANE_ENABLE))
8100                 return;
8101
8102         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8103         if (!intel_fb) {
8104                 DRM_DEBUG_KMS("failed to alloc fb\n");
8105                 return;
8106         }
8107
8108         fb = &intel_fb->base;
8109
8110         if (INTEL_INFO(dev)->gen >= 4) {
8111                 if (val & DISPPLANE_TILED) {
8112                         plane_config->tiling = I915_TILING_X;
8113                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8114                 }
8115         }
8116
8117         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8118         fourcc = i9xx_format_to_fourcc(pixel_format);
8119         fb->pixel_format = fourcc;
8120         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8121
8122         if (INTEL_INFO(dev)->gen >= 4) {
8123                 if (plane_config->tiling)
8124                         offset = I915_READ(DSPTILEOFF(plane));
8125                 else
8126                         offset = I915_READ(DSPLINOFF(plane));
8127                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8128         } else {
8129                 base = I915_READ(DSPADDR(plane));
8130         }
8131         plane_config->base = base;
8132
8133         val = I915_READ(PIPESRC(pipe));
8134         fb->width = ((val >> 16) & 0xfff) + 1;
8135         fb->height = ((val >> 0) & 0xfff) + 1;
8136
8137         val = I915_READ(DSPSTRIDE(pipe));
8138         fb->pitches[0] = val & 0xffffffc0;
8139
8140         aligned_height = intel_fb_align_height(dev, fb->height,
8141                                                fb->pixel_format,
8142                                                fb->modifier[0]);
8143
8144         plane_config->size = fb->pitches[0] * aligned_height;
8145
8146         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8147                       pipe_name(pipe), plane, fb->width, fb->height,
8148                       fb->bits_per_pixel, base, fb->pitches[0],
8149                       plane_config->size);
8150
8151         plane_config->fb = intel_fb;
8152 }
8153
8154 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8155                                struct intel_crtc_state *pipe_config)
8156 {
8157         struct drm_device *dev = crtc->base.dev;
8158         struct drm_i915_private *dev_priv = dev->dev_private;
8159         int pipe = pipe_config->cpu_transcoder;
8160         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8161         intel_clock_t clock;
8162         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8163         int refclk = 100000;
8164
8165         mutex_lock(&dev_priv->sb_lock);
8166         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8167         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8168         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8169         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8170         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8171         mutex_unlock(&dev_priv->sb_lock);
8172
8173         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8174         clock.m2 = (pll_dw0 & 0xff) << 22;
8175         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8176                 clock.m2 |= pll_dw2 & 0x3fffff;
8177         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8178         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8179         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8180
8181         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8182 }
8183
8184 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8185                                  struct intel_crtc_state *pipe_config)
8186 {
8187         struct drm_device *dev = crtc->base.dev;
8188         struct drm_i915_private *dev_priv = dev->dev_private;
8189         uint32_t tmp;
8190
8191         if (!intel_display_power_is_enabled(dev_priv,
8192                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8193                 return false;
8194
8195         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8196         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8197
8198         tmp = I915_READ(PIPECONF(crtc->pipe));
8199         if (!(tmp & PIPECONF_ENABLE))
8200                 return false;
8201
8202         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8203                 switch (tmp & PIPECONF_BPC_MASK) {
8204                 case PIPECONF_6BPC:
8205                         pipe_config->pipe_bpp = 18;
8206                         break;
8207                 case PIPECONF_8BPC:
8208                         pipe_config->pipe_bpp = 24;
8209                         break;
8210                 case PIPECONF_10BPC:
8211                         pipe_config->pipe_bpp = 30;
8212                         break;
8213                 default:
8214                         break;
8215                 }
8216         }
8217
8218         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8219             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8220                 pipe_config->limited_color_range = true;
8221
8222         if (INTEL_INFO(dev)->gen < 4)
8223                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8224
8225         intel_get_pipe_timings(crtc, pipe_config);
8226
8227         i9xx_get_pfit_config(crtc, pipe_config);
8228
8229         if (INTEL_INFO(dev)->gen >= 4) {
8230                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8231                 pipe_config->pixel_multiplier =
8232                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8233                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8234                 pipe_config->dpll_hw_state.dpll_md = tmp;
8235         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8236                 tmp = I915_READ(DPLL(crtc->pipe));
8237                 pipe_config->pixel_multiplier =
8238                         ((tmp & SDVO_MULTIPLIER_MASK)
8239                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8240         } else {
8241                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8242                  * port and will be fixed up in the encoder->get_config
8243                  * function. */
8244                 pipe_config->pixel_multiplier = 1;
8245         }
8246         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8247         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8248                 /*
8249                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8250                  * on 830. Filter it out here so that we don't
8251                  * report errors due to that.
8252                  */
8253                 if (IS_I830(dev))
8254                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8255
8256                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8257                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8258         } else {
8259                 /* Mask out read-only status bits. */
8260                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8261                                                      DPLL_PORTC_READY_MASK |
8262                                                      DPLL_PORTB_READY_MASK);
8263         }
8264
8265         if (IS_CHERRYVIEW(dev))
8266                 chv_crtc_clock_get(crtc, pipe_config);
8267         else if (IS_VALLEYVIEW(dev))
8268                 vlv_crtc_clock_get(crtc, pipe_config);
8269         else
8270                 i9xx_crtc_clock_get(crtc, pipe_config);
8271
8272         /*
8273          * Normally the dotclock is filled in by the encoder .get_config()
8274          * but in case the pipe is enabled w/o any ports we need a sane
8275          * default.
8276          */
8277         pipe_config->base.adjusted_mode.crtc_clock =
8278                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8279
8280         return true;
8281 }
8282
8283 static void ironlake_init_pch_refclk(struct drm_device *dev)
8284 {
8285         struct drm_i915_private *dev_priv = dev->dev_private;
8286         struct intel_encoder *encoder;
8287         u32 val, final;
8288         bool has_lvds = false;
8289         bool has_cpu_edp = false;
8290         bool has_panel = false;
8291         bool has_ck505 = false;
8292         bool can_ssc = false;
8293
8294         /* We need to take the global config into account */
8295         for_each_intel_encoder(dev, encoder) {
8296                 switch (encoder->type) {
8297                 case INTEL_OUTPUT_LVDS:
8298                         has_panel = true;
8299                         has_lvds = true;
8300                         break;
8301                 case INTEL_OUTPUT_EDP:
8302                         has_panel = true;
8303                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8304                                 has_cpu_edp = true;
8305                         break;
8306                 default:
8307                         break;
8308                 }
8309         }
8310
8311         if (HAS_PCH_IBX(dev)) {
8312                 has_ck505 = dev_priv->vbt.display_clock_mode;
8313                 can_ssc = has_ck505;
8314         } else {
8315                 has_ck505 = false;
8316                 can_ssc = true;
8317         }
8318
8319         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8320                       has_panel, has_lvds, has_ck505);
8321
8322         /* Ironlake: try to setup display ref clock before DPLL
8323          * enabling. This is only under driver's control after
8324          * PCH B stepping, previous chipset stepping should be
8325          * ignoring this setting.
8326          */
8327         val = I915_READ(PCH_DREF_CONTROL);
8328
8329         /* As we must carefully and slowly disable/enable each source in turn,
8330          * compute the final state we want first and check if we need to
8331          * make any changes at all.
8332          */
8333         final = val;
8334         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8335         if (has_ck505)
8336                 final |= DREF_NONSPREAD_CK505_ENABLE;
8337         else
8338                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8339
8340         final &= ~DREF_SSC_SOURCE_MASK;
8341         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8342         final &= ~DREF_SSC1_ENABLE;
8343
8344         if (has_panel) {
8345                 final |= DREF_SSC_SOURCE_ENABLE;
8346
8347                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8348                         final |= DREF_SSC1_ENABLE;
8349
8350                 if (has_cpu_edp) {
8351                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8352                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8353                         else
8354                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8355                 } else
8356                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8357         } else {
8358                 final |= DREF_SSC_SOURCE_DISABLE;
8359                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8360         }
8361
8362         if (final == val)
8363                 return;
8364
8365         /* Always enable nonspread source */
8366         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8367
8368         if (has_ck505)
8369                 val |= DREF_NONSPREAD_CK505_ENABLE;
8370         else
8371                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8372
8373         if (has_panel) {
8374                 val &= ~DREF_SSC_SOURCE_MASK;
8375                 val |= DREF_SSC_SOURCE_ENABLE;
8376
8377                 /* SSC must be turned on before enabling the CPU output  */
8378                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8379                         DRM_DEBUG_KMS("Using SSC on panel\n");
8380                         val |= DREF_SSC1_ENABLE;
8381                 } else
8382                         val &= ~DREF_SSC1_ENABLE;
8383
8384                 /* Get SSC going before enabling the outputs */
8385                 I915_WRITE(PCH_DREF_CONTROL, val);
8386                 POSTING_READ(PCH_DREF_CONTROL);
8387                 udelay(200);
8388
8389                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8390
8391                 /* Enable CPU source on CPU attached eDP */
8392                 if (has_cpu_edp) {
8393                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8394                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8395                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8396                         } else
8397                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8398                 } else
8399                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8400
8401                 I915_WRITE(PCH_DREF_CONTROL, val);
8402                 POSTING_READ(PCH_DREF_CONTROL);
8403                 udelay(200);
8404         } else {
8405                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8406
8407                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8408
8409                 /* Turn off CPU output */
8410                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8411
8412                 I915_WRITE(PCH_DREF_CONTROL, val);
8413                 POSTING_READ(PCH_DREF_CONTROL);
8414                 udelay(200);
8415
8416                 /* Turn off the SSC source */
8417                 val &= ~DREF_SSC_SOURCE_MASK;
8418                 val |= DREF_SSC_SOURCE_DISABLE;
8419
8420                 /* Turn off SSC1 */
8421                 val &= ~DREF_SSC1_ENABLE;
8422
8423                 I915_WRITE(PCH_DREF_CONTROL, val);
8424                 POSTING_READ(PCH_DREF_CONTROL);
8425                 udelay(200);
8426         }
8427
8428         BUG_ON(val != final);
8429 }
8430
8431 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8432 {
8433         uint32_t tmp;
8434
8435         tmp = I915_READ(SOUTH_CHICKEN2);
8436         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8437         I915_WRITE(SOUTH_CHICKEN2, tmp);
8438
8439         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8440                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8441                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8442
8443         tmp = I915_READ(SOUTH_CHICKEN2);
8444         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8445         I915_WRITE(SOUTH_CHICKEN2, tmp);
8446
8447         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8448                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8449                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8450 }
8451
8452 /* WaMPhyProgramming:hsw */
8453 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8454 {
8455         uint32_t tmp;
8456
8457         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8458         tmp &= ~(0xFF << 24);
8459         tmp |= (0x12 << 24);
8460         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8461
8462         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8463         tmp |= (1 << 11);
8464         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8465
8466         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8467         tmp |= (1 << 11);
8468         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8469
8470         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8471         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8472         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8473
8474         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8475         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8476         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8477
8478         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8479         tmp &= ~(7 << 13);
8480         tmp |= (5 << 13);
8481         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8482
8483         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8484         tmp &= ~(7 << 13);
8485         tmp |= (5 << 13);
8486         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8487
8488         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8489         tmp &= ~0xFF;
8490         tmp |= 0x1C;
8491         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8492
8493         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8494         tmp &= ~0xFF;
8495         tmp |= 0x1C;
8496         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8497
8498         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8499         tmp &= ~(0xFF << 16);
8500         tmp |= (0x1C << 16);
8501         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8502
8503         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8504         tmp &= ~(0xFF << 16);
8505         tmp |= (0x1C << 16);
8506         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8507
8508         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8509         tmp |= (1 << 27);
8510         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8511
8512         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8513         tmp |= (1 << 27);
8514         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8515
8516         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8517         tmp &= ~(0xF << 28);
8518         tmp |= (4 << 28);
8519         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8520
8521         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8522         tmp &= ~(0xF << 28);
8523         tmp |= (4 << 28);
8524         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8525 }
8526
8527 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8528  * Programming" based on the parameters passed:
8529  * - Sequence to enable CLKOUT_DP
8530  * - Sequence to enable CLKOUT_DP without spread
8531  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8532  */
8533 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8534                                  bool with_fdi)
8535 {
8536         struct drm_i915_private *dev_priv = dev->dev_private;
8537         uint32_t reg, tmp;
8538
8539         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8540                 with_spread = true;
8541         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8542                 with_fdi = false;
8543
8544         mutex_lock(&dev_priv->sb_lock);
8545
8546         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8547         tmp &= ~SBI_SSCCTL_DISABLE;
8548         tmp |= SBI_SSCCTL_PATHALT;
8549         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8550
8551         udelay(24);
8552
8553         if (with_spread) {
8554                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8555                 tmp &= ~SBI_SSCCTL_PATHALT;
8556                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8557
8558                 if (with_fdi) {
8559                         lpt_reset_fdi_mphy(dev_priv);
8560                         lpt_program_fdi_mphy(dev_priv);
8561                 }
8562         }
8563
8564         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8565         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8566         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8567         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8568
8569         mutex_unlock(&dev_priv->sb_lock);
8570 }
8571
8572 /* Sequence to disable CLKOUT_DP */
8573 static void lpt_disable_clkout_dp(struct drm_device *dev)
8574 {
8575         struct drm_i915_private *dev_priv = dev->dev_private;
8576         uint32_t reg, tmp;
8577
8578         mutex_lock(&dev_priv->sb_lock);
8579
8580         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8581         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8582         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8583         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8584
8585         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8586         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8587                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8588                         tmp |= SBI_SSCCTL_PATHALT;
8589                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8590                         udelay(32);
8591                 }
8592                 tmp |= SBI_SSCCTL_DISABLE;
8593                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8594         }
8595
8596         mutex_unlock(&dev_priv->sb_lock);
8597 }
8598
8599 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8600
8601 static const uint16_t sscdivintphase[] = {
8602         [BEND_IDX( 50)] = 0x3B23,
8603         [BEND_IDX( 45)] = 0x3B23,
8604         [BEND_IDX( 40)] = 0x3C23,
8605         [BEND_IDX( 35)] = 0x3C23,
8606         [BEND_IDX( 30)] = 0x3D23,
8607         [BEND_IDX( 25)] = 0x3D23,
8608         [BEND_IDX( 20)] = 0x3E23,
8609         [BEND_IDX( 15)] = 0x3E23,
8610         [BEND_IDX( 10)] = 0x3F23,
8611         [BEND_IDX(  5)] = 0x3F23,
8612         [BEND_IDX(  0)] = 0x0025,
8613         [BEND_IDX( -5)] = 0x0025,
8614         [BEND_IDX(-10)] = 0x0125,
8615         [BEND_IDX(-15)] = 0x0125,
8616         [BEND_IDX(-20)] = 0x0225,
8617         [BEND_IDX(-25)] = 0x0225,
8618         [BEND_IDX(-30)] = 0x0325,
8619         [BEND_IDX(-35)] = 0x0325,
8620         [BEND_IDX(-40)] = 0x0425,
8621         [BEND_IDX(-45)] = 0x0425,
8622         [BEND_IDX(-50)] = 0x0525,
8623 };
8624
8625 /*
8626  * Bend CLKOUT_DP
8627  * steps -50 to 50 inclusive, in steps of 5
8628  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8629  * change in clock period = -(steps / 10) * 5.787 ps
8630  */
8631 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8632 {
8633         uint32_t tmp;
8634         int idx = BEND_IDX(steps);
8635
8636         if (WARN_ON(steps % 5 != 0))
8637                 return;
8638
8639         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8640                 return;
8641
8642         mutex_lock(&dev_priv->sb_lock);
8643
8644         if (steps % 10 != 0)
8645                 tmp = 0xAAAAAAAB;
8646         else
8647                 tmp = 0x00000000;
8648         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8649
8650         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8651         tmp &= 0xffff0000;
8652         tmp |= sscdivintphase[idx];
8653         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8654
8655         mutex_unlock(&dev_priv->sb_lock);
8656 }
8657
8658 #undef BEND_IDX
8659
8660 static void lpt_init_pch_refclk(struct drm_device *dev)
8661 {
8662         struct intel_encoder *encoder;
8663         bool has_vga = false;
8664
8665         for_each_intel_encoder(dev, encoder) {
8666                 switch (encoder->type) {
8667                 case INTEL_OUTPUT_ANALOG:
8668                         has_vga = true;
8669                         break;
8670                 default:
8671                         break;
8672                 }
8673         }
8674
8675         if (has_vga) {
8676                 lpt_bend_clkout_dp(to_i915(dev), 0);
8677                 lpt_enable_clkout_dp(dev, true, true);
8678         } else {
8679                 lpt_disable_clkout_dp(dev);
8680         }
8681 }
8682
8683 /*
8684  * Initialize reference clocks when the driver loads
8685  */
8686 void intel_init_pch_refclk(struct drm_device *dev)
8687 {
8688         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8689                 ironlake_init_pch_refclk(dev);
8690         else if (HAS_PCH_LPT(dev))
8691                 lpt_init_pch_refclk(dev);
8692 }
8693
8694 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8695 {
8696         struct drm_device *dev = crtc_state->base.crtc->dev;
8697         struct drm_i915_private *dev_priv = dev->dev_private;
8698         struct drm_atomic_state *state = crtc_state->base.state;
8699         struct drm_connector *connector;
8700         struct drm_connector_state *connector_state;
8701         struct intel_encoder *encoder;
8702         int num_connectors = 0, i;
8703         bool is_lvds = false;
8704
8705         for_each_connector_in_state(state, connector, connector_state, i) {
8706                 if (connector_state->crtc != crtc_state->base.crtc)
8707                         continue;
8708
8709                 encoder = to_intel_encoder(connector_state->best_encoder);
8710
8711                 switch (encoder->type) {
8712                 case INTEL_OUTPUT_LVDS:
8713                         is_lvds = true;
8714                         break;
8715                 default:
8716                         break;
8717                 }
8718                 num_connectors++;
8719         }
8720
8721         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8722                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8723                               dev_priv->vbt.lvds_ssc_freq);
8724                 return dev_priv->vbt.lvds_ssc_freq;
8725         }
8726
8727         return 120000;
8728 }
8729
8730 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8731 {
8732         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8734         int pipe = intel_crtc->pipe;
8735         uint32_t val;
8736
8737         val = 0;
8738
8739         switch (intel_crtc->config->pipe_bpp) {
8740         case 18:
8741                 val |= PIPECONF_6BPC;
8742                 break;
8743         case 24:
8744                 val |= PIPECONF_8BPC;
8745                 break;
8746         case 30:
8747                 val |= PIPECONF_10BPC;
8748                 break;
8749         case 36:
8750                 val |= PIPECONF_12BPC;
8751                 break;
8752         default:
8753                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8754                 BUG();
8755         }
8756
8757         if (intel_crtc->config->dither)
8758                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8759
8760         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8761                 val |= PIPECONF_INTERLACED_ILK;
8762         else
8763                 val |= PIPECONF_PROGRESSIVE;
8764
8765         if (intel_crtc->config->limited_color_range)
8766                 val |= PIPECONF_COLOR_RANGE_SELECT;
8767
8768         I915_WRITE(PIPECONF(pipe), val);
8769         POSTING_READ(PIPECONF(pipe));
8770 }
8771
8772 /*
8773  * Set up the pipe CSC unit.
8774  *
8775  * Currently only full range RGB to limited range RGB conversion
8776  * is supported, but eventually this should handle various
8777  * RGB<->YCbCr scenarios as well.
8778  */
8779 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8780 {
8781         struct drm_device *dev = crtc->dev;
8782         struct drm_i915_private *dev_priv = dev->dev_private;
8783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8784         int pipe = intel_crtc->pipe;
8785         uint16_t coeff = 0x7800; /* 1.0 */
8786
8787         /*
8788          * TODO: Check what kind of values actually come out of the pipe
8789          * with these coeff/postoff values and adjust to get the best
8790          * accuracy. Perhaps we even need to take the bpc value into
8791          * consideration.
8792          */
8793
8794         if (intel_crtc->config->limited_color_range)
8795                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8796
8797         /*
8798          * GY/GU and RY/RU should be the other way around according
8799          * to BSpec, but reality doesn't agree. Just set them up in
8800          * a way that results in the correct picture.
8801          */
8802         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8803         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8804
8805         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8806         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8807
8808         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8809         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8810
8811         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8812         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8813         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8814
8815         if (INTEL_INFO(dev)->gen > 6) {
8816                 uint16_t postoff = 0;
8817
8818                 if (intel_crtc->config->limited_color_range)
8819                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8820
8821                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8822                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8823                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8824
8825                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8826         } else {
8827                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8828
8829                 if (intel_crtc->config->limited_color_range)
8830                         mode |= CSC_BLACK_SCREEN_OFFSET;
8831
8832                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8833         }
8834 }
8835
8836 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8837 {
8838         struct drm_device *dev = crtc->dev;
8839         struct drm_i915_private *dev_priv = dev->dev_private;
8840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8841         enum pipe pipe = intel_crtc->pipe;
8842         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8843         uint32_t val;
8844
8845         val = 0;
8846
8847         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8848                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8849
8850         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8851                 val |= PIPECONF_INTERLACED_ILK;
8852         else
8853                 val |= PIPECONF_PROGRESSIVE;
8854
8855         I915_WRITE(PIPECONF(cpu_transcoder), val);
8856         POSTING_READ(PIPECONF(cpu_transcoder));
8857
8858         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8859         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8860
8861         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8862                 val = 0;
8863
8864                 switch (intel_crtc->config->pipe_bpp) {
8865                 case 18:
8866                         val |= PIPEMISC_DITHER_6_BPC;
8867                         break;
8868                 case 24:
8869                         val |= PIPEMISC_DITHER_8_BPC;
8870                         break;
8871                 case 30:
8872                         val |= PIPEMISC_DITHER_10_BPC;
8873                         break;
8874                 case 36:
8875                         val |= PIPEMISC_DITHER_12_BPC;
8876                         break;
8877                 default:
8878                         /* Case prevented by pipe_config_set_bpp. */
8879                         BUG();
8880                 }
8881
8882                 if (intel_crtc->config->dither)
8883                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8884
8885                 I915_WRITE(PIPEMISC(pipe), val);
8886         }
8887 }
8888
8889 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8890                                     struct intel_crtc_state *crtc_state,
8891                                     intel_clock_t *clock,
8892                                     bool *has_reduced_clock,
8893                                     intel_clock_t *reduced_clock)
8894 {
8895         struct drm_device *dev = crtc->dev;
8896         struct drm_i915_private *dev_priv = dev->dev_private;
8897         int refclk;
8898         const intel_limit_t *limit;
8899         bool ret;
8900
8901         refclk = ironlake_get_refclk(crtc_state);
8902
8903         /*
8904          * Returns a set of divisors for the desired target clock with the given
8905          * refclk, or FALSE.  The returned values represent the clock equation:
8906          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8907          */
8908         limit = intel_limit(crtc_state, refclk);
8909         ret = dev_priv->display.find_dpll(limit, crtc_state,
8910                                           crtc_state->port_clock,
8911                                           refclk, NULL, clock);
8912         if (!ret)
8913                 return false;
8914
8915         return true;
8916 }
8917
8918 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8919 {
8920         /*
8921          * Account for spread spectrum to avoid
8922          * oversubscribing the link. Max center spread
8923          * is 2.5%; use 5% for safety's sake.
8924          */
8925         u32 bps = target_clock * bpp * 21 / 20;
8926         return DIV_ROUND_UP(bps, link_bw * 8);
8927 }
8928
8929 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8930 {
8931         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8932 }
8933
8934 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8935                                       struct intel_crtc_state *crtc_state,
8936                                       u32 *fp,
8937                                       intel_clock_t *reduced_clock, u32 *fp2)
8938 {
8939         struct drm_crtc *crtc = &intel_crtc->base;
8940         struct drm_device *dev = crtc->dev;
8941         struct drm_i915_private *dev_priv = dev->dev_private;
8942         struct drm_atomic_state *state = crtc_state->base.state;
8943         struct drm_connector *connector;
8944         struct drm_connector_state *connector_state;
8945         struct intel_encoder *encoder;
8946         uint32_t dpll;
8947         int factor, num_connectors = 0, i;
8948         bool is_lvds = false, is_sdvo = false;
8949
8950         for_each_connector_in_state(state, connector, connector_state, i) {
8951                 if (connector_state->crtc != crtc_state->base.crtc)
8952                         continue;
8953
8954                 encoder = to_intel_encoder(connector_state->best_encoder);
8955
8956                 switch (encoder->type) {
8957                 case INTEL_OUTPUT_LVDS:
8958                         is_lvds = true;
8959                         break;
8960                 case INTEL_OUTPUT_SDVO:
8961                 case INTEL_OUTPUT_HDMI:
8962                         is_sdvo = true;
8963                         break;
8964                 default:
8965                         break;
8966                 }
8967
8968                 num_connectors++;
8969         }
8970
8971         /* Enable autotuning of the PLL clock (if permissible) */
8972         factor = 21;
8973         if (is_lvds) {
8974                 if ((intel_panel_use_ssc(dev_priv) &&
8975                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8976                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8977                         factor = 25;
8978         } else if (crtc_state->sdvo_tv_clock)
8979                 factor = 20;
8980
8981         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8982                 *fp |= FP_CB_TUNE;
8983
8984         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8985                 *fp2 |= FP_CB_TUNE;
8986
8987         dpll = 0;
8988
8989         if (is_lvds)
8990                 dpll |= DPLLB_MODE_LVDS;
8991         else
8992                 dpll |= DPLLB_MODE_DAC_SERIAL;
8993
8994         dpll |= (crtc_state->pixel_multiplier - 1)
8995                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8996
8997         if (is_sdvo)
8998                 dpll |= DPLL_SDVO_HIGH_SPEED;
8999         if (crtc_state->has_dp_encoder)
9000                 dpll |= DPLL_SDVO_HIGH_SPEED;
9001
9002         /* compute bitmask from p1 value */
9003         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9004         /* also FPA1 */
9005         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9006
9007         switch (crtc_state->dpll.p2) {
9008         case 5:
9009                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9010                 break;
9011         case 7:
9012                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9013                 break;
9014         case 10:
9015                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9016                 break;
9017         case 14:
9018                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9019                 break;
9020         }
9021
9022         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
9023                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9024         else
9025                 dpll |= PLL_REF_INPUT_DREFCLK;
9026
9027         return dpll | DPLL_VCO_ENABLE;
9028 }
9029
9030 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9031                                        struct intel_crtc_state *crtc_state)
9032 {
9033         struct drm_device *dev = crtc->base.dev;
9034         intel_clock_t clock, reduced_clock;
9035         u32 dpll = 0, fp = 0, fp2 = 0;
9036         bool ok, has_reduced_clock = false;
9037         bool is_lvds = false;
9038         struct intel_shared_dpll *pll;
9039
9040         memset(&crtc_state->dpll_hw_state, 0,
9041                sizeof(crtc_state->dpll_hw_state));
9042
9043         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9044
9045         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9046              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9047
9048         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9049                                      &has_reduced_clock, &reduced_clock);
9050         if (!ok && !crtc_state->clock_set) {
9051                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9052                 return -EINVAL;
9053         }
9054         /* Compat-code for transition, will disappear. */
9055         if (!crtc_state->clock_set) {
9056                 crtc_state->dpll.n = clock.n;
9057                 crtc_state->dpll.m1 = clock.m1;
9058                 crtc_state->dpll.m2 = clock.m2;
9059                 crtc_state->dpll.p1 = clock.p1;
9060                 crtc_state->dpll.p2 = clock.p2;
9061         }
9062
9063         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9064         if (crtc_state->has_pch_encoder) {
9065                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9066                 if (has_reduced_clock)
9067                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9068
9069                 dpll = ironlake_compute_dpll(crtc, crtc_state,
9070                                              &fp, &reduced_clock,
9071                                              has_reduced_clock ? &fp2 : NULL);
9072
9073                 crtc_state->dpll_hw_state.dpll = dpll;
9074                 crtc_state->dpll_hw_state.fp0 = fp;
9075                 if (has_reduced_clock)
9076                         crtc_state->dpll_hw_state.fp1 = fp2;
9077                 else
9078                         crtc_state->dpll_hw_state.fp1 = fp;
9079
9080                 pll = intel_get_shared_dpll(crtc, crtc_state);
9081                 if (pll == NULL) {
9082                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9083                                          pipe_name(crtc->pipe));
9084                         return -EINVAL;
9085                 }
9086         }
9087
9088         if (is_lvds && has_reduced_clock)
9089                 crtc->lowfreq_avail = true;
9090         else
9091                 crtc->lowfreq_avail = false;
9092
9093         return 0;
9094 }
9095
9096 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9097                                          struct intel_link_m_n *m_n)
9098 {
9099         struct drm_device *dev = crtc->base.dev;
9100         struct drm_i915_private *dev_priv = dev->dev_private;
9101         enum pipe pipe = crtc->pipe;
9102
9103         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9104         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9105         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9106                 & ~TU_SIZE_MASK;
9107         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9108         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9109                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9110 }
9111
9112 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9113                                          enum transcoder transcoder,
9114                                          struct intel_link_m_n *m_n,
9115                                          struct intel_link_m_n *m2_n2)
9116 {
9117         struct drm_device *dev = crtc->base.dev;
9118         struct drm_i915_private *dev_priv = dev->dev_private;
9119         enum pipe pipe = crtc->pipe;
9120
9121         if (INTEL_INFO(dev)->gen >= 5) {
9122                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9123                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9124                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9125                         & ~TU_SIZE_MASK;
9126                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9127                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9128                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9129                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9130                  * gen < 8) and if DRRS is supported (to make sure the
9131                  * registers are not unnecessarily read).
9132                  */
9133                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9134                         crtc->config->has_drrs) {
9135                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9136                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9137                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9138                                         & ~TU_SIZE_MASK;
9139                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9140                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9141                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9142                 }
9143         } else {
9144                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9145                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9146                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9147                         & ~TU_SIZE_MASK;
9148                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9149                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9150                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9151         }
9152 }
9153
9154 void intel_dp_get_m_n(struct intel_crtc *crtc,
9155                       struct intel_crtc_state *pipe_config)
9156 {
9157         if (pipe_config->has_pch_encoder)
9158                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9159         else
9160                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9161                                              &pipe_config->dp_m_n,
9162                                              &pipe_config->dp_m2_n2);
9163 }
9164
9165 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9166                                         struct intel_crtc_state *pipe_config)
9167 {
9168         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9169                                      &pipe_config->fdi_m_n, NULL);
9170 }
9171
9172 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9173                                     struct intel_crtc_state *pipe_config)
9174 {
9175         struct drm_device *dev = crtc->base.dev;
9176         struct drm_i915_private *dev_priv = dev->dev_private;
9177         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9178         uint32_t ps_ctrl = 0;
9179         int id = -1;
9180         int i;
9181
9182         /* find scaler attached to this pipe */
9183         for (i = 0; i < crtc->num_scalers; i++) {
9184                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9185                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9186                         id = i;
9187                         pipe_config->pch_pfit.enabled = true;
9188                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9189                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9190                         break;
9191                 }
9192         }
9193
9194         scaler_state->scaler_id = id;
9195         if (id >= 0) {
9196                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9197         } else {
9198                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9199         }
9200 }
9201
9202 static void
9203 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9204                                  struct intel_initial_plane_config *plane_config)
9205 {
9206         struct drm_device *dev = crtc->base.dev;
9207         struct drm_i915_private *dev_priv = dev->dev_private;
9208         u32 val, base, offset, stride_mult, tiling;
9209         int pipe = crtc->pipe;
9210         int fourcc, pixel_format;
9211         unsigned int aligned_height;
9212         struct drm_framebuffer *fb;
9213         struct intel_framebuffer *intel_fb;
9214
9215         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9216         if (!intel_fb) {
9217                 DRM_DEBUG_KMS("failed to alloc fb\n");
9218                 return;
9219         }
9220
9221         fb = &intel_fb->base;
9222
9223         val = I915_READ(PLANE_CTL(pipe, 0));
9224         if (!(val & PLANE_CTL_ENABLE))
9225                 goto error;
9226
9227         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9228         fourcc = skl_format_to_fourcc(pixel_format,
9229                                       val & PLANE_CTL_ORDER_RGBX,
9230                                       val & PLANE_CTL_ALPHA_MASK);
9231         fb->pixel_format = fourcc;
9232         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9233
9234         tiling = val & PLANE_CTL_TILED_MASK;
9235         switch (tiling) {
9236         case PLANE_CTL_TILED_LINEAR:
9237                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9238                 break;
9239         case PLANE_CTL_TILED_X:
9240                 plane_config->tiling = I915_TILING_X;
9241                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9242                 break;
9243         case PLANE_CTL_TILED_Y:
9244                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9245                 break;
9246         case PLANE_CTL_TILED_YF:
9247                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9248                 break;
9249         default:
9250                 MISSING_CASE(tiling);
9251                 goto error;
9252         }
9253
9254         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9255         plane_config->base = base;
9256
9257         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9258
9259         val = I915_READ(PLANE_SIZE(pipe, 0));
9260         fb->height = ((val >> 16) & 0xfff) + 1;
9261         fb->width = ((val >> 0) & 0x1fff) + 1;
9262
9263         val = I915_READ(PLANE_STRIDE(pipe, 0));
9264         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9265                                                 fb->pixel_format);
9266         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9267
9268         aligned_height = intel_fb_align_height(dev, fb->height,
9269                                                fb->pixel_format,
9270                                                fb->modifier[0]);
9271
9272         plane_config->size = fb->pitches[0] * aligned_height;
9273
9274         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9275                       pipe_name(pipe), fb->width, fb->height,
9276                       fb->bits_per_pixel, base, fb->pitches[0],
9277                       plane_config->size);
9278
9279         plane_config->fb = intel_fb;
9280         return;
9281
9282 error:
9283         kfree(fb);
9284 }
9285
9286 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9287                                      struct intel_crtc_state *pipe_config)
9288 {
9289         struct drm_device *dev = crtc->base.dev;
9290         struct drm_i915_private *dev_priv = dev->dev_private;
9291         uint32_t tmp;
9292
9293         tmp = I915_READ(PF_CTL(crtc->pipe));
9294
9295         if (tmp & PF_ENABLE) {
9296                 pipe_config->pch_pfit.enabled = true;
9297                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9298                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9299
9300                 /* We currently do not free assignements of panel fitters on
9301                  * ivb/hsw (since we don't use the higher upscaling modes which
9302                  * differentiates them) so just WARN about this case for now. */
9303                 if (IS_GEN7(dev)) {
9304                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9305                                 PF_PIPE_SEL_IVB(crtc->pipe));
9306                 }
9307         }
9308 }
9309
9310 static void
9311 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9312                                   struct intel_initial_plane_config *plane_config)
9313 {
9314         struct drm_device *dev = crtc->base.dev;
9315         struct drm_i915_private *dev_priv = dev->dev_private;
9316         u32 val, base, offset;
9317         int pipe = crtc->pipe;
9318         int fourcc, pixel_format;
9319         unsigned int aligned_height;
9320         struct drm_framebuffer *fb;
9321         struct intel_framebuffer *intel_fb;
9322
9323         val = I915_READ(DSPCNTR(pipe));
9324         if (!(val & DISPLAY_PLANE_ENABLE))
9325                 return;
9326
9327         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9328         if (!intel_fb) {
9329                 DRM_DEBUG_KMS("failed to alloc fb\n");
9330                 return;
9331         }
9332
9333         fb = &intel_fb->base;
9334
9335         if (INTEL_INFO(dev)->gen >= 4) {
9336                 if (val & DISPPLANE_TILED) {
9337                         plane_config->tiling = I915_TILING_X;
9338                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9339                 }
9340         }
9341
9342         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9343         fourcc = i9xx_format_to_fourcc(pixel_format);
9344         fb->pixel_format = fourcc;
9345         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9346
9347         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9348         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9349                 offset = I915_READ(DSPOFFSET(pipe));
9350         } else {
9351                 if (plane_config->tiling)
9352                         offset = I915_READ(DSPTILEOFF(pipe));
9353                 else
9354                         offset = I915_READ(DSPLINOFF(pipe));
9355         }
9356         plane_config->base = base;
9357
9358         val = I915_READ(PIPESRC(pipe));
9359         fb->width = ((val >> 16) & 0xfff) + 1;
9360         fb->height = ((val >> 0) & 0xfff) + 1;
9361
9362         val = I915_READ(DSPSTRIDE(pipe));
9363         fb->pitches[0] = val & 0xffffffc0;
9364
9365         aligned_height = intel_fb_align_height(dev, fb->height,
9366                                                fb->pixel_format,
9367                                                fb->modifier[0]);
9368
9369         plane_config->size = fb->pitches[0] * aligned_height;
9370
9371         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9372                       pipe_name(pipe), fb->width, fb->height,
9373                       fb->bits_per_pixel, base, fb->pitches[0],
9374                       plane_config->size);
9375
9376         plane_config->fb = intel_fb;
9377 }
9378
9379 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9380                                      struct intel_crtc_state *pipe_config)
9381 {
9382         struct drm_device *dev = crtc->base.dev;
9383         struct drm_i915_private *dev_priv = dev->dev_private;
9384         uint32_t tmp;
9385
9386         if (!intel_display_power_is_enabled(dev_priv,
9387                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9388                 return false;
9389
9390         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9391         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9392
9393         tmp = I915_READ(PIPECONF(crtc->pipe));
9394         if (!(tmp & PIPECONF_ENABLE))
9395                 return false;
9396
9397         switch (tmp & PIPECONF_BPC_MASK) {
9398         case PIPECONF_6BPC:
9399                 pipe_config->pipe_bpp = 18;
9400                 break;
9401         case PIPECONF_8BPC:
9402                 pipe_config->pipe_bpp = 24;
9403                 break;
9404         case PIPECONF_10BPC:
9405                 pipe_config->pipe_bpp = 30;
9406                 break;
9407         case PIPECONF_12BPC:
9408                 pipe_config->pipe_bpp = 36;
9409                 break;
9410         default:
9411                 break;
9412         }
9413
9414         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9415                 pipe_config->limited_color_range = true;
9416
9417         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9418                 struct intel_shared_dpll *pll;
9419
9420                 pipe_config->has_pch_encoder = true;
9421
9422                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9423                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9424                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9425
9426                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9427
9428                 if (HAS_PCH_IBX(dev_priv->dev)) {
9429                         pipe_config->shared_dpll =
9430                                 (enum intel_dpll_id) crtc->pipe;
9431                 } else {
9432                         tmp = I915_READ(PCH_DPLL_SEL);
9433                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9434                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9435                         else
9436                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9437                 }
9438
9439                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9440
9441                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9442                                            &pipe_config->dpll_hw_state));
9443
9444                 tmp = pipe_config->dpll_hw_state.dpll;
9445                 pipe_config->pixel_multiplier =
9446                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9447                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9448
9449                 ironlake_pch_clock_get(crtc, pipe_config);
9450         } else {
9451                 pipe_config->pixel_multiplier = 1;
9452         }
9453
9454         intel_get_pipe_timings(crtc, pipe_config);
9455
9456         ironlake_get_pfit_config(crtc, pipe_config);
9457
9458         return true;
9459 }
9460
9461 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9462 {
9463         struct drm_device *dev = dev_priv->dev;
9464         struct intel_crtc *crtc;
9465
9466         for_each_intel_crtc(dev, crtc)
9467                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9468                      pipe_name(crtc->pipe));
9469
9470         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9471         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9472         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9473         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9474         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9475         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9476              "CPU PWM1 enabled\n");
9477         if (IS_HASWELL(dev))
9478                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9479                      "CPU PWM2 enabled\n");
9480         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9481              "PCH PWM1 enabled\n");
9482         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9483              "Utility pin enabled\n");
9484         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9485
9486         /*
9487          * In theory we can still leave IRQs enabled, as long as only the HPD
9488          * interrupts remain enabled. We used to check for that, but since it's
9489          * gen-specific and since we only disable LCPLL after we fully disable
9490          * the interrupts, the check below should be enough.
9491          */
9492         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9493 }
9494
9495 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9496 {
9497         struct drm_device *dev = dev_priv->dev;
9498
9499         if (IS_HASWELL(dev))
9500                 return I915_READ(D_COMP_HSW);
9501         else
9502                 return I915_READ(D_COMP_BDW);
9503 }
9504
9505 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9506 {
9507         struct drm_device *dev = dev_priv->dev;
9508
9509         if (IS_HASWELL(dev)) {
9510                 mutex_lock(&dev_priv->rps.hw_lock);
9511                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9512                                             val))
9513                         DRM_ERROR("Failed to write to D_COMP\n");
9514                 mutex_unlock(&dev_priv->rps.hw_lock);
9515         } else {
9516                 I915_WRITE(D_COMP_BDW, val);
9517                 POSTING_READ(D_COMP_BDW);
9518         }
9519 }
9520
9521 /*
9522  * This function implements pieces of two sequences from BSpec:
9523  * - Sequence for display software to disable LCPLL
9524  * - Sequence for display software to allow package C8+
9525  * The steps implemented here are just the steps that actually touch the LCPLL
9526  * register. Callers should take care of disabling all the display engine
9527  * functions, doing the mode unset, fixing interrupts, etc.
9528  */
9529 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9530                               bool switch_to_fclk, bool allow_power_down)
9531 {
9532         uint32_t val;
9533
9534         assert_can_disable_lcpll(dev_priv);
9535
9536         val = I915_READ(LCPLL_CTL);
9537
9538         if (switch_to_fclk) {
9539                 val |= LCPLL_CD_SOURCE_FCLK;
9540                 I915_WRITE(LCPLL_CTL, val);
9541
9542                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9543                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9544                         DRM_ERROR("Switching to FCLK failed\n");
9545
9546                 val = I915_READ(LCPLL_CTL);
9547         }
9548
9549         val |= LCPLL_PLL_DISABLE;
9550         I915_WRITE(LCPLL_CTL, val);
9551         POSTING_READ(LCPLL_CTL);
9552
9553         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9554                 DRM_ERROR("LCPLL still locked\n");
9555
9556         val = hsw_read_dcomp(dev_priv);
9557         val |= D_COMP_COMP_DISABLE;
9558         hsw_write_dcomp(dev_priv, val);
9559         ndelay(100);
9560
9561         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9562                      1))
9563                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9564
9565         if (allow_power_down) {
9566                 val = I915_READ(LCPLL_CTL);
9567                 val |= LCPLL_POWER_DOWN_ALLOW;
9568                 I915_WRITE(LCPLL_CTL, val);
9569                 POSTING_READ(LCPLL_CTL);
9570         }
9571 }
9572
9573 /*
9574  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9575  * source.
9576  */
9577 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9578 {
9579         uint32_t val;
9580
9581         val = I915_READ(LCPLL_CTL);
9582
9583         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9584                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9585                 return;
9586
9587         /*
9588          * Make sure we're not on PC8 state before disabling PC8, otherwise
9589          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9590          */
9591         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9592
9593         if (val & LCPLL_POWER_DOWN_ALLOW) {
9594                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9595                 I915_WRITE(LCPLL_CTL, val);
9596                 POSTING_READ(LCPLL_CTL);
9597         }
9598
9599         val = hsw_read_dcomp(dev_priv);
9600         val |= D_COMP_COMP_FORCE;
9601         val &= ~D_COMP_COMP_DISABLE;
9602         hsw_write_dcomp(dev_priv, val);
9603
9604         val = I915_READ(LCPLL_CTL);
9605         val &= ~LCPLL_PLL_DISABLE;
9606         I915_WRITE(LCPLL_CTL, val);
9607
9608         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9609                 DRM_ERROR("LCPLL not locked yet\n");
9610
9611         if (val & LCPLL_CD_SOURCE_FCLK) {
9612                 val = I915_READ(LCPLL_CTL);
9613                 val &= ~LCPLL_CD_SOURCE_FCLK;
9614                 I915_WRITE(LCPLL_CTL, val);
9615
9616                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9617                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9618                         DRM_ERROR("Switching back to LCPLL failed\n");
9619         }
9620
9621         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9622         intel_update_cdclk(dev_priv->dev);
9623 }
9624
9625 /*
9626  * Package states C8 and deeper are really deep PC states that can only be
9627  * reached when all the devices on the system allow it, so even if the graphics
9628  * device allows PC8+, it doesn't mean the system will actually get to these
9629  * states. Our driver only allows PC8+ when going into runtime PM.
9630  *
9631  * The requirements for PC8+ are that all the outputs are disabled, the power
9632  * well is disabled and most interrupts are disabled, and these are also
9633  * requirements for runtime PM. When these conditions are met, we manually do
9634  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9635  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9636  * hang the machine.
9637  *
9638  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9639  * the state of some registers, so when we come back from PC8+ we need to
9640  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9641  * need to take care of the registers kept by RC6. Notice that this happens even
9642  * if we don't put the device in PCI D3 state (which is what currently happens
9643  * because of the runtime PM support).
9644  *
9645  * For more, read "Display Sequences for Package C8" on the hardware
9646  * documentation.
9647  */
9648 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9649 {
9650         struct drm_device *dev = dev_priv->dev;
9651         uint32_t val;
9652
9653         DRM_DEBUG_KMS("Enabling package C8+\n");
9654
9655         if (HAS_PCH_LPT_LP(dev)) {
9656                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9657                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9658                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9659         }
9660
9661         lpt_disable_clkout_dp(dev);
9662         hsw_disable_lcpll(dev_priv, true, true);
9663 }
9664
9665 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9666 {
9667         struct drm_device *dev = dev_priv->dev;
9668         uint32_t val;
9669
9670         DRM_DEBUG_KMS("Disabling package C8+\n");
9671
9672         hsw_restore_lcpll(dev_priv);
9673         lpt_init_pch_refclk(dev);
9674
9675         if (HAS_PCH_LPT_LP(dev)) {
9676                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9677                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9678                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9679         }
9680 }
9681
9682 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9683 {
9684         struct drm_device *dev = old_state->dev;
9685         struct intel_atomic_state *old_intel_state =
9686                 to_intel_atomic_state(old_state);
9687         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9688
9689         broxton_set_cdclk(dev, req_cdclk);
9690 }
9691
9692 /* compute the max rate for new configuration */
9693 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9694 {
9695         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9696         struct drm_i915_private *dev_priv = state->dev->dev_private;
9697         struct drm_crtc *crtc;
9698         struct drm_crtc_state *cstate;
9699         struct intel_crtc_state *crtc_state;
9700         unsigned max_pixel_rate = 0, i;
9701         enum pipe pipe;
9702
9703         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9704                sizeof(intel_state->min_pixclk));
9705
9706         for_each_crtc_in_state(state, crtc, cstate, i) {
9707                 int pixel_rate;
9708
9709                 crtc_state = to_intel_crtc_state(cstate);
9710                 if (!crtc_state->base.enable) {
9711                         intel_state->min_pixclk[i] = 0;
9712                         continue;
9713                 }
9714
9715                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9716
9717                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9718                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9719                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9720
9721                 intel_state->min_pixclk[i] = pixel_rate;
9722         }
9723
9724         if (!intel_state->active_crtcs)
9725                 return 0;
9726
9727         for_each_pipe(dev_priv, pipe)
9728                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9729
9730         return max_pixel_rate;
9731 }
9732
9733 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9734 {
9735         struct drm_i915_private *dev_priv = dev->dev_private;
9736         uint32_t val, data;
9737         int ret;
9738
9739         if (WARN((I915_READ(LCPLL_CTL) &
9740                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9741                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9742                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9743                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9744                  "trying to change cdclk frequency with cdclk not enabled\n"))
9745                 return;
9746
9747         mutex_lock(&dev_priv->rps.hw_lock);
9748         ret = sandybridge_pcode_write(dev_priv,
9749                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9750         mutex_unlock(&dev_priv->rps.hw_lock);
9751         if (ret) {
9752                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9753                 return;
9754         }
9755
9756         val = I915_READ(LCPLL_CTL);
9757         val |= LCPLL_CD_SOURCE_FCLK;
9758         I915_WRITE(LCPLL_CTL, val);
9759
9760         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9761                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9762                 DRM_ERROR("Switching to FCLK failed\n");
9763
9764         val = I915_READ(LCPLL_CTL);
9765         val &= ~LCPLL_CLK_FREQ_MASK;
9766
9767         switch (cdclk) {
9768         case 450000:
9769                 val |= LCPLL_CLK_FREQ_450;
9770                 data = 0;
9771                 break;
9772         case 540000:
9773                 val |= LCPLL_CLK_FREQ_54O_BDW;
9774                 data = 1;
9775                 break;
9776         case 337500:
9777                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9778                 data = 2;
9779                 break;
9780         case 675000:
9781                 val |= LCPLL_CLK_FREQ_675_BDW;
9782                 data = 3;
9783                 break;
9784         default:
9785                 WARN(1, "invalid cdclk frequency\n");
9786                 return;
9787         }
9788
9789         I915_WRITE(LCPLL_CTL, val);
9790
9791         val = I915_READ(LCPLL_CTL);
9792         val &= ~LCPLL_CD_SOURCE_FCLK;
9793         I915_WRITE(LCPLL_CTL, val);
9794
9795         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9796                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9797                 DRM_ERROR("Switching back to LCPLL failed\n");
9798
9799         mutex_lock(&dev_priv->rps.hw_lock);
9800         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9801         mutex_unlock(&dev_priv->rps.hw_lock);
9802
9803         intel_update_cdclk(dev);
9804
9805         WARN(cdclk != dev_priv->cdclk_freq,
9806              "cdclk requested %d kHz but got %d kHz\n",
9807              cdclk, dev_priv->cdclk_freq);
9808 }
9809
9810 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9811 {
9812         struct drm_i915_private *dev_priv = to_i915(state->dev);
9813         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9814         int max_pixclk = ilk_max_pixel_rate(state);
9815         int cdclk;
9816
9817         /*
9818          * FIXME should also account for plane ratio
9819          * once 64bpp pixel formats are supported.
9820          */
9821         if (max_pixclk > 540000)
9822                 cdclk = 675000;
9823         else if (max_pixclk > 450000)
9824                 cdclk = 540000;
9825         else if (max_pixclk > 337500)
9826                 cdclk = 450000;
9827         else
9828                 cdclk = 337500;
9829
9830         if (cdclk > dev_priv->max_cdclk_freq) {
9831                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9832                               cdclk, dev_priv->max_cdclk_freq);
9833                 return -EINVAL;
9834         }
9835
9836         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9837         if (!intel_state->active_crtcs)
9838                 intel_state->dev_cdclk = 337500;
9839
9840         return 0;
9841 }
9842
9843 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9844 {
9845         struct drm_device *dev = old_state->dev;
9846         struct intel_atomic_state *old_intel_state =
9847                 to_intel_atomic_state(old_state);
9848         unsigned req_cdclk = old_intel_state->dev_cdclk;
9849
9850         broadwell_set_cdclk(dev, req_cdclk);
9851 }
9852
9853 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9854                                       struct intel_crtc_state *crtc_state)
9855 {
9856         if (!intel_ddi_pll_select(crtc, crtc_state))
9857                 return -EINVAL;
9858
9859         crtc->lowfreq_avail = false;
9860
9861         return 0;
9862 }
9863
9864 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9865                                 enum port port,
9866                                 struct intel_crtc_state *pipe_config)
9867 {
9868         switch (port) {
9869         case PORT_A:
9870                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9871                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9872                 break;
9873         case PORT_B:
9874                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9875                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9876                 break;
9877         case PORT_C:
9878                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9879                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9880                 break;
9881         default:
9882                 DRM_ERROR("Incorrect port type\n");
9883         }
9884 }
9885
9886 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9887                                 enum port port,
9888                                 struct intel_crtc_state *pipe_config)
9889 {
9890         u32 temp, dpll_ctl1;
9891
9892         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9893         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9894
9895         switch (pipe_config->ddi_pll_sel) {
9896         case SKL_DPLL0:
9897                 /*
9898                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9899                  * of the shared DPLL framework and thus needs to be read out
9900                  * separately
9901                  */
9902                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9903                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9904                 break;
9905         case SKL_DPLL1:
9906                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9907                 break;
9908         case SKL_DPLL2:
9909                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9910                 break;
9911         case SKL_DPLL3:
9912                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9913                 break;
9914         }
9915 }
9916
9917 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9918                                 enum port port,
9919                                 struct intel_crtc_state *pipe_config)
9920 {
9921         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9922
9923         switch (pipe_config->ddi_pll_sel) {
9924         case PORT_CLK_SEL_WRPLL1:
9925                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9926                 break;
9927         case PORT_CLK_SEL_WRPLL2:
9928                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9929                 break;
9930         case PORT_CLK_SEL_SPLL:
9931                 pipe_config->shared_dpll = DPLL_ID_SPLL;
9932                 break;
9933         }
9934 }
9935
9936 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9937                                        struct intel_crtc_state *pipe_config)
9938 {
9939         struct drm_device *dev = crtc->base.dev;
9940         struct drm_i915_private *dev_priv = dev->dev_private;
9941         struct intel_shared_dpll *pll;
9942         enum port port;
9943         uint32_t tmp;
9944
9945         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9946
9947         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9948
9949         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9950                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9951         else if (IS_BROXTON(dev))
9952                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9953         else
9954                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9955
9956         if (pipe_config->shared_dpll >= 0) {
9957                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9958
9959                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9960                                            &pipe_config->dpll_hw_state));
9961         }
9962
9963         /*
9964          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9965          * DDI E. So just check whether this pipe is wired to DDI E and whether
9966          * the PCH transcoder is on.
9967          */
9968         if (INTEL_INFO(dev)->gen < 9 &&
9969             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9970                 pipe_config->has_pch_encoder = true;
9971
9972                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9973                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9974                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9975
9976                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9977         }
9978 }
9979
9980 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9981                                     struct intel_crtc_state *pipe_config)
9982 {
9983         struct drm_device *dev = crtc->base.dev;
9984         struct drm_i915_private *dev_priv = dev->dev_private;
9985         enum intel_display_power_domain pfit_domain;
9986         uint32_t tmp;
9987
9988         if (!intel_display_power_is_enabled(dev_priv,
9989                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9990                 return false;
9991
9992         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9993         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9994
9995         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9996         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9997                 enum pipe trans_edp_pipe;
9998                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9999                 default:
10000                         WARN(1, "unknown pipe linked to edp transcoder\n");
10001                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10002                 case TRANS_DDI_EDP_INPUT_A_ON:
10003                         trans_edp_pipe = PIPE_A;
10004                         break;
10005                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10006                         trans_edp_pipe = PIPE_B;
10007                         break;
10008                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10009                         trans_edp_pipe = PIPE_C;
10010                         break;
10011                 }
10012
10013                 if (trans_edp_pipe == crtc->pipe)
10014                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10015         }
10016
10017         if (!intel_display_power_is_enabled(dev_priv,
10018                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
10019                 return false;
10020
10021         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10022         if (!(tmp & PIPECONF_ENABLE))
10023                 return false;
10024
10025         haswell_get_ddi_port_state(crtc, pipe_config);
10026
10027         intel_get_pipe_timings(crtc, pipe_config);
10028
10029         if (INTEL_INFO(dev)->gen >= 9) {
10030                 skl_init_scalers(dev, crtc, pipe_config);
10031         }
10032
10033         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10034
10035         if (INTEL_INFO(dev)->gen >= 9) {
10036                 pipe_config->scaler_state.scaler_id = -1;
10037                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10038         }
10039
10040         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
10041                 if (INTEL_INFO(dev)->gen >= 9)
10042                         skylake_get_pfit_config(crtc, pipe_config);
10043                 else
10044                         ironlake_get_pfit_config(crtc, pipe_config);
10045         }
10046
10047         if (IS_HASWELL(dev))
10048                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10049                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10050
10051         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10052                 pipe_config->pixel_multiplier =
10053                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10054         } else {
10055                 pipe_config->pixel_multiplier = 1;
10056         }
10057
10058         return true;
10059 }
10060
10061 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10062                                const struct intel_plane_state *plane_state)
10063 {
10064         struct drm_device *dev = crtc->dev;
10065         struct drm_i915_private *dev_priv = dev->dev_private;
10066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10067         uint32_t cntl = 0, size = 0;
10068
10069         if (plane_state && plane_state->visible) {
10070                 unsigned int width = plane_state->base.crtc_w;
10071                 unsigned int height = plane_state->base.crtc_h;
10072                 unsigned int stride = roundup_pow_of_two(width) * 4;
10073
10074                 switch (stride) {
10075                 default:
10076                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10077                                   width, stride);
10078                         stride = 256;
10079                         /* fallthrough */
10080                 case 256:
10081                 case 512:
10082                 case 1024:
10083                 case 2048:
10084                         break;
10085                 }
10086
10087                 cntl |= CURSOR_ENABLE |
10088                         CURSOR_GAMMA_ENABLE |
10089                         CURSOR_FORMAT_ARGB |
10090                         CURSOR_STRIDE(stride);
10091
10092                 size = (height << 12) | width;
10093         }
10094
10095         if (intel_crtc->cursor_cntl != 0 &&
10096             (intel_crtc->cursor_base != base ||
10097              intel_crtc->cursor_size != size ||
10098              intel_crtc->cursor_cntl != cntl)) {
10099                 /* On these chipsets we can only modify the base/size/stride
10100                  * whilst the cursor is disabled.
10101                  */
10102                 I915_WRITE(CURCNTR(PIPE_A), 0);
10103                 POSTING_READ(CURCNTR(PIPE_A));
10104                 intel_crtc->cursor_cntl = 0;
10105         }
10106
10107         if (intel_crtc->cursor_base != base) {
10108                 I915_WRITE(CURBASE(PIPE_A), base);
10109                 intel_crtc->cursor_base = base;
10110         }
10111
10112         if (intel_crtc->cursor_size != size) {
10113                 I915_WRITE(CURSIZE, size);
10114                 intel_crtc->cursor_size = size;
10115         }
10116
10117         if (intel_crtc->cursor_cntl != cntl) {
10118                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10119                 POSTING_READ(CURCNTR(PIPE_A));
10120                 intel_crtc->cursor_cntl = cntl;
10121         }
10122 }
10123
10124 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10125                                const struct intel_plane_state *plane_state)
10126 {
10127         struct drm_device *dev = crtc->dev;
10128         struct drm_i915_private *dev_priv = dev->dev_private;
10129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10130         int pipe = intel_crtc->pipe;
10131         uint32_t cntl = 0;
10132
10133         if (plane_state && plane_state->visible) {
10134                 cntl = MCURSOR_GAMMA_ENABLE;
10135                 switch (plane_state->base.crtc_w) {
10136                         case 64:
10137                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10138                                 break;
10139                         case 128:
10140                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10141                                 break;
10142                         case 256:
10143                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10144                                 break;
10145                         default:
10146                                 MISSING_CASE(plane_state->base.crtc_w);
10147                                 return;
10148                 }
10149                 cntl |= pipe << 28; /* Connect to correct pipe */
10150
10151                 if (HAS_DDI(dev))
10152                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10153
10154                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10155                         cntl |= CURSOR_ROTATE_180;
10156         }
10157
10158         if (intel_crtc->cursor_cntl != cntl) {
10159                 I915_WRITE(CURCNTR(pipe), cntl);
10160                 POSTING_READ(CURCNTR(pipe));
10161                 intel_crtc->cursor_cntl = cntl;
10162         }
10163
10164         /* and commit changes on next vblank */
10165         I915_WRITE(CURBASE(pipe), base);
10166         POSTING_READ(CURBASE(pipe));
10167
10168         intel_crtc->cursor_base = base;
10169 }
10170
10171 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10172 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10173                                      const struct intel_plane_state *plane_state)
10174 {
10175         struct drm_device *dev = crtc->dev;
10176         struct drm_i915_private *dev_priv = dev->dev_private;
10177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10178         int pipe = intel_crtc->pipe;
10179         u32 base = intel_crtc->cursor_addr;
10180         u32 pos = 0;
10181
10182         if (plane_state) {
10183                 int x = plane_state->base.crtc_x;
10184                 int y = plane_state->base.crtc_y;
10185
10186                 if (x < 0) {
10187                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10188                         x = -x;
10189                 }
10190                 pos |= x << CURSOR_X_SHIFT;
10191
10192                 if (y < 0) {
10193                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10194                         y = -y;
10195                 }
10196                 pos |= y << CURSOR_Y_SHIFT;
10197
10198                 /* ILK+ do this automagically */
10199                 if (HAS_GMCH_DISPLAY(dev) &&
10200                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10201                         base += (plane_state->base.crtc_h *
10202                                  plane_state->base.crtc_w - 1) * 4;
10203                 }
10204         }
10205
10206         I915_WRITE(CURPOS(pipe), pos);
10207
10208         if (IS_845G(dev) || IS_I865G(dev))
10209                 i845_update_cursor(crtc, base, plane_state);
10210         else
10211                 i9xx_update_cursor(crtc, base, plane_state);
10212 }
10213
10214 static bool cursor_size_ok(struct drm_device *dev,
10215                            uint32_t width, uint32_t height)
10216 {
10217         if (width == 0 || height == 0)
10218                 return false;
10219
10220         /*
10221          * 845g/865g are special in that they are only limited by
10222          * the width of their cursors, the height is arbitrary up to
10223          * the precision of the register. Everything else requires
10224          * square cursors, limited to a few power-of-two sizes.
10225          */
10226         if (IS_845G(dev) || IS_I865G(dev)) {
10227                 if ((width & 63) != 0)
10228                         return false;
10229
10230                 if (width > (IS_845G(dev) ? 64 : 512))
10231                         return false;
10232
10233                 if (height > 1023)
10234                         return false;
10235         } else {
10236                 switch (width | height) {
10237                 case 256:
10238                 case 128:
10239                         if (IS_GEN2(dev))
10240                                 return false;
10241                 case 64:
10242                         break;
10243                 default:
10244                         return false;
10245                 }
10246         }
10247
10248         return true;
10249 }
10250
10251 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10252                                  u16 *blue, uint32_t start, uint32_t size)
10253 {
10254         int end = (start + size > 256) ? 256 : start + size, i;
10255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10256
10257         for (i = start; i < end; i++) {
10258                 intel_crtc->lut_r[i] = red[i] >> 8;
10259                 intel_crtc->lut_g[i] = green[i] >> 8;
10260                 intel_crtc->lut_b[i] = blue[i] >> 8;
10261         }
10262
10263         intel_crtc_load_lut(crtc);
10264 }
10265
10266 /* VESA 640x480x72Hz mode to set on the pipe */
10267 static struct drm_display_mode load_detect_mode = {
10268         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10269                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10270 };
10271
10272 struct drm_framebuffer *
10273 __intel_framebuffer_create(struct drm_device *dev,
10274                            struct drm_mode_fb_cmd2 *mode_cmd,
10275                            struct drm_i915_gem_object *obj)
10276 {
10277         struct intel_framebuffer *intel_fb;
10278         int ret;
10279
10280         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10281         if (!intel_fb)
10282                 return ERR_PTR(-ENOMEM);
10283
10284         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10285         if (ret)
10286                 goto err;
10287
10288         return &intel_fb->base;
10289
10290 err:
10291         kfree(intel_fb);
10292         return ERR_PTR(ret);
10293 }
10294
10295 static struct drm_framebuffer *
10296 intel_framebuffer_create(struct drm_device *dev,
10297                          struct drm_mode_fb_cmd2 *mode_cmd,
10298                          struct drm_i915_gem_object *obj)
10299 {
10300         struct drm_framebuffer *fb;
10301         int ret;
10302
10303         ret = i915_mutex_lock_interruptible(dev);
10304         if (ret)
10305                 return ERR_PTR(ret);
10306         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10307         mutex_unlock(&dev->struct_mutex);
10308
10309         return fb;
10310 }
10311
10312 static u32
10313 intel_framebuffer_pitch_for_width(int width, int bpp)
10314 {
10315         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10316         return ALIGN(pitch, 64);
10317 }
10318
10319 static u32
10320 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10321 {
10322         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10323         return PAGE_ALIGN(pitch * mode->vdisplay);
10324 }
10325
10326 static struct drm_framebuffer *
10327 intel_framebuffer_create_for_mode(struct drm_device *dev,
10328                                   struct drm_display_mode *mode,
10329                                   int depth, int bpp)
10330 {
10331         struct drm_framebuffer *fb;
10332         struct drm_i915_gem_object *obj;
10333         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10334
10335         obj = i915_gem_alloc_object(dev,
10336                                     intel_framebuffer_size_for_mode(mode, bpp));
10337         if (obj == NULL)
10338                 return ERR_PTR(-ENOMEM);
10339
10340         mode_cmd.width = mode->hdisplay;
10341         mode_cmd.height = mode->vdisplay;
10342         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10343                                                                 bpp);
10344         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10345
10346         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10347         if (IS_ERR(fb))
10348                 drm_gem_object_unreference_unlocked(&obj->base);
10349
10350         return fb;
10351 }
10352
10353 static struct drm_framebuffer *
10354 mode_fits_in_fbdev(struct drm_device *dev,
10355                    struct drm_display_mode *mode)
10356 {
10357 #ifdef CONFIG_DRM_FBDEV_EMULATION
10358         struct drm_i915_private *dev_priv = dev->dev_private;
10359         struct drm_i915_gem_object *obj;
10360         struct drm_framebuffer *fb;
10361
10362         if (!dev_priv->fbdev)
10363                 return NULL;
10364
10365         if (!dev_priv->fbdev->fb)
10366                 return NULL;
10367
10368         obj = dev_priv->fbdev->fb->obj;
10369         BUG_ON(!obj);
10370
10371         fb = &dev_priv->fbdev->fb->base;
10372         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10373                                                                fb->bits_per_pixel))
10374                 return NULL;
10375
10376         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10377                 return NULL;
10378
10379         return fb;
10380 #else
10381         return NULL;
10382 #endif
10383 }
10384
10385 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10386                                            struct drm_crtc *crtc,
10387                                            struct drm_display_mode *mode,
10388                                            struct drm_framebuffer *fb,
10389                                            int x, int y)
10390 {
10391         struct drm_plane_state *plane_state;
10392         int hdisplay, vdisplay;
10393         int ret;
10394
10395         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10396         if (IS_ERR(plane_state))
10397                 return PTR_ERR(plane_state);
10398
10399         if (mode)
10400                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10401         else
10402                 hdisplay = vdisplay = 0;
10403
10404         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10405         if (ret)
10406                 return ret;
10407         drm_atomic_set_fb_for_plane(plane_state, fb);
10408         plane_state->crtc_x = 0;
10409         plane_state->crtc_y = 0;
10410         plane_state->crtc_w = hdisplay;
10411         plane_state->crtc_h = vdisplay;
10412         plane_state->src_x = x << 16;
10413         plane_state->src_y = y << 16;
10414         plane_state->src_w = hdisplay << 16;
10415         plane_state->src_h = vdisplay << 16;
10416
10417         return 0;
10418 }
10419
10420 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10421                                 struct drm_display_mode *mode,
10422                                 struct intel_load_detect_pipe *old,
10423                                 struct drm_modeset_acquire_ctx *ctx)
10424 {
10425         struct intel_crtc *intel_crtc;
10426         struct intel_encoder *intel_encoder =
10427                 intel_attached_encoder(connector);
10428         struct drm_crtc *possible_crtc;
10429         struct drm_encoder *encoder = &intel_encoder->base;
10430         struct drm_crtc *crtc = NULL;
10431         struct drm_device *dev = encoder->dev;
10432         struct drm_framebuffer *fb;
10433         struct drm_mode_config *config = &dev->mode_config;
10434         struct drm_atomic_state *state = NULL;
10435         struct drm_connector_state *connector_state;
10436         struct intel_crtc_state *crtc_state;
10437         int ret, i = -1;
10438
10439         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10440                       connector->base.id, connector->name,
10441                       encoder->base.id, encoder->name);
10442
10443 retry:
10444         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10445         if (ret)
10446                 goto fail;
10447
10448         /*
10449          * Algorithm gets a little messy:
10450          *
10451          *   - if the connector already has an assigned crtc, use it (but make
10452          *     sure it's on first)
10453          *
10454          *   - try to find the first unused crtc that can drive this connector,
10455          *     and use that if we find one
10456          */
10457
10458         /* See if we already have a CRTC for this connector */
10459         if (encoder->crtc) {
10460                 crtc = encoder->crtc;
10461
10462                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10463                 if (ret)
10464                         goto fail;
10465                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10466                 if (ret)
10467                         goto fail;
10468
10469                 old->dpms_mode = connector->dpms;
10470                 old->load_detect_temp = false;
10471
10472                 /* Make sure the crtc and connector are running */
10473                 if (connector->dpms != DRM_MODE_DPMS_ON)
10474                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10475
10476                 return true;
10477         }
10478
10479         /* Find an unused one (if possible) */
10480         for_each_crtc(dev, possible_crtc) {
10481                 i++;
10482                 if (!(encoder->possible_crtcs & (1 << i)))
10483                         continue;
10484                 if (possible_crtc->state->enable)
10485                         continue;
10486
10487                 crtc = possible_crtc;
10488                 break;
10489         }
10490
10491         /*
10492          * If we didn't find an unused CRTC, don't use any.
10493          */
10494         if (!crtc) {
10495                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10496                 goto fail;
10497         }
10498
10499         ret = drm_modeset_lock(&crtc->mutex, ctx);
10500         if (ret)
10501                 goto fail;
10502         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10503         if (ret)
10504                 goto fail;
10505
10506         intel_crtc = to_intel_crtc(crtc);
10507         old->dpms_mode = connector->dpms;
10508         old->load_detect_temp = true;
10509         old->release_fb = NULL;
10510
10511         state = drm_atomic_state_alloc(dev);
10512         if (!state)
10513                 return false;
10514
10515         state->acquire_ctx = ctx;
10516
10517         connector_state = drm_atomic_get_connector_state(state, connector);
10518         if (IS_ERR(connector_state)) {
10519                 ret = PTR_ERR(connector_state);
10520                 goto fail;
10521         }
10522
10523         connector_state->crtc = crtc;
10524         connector_state->best_encoder = &intel_encoder->base;
10525
10526         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10527         if (IS_ERR(crtc_state)) {
10528                 ret = PTR_ERR(crtc_state);
10529                 goto fail;
10530         }
10531
10532         crtc_state->base.active = crtc_state->base.enable = true;
10533
10534         if (!mode)
10535                 mode = &load_detect_mode;
10536
10537         /* We need a framebuffer large enough to accommodate all accesses
10538          * that the plane may generate whilst we perform load detection.
10539          * We can not rely on the fbcon either being present (we get called
10540          * during its initialisation to detect all boot displays, or it may
10541          * not even exist) or that it is large enough to satisfy the
10542          * requested mode.
10543          */
10544         fb = mode_fits_in_fbdev(dev, mode);
10545         if (fb == NULL) {
10546                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10547                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10548                 old->release_fb = fb;
10549         } else
10550                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10551         if (IS_ERR(fb)) {
10552                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10553                 goto fail;
10554         }
10555
10556         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10557         if (ret)
10558                 goto fail;
10559
10560         drm_mode_copy(&crtc_state->base.mode, mode);
10561
10562         if (drm_atomic_commit(state)) {
10563                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10564                 if (old->release_fb)
10565                         old->release_fb->funcs->destroy(old->release_fb);
10566                 goto fail;
10567         }
10568         crtc->primary->crtc = crtc;
10569
10570         /* let the connector get through one full cycle before testing */
10571         intel_wait_for_vblank(dev, intel_crtc->pipe);
10572         return true;
10573
10574 fail:
10575         drm_atomic_state_free(state);
10576         state = NULL;
10577
10578         if (ret == -EDEADLK) {
10579                 drm_modeset_backoff(ctx);
10580                 goto retry;
10581         }
10582
10583         return false;
10584 }
10585
10586 void intel_release_load_detect_pipe(struct drm_connector *connector,
10587                                     struct intel_load_detect_pipe *old,
10588                                     struct drm_modeset_acquire_ctx *ctx)
10589 {
10590         struct drm_device *dev = connector->dev;
10591         struct intel_encoder *intel_encoder =
10592                 intel_attached_encoder(connector);
10593         struct drm_encoder *encoder = &intel_encoder->base;
10594         struct drm_crtc *crtc = encoder->crtc;
10595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10596         struct drm_atomic_state *state;
10597         struct drm_connector_state *connector_state;
10598         struct intel_crtc_state *crtc_state;
10599         int ret;
10600
10601         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10602                       connector->base.id, connector->name,
10603                       encoder->base.id, encoder->name);
10604
10605         if (old->load_detect_temp) {
10606                 state = drm_atomic_state_alloc(dev);
10607                 if (!state)
10608                         goto fail;
10609
10610                 state->acquire_ctx = ctx;
10611
10612                 connector_state = drm_atomic_get_connector_state(state, connector);
10613                 if (IS_ERR(connector_state))
10614                         goto fail;
10615
10616                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10617                 if (IS_ERR(crtc_state))
10618                         goto fail;
10619
10620                 connector_state->best_encoder = NULL;
10621                 connector_state->crtc = NULL;
10622
10623                 crtc_state->base.enable = crtc_state->base.active = false;
10624
10625                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10626                                                       0, 0);
10627                 if (ret)
10628                         goto fail;
10629
10630                 ret = drm_atomic_commit(state);
10631                 if (ret)
10632                         goto fail;
10633
10634                 if (old->release_fb) {
10635                         drm_framebuffer_unregister_private(old->release_fb);
10636                         drm_framebuffer_unreference(old->release_fb);
10637                 }
10638
10639                 return;
10640         }
10641
10642         /* Switch crtc and encoder back off if necessary */
10643         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10644                 connector->funcs->dpms(connector, old->dpms_mode);
10645
10646         return;
10647 fail:
10648         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10649         drm_atomic_state_free(state);
10650 }
10651
10652 static int i9xx_pll_refclk(struct drm_device *dev,
10653                            const struct intel_crtc_state *pipe_config)
10654 {
10655         struct drm_i915_private *dev_priv = dev->dev_private;
10656         u32 dpll = pipe_config->dpll_hw_state.dpll;
10657
10658         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10659                 return dev_priv->vbt.lvds_ssc_freq;
10660         else if (HAS_PCH_SPLIT(dev))
10661                 return 120000;
10662         else if (!IS_GEN2(dev))
10663                 return 96000;
10664         else
10665                 return 48000;
10666 }
10667
10668 /* Returns the clock of the currently programmed mode of the given pipe. */
10669 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10670                                 struct intel_crtc_state *pipe_config)
10671 {
10672         struct drm_device *dev = crtc->base.dev;
10673         struct drm_i915_private *dev_priv = dev->dev_private;
10674         int pipe = pipe_config->cpu_transcoder;
10675         u32 dpll = pipe_config->dpll_hw_state.dpll;
10676         u32 fp;
10677         intel_clock_t clock;
10678         int port_clock;
10679         int refclk = i9xx_pll_refclk(dev, pipe_config);
10680
10681         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10682                 fp = pipe_config->dpll_hw_state.fp0;
10683         else
10684                 fp = pipe_config->dpll_hw_state.fp1;
10685
10686         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10687         if (IS_PINEVIEW(dev)) {
10688                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10689                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10690         } else {
10691                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10692                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10693         }
10694
10695         if (!IS_GEN2(dev)) {
10696                 if (IS_PINEVIEW(dev))
10697                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10698                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10699                 else
10700                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10701                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10702
10703                 switch (dpll & DPLL_MODE_MASK) {
10704                 case DPLLB_MODE_DAC_SERIAL:
10705                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10706                                 5 : 10;
10707                         break;
10708                 case DPLLB_MODE_LVDS:
10709                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10710                                 7 : 14;
10711                         break;
10712                 default:
10713                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10714                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10715                         return;
10716                 }
10717
10718                 if (IS_PINEVIEW(dev))
10719                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10720                 else
10721                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10722         } else {
10723                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10724                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10725
10726                 if (is_lvds) {
10727                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10728                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10729
10730                         if (lvds & LVDS_CLKB_POWER_UP)
10731                                 clock.p2 = 7;
10732                         else
10733                                 clock.p2 = 14;
10734                 } else {
10735                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10736                                 clock.p1 = 2;
10737                         else {
10738                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10739                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10740                         }
10741                         if (dpll & PLL_P2_DIVIDE_BY_4)
10742                                 clock.p2 = 4;
10743                         else
10744                                 clock.p2 = 2;
10745                 }
10746
10747                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10748         }
10749
10750         /*
10751          * This value includes pixel_multiplier. We will use
10752          * port_clock to compute adjusted_mode.crtc_clock in the
10753          * encoder's get_config() function.
10754          */
10755         pipe_config->port_clock = port_clock;
10756 }
10757
10758 int intel_dotclock_calculate(int link_freq,
10759                              const struct intel_link_m_n *m_n)
10760 {
10761         /*
10762          * The calculation for the data clock is:
10763          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10764          * But we want to avoid losing precison if possible, so:
10765          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10766          *
10767          * and the link clock is simpler:
10768          * link_clock = (m * link_clock) / n
10769          */
10770
10771         if (!m_n->link_n)
10772                 return 0;
10773
10774         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10775 }
10776
10777 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10778                                    struct intel_crtc_state *pipe_config)
10779 {
10780         struct drm_device *dev = crtc->base.dev;
10781
10782         /* read out port_clock from the DPLL */
10783         i9xx_crtc_clock_get(crtc, pipe_config);
10784
10785         /*
10786          * This value does not include pixel_multiplier.
10787          * We will check that port_clock and adjusted_mode.crtc_clock
10788          * agree once we know their relationship in the encoder's
10789          * get_config() function.
10790          */
10791         pipe_config->base.adjusted_mode.crtc_clock =
10792                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10793                                          &pipe_config->fdi_m_n);
10794 }
10795
10796 /** Returns the currently programmed mode of the given pipe. */
10797 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10798                                              struct drm_crtc *crtc)
10799 {
10800         struct drm_i915_private *dev_priv = dev->dev_private;
10801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10802         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10803         struct drm_display_mode *mode;
10804         struct intel_crtc_state *pipe_config;
10805         int htot = I915_READ(HTOTAL(cpu_transcoder));
10806         int hsync = I915_READ(HSYNC(cpu_transcoder));
10807         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10808         int vsync = I915_READ(VSYNC(cpu_transcoder));
10809         enum pipe pipe = intel_crtc->pipe;
10810
10811         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10812         if (!mode)
10813                 return NULL;
10814
10815         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10816         if (!pipe_config) {
10817                 kfree(mode);
10818                 return NULL;
10819         }
10820
10821         /*
10822          * Construct a pipe_config sufficient for getting the clock info
10823          * back out of crtc_clock_get.
10824          *
10825          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10826          * to use a real value here instead.
10827          */
10828         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10829         pipe_config->pixel_multiplier = 1;
10830         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10831         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10832         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10833         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10834
10835         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10836         mode->hdisplay = (htot & 0xffff) + 1;
10837         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10838         mode->hsync_start = (hsync & 0xffff) + 1;
10839         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10840         mode->vdisplay = (vtot & 0xffff) + 1;
10841         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10842         mode->vsync_start = (vsync & 0xffff) + 1;
10843         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10844
10845         drm_mode_set_name(mode);
10846
10847         kfree(pipe_config);
10848
10849         return mode;
10850 }
10851
10852 void intel_mark_busy(struct drm_device *dev)
10853 {
10854         struct drm_i915_private *dev_priv = dev->dev_private;
10855
10856         if (dev_priv->mm.busy)
10857                 return;
10858
10859         intel_runtime_pm_get(dev_priv);
10860         i915_update_gfx_val(dev_priv);
10861         if (INTEL_INFO(dev)->gen >= 6)
10862                 gen6_rps_busy(dev_priv);
10863         dev_priv->mm.busy = true;
10864 }
10865
10866 void intel_mark_idle(struct drm_device *dev)
10867 {
10868         struct drm_i915_private *dev_priv = dev->dev_private;
10869
10870         if (!dev_priv->mm.busy)
10871                 return;
10872
10873         dev_priv->mm.busy = false;
10874
10875         if (INTEL_INFO(dev)->gen >= 6)
10876                 gen6_rps_idle(dev->dev_private);
10877
10878         intel_runtime_pm_put(dev_priv);
10879 }
10880
10881 static void intel_crtc_destroy(struct drm_crtc *crtc)
10882 {
10883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10884         struct drm_device *dev = crtc->dev;
10885         struct intel_unpin_work *work;
10886
10887         spin_lock_irq(&dev->event_lock);
10888         work = intel_crtc->unpin_work;
10889         intel_crtc->unpin_work = NULL;
10890         spin_unlock_irq(&dev->event_lock);
10891
10892         if (work) {
10893                 cancel_work_sync(&work->work);
10894                 kfree(work);
10895         }
10896
10897         drm_crtc_cleanup(crtc);
10898
10899         kfree(intel_crtc);
10900 }
10901
10902 static void intel_unpin_work_fn(struct work_struct *__work)
10903 {
10904         struct intel_unpin_work *work =
10905                 container_of(__work, struct intel_unpin_work, work);
10906         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10907         struct drm_device *dev = crtc->base.dev;
10908         struct drm_plane *primary = crtc->base.primary;
10909
10910         mutex_lock(&dev->struct_mutex);
10911         intel_unpin_fb_obj(work->old_fb, primary->state);
10912         drm_gem_object_unreference(&work->pending_flip_obj->base);
10913
10914         if (work->flip_queued_req)
10915                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10916         mutex_unlock(&dev->struct_mutex);
10917
10918         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10919         drm_framebuffer_unreference(work->old_fb);
10920
10921         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10922         atomic_dec(&crtc->unpin_work_count);
10923
10924         kfree(work);
10925 }
10926
10927 static void do_intel_finish_page_flip(struct drm_device *dev,
10928                                       struct drm_crtc *crtc)
10929 {
10930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10931         struct intel_unpin_work *work;
10932         unsigned long flags;
10933
10934         /* Ignore early vblank irqs */
10935         if (intel_crtc == NULL)
10936                 return;
10937
10938         /*
10939          * This is called both by irq handlers and the reset code (to complete
10940          * lost pageflips) so needs the full irqsave spinlocks.
10941          */
10942         spin_lock_irqsave(&dev->event_lock, flags);
10943         work = intel_crtc->unpin_work;
10944
10945         /* Ensure we don't miss a work->pending update ... */
10946         smp_rmb();
10947
10948         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10949                 spin_unlock_irqrestore(&dev->event_lock, flags);
10950                 return;
10951         }
10952
10953         page_flip_completed(intel_crtc);
10954
10955         spin_unlock_irqrestore(&dev->event_lock, flags);
10956 }
10957
10958 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10959 {
10960         struct drm_i915_private *dev_priv = dev->dev_private;
10961         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10962
10963         do_intel_finish_page_flip(dev, crtc);
10964 }
10965
10966 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10967 {
10968         struct drm_i915_private *dev_priv = dev->dev_private;
10969         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10970
10971         do_intel_finish_page_flip(dev, crtc);
10972 }
10973
10974 /* Is 'a' after or equal to 'b'? */
10975 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10976 {
10977         return !((a - b) & 0x80000000);
10978 }
10979
10980 static bool page_flip_finished(struct intel_crtc *crtc)
10981 {
10982         struct drm_device *dev = crtc->base.dev;
10983         struct drm_i915_private *dev_priv = dev->dev_private;
10984
10985         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10986             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10987                 return true;
10988
10989         /*
10990          * The relevant registers doen't exist on pre-ctg.
10991          * As the flip done interrupt doesn't trigger for mmio
10992          * flips on gmch platforms, a flip count check isn't
10993          * really needed there. But since ctg has the registers,
10994          * include it in the check anyway.
10995          */
10996         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10997                 return true;
10998
10999         /*
11000          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11001          * used the same base address. In that case the mmio flip might
11002          * have completed, but the CS hasn't even executed the flip yet.
11003          *
11004          * A flip count check isn't enough as the CS might have updated
11005          * the base address just after start of vblank, but before we
11006          * managed to process the interrupt. This means we'd complete the
11007          * CS flip too soon.
11008          *
11009          * Combining both checks should get us a good enough result. It may
11010          * still happen that the CS flip has been executed, but has not
11011          * yet actually completed. But in case the base address is the same
11012          * anyway, we don't really care.
11013          */
11014         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11015                 crtc->unpin_work->gtt_offset &&
11016                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11017                                     crtc->unpin_work->flip_count);
11018 }
11019
11020 void intel_prepare_page_flip(struct drm_device *dev, int plane)
11021 {
11022         struct drm_i915_private *dev_priv = dev->dev_private;
11023         struct intel_crtc *intel_crtc =
11024                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11025         unsigned long flags;
11026
11027
11028         /*
11029          * This is called both by irq handlers and the reset code (to complete
11030          * lost pageflips) so needs the full irqsave spinlocks.
11031          *
11032          * NB: An MMIO update of the plane base pointer will also
11033          * generate a page-flip completion irq, i.e. every modeset
11034          * is also accompanied by a spurious intel_prepare_page_flip().
11035          */
11036         spin_lock_irqsave(&dev->event_lock, flags);
11037         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11038                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11039         spin_unlock_irqrestore(&dev->event_lock, flags);
11040 }
11041
11042 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11043 {
11044         /* Ensure that the work item is consistent when activating it ... */
11045         smp_wmb();
11046         atomic_set(&work->pending, INTEL_FLIP_PENDING);
11047         /* and that it is marked active as soon as the irq could fire. */
11048         smp_wmb();
11049 }
11050
11051 static int intel_gen2_queue_flip(struct drm_device *dev,
11052                                  struct drm_crtc *crtc,
11053                                  struct drm_framebuffer *fb,
11054                                  struct drm_i915_gem_object *obj,
11055                                  struct drm_i915_gem_request *req,
11056                                  uint32_t flags)
11057 {
11058         struct intel_engine_cs *ring = req->ring;
11059         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11060         u32 flip_mask;
11061         int ret;
11062
11063         ret = intel_ring_begin(req, 6);
11064         if (ret)
11065                 return ret;
11066
11067         /* Can't queue multiple flips, so wait for the previous
11068          * one to finish before executing the next.
11069          */
11070         if (intel_crtc->plane)
11071                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11072         else
11073                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11074         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11075         intel_ring_emit(ring, MI_NOOP);
11076         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11077                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11078         intel_ring_emit(ring, fb->pitches[0]);
11079         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11080         intel_ring_emit(ring, 0); /* aux display base address, unused */
11081
11082         intel_mark_page_flip_active(intel_crtc->unpin_work);
11083         return 0;
11084 }
11085
11086 static int intel_gen3_queue_flip(struct drm_device *dev,
11087                                  struct drm_crtc *crtc,
11088                                  struct drm_framebuffer *fb,
11089                                  struct drm_i915_gem_object *obj,
11090                                  struct drm_i915_gem_request *req,
11091                                  uint32_t flags)
11092 {
11093         struct intel_engine_cs *ring = req->ring;
11094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11095         u32 flip_mask;
11096         int ret;
11097
11098         ret = intel_ring_begin(req, 6);
11099         if (ret)
11100                 return ret;
11101
11102         if (intel_crtc->plane)
11103                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11104         else
11105                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11106         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11107         intel_ring_emit(ring, MI_NOOP);
11108         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11109                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11110         intel_ring_emit(ring, fb->pitches[0]);
11111         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11112         intel_ring_emit(ring, MI_NOOP);
11113
11114         intel_mark_page_flip_active(intel_crtc->unpin_work);
11115         return 0;
11116 }
11117
11118 static int intel_gen4_queue_flip(struct drm_device *dev,
11119                                  struct drm_crtc *crtc,
11120                                  struct drm_framebuffer *fb,
11121                                  struct drm_i915_gem_object *obj,
11122                                  struct drm_i915_gem_request *req,
11123                                  uint32_t flags)
11124 {
11125         struct intel_engine_cs *ring = req->ring;
11126         struct drm_i915_private *dev_priv = dev->dev_private;
11127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11128         uint32_t pf, pipesrc;
11129         int ret;
11130
11131         ret = intel_ring_begin(req, 4);
11132         if (ret)
11133                 return ret;
11134
11135         /* i965+ uses the linear or tiled offsets from the
11136          * Display Registers (which do not change across a page-flip)
11137          * so we need only reprogram the base address.
11138          */
11139         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11140                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11141         intel_ring_emit(ring, fb->pitches[0]);
11142         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11143                         obj->tiling_mode);
11144
11145         /* XXX Enabling the panel-fitter across page-flip is so far
11146          * untested on non-native modes, so ignore it for now.
11147          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11148          */
11149         pf = 0;
11150         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11151         intel_ring_emit(ring, pf | pipesrc);
11152
11153         intel_mark_page_flip_active(intel_crtc->unpin_work);
11154         return 0;
11155 }
11156
11157 static int intel_gen6_queue_flip(struct drm_device *dev,
11158                                  struct drm_crtc *crtc,
11159                                  struct drm_framebuffer *fb,
11160                                  struct drm_i915_gem_object *obj,
11161                                  struct drm_i915_gem_request *req,
11162                                  uint32_t flags)
11163 {
11164         struct intel_engine_cs *ring = req->ring;
11165         struct drm_i915_private *dev_priv = dev->dev_private;
11166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11167         uint32_t pf, pipesrc;
11168         int ret;
11169
11170         ret = intel_ring_begin(req, 4);
11171         if (ret)
11172                 return ret;
11173
11174         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11175                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11176         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11177         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11178
11179         /* Contrary to the suggestions in the documentation,
11180          * "Enable Panel Fitter" does not seem to be required when page
11181          * flipping with a non-native mode, and worse causes a normal
11182          * modeset to fail.
11183          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11184          */
11185         pf = 0;
11186         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11187         intel_ring_emit(ring, pf | pipesrc);
11188
11189         intel_mark_page_flip_active(intel_crtc->unpin_work);
11190         return 0;
11191 }
11192
11193 static int intel_gen7_queue_flip(struct drm_device *dev,
11194                                  struct drm_crtc *crtc,
11195                                  struct drm_framebuffer *fb,
11196                                  struct drm_i915_gem_object *obj,
11197                                  struct drm_i915_gem_request *req,
11198                                  uint32_t flags)
11199 {
11200         struct intel_engine_cs *ring = req->ring;
11201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11202         uint32_t plane_bit = 0;
11203         int len, ret;
11204
11205         switch (intel_crtc->plane) {
11206         case PLANE_A:
11207                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11208                 break;
11209         case PLANE_B:
11210                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11211                 break;
11212         case PLANE_C:
11213                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11214                 break;
11215         default:
11216                 WARN_ONCE(1, "unknown plane in flip command\n");
11217                 return -ENODEV;
11218         }
11219
11220         len = 4;
11221         if (ring->id == RCS) {
11222                 len += 6;
11223                 /*
11224                  * On Gen 8, SRM is now taking an extra dword to accommodate
11225                  * 48bits addresses, and we need a NOOP for the batch size to
11226                  * stay even.
11227                  */
11228                 if (IS_GEN8(dev))
11229                         len += 2;
11230         }
11231
11232         /*
11233          * BSpec MI_DISPLAY_FLIP for IVB:
11234          * "The full packet must be contained within the same cache line."
11235          *
11236          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11237          * cacheline, if we ever start emitting more commands before
11238          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11239          * then do the cacheline alignment, and finally emit the
11240          * MI_DISPLAY_FLIP.
11241          */
11242         ret = intel_ring_cacheline_align(req);
11243         if (ret)
11244                 return ret;
11245
11246         ret = intel_ring_begin(req, len);
11247         if (ret)
11248                 return ret;
11249
11250         /* Unmask the flip-done completion message. Note that the bspec says that
11251          * we should do this for both the BCS and RCS, and that we must not unmask
11252          * more than one flip event at any time (or ensure that one flip message
11253          * can be sent by waiting for flip-done prior to queueing new flips).
11254          * Experimentation says that BCS works despite DERRMR masking all
11255          * flip-done completion events and that unmasking all planes at once
11256          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11257          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11258          */
11259         if (ring->id == RCS) {
11260                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11261                 intel_ring_emit_reg(ring, DERRMR);
11262                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11263                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11264                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11265                 if (IS_GEN8(dev))
11266                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11267                                               MI_SRM_LRM_GLOBAL_GTT);
11268                 else
11269                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11270                                               MI_SRM_LRM_GLOBAL_GTT);
11271                 intel_ring_emit_reg(ring, DERRMR);
11272                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11273                 if (IS_GEN8(dev)) {
11274                         intel_ring_emit(ring, 0);
11275                         intel_ring_emit(ring, MI_NOOP);
11276                 }
11277         }
11278
11279         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11280         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11281         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11282         intel_ring_emit(ring, (MI_NOOP));
11283
11284         intel_mark_page_flip_active(intel_crtc->unpin_work);
11285         return 0;
11286 }
11287
11288 static bool use_mmio_flip(struct intel_engine_cs *ring,
11289                           struct drm_i915_gem_object *obj)
11290 {
11291         /*
11292          * This is not being used for older platforms, because
11293          * non-availability of flip done interrupt forces us to use
11294          * CS flips. Older platforms derive flip done using some clever
11295          * tricks involving the flip_pending status bits and vblank irqs.
11296          * So using MMIO flips there would disrupt this mechanism.
11297          */
11298
11299         if (ring == NULL)
11300                 return true;
11301
11302         if (INTEL_INFO(ring->dev)->gen < 5)
11303                 return false;
11304
11305         if (i915.use_mmio_flip < 0)
11306                 return false;
11307         else if (i915.use_mmio_flip > 0)
11308                 return true;
11309         else if (i915.enable_execlists)
11310                 return true;
11311         else if (obj->base.dma_buf &&
11312                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11313                                                        false))
11314                 return true;
11315         else
11316                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11317 }
11318
11319 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11320                              unsigned int rotation,
11321                              struct intel_unpin_work *work)
11322 {
11323         struct drm_device *dev = intel_crtc->base.dev;
11324         struct drm_i915_private *dev_priv = dev->dev_private;
11325         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11326         const enum pipe pipe = intel_crtc->pipe;
11327         u32 ctl, stride, tile_height;
11328
11329         ctl = I915_READ(PLANE_CTL(pipe, 0));
11330         ctl &= ~PLANE_CTL_TILED_MASK;
11331         switch (fb->modifier[0]) {
11332         case DRM_FORMAT_MOD_NONE:
11333                 break;
11334         case I915_FORMAT_MOD_X_TILED:
11335                 ctl |= PLANE_CTL_TILED_X;
11336                 break;
11337         case I915_FORMAT_MOD_Y_TILED:
11338                 ctl |= PLANE_CTL_TILED_Y;
11339                 break;
11340         case I915_FORMAT_MOD_Yf_TILED:
11341                 ctl |= PLANE_CTL_TILED_YF;
11342                 break;
11343         default:
11344                 MISSING_CASE(fb->modifier[0]);
11345         }
11346
11347         /*
11348          * The stride is either expressed as a multiple of 64 bytes chunks for
11349          * linear buffers or in number of tiles for tiled buffers.
11350          */
11351         if (intel_rotation_90_or_270(rotation)) {
11352                 /* stride = Surface height in tiles */
11353                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11354                 stride = DIV_ROUND_UP(fb->height, tile_height);
11355         } else {
11356                 stride = fb->pitches[0] /
11357                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11358                                                   fb->pixel_format);
11359         }
11360
11361         /*
11362          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11363          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11364          */
11365         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11366         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11367
11368         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11369         POSTING_READ(PLANE_SURF(pipe, 0));
11370 }
11371
11372 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11373                              struct intel_unpin_work *work)
11374 {
11375         struct drm_device *dev = intel_crtc->base.dev;
11376         struct drm_i915_private *dev_priv = dev->dev_private;
11377         struct intel_framebuffer *intel_fb =
11378                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11379         struct drm_i915_gem_object *obj = intel_fb->obj;
11380         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11381         u32 dspcntr;
11382
11383         dspcntr = I915_READ(reg);
11384
11385         if (obj->tiling_mode != I915_TILING_NONE)
11386                 dspcntr |= DISPPLANE_TILED;
11387         else
11388                 dspcntr &= ~DISPPLANE_TILED;
11389
11390         I915_WRITE(reg, dspcntr);
11391
11392         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11393         POSTING_READ(DSPSURF(intel_crtc->plane));
11394 }
11395
11396 /*
11397  * XXX: This is the temporary way to update the plane registers until we get
11398  * around to using the usual plane update functions for MMIO flips
11399  */
11400 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11401 {
11402         struct intel_crtc *crtc = mmio_flip->crtc;
11403         struct intel_unpin_work *work;
11404
11405         spin_lock_irq(&crtc->base.dev->event_lock);
11406         work = crtc->unpin_work;
11407         spin_unlock_irq(&crtc->base.dev->event_lock);
11408         if (work == NULL)
11409                 return;
11410
11411         intel_mark_page_flip_active(work);
11412
11413         intel_pipe_update_start(crtc);
11414
11415         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11416                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11417         else
11418                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11419                 ilk_do_mmio_flip(crtc, work);
11420
11421         intel_pipe_update_end(crtc);
11422 }
11423
11424 static void intel_mmio_flip_work_func(struct work_struct *work)
11425 {
11426         struct intel_mmio_flip *mmio_flip =
11427                 container_of(work, struct intel_mmio_flip, work);
11428         struct intel_framebuffer *intel_fb =
11429                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11430         struct drm_i915_gem_object *obj = intel_fb->obj;
11431
11432         if (mmio_flip->req) {
11433                 WARN_ON(__i915_wait_request(mmio_flip->req,
11434                                             mmio_flip->crtc->reset_counter,
11435                                             false, NULL,
11436                                             &mmio_flip->i915->rps.mmioflips));
11437                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11438         }
11439
11440         /* For framebuffer backed by dmabuf, wait for fence */
11441         if (obj->base.dma_buf)
11442                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11443                                                             false, false,
11444                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11445
11446         intel_do_mmio_flip(mmio_flip);
11447         kfree(mmio_flip);
11448 }
11449
11450 static int intel_queue_mmio_flip(struct drm_device *dev,
11451                                  struct drm_crtc *crtc,
11452                                  struct drm_i915_gem_object *obj)
11453 {
11454         struct intel_mmio_flip *mmio_flip;
11455
11456         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11457         if (mmio_flip == NULL)
11458                 return -ENOMEM;
11459
11460         mmio_flip->i915 = to_i915(dev);
11461         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11462         mmio_flip->crtc = to_intel_crtc(crtc);
11463         mmio_flip->rotation = crtc->primary->state->rotation;
11464
11465         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11466         schedule_work(&mmio_flip->work);
11467
11468         return 0;
11469 }
11470
11471 static int intel_default_queue_flip(struct drm_device *dev,
11472                                     struct drm_crtc *crtc,
11473                                     struct drm_framebuffer *fb,
11474                                     struct drm_i915_gem_object *obj,
11475                                     struct drm_i915_gem_request *req,
11476                                     uint32_t flags)
11477 {
11478         return -ENODEV;
11479 }
11480
11481 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11482                                          struct drm_crtc *crtc)
11483 {
11484         struct drm_i915_private *dev_priv = dev->dev_private;
11485         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11486         struct intel_unpin_work *work = intel_crtc->unpin_work;
11487         u32 addr;
11488
11489         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11490                 return true;
11491
11492         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11493                 return false;
11494
11495         if (!work->enable_stall_check)
11496                 return false;
11497
11498         if (work->flip_ready_vblank == 0) {
11499                 if (work->flip_queued_req &&
11500                     !i915_gem_request_completed(work->flip_queued_req, true))
11501                         return false;
11502
11503                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11504         }
11505
11506         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11507                 return false;
11508
11509         /* Potential stall - if we see that the flip has happened,
11510          * assume a missed interrupt. */
11511         if (INTEL_INFO(dev)->gen >= 4)
11512                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11513         else
11514                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11515
11516         /* There is a potential issue here with a false positive after a flip
11517          * to the same address. We could address this by checking for a
11518          * non-incrementing frame counter.
11519          */
11520         return addr == work->gtt_offset;
11521 }
11522
11523 void intel_check_page_flip(struct drm_device *dev, int pipe)
11524 {
11525         struct drm_i915_private *dev_priv = dev->dev_private;
11526         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11528         struct intel_unpin_work *work;
11529
11530         WARN_ON(!in_interrupt());
11531
11532         if (crtc == NULL)
11533                 return;
11534
11535         spin_lock(&dev->event_lock);
11536         work = intel_crtc->unpin_work;
11537         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11538                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11539                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11540                 page_flip_completed(intel_crtc);
11541                 work = NULL;
11542         }
11543         if (work != NULL &&
11544             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11545                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11546         spin_unlock(&dev->event_lock);
11547 }
11548
11549 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11550                                 struct drm_framebuffer *fb,
11551                                 struct drm_pending_vblank_event *event,
11552                                 uint32_t page_flip_flags)
11553 {
11554         struct drm_device *dev = crtc->dev;
11555         struct drm_i915_private *dev_priv = dev->dev_private;
11556         struct drm_framebuffer *old_fb = crtc->primary->fb;
11557         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11559         struct drm_plane *primary = crtc->primary;
11560         enum pipe pipe = intel_crtc->pipe;
11561         struct intel_unpin_work *work;
11562         struct intel_engine_cs *ring;
11563         bool mmio_flip;
11564         struct drm_i915_gem_request *request = NULL;
11565         int ret;
11566
11567         /*
11568          * drm_mode_page_flip_ioctl() should already catch this, but double
11569          * check to be safe.  In the future we may enable pageflipping from
11570          * a disabled primary plane.
11571          */
11572         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11573                 return -EBUSY;
11574
11575         /* Can't change pixel format via MI display flips. */
11576         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11577                 return -EINVAL;
11578
11579         /*
11580          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11581          * Note that pitch changes could also affect these register.
11582          */
11583         if (INTEL_INFO(dev)->gen > 3 &&
11584             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11585              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11586                 return -EINVAL;
11587
11588         if (i915_terminally_wedged(&dev_priv->gpu_error))
11589                 goto out_hang;
11590
11591         work = kzalloc(sizeof(*work), GFP_KERNEL);
11592         if (work == NULL)
11593                 return -ENOMEM;
11594
11595         work->event = event;
11596         work->crtc = crtc;
11597         work->old_fb = old_fb;
11598         INIT_WORK(&work->work, intel_unpin_work_fn);
11599
11600         ret = drm_crtc_vblank_get(crtc);
11601         if (ret)
11602                 goto free_work;
11603
11604         /* We borrow the event spin lock for protecting unpin_work */
11605         spin_lock_irq(&dev->event_lock);
11606         if (intel_crtc->unpin_work) {
11607                 /* Before declaring the flip queue wedged, check if
11608                  * the hardware completed the operation behind our backs.
11609                  */
11610                 if (__intel_pageflip_stall_check(dev, crtc)) {
11611                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11612                         page_flip_completed(intel_crtc);
11613                 } else {
11614                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11615                         spin_unlock_irq(&dev->event_lock);
11616
11617                         drm_crtc_vblank_put(crtc);
11618                         kfree(work);
11619                         return -EBUSY;
11620                 }
11621         }
11622         intel_crtc->unpin_work = work;
11623         spin_unlock_irq(&dev->event_lock);
11624
11625         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11626                 flush_workqueue(dev_priv->wq);
11627
11628         /* Reference the objects for the scheduled work. */
11629         drm_framebuffer_reference(work->old_fb);
11630         drm_gem_object_reference(&obj->base);
11631
11632         crtc->primary->fb = fb;
11633         update_state_fb(crtc->primary);
11634
11635         work->pending_flip_obj = obj;
11636
11637         ret = i915_mutex_lock_interruptible(dev);
11638         if (ret)
11639                 goto cleanup;
11640
11641         atomic_inc(&intel_crtc->unpin_work_count);
11642         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11643
11644         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11645                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11646
11647         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11648                 ring = &dev_priv->ring[BCS];
11649                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11650                         /* vlv: DISPLAY_FLIP fails to change tiling */
11651                         ring = NULL;
11652         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11653                 ring = &dev_priv->ring[BCS];
11654         } else if (INTEL_INFO(dev)->gen >= 7) {
11655                 ring = i915_gem_request_get_ring(obj->last_write_req);
11656                 if (ring == NULL || ring->id != RCS)
11657                         ring = &dev_priv->ring[BCS];
11658         } else {
11659                 ring = &dev_priv->ring[RCS];
11660         }
11661
11662         mmio_flip = use_mmio_flip(ring, obj);
11663
11664         /* When using CS flips, we want to emit semaphores between rings.
11665          * However, when using mmio flips we will create a task to do the
11666          * synchronisation, so all we want here is to pin the framebuffer
11667          * into the display plane and skip any waits.
11668          */
11669         if (!mmio_flip) {
11670                 ret = i915_gem_object_sync(obj, ring, &request);
11671                 if (ret)
11672                         goto cleanup_pending;
11673         }
11674
11675         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11676                                          crtc->primary->state);
11677         if (ret)
11678                 goto cleanup_pending;
11679
11680         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11681                                                   obj, 0);
11682         work->gtt_offset += intel_crtc->dspaddr_offset;
11683
11684         if (mmio_flip) {
11685                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11686                 if (ret)
11687                         goto cleanup_unpin;
11688
11689                 i915_gem_request_assign(&work->flip_queued_req,
11690                                         obj->last_write_req);
11691         } else {
11692                 if (!request) {
11693                         request = i915_gem_request_alloc(ring, NULL);
11694                         if (IS_ERR(request)) {
11695                                 ret = PTR_ERR(request);
11696                                 goto cleanup_unpin;
11697                         }
11698                 }
11699
11700                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11701                                                    page_flip_flags);
11702                 if (ret)
11703                         goto cleanup_unpin;
11704
11705                 i915_gem_request_assign(&work->flip_queued_req, request);
11706         }
11707
11708         if (request)
11709                 i915_add_request_no_flush(request);
11710
11711         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11712         work->enable_stall_check = true;
11713
11714         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11715                           to_intel_plane(primary)->frontbuffer_bit);
11716         mutex_unlock(&dev->struct_mutex);
11717
11718         intel_fbc_deactivate(intel_crtc);
11719         intel_frontbuffer_flip_prepare(dev,
11720                                        to_intel_plane(primary)->frontbuffer_bit);
11721
11722         trace_i915_flip_request(intel_crtc->plane, obj);
11723
11724         return 0;
11725
11726 cleanup_unpin:
11727         intel_unpin_fb_obj(fb, crtc->primary->state);
11728 cleanup_pending:
11729         if (request)
11730                 i915_gem_request_cancel(request);
11731         atomic_dec(&intel_crtc->unpin_work_count);
11732         mutex_unlock(&dev->struct_mutex);
11733 cleanup:
11734         crtc->primary->fb = old_fb;
11735         update_state_fb(crtc->primary);
11736
11737         drm_gem_object_unreference_unlocked(&obj->base);
11738         drm_framebuffer_unreference(work->old_fb);
11739
11740         spin_lock_irq(&dev->event_lock);
11741         intel_crtc->unpin_work = NULL;
11742         spin_unlock_irq(&dev->event_lock);
11743
11744         drm_crtc_vblank_put(crtc);
11745 free_work:
11746         kfree(work);
11747
11748         if (ret == -EIO) {
11749                 struct drm_atomic_state *state;
11750                 struct drm_plane_state *plane_state;
11751
11752 out_hang:
11753                 state = drm_atomic_state_alloc(dev);
11754                 if (!state)
11755                         return -ENOMEM;
11756                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11757
11758 retry:
11759                 plane_state = drm_atomic_get_plane_state(state, primary);
11760                 ret = PTR_ERR_OR_ZERO(plane_state);
11761                 if (!ret) {
11762                         drm_atomic_set_fb_for_plane(plane_state, fb);
11763
11764                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11765                         if (!ret)
11766                                 ret = drm_atomic_commit(state);
11767                 }
11768
11769                 if (ret == -EDEADLK) {
11770                         drm_modeset_backoff(state->acquire_ctx);
11771                         drm_atomic_state_clear(state);
11772                         goto retry;
11773                 }
11774
11775                 if (ret)
11776                         drm_atomic_state_free(state);
11777
11778                 if (ret == 0 && event) {
11779                         spin_lock_irq(&dev->event_lock);
11780                         drm_send_vblank_event(dev, pipe, event);
11781                         spin_unlock_irq(&dev->event_lock);
11782                 }
11783         }
11784         return ret;
11785 }
11786
11787
11788 /**
11789  * intel_wm_need_update - Check whether watermarks need updating
11790  * @plane: drm plane
11791  * @state: new plane state
11792  *
11793  * Check current plane state versus the new one to determine whether
11794  * watermarks need to be recalculated.
11795  *
11796  * Returns true or false.
11797  */
11798 static bool intel_wm_need_update(struct drm_plane *plane,
11799                                  struct drm_plane_state *state)
11800 {
11801         struct intel_plane_state *new = to_intel_plane_state(state);
11802         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11803
11804         /* Update watermarks on tiling or size changes. */
11805         if (new->visible != cur->visible)
11806                 return true;
11807
11808         if (!cur->base.fb || !new->base.fb)
11809                 return false;
11810
11811         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11812             cur->base.rotation != new->base.rotation ||
11813             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11814             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11815             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11816             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11817                 return true;
11818
11819         return false;
11820 }
11821
11822 static bool needs_scaling(struct intel_plane_state *state)
11823 {
11824         int src_w = drm_rect_width(&state->src) >> 16;
11825         int src_h = drm_rect_height(&state->src) >> 16;
11826         int dst_w = drm_rect_width(&state->dst);
11827         int dst_h = drm_rect_height(&state->dst);
11828
11829         return (src_w != dst_w || src_h != dst_h);
11830 }
11831
11832 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11833                                     struct drm_plane_state *plane_state)
11834 {
11835         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11836         struct drm_crtc *crtc = crtc_state->crtc;
11837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11838         struct drm_plane *plane = plane_state->plane;
11839         struct drm_device *dev = crtc->dev;
11840         struct drm_i915_private *dev_priv = dev->dev_private;
11841         struct intel_plane_state *old_plane_state =
11842                 to_intel_plane_state(plane->state);
11843         int idx = intel_crtc->base.base.id, ret;
11844         int i = drm_plane_index(plane);
11845         bool mode_changed = needs_modeset(crtc_state);
11846         bool was_crtc_enabled = crtc->state->active;
11847         bool is_crtc_enabled = crtc_state->active;
11848         bool turn_off, turn_on, visible, was_visible;
11849         struct drm_framebuffer *fb = plane_state->fb;
11850
11851         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11852             plane->type != DRM_PLANE_TYPE_CURSOR) {
11853                 ret = skl_update_scaler_plane(
11854                         to_intel_crtc_state(crtc_state),
11855                         to_intel_plane_state(plane_state));
11856                 if (ret)
11857                         return ret;
11858         }
11859
11860         was_visible = old_plane_state->visible;
11861         visible = to_intel_plane_state(plane_state)->visible;
11862
11863         if (!was_crtc_enabled && WARN_ON(was_visible))
11864                 was_visible = false;
11865
11866         /*
11867          * Visibility is calculated as if the crtc was on, but
11868          * after scaler setup everything depends on it being off
11869          * when the crtc isn't active.
11870          */
11871         if (!is_crtc_enabled)
11872                 to_intel_plane_state(plane_state)->visible = visible = false;
11873
11874         if (!was_visible && !visible)
11875                 return 0;
11876
11877         turn_off = was_visible && (!visible || mode_changed);
11878         turn_on = visible && (!was_visible || mode_changed);
11879
11880         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11881                          plane->base.id, fb ? fb->base.id : -1);
11882
11883         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11884                          plane->base.id, was_visible, visible,
11885                          turn_off, turn_on, mode_changed);
11886
11887         if (turn_on || turn_off) {
11888                 pipe_config->wm_changed = true;
11889
11890                 /* must disable cxsr around plane enable/disable */
11891                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11892                         if (is_crtc_enabled)
11893                                 intel_crtc->atomic.wait_vblank = true;
11894                         pipe_config->disable_cxsr = true;
11895                 }
11896         } else if (intel_wm_need_update(plane, plane_state)) {
11897                 pipe_config->wm_changed = true;
11898         }
11899
11900         if (visible || was_visible)
11901                 intel_crtc->atomic.fb_bits |=
11902                         to_intel_plane(plane)->frontbuffer_bit;
11903
11904         switch (plane->type) {
11905         case DRM_PLANE_TYPE_PRIMARY:
11906                 intel_crtc->atomic.pre_disable_primary = turn_off;
11907                 intel_crtc->atomic.post_enable_primary = turn_on;
11908
11909                 if (turn_off) {
11910                         /*
11911                          * FIXME: Actually if we will still have any other
11912                          * plane enabled on the pipe we could let IPS enabled
11913                          * still, but for now lets consider that when we make
11914                          * primary invisible by setting DSPCNTR to 0 on
11915                          * update_primary_plane function IPS needs to be
11916                          * disable.
11917                          */
11918                         intel_crtc->atomic.disable_ips = true;
11919
11920                         intel_crtc->atomic.disable_fbc = true;
11921                 }
11922
11923                 /*
11924                  * FBC does not work on some platforms for rotated
11925                  * planes, so disable it when rotation is not 0 and
11926                  * update it when rotation is set back to 0.
11927                  *
11928                  * FIXME: This is redundant with the fbc update done in
11929                  * the primary plane enable function except that that
11930                  * one is done too late. We eventually need to unify
11931                  * this.
11932                  */
11933
11934                 if (visible &&
11935                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11936                     dev_priv->fbc.crtc == intel_crtc &&
11937                     plane_state->rotation != BIT(DRM_ROTATE_0))
11938                         intel_crtc->atomic.disable_fbc = true;
11939
11940                 /*
11941                  * BDW signals flip done immediately if the plane
11942                  * is disabled, even if the plane enable is already
11943                  * armed to occur at the next vblank :(
11944                  */
11945                 if (turn_on && IS_BROADWELL(dev))
11946                         intel_crtc->atomic.wait_vblank = true;
11947
11948                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11949                 break;
11950         case DRM_PLANE_TYPE_CURSOR:
11951                 break;
11952         case DRM_PLANE_TYPE_OVERLAY:
11953                 /*
11954                  * WaCxSRDisabledForSpriteScaling:ivb
11955                  *
11956                  * cstate->update_wm was already set above, so this flag will
11957                  * take effect when we commit and program watermarks.
11958                  */
11959                 if (IS_IVYBRIDGE(dev) &&
11960                     needs_scaling(to_intel_plane_state(plane_state)) &&
11961                     !needs_scaling(old_plane_state)) {
11962                         to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11963                 } else if (turn_off && !mode_changed) {
11964                         intel_crtc->atomic.wait_vblank = true;
11965                         intel_crtc->atomic.update_sprite_watermarks |=
11966                                 1 << i;
11967                 }
11968
11969                 break;
11970         }
11971         return 0;
11972 }
11973
11974 static bool encoders_cloneable(const struct intel_encoder *a,
11975                                const struct intel_encoder *b)
11976 {
11977         /* masks could be asymmetric, so check both ways */
11978         return a == b || (a->cloneable & (1 << b->type) &&
11979                           b->cloneable & (1 << a->type));
11980 }
11981
11982 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11983                                          struct intel_crtc *crtc,
11984                                          struct intel_encoder *encoder)
11985 {
11986         struct intel_encoder *source_encoder;
11987         struct drm_connector *connector;
11988         struct drm_connector_state *connector_state;
11989         int i;
11990
11991         for_each_connector_in_state(state, connector, connector_state, i) {
11992                 if (connector_state->crtc != &crtc->base)
11993                         continue;
11994
11995                 source_encoder =
11996                         to_intel_encoder(connector_state->best_encoder);
11997                 if (!encoders_cloneable(encoder, source_encoder))
11998                         return false;
11999         }
12000
12001         return true;
12002 }
12003
12004 static bool check_encoder_cloning(struct drm_atomic_state *state,
12005                                   struct intel_crtc *crtc)
12006 {
12007         struct intel_encoder *encoder;
12008         struct drm_connector *connector;
12009         struct drm_connector_state *connector_state;
12010         int i;
12011
12012         for_each_connector_in_state(state, connector, connector_state, i) {
12013                 if (connector_state->crtc != &crtc->base)
12014                         continue;
12015
12016                 encoder = to_intel_encoder(connector_state->best_encoder);
12017                 if (!check_single_encoder_cloning(state, crtc, encoder))
12018                         return false;
12019         }
12020
12021         return true;
12022 }
12023
12024 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12025                                    struct drm_crtc_state *crtc_state)
12026 {
12027         struct drm_device *dev = crtc->dev;
12028         struct drm_i915_private *dev_priv = dev->dev_private;
12029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12030         struct intel_crtc_state *pipe_config =
12031                 to_intel_crtc_state(crtc_state);
12032         struct drm_atomic_state *state = crtc_state->state;
12033         int ret;
12034         bool mode_changed = needs_modeset(crtc_state);
12035
12036         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12037                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12038                 return -EINVAL;
12039         }
12040
12041         if (mode_changed && !crtc_state->active)
12042                 pipe_config->wm_changed = true;
12043
12044         if (mode_changed && crtc_state->enable &&
12045             dev_priv->display.crtc_compute_clock &&
12046             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
12047                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12048                                                            pipe_config);
12049                 if (ret)
12050                         return ret;
12051         }
12052
12053         ret = 0;
12054         if (dev_priv->display.compute_pipe_wm) {
12055                 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12056                 if (ret)
12057                         return ret;
12058         }
12059
12060         if (INTEL_INFO(dev)->gen >= 9) {
12061                 if (mode_changed)
12062                         ret = skl_update_scaler_crtc(pipe_config);
12063
12064                 if (!ret)
12065                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12066                                                          pipe_config);
12067         }
12068
12069         return ret;
12070 }
12071
12072 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12073         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12074         .load_lut = intel_crtc_load_lut,
12075         .atomic_begin = intel_begin_crtc_commit,
12076         .atomic_flush = intel_finish_crtc_commit,
12077         .atomic_check = intel_crtc_atomic_check,
12078 };
12079
12080 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12081 {
12082         struct intel_connector *connector;
12083
12084         for_each_intel_connector(dev, connector) {
12085                 if (connector->base.encoder) {
12086                         connector->base.state->best_encoder =
12087                                 connector->base.encoder;
12088                         connector->base.state->crtc =
12089                                 connector->base.encoder->crtc;
12090                 } else {
12091                         connector->base.state->best_encoder = NULL;
12092                         connector->base.state->crtc = NULL;
12093                 }
12094         }
12095 }
12096
12097 static void
12098 connected_sink_compute_bpp(struct intel_connector *connector,
12099                            struct intel_crtc_state *pipe_config)
12100 {
12101         int bpp = pipe_config->pipe_bpp;
12102
12103         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12104                 connector->base.base.id,
12105                 connector->base.name);
12106
12107         /* Don't use an invalid EDID bpc value */
12108         if (connector->base.display_info.bpc &&
12109             connector->base.display_info.bpc * 3 < bpp) {
12110                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12111                               bpp, connector->base.display_info.bpc*3);
12112                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12113         }
12114
12115         /* Clamp bpp to default limit on screens without EDID 1.4 */
12116         if (connector->base.display_info.bpc == 0) {
12117                 int type = connector->base.connector_type;
12118                 int clamp_bpp = 24;
12119
12120                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12121                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12122                     type == DRM_MODE_CONNECTOR_eDP)
12123                         clamp_bpp = 18;
12124
12125                 if (bpp > clamp_bpp) {
12126                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12127                                       bpp, clamp_bpp);
12128                         pipe_config->pipe_bpp = clamp_bpp;
12129                 }
12130         }
12131 }
12132
12133 static int
12134 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12135                           struct intel_crtc_state *pipe_config)
12136 {
12137         struct drm_device *dev = crtc->base.dev;
12138         struct drm_atomic_state *state;
12139         struct drm_connector *connector;
12140         struct drm_connector_state *connector_state;
12141         int bpp, i;
12142
12143         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12144                 bpp = 10*3;
12145         else if (INTEL_INFO(dev)->gen >= 5)
12146                 bpp = 12*3;
12147         else
12148                 bpp = 8*3;
12149
12150
12151         pipe_config->pipe_bpp = bpp;
12152
12153         state = pipe_config->base.state;
12154
12155         /* Clamp display bpp to EDID value */
12156         for_each_connector_in_state(state, connector, connector_state, i) {
12157                 if (connector_state->crtc != &crtc->base)
12158                         continue;
12159
12160                 connected_sink_compute_bpp(to_intel_connector(connector),
12161                                            pipe_config);
12162         }
12163
12164         return bpp;
12165 }
12166
12167 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12168 {
12169         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12170                         "type: 0x%x flags: 0x%x\n",
12171                 mode->crtc_clock,
12172                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12173                 mode->crtc_hsync_end, mode->crtc_htotal,
12174                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12175                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12176 }
12177
12178 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12179                                    struct intel_crtc_state *pipe_config,
12180                                    const char *context)
12181 {
12182         struct drm_device *dev = crtc->base.dev;
12183         struct drm_plane *plane;
12184         struct intel_plane *intel_plane;
12185         struct intel_plane_state *state;
12186         struct drm_framebuffer *fb;
12187
12188         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12189                       context, pipe_config, pipe_name(crtc->pipe));
12190
12191         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12192         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12193                       pipe_config->pipe_bpp, pipe_config->dither);
12194         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12195                       pipe_config->has_pch_encoder,
12196                       pipe_config->fdi_lanes,
12197                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12198                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12199                       pipe_config->fdi_m_n.tu);
12200         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12201                       pipe_config->has_dp_encoder,
12202                       pipe_config->lane_count,
12203                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12204                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12205                       pipe_config->dp_m_n.tu);
12206
12207         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12208                       pipe_config->has_dp_encoder,
12209                       pipe_config->lane_count,
12210                       pipe_config->dp_m2_n2.gmch_m,
12211                       pipe_config->dp_m2_n2.gmch_n,
12212                       pipe_config->dp_m2_n2.link_m,
12213                       pipe_config->dp_m2_n2.link_n,
12214                       pipe_config->dp_m2_n2.tu);
12215
12216         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12217                       pipe_config->has_audio,
12218                       pipe_config->has_infoframe);
12219
12220         DRM_DEBUG_KMS("requested mode:\n");
12221         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12222         DRM_DEBUG_KMS("adjusted mode:\n");
12223         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12224         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12225         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12226         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12227                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12228         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12229                       crtc->num_scalers,
12230                       pipe_config->scaler_state.scaler_users,
12231                       pipe_config->scaler_state.scaler_id);
12232         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12233                       pipe_config->gmch_pfit.control,
12234                       pipe_config->gmch_pfit.pgm_ratios,
12235                       pipe_config->gmch_pfit.lvds_border_bits);
12236         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12237                       pipe_config->pch_pfit.pos,
12238                       pipe_config->pch_pfit.size,
12239                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12240         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12241         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12242
12243         if (IS_BROXTON(dev)) {
12244                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12245                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12246                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12247                               pipe_config->ddi_pll_sel,
12248                               pipe_config->dpll_hw_state.ebb0,
12249                               pipe_config->dpll_hw_state.ebb4,
12250                               pipe_config->dpll_hw_state.pll0,
12251                               pipe_config->dpll_hw_state.pll1,
12252                               pipe_config->dpll_hw_state.pll2,
12253                               pipe_config->dpll_hw_state.pll3,
12254                               pipe_config->dpll_hw_state.pll6,
12255                               pipe_config->dpll_hw_state.pll8,
12256                               pipe_config->dpll_hw_state.pll9,
12257                               pipe_config->dpll_hw_state.pll10,
12258                               pipe_config->dpll_hw_state.pcsdw12);
12259         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12260                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12261                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12262                               pipe_config->ddi_pll_sel,
12263                               pipe_config->dpll_hw_state.ctrl1,
12264                               pipe_config->dpll_hw_state.cfgcr1,
12265                               pipe_config->dpll_hw_state.cfgcr2);
12266         } else if (HAS_DDI(dev)) {
12267                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12268                               pipe_config->ddi_pll_sel,
12269                               pipe_config->dpll_hw_state.wrpll,
12270                               pipe_config->dpll_hw_state.spll);
12271         } else {
12272                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12273                               "fp0: 0x%x, fp1: 0x%x\n",
12274                               pipe_config->dpll_hw_state.dpll,
12275                               pipe_config->dpll_hw_state.dpll_md,
12276                               pipe_config->dpll_hw_state.fp0,
12277                               pipe_config->dpll_hw_state.fp1);
12278         }
12279
12280         DRM_DEBUG_KMS("planes on this crtc\n");
12281         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12282                 intel_plane = to_intel_plane(plane);
12283                 if (intel_plane->pipe != crtc->pipe)
12284                         continue;
12285
12286                 state = to_intel_plane_state(plane->state);
12287                 fb = state->base.fb;
12288                 if (!fb) {
12289                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12290                                 "disabled, scaler_id = %d\n",
12291                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12292                                 plane->base.id, intel_plane->pipe,
12293                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12294                                 drm_plane_index(plane), state->scaler_id);
12295                         continue;
12296                 }
12297
12298                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12299                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12300                         plane->base.id, intel_plane->pipe,
12301                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12302                         drm_plane_index(plane));
12303                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12304                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12305                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12306                         state->scaler_id,
12307                         state->src.x1 >> 16, state->src.y1 >> 16,
12308                         drm_rect_width(&state->src) >> 16,
12309                         drm_rect_height(&state->src) >> 16,
12310                         state->dst.x1, state->dst.y1,
12311                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12312         }
12313 }
12314
12315 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12316 {
12317         struct drm_device *dev = state->dev;
12318         struct drm_connector *connector;
12319         unsigned int used_ports = 0;
12320
12321         /*
12322          * Walk the connector list instead of the encoder
12323          * list to detect the problem on ddi platforms
12324          * where there's just one encoder per digital port.
12325          */
12326         drm_for_each_connector(connector, dev) {
12327                 struct drm_connector_state *connector_state;
12328                 struct intel_encoder *encoder;
12329
12330                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12331                 if (!connector_state)
12332                         connector_state = connector->state;
12333
12334                 if (!connector_state->best_encoder)
12335                         continue;
12336
12337                 encoder = to_intel_encoder(connector_state->best_encoder);
12338
12339                 WARN_ON(!connector_state->crtc);
12340
12341                 switch (encoder->type) {
12342                         unsigned int port_mask;
12343                 case INTEL_OUTPUT_UNKNOWN:
12344                         if (WARN_ON(!HAS_DDI(dev)))
12345                                 break;
12346                 case INTEL_OUTPUT_DISPLAYPORT:
12347                 case INTEL_OUTPUT_HDMI:
12348                 case INTEL_OUTPUT_EDP:
12349                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12350
12351                         /* the same port mustn't appear more than once */
12352                         if (used_ports & port_mask)
12353                                 return false;
12354
12355                         used_ports |= port_mask;
12356                 default:
12357                         break;
12358                 }
12359         }
12360
12361         return true;
12362 }
12363
12364 static void
12365 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12366 {
12367         struct drm_crtc_state tmp_state;
12368         struct intel_crtc_scaler_state scaler_state;
12369         struct intel_dpll_hw_state dpll_hw_state;
12370         enum intel_dpll_id shared_dpll;
12371         uint32_t ddi_pll_sel;
12372         bool force_thru;
12373
12374         /* FIXME: before the switch to atomic started, a new pipe_config was
12375          * kzalloc'd. Code that depends on any field being zero should be
12376          * fixed, so that the crtc_state can be safely duplicated. For now,
12377          * only fields that are know to not cause problems are preserved. */
12378
12379         tmp_state = crtc_state->base;
12380         scaler_state = crtc_state->scaler_state;
12381         shared_dpll = crtc_state->shared_dpll;
12382         dpll_hw_state = crtc_state->dpll_hw_state;
12383         ddi_pll_sel = crtc_state->ddi_pll_sel;
12384         force_thru = crtc_state->pch_pfit.force_thru;
12385
12386         memset(crtc_state, 0, sizeof *crtc_state);
12387
12388         crtc_state->base = tmp_state;
12389         crtc_state->scaler_state = scaler_state;
12390         crtc_state->shared_dpll = shared_dpll;
12391         crtc_state->dpll_hw_state = dpll_hw_state;
12392         crtc_state->ddi_pll_sel = ddi_pll_sel;
12393         crtc_state->pch_pfit.force_thru = force_thru;
12394 }
12395
12396 static int
12397 intel_modeset_pipe_config(struct drm_crtc *crtc,
12398                           struct intel_crtc_state *pipe_config)
12399 {
12400         struct drm_atomic_state *state = pipe_config->base.state;
12401         struct intel_encoder *encoder;
12402         struct drm_connector *connector;
12403         struct drm_connector_state *connector_state;
12404         int base_bpp, ret = -EINVAL;
12405         int i;
12406         bool retry = true;
12407
12408         clear_intel_crtc_state(pipe_config);
12409
12410         pipe_config->cpu_transcoder =
12411                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12412
12413         /*
12414          * Sanitize sync polarity flags based on requested ones. If neither
12415          * positive or negative polarity is requested, treat this as meaning
12416          * negative polarity.
12417          */
12418         if (!(pipe_config->base.adjusted_mode.flags &
12419               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12420                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12421
12422         if (!(pipe_config->base.adjusted_mode.flags &
12423               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12424                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12425
12426         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12427                                              pipe_config);
12428         if (base_bpp < 0)
12429                 goto fail;
12430
12431         /*
12432          * Determine the real pipe dimensions. Note that stereo modes can
12433          * increase the actual pipe size due to the frame doubling and
12434          * insertion of additional space for blanks between the frame. This
12435          * is stored in the crtc timings. We use the requested mode to do this
12436          * computation to clearly distinguish it from the adjusted mode, which
12437          * can be changed by the connectors in the below retry loop.
12438          */
12439         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12440                                &pipe_config->pipe_src_w,
12441                                &pipe_config->pipe_src_h);
12442
12443 encoder_retry:
12444         /* Ensure the port clock defaults are reset when retrying. */
12445         pipe_config->port_clock = 0;
12446         pipe_config->pixel_multiplier = 1;
12447
12448         /* Fill in default crtc timings, allow encoders to overwrite them. */
12449         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12450                               CRTC_STEREO_DOUBLE);
12451
12452         /* Pass our mode to the connectors and the CRTC to give them a chance to
12453          * adjust it according to limitations or connector properties, and also
12454          * a chance to reject the mode entirely.
12455          */
12456         for_each_connector_in_state(state, connector, connector_state, i) {
12457                 if (connector_state->crtc != crtc)
12458                         continue;
12459
12460                 encoder = to_intel_encoder(connector_state->best_encoder);
12461
12462                 if (!(encoder->compute_config(encoder, pipe_config))) {
12463                         DRM_DEBUG_KMS("Encoder config failure\n");
12464                         goto fail;
12465                 }
12466         }
12467
12468         /* Set default port clock if not overwritten by the encoder. Needs to be
12469          * done afterwards in case the encoder adjusts the mode. */
12470         if (!pipe_config->port_clock)
12471                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12472                         * pipe_config->pixel_multiplier;
12473
12474         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12475         if (ret < 0) {
12476                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12477                 goto fail;
12478         }
12479
12480         if (ret == RETRY) {
12481                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12482                         ret = -EINVAL;
12483                         goto fail;
12484                 }
12485
12486                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12487                 retry = false;
12488                 goto encoder_retry;
12489         }
12490
12491         /* Dithering seems to not pass-through bits correctly when it should, so
12492          * only enable it on 6bpc panels. */
12493         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12494         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12495                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12496
12497 fail:
12498         return ret;
12499 }
12500
12501 static void
12502 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12503 {
12504         struct drm_crtc *crtc;
12505         struct drm_crtc_state *crtc_state;
12506         int i;
12507
12508         /* Double check state. */
12509         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12510                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12511
12512                 /* Update hwmode for vblank functions */
12513                 if (crtc->state->active)
12514                         crtc->hwmode = crtc->state->adjusted_mode;
12515                 else
12516                         crtc->hwmode.crtc_clock = 0;
12517
12518                 /*
12519                  * Update legacy state to satisfy fbc code. This can
12520                  * be removed when fbc uses the atomic state.
12521                  */
12522                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12523                         struct drm_plane_state *plane_state = crtc->primary->state;
12524
12525                         crtc->primary->fb = plane_state->fb;
12526                         crtc->x = plane_state->src_x >> 16;
12527                         crtc->y = plane_state->src_y >> 16;
12528                 }
12529         }
12530 }
12531
12532 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12533 {
12534         int diff;
12535
12536         if (clock1 == clock2)
12537                 return true;
12538
12539         if (!clock1 || !clock2)
12540                 return false;
12541
12542         diff = abs(clock1 - clock2);
12543
12544         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12545                 return true;
12546
12547         return false;
12548 }
12549
12550 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12551         list_for_each_entry((intel_crtc), \
12552                             &(dev)->mode_config.crtc_list, \
12553                             base.head) \
12554                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12555
12556 static bool
12557 intel_compare_m_n(unsigned int m, unsigned int n,
12558                   unsigned int m2, unsigned int n2,
12559                   bool exact)
12560 {
12561         if (m == m2 && n == n2)
12562                 return true;
12563
12564         if (exact || !m || !n || !m2 || !n2)
12565                 return false;
12566
12567         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12568
12569         if (n > n2) {
12570                 while (n > n2) {
12571                         m2 <<= 1;
12572                         n2 <<= 1;
12573                 }
12574         } else if (n < n2) {
12575                 while (n < n2) {
12576                         m <<= 1;
12577                         n <<= 1;
12578                 }
12579         }
12580
12581         if (n != n2)
12582                 return false;
12583
12584         return intel_fuzzy_clock_check(m, m2);
12585 }
12586
12587 static bool
12588 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12589                        struct intel_link_m_n *m2_n2,
12590                        bool adjust)
12591 {
12592         if (m_n->tu == m2_n2->tu &&
12593             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12594                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12595             intel_compare_m_n(m_n->link_m, m_n->link_n,
12596                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12597                 if (adjust)
12598                         *m2_n2 = *m_n;
12599
12600                 return true;
12601         }
12602
12603         return false;
12604 }
12605
12606 static bool
12607 intel_pipe_config_compare(struct drm_device *dev,
12608                           struct intel_crtc_state *current_config,
12609                           struct intel_crtc_state *pipe_config,
12610                           bool adjust)
12611 {
12612         bool ret = true;
12613
12614 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12615         do { \
12616                 if (!adjust) \
12617                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12618                 else \
12619                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12620         } while (0)
12621
12622 #define PIPE_CONF_CHECK_X(name) \
12623         if (current_config->name != pipe_config->name) { \
12624                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12625                           "(expected 0x%08x, found 0x%08x)\n", \
12626                           current_config->name, \
12627                           pipe_config->name); \
12628                 ret = false; \
12629         }
12630
12631 #define PIPE_CONF_CHECK_I(name) \
12632         if (current_config->name != pipe_config->name) { \
12633                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12634                           "(expected %i, found %i)\n", \
12635                           current_config->name, \
12636                           pipe_config->name); \
12637                 ret = false; \
12638         }
12639
12640 #define PIPE_CONF_CHECK_M_N(name) \
12641         if (!intel_compare_link_m_n(&current_config->name, \
12642                                     &pipe_config->name,\
12643                                     adjust)) { \
12644                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12645                           "(expected tu %i gmch %i/%i link %i/%i, " \
12646                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12647                           current_config->name.tu, \
12648                           current_config->name.gmch_m, \
12649                           current_config->name.gmch_n, \
12650                           current_config->name.link_m, \
12651                           current_config->name.link_n, \
12652                           pipe_config->name.tu, \
12653                           pipe_config->name.gmch_m, \
12654                           pipe_config->name.gmch_n, \
12655                           pipe_config->name.link_m, \
12656                           pipe_config->name.link_n); \
12657                 ret = false; \
12658         }
12659
12660 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12661         if (!intel_compare_link_m_n(&current_config->name, \
12662                                     &pipe_config->name, adjust) && \
12663             !intel_compare_link_m_n(&current_config->alt_name, \
12664                                     &pipe_config->name, adjust)) { \
12665                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12666                           "(expected tu %i gmch %i/%i link %i/%i, " \
12667                           "or tu %i gmch %i/%i link %i/%i, " \
12668                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12669                           current_config->name.tu, \
12670                           current_config->name.gmch_m, \
12671                           current_config->name.gmch_n, \
12672                           current_config->name.link_m, \
12673                           current_config->name.link_n, \
12674                           current_config->alt_name.tu, \
12675                           current_config->alt_name.gmch_m, \
12676                           current_config->alt_name.gmch_n, \
12677                           current_config->alt_name.link_m, \
12678                           current_config->alt_name.link_n, \
12679                           pipe_config->name.tu, \
12680                           pipe_config->name.gmch_m, \
12681                           pipe_config->name.gmch_n, \
12682                           pipe_config->name.link_m, \
12683                           pipe_config->name.link_n); \
12684                 ret = false; \
12685         }
12686
12687 /* This is required for BDW+ where there is only one set of registers for
12688  * switching between high and low RR.
12689  * This macro can be used whenever a comparison has to be made between one
12690  * hw state and multiple sw state variables.
12691  */
12692 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12693         if ((current_config->name != pipe_config->name) && \
12694                 (current_config->alt_name != pipe_config->name)) { \
12695                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12696                                   "(expected %i or %i, found %i)\n", \
12697                                   current_config->name, \
12698                                   current_config->alt_name, \
12699                                   pipe_config->name); \
12700                         ret = false; \
12701         }
12702
12703 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12704         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12705                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12706                           "(expected %i, found %i)\n", \
12707                           current_config->name & (mask), \
12708                           pipe_config->name & (mask)); \
12709                 ret = false; \
12710         }
12711
12712 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12713         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12714                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12715                           "(expected %i, found %i)\n", \
12716                           current_config->name, \
12717                           pipe_config->name); \
12718                 ret = false; \
12719         }
12720
12721 #define PIPE_CONF_QUIRK(quirk)  \
12722         ((current_config->quirks | pipe_config->quirks) & (quirk))
12723
12724         PIPE_CONF_CHECK_I(cpu_transcoder);
12725
12726         PIPE_CONF_CHECK_I(has_pch_encoder);
12727         PIPE_CONF_CHECK_I(fdi_lanes);
12728         PIPE_CONF_CHECK_M_N(fdi_m_n);
12729
12730         PIPE_CONF_CHECK_I(has_dp_encoder);
12731         PIPE_CONF_CHECK_I(lane_count);
12732
12733         if (INTEL_INFO(dev)->gen < 8) {
12734                 PIPE_CONF_CHECK_M_N(dp_m_n);
12735
12736                 if (current_config->has_drrs)
12737                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12738         } else
12739                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12740
12741         PIPE_CONF_CHECK_I(has_dsi_encoder);
12742
12743         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12744         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12745         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12746         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12747         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12748         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12749
12750         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12751         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12752         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12753         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12754         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12755         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12756
12757         PIPE_CONF_CHECK_I(pixel_multiplier);
12758         PIPE_CONF_CHECK_I(has_hdmi_sink);
12759         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12760             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12761                 PIPE_CONF_CHECK_I(limited_color_range);
12762         PIPE_CONF_CHECK_I(has_infoframe);
12763
12764         PIPE_CONF_CHECK_I(has_audio);
12765
12766         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12767                               DRM_MODE_FLAG_INTERLACE);
12768
12769         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12770                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12771                                       DRM_MODE_FLAG_PHSYNC);
12772                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12773                                       DRM_MODE_FLAG_NHSYNC);
12774                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12775                                       DRM_MODE_FLAG_PVSYNC);
12776                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12777                                       DRM_MODE_FLAG_NVSYNC);
12778         }
12779
12780         PIPE_CONF_CHECK_X(gmch_pfit.control);
12781         /* pfit ratios are autocomputed by the hw on gen4+ */
12782         if (INTEL_INFO(dev)->gen < 4)
12783                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12784         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12785
12786         if (!adjust) {
12787                 PIPE_CONF_CHECK_I(pipe_src_w);
12788                 PIPE_CONF_CHECK_I(pipe_src_h);
12789
12790                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12791                 if (current_config->pch_pfit.enabled) {
12792                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12793                         PIPE_CONF_CHECK_X(pch_pfit.size);
12794                 }
12795
12796                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12797         }
12798
12799         /* BDW+ don't expose a synchronous way to read the state */
12800         if (IS_HASWELL(dev))
12801                 PIPE_CONF_CHECK_I(ips_enabled);
12802
12803         PIPE_CONF_CHECK_I(double_wide);
12804
12805         PIPE_CONF_CHECK_X(ddi_pll_sel);
12806
12807         PIPE_CONF_CHECK_I(shared_dpll);
12808         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12809         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12810         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12811         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12812         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12813         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12814         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12815         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12816         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12817
12818         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12819                 PIPE_CONF_CHECK_I(pipe_bpp);
12820
12821         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12822         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12823
12824 #undef PIPE_CONF_CHECK_X
12825 #undef PIPE_CONF_CHECK_I
12826 #undef PIPE_CONF_CHECK_I_ALT
12827 #undef PIPE_CONF_CHECK_FLAGS
12828 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12829 #undef PIPE_CONF_QUIRK
12830 #undef INTEL_ERR_OR_DBG_KMS
12831
12832         return ret;
12833 }
12834
12835 static void check_wm_state(struct drm_device *dev)
12836 {
12837         struct drm_i915_private *dev_priv = dev->dev_private;
12838         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12839         struct intel_crtc *intel_crtc;
12840         int plane;
12841
12842         if (INTEL_INFO(dev)->gen < 9)
12843                 return;
12844
12845         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12846         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12847
12848         for_each_intel_crtc(dev, intel_crtc) {
12849                 struct skl_ddb_entry *hw_entry, *sw_entry;
12850                 const enum pipe pipe = intel_crtc->pipe;
12851
12852                 if (!intel_crtc->active)
12853                         continue;
12854
12855                 /* planes */
12856                 for_each_plane(dev_priv, pipe, plane) {
12857                         hw_entry = &hw_ddb.plane[pipe][plane];
12858                         sw_entry = &sw_ddb->plane[pipe][plane];
12859
12860                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12861                                 continue;
12862
12863                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12864                                   "(expected (%u,%u), found (%u,%u))\n",
12865                                   pipe_name(pipe), plane + 1,
12866                                   sw_entry->start, sw_entry->end,
12867                                   hw_entry->start, hw_entry->end);
12868                 }
12869
12870                 /* cursor */
12871                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12872                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12873
12874                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12875                         continue;
12876
12877                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12878                           "(expected (%u,%u), found (%u,%u))\n",
12879                           pipe_name(pipe),
12880                           sw_entry->start, sw_entry->end,
12881                           hw_entry->start, hw_entry->end);
12882         }
12883 }
12884
12885 static void
12886 check_connector_state(struct drm_device *dev,
12887                       struct drm_atomic_state *old_state)
12888 {
12889         struct drm_connector_state *old_conn_state;
12890         struct drm_connector *connector;
12891         int i;
12892
12893         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12894                 struct drm_encoder *encoder = connector->encoder;
12895                 struct drm_connector_state *state = connector->state;
12896
12897                 /* This also checks the encoder/connector hw state with the
12898                  * ->get_hw_state callbacks. */
12899                 intel_connector_check_state(to_intel_connector(connector));
12900
12901                 I915_STATE_WARN(state->best_encoder != encoder,
12902                      "connector's atomic encoder doesn't match legacy encoder\n");
12903         }
12904 }
12905
12906 static void
12907 check_encoder_state(struct drm_device *dev)
12908 {
12909         struct intel_encoder *encoder;
12910         struct intel_connector *connector;
12911
12912         for_each_intel_encoder(dev, encoder) {
12913                 bool enabled = false;
12914                 enum pipe pipe;
12915
12916                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12917                               encoder->base.base.id,
12918                               encoder->base.name);
12919
12920                 for_each_intel_connector(dev, connector) {
12921                         if (connector->base.state->best_encoder != &encoder->base)
12922                                 continue;
12923                         enabled = true;
12924
12925                         I915_STATE_WARN(connector->base.state->crtc !=
12926                                         encoder->base.crtc,
12927                              "connector's crtc doesn't match encoder crtc\n");
12928                 }
12929
12930                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12931                      "encoder's enabled state mismatch "
12932                      "(expected %i, found %i)\n",
12933                      !!encoder->base.crtc, enabled);
12934
12935                 if (!encoder->base.crtc) {
12936                         bool active;
12937
12938                         active = encoder->get_hw_state(encoder, &pipe);
12939                         I915_STATE_WARN(active,
12940                              "encoder detached but still enabled on pipe %c.\n",
12941                              pipe_name(pipe));
12942                 }
12943         }
12944 }
12945
12946 static void
12947 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12948 {
12949         struct drm_i915_private *dev_priv = dev->dev_private;
12950         struct intel_encoder *encoder;
12951         struct drm_crtc_state *old_crtc_state;
12952         struct drm_crtc *crtc;
12953         int i;
12954
12955         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12956                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12957                 struct intel_crtc_state *pipe_config, *sw_config;
12958                 bool active;
12959
12960                 if (!needs_modeset(crtc->state) &&
12961                     !to_intel_crtc_state(crtc->state)->update_pipe)
12962                         continue;
12963
12964                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12965                 pipe_config = to_intel_crtc_state(old_crtc_state);
12966                 memset(pipe_config, 0, sizeof(*pipe_config));
12967                 pipe_config->base.crtc = crtc;
12968                 pipe_config->base.state = old_state;
12969
12970                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12971                               crtc->base.id);
12972
12973                 active = dev_priv->display.get_pipe_config(intel_crtc,
12974                                                            pipe_config);
12975
12976                 /* hw state is inconsistent with the pipe quirk */
12977                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12978                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12979                         active = crtc->state->active;
12980
12981                 I915_STATE_WARN(crtc->state->active != active,
12982                      "crtc active state doesn't match with hw state "
12983                      "(expected %i, found %i)\n", crtc->state->active, active);
12984
12985                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12986                      "transitional active state does not match atomic hw state "
12987                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12988
12989                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12990                         enum pipe pipe;
12991
12992                         active = encoder->get_hw_state(encoder, &pipe);
12993                         I915_STATE_WARN(active != crtc->state->active,
12994                                 "[ENCODER:%i] active %i with crtc active %i\n",
12995                                 encoder->base.base.id, active, crtc->state->active);
12996
12997                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12998                                         "Encoder connected to wrong pipe %c\n",
12999                                         pipe_name(pipe));
13000
13001                         if (active)
13002                                 encoder->get_config(encoder, pipe_config);
13003                 }
13004
13005                 if (!crtc->state->active)
13006                         continue;
13007
13008                 sw_config = to_intel_crtc_state(crtc->state);
13009                 if (!intel_pipe_config_compare(dev, sw_config,
13010                                                pipe_config, false)) {
13011                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
13012                         intel_dump_pipe_config(intel_crtc, pipe_config,
13013                                                "[hw state]");
13014                         intel_dump_pipe_config(intel_crtc, sw_config,
13015                                                "[sw state]");
13016                 }
13017         }
13018 }
13019
13020 static void
13021 check_shared_dpll_state(struct drm_device *dev)
13022 {
13023         struct drm_i915_private *dev_priv = dev->dev_private;
13024         struct intel_crtc *crtc;
13025         struct intel_dpll_hw_state dpll_hw_state;
13026         int i;
13027
13028         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13029                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13030                 int enabled_crtcs = 0, active_crtcs = 0;
13031                 bool active;
13032
13033                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13034
13035                 DRM_DEBUG_KMS("%s\n", pll->name);
13036
13037                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
13038
13039                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
13040                      "more active pll users than references: %i vs %i\n",
13041                      pll->active, hweight32(pll->config.crtc_mask));
13042                 I915_STATE_WARN(pll->active && !pll->on,
13043                      "pll in active use but not on in sw tracking\n");
13044                 I915_STATE_WARN(pll->on && !pll->active,
13045                      "pll in on but not on in use in sw tracking\n");
13046                 I915_STATE_WARN(pll->on != active,
13047                      "pll on state mismatch (expected %i, found %i)\n",
13048                      pll->on, active);
13049
13050                 for_each_intel_crtc(dev, crtc) {
13051                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
13052                                 enabled_crtcs++;
13053                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13054                                 active_crtcs++;
13055                 }
13056                 I915_STATE_WARN(pll->active != active_crtcs,
13057                      "pll active crtcs mismatch (expected %i, found %i)\n",
13058                      pll->active, active_crtcs);
13059                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
13060                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
13061                      hweight32(pll->config.crtc_mask), enabled_crtcs);
13062
13063                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
13064                                        sizeof(dpll_hw_state)),
13065                      "pll hw state mismatch\n");
13066         }
13067 }
13068
13069 static void
13070 intel_modeset_check_state(struct drm_device *dev,
13071                           struct drm_atomic_state *old_state)
13072 {
13073         check_wm_state(dev);
13074         check_connector_state(dev, old_state);
13075         check_encoder_state(dev);
13076         check_crtc_state(dev, old_state);
13077         check_shared_dpll_state(dev);
13078 }
13079
13080 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13081                                      int dotclock)
13082 {
13083         /*
13084          * FDI already provided one idea for the dotclock.
13085          * Yell if the encoder disagrees.
13086          */
13087         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13088              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13089              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13090 }
13091
13092 static void update_scanline_offset(struct intel_crtc *crtc)
13093 {
13094         struct drm_device *dev = crtc->base.dev;
13095
13096         /*
13097          * The scanline counter increments at the leading edge of hsync.
13098          *
13099          * On most platforms it starts counting from vtotal-1 on the
13100          * first active line. That means the scanline counter value is
13101          * always one less than what we would expect. Ie. just after
13102          * start of vblank, which also occurs at start of hsync (on the
13103          * last active line), the scanline counter will read vblank_start-1.
13104          *
13105          * On gen2 the scanline counter starts counting from 1 instead
13106          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13107          * to keep the value positive), instead of adding one.
13108          *
13109          * On HSW+ the behaviour of the scanline counter depends on the output
13110          * type. For DP ports it behaves like most other platforms, but on HDMI
13111          * there's an extra 1 line difference. So we need to add two instead of
13112          * one to the value.
13113          */
13114         if (IS_GEN2(dev)) {
13115                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13116                 int vtotal;
13117
13118                 vtotal = adjusted_mode->crtc_vtotal;
13119                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13120                         vtotal /= 2;
13121
13122                 crtc->scanline_offset = vtotal - 1;
13123         } else if (HAS_DDI(dev) &&
13124                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13125                 crtc->scanline_offset = 2;
13126         } else
13127                 crtc->scanline_offset = 1;
13128 }
13129
13130 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13131 {
13132         struct drm_device *dev = state->dev;
13133         struct drm_i915_private *dev_priv = to_i915(dev);
13134         struct intel_shared_dpll_config *shared_dpll = NULL;
13135         struct intel_crtc *intel_crtc;
13136         struct intel_crtc_state *intel_crtc_state;
13137         struct drm_crtc *crtc;
13138         struct drm_crtc_state *crtc_state;
13139         int i;
13140
13141         if (!dev_priv->display.crtc_compute_clock)
13142                 return;
13143
13144         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13145                 int dpll;
13146
13147                 intel_crtc = to_intel_crtc(crtc);
13148                 intel_crtc_state = to_intel_crtc_state(crtc_state);
13149                 dpll = intel_crtc_state->shared_dpll;
13150
13151                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13152                         continue;
13153
13154                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13155
13156                 if (!shared_dpll)
13157                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13158
13159                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13160         }
13161 }
13162
13163 /*
13164  * This implements the workaround described in the "notes" section of the mode
13165  * set sequence documentation. When going from no pipes or single pipe to
13166  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13167  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13168  */
13169 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13170 {
13171         struct drm_crtc_state *crtc_state;
13172         struct intel_crtc *intel_crtc;
13173         struct drm_crtc *crtc;
13174         struct intel_crtc_state *first_crtc_state = NULL;
13175         struct intel_crtc_state *other_crtc_state = NULL;
13176         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13177         int i;
13178
13179         /* look at all crtc's that are going to be enabled in during modeset */
13180         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13181                 intel_crtc = to_intel_crtc(crtc);
13182
13183                 if (!crtc_state->active || !needs_modeset(crtc_state))
13184                         continue;
13185
13186                 if (first_crtc_state) {
13187                         other_crtc_state = to_intel_crtc_state(crtc_state);
13188                         break;
13189                 } else {
13190                         first_crtc_state = to_intel_crtc_state(crtc_state);
13191                         first_pipe = intel_crtc->pipe;
13192                 }
13193         }
13194
13195         /* No workaround needed? */
13196         if (!first_crtc_state)
13197                 return 0;
13198
13199         /* w/a possibly needed, check how many crtc's are already enabled. */
13200         for_each_intel_crtc(state->dev, intel_crtc) {
13201                 struct intel_crtc_state *pipe_config;
13202
13203                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13204                 if (IS_ERR(pipe_config))
13205                         return PTR_ERR(pipe_config);
13206
13207                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13208
13209                 if (!pipe_config->base.active ||
13210                     needs_modeset(&pipe_config->base))
13211                         continue;
13212
13213                 /* 2 or more enabled crtcs means no need for w/a */
13214                 if (enabled_pipe != INVALID_PIPE)
13215                         return 0;
13216
13217                 enabled_pipe = intel_crtc->pipe;
13218         }
13219
13220         if (enabled_pipe != INVALID_PIPE)
13221                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13222         else if (other_crtc_state)
13223                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13224
13225         return 0;
13226 }
13227
13228 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13229 {
13230         struct drm_crtc *crtc;
13231         struct drm_crtc_state *crtc_state;
13232         int ret = 0;
13233
13234         /* add all active pipes to the state */
13235         for_each_crtc(state->dev, crtc) {
13236                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13237                 if (IS_ERR(crtc_state))
13238                         return PTR_ERR(crtc_state);
13239
13240                 if (!crtc_state->active || needs_modeset(crtc_state))
13241                         continue;
13242
13243                 crtc_state->mode_changed = true;
13244
13245                 ret = drm_atomic_add_affected_connectors(state, crtc);
13246                 if (ret)
13247                         break;
13248
13249                 ret = drm_atomic_add_affected_planes(state, crtc);
13250                 if (ret)
13251                         break;
13252         }
13253
13254         return ret;
13255 }
13256
13257 static int intel_modeset_checks(struct drm_atomic_state *state)
13258 {
13259         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13260         struct drm_i915_private *dev_priv = state->dev->dev_private;
13261         struct drm_crtc *crtc;
13262         struct drm_crtc_state *crtc_state;
13263         int ret = 0, i;
13264
13265         if (!check_digital_port_conflicts(state)) {
13266                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13267                 return -EINVAL;
13268         }
13269
13270         intel_state->modeset = true;
13271         intel_state->active_crtcs = dev_priv->active_crtcs;
13272
13273         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13274                 if (crtc_state->active)
13275                         intel_state->active_crtcs |= 1 << i;
13276                 else
13277                         intel_state->active_crtcs &= ~(1 << i);
13278         }
13279
13280         /*
13281          * See if the config requires any additional preparation, e.g.
13282          * to adjust global state with pipes off.  We need to do this
13283          * here so we can get the modeset_pipe updated config for the new
13284          * mode set on this crtc.  For other crtcs we need to use the
13285          * adjusted_mode bits in the crtc directly.
13286          */
13287         if (dev_priv->display.modeset_calc_cdclk) {
13288                 ret = dev_priv->display.modeset_calc_cdclk(state);
13289
13290                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13291                         ret = intel_modeset_all_pipes(state);
13292
13293                 if (ret < 0)
13294                         return ret;
13295         } else
13296                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13297
13298         intel_modeset_clear_plls(state);
13299
13300         if (IS_HASWELL(dev_priv))
13301                 return haswell_mode_set_planes_workaround(state);
13302
13303         return 0;
13304 }
13305
13306 /*
13307  * Handle calculation of various watermark data at the end of the atomic check
13308  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13309  * handlers to ensure that all derived state has been updated.
13310  */
13311 static void calc_watermark_data(struct drm_atomic_state *state)
13312 {
13313         struct drm_device *dev = state->dev;
13314         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13315         struct drm_crtc *crtc;
13316         struct drm_crtc_state *cstate;
13317         struct drm_plane *plane;
13318         struct drm_plane_state *pstate;
13319
13320         /*
13321          * Calculate watermark configuration details now that derived
13322          * plane/crtc state is all properly updated.
13323          */
13324         drm_for_each_crtc(crtc, dev) {
13325                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13326                         crtc->state;
13327
13328                 if (cstate->active)
13329                         intel_state->wm_config.num_pipes_active++;
13330         }
13331         drm_for_each_legacy_plane(plane, dev) {
13332                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13333                         plane->state;
13334
13335                 if (!to_intel_plane_state(pstate)->visible)
13336                         continue;
13337
13338                 intel_state->wm_config.sprites_enabled = true;
13339                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13340                     pstate->crtc_h != pstate->src_h >> 16)
13341                         intel_state->wm_config.sprites_scaled = true;
13342         }
13343 }
13344
13345 /**
13346  * intel_atomic_check - validate state object
13347  * @dev: drm device
13348  * @state: state to validate
13349  */
13350 static int intel_atomic_check(struct drm_device *dev,
13351                               struct drm_atomic_state *state)
13352 {
13353         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13354         struct drm_crtc *crtc;
13355         struct drm_crtc_state *crtc_state;
13356         int ret, i;
13357         bool any_ms = false;
13358
13359         ret = drm_atomic_helper_check_modeset(dev, state);
13360         if (ret)
13361                 return ret;
13362
13363         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13364                 struct intel_crtc_state *pipe_config =
13365                         to_intel_crtc_state(crtc_state);
13366
13367                 memset(&to_intel_crtc(crtc)->atomic, 0,
13368                        sizeof(struct intel_crtc_atomic_commit));
13369
13370                 /* Catch I915_MODE_FLAG_INHERITED */
13371                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13372                         crtc_state->mode_changed = true;
13373
13374                 if (!crtc_state->enable) {
13375                         if (needs_modeset(crtc_state))
13376                                 any_ms = true;
13377                         continue;
13378                 }
13379
13380                 if (!needs_modeset(crtc_state))
13381                         continue;
13382
13383                 /* FIXME: For only active_changed we shouldn't need to do any
13384                  * state recomputation at all. */
13385
13386                 ret = drm_atomic_add_affected_connectors(state, crtc);
13387                 if (ret)
13388                         return ret;
13389
13390                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13391                 if (ret)
13392                         return ret;
13393
13394                 if (i915.fastboot &&
13395                     intel_pipe_config_compare(state->dev,
13396                                         to_intel_crtc_state(crtc->state),
13397                                         pipe_config, true)) {
13398                         crtc_state->mode_changed = false;
13399                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13400                 }
13401
13402                 if (needs_modeset(crtc_state)) {
13403                         any_ms = true;
13404
13405                         ret = drm_atomic_add_affected_planes(state, crtc);
13406                         if (ret)
13407                                 return ret;
13408                 }
13409
13410                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13411                                        needs_modeset(crtc_state) ?
13412                                        "[modeset]" : "[fastset]");
13413         }
13414
13415         if (any_ms) {
13416                 ret = intel_modeset_checks(state);
13417
13418                 if (ret)
13419                         return ret;
13420         } else
13421                 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13422
13423         ret = drm_atomic_helper_check_planes(state->dev, state);
13424         if (ret)
13425                 return ret;
13426
13427         calc_watermark_data(state);
13428
13429         return 0;
13430 }
13431
13432 static int intel_atomic_prepare_commit(struct drm_device *dev,
13433                                        struct drm_atomic_state *state,
13434                                        bool async)
13435 {
13436         struct drm_i915_private *dev_priv = dev->dev_private;
13437         struct drm_plane_state *plane_state;
13438         struct drm_crtc_state *crtc_state;
13439         struct drm_plane *plane;
13440         struct drm_crtc *crtc;
13441         int i, ret;
13442
13443         if (async) {
13444                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13445                 return -EINVAL;
13446         }
13447
13448         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13449                 ret = intel_crtc_wait_for_pending_flips(crtc);
13450                 if (ret)
13451                         return ret;
13452
13453                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13454                         flush_workqueue(dev_priv->wq);
13455         }
13456
13457         ret = mutex_lock_interruptible(&dev->struct_mutex);
13458         if (ret)
13459                 return ret;
13460
13461         ret = drm_atomic_helper_prepare_planes(dev, state);
13462         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13463                 u32 reset_counter;
13464
13465                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13466                 mutex_unlock(&dev->struct_mutex);
13467
13468                 for_each_plane_in_state(state, plane, plane_state, i) {
13469                         struct intel_plane_state *intel_plane_state =
13470                                 to_intel_plane_state(plane_state);
13471
13472                         if (!intel_plane_state->wait_req)
13473                                 continue;
13474
13475                         ret = __i915_wait_request(intel_plane_state->wait_req,
13476                                                   reset_counter, true,
13477                                                   NULL, NULL);
13478
13479                         /* Swallow -EIO errors to allow updates during hw lockup. */
13480                         if (ret == -EIO)
13481                                 ret = 0;
13482
13483                         if (ret)
13484                                 break;
13485                 }
13486
13487                 if (!ret)
13488                         return 0;
13489
13490                 mutex_lock(&dev->struct_mutex);
13491                 drm_atomic_helper_cleanup_planes(dev, state);
13492         }
13493
13494         mutex_unlock(&dev->struct_mutex);
13495         return ret;
13496 }
13497
13498 /**
13499  * intel_atomic_commit - commit validated state object
13500  * @dev: DRM device
13501  * @state: the top-level driver state object
13502  * @async: asynchronous commit
13503  *
13504  * This function commits a top-level state object that has been validated
13505  * with drm_atomic_helper_check().
13506  *
13507  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13508  * we can only handle plane-related operations and do not yet support
13509  * asynchronous commit.
13510  *
13511  * RETURNS
13512  * Zero for success or -errno.
13513  */
13514 static int intel_atomic_commit(struct drm_device *dev,
13515                                struct drm_atomic_state *state,
13516                                bool async)
13517 {
13518         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13519         struct drm_i915_private *dev_priv = dev->dev_private;
13520         struct drm_crtc_state *crtc_state;
13521         struct drm_crtc *crtc;
13522         int ret = 0, i;
13523         bool hw_check = intel_state->modeset;
13524
13525         ret = intel_atomic_prepare_commit(dev, state, async);
13526         if (ret) {
13527                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13528                 return ret;
13529         }
13530
13531         drm_atomic_helper_swap_state(dev, state);
13532         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13533
13534         if (intel_state->modeset) {
13535                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13536                        sizeof(intel_state->min_pixclk));
13537                 dev_priv->active_crtcs = intel_state->active_crtcs;
13538                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13539         }
13540
13541         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13542                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13543
13544                 if (!needs_modeset(crtc->state))
13545                         continue;
13546
13547                 intel_pre_plane_update(intel_crtc);
13548
13549                 if (crtc_state->active) {
13550                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13551                         dev_priv->display.crtc_disable(crtc);
13552                         intel_crtc->active = false;
13553                         intel_disable_shared_dpll(intel_crtc);
13554
13555                         /*
13556                          * Underruns don't always raise
13557                          * interrupts, so check manually.
13558                          */
13559                         intel_check_cpu_fifo_underruns(dev_priv);
13560                         intel_check_pch_fifo_underruns(dev_priv);
13561
13562                         if (!crtc->state->active)
13563                                 intel_update_watermarks(crtc);
13564                 }
13565         }
13566
13567         /* Only after disabling all output pipelines that will be changed can we
13568          * update the the output configuration. */
13569         intel_modeset_update_crtc_state(state);
13570
13571         if (intel_state->modeset) {
13572                 intel_shared_dpll_commit(state);
13573
13574                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13575                 modeset_update_crtc_power_domains(state);
13576         }
13577
13578         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13579         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13580                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13581                 bool modeset = needs_modeset(crtc->state);
13582                 bool update_pipe = !modeset &&
13583                         to_intel_crtc_state(crtc->state)->update_pipe;
13584                 unsigned long put_domains = 0;
13585
13586                 if (modeset)
13587                         intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13588
13589                 if (modeset && crtc->state->active) {
13590                         update_scanline_offset(to_intel_crtc(crtc));
13591                         dev_priv->display.crtc_enable(crtc);
13592                 }
13593
13594                 if (update_pipe) {
13595                         put_domains = modeset_get_crtc_power_domains(crtc);
13596
13597                         /* make sure intel_modeset_check_state runs */
13598                         hw_check = true;
13599                 }
13600
13601                 if (!modeset)
13602                         intel_pre_plane_update(intel_crtc);
13603
13604                 if (crtc->state->active &&
13605                     (crtc->state->planes_changed || update_pipe))
13606                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13607
13608                 if (put_domains)
13609                         modeset_put_power_domains(dev_priv, put_domains);
13610
13611                 intel_post_plane_update(intel_crtc);
13612
13613                 if (modeset)
13614                         intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13615         }
13616
13617         /* FIXME: add subpixel order */
13618
13619         drm_atomic_helper_wait_for_vblanks(dev, state);
13620
13621         mutex_lock(&dev->struct_mutex);
13622         drm_atomic_helper_cleanup_planes(dev, state);
13623         mutex_unlock(&dev->struct_mutex);
13624
13625         if (hw_check)
13626                 intel_modeset_check_state(dev, state);
13627
13628         drm_atomic_state_free(state);
13629
13630         /* As one of the primary mmio accessors, KMS has a high likelihood
13631          * of triggering bugs in unclaimed access. After we finish
13632          * modesetting, see if an error has been flagged, and if so
13633          * enable debugging for the next modeset - and hope we catch
13634          * the culprit.
13635          *
13636          * XXX note that we assume display power is on at this point.
13637          * This might hold true now but we need to add pm helper to check
13638          * unclaimed only when the hardware is on, as atomic commits
13639          * can happen also when the device is completely off.
13640          */
13641         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13642
13643         return 0;
13644 }
13645
13646 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13647 {
13648         struct drm_device *dev = crtc->dev;
13649         struct drm_atomic_state *state;
13650         struct drm_crtc_state *crtc_state;
13651         int ret;
13652
13653         state = drm_atomic_state_alloc(dev);
13654         if (!state) {
13655                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13656                               crtc->base.id);
13657                 return;
13658         }
13659
13660         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13661
13662 retry:
13663         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13664         ret = PTR_ERR_OR_ZERO(crtc_state);
13665         if (!ret) {
13666                 if (!crtc_state->active)
13667                         goto out;
13668
13669                 crtc_state->mode_changed = true;
13670                 ret = drm_atomic_commit(state);
13671         }
13672
13673         if (ret == -EDEADLK) {
13674                 drm_atomic_state_clear(state);
13675                 drm_modeset_backoff(state->acquire_ctx);
13676                 goto retry;
13677         }
13678
13679         if (ret)
13680 out:
13681                 drm_atomic_state_free(state);
13682 }
13683
13684 #undef for_each_intel_crtc_masked
13685
13686 static const struct drm_crtc_funcs intel_crtc_funcs = {
13687         .gamma_set = intel_crtc_gamma_set,
13688         .set_config = drm_atomic_helper_set_config,
13689         .destroy = intel_crtc_destroy,
13690         .page_flip = intel_crtc_page_flip,
13691         .atomic_duplicate_state = intel_crtc_duplicate_state,
13692         .atomic_destroy_state = intel_crtc_destroy_state,
13693 };
13694
13695 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13696                                       struct intel_shared_dpll *pll,
13697                                       struct intel_dpll_hw_state *hw_state)
13698 {
13699         uint32_t val;
13700
13701         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13702                 return false;
13703
13704         val = I915_READ(PCH_DPLL(pll->id));
13705         hw_state->dpll = val;
13706         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13707         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13708
13709         return val & DPLL_VCO_ENABLE;
13710 }
13711
13712 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13713                                   struct intel_shared_dpll *pll)
13714 {
13715         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13716         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13717 }
13718
13719 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13720                                 struct intel_shared_dpll *pll)
13721 {
13722         /* PCH refclock must be enabled first */
13723         ibx_assert_pch_refclk_enabled(dev_priv);
13724
13725         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13726
13727         /* Wait for the clocks to stabilize. */
13728         POSTING_READ(PCH_DPLL(pll->id));
13729         udelay(150);
13730
13731         /* The pixel multiplier can only be updated once the
13732          * DPLL is enabled and the clocks are stable.
13733          *
13734          * So write it again.
13735          */
13736         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13737         POSTING_READ(PCH_DPLL(pll->id));
13738         udelay(200);
13739 }
13740
13741 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13742                                  struct intel_shared_dpll *pll)
13743 {
13744         struct drm_device *dev = dev_priv->dev;
13745         struct intel_crtc *crtc;
13746
13747         /* Make sure no transcoder isn't still depending on us. */
13748         for_each_intel_crtc(dev, crtc) {
13749                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13750                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13751         }
13752
13753         I915_WRITE(PCH_DPLL(pll->id), 0);
13754         POSTING_READ(PCH_DPLL(pll->id));
13755         udelay(200);
13756 }
13757
13758 static char *ibx_pch_dpll_names[] = {
13759         "PCH DPLL A",
13760         "PCH DPLL B",
13761 };
13762
13763 static void ibx_pch_dpll_init(struct drm_device *dev)
13764 {
13765         struct drm_i915_private *dev_priv = dev->dev_private;
13766         int i;
13767
13768         dev_priv->num_shared_dpll = 2;
13769
13770         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13771                 dev_priv->shared_dplls[i].id = i;
13772                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13773                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13774                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13775                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13776                 dev_priv->shared_dplls[i].get_hw_state =
13777                         ibx_pch_dpll_get_hw_state;
13778         }
13779 }
13780
13781 static void intel_shared_dpll_init(struct drm_device *dev)
13782 {
13783         struct drm_i915_private *dev_priv = dev->dev_private;
13784
13785         if (HAS_DDI(dev))
13786                 intel_ddi_pll_init(dev);
13787         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13788                 ibx_pch_dpll_init(dev);
13789         else
13790                 dev_priv->num_shared_dpll = 0;
13791
13792         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13793 }
13794
13795 /**
13796  * intel_prepare_plane_fb - Prepare fb for usage on plane
13797  * @plane: drm plane to prepare for
13798  * @fb: framebuffer to prepare for presentation
13799  *
13800  * Prepares a framebuffer for usage on a display plane.  Generally this
13801  * involves pinning the underlying object and updating the frontbuffer tracking
13802  * bits.  Some older platforms need special physical address handling for
13803  * cursor planes.
13804  *
13805  * Must be called with struct_mutex held.
13806  *
13807  * Returns 0 on success, negative error code on failure.
13808  */
13809 int
13810 intel_prepare_plane_fb(struct drm_plane *plane,
13811                        const struct drm_plane_state *new_state)
13812 {
13813         struct drm_device *dev = plane->dev;
13814         struct drm_framebuffer *fb = new_state->fb;
13815         struct intel_plane *intel_plane = to_intel_plane(plane);
13816         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13817         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13818         int ret = 0;
13819
13820         if (!obj && !old_obj)
13821                 return 0;
13822
13823         if (old_obj) {
13824                 struct drm_crtc_state *crtc_state =
13825                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13826
13827                 /* Big Hammer, we also need to ensure that any pending
13828                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13829                  * current scanout is retired before unpinning the old
13830                  * framebuffer. Note that we rely on userspace rendering
13831                  * into the buffer attached to the pipe they are waiting
13832                  * on. If not, userspace generates a GPU hang with IPEHR
13833                  * point to the MI_WAIT_FOR_EVENT.
13834                  *
13835                  * This should only fail upon a hung GPU, in which case we
13836                  * can safely continue.
13837                  */
13838                 if (needs_modeset(crtc_state))
13839                         ret = i915_gem_object_wait_rendering(old_obj, true);
13840
13841                 /* Swallow -EIO errors to allow updates during hw lockup. */
13842                 if (ret && ret != -EIO)
13843                         return ret;
13844         }
13845
13846         /* For framebuffer backed by dmabuf, wait for fence */
13847         if (obj && obj->base.dma_buf) {
13848                 long lret;
13849
13850                 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13851                                                            false, true,
13852                                                            MAX_SCHEDULE_TIMEOUT);
13853                 if (lret == -ERESTARTSYS)
13854                         return lret;
13855
13856                 WARN(lret < 0, "waiting returns %li\n", lret);
13857         }
13858
13859         if (!obj) {
13860                 ret = 0;
13861         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13862             INTEL_INFO(dev)->cursor_needs_physical) {
13863                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13864                 ret = i915_gem_object_attach_phys(obj, align);
13865                 if (ret)
13866                         DRM_DEBUG_KMS("failed to attach phys object\n");
13867         } else {
13868                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13869         }
13870
13871         if (ret == 0) {
13872                 if (obj) {
13873                         struct intel_plane_state *plane_state =
13874                                 to_intel_plane_state(new_state);
13875
13876                         i915_gem_request_assign(&plane_state->wait_req,
13877                                                 obj->last_write_req);
13878                 }
13879
13880                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13881         }
13882
13883         return ret;
13884 }
13885
13886 /**
13887  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13888  * @plane: drm plane to clean up for
13889  * @fb: old framebuffer that was on plane
13890  *
13891  * Cleans up a framebuffer that has just been removed from a plane.
13892  *
13893  * Must be called with struct_mutex held.
13894  */
13895 void
13896 intel_cleanup_plane_fb(struct drm_plane *plane,
13897                        const struct drm_plane_state *old_state)
13898 {
13899         struct drm_device *dev = plane->dev;
13900         struct intel_plane *intel_plane = to_intel_plane(plane);
13901         struct intel_plane_state *old_intel_state;
13902         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13903         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13904
13905         old_intel_state = to_intel_plane_state(old_state);
13906
13907         if (!obj && !old_obj)
13908                 return;
13909
13910         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13911             !INTEL_INFO(dev)->cursor_needs_physical))
13912                 intel_unpin_fb_obj(old_state->fb, old_state);
13913
13914         /* prepare_fb aborted? */
13915         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13916             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13917                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13918
13919         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13920
13921 }
13922
13923 int
13924 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13925 {
13926         int max_scale;
13927         struct drm_device *dev;
13928         struct drm_i915_private *dev_priv;
13929         int crtc_clock, cdclk;
13930
13931         if (!intel_crtc || !crtc_state->base.enable)
13932                 return DRM_PLANE_HELPER_NO_SCALING;
13933
13934         dev = intel_crtc->base.dev;
13935         dev_priv = dev->dev_private;
13936         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13937         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13938
13939         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13940                 return DRM_PLANE_HELPER_NO_SCALING;
13941
13942         /*
13943          * skl max scale is lower of:
13944          *    close to 3 but not 3, -1 is for that purpose
13945          *            or
13946          *    cdclk/crtc_clock
13947          */
13948         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13949
13950         return max_scale;
13951 }
13952
13953 static int
13954 intel_check_primary_plane(struct drm_plane *plane,
13955                           struct intel_crtc_state *crtc_state,
13956                           struct intel_plane_state *state)
13957 {
13958         struct drm_crtc *crtc = state->base.crtc;
13959         struct drm_framebuffer *fb = state->base.fb;
13960         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13961         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13962         bool can_position = false;
13963
13964         if (INTEL_INFO(plane->dev)->gen >= 9) {
13965                 /* use scaler when colorkey is not required */
13966                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13967                         min_scale = 1;
13968                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13969                 }
13970                 can_position = true;
13971         }
13972
13973         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13974                                              &state->dst, &state->clip,
13975                                              min_scale, max_scale,
13976                                              can_position, true,
13977                                              &state->visible);
13978 }
13979
13980 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13981                                     struct drm_crtc_state *old_crtc_state)
13982 {
13983         struct drm_device *dev = crtc->dev;
13984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13985         struct intel_crtc_state *old_intel_state =
13986                 to_intel_crtc_state(old_crtc_state);
13987         bool modeset = needs_modeset(crtc->state);
13988
13989         /* Perform vblank evasion around commit operation */
13990         intel_pipe_update_start(intel_crtc);
13991
13992         if (modeset)
13993                 return;
13994
13995         if (to_intel_crtc_state(crtc->state)->update_pipe)
13996                 intel_update_pipe_config(intel_crtc, old_intel_state);
13997         else if (INTEL_INFO(dev)->gen >= 9)
13998                 skl_detach_scalers(intel_crtc);
13999 }
14000
14001 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14002                                      struct drm_crtc_state *old_crtc_state)
14003 {
14004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14005
14006         intel_pipe_update_end(intel_crtc);
14007 }
14008
14009 /**
14010  * intel_plane_destroy - destroy a plane
14011  * @plane: plane to destroy
14012  *
14013  * Common destruction function for all types of planes (primary, cursor,
14014  * sprite).
14015  */
14016 void intel_plane_destroy(struct drm_plane *plane)
14017 {
14018         struct intel_plane *intel_plane = to_intel_plane(plane);
14019         drm_plane_cleanup(plane);
14020         kfree(intel_plane);
14021 }
14022
14023 const struct drm_plane_funcs intel_plane_funcs = {
14024         .update_plane = drm_atomic_helper_update_plane,
14025         .disable_plane = drm_atomic_helper_disable_plane,
14026         .destroy = intel_plane_destroy,
14027         .set_property = drm_atomic_helper_plane_set_property,
14028         .atomic_get_property = intel_plane_atomic_get_property,
14029         .atomic_set_property = intel_plane_atomic_set_property,
14030         .atomic_duplicate_state = intel_plane_duplicate_state,
14031         .atomic_destroy_state = intel_plane_destroy_state,
14032
14033 };
14034
14035 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14036                                                     int pipe)
14037 {
14038         struct intel_plane *primary;
14039         struct intel_plane_state *state;
14040         const uint32_t *intel_primary_formats;
14041         unsigned int num_formats;
14042
14043         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14044         if (primary == NULL)
14045                 return NULL;
14046
14047         state = intel_create_plane_state(&primary->base);
14048         if (!state) {
14049                 kfree(primary);
14050                 return NULL;
14051         }
14052         primary->base.state = &state->base;
14053
14054         primary->can_scale = false;
14055         primary->max_downscale = 1;
14056         if (INTEL_INFO(dev)->gen >= 9) {
14057                 primary->can_scale = true;
14058                 state->scaler_id = -1;
14059         }
14060         primary->pipe = pipe;
14061         primary->plane = pipe;
14062         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14063         primary->check_plane = intel_check_primary_plane;
14064         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14065                 primary->plane = !pipe;
14066
14067         if (INTEL_INFO(dev)->gen >= 9) {
14068                 intel_primary_formats = skl_primary_formats;
14069                 num_formats = ARRAY_SIZE(skl_primary_formats);
14070
14071                 primary->update_plane = skylake_update_primary_plane;
14072                 primary->disable_plane = skylake_disable_primary_plane;
14073         } else if (HAS_PCH_SPLIT(dev)) {
14074                 intel_primary_formats = i965_primary_formats;
14075                 num_formats = ARRAY_SIZE(i965_primary_formats);
14076
14077                 primary->update_plane = ironlake_update_primary_plane;
14078                 primary->disable_plane = i9xx_disable_primary_plane;
14079         } else if (INTEL_INFO(dev)->gen >= 4) {
14080                 intel_primary_formats = i965_primary_formats;
14081                 num_formats = ARRAY_SIZE(i965_primary_formats);
14082
14083                 primary->update_plane = i9xx_update_primary_plane;
14084                 primary->disable_plane = i9xx_disable_primary_plane;
14085         } else {
14086                 intel_primary_formats = i8xx_primary_formats;
14087                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14088
14089                 primary->update_plane = i9xx_update_primary_plane;
14090                 primary->disable_plane = i9xx_disable_primary_plane;
14091         }
14092
14093         drm_universal_plane_init(dev, &primary->base, 0,
14094                                  &intel_plane_funcs,
14095                                  intel_primary_formats, num_formats,
14096                                  DRM_PLANE_TYPE_PRIMARY, NULL);
14097
14098         if (INTEL_INFO(dev)->gen >= 4)
14099                 intel_create_rotation_property(dev, primary);
14100
14101         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14102
14103         return &primary->base;
14104 }
14105
14106 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14107 {
14108         if (!dev->mode_config.rotation_property) {
14109                 unsigned long flags = BIT(DRM_ROTATE_0) |
14110                         BIT(DRM_ROTATE_180);
14111
14112                 if (INTEL_INFO(dev)->gen >= 9)
14113                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14114
14115                 dev->mode_config.rotation_property =
14116                         drm_mode_create_rotation_property(dev, flags);
14117         }
14118         if (dev->mode_config.rotation_property)
14119                 drm_object_attach_property(&plane->base.base,
14120                                 dev->mode_config.rotation_property,
14121                                 plane->base.state->rotation);
14122 }
14123
14124 static int
14125 intel_check_cursor_plane(struct drm_plane *plane,
14126                          struct intel_crtc_state *crtc_state,
14127                          struct intel_plane_state *state)
14128 {
14129         struct drm_crtc *crtc = crtc_state->base.crtc;
14130         struct drm_framebuffer *fb = state->base.fb;
14131         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14132         enum pipe pipe = to_intel_plane(plane)->pipe;
14133         unsigned stride;
14134         int ret;
14135
14136         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14137                                             &state->dst, &state->clip,
14138                                             DRM_PLANE_HELPER_NO_SCALING,
14139                                             DRM_PLANE_HELPER_NO_SCALING,
14140                                             true, true, &state->visible);
14141         if (ret)
14142                 return ret;
14143
14144         /* if we want to turn off the cursor ignore width and height */
14145         if (!obj)
14146                 return 0;
14147
14148         /* Check for which cursor types we support */
14149         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14150                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14151                           state->base.crtc_w, state->base.crtc_h);
14152                 return -EINVAL;
14153         }
14154
14155         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14156         if (obj->base.size < stride * state->base.crtc_h) {
14157                 DRM_DEBUG_KMS("buffer is too small\n");
14158                 return -ENOMEM;
14159         }
14160
14161         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14162                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14163                 return -EINVAL;
14164         }
14165
14166         /*
14167          * There's something wrong with the cursor on CHV pipe C.
14168          * If it straddles the left edge of the screen then
14169          * moving it away from the edge or disabling it often
14170          * results in a pipe underrun, and often that can lead to
14171          * dead pipe (constant underrun reported, and it scans
14172          * out just a solid color). To recover from that, the
14173          * display power well must be turned off and on again.
14174          * Refuse the put the cursor into that compromised position.
14175          */
14176         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14177             state->visible && state->base.crtc_x < 0) {
14178                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14179                 return -EINVAL;
14180         }
14181
14182         return 0;
14183 }
14184
14185 static void
14186 intel_disable_cursor_plane(struct drm_plane *plane,
14187                            struct drm_crtc *crtc)
14188 {
14189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14190
14191         intel_crtc->cursor_addr = 0;
14192         intel_crtc_update_cursor(crtc, NULL);
14193 }
14194
14195 static void
14196 intel_update_cursor_plane(struct drm_plane *plane,
14197                           const struct intel_crtc_state *crtc_state,
14198                           const struct intel_plane_state *state)
14199 {
14200         struct drm_crtc *crtc = crtc_state->base.crtc;
14201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14202         struct drm_device *dev = plane->dev;
14203         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14204         uint32_t addr;
14205
14206         if (!obj)
14207                 addr = 0;
14208         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14209                 addr = i915_gem_obj_ggtt_offset(obj);
14210         else
14211                 addr = obj->phys_handle->busaddr;
14212
14213         intel_crtc->cursor_addr = addr;
14214         intel_crtc_update_cursor(crtc, state);
14215 }
14216
14217 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14218                                                    int pipe)
14219 {
14220         struct intel_plane *cursor;
14221         struct intel_plane_state *state;
14222
14223         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14224         if (cursor == NULL)
14225                 return NULL;
14226
14227         state = intel_create_plane_state(&cursor->base);
14228         if (!state) {
14229                 kfree(cursor);
14230                 return NULL;
14231         }
14232         cursor->base.state = &state->base;
14233
14234         cursor->can_scale = false;
14235         cursor->max_downscale = 1;
14236         cursor->pipe = pipe;
14237         cursor->plane = pipe;
14238         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14239         cursor->check_plane = intel_check_cursor_plane;
14240         cursor->update_plane = intel_update_cursor_plane;
14241         cursor->disable_plane = intel_disable_cursor_plane;
14242
14243         drm_universal_plane_init(dev, &cursor->base, 0,
14244                                  &intel_plane_funcs,
14245                                  intel_cursor_formats,
14246                                  ARRAY_SIZE(intel_cursor_formats),
14247                                  DRM_PLANE_TYPE_CURSOR, NULL);
14248
14249         if (INTEL_INFO(dev)->gen >= 4) {
14250                 if (!dev->mode_config.rotation_property)
14251                         dev->mode_config.rotation_property =
14252                                 drm_mode_create_rotation_property(dev,
14253                                                         BIT(DRM_ROTATE_0) |
14254                                                         BIT(DRM_ROTATE_180));
14255                 if (dev->mode_config.rotation_property)
14256                         drm_object_attach_property(&cursor->base.base,
14257                                 dev->mode_config.rotation_property,
14258                                 state->base.rotation);
14259         }
14260
14261         if (INTEL_INFO(dev)->gen >=9)
14262                 state->scaler_id = -1;
14263
14264         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14265
14266         return &cursor->base;
14267 }
14268
14269 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14270         struct intel_crtc_state *crtc_state)
14271 {
14272         int i;
14273         struct intel_scaler *intel_scaler;
14274         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14275
14276         for (i = 0; i < intel_crtc->num_scalers; i++) {
14277                 intel_scaler = &scaler_state->scalers[i];
14278                 intel_scaler->in_use = 0;
14279                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14280         }
14281
14282         scaler_state->scaler_id = -1;
14283 }
14284
14285 static void intel_crtc_init(struct drm_device *dev, int pipe)
14286 {
14287         struct drm_i915_private *dev_priv = dev->dev_private;
14288         struct intel_crtc *intel_crtc;
14289         struct intel_crtc_state *crtc_state = NULL;
14290         struct drm_plane *primary = NULL;
14291         struct drm_plane *cursor = NULL;
14292         int i, ret;
14293
14294         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14295         if (intel_crtc == NULL)
14296                 return;
14297
14298         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14299         if (!crtc_state)
14300                 goto fail;
14301         intel_crtc->config = crtc_state;
14302         intel_crtc->base.state = &crtc_state->base;
14303         crtc_state->base.crtc = &intel_crtc->base;
14304
14305         /* initialize shared scalers */
14306         if (INTEL_INFO(dev)->gen >= 9) {
14307                 if (pipe == PIPE_C)
14308                         intel_crtc->num_scalers = 1;
14309                 else
14310                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14311
14312                 skl_init_scalers(dev, intel_crtc, crtc_state);
14313         }
14314
14315         primary = intel_primary_plane_create(dev, pipe);
14316         if (!primary)
14317                 goto fail;
14318
14319         cursor = intel_cursor_plane_create(dev, pipe);
14320         if (!cursor)
14321                 goto fail;
14322
14323         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14324                                         cursor, &intel_crtc_funcs, NULL);
14325         if (ret)
14326                 goto fail;
14327
14328         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14329         for (i = 0; i < 256; i++) {
14330                 intel_crtc->lut_r[i] = i;
14331                 intel_crtc->lut_g[i] = i;
14332                 intel_crtc->lut_b[i] = i;
14333         }
14334
14335         /*
14336          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14337          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14338          */
14339         intel_crtc->pipe = pipe;
14340         intel_crtc->plane = pipe;
14341         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14342                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14343                 intel_crtc->plane = !pipe;
14344         }
14345
14346         intel_crtc->cursor_base = ~0;
14347         intel_crtc->cursor_cntl = ~0;
14348         intel_crtc->cursor_size = ~0;
14349
14350         intel_crtc->wm.cxsr_allowed = true;
14351
14352         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14353                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14354         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14355         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14356
14357         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14358
14359         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14360         return;
14361
14362 fail:
14363         if (primary)
14364                 drm_plane_cleanup(primary);
14365         if (cursor)
14366                 drm_plane_cleanup(cursor);
14367         kfree(crtc_state);
14368         kfree(intel_crtc);
14369 }
14370
14371 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14372 {
14373         struct drm_encoder *encoder = connector->base.encoder;
14374         struct drm_device *dev = connector->base.dev;
14375
14376         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14377
14378         if (!encoder || WARN_ON(!encoder->crtc))
14379                 return INVALID_PIPE;
14380
14381         return to_intel_crtc(encoder->crtc)->pipe;
14382 }
14383
14384 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14385                                 struct drm_file *file)
14386 {
14387         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14388         struct drm_crtc *drmmode_crtc;
14389         struct intel_crtc *crtc;
14390
14391         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14392
14393         if (!drmmode_crtc) {
14394                 DRM_ERROR("no such CRTC id\n");
14395                 return -ENOENT;
14396         }
14397
14398         crtc = to_intel_crtc(drmmode_crtc);
14399         pipe_from_crtc_id->pipe = crtc->pipe;
14400
14401         return 0;
14402 }
14403
14404 static int intel_encoder_clones(struct intel_encoder *encoder)
14405 {
14406         struct drm_device *dev = encoder->base.dev;
14407         struct intel_encoder *source_encoder;
14408         int index_mask = 0;
14409         int entry = 0;
14410
14411         for_each_intel_encoder(dev, source_encoder) {
14412                 if (encoders_cloneable(encoder, source_encoder))
14413                         index_mask |= (1 << entry);
14414
14415                 entry++;
14416         }
14417
14418         return index_mask;
14419 }
14420
14421 static bool has_edp_a(struct drm_device *dev)
14422 {
14423         struct drm_i915_private *dev_priv = dev->dev_private;
14424
14425         if (!IS_MOBILE(dev))
14426                 return false;
14427
14428         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14429                 return false;
14430
14431         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14432                 return false;
14433
14434         return true;
14435 }
14436
14437 static bool intel_crt_present(struct drm_device *dev)
14438 {
14439         struct drm_i915_private *dev_priv = dev->dev_private;
14440
14441         if (INTEL_INFO(dev)->gen >= 9)
14442                 return false;
14443
14444         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14445                 return false;
14446
14447         if (IS_CHERRYVIEW(dev))
14448                 return false;
14449
14450         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14451                 return false;
14452
14453         /* DDI E can't be used if DDI A requires 4 lanes */
14454         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14455                 return false;
14456
14457         if (!dev_priv->vbt.int_crt_support)
14458                 return false;
14459
14460         return true;
14461 }
14462
14463 static void intel_setup_outputs(struct drm_device *dev)
14464 {
14465         struct drm_i915_private *dev_priv = dev->dev_private;
14466         struct intel_encoder *encoder;
14467         bool dpd_is_edp = false;
14468
14469         intel_lvds_init(dev);
14470
14471         if (intel_crt_present(dev))
14472                 intel_crt_init(dev);
14473
14474         if (IS_BROXTON(dev)) {
14475                 /*
14476                  * FIXME: Broxton doesn't support port detection via the
14477                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14478                  * detect the ports.
14479                  */
14480                 intel_ddi_init(dev, PORT_A);
14481                 intel_ddi_init(dev, PORT_B);
14482                 intel_ddi_init(dev, PORT_C);
14483         } else if (HAS_DDI(dev)) {
14484                 int found;
14485
14486                 /*
14487                  * Haswell uses DDI functions to detect digital outputs.
14488                  * On SKL pre-D0 the strap isn't connected, so we assume
14489                  * it's there.
14490                  */
14491                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14492                 /* WaIgnoreDDIAStrap: skl */
14493                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14494                         intel_ddi_init(dev, PORT_A);
14495
14496                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14497                  * register */
14498                 found = I915_READ(SFUSE_STRAP);
14499
14500                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14501                         intel_ddi_init(dev, PORT_B);
14502                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14503                         intel_ddi_init(dev, PORT_C);
14504                 if (found & SFUSE_STRAP_DDID_DETECTED)
14505                         intel_ddi_init(dev, PORT_D);
14506                 /*
14507                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14508                  */
14509                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14510                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14511                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14512                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14513                         intel_ddi_init(dev, PORT_E);
14514
14515         } else if (HAS_PCH_SPLIT(dev)) {
14516                 int found;
14517                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14518
14519                 if (has_edp_a(dev))
14520                         intel_dp_init(dev, DP_A, PORT_A);
14521
14522                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14523                         /* PCH SDVOB multiplex with HDMIB */
14524                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14525                         if (!found)
14526                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14527                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14528                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14529                 }
14530
14531                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14532                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14533
14534                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14535                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14536
14537                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14538                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14539
14540                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14541                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14542         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14543                 /*
14544                  * The DP_DETECTED bit is the latched state of the DDC
14545                  * SDA pin at boot. However since eDP doesn't require DDC
14546                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14547                  * eDP ports may have been muxed to an alternate function.
14548                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14549                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14550                  * detect eDP ports.
14551                  */
14552                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14553                     !intel_dp_is_edp(dev, PORT_B))
14554                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14555                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14556                     intel_dp_is_edp(dev, PORT_B))
14557                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14558
14559                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14560                     !intel_dp_is_edp(dev, PORT_C))
14561                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14562                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14563                     intel_dp_is_edp(dev, PORT_C))
14564                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14565
14566                 if (IS_CHERRYVIEW(dev)) {
14567                         /* eDP not supported on port D, so don't check VBT */
14568                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14569                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14570                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14571                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14572                 }
14573
14574                 intel_dsi_init(dev);
14575         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14576                 bool found = false;
14577
14578                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14579                         DRM_DEBUG_KMS("probing SDVOB\n");
14580                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14581                         if (!found && IS_G4X(dev)) {
14582                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14583                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14584                         }
14585
14586                         if (!found && IS_G4X(dev))
14587                                 intel_dp_init(dev, DP_B, PORT_B);
14588                 }
14589
14590                 /* Before G4X SDVOC doesn't have its own detect register */
14591
14592                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14593                         DRM_DEBUG_KMS("probing SDVOC\n");
14594                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14595                 }
14596
14597                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14598
14599                         if (IS_G4X(dev)) {
14600                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14601                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14602                         }
14603                         if (IS_G4X(dev))
14604                                 intel_dp_init(dev, DP_C, PORT_C);
14605                 }
14606
14607                 if (IS_G4X(dev) &&
14608                     (I915_READ(DP_D) & DP_DETECTED))
14609                         intel_dp_init(dev, DP_D, PORT_D);
14610         } else if (IS_GEN2(dev))
14611                 intel_dvo_init(dev);
14612
14613         if (SUPPORTS_TV(dev))
14614                 intel_tv_init(dev);
14615
14616         intel_psr_init(dev);
14617
14618         for_each_intel_encoder(dev, encoder) {
14619                 encoder->base.possible_crtcs = encoder->crtc_mask;
14620                 encoder->base.possible_clones =
14621                         intel_encoder_clones(encoder);
14622         }
14623
14624         intel_init_pch_refclk(dev);
14625
14626         drm_helper_move_panel_connectors_to_head(dev);
14627 }
14628
14629 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14630 {
14631         struct drm_device *dev = fb->dev;
14632         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14633
14634         drm_framebuffer_cleanup(fb);
14635         mutex_lock(&dev->struct_mutex);
14636         WARN_ON(!intel_fb->obj->framebuffer_references--);
14637         drm_gem_object_unreference(&intel_fb->obj->base);
14638         mutex_unlock(&dev->struct_mutex);
14639         kfree(intel_fb);
14640 }
14641
14642 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14643                                                 struct drm_file *file,
14644                                                 unsigned int *handle)
14645 {
14646         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14647         struct drm_i915_gem_object *obj = intel_fb->obj;
14648
14649         if (obj->userptr.mm) {
14650                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14651                 return -EINVAL;
14652         }
14653
14654         return drm_gem_handle_create(file, &obj->base, handle);
14655 }
14656
14657 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14658                                         struct drm_file *file,
14659                                         unsigned flags, unsigned color,
14660                                         struct drm_clip_rect *clips,
14661                                         unsigned num_clips)
14662 {
14663         struct drm_device *dev = fb->dev;
14664         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14665         struct drm_i915_gem_object *obj = intel_fb->obj;
14666
14667         mutex_lock(&dev->struct_mutex);
14668         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14669         mutex_unlock(&dev->struct_mutex);
14670
14671         return 0;
14672 }
14673
14674 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14675         .destroy = intel_user_framebuffer_destroy,
14676         .create_handle = intel_user_framebuffer_create_handle,
14677         .dirty = intel_user_framebuffer_dirty,
14678 };
14679
14680 static
14681 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14682                          uint32_t pixel_format)
14683 {
14684         u32 gen = INTEL_INFO(dev)->gen;
14685
14686         if (gen >= 9) {
14687                 /* "The stride in bytes must not exceed the of the size of 8K
14688                  *  pixels and 32K bytes."
14689                  */
14690                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14691         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14692                 return 32*1024;
14693         } else if (gen >= 4) {
14694                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14695                         return 16*1024;
14696                 else
14697                         return 32*1024;
14698         } else if (gen >= 3) {
14699                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14700                         return 8*1024;
14701                 else
14702                         return 16*1024;
14703         } else {
14704                 /* XXX DSPC is limited to 4k tiled */
14705                 return 8*1024;
14706         }
14707 }
14708
14709 static int intel_framebuffer_init(struct drm_device *dev,
14710                                   struct intel_framebuffer *intel_fb,
14711                                   struct drm_mode_fb_cmd2 *mode_cmd,
14712                                   struct drm_i915_gem_object *obj)
14713 {
14714         struct drm_i915_private *dev_priv = to_i915(dev);
14715         unsigned int aligned_height;
14716         int ret;
14717         u32 pitch_limit, stride_alignment;
14718
14719         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14720
14721         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14722                 /* Enforce that fb modifier and tiling mode match, but only for
14723                  * X-tiled. This is needed for FBC. */
14724                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14725                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14726                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14727                         return -EINVAL;
14728                 }
14729         } else {
14730                 if (obj->tiling_mode == I915_TILING_X)
14731                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14732                 else if (obj->tiling_mode == I915_TILING_Y) {
14733                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14734                         return -EINVAL;
14735                 }
14736         }
14737
14738         /* Passed in modifier sanity checking. */
14739         switch (mode_cmd->modifier[0]) {
14740         case I915_FORMAT_MOD_Y_TILED:
14741         case I915_FORMAT_MOD_Yf_TILED:
14742                 if (INTEL_INFO(dev)->gen < 9) {
14743                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14744                                   mode_cmd->modifier[0]);
14745                         return -EINVAL;
14746                 }
14747         case DRM_FORMAT_MOD_NONE:
14748         case I915_FORMAT_MOD_X_TILED:
14749                 break;
14750         default:
14751                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14752                           mode_cmd->modifier[0]);
14753                 return -EINVAL;
14754         }
14755
14756         stride_alignment = intel_fb_stride_alignment(dev_priv,
14757                                                      mode_cmd->modifier[0],
14758                                                      mode_cmd->pixel_format);
14759         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14760                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14761                           mode_cmd->pitches[0], stride_alignment);
14762                 return -EINVAL;
14763         }
14764
14765         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14766                                            mode_cmd->pixel_format);
14767         if (mode_cmd->pitches[0] > pitch_limit) {
14768                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14769                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14770                           "tiled" : "linear",
14771                           mode_cmd->pitches[0], pitch_limit);
14772                 return -EINVAL;
14773         }
14774
14775         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14776             mode_cmd->pitches[0] != obj->stride) {
14777                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14778                           mode_cmd->pitches[0], obj->stride);
14779                 return -EINVAL;
14780         }
14781
14782         /* Reject formats not supported by any plane early. */
14783         switch (mode_cmd->pixel_format) {
14784         case DRM_FORMAT_C8:
14785         case DRM_FORMAT_RGB565:
14786         case DRM_FORMAT_XRGB8888:
14787         case DRM_FORMAT_ARGB8888:
14788                 break;
14789         case DRM_FORMAT_XRGB1555:
14790                 if (INTEL_INFO(dev)->gen > 3) {
14791                         DRM_DEBUG("unsupported pixel format: %s\n",
14792                                   drm_get_format_name(mode_cmd->pixel_format));
14793                         return -EINVAL;
14794                 }
14795                 break;
14796         case DRM_FORMAT_ABGR8888:
14797                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14798                     INTEL_INFO(dev)->gen < 9) {
14799                         DRM_DEBUG("unsupported pixel format: %s\n",
14800                                   drm_get_format_name(mode_cmd->pixel_format));
14801                         return -EINVAL;
14802                 }
14803                 break;
14804         case DRM_FORMAT_XBGR8888:
14805         case DRM_FORMAT_XRGB2101010:
14806         case DRM_FORMAT_XBGR2101010:
14807                 if (INTEL_INFO(dev)->gen < 4) {
14808                         DRM_DEBUG("unsupported pixel format: %s\n",
14809                                   drm_get_format_name(mode_cmd->pixel_format));
14810                         return -EINVAL;
14811                 }
14812                 break;
14813         case DRM_FORMAT_ABGR2101010:
14814                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14815                         DRM_DEBUG("unsupported pixel format: %s\n",
14816                                   drm_get_format_name(mode_cmd->pixel_format));
14817                         return -EINVAL;
14818                 }
14819                 break;
14820         case DRM_FORMAT_YUYV:
14821         case DRM_FORMAT_UYVY:
14822         case DRM_FORMAT_YVYU:
14823         case DRM_FORMAT_VYUY:
14824                 if (INTEL_INFO(dev)->gen < 5) {
14825                         DRM_DEBUG("unsupported pixel format: %s\n",
14826                                   drm_get_format_name(mode_cmd->pixel_format));
14827                         return -EINVAL;
14828                 }
14829                 break;
14830         default:
14831                 DRM_DEBUG("unsupported pixel format: %s\n",
14832                           drm_get_format_name(mode_cmd->pixel_format));
14833                 return -EINVAL;
14834         }
14835
14836         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14837         if (mode_cmd->offsets[0] != 0)
14838                 return -EINVAL;
14839
14840         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14841                                                mode_cmd->pixel_format,
14842                                                mode_cmd->modifier[0]);
14843         /* FIXME drm helper for size checks (especially planar formats)? */
14844         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14845                 return -EINVAL;
14846
14847         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14848         intel_fb->obj = obj;
14849
14850         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14851         if (ret) {
14852                 DRM_ERROR("framebuffer init failed %d\n", ret);
14853                 return ret;
14854         }
14855
14856         intel_fb->obj->framebuffer_references++;
14857
14858         return 0;
14859 }
14860
14861 static struct drm_framebuffer *
14862 intel_user_framebuffer_create(struct drm_device *dev,
14863                               struct drm_file *filp,
14864                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14865 {
14866         struct drm_framebuffer *fb;
14867         struct drm_i915_gem_object *obj;
14868         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14869
14870         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14871                                                 mode_cmd.handles[0]));
14872         if (&obj->base == NULL)
14873                 return ERR_PTR(-ENOENT);
14874
14875         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14876         if (IS_ERR(fb))
14877                 drm_gem_object_unreference_unlocked(&obj->base);
14878
14879         return fb;
14880 }
14881
14882 #ifndef CONFIG_DRM_FBDEV_EMULATION
14883 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14884 {
14885 }
14886 #endif
14887
14888 static const struct drm_mode_config_funcs intel_mode_funcs = {
14889         .fb_create = intel_user_framebuffer_create,
14890         .output_poll_changed = intel_fbdev_output_poll_changed,
14891         .atomic_check = intel_atomic_check,
14892         .atomic_commit = intel_atomic_commit,
14893         .atomic_state_alloc = intel_atomic_state_alloc,
14894         .atomic_state_clear = intel_atomic_state_clear,
14895 };
14896
14897 /* Set up chip specific display functions */
14898 static void intel_init_display(struct drm_device *dev)
14899 {
14900         struct drm_i915_private *dev_priv = dev->dev_private;
14901
14902         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14903                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14904         else if (IS_CHERRYVIEW(dev))
14905                 dev_priv->display.find_dpll = chv_find_best_dpll;
14906         else if (IS_VALLEYVIEW(dev))
14907                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14908         else if (IS_PINEVIEW(dev))
14909                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14910         else
14911                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14912
14913         if (INTEL_INFO(dev)->gen >= 9) {
14914                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14915                 dev_priv->display.get_initial_plane_config =
14916                         skylake_get_initial_plane_config;
14917                 dev_priv->display.crtc_compute_clock =
14918                         haswell_crtc_compute_clock;
14919                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14920                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14921         } else if (HAS_DDI(dev)) {
14922                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14923                 dev_priv->display.get_initial_plane_config =
14924                         ironlake_get_initial_plane_config;
14925                 dev_priv->display.crtc_compute_clock =
14926                         haswell_crtc_compute_clock;
14927                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14928                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14929         } else if (HAS_PCH_SPLIT(dev)) {
14930                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14931                 dev_priv->display.get_initial_plane_config =
14932                         ironlake_get_initial_plane_config;
14933                 dev_priv->display.crtc_compute_clock =
14934                         ironlake_crtc_compute_clock;
14935                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14936                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14937         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14938                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14939                 dev_priv->display.get_initial_plane_config =
14940                         i9xx_get_initial_plane_config;
14941                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14942                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14943                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14944         } else {
14945                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14946                 dev_priv->display.get_initial_plane_config =
14947                         i9xx_get_initial_plane_config;
14948                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14949                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14950                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14951         }
14952
14953         /* Returns the core display clock speed */
14954         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14955                 dev_priv->display.get_display_clock_speed =
14956                         skylake_get_display_clock_speed;
14957         else if (IS_BROXTON(dev))
14958                 dev_priv->display.get_display_clock_speed =
14959                         broxton_get_display_clock_speed;
14960         else if (IS_BROADWELL(dev))
14961                 dev_priv->display.get_display_clock_speed =
14962                         broadwell_get_display_clock_speed;
14963         else if (IS_HASWELL(dev))
14964                 dev_priv->display.get_display_clock_speed =
14965                         haswell_get_display_clock_speed;
14966         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14967                 dev_priv->display.get_display_clock_speed =
14968                         valleyview_get_display_clock_speed;
14969         else if (IS_GEN5(dev))
14970                 dev_priv->display.get_display_clock_speed =
14971                         ilk_get_display_clock_speed;
14972         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14973                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14974                 dev_priv->display.get_display_clock_speed =
14975                         i945_get_display_clock_speed;
14976         else if (IS_GM45(dev))
14977                 dev_priv->display.get_display_clock_speed =
14978                         gm45_get_display_clock_speed;
14979         else if (IS_CRESTLINE(dev))
14980                 dev_priv->display.get_display_clock_speed =
14981                         i965gm_get_display_clock_speed;
14982         else if (IS_PINEVIEW(dev))
14983                 dev_priv->display.get_display_clock_speed =
14984                         pnv_get_display_clock_speed;
14985         else if (IS_G33(dev) || IS_G4X(dev))
14986                 dev_priv->display.get_display_clock_speed =
14987                         g33_get_display_clock_speed;
14988         else if (IS_I915G(dev))
14989                 dev_priv->display.get_display_clock_speed =
14990                         i915_get_display_clock_speed;
14991         else if (IS_I945GM(dev) || IS_845G(dev))
14992                 dev_priv->display.get_display_clock_speed =
14993                         i9xx_misc_get_display_clock_speed;
14994         else if (IS_I915GM(dev))
14995                 dev_priv->display.get_display_clock_speed =
14996                         i915gm_get_display_clock_speed;
14997         else if (IS_I865G(dev))
14998                 dev_priv->display.get_display_clock_speed =
14999                         i865_get_display_clock_speed;
15000         else if (IS_I85X(dev))
15001                 dev_priv->display.get_display_clock_speed =
15002                         i85x_get_display_clock_speed;
15003         else { /* 830 */
15004                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
15005                 dev_priv->display.get_display_clock_speed =
15006                         i830_get_display_clock_speed;
15007         }
15008
15009         if (IS_GEN5(dev)) {
15010                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15011         } else if (IS_GEN6(dev)) {
15012                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15013         } else if (IS_IVYBRIDGE(dev)) {
15014                 /* FIXME: detect B0+ stepping and use auto training */
15015                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15016         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
15017                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15018                 if (IS_BROADWELL(dev)) {
15019                         dev_priv->display.modeset_commit_cdclk =
15020                                 broadwell_modeset_commit_cdclk;
15021                         dev_priv->display.modeset_calc_cdclk =
15022                                 broadwell_modeset_calc_cdclk;
15023                 }
15024         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15025                 dev_priv->display.modeset_commit_cdclk =
15026                         valleyview_modeset_commit_cdclk;
15027                 dev_priv->display.modeset_calc_cdclk =
15028                         valleyview_modeset_calc_cdclk;
15029         } else if (IS_BROXTON(dev)) {
15030                 dev_priv->display.modeset_commit_cdclk =
15031                         broxton_modeset_commit_cdclk;
15032                 dev_priv->display.modeset_calc_cdclk =
15033                         broxton_modeset_calc_cdclk;
15034         }
15035
15036         switch (INTEL_INFO(dev)->gen) {
15037         case 2:
15038                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15039                 break;
15040
15041         case 3:
15042                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15043                 break;
15044
15045         case 4:
15046         case 5:
15047                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15048                 break;
15049
15050         case 6:
15051                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15052                 break;
15053         case 7:
15054         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15055                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15056                 break;
15057         case 9:
15058                 /* Drop through - unsupported since execlist only. */
15059         default:
15060                 /* Default just returns -ENODEV to indicate unsupported */
15061                 dev_priv->display.queue_flip = intel_default_queue_flip;
15062         }
15063
15064         mutex_init(&dev_priv->pps_mutex);
15065 }
15066
15067 /*
15068  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15069  * resume, or other times.  This quirk makes sure that's the case for
15070  * affected systems.
15071  */
15072 static void quirk_pipea_force(struct drm_device *dev)
15073 {
15074         struct drm_i915_private *dev_priv = dev->dev_private;
15075
15076         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15077         DRM_INFO("applying pipe a force quirk\n");
15078 }
15079
15080 static void quirk_pipeb_force(struct drm_device *dev)
15081 {
15082         struct drm_i915_private *dev_priv = dev->dev_private;
15083
15084         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15085         DRM_INFO("applying pipe b force quirk\n");
15086 }
15087
15088 /*
15089  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15090  */
15091 static void quirk_ssc_force_disable(struct drm_device *dev)
15092 {
15093         struct drm_i915_private *dev_priv = dev->dev_private;
15094         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15095         DRM_INFO("applying lvds SSC disable quirk\n");
15096 }
15097
15098 /*
15099  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15100  * brightness value
15101  */
15102 static void quirk_invert_brightness(struct drm_device *dev)
15103 {
15104         struct drm_i915_private *dev_priv = dev->dev_private;
15105         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15106         DRM_INFO("applying inverted panel brightness quirk\n");
15107 }
15108
15109 /* Some VBT's incorrectly indicate no backlight is present */
15110 static void quirk_backlight_present(struct drm_device *dev)
15111 {
15112         struct drm_i915_private *dev_priv = dev->dev_private;
15113         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15114         DRM_INFO("applying backlight present quirk\n");
15115 }
15116
15117 struct intel_quirk {
15118         int device;
15119         int subsystem_vendor;
15120         int subsystem_device;
15121         void (*hook)(struct drm_device *dev);
15122 };
15123
15124 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15125 struct intel_dmi_quirk {
15126         void (*hook)(struct drm_device *dev);
15127         const struct dmi_system_id (*dmi_id_list)[];
15128 };
15129
15130 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15131 {
15132         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15133         return 1;
15134 }
15135
15136 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15137         {
15138                 .dmi_id_list = &(const struct dmi_system_id[]) {
15139                         {
15140                                 .callback = intel_dmi_reverse_brightness,
15141                                 .ident = "NCR Corporation",
15142                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15143                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15144                                 },
15145                         },
15146                         { }  /* terminating entry */
15147                 },
15148                 .hook = quirk_invert_brightness,
15149         },
15150 };
15151
15152 static struct intel_quirk intel_quirks[] = {
15153         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15154         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15155
15156         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15157         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15158
15159         /* 830 needs to leave pipe A & dpll A up */
15160         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15161
15162         /* 830 needs to leave pipe B & dpll B up */
15163         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15164
15165         /* Lenovo U160 cannot use SSC on LVDS */
15166         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15167
15168         /* Sony Vaio Y cannot use SSC on LVDS */
15169         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15170
15171         /* Acer Aspire 5734Z must invert backlight brightness */
15172         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15173
15174         /* Acer/eMachines G725 */
15175         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15176
15177         /* Acer/eMachines e725 */
15178         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15179
15180         /* Acer/Packard Bell NCL20 */
15181         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15182
15183         /* Acer Aspire 4736Z */
15184         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15185
15186         /* Acer Aspire 5336 */
15187         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15188
15189         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15190         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15191
15192         /* Acer C720 Chromebook (Core i3 4005U) */
15193         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15194
15195         /* Apple Macbook 2,1 (Core 2 T7400) */
15196         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15197
15198         /* Apple Macbook 4,1 */
15199         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15200
15201         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15202         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15203
15204         /* HP Chromebook 14 (Celeron 2955U) */
15205         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15206
15207         /* Dell Chromebook 11 */
15208         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15209
15210         /* Dell Chromebook 11 (2015 version) */
15211         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15212 };
15213
15214 static void intel_init_quirks(struct drm_device *dev)
15215 {
15216         struct pci_dev *d = dev->pdev;
15217         int i;
15218
15219         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15220                 struct intel_quirk *q = &intel_quirks[i];
15221
15222                 if (d->device == q->device &&
15223                     (d->subsystem_vendor == q->subsystem_vendor ||
15224                      q->subsystem_vendor == PCI_ANY_ID) &&
15225                     (d->subsystem_device == q->subsystem_device ||
15226                      q->subsystem_device == PCI_ANY_ID))
15227                         q->hook(dev);
15228         }
15229         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15230                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15231                         intel_dmi_quirks[i].hook(dev);
15232         }
15233 }
15234
15235 /* Disable the VGA plane that we never use */
15236 static void i915_disable_vga(struct drm_device *dev)
15237 {
15238         struct drm_i915_private *dev_priv = dev->dev_private;
15239         u8 sr1;
15240         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15241
15242         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15243         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15244         outb(SR01, VGA_SR_INDEX);
15245         sr1 = inb(VGA_SR_DATA);
15246         outb(sr1 | 1<<5, VGA_SR_DATA);
15247         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15248         udelay(300);
15249
15250         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15251         POSTING_READ(vga_reg);
15252 }
15253
15254 void intel_modeset_init_hw(struct drm_device *dev)
15255 {
15256         struct drm_i915_private *dev_priv = dev->dev_private;
15257
15258         intel_update_cdclk(dev);
15259
15260         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15261
15262         intel_init_clock_gating(dev);
15263         intel_enable_gt_powersave(dev);
15264 }
15265
15266 /*
15267  * Calculate what we think the watermarks should be for the state we've read
15268  * out of the hardware and then immediately program those watermarks so that
15269  * we ensure the hardware settings match our internal state.
15270  *
15271  * We can calculate what we think WM's should be by creating a duplicate of the
15272  * current state (which was constructed during hardware readout) and running it
15273  * through the atomic check code to calculate new watermark values in the
15274  * state object.
15275  */
15276 static void sanitize_watermarks(struct drm_device *dev)
15277 {
15278         struct drm_i915_private *dev_priv = to_i915(dev);
15279         struct drm_atomic_state *state;
15280         struct drm_crtc *crtc;
15281         struct drm_crtc_state *cstate;
15282         struct drm_modeset_acquire_ctx ctx;
15283         int ret;
15284         int i;
15285
15286         /* Only supported on platforms that use atomic watermark design */
15287         if (!dev_priv->display.program_watermarks)
15288                 return;
15289
15290         /*
15291          * We need to hold connection_mutex before calling duplicate_state so
15292          * that the connector loop is protected.
15293          */
15294         drm_modeset_acquire_init(&ctx, 0);
15295 retry:
15296         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15297         if (ret == -EDEADLK) {
15298                 drm_modeset_backoff(&ctx);
15299                 goto retry;
15300         } else if (WARN_ON(ret)) {
15301                 goto fail;
15302         }
15303
15304         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15305         if (WARN_ON(IS_ERR(state)))
15306                 goto fail;
15307
15308         ret = intel_atomic_check(dev, state);
15309         if (ret) {
15310                 /*
15311                  * If we fail here, it means that the hardware appears to be
15312                  * programmed in a way that shouldn't be possible, given our
15313                  * understanding of watermark requirements.  This might mean a
15314                  * mistake in the hardware readout code or a mistake in the
15315                  * watermark calculations for a given platform.  Raise a WARN
15316                  * so that this is noticeable.
15317                  *
15318                  * If this actually happens, we'll have to just leave the
15319                  * BIOS-programmed watermarks untouched and hope for the best.
15320                  */
15321                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15322                 goto fail;
15323         }
15324
15325         /* Write calculated watermark values back */
15326         to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15327         for_each_crtc_in_state(state, crtc, cstate, i) {
15328                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15329
15330                 dev_priv->display.program_watermarks(cs);
15331         }
15332
15333         drm_atomic_state_free(state);
15334 fail:
15335         drm_modeset_drop_locks(&ctx);
15336         drm_modeset_acquire_fini(&ctx);
15337 }
15338
15339 void intel_modeset_init(struct drm_device *dev)
15340 {
15341         struct drm_i915_private *dev_priv = dev->dev_private;
15342         int sprite, ret;
15343         enum pipe pipe;
15344         struct intel_crtc *crtc;
15345
15346         drm_mode_config_init(dev);
15347
15348         dev->mode_config.min_width = 0;
15349         dev->mode_config.min_height = 0;
15350
15351         dev->mode_config.preferred_depth = 24;
15352         dev->mode_config.prefer_shadow = 1;
15353
15354         dev->mode_config.allow_fb_modifiers = true;
15355
15356         dev->mode_config.funcs = &intel_mode_funcs;
15357
15358         intel_init_quirks(dev);
15359
15360         intel_init_pm(dev);
15361
15362         if (INTEL_INFO(dev)->num_pipes == 0)
15363                 return;
15364
15365         /*
15366          * There may be no VBT; and if the BIOS enabled SSC we can
15367          * just keep using it to avoid unnecessary flicker.  Whereas if the
15368          * BIOS isn't using it, don't assume it will work even if the VBT
15369          * indicates as much.
15370          */
15371         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15372                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15373                                             DREF_SSC1_ENABLE);
15374
15375                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15376                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15377                                      bios_lvds_use_ssc ? "en" : "dis",
15378                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15379                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15380                 }
15381         }
15382
15383         intel_init_display(dev);
15384         intel_init_audio(dev);
15385
15386         if (IS_GEN2(dev)) {
15387                 dev->mode_config.max_width = 2048;
15388                 dev->mode_config.max_height = 2048;
15389         } else if (IS_GEN3(dev)) {
15390                 dev->mode_config.max_width = 4096;
15391                 dev->mode_config.max_height = 4096;
15392         } else {
15393                 dev->mode_config.max_width = 8192;
15394                 dev->mode_config.max_height = 8192;
15395         }
15396
15397         if (IS_845G(dev) || IS_I865G(dev)) {
15398                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15399                 dev->mode_config.cursor_height = 1023;
15400         } else if (IS_GEN2(dev)) {
15401                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15402                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15403         } else {
15404                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15405                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15406         }
15407
15408         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15409
15410         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15411                       INTEL_INFO(dev)->num_pipes,
15412                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15413
15414         for_each_pipe(dev_priv, pipe) {
15415                 intel_crtc_init(dev, pipe);
15416                 for_each_sprite(dev_priv, pipe, sprite) {
15417                         ret = intel_plane_init(dev, pipe, sprite);
15418                         if (ret)
15419                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15420                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15421                 }
15422         }
15423
15424         intel_update_czclk(dev_priv);
15425         intel_update_cdclk(dev);
15426
15427         intel_shared_dpll_init(dev);
15428
15429         /* Just disable it once at startup */
15430         i915_disable_vga(dev);
15431         intel_setup_outputs(dev);
15432
15433         drm_modeset_lock_all(dev);
15434         intel_modeset_setup_hw_state(dev);
15435         drm_modeset_unlock_all(dev);
15436
15437         for_each_intel_crtc(dev, crtc) {
15438                 struct intel_initial_plane_config plane_config = {};
15439
15440                 if (!crtc->active)
15441                         continue;
15442
15443                 /*
15444                  * Note that reserving the BIOS fb up front prevents us
15445                  * from stuffing other stolen allocations like the ring
15446                  * on top.  This prevents some ugliness at boot time, and
15447                  * can even allow for smooth boot transitions if the BIOS
15448                  * fb is large enough for the active pipe configuration.
15449                  */
15450                 dev_priv->display.get_initial_plane_config(crtc,
15451                                                            &plane_config);
15452
15453                 /*
15454                  * If the fb is shared between multiple heads, we'll
15455                  * just get the first one.
15456                  */
15457                 intel_find_initial_plane_obj(crtc, &plane_config);
15458         }
15459
15460         /*
15461          * Make sure hardware watermarks really match the state we read out.
15462          * Note that we need to do this after reconstructing the BIOS fb's
15463          * since the watermark calculation done here will use pstate->fb.
15464          */
15465         sanitize_watermarks(dev);
15466 }
15467
15468 static void intel_enable_pipe_a(struct drm_device *dev)
15469 {
15470         struct intel_connector *connector;
15471         struct drm_connector *crt = NULL;
15472         struct intel_load_detect_pipe load_detect_temp;
15473         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15474
15475         /* We can't just switch on the pipe A, we need to set things up with a
15476          * proper mode and output configuration. As a gross hack, enable pipe A
15477          * by enabling the load detect pipe once. */
15478         for_each_intel_connector(dev, connector) {
15479                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15480                         crt = &connector->base;
15481                         break;
15482                 }
15483         }
15484
15485         if (!crt)
15486                 return;
15487
15488         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15489                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15490 }
15491
15492 static bool
15493 intel_check_plane_mapping(struct intel_crtc *crtc)
15494 {
15495         struct drm_device *dev = crtc->base.dev;
15496         struct drm_i915_private *dev_priv = dev->dev_private;
15497         u32 val;
15498
15499         if (INTEL_INFO(dev)->num_pipes == 1)
15500                 return true;
15501
15502         val = I915_READ(DSPCNTR(!crtc->plane));
15503
15504         if ((val & DISPLAY_PLANE_ENABLE) &&
15505             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15506                 return false;
15507
15508         return true;
15509 }
15510
15511 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15512 {
15513         struct drm_device *dev = crtc->base.dev;
15514         struct intel_encoder *encoder;
15515
15516         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15517                 return true;
15518
15519         return false;
15520 }
15521
15522 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15523 {
15524         struct drm_device *dev = crtc->base.dev;
15525         struct drm_i915_private *dev_priv = dev->dev_private;
15526         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15527
15528         /* Clear any frame start delays used for debugging left by the BIOS */
15529         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15530
15531         /* restore vblank interrupts to correct state */
15532         drm_crtc_vblank_reset(&crtc->base);
15533         if (crtc->active) {
15534                 struct intel_plane *plane;
15535
15536                 drm_crtc_vblank_on(&crtc->base);
15537
15538                 /* Disable everything but the primary plane */
15539                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15540                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15541                                 continue;
15542
15543                         plane->disable_plane(&plane->base, &crtc->base);
15544                 }
15545         }
15546
15547         /* We need to sanitize the plane -> pipe mapping first because this will
15548          * disable the crtc (and hence change the state) if it is wrong. Note
15549          * that gen4+ has a fixed plane -> pipe mapping.  */
15550         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15551                 bool plane;
15552
15553                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15554                               crtc->base.base.id);
15555
15556                 /* Pipe has the wrong plane attached and the plane is active.
15557                  * Temporarily change the plane mapping and disable everything
15558                  * ...  */
15559                 plane = crtc->plane;
15560                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15561                 crtc->plane = !plane;
15562                 intel_crtc_disable_noatomic(&crtc->base);
15563                 crtc->plane = plane;
15564         }
15565
15566         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15567             crtc->pipe == PIPE_A && !crtc->active) {
15568                 /* BIOS forgot to enable pipe A, this mostly happens after
15569                  * resume. Force-enable the pipe to fix this, the update_dpms
15570                  * call below we restore the pipe to the right state, but leave
15571                  * the required bits on. */
15572                 intel_enable_pipe_a(dev);
15573         }
15574
15575         /* Adjust the state of the output pipe according to whether we
15576          * have active connectors/encoders. */
15577         if (!intel_crtc_has_encoders(crtc))
15578                 intel_crtc_disable_noatomic(&crtc->base);
15579
15580         if (crtc->active != crtc->base.state->active) {
15581                 struct intel_encoder *encoder;
15582
15583                 /* This can happen either due to bugs in the get_hw_state
15584                  * functions or because of calls to intel_crtc_disable_noatomic,
15585                  * or because the pipe is force-enabled due to the
15586                  * pipe A quirk. */
15587                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15588                               crtc->base.base.id,
15589                               crtc->base.state->enable ? "enabled" : "disabled",
15590                               crtc->active ? "enabled" : "disabled");
15591
15592                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15593                 crtc->base.state->active = crtc->active;
15594                 crtc->base.enabled = crtc->active;
15595                 crtc->base.state->connector_mask = 0;
15596
15597                 /* Because we only establish the connector -> encoder ->
15598                  * crtc links if something is active, this means the
15599                  * crtc is now deactivated. Break the links. connector
15600                  * -> encoder links are only establish when things are
15601                  *  actually up, hence no need to break them. */
15602                 WARN_ON(crtc->active);
15603
15604                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15605                         encoder->base.crtc = NULL;
15606         }
15607
15608         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15609                 /*
15610                  * We start out with underrun reporting disabled to avoid races.
15611                  * For correct bookkeeping mark this on active crtcs.
15612                  *
15613                  * Also on gmch platforms we dont have any hardware bits to
15614                  * disable the underrun reporting. Which means we need to start
15615                  * out with underrun reporting disabled also on inactive pipes,
15616                  * since otherwise we'll complain about the garbage we read when
15617                  * e.g. coming up after runtime pm.
15618                  *
15619                  * No protection against concurrent access is required - at
15620                  * worst a fifo underrun happens which also sets this to false.
15621                  */
15622                 crtc->cpu_fifo_underrun_disabled = true;
15623                 crtc->pch_fifo_underrun_disabled = true;
15624         }
15625 }
15626
15627 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15628 {
15629         struct intel_connector *connector;
15630         struct drm_device *dev = encoder->base.dev;
15631         bool active = false;
15632
15633         /* We need to check both for a crtc link (meaning that the
15634          * encoder is active and trying to read from a pipe) and the
15635          * pipe itself being active. */
15636         bool has_active_crtc = encoder->base.crtc &&
15637                 to_intel_crtc(encoder->base.crtc)->active;
15638
15639         for_each_intel_connector(dev, connector) {
15640                 if (connector->base.encoder != &encoder->base)
15641                         continue;
15642
15643                 active = true;
15644                 break;
15645         }
15646
15647         if (active && !has_active_crtc) {
15648                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15649                               encoder->base.base.id,
15650                               encoder->base.name);
15651
15652                 /* Connector is active, but has no active pipe. This is
15653                  * fallout from our resume register restoring. Disable
15654                  * the encoder manually again. */
15655                 if (encoder->base.crtc) {
15656                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15657                                       encoder->base.base.id,
15658                                       encoder->base.name);
15659                         encoder->disable(encoder);
15660                         if (encoder->post_disable)
15661                                 encoder->post_disable(encoder);
15662                 }
15663                 encoder->base.crtc = NULL;
15664
15665                 /* Inconsistent output/port/pipe state happens presumably due to
15666                  * a bug in one of the get_hw_state functions. Or someplace else
15667                  * in our code, like the register restore mess on resume. Clamp
15668                  * things to off as a safer default. */
15669                 for_each_intel_connector(dev, connector) {
15670                         if (connector->encoder != encoder)
15671                                 continue;
15672                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15673                         connector->base.encoder = NULL;
15674                 }
15675         }
15676         /* Enabled encoders without active connectors will be fixed in
15677          * the crtc fixup. */
15678 }
15679
15680 void i915_redisable_vga_power_on(struct drm_device *dev)
15681 {
15682         struct drm_i915_private *dev_priv = dev->dev_private;
15683         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15684
15685         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15686                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15687                 i915_disable_vga(dev);
15688         }
15689 }
15690
15691 void i915_redisable_vga(struct drm_device *dev)
15692 {
15693         struct drm_i915_private *dev_priv = dev->dev_private;
15694
15695         /* This function can be called both from intel_modeset_setup_hw_state or
15696          * at a very early point in our resume sequence, where the power well
15697          * structures are not yet restored. Since this function is at a very
15698          * paranoid "someone might have enabled VGA while we were not looking"
15699          * level, just check if the power well is enabled instead of trying to
15700          * follow the "don't touch the power well if we don't need it" policy
15701          * the rest of the driver uses. */
15702         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15703                 return;
15704
15705         i915_redisable_vga_power_on(dev);
15706 }
15707
15708 static bool primary_get_hw_state(struct intel_plane *plane)
15709 {
15710         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15711
15712         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15713 }
15714
15715 /* FIXME read out full plane state for all planes */
15716 static void readout_plane_state(struct intel_crtc *crtc)
15717 {
15718         struct drm_plane *primary = crtc->base.primary;
15719         struct intel_plane_state *plane_state =
15720                 to_intel_plane_state(primary->state);
15721
15722         plane_state->visible = crtc->active &&
15723                 primary_get_hw_state(to_intel_plane(primary));
15724
15725         if (plane_state->visible)
15726                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15727 }
15728
15729 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15730 {
15731         struct drm_i915_private *dev_priv = dev->dev_private;
15732         enum pipe pipe;
15733         struct intel_crtc *crtc;
15734         struct intel_encoder *encoder;
15735         struct intel_connector *connector;
15736         int i;
15737
15738         dev_priv->active_crtcs = 0;
15739
15740         for_each_intel_crtc(dev, crtc) {
15741                 struct intel_crtc_state *crtc_state = crtc->config;
15742                 int pixclk = 0;
15743
15744                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15745                 memset(crtc_state, 0, sizeof(*crtc_state));
15746                 crtc_state->base.crtc = &crtc->base;
15747
15748                 crtc_state->base.active = crtc_state->base.enable =
15749                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15750
15751                 crtc->base.enabled = crtc_state->base.enable;
15752                 crtc->active = crtc_state->base.active;
15753
15754                 if (crtc_state->base.active) {
15755                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15756
15757                         if (IS_BROADWELL(dev_priv)) {
15758                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15759
15760                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15761                                 if (crtc_state->ips_enabled)
15762                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15763                         } else if (IS_VALLEYVIEW(dev_priv) ||
15764                                    IS_CHERRYVIEW(dev_priv) ||
15765                                    IS_BROXTON(dev_priv))
15766                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15767                         else
15768                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15769                 }
15770
15771                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15772
15773                 readout_plane_state(crtc);
15774
15775                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15776                               crtc->base.base.id,
15777                               crtc->active ? "enabled" : "disabled");
15778         }
15779
15780         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15781                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15782
15783                 pll->on = pll->get_hw_state(dev_priv, pll,
15784                                             &pll->config.hw_state);
15785                 pll->active = 0;
15786                 pll->config.crtc_mask = 0;
15787                 for_each_intel_crtc(dev, crtc) {
15788                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15789                                 pll->active++;
15790                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15791                         }
15792                 }
15793
15794                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15795                               pll->name, pll->config.crtc_mask, pll->on);
15796
15797                 if (pll->config.crtc_mask)
15798                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15799         }
15800
15801         for_each_intel_encoder(dev, encoder) {
15802                 pipe = 0;
15803
15804                 if (encoder->get_hw_state(encoder, &pipe)) {
15805                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15806                         encoder->base.crtc = &crtc->base;
15807                         encoder->get_config(encoder, crtc->config);
15808                 } else {
15809                         encoder->base.crtc = NULL;
15810                 }
15811
15812                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15813                               encoder->base.base.id,
15814                               encoder->base.name,
15815                               encoder->base.crtc ? "enabled" : "disabled",
15816                               pipe_name(pipe));
15817         }
15818
15819         for_each_intel_connector(dev, connector) {
15820                 if (connector->get_hw_state(connector)) {
15821                         connector->base.dpms = DRM_MODE_DPMS_ON;
15822
15823                         encoder = connector->encoder;
15824                         connector->base.encoder = &encoder->base;
15825
15826                         if (encoder->base.crtc &&
15827                             encoder->base.crtc->state->active) {
15828                                 /*
15829                                  * This has to be done during hardware readout
15830                                  * because anything calling .crtc_disable may
15831                                  * rely on the connector_mask being accurate.
15832                                  */
15833                                 encoder->base.crtc->state->connector_mask |=
15834                                         1 << drm_connector_index(&connector->base);
15835                         }
15836
15837                 } else {
15838                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15839                         connector->base.encoder = NULL;
15840                 }
15841                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15842                               connector->base.base.id,
15843                               connector->base.name,
15844                               connector->base.encoder ? "enabled" : "disabled");
15845         }
15846
15847         for_each_intel_crtc(dev, crtc) {
15848                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15849
15850                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15851                 if (crtc->base.state->active) {
15852                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15853                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15854                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15855
15856                         /*
15857                          * The initial mode needs to be set in order to keep
15858                          * the atomic core happy. It wants a valid mode if the
15859                          * crtc's enabled, so we do the above call.
15860                          *
15861                          * At this point some state updated by the connectors
15862                          * in their ->detect() callback has not run yet, so
15863                          * no recalculation can be done yet.
15864                          *
15865                          * Even if we could do a recalculation and modeset
15866                          * right now it would cause a double modeset if
15867                          * fbdev or userspace chooses a different initial mode.
15868                          *
15869                          * If that happens, someone indicated they wanted a
15870                          * mode change, which means it's safe to do a full
15871                          * recalculation.
15872                          */
15873                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15874
15875                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15876                         update_scanline_offset(crtc);
15877                 }
15878         }
15879 }
15880
15881 /* Scan out the current hw modeset state,
15882  * and sanitizes it to the current state
15883  */
15884 static void
15885 intel_modeset_setup_hw_state(struct drm_device *dev)
15886 {
15887         struct drm_i915_private *dev_priv = dev->dev_private;
15888         enum pipe pipe;
15889         struct intel_crtc *crtc;
15890         struct intel_encoder *encoder;
15891         int i;
15892
15893         intel_modeset_readout_hw_state(dev);
15894
15895         /* HW state is read out, now we need to sanitize this mess. */
15896         for_each_intel_encoder(dev, encoder) {
15897                 intel_sanitize_encoder(encoder);
15898         }
15899
15900         for_each_pipe(dev_priv, pipe) {
15901                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15902                 intel_sanitize_crtc(crtc);
15903                 intel_dump_pipe_config(crtc, crtc->config,
15904                                        "[setup_hw_state]");
15905         }
15906
15907         intel_modeset_update_connector_atomic_state(dev);
15908
15909         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15910                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15911
15912                 if (!pll->on || pll->active)
15913                         continue;
15914
15915                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15916
15917                 pll->disable(dev_priv, pll);
15918                 pll->on = false;
15919         }
15920
15921         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15922                 vlv_wm_get_hw_state(dev);
15923         else if (IS_GEN9(dev))
15924                 skl_wm_get_hw_state(dev);
15925         else if (HAS_PCH_SPLIT(dev))
15926                 ilk_wm_get_hw_state(dev);
15927
15928         for_each_intel_crtc(dev, crtc) {
15929                 unsigned long put_domains;
15930
15931                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15932                 if (WARN_ON(put_domains))
15933                         modeset_put_power_domains(dev_priv, put_domains);
15934         }
15935         intel_display_set_init_power(dev_priv, false);
15936 }
15937
15938 void intel_display_resume(struct drm_device *dev)
15939 {
15940         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15941         struct intel_connector *conn;
15942         struct intel_plane *plane;
15943         struct drm_crtc *crtc;
15944         int ret;
15945
15946         if (!state)
15947                 return;
15948
15949         state->acquire_ctx = dev->mode_config.acquire_ctx;
15950
15951         /* preserve complete old state, including dpll */
15952         intel_atomic_get_shared_dpll_state(state);
15953
15954         for_each_crtc(dev, crtc) {
15955                 struct drm_crtc_state *crtc_state =
15956                         drm_atomic_get_crtc_state(state, crtc);
15957
15958                 ret = PTR_ERR_OR_ZERO(crtc_state);
15959                 if (ret)
15960                         goto err;
15961
15962                 /* force a restore */
15963                 crtc_state->mode_changed = true;
15964         }
15965
15966         for_each_intel_plane(dev, plane) {
15967                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15968                 if (ret)
15969                         goto err;
15970         }
15971
15972         for_each_intel_connector(dev, conn) {
15973                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15974                 if (ret)
15975                         goto err;
15976         }
15977
15978         intel_modeset_setup_hw_state(dev);
15979
15980         i915_redisable_vga(dev);
15981         ret = drm_atomic_commit(state);
15982         if (!ret)
15983                 return;
15984
15985 err:
15986         DRM_ERROR("Restoring old state failed with %i\n", ret);
15987         drm_atomic_state_free(state);
15988 }
15989
15990 void intel_modeset_gem_init(struct drm_device *dev)
15991 {
15992         struct drm_crtc *c;
15993         struct drm_i915_gem_object *obj;
15994         int ret;
15995
15996         mutex_lock(&dev->struct_mutex);
15997         intel_init_gt_powersave(dev);
15998         mutex_unlock(&dev->struct_mutex);
15999
16000         intel_modeset_init_hw(dev);
16001
16002         intel_setup_overlay(dev);
16003
16004         /*
16005          * Make sure any fbs we allocated at startup are properly
16006          * pinned & fenced.  When we do the allocation it's too early
16007          * for this.
16008          */
16009         for_each_crtc(dev, c) {
16010                 obj = intel_fb_obj(c->primary->fb);
16011                 if (obj == NULL)
16012                         continue;
16013
16014                 mutex_lock(&dev->struct_mutex);
16015                 ret = intel_pin_and_fence_fb_obj(c->primary,
16016                                                  c->primary->fb,
16017                                                  c->primary->state);
16018                 mutex_unlock(&dev->struct_mutex);
16019                 if (ret) {
16020                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16021                                   to_intel_crtc(c)->pipe);
16022                         drm_framebuffer_unreference(c->primary->fb);
16023                         c->primary->fb = NULL;
16024                         c->primary->crtc = c->primary->state->crtc = NULL;
16025                         update_state_fb(c->primary);
16026                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16027                 }
16028         }
16029
16030         intel_backlight_register(dev);
16031 }
16032
16033 void intel_connector_unregister(struct intel_connector *intel_connector)
16034 {
16035         struct drm_connector *connector = &intel_connector->base;
16036
16037         intel_panel_destroy_backlight(connector);
16038         drm_connector_unregister(connector);
16039 }
16040
16041 void intel_modeset_cleanup(struct drm_device *dev)
16042 {
16043         struct drm_i915_private *dev_priv = dev->dev_private;
16044         struct intel_connector *connector;
16045
16046         intel_disable_gt_powersave(dev);
16047
16048         intel_backlight_unregister(dev);
16049
16050         /*
16051          * Interrupts and polling as the first thing to avoid creating havoc.
16052          * Too much stuff here (turning of connectors, ...) would
16053          * experience fancy races otherwise.
16054          */
16055         intel_irq_uninstall(dev_priv);
16056
16057         /*
16058          * Due to the hpd irq storm handling the hotplug work can re-arm the
16059          * poll handlers. Hence disable polling after hpd handling is shut down.
16060          */
16061         drm_kms_helper_poll_fini(dev);
16062
16063         intel_unregister_dsm_handler();
16064
16065         intel_fbc_disable(dev_priv);
16066
16067         /* flush any delayed tasks or pending work */
16068         flush_scheduled_work();
16069
16070         /* destroy the backlight and sysfs files before encoders/connectors */
16071         for_each_intel_connector(dev, connector)
16072                 connector->unregister(connector);
16073
16074         drm_mode_config_cleanup(dev);
16075
16076         intel_cleanup_overlay(dev);
16077
16078         mutex_lock(&dev->struct_mutex);
16079         intel_cleanup_gt_powersave(dev);
16080         mutex_unlock(&dev->struct_mutex);
16081
16082         intel_teardown_gmbus(dev);
16083 }
16084
16085 /*
16086  * Return which encoder is currently attached for connector.
16087  */
16088 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16089 {
16090         return &intel_attached_encoder(connector)->base;
16091 }
16092
16093 void intel_connector_attach_encoder(struct intel_connector *connector,
16094                                     struct intel_encoder *encoder)
16095 {
16096         connector->encoder = encoder;
16097         drm_mode_connector_attach_encoder(&connector->base,
16098                                           &encoder->base);
16099 }
16100
16101 /*
16102  * set vga decode state - true == enable VGA decode
16103  */
16104 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16105 {
16106         struct drm_i915_private *dev_priv = dev->dev_private;
16107         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16108         u16 gmch_ctrl;
16109
16110         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16111                 DRM_ERROR("failed to read control word\n");
16112                 return -EIO;
16113         }
16114
16115         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16116                 return 0;
16117
16118         if (state)
16119                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16120         else
16121                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16122
16123         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16124                 DRM_ERROR("failed to write control word\n");
16125                 return -EIO;
16126         }
16127
16128         return 0;
16129 }
16130
16131 struct intel_display_error_state {
16132
16133         u32 power_well_driver;
16134
16135         int num_transcoders;
16136
16137         struct intel_cursor_error_state {
16138                 u32 control;
16139                 u32 position;
16140                 u32 base;
16141                 u32 size;
16142         } cursor[I915_MAX_PIPES];
16143
16144         struct intel_pipe_error_state {
16145                 bool power_domain_on;
16146                 u32 source;
16147                 u32 stat;
16148         } pipe[I915_MAX_PIPES];
16149
16150         struct intel_plane_error_state {
16151                 u32 control;
16152                 u32 stride;
16153                 u32 size;
16154                 u32 pos;
16155                 u32 addr;
16156                 u32 surface;
16157                 u32 tile_offset;
16158         } plane[I915_MAX_PIPES];
16159
16160         struct intel_transcoder_error_state {
16161                 bool power_domain_on;
16162                 enum transcoder cpu_transcoder;
16163
16164                 u32 conf;
16165
16166                 u32 htotal;
16167                 u32 hblank;
16168                 u32 hsync;
16169                 u32 vtotal;
16170                 u32 vblank;
16171                 u32 vsync;
16172         } transcoder[4];
16173 };
16174
16175 struct intel_display_error_state *
16176 intel_display_capture_error_state(struct drm_device *dev)
16177 {
16178         struct drm_i915_private *dev_priv = dev->dev_private;
16179         struct intel_display_error_state *error;
16180         int transcoders[] = {
16181                 TRANSCODER_A,
16182                 TRANSCODER_B,
16183                 TRANSCODER_C,
16184                 TRANSCODER_EDP,
16185         };
16186         int i;
16187
16188         if (INTEL_INFO(dev)->num_pipes == 0)
16189                 return NULL;
16190
16191         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16192         if (error == NULL)
16193                 return NULL;
16194
16195         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16196                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16197
16198         for_each_pipe(dev_priv, i) {
16199                 error->pipe[i].power_domain_on =
16200                         __intel_display_power_is_enabled(dev_priv,
16201                                                          POWER_DOMAIN_PIPE(i));
16202                 if (!error->pipe[i].power_domain_on)
16203                         continue;
16204
16205                 error->cursor[i].control = I915_READ(CURCNTR(i));
16206                 error->cursor[i].position = I915_READ(CURPOS(i));
16207                 error->cursor[i].base = I915_READ(CURBASE(i));
16208
16209                 error->plane[i].control = I915_READ(DSPCNTR(i));
16210                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16211                 if (INTEL_INFO(dev)->gen <= 3) {
16212                         error->plane[i].size = I915_READ(DSPSIZE(i));
16213                         error->plane[i].pos = I915_READ(DSPPOS(i));
16214                 }
16215                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16216                         error->plane[i].addr = I915_READ(DSPADDR(i));
16217                 if (INTEL_INFO(dev)->gen >= 4) {
16218                         error->plane[i].surface = I915_READ(DSPSURF(i));
16219                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16220                 }
16221
16222                 error->pipe[i].source = I915_READ(PIPESRC(i));
16223
16224                 if (HAS_GMCH_DISPLAY(dev))
16225                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16226         }
16227
16228         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16229         if (HAS_DDI(dev_priv->dev))
16230                 error->num_transcoders++; /* Account for eDP. */
16231
16232         for (i = 0; i < error->num_transcoders; i++) {
16233                 enum transcoder cpu_transcoder = transcoders[i];
16234
16235                 error->transcoder[i].power_domain_on =
16236                         __intel_display_power_is_enabled(dev_priv,
16237                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16238                 if (!error->transcoder[i].power_domain_on)
16239                         continue;
16240
16241                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16242
16243                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16244                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16245                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16246                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16247                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16248                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16249                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16250         }
16251
16252         return error;
16253 }
16254
16255 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16256
16257 void
16258 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16259                                 struct drm_device *dev,
16260                                 struct intel_display_error_state *error)
16261 {
16262         struct drm_i915_private *dev_priv = dev->dev_private;
16263         int i;
16264
16265         if (!error)
16266                 return;
16267
16268         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16269         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16270                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16271                            error->power_well_driver);
16272         for_each_pipe(dev_priv, i) {
16273                 err_printf(m, "Pipe [%d]:\n", i);
16274                 err_printf(m, "  Power: %s\n",
16275                            onoff(error->pipe[i].power_domain_on));
16276                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16277                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16278
16279                 err_printf(m, "Plane [%d]:\n", i);
16280                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16281                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16282                 if (INTEL_INFO(dev)->gen <= 3) {
16283                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16284                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16285                 }
16286                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16287                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16288                 if (INTEL_INFO(dev)->gen >= 4) {
16289                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16290                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16291                 }
16292
16293                 err_printf(m, "Cursor [%d]:\n", i);
16294                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16295                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16296                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16297         }
16298
16299         for (i = 0; i < error->num_transcoders; i++) {
16300                 err_printf(m, "CPU transcoder: %c\n",
16301                            transcoder_name(error->transcoder[i].cpu_transcoder));
16302                 err_printf(m, "  Power: %s\n",
16303                            onoff(error->transcoder[i].power_domain_on));
16304                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16305                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16306                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16307                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16308                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16309                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16310                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16311         }
16312 }