drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 /**
 424  * Returns whether any output on the specified pipe will have the specified
 425  * type after a staged modeset is complete, i.e., the same as
 426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 427  * encoder->crtc.
 428  */
 429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 430 {
 431         struct drm_device *dev = crtc->base.dev;
 432         struct intel_encoder *encoder;
 433
 434         for_each_intel_encoder(dev, encoder)
 435                 if (encoder->new_crtc == crtc && encoder->type == type)
 436                         return true;
 437
 438         return false;
 439 }
 440
 441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 442                                                 int refclk)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         const intel_limit_t *limit;
 446
 447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 448                 if (intel_is_dual_link_lvds(dev)) {
 449                         if (refclk == 100000)
 450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 451                         else
 452                                 limit = &intel_limits_ironlake_dual_lvds;
 453                 } else {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_single_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_single_lvds;
 458                 }
 459         } else
 460                 limit = &intel_limits_ironlake_dac;
 461
 462         return limit;
 463 }
 464
 465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 466 {
 467         struct drm_device *dev = crtc->base.dev;
 468         const intel_limit_t *limit;
 469
 470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 471                 if (intel_is_dual_link_lvds(dev))
 472                         limit = &intel_limits_g4x_dual_channel_lvds;
 473                 else
 474                         limit = &intel_limits_g4x_single_channel_lvds;
 475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 477                 limit = &intel_limits_g4x_hdmi;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 479                 limit = &intel_limits_g4x_sdvo;
 480         } else /* The option is for other outputs */
 481                 limit = &intel_limits_i9xx_sdvo;
 482
 483         return limit;
 484 }
 485
 486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 487 {
 488         struct drm_device *dev = crtc->base.dev;
 489         const intel_limit_t *limit;
 490
 491         if (HAS_PCH_SPLIT(dev))
 492                 limit = intel_ironlake_limit(crtc, refclk);
 493         else if (IS_G4X(dev)) {
 494                 limit = intel_g4x_limit(crtc);
 495         } else if (IS_PINEVIEW(dev)) {
 496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 497                         limit = &intel_limits_pineview_lvds;
 498                 else
 499                         limit = &intel_limits_pineview_sdvo;
 500         } else if (IS_CHERRYVIEW(dev)) {
 501                 limit = &intel_limits_chv;
 502         } else if (IS_VALLEYVIEW(dev)) {
 503                 limit = &intel_limits_vlv;
 504         } else if (!IS_GEN2(dev)) {
 505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 506                         limit = &intel_limits_i9xx_lvds;
 507                 else
 508                         limit = &intel_limits_i9xx_sdvo;
 509         } else {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i8xx_lvds;
 512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 513                         limit = &intel_limits_i8xx_dvo;
 514                 else
 515                         limit = &intel_limits_i8xx_dac;
 516         }
 517         return limit;
 518 }
 519
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static void pineview_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 532 {
 533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 534 }
 535
 536 static void i9xx_clock(int refclk, intel_clock_t *clock)
 537 {
 538         clock->m = i9xx_dpll_compute_m(clock);
 539         clock->p = clock->p1 * clock->p2;
 540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 541                 return;
 542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 544 }
 545
 546 static void chv_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m1 * clock->m2;
 549         clock->p = clock->p1 * clock->p2;
 550         if (WARN_ON(clock->n == 0 || clock->p == 0))
 551                 return;
 552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 553                         clock->n << 22);
 554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 555 }
 556
 557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 558 /**
 559  * Returns whether the given set of divisors are valid for a given refclk with
 560  * the given connectors.
 561  */
 562
 563 static bool intel_PLL_is_valid(struct drm_device *dev,
 564                                const intel_limit_t *limit,
 565                                const intel_clock_t *clock)
 566 {
 567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 568                 INTELPllInvalid("n out of range\n");
 569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 570                 INTELPllInvalid("p1 out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid("m1 out of range\n");
 575
 576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 577                 if (clock->m1 <= clock->m2)
 578                         INTELPllInvalid("m1 <= m2\n");
 579
 580         if (!IS_VALLEYVIEW(dev)) {
 581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 582                         INTELPllInvalid("p out of range\n");
 583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 584                         INTELPllInvalid("m out of range\n");
 585         }
 586
 587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 588                 INTELPllInvalid("vco out of range\n");
 589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 590          * connector, etc., rather than just a single range.
 591          */
 592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 593                 INTELPllInvalid("dot out of range\n");
 594
 595         return true;
 596 }
 597
 598 static bool
 599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 600                     int target, int refclk, intel_clock_t *match_clock,
 601                     intel_clock_t *best_clock)
 602 {
 603         struct drm_device *dev = crtc->base.dev;
 604         intel_clock_t clock;
 605         int err = target;
 606
 607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 608                 /*
 609                  * For LVDS just rely on its current settings for dual-channel.
 610                  * We haven't figured out how to reliably set up different
 611                  * single/dual channel state, if we even can.
 612                  */
 613                 if (intel_is_dual_link_lvds(dev))
 614                         clock.p2 = limit->p2.p2_fast;
 615                 else
 616                         clock.p2 = limit->p2.p2_slow;
 617         } else {
 618                 if (target < limit->p2.dot_limit)
 619                         clock.p2 = limit->p2.p2_slow;
 620                 else
 621                         clock.p2 = limit->p2.p2_fast;
 622         }
 623
 624         memset(best_clock, 0, sizeof(*best_clock));
 625
 626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 627              clock.m1++) {
 628                 for (clock.m2 = limit->m2.min;
 629                      clock.m2 <= limit->m2.max; clock.m2++) {
 630                         if (clock.m2 >= clock.m1)
 631                                 break;
 632                         for (clock.n = limit->n.min;
 633                              clock.n <= limit->n.max; clock.n++) {
 634                                 for (clock.p1 = limit->p1.min;
 635                                         clock.p1 <= limit->p1.max; clock.p1++) {
 636                                         int this_err;
 637
 638                                         i9xx_clock(refclk, &clock);
 639                                         if (!intel_PLL_is_valid(dev, limit,
 640                                                                 &clock))
 641                                                 continue;
 642                                         if (match_clock &&
 643                                             clock.p != match_clock->p)
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err) {
 648                                                 *best_clock = clock;
 649                                                 err = this_err;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655
 656         return (err != target);
 657 }
 658
 659 static bool
 660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 661                    int target, int refclk, intel_clock_t *match_clock,
 662                    intel_clock_t *best_clock)
 663 {
 664         struct drm_device *dev = crtc->base.dev;
 665         intel_clock_t clock;
 666         int err = target;
 667
 668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         clock.p2 = limit->p2.p2_fast;
 676                 else
 677                         clock.p2 = limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         clock.p2 = limit->p2.p2_slow;
 681                 else
 682                         clock.p2 = limit->p2.p2_fast;
 683         }
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pineview_clock(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(dev, limit,
 699                                                                 &clock))
 700                                                 continue;
 701                                         if (match_clock &&
 702                                             clock.p != match_clock->p)
 703                                                 continue;
 704
 705                                         this_err = abs(clock.dot - target);
 706                                         if (this_err < err) {
 707                                                 *best_clock = clock;
 708                                                 err = this_err;
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714
 715         return (err != target);
 716 }
 717
 718 static bool
 719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->base.dev;
 724         intel_clock_t clock;
 725         int max_n;
 726         bool found;
 727         /* approximately equals target * 0.00585 */
 728         int err_most = (target >> 8) + (target >> 9);
 729         found = false;
 730
 731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 732                 if (intel_is_dual_link_lvds(dev))
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744         max_n = limit->n.max;
 745         /* based on hardware requirement, prefer smaller n to precision */
 746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 747                 /* based on hardware requirement, prefere larger m1,m2 */
 748                 for (clock.m1 = limit->m1.max;
 749                      clock.m1 >= limit->m1.min; clock.m1--) {
 750                         for (clock.m2 = limit->m2.max;
 751                              clock.m2 >= limit->m2.min; clock.m2--) {
 752                                 for (clock.p1 = limit->p1.max;
 753                                      clock.p1 >= limit->p1.min; clock.p1--) {
 754                                         int this_err;
 755
 756                                         i9xx_clock(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760
 761                                         this_err = abs(clock.dot - target);
 762                                         if (this_err < err_most) {
 763                                                 *best_clock = clock;
 764                                                 err_most = this_err;
 765                                                 max_n = clock.n;
 766                                                 found = true;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772         return found;
 773 }
 774
 775 static bool
 776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         intel_clock_t clock;
 782         unsigned int bestppm = 1000000;
 783         /* min update 19.2 MHz */
 784         int max_n = min(limit->n.max, refclk / 19200);
 785         bool found = false;
 786
 787         target *= 5; /* fast clock */
 788
 789         memset(best_clock, 0, sizeof(*best_clock));
 790
 791         /* based on hardware requirement, prefer smaller n to precision */
 792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 796                                 clock.p = clock.p1 * clock.p2;
 797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 799                                         unsigned int ppm, diff;
 800
 801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 802                                                                      refclk * clock.m1);
 803
 804                                         vlv_clock(refclk, &clock);
 805
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         diff = abs(clock.dot - target);
 811                                         ppm = div_u64(1000000ULL * diff, target);
 812
 813                                         if (ppm < 100 && clock.p > best_clock->p) {
 814                                                 bestppm = 0;
 815                                                 *best_clock = clock;
 816                                                 found = true;
 817                                         }
 818
 819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 820                                                 bestppm = ppm;
 821                                                 *best_clock = clock;
 822                                                 found = true;
 823                                         }
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         return found;
 830 }
 831
 832 static bool
 833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 834                    int target, int refclk, intel_clock_t *match_clock,
 835                    intel_clock_t *best_clock)
 836 {
 837         struct drm_device *dev = crtc->base.dev;
 838         intel_clock_t clock;
 839         uint64_t m2;
 840         int found = false;
 841
 842         memset(best_clock, 0, sizeof(*best_clock));
 843
 844         /*
 845          * Based on hardware doc, the n always set to 1, and m1 always
 846          * set to 2.  If requires to support 200Mhz refclk, we need to
 847          * revisit this because n may not 1 anymore.
 848          */
 849         clock.n = 1, clock.m1 = 2;
 850         target *= 5;    /* fast clock */
 851
 852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 853                 for (clock.p2 = limit->p2.p2_fast;
 854                                 clock.p2 >= limit->p2.p2_slow;
 855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 856
 857                         clock.p = clock.p1 * clock.p2;
 858
 859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 860                                         clock.n) << 22, refclk * clock.m1);
 861
 862                         if (m2 > INT_MAX/clock.m1)
 863                                 continue;
 864
 865                         clock.m2 = m2;
 866
 867                         chv_clock(refclk, &clock);
 868
 869                         if (!intel_PLL_is_valid(dev, limit, &clock))
 870                                 continue;
 871
 872                         /* based on hardware requirement, prefer bigger p
 873                          */
 874                         if (clock.p > best_clock->p) {
 875                                 *best_clock = clock;
 876                                 found = true;
 877                         }
 878                 }
 879         }
 880
 881         return found;
 882 }
 883
 884 bool intel_crtc_active(struct drm_crtc *crtc)
 885 {
 886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 887
 888         /* Be paranoid as we can arrive here with only partial
 889          * state retrieved from the hardware during setup.
 890          *
 891          * We can ditch the adjusted_mode.crtc_clock check as soon
 892          * as Haswell has gained clock readout/fastboot support.
 893          *
 894          * We can ditch the crtc->primary->fb check as soon as we can
 895          * properly reconstruct framebuffers.
 896          */
 897         return intel_crtc->active && crtc->primary->fb &&
 898                 intel_crtc->config.adjusted_mode.crtc_clock;
 899 }
 900
 901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 902                                              enum pipe pipe)
 903 {
 904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 906
 907         return intel_crtc->config.cpu_transcoder;
 908 }
 909
 910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         u32 reg = PIPEDSL(pipe);
 914         u32 line1, line2;
 915         u32 line_mask;
 916
 917         if (IS_GEN2(dev))
 918                 line_mask = DSL_LINEMASK_GEN2;
 919         else
 920                 line_mask = DSL_LINEMASK_GEN3;
 921
 922         line1 = I915_READ(reg) & line_mask;
 923         mdelay(5);
 924         line2 = I915_READ(reg) & line_mask;
 925
 926         return line1 == line2;
 927 }
 928
 929 /*
 930  * intel_wait_for_pipe_off - wait for pipe to turn off
 931  * @crtc: crtc whose pipe to wait for
 932  *
 933  * After disabling a pipe, we can't wait for vblank in the usual way,
 934  * spinning on the vblank interrupt status bit, since we won't actually
 935  * see an interrupt when the pipe is disabled.
 936  *
 937  * On Gen4 and above:
 938  *   wait for the pipe register state bit to turn off
 939  *
 940  * Otherwise:
 941  *   wait for the display line value to settle (it usually
 942  *   ends up stopping at the start of the next frame).
 943  *
 944  */
 945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 946 {
 947         struct drm_device *dev = crtc->base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 950         enum pipe pipe = crtc->pipe;
 951
 952         if (INTEL_INFO(dev)->gen >= 4) {
 953                 int reg = PIPECONF(cpu_transcoder);
 954
 955                 /* Wait for the Pipe State to go off */
 956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 957                              100))
 958                         WARN(1, "pipe_off wait timed out\n");
 959         } else {
 960                 /* Wait for the display line to settle */
 961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 962                         WARN(1, "pipe_off wait timed out\n");
 963         }
 964 }
 965
 966 /*
 967  * ibx_digital_port_connected - is the specified port connected?
 968  * @dev_priv: i915 private structure
 969  * @port: the port to test
 970  *
 971  * Returns true if @port is connected, false otherwise.
 972  */
 973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 974                                 struct intel_digital_port *port)
 975 {
 976         u32 bit;
 977
 978         if (HAS_PCH_IBX(dev_priv->dev)) {
 979                 switch (port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         } else {
 993                 switch (port->port) {
 994                 case PORT_B:
 995                         bit = SDE_PORTB_HOTPLUG_CPT;
 996                         break;
 997                 case PORT_C:
 998                         bit = SDE_PORTC_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007
1008         return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         I915_STATE_WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         I915_STATE_WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         I915_STATE_WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         I915_STATE_WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         I915_STATE_WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         I915_STATE_WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         I915_STATE_WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209         I915_STATE_WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         I915_STATE_WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         I915_STATE_WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         I915_STATE_WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 I915_STATE_WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 I915_STATE_WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339
1340         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         I915_STATE_WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441
1442         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454
1455         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559         mutex_lock(&dev_priv->dpio_lock);
1560
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594         return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724         mutex_lock(&dev_priv->dpio_lock);
1725
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781
1782         WARN_ON(!pll->config.crtc_mask);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         if (WARN_ON(pll->config.crtc_mask == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840
1841         if (WARN_ON(pll->config.crtc_mask == 0))
1842                 return;
1843
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139
2140         intel_crtc->primary_enabled = true;
2141
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172
2173         intel_crtc->primary_enabled = false;
2174
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198                            struct drm_framebuffer *fb,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_device *dev = fb->dev;
2202         struct drm_i915_private *dev_priv = dev->dev_private;
2203         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2204         u32 alignment;
2205         int ret;
2206
2207         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
2209         switch (obj->tiling_mode) {
2210         case I915_TILING_NONE:
2211                 if (INTEL_INFO(dev)->gen >= 9)
2212                         alignment = 256 * 1024;
2213                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214                         alignment = 128 * 1024;
2215                 else if (INTEL_INFO(dev)->gen >= 4)
2216                         alignment = 4 * 1024;
2217                 else
2218                         alignment = 64 * 1024;
2219                 break;
2220         case I915_TILING_X:
2221                 if (INTEL_INFO(dev)->gen >= 9)
2222                         alignment = 256 * 1024;
2223                 else {
2224                         /* pin() will align the object as required by fence */
2225                         alignment = 0;
2226                 }
2227                 break;
2228         case I915_TILING_Y:
2229                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2230                 return -EINVAL;
2231         default:
2232                 BUG();
2233         }
2234
2235         /* Note that the w/a also requires 64 PTE of padding following the
2236          * bo. We currently fill all unused PTE with the shadow page and so
2237          * we should always have valid PTE following the scanout preventing
2238          * the VT-d warning.
2239          */
2240         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241                 alignment = 256 * 1024;
2242
2243         /*
2244          * Global gtt pte registers are special registers which actually forward
2245          * writes to a chunk of system memory. Which means that there is no risk
2246          * that the register values disappear as soon as we call
2247          * intel_runtime_pm_put(), so it is correct to wrap only the
2248          * pin/unpin/fence and not more.
2249          */
2250         intel_runtime_pm_get(dev_priv);
2251
2252         dev_priv->mm.interruptible = false;
2253         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2254         if (ret)
2255                 goto err_interruptible;
2256
2257         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258          * fence, whereas 965+ only requires a fence if using
2259          * framebuffer compression.  For simplicity, we always install
2260          * a fence as the cost is not that onerous.
2261          */
2262         ret = i915_gem_object_get_fence(obj);
2263         if (ret)
2264                 goto err_unpin;
2265
2266         i915_gem_object_pin_fence(obj);
2267
2268         dev_priv->mm.interruptible = true;
2269         intel_runtime_pm_put(dev_priv);
2270         return 0;
2271
2272 err_unpin:
2273         i915_gem_object_unpin_from_display_plane(obj);
2274 err_interruptible:
2275         dev_priv->mm.interruptible = true;
2276         intel_runtime_pm_put(dev_priv);
2277         return ret;
2278 }
2279
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281 {
2282         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
2284         i915_gem_object_unpin_fence(obj);
2285         i915_gem_object_unpin_from_display_plane(obj);
2286 }
2287
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289  * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291                                              unsigned int tiling_mode,
2292                                              unsigned int cpp,
2293                                              unsigned int pitch)
2294 {
2295         if (tiling_mode != I915_TILING_NONE) {
2296                 unsigned int tile_rows, tiles;
2297
2298                 tile_rows = *y / 8;
2299                 *y %= 8;
2300
2301                 tiles = *x / (512/cpp);
2302                 *x %= 512/cpp;
2303
2304                 return tile_rows * pitch * 8 + tiles * 4096;
2305         } else {
2306                 unsigned int offset;
2307
2308                 offset = *y * pitch + *x * cpp;
2309                 *y = 0;
2310                 *x = (offset & 4095) / cpp;
2311                 return offset & -4096;
2312         }
2313 }
2314
2315 int intel_format_to_fourcc(int format)
2316 {
2317         switch (format) {
2318         case DISPPLANE_8BPP:
2319                 return DRM_FORMAT_C8;
2320         case DISPPLANE_BGRX555:
2321                 return DRM_FORMAT_XRGB1555;
2322         case DISPPLANE_BGRX565:
2323                 return DRM_FORMAT_RGB565;
2324         default:
2325         case DISPPLANE_BGRX888:
2326                 return DRM_FORMAT_XRGB8888;
2327         case DISPPLANE_RGBX888:
2328                 return DRM_FORMAT_XBGR8888;
2329         case DISPPLANE_BGRX101010:
2330                 return DRM_FORMAT_XRGB2101010;
2331         case DISPPLANE_RGBX101010:
2332                 return DRM_FORMAT_XBGR2101010;
2333         }
2334 }
2335
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337                                   struct intel_plane_config *plane_config)
2338 {
2339         struct drm_device *dev = crtc->base.dev;
2340         struct drm_i915_gem_object *obj = NULL;
2341         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342         u32 base = plane_config->base;
2343
2344         if (plane_config->size == 0)
2345                 return false;
2346
2347         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348                                                              plane_config->size);
2349         if (!obj)
2350                 return false;
2351
2352         if (plane_config->tiled) {
2353                 obj->tiling_mode = I915_TILING_X;
2354                 obj->stride = crtc->base.primary->fb->pitches[0];
2355         }
2356
2357         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358         mode_cmd.width = crtc->base.primary->fb->width;
2359         mode_cmd.height = crtc->base.primary->fb->height;
2360         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2361
2362         mutex_lock(&dev->struct_mutex);
2363
2364         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2365                                    &mode_cmd, obj)) {
2366                 DRM_DEBUG_KMS("intel fb init failed\n");
2367                 goto out_unref_obj;
2368         }
2369
2370         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371         mutex_unlock(&dev->struct_mutex);
2372
2373         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374         return true;
2375
2376 out_unref_obj:
2377         drm_gem_object_unreference(&obj->base);
2378         mutex_unlock(&dev->struct_mutex);
2379         return false;
2380 }
2381
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383                                  struct intel_plane_config *plane_config)
2384 {
2385         struct drm_device *dev = intel_crtc->base.dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct drm_crtc *c;
2388         struct intel_crtc *i;
2389         struct drm_i915_gem_object *obj;
2390
2391         if (!intel_crtc->base.primary->fb)
2392                 return;
2393
2394         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395                 return;
2396
2397         kfree(intel_crtc->base.primary->fb);
2398         intel_crtc->base.primary->fb = NULL;
2399
2400         /*
2401          * Failed to alloc the obj, check to see if we should share
2402          * an fb with another CRTC instead
2403          */
2404         for_each_crtc(dev, c) {
2405                 i = to_intel_crtc(c);
2406
2407                 if (c == &intel_crtc->base)
2408                         continue;
2409
2410                 if (!i->active)
2411                         continue;
2412
2413                 obj = intel_fb_obj(c->primary->fb);
2414                 if (obj == NULL)
2415                         continue;
2416
2417                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418                         if (obj->tiling_mode != I915_TILING_NONE)
2419                                 dev_priv->preserve_bios_swizzle = true;
2420
2421                         drm_framebuffer_reference(c->primary->fb);
2422                         intel_crtc->base.primary->fb = c->primary->fb;
2423                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2424                         break;
2425                 }
2426         }
2427 }
2428
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430                                       struct drm_framebuffer *fb,
2431                                       int x, int y)
2432 {
2433         struct drm_device *dev = crtc->dev;
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436         struct drm_i915_gem_object *obj;
2437         int plane = intel_crtc->plane;
2438         unsigned long linear_offset;
2439         u32 dspcntr;
2440         u32 reg = DSPCNTR(plane);
2441         int pixel_size;
2442
2443         if (!intel_crtc->primary_enabled) {
2444                 I915_WRITE(reg, 0);
2445                 if (INTEL_INFO(dev)->gen >= 4)
2446                         I915_WRITE(DSPSURF(plane), 0);
2447                 else
2448                         I915_WRITE(DSPADDR(plane), 0);
2449                 POSTING_READ(reg);
2450                 return;
2451         }
2452
2453         obj = intel_fb_obj(fb);
2454         if (WARN_ON(obj == NULL))
2455                 return;
2456
2457         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
2459         dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
2461         dspcntr |= DISPLAY_PLANE_ENABLE;
2462
2463         if (INTEL_INFO(dev)->gen < 4) {
2464                 if (intel_crtc->pipe == PIPE_B)
2465                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467                 /* pipesrc and dspsize control the size that is scaled from,
2468                  * which should always be the user's requested size.
2469                  */
2470                 I915_WRITE(DSPSIZE(plane),
2471                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472                            (intel_crtc->config.pipe_src_w - 1));
2473                 I915_WRITE(DSPPOS(plane), 0);
2474         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475                 I915_WRITE(PRIMSIZE(plane),
2476                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477                            (intel_crtc->config.pipe_src_w - 1));
2478                 I915_WRITE(PRIMPOS(plane), 0);
2479                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480         }
2481
2482         switch (fb->pixel_format) {
2483         case DRM_FORMAT_C8:
2484                 dspcntr |= DISPPLANE_8BPP;
2485                 break;
2486         case DRM_FORMAT_XRGB1555:
2487         case DRM_FORMAT_ARGB1555:
2488                 dspcntr |= DISPPLANE_BGRX555;
2489                 break;
2490         case DRM_FORMAT_RGB565:
2491                 dspcntr |= DISPPLANE_BGRX565;
2492                 break;
2493         case DRM_FORMAT_XRGB8888:
2494         case DRM_FORMAT_ARGB8888:
2495                 dspcntr |= DISPPLANE_BGRX888;
2496                 break;
2497         case DRM_FORMAT_XBGR8888:
2498         case DRM_FORMAT_ABGR8888:
2499                 dspcntr |= DISPPLANE_RGBX888;
2500                 break;
2501         case DRM_FORMAT_XRGB2101010:
2502         case DRM_FORMAT_ARGB2101010:
2503                 dspcntr |= DISPPLANE_BGRX101010;
2504                 break;
2505         case DRM_FORMAT_XBGR2101010:
2506         case DRM_FORMAT_ABGR2101010:
2507                 dspcntr |= DISPPLANE_RGBX101010;
2508                 break;
2509         default:
2510                 BUG();
2511         }
2512
2513         if (INTEL_INFO(dev)->gen >= 4 &&
2514             obj->tiling_mode != I915_TILING_NONE)
2515                 dspcntr |= DISPPLANE_TILED;
2516
2517         if (IS_G4X(dev))
2518                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
2520         linear_offset = y * fb->pitches[0] + x * pixel_size;
2521
2522         if (INTEL_INFO(dev)->gen >= 4) {
2523                 intel_crtc->dspaddr_offset =
2524                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525                                                        pixel_size,
2526                                                        fb->pitches[0]);
2527                 linear_offset -= intel_crtc->dspaddr_offset;
2528         } else {
2529                 intel_crtc->dspaddr_offset = linear_offset;
2530         }
2531
2532         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533                 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535                 x += (intel_crtc->config.pipe_src_w - 1);
2536                 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538                 /* Finding the last pixel of the last line of the display
2539                 data and adding to linear_offset*/
2540                 linear_offset +=
2541                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543         }
2544
2545         I915_WRITE(reg, dspcntr);
2546
2547         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549                       fb->pitches[0]);
2550         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551         if (INTEL_INFO(dev)->gen >= 4) {
2552                 I915_WRITE(DSPSURF(plane),
2553                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2556         } else
2557                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2558         POSTING_READ(reg);
2559 }
2560
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562                                           struct drm_framebuffer *fb,
2563                                           int x, int y)
2564 {
2565         struct drm_device *dev = crtc->dev;
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568         struct drm_i915_gem_object *obj;
2569         int plane = intel_crtc->plane;
2570         unsigned long linear_offset;
2571         u32 dspcntr;
2572         u32 reg = DSPCNTR(plane);
2573         int pixel_size;
2574
2575         if (!intel_crtc->primary_enabled) {
2576                 I915_WRITE(reg, 0);
2577                 I915_WRITE(DSPSURF(plane), 0);
2578                 POSTING_READ(reg);
2579                 return;
2580         }
2581
2582         obj = intel_fb_obj(fb);
2583         if (WARN_ON(obj == NULL))
2584                 return;
2585
2586         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
2588         dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
2590         dspcntr |= DISPLAY_PLANE_ENABLE;
2591
2592         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
2595         switch (fb->pixel_format) {
2596         case DRM_FORMAT_C8:
2597                 dspcntr |= DISPPLANE_8BPP;
2598                 break;
2599         case DRM_FORMAT_RGB565:
2600                 dspcntr |= DISPPLANE_BGRX565;
2601                 break;
2602         case DRM_FORMAT_XRGB8888:
2603         case DRM_FORMAT_ARGB8888:
2604                 dspcntr |= DISPPLANE_BGRX888;
2605                 break;
2606         case DRM_FORMAT_XBGR8888:
2607         case DRM_FORMAT_ABGR8888:
2608                 dspcntr |= DISPPLANE_RGBX888;
2609                 break;
2610         case DRM_FORMAT_XRGB2101010:
2611         case DRM_FORMAT_ARGB2101010:
2612                 dspcntr |= DISPPLANE_BGRX101010;
2613                 break;
2614         case DRM_FORMAT_XBGR2101010:
2615         case DRM_FORMAT_ABGR2101010:
2616                 dspcntr |= DISPPLANE_RGBX101010;
2617                 break;
2618         default:
2619                 BUG();
2620         }
2621
2622         if (obj->tiling_mode != I915_TILING_NONE)
2623                 dspcntr |= DISPPLANE_TILED;
2624
2625         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2627
2628         linear_offset = y * fb->pitches[0] + x * pixel_size;
2629         intel_crtc->dspaddr_offset =
2630                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631                                                pixel_size,
2632                                                fb->pitches[0]);
2633         linear_offset -= intel_crtc->dspaddr_offset;
2634         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635                 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638                         x += (intel_crtc->config.pipe_src_w - 1);
2639                         y += (intel_crtc->config.pipe_src_h - 1);
2640
2641                         /* Finding the last pixel of the last line of the display
2642                         data and adding to linear_offset*/
2643                         linear_offset +=
2644                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646                 }
2647         }
2648
2649         I915_WRITE(reg, dspcntr);
2650
2651         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653                       fb->pitches[0]);
2654         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655         I915_WRITE(DSPSURF(plane),
2656                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659         } else {
2660                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662         }
2663         POSTING_READ(reg);
2664 }
2665
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667                                          struct drm_framebuffer *fb,
2668                                          int x, int y)
2669 {
2670         struct drm_device *dev = crtc->dev;
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673         struct intel_framebuffer *intel_fb;
2674         struct drm_i915_gem_object *obj;
2675         int pipe = intel_crtc->pipe;
2676         u32 plane_ctl, stride;
2677
2678         if (!intel_crtc->primary_enabled) {
2679                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681                 POSTING_READ(PLANE_CTL(pipe, 0));
2682                 return;
2683         }
2684
2685         plane_ctl = PLANE_CTL_ENABLE |
2686                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2687                     PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689         switch (fb->pixel_format) {
2690         case DRM_FORMAT_RGB565:
2691                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692                 break;
2693         case DRM_FORMAT_XRGB8888:
2694                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695                 break;
2696         case DRM_FORMAT_XBGR8888:
2697                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699                 break;
2700         case DRM_FORMAT_XRGB2101010:
2701                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702                 break;
2703         case DRM_FORMAT_XBGR2101010:
2704                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706                 break;
2707         default:
2708                 BUG();
2709         }
2710
2711         intel_fb = to_intel_framebuffer(fb);
2712         obj = intel_fb->obj;
2713
2714         /*
2715          * The stride is either expressed as a multiple of 64 bytes chunks for
2716          * linear buffers or in number of tiles for tiled buffers.
2717          */
2718         switch (obj->tiling_mode) {
2719         case I915_TILING_NONE:
2720                 stride = fb->pitches[0] >> 6;
2721                 break;
2722         case I915_TILING_X:
2723                 plane_ctl |= PLANE_CTL_TILED_X;
2724                 stride = fb->pitches[0] >> 9;
2725                 break;
2726         default:
2727                 BUG();
2728         }
2729
2730         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732                 plane_ctl |= PLANE_CTL_ROTATE_180;
2733
2734         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737                       i915_gem_obj_ggtt_offset(obj),
2738                       x, y, fb->width, fb->height,
2739                       fb->pitches[0]);
2740
2741         I915_WRITE(PLANE_POS(pipe, 0), 0);
2742         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743         I915_WRITE(PLANE_SIZE(pipe, 0),
2744                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2745                    (intel_crtc->config.pipe_src_w - 1));
2746         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749         POSTING_READ(PLANE_SURF(pipe, 0));
2750 }
2751
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2753 static int
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755                            int x, int y, enum mode_set_atomic state)
2756 {
2757         struct drm_device *dev = crtc->dev;
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759
2760         if (dev_priv->display.disable_fbc)
2761                 dev_priv->display.disable_fbc(dev);
2762
2763         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765         return 0;
2766 }
2767
2768 static void intel_complete_page_flips(struct drm_device *dev)
2769 {
2770         struct drm_crtc *crtc;
2771
2772         for_each_crtc(dev, crtc) {
2773                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774                 enum plane plane = intel_crtc->plane;
2775
2776                 intel_prepare_page_flip(dev, plane);
2777                 intel_finish_page_flip_plane(dev, plane);
2778         }
2779 }
2780
2781 static void intel_update_primary_planes(struct drm_device *dev)
2782 {
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         struct drm_crtc *crtc;
2785
2786         for_each_crtc(dev, crtc) {
2787                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2788
2789                 drm_modeset_lock(&crtc->mutex, NULL);
2790                 /*
2791                  * FIXME: Once we have proper support for primary planes (and
2792                  * disabling them without disabling the entire crtc) allow again
2793                  * a NULL crtc->primary->fb.
2794                  */
2795                 if (intel_crtc->active && crtc->primary->fb)
2796                         dev_priv->display.update_primary_plane(crtc,
2797                                                                crtc->primary->fb,
2798                                                                crtc->x,
2799                                                                crtc->y);
2800                 drm_modeset_unlock(&crtc->mutex);
2801         }
2802 }
2803
2804 void intel_prepare_reset(struct drm_device *dev)
2805 {
2806         struct drm_i915_private *dev_priv = to_i915(dev);
2807         struct intel_crtc *crtc;
2808
2809         /* no reset support for gen2 */
2810         if (IS_GEN2(dev))
2811                 return;
2812
2813         /* reset doesn't touch the display */
2814         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2815                 return;
2816
2817         drm_modeset_lock_all(dev);
2818
2819         /*
2820          * Disabling the crtcs gracefully seems nicer. Also the
2821          * g33 docs say we should at least disable all the planes.
2822          */
2823         for_each_intel_crtc(dev, crtc) {
2824                 if (crtc->active)
2825                         dev_priv->display.crtc_disable(&crtc->base);
2826         }
2827 }
2828
2829 void intel_finish_reset(struct drm_device *dev)
2830 {
2831         struct drm_i915_private *dev_priv = to_i915(dev);
2832
2833         /*
2834          * Flips in the rings will be nuked by the reset,
2835          * so complete all pending flips so that user space
2836          * will get its events and not get stuck.
2837          */
2838         intel_complete_page_flips(dev);
2839
2840         /* no reset support for gen2 */
2841         if (IS_GEN2(dev))
2842                 return;
2843
2844         /* reset doesn't touch the display */
2845         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2846                 /*
2847                  * Flips in the rings have been nuked by the reset,
2848                  * so update the base address of all primary
2849                  * planes to the the last fb to make sure we're
2850                  * showing the correct fb after a reset.
2851                  */
2852                 intel_update_primary_planes(dev);
2853                 return;
2854         }
2855
2856         /*
2857          * The display has been reset as well,
2858          * so need a full re-initialization.
2859          */
2860         intel_runtime_pm_disable_interrupts(dev_priv);
2861         intel_runtime_pm_enable_interrupts(dev_priv);
2862
2863         intel_modeset_init_hw(dev);
2864
2865         spin_lock_irq(&dev_priv->irq_lock);
2866         if (dev_priv->display.hpd_irq_setup)
2867                 dev_priv->display.hpd_irq_setup(dev);
2868         spin_unlock_irq(&dev_priv->irq_lock);
2869
2870         intel_modeset_setup_hw_state(dev, true);
2871
2872         intel_hpd_init(dev_priv);
2873
2874         drm_modeset_unlock_all(dev);
2875 }
2876
2877 static int
2878 intel_finish_fb(struct drm_framebuffer *old_fb)
2879 {
2880         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2881         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2882         bool was_interruptible = dev_priv->mm.interruptible;
2883         int ret;
2884
2885         /* Big Hammer, we also need to ensure that any pending
2886          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2887          * current scanout is retired before unpinning the old
2888          * framebuffer.
2889          *
2890          * This should only fail upon a hung GPU, in which case we
2891          * can safely continue.
2892          */
2893         dev_priv->mm.interruptible = false;
2894         ret = i915_gem_object_finish_gpu(obj);
2895         dev_priv->mm.interruptible = was_interruptible;
2896
2897         return ret;
2898 }
2899
2900 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2901 {
2902         struct drm_device *dev = crtc->dev;
2903         struct drm_i915_private *dev_priv = dev->dev_private;
2904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2905         bool pending;
2906
2907         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2908             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2909                 return false;
2910
2911         spin_lock_irq(&dev->event_lock);
2912         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2913         spin_unlock_irq(&dev->event_lock);
2914
2915         return pending;
2916 }
2917
2918 static void intel_update_pipe_size(struct intel_crtc *crtc)
2919 {
2920         struct drm_device *dev = crtc->base.dev;
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922         const struct drm_display_mode *adjusted_mode;
2923
2924         if (!i915.fastboot)
2925                 return;
2926
2927         /*
2928          * Update pipe size and adjust fitter if needed: the reason for this is
2929          * that in compute_mode_changes we check the native mode (not the pfit
2930          * mode) to see if we can flip rather than do a full mode set. In the
2931          * fastboot case, we'll flip, but if we don't update the pipesrc and
2932          * pfit state, we'll end up with a big fb scanned out into the wrong
2933          * sized surface.
2934          *
2935          * To fix this properly, we need to hoist the checks up into
2936          * compute_mode_changes (or above), check the actual pfit state and
2937          * whether the platform allows pfit disable with pipe active, and only
2938          * then update the pipesrc and pfit state, even on the flip path.
2939          */
2940
2941         adjusted_mode = &crtc->config.adjusted_mode;
2942
2943         I915_WRITE(PIPESRC(crtc->pipe),
2944                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2945                    (adjusted_mode->crtc_vdisplay - 1));
2946         if (!crtc->config.pch_pfit.enabled &&
2947             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2948              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2949                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2950                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2951                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2952         }
2953         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2954         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2955 }
2956
2957 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2958 {
2959         struct drm_device *dev = crtc->dev;
2960         struct drm_i915_private *dev_priv = dev->dev_private;
2961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2962         int pipe = intel_crtc->pipe;
2963         u32 reg, temp;
2964
2965         /* enable normal train */
2966         reg = FDI_TX_CTL(pipe);
2967         temp = I915_READ(reg);
2968         if (IS_IVYBRIDGE(dev)) {
2969                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2970                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2971         } else {
2972                 temp &= ~FDI_LINK_TRAIN_NONE;
2973                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2974         }
2975         I915_WRITE(reg, temp);
2976
2977         reg = FDI_RX_CTL(pipe);
2978         temp = I915_READ(reg);
2979         if (HAS_PCH_CPT(dev)) {
2980                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2981                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2982         } else {
2983                 temp &= ~FDI_LINK_TRAIN_NONE;
2984                 temp |= FDI_LINK_TRAIN_NONE;
2985         }
2986         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2987
2988         /* wait one idle pattern time */
2989         POSTING_READ(reg);
2990         udelay(1000);
2991
2992         /* IVB wants error correction enabled */
2993         if (IS_IVYBRIDGE(dev))
2994                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2995                            FDI_FE_ERRC_ENABLE);
2996 }
2997
2998 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2999 {
3000         return crtc->base.enabled && crtc->active &&
3001                 crtc->config.has_pch_encoder;
3002 }
3003
3004 static void ivb_modeset_global_resources(struct drm_device *dev)
3005 {
3006         struct drm_i915_private *dev_priv = dev->dev_private;
3007         struct intel_crtc *pipe_B_crtc =
3008                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3009         struct intel_crtc *pipe_C_crtc =
3010                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3011         uint32_t temp;
3012
3013         /*
3014          * When everything is off disable fdi C so that we could enable fdi B
3015          * with all lanes. Note that we don't care about enabled pipes without
3016          * an enabled pch encoder.
3017          */
3018         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3019             !pipe_has_enabled_pch(pipe_C_crtc)) {
3020                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3021                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3022
3023                 temp = I915_READ(SOUTH_CHICKEN1);
3024                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3025                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3026                 I915_WRITE(SOUTH_CHICKEN1, temp);
3027         }
3028 }
3029
3030 /* The FDI link training functions for ILK/Ibexpeak. */
3031 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3032 {
3033         struct drm_device *dev = crtc->dev;
3034         struct drm_i915_private *dev_priv = dev->dev_private;
3035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3036         int pipe = intel_crtc->pipe;
3037         u32 reg, temp, tries;
3038
3039         /* FDI needs bits from pipe first */
3040         assert_pipe_enabled(dev_priv, pipe);
3041
3042         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3043            for train result */
3044         reg = FDI_RX_IMR(pipe);
3045         temp = I915_READ(reg);
3046         temp &= ~FDI_RX_SYMBOL_LOCK;
3047         temp &= ~FDI_RX_BIT_LOCK;
3048         I915_WRITE(reg, temp);
3049         I915_READ(reg);
3050         udelay(150);
3051
3052         /* enable CPU FDI TX and PCH FDI RX */
3053         reg = FDI_TX_CTL(pipe);
3054         temp = I915_READ(reg);
3055         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3056         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3057         temp &= ~FDI_LINK_TRAIN_NONE;
3058         temp |= FDI_LINK_TRAIN_PATTERN_1;
3059         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3060
3061         reg = FDI_RX_CTL(pipe);
3062         temp = I915_READ(reg);
3063         temp &= ~FDI_LINK_TRAIN_NONE;
3064         temp |= FDI_LINK_TRAIN_PATTERN_1;
3065         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3066
3067         POSTING_READ(reg);
3068         udelay(150);
3069
3070         /* Ironlake workaround, enable clock pointer after FDI enable*/
3071         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3072         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3073                    FDI_RX_PHASE_SYNC_POINTER_EN);
3074
3075         reg = FDI_RX_IIR(pipe);
3076         for (tries = 0; tries < 5; tries++) {
3077                 temp = I915_READ(reg);
3078                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3079
3080                 if ((temp & FDI_RX_BIT_LOCK)) {
3081                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3082                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3083                         break;
3084                 }
3085         }
3086         if (tries == 5)
3087                 DRM_ERROR("FDI train 1 fail!\n");
3088
3089         /* Train 2 */
3090         reg = FDI_TX_CTL(pipe);
3091         temp = I915_READ(reg);
3092         temp &= ~FDI_LINK_TRAIN_NONE;
3093         temp |= FDI_LINK_TRAIN_PATTERN_2;
3094         I915_WRITE(reg, temp);
3095
3096         reg = FDI_RX_CTL(pipe);
3097         temp = I915_READ(reg);
3098         temp &= ~FDI_LINK_TRAIN_NONE;
3099         temp |= FDI_LINK_TRAIN_PATTERN_2;
3100         I915_WRITE(reg, temp);
3101
3102         POSTING_READ(reg);
3103         udelay(150);
3104
3105         reg = FDI_RX_IIR(pipe);
3106         for (tries = 0; tries < 5; tries++) {
3107                 temp = I915_READ(reg);
3108                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3109
3110                 if (temp & FDI_RX_SYMBOL_LOCK) {
3111                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3112                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3113                         break;
3114                 }
3115         }
3116         if (tries == 5)
3117                 DRM_ERROR("FDI train 2 fail!\n");
3118
3119         DRM_DEBUG_KMS("FDI train done\n");
3120
3121 }
3122
3123 static const int snb_b_fdi_train_param[] = {
3124         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3125         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3126         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3127         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3128 };
3129
3130 /* The FDI link training functions for SNB/Cougarpoint. */
3131 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3132 {
3133         struct drm_device *dev = crtc->dev;
3134         struct drm_i915_private *dev_priv = dev->dev_private;
3135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3136         int pipe = intel_crtc->pipe;
3137         u32 reg, temp, i, retry;
3138
3139         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3140            for train result */
3141         reg = FDI_RX_IMR(pipe);
3142         temp = I915_READ(reg);
3143         temp &= ~FDI_RX_SYMBOL_LOCK;
3144         temp &= ~FDI_RX_BIT_LOCK;
3145         I915_WRITE(reg, temp);
3146
3147         POSTING_READ(reg);
3148         udelay(150);
3149
3150         /* enable CPU FDI TX and PCH FDI RX */
3151         reg = FDI_TX_CTL(pipe);
3152         temp = I915_READ(reg);
3153         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3154         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3155         temp &= ~FDI_LINK_TRAIN_NONE;
3156         temp |= FDI_LINK_TRAIN_PATTERN_1;
3157         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3158         /* SNB-B */
3159         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3160         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3161
3162         I915_WRITE(FDI_RX_MISC(pipe),
3163                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3164
3165         reg = FDI_RX_CTL(pipe);
3166         temp = I915_READ(reg);
3167         if (HAS_PCH_CPT(dev)) {
3168                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3169                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3170         } else {
3171                 temp &= ~FDI_LINK_TRAIN_NONE;
3172                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3173         }
3174         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3175
3176         POSTING_READ(reg);
3177         udelay(150);
3178
3179         for (i = 0; i < 4; i++) {
3180                 reg = FDI_TX_CTL(pipe);
3181                 temp = I915_READ(reg);
3182                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3183                 temp |= snb_b_fdi_train_param[i];
3184                 I915_WRITE(reg, temp);
3185
3186                 POSTING_READ(reg);
3187                 udelay(500);
3188
3189                 for (retry = 0; retry < 5; retry++) {
3190                         reg = FDI_RX_IIR(pipe);
3191                         temp = I915_READ(reg);
3192                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3193                         if (temp & FDI_RX_BIT_LOCK) {
3194                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3195                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3196                                 break;
3197                         }
3198                         udelay(50);
3199                 }
3200                 if (retry < 5)
3201                         break;
3202         }
3203         if (i == 4)
3204                 DRM_ERROR("FDI train 1 fail!\n");
3205
3206         /* Train 2 */
3207         reg = FDI_TX_CTL(pipe);
3208         temp = I915_READ(reg);
3209         temp &= ~FDI_LINK_TRAIN_NONE;
3210         temp |= FDI_LINK_TRAIN_PATTERN_2;
3211         if (IS_GEN6(dev)) {
3212                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3213                 /* SNB-B */
3214                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3215         }
3216         I915_WRITE(reg, temp);
3217
3218         reg = FDI_RX_CTL(pipe);
3219         temp = I915_READ(reg);
3220         if (HAS_PCH_CPT(dev)) {
3221                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3222                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3223         } else {
3224                 temp &= ~FDI_LINK_TRAIN_NONE;
3225                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3226         }
3227         I915_WRITE(reg, temp);
3228
3229         POSTING_READ(reg);
3230         udelay(150);
3231
3232         for (i = 0; i < 4; i++) {
3233                 reg = FDI_TX_CTL(pipe);
3234                 temp = I915_READ(reg);
3235                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3236                 temp |= snb_b_fdi_train_param[i];
3237                 I915_WRITE(reg, temp);
3238
3239                 POSTING_READ(reg);
3240                 udelay(500);
3241
3242                 for (retry = 0; retry < 5; retry++) {
3243                         reg = FDI_RX_IIR(pipe);
3244                         temp = I915_READ(reg);
3245                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3246                         if (temp & FDI_RX_SYMBOL_LOCK) {
3247                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3248                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3249                                 break;
3250                         }
3251                         udelay(50);
3252                 }
3253                 if (retry < 5)
3254                         break;
3255         }
3256         if (i == 4)
3257                 DRM_ERROR("FDI train 2 fail!\n");
3258
3259         DRM_DEBUG_KMS("FDI train done.\n");
3260 }
3261
3262 /* Manual link training for Ivy Bridge A0 parts */
3263 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3264 {
3265         struct drm_device *dev = crtc->dev;
3266         struct drm_i915_private *dev_priv = dev->dev_private;
3267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3268         int pipe = intel_crtc->pipe;
3269         u32 reg, temp, i, j;
3270
3271         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3272            for train result */
3273         reg = FDI_RX_IMR(pipe);
3274         temp = I915_READ(reg);
3275         temp &= ~FDI_RX_SYMBOL_LOCK;
3276         temp &= ~FDI_RX_BIT_LOCK;
3277         I915_WRITE(reg, temp);
3278
3279         POSTING_READ(reg);
3280         udelay(150);
3281
3282         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3283                       I915_READ(FDI_RX_IIR(pipe)));
3284
3285         /* Try each vswing and preemphasis setting twice before moving on */
3286         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3287                 /* disable first in case we need to retry */
3288                 reg = FDI_TX_CTL(pipe);
3289                 temp = I915_READ(reg);
3290                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3291                 temp &= ~FDI_TX_ENABLE;
3292                 I915_WRITE(reg, temp);
3293
3294                 reg = FDI_RX_CTL(pipe);
3295                 temp = I915_READ(reg);
3296                 temp &= ~FDI_LINK_TRAIN_AUTO;
3297                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3298                 temp &= ~FDI_RX_ENABLE;
3299                 I915_WRITE(reg, temp);
3300
3301                 /* enable CPU FDI TX and PCH FDI RX */
3302                 reg = FDI_TX_CTL(pipe);
3303                 temp = I915_READ(reg);
3304                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3305                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3306                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3307                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3308                 temp |= snb_b_fdi_train_param[j/2];
3309                 temp |= FDI_COMPOSITE_SYNC;
3310                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3311
3312                 I915_WRITE(FDI_RX_MISC(pipe),
3313                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3314
3315                 reg = FDI_RX_CTL(pipe);
3316                 temp = I915_READ(reg);
3317                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3318                 temp |= FDI_COMPOSITE_SYNC;
3319                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3320
3321                 POSTING_READ(reg);
3322                 udelay(1); /* should be 0.5us */
3323
3324                 for (i = 0; i < 4; i++) {
3325                         reg = FDI_RX_IIR(pipe);
3326                         temp = I915_READ(reg);
3327                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3328
3329                         if (temp & FDI_RX_BIT_LOCK ||
3330                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3331                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3332                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3333                                               i);
3334                                 break;
3335                         }
3336                         udelay(1); /* should be 0.5us */
3337                 }
3338                 if (i == 4) {
3339                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3340                         continue;
3341                 }
3342
3343                 /* Train 2 */
3344                 reg = FDI_TX_CTL(pipe);
3345                 temp = I915_READ(reg);
3346                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3347                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3348                 I915_WRITE(reg, temp);
3349
3350                 reg = FDI_RX_CTL(pipe);
3351                 temp = I915_READ(reg);
3352                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3353                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3354                 I915_WRITE(reg, temp);
3355
3356                 POSTING_READ(reg);
3357                 udelay(2); /* should be 1.5us */
3358
3359                 for (i = 0; i < 4; i++) {
3360                         reg = FDI_RX_IIR(pipe);
3361                         temp = I915_READ(reg);
3362                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3363
3364                         if (temp & FDI_RX_SYMBOL_LOCK ||
3365                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3366                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3367                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3368                                               i);
3369                                 goto train_done;
3370                         }
3371                         udelay(2); /* should be 1.5us */
3372                 }
3373                 if (i == 4)
3374                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3375         }
3376
3377 train_done:
3378         DRM_DEBUG_KMS("FDI train done.\n");
3379 }
3380
3381 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3382 {
3383         struct drm_device *dev = intel_crtc->base.dev;
3384         struct drm_i915_private *dev_priv = dev->dev_private;
3385         int pipe = intel_crtc->pipe;
3386         u32 reg, temp;
3387
3388
3389         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3390         reg = FDI_RX_CTL(pipe);
3391         temp = I915_READ(reg);
3392         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3393         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3394         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3395         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3396
3397         POSTING_READ(reg);
3398         udelay(200);
3399
3400         /* Switch from Rawclk to PCDclk */
3401         temp = I915_READ(reg);
3402         I915_WRITE(reg, temp | FDI_PCDCLK);
3403
3404         POSTING_READ(reg);
3405         udelay(200);
3406
3407         /* Enable CPU FDI TX PLL, always on for Ironlake */
3408         reg = FDI_TX_CTL(pipe);
3409         temp = I915_READ(reg);
3410         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3411                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3412
3413                 POSTING_READ(reg);
3414                 udelay(100);
3415         }
3416 }
3417
3418 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3419 {
3420         struct drm_device *dev = intel_crtc->base.dev;
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         int pipe = intel_crtc->pipe;
3423         u32 reg, temp;
3424
3425         /* Switch from PCDclk to Rawclk */
3426         reg = FDI_RX_CTL(pipe);
3427         temp = I915_READ(reg);
3428         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3429
3430         /* Disable CPU FDI TX PLL */
3431         reg = FDI_TX_CTL(pipe);
3432         temp = I915_READ(reg);
3433         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3434
3435         POSTING_READ(reg);
3436         udelay(100);
3437
3438         reg = FDI_RX_CTL(pipe);
3439         temp = I915_READ(reg);
3440         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3441
3442         /* Wait for the clocks to turn off. */
3443         POSTING_READ(reg);
3444         udelay(100);
3445 }
3446
3447 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3448 {
3449         struct drm_device *dev = crtc->dev;
3450         struct drm_i915_private *dev_priv = dev->dev_private;
3451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3452         int pipe = intel_crtc->pipe;
3453         u32 reg, temp;
3454
3455         /* disable CPU FDI tx and PCH FDI rx */
3456         reg = FDI_TX_CTL(pipe);
3457         temp = I915_READ(reg);
3458         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3459         POSTING_READ(reg);
3460
3461         reg = FDI_RX_CTL(pipe);
3462         temp = I915_READ(reg);
3463         temp &= ~(0x7 << 16);
3464         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3465         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3466
3467         POSTING_READ(reg);
3468         udelay(100);
3469
3470         /* Ironlake workaround, disable clock pointer after downing FDI */
3471         if (HAS_PCH_IBX(dev))
3472                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3473
3474         /* still set train pattern 1 */
3475         reg = FDI_TX_CTL(pipe);
3476         temp = I915_READ(reg);
3477         temp &= ~FDI_LINK_TRAIN_NONE;
3478         temp |= FDI_LINK_TRAIN_PATTERN_1;
3479         I915_WRITE(reg, temp);
3480
3481         reg = FDI_RX_CTL(pipe);
3482         temp = I915_READ(reg);
3483         if (HAS_PCH_CPT(dev)) {
3484                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3485                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3486         } else {
3487                 temp &= ~FDI_LINK_TRAIN_NONE;
3488                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3489         }
3490         /* BPC in FDI rx is consistent with that in PIPECONF */
3491         temp &= ~(0x07 << 16);
3492         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3493         I915_WRITE(reg, temp);
3494
3495         POSTING_READ(reg);
3496         udelay(100);
3497 }
3498
3499 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3500 {
3501         struct intel_crtc *crtc;
3502
3503         /* Note that we don't need to be called with mode_config.lock here
3504          * as our list of CRTC objects is static for the lifetime of the
3505          * device and so cannot disappear as we iterate. Similarly, we can
3506          * happily treat the predicates as racy, atomic checks as userspace
3507          * cannot claim and pin a new fb without at least acquring the
3508          * struct_mutex and so serialising with us.
3509          */
3510         for_each_intel_crtc(dev, crtc) {
3511                 if (atomic_read(&crtc->unpin_work_count) == 0)
3512                         continue;
3513
3514                 if (crtc->unpin_work)
3515                         intel_wait_for_vblank(dev, crtc->pipe);
3516
3517                 return true;
3518         }
3519
3520         return false;
3521 }
3522
3523 static void page_flip_completed(struct intel_crtc *intel_crtc)
3524 {
3525         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3526         struct intel_unpin_work *work = intel_crtc->unpin_work;
3527
3528         /* ensure that the unpin work is consistent wrt ->pending. */
3529         smp_rmb();
3530         intel_crtc->unpin_work = NULL;
3531
3532         if (work->event)
3533                 drm_send_vblank_event(intel_crtc->base.dev,
3534                                       intel_crtc->pipe,
3535                                       work->event);
3536
3537         drm_crtc_vblank_put(&intel_crtc->base);
3538
3539         wake_up_all(&dev_priv->pending_flip_queue);
3540         queue_work(dev_priv->wq, &work->work);
3541
3542         trace_i915_flip_complete(intel_crtc->plane,
3543                                  work->pending_flip_obj);
3544 }
3545
3546 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3547 {
3548         struct drm_device *dev = crtc->dev;
3549         struct drm_i915_private *dev_priv = dev->dev_private;
3550
3551         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3552         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3553                                        !intel_crtc_has_pending_flip(crtc),
3554                                        60*HZ) == 0)) {
3555                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3556
3557                 spin_lock_irq(&dev->event_lock);
3558                 if (intel_crtc->unpin_work) {
3559                         WARN_ONCE(1, "Removing stuck page flip\n");
3560                         page_flip_completed(intel_crtc);
3561                 }
3562                 spin_unlock_irq(&dev->event_lock);
3563         }
3564
3565         if (crtc->primary->fb) {
3566                 mutex_lock(&dev->struct_mutex);
3567                 intel_finish_fb(crtc->primary->fb);
3568                 mutex_unlock(&dev->struct_mutex);
3569         }
3570 }
3571
3572 /* Program iCLKIP clock to the desired frequency */
3573 static void lpt_program_iclkip(struct drm_crtc *crtc)
3574 {
3575         struct drm_device *dev = crtc->dev;
3576         struct drm_i915_private *dev_priv = dev->dev_private;
3577         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3578         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3579         u32 temp;
3580
3581         mutex_lock(&dev_priv->dpio_lock);
3582
3583         /* It is necessary to ungate the pixclk gate prior to programming
3584          * the divisors, and gate it back when it is done.
3585          */
3586         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3587
3588         /* Disable SSCCTL */
3589         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3590                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3591                                 SBI_SSCCTL_DISABLE,
3592                         SBI_ICLK);
3593
3594         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3595         if (clock == 20000) {
3596                 auxdiv = 1;
3597                 divsel = 0x41;
3598                 phaseinc = 0x20;
3599         } else {
3600                 /* The iCLK virtual clock root frequency is in MHz,
3601                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3602                  * divisors, it is necessary to divide one by another, so we
3603                  * convert the virtual clock precision to KHz here for higher
3604                  * precision.
3605                  */
3606                 u32 iclk_virtual_root_freq = 172800 * 1000;
3607                 u32 iclk_pi_range = 64;
3608                 u32 desired_divisor, msb_divisor_value, pi_value;
3609
3610                 desired_divisor = (iclk_virtual_root_freq / clock);
3611                 msb_divisor_value = desired_divisor / iclk_pi_range;
3612                 pi_value = desired_divisor % iclk_pi_range;
3613
3614                 auxdiv = 0;
3615                 divsel = msb_divisor_value - 2;
3616                 phaseinc = pi_value;
3617         }
3618
3619         /* This should not happen with any sane values */
3620         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3621                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3622         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3623                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3624
3625         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3626                         clock,
3627                         auxdiv,
3628                         divsel,
3629                         phasedir,
3630                         phaseinc);
3631
3632         /* Program SSCDIVINTPHASE6 */
3633         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3634         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3635         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3636         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3637         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3638         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3639         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3640         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3641
3642         /* Program SSCAUXDIV */
3643         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3644         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3645         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3646         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3647
3648         /* Enable modulator and associated divider */
3649         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3650         temp &= ~SBI_SSCCTL_DISABLE;
3651         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3652
3653         /* Wait for initialization time */
3654         udelay(24);
3655
3656         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3657
3658         mutex_unlock(&dev_priv->dpio_lock);
3659 }
3660
3661 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3662                                                 enum pipe pch_transcoder)
3663 {
3664         struct drm_device *dev = crtc->base.dev;
3665         struct drm_i915_private *dev_priv = dev->dev_private;
3666         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3667
3668         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3669                    I915_READ(HTOTAL(cpu_transcoder)));
3670         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3671                    I915_READ(HBLANK(cpu_transcoder)));
3672         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3673                    I915_READ(HSYNC(cpu_transcoder)));
3674
3675         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3676                    I915_READ(VTOTAL(cpu_transcoder)));
3677         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3678                    I915_READ(VBLANK(cpu_transcoder)));
3679         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3680                    I915_READ(VSYNC(cpu_transcoder)));
3681         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3682                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3683 }
3684
3685 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3686 {
3687         struct drm_i915_private *dev_priv = dev->dev_private;
3688         uint32_t temp;
3689
3690         temp = I915_READ(SOUTH_CHICKEN1);
3691         if (temp & FDI_BC_BIFURCATION_SELECT)
3692                 return;
3693
3694         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3695         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3696
3697         temp |= FDI_BC_BIFURCATION_SELECT;
3698         DRM_DEBUG_KMS("enabling fdi C rx\n");
3699         I915_WRITE(SOUTH_CHICKEN1, temp);
3700         POSTING_READ(SOUTH_CHICKEN1);
3701 }
3702
3703 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3704 {
3705         struct drm_device *dev = intel_crtc->base.dev;
3706         struct drm_i915_private *dev_priv = dev->dev_private;
3707
3708         switch (intel_crtc->pipe) {
3709         case PIPE_A:
3710                 break;
3711         case PIPE_B:
3712                 if (intel_crtc->config.fdi_lanes > 2)
3713                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3714                 else
3715                         cpt_enable_fdi_bc_bifurcation(dev);
3716
3717                 break;
3718         case PIPE_C:
3719                 cpt_enable_fdi_bc_bifurcation(dev);
3720
3721                 break;
3722         default:
3723                 BUG();
3724         }
3725 }
3726
3727 /*
3728  * Enable PCH resources required for PCH ports:
3729  *   - PCH PLLs
3730  *   - FDI training & RX/TX
3731  *   - update transcoder timings
3732  *   - DP transcoding bits
3733  *   - transcoder
3734  */
3735 static void ironlake_pch_enable(struct drm_crtc *crtc)
3736 {
3737         struct drm_device *dev = crtc->dev;
3738         struct drm_i915_private *dev_priv = dev->dev_private;
3739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740         int pipe = intel_crtc->pipe;
3741         u32 reg, temp;
3742
3743         assert_pch_transcoder_disabled(dev_priv, pipe);
3744
3745         if (IS_IVYBRIDGE(dev))
3746                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3747
3748         /* Write the TU size bits before fdi link training, so that error
3749          * detection works. */
3750         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3751                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3752
3753         /* For PCH output, training FDI link */
3754         dev_priv->display.fdi_link_train(crtc);
3755
3756         /* We need to program the right clock selection before writing the pixel
3757          * mutliplier into the DPLL. */
3758         if (HAS_PCH_CPT(dev)) {
3759                 u32 sel;
3760
3761                 temp = I915_READ(PCH_DPLL_SEL);
3762                 temp |= TRANS_DPLL_ENABLE(pipe);
3763                 sel = TRANS_DPLLB_SEL(pipe);
3764                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3765                         temp |= sel;
3766                 else
3767                         temp &= ~sel;
3768                 I915_WRITE(PCH_DPLL_SEL, temp);
3769         }
3770
3771         /* XXX: pch pll's can be enabled any time before we enable the PCH
3772          * transcoder, and we actually should do this to not upset any PCH
3773          * transcoder that already use the clock when we share it.
3774          *
3775          * Note that enable_shared_dpll tries to do the right thing, but
3776          * get_shared_dpll unconditionally resets the pll - we need that to have
3777          * the right LVDS enable sequence. */
3778         intel_enable_shared_dpll(intel_crtc);
3779
3780         /* set transcoder timing, panel must allow it */
3781         assert_panel_unlocked(dev_priv, pipe);
3782         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3783
3784         intel_fdi_normal_train(crtc);
3785
3786         /* For PCH DP, enable TRANS_DP_CTL */
3787         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3788                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3789                 reg = TRANS_DP_CTL(pipe);
3790                 temp = I915_READ(reg);
3791                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3792                           TRANS_DP_SYNC_MASK |
3793                           TRANS_DP_BPC_MASK);
3794                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3795                          TRANS_DP_ENH_FRAMING);
3796                 temp |= bpc << 9; /* same format but at 11:9 */
3797
3798                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3799                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3800                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3801                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3802
3803                 switch (intel_trans_dp_port_sel(crtc)) {
3804                 case PCH_DP_B:
3805                         temp |= TRANS_DP_PORT_SEL_B;
3806                         break;
3807                 case PCH_DP_C:
3808                         temp |= TRANS_DP_PORT_SEL_C;
3809                         break;
3810                 case PCH_DP_D:
3811                         temp |= TRANS_DP_PORT_SEL_D;
3812                         break;
3813                 default:
3814                         BUG();
3815                 }
3816
3817                 I915_WRITE(reg, temp);
3818         }
3819
3820         ironlake_enable_pch_transcoder(dev_priv, pipe);
3821 }
3822
3823 static void lpt_pch_enable(struct drm_crtc *crtc)
3824 {
3825         struct drm_device *dev = crtc->dev;
3826         struct drm_i915_private *dev_priv = dev->dev_private;
3827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3828         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3829
3830         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3831
3832         lpt_program_iclkip(crtc);
3833
3834         /* Set transcoder timing. */
3835         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3836
3837         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3838 }
3839
3840 void intel_put_shared_dpll(struct intel_crtc *crtc)
3841 {
3842         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3843
3844         if (pll == NULL)
3845                 return;
3846
3847         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3848                 WARN(1, "bad %s crtc mask\n", pll->name);
3849                 return;
3850         }
3851
3852         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3853         if (pll->config.crtc_mask == 0) {
3854                 WARN_ON(pll->on);
3855                 WARN_ON(pll->active);
3856         }
3857
3858         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3859 }
3860
3861 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3862 {
3863         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3864         struct intel_shared_dpll *pll;
3865         enum intel_dpll_id i;
3866
3867         if (HAS_PCH_IBX(dev_priv->dev)) {
3868                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3869                 i = (enum intel_dpll_id) crtc->pipe;
3870                 pll = &dev_priv->shared_dplls[i];
3871
3872                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3873                               crtc->base.base.id, pll->name);
3874
3875                 WARN_ON(pll->new_config->crtc_mask);
3876
3877                 goto found;
3878         }
3879
3880         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3881                 pll = &dev_priv->shared_dplls[i];
3882
3883                 /* Only want to check enabled timings first */
3884                 if (pll->new_config->crtc_mask == 0)
3885                         continue;
3886
3887                 if (memcmp(&crtc->new_config->dpll_hw_state,
3888                            &pll->new_config->hw_state,
3889                            sizeof(pll->new_config->hw_state)) == 0) {
3890                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3891                                       crtc->base.base.id, pll->name,
3892                                       pll->new_config->crtc_mask,
3893                                       pll->active);
3894                         goto found;
3895                 }
3896         }
3897
3898         /* Ok no matching timings, maybe there's a free one? */
3899         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3900                 pll = &dev_priv->shared_dplls[i];
3901                 if (pll->new_config->crtc_mask == 0) {
3902                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3903                                       crtc->base.base.id, pll->name);
3904                         goto found;
3905                 }
3906         }
3907
3908         return NULL;
3909
3910 found:
3911         if (pll->new_config->crtc_mask == 0)
3912                 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3913
3914         crtc->new_config->shared_dpll = i;
3915         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3916                          pipe_name(crtc->pipe));
3917
3918         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3919
3920         return pll;
3921 }
3922
3923 /**
3924  * intel_shared_dpll_start_config - start a new PLL staged config
3925  * @dev_priv: DRM device
3926  * @clear_pipes: mask of pipes that will have their PLLs freed
3927  *
3928  * Starts a new PLL staged config, copying the current config but
3929  * releasing the references of pipes specified in clear_pipes.
3930  */
3931 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3932                                           unsigned clear_pipes)
3933 {
3934         struct intel_shared_dpll *pll;
3935         enum intel_dpll_id i;
3936
3937         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3938                 pll = &dev_priv->shared_dplls[i];
3939
3940                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3941                                           GFP_KERNEL);
3942                 if (!pll->new_config)
3943                         goto cleanup;
3944
3945                 pll->new_config->crtc_mask &= ~clear_pipes;
3946         }
3947
3948         return 0;
3949
3950 cleanup:
3951         while (--i >= 0) {
3952                 pll = &dev_priv->shared_dplls[i];
3953                 kfree(pll->new_config);
3954                 pll->new_config = NULL;
3955         }
3956
3957         return -ENOMEM;
3958 }
3959
3960 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3961 {
3962         struct intel_shared_dpll *pll;
3963         enum intel_dpll_id i;
3964
3965         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3966                 pll = &dev_priv->shared_dplls[i];
3967
3968                 WARN_ON(pll->new_config == &pll->config);
3969
3970                 pll->config = *pll->new_config;
3971                 kfree(pll->new_config);
3972                 pll->new_config = NULL;
3973         }
3974 }
3975
3976 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3977 {
3978         struct intel_shared_dpll *pll;
3979         enum intel_dpll_id i;
3980
3981         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3982                 pll = &dev_priv->shared_dplls[i];
3983
3984                 WARN_ON(pll->new_config == &pll->config);
3985
3986                 kfree(pll->new_config);
3987                 pll->new_config = NULL;
3988         }
3989 }
3990
3991 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3992 {
3993         struct drm_i915_private *dev_priv = dev->dev_private;
3994         int dslreg = PIPEDSL(pipe);
3995         u32 temp;
3996
3997         temp = I915_READ(dslreg);
3998         udelay(500);
3999         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4000                 if (wait_for(I915_READ(dslreg) != temp, 5))
4001                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4002         }
4003 }
4004
4005 static void skylake_pfit_enable(struct intel_crtc *crtc)
4006 {
4007         struct drm_device *dev = crtc->base.dev;
4008         struct drm_i915_private *dev_priv = dev->dev_private;
4009         int pipe = crtc->pipe;
4010
4011         if (crtc->config.pch_pfit.enabled) {
4012                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4013                 I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4014                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4015         }
4016 }
4017
4018 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4019 {
4020         struct drm_device *dev = crtc->base.dev;
4021         struct drm_i915_private *dev_priv = dev->dev_private;
4022         int pipe = crtc->pipe;
4023
4024         if (crtc->config.pch_pfit.enabled) {
4025                 /* Force use of hard-coded filter coefficients
4026                  * as some pre-programmed values are broken,
4027                  * e.g. x201.
4028                  */
4029                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4030                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4031                                                  PF_PIPE_SEL_IVB(pipe));
4032                 else
4033                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4034                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4035                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4036         }
4037 }
4038
4039 static void intel_enable_planes(struct drm_crtc *crtc)
4040 {
4041         struct drm_device *dev = crtc->dev;
4042         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4043         struct drm_plane *plane;
4044         struct intel_plane *intel_plane;
4045
4046         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4047                 intel_plane = to_intel_plane(plane);
4048                 if (intel_plane->pipe == pipe)
4049                         intel_plane_restore(&intel_plane->base);
4050         }
4051 }
4052
4053 static void intel_disable_planes(struct drm_crtc *crtc)
4054 {
4055         struct drm_device *dev = crtc->dev;
4056         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4057         struct drm_plane *plane;
4058         struct intel_plane *intel_plane;
4059
4060         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4061                 intel_plane = to_intel_plane(plane);
4062                 if (intel_plane->pipe == pipe)
4063                         plane->funcs->disable_plane(plane);
4064         }
4065 }
4066
4067 void hsw_enable_ips(struct intel_crtc *crtc)
4068 {
4069         struct drm_device *dev = crtc->base.dev;
4070         struct drm_i915_private *dev_priv = dev->dev_private;
4071
4072         if (!crtc->config.ips_enabled)
4073                 return;
4074
4075         /* We can only enable IPS after we enable a plane and wait for a vblank */
4076         intel_wait_for_vblank(dev, crtc->pipe);
4077
4078         assert_plane_enabled(dev_priv, crtc->plane);
4079         if (IS_BROADWELL(dev)) {
4080                 mutex_lock(&dev_priv->rps.hw_lock);
4081                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4082                 mutex_unlock(&dev_priv->rps.hw_lock);
4083                 /* Quoting Art Runyan: "its not safe to expect any particular
4084                  * value in IPS_CTL bit 31 after enabling IPS through the
4085                  * mailbox." Moreover, the mailbox may return a bogus state,
4086                  * so we need to just enable it and continue on.
4087                  */
4088         } else {
4089                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4090                 /* The bit only becomes 1 in the next vblank, so this wait here
4091                  * is essentially intel_wait_for_vblank. If we don't have this
4092                  * and don't wait for vblanks until the end of crtc_enable, then
4093                  * the HW state readout code will complain that the expected
4094                  * IPS_CTL value is not the one we read. */
4095                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4096                         DRM_ERROR("Timed out waiting for IPS enable\n");
4097         }
4098 }
4099
4100 void hsw_disable_ips(struct intel_crtc *crtc)
4101 {
4102         struct drm_device *dev = crtc->base.dev;
4103         struct drm_i915_private *dev_priv = dev->dev_private;
4104
4105         if (!crtc->config.ips_enabled)
4106                 return;
4107
4108         assert_plane_enabled(dev_priv, crtc->plane);
4109         if (IS_BROADWELL(dev)) {
4110                 mutex_lock(&dev_priv->rps.hw_lock);
4111                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4112                 mutex_unlock(&dev_priv->rps.hw_lock);
4113                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4114                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4115                         DRM_ERROR("Timed out waiting for IPS disable\n");
4116         } else {
4117                 I915_WRITE(IPS_CTL, 0);
4118                 POSTING_READ(IPS_CTL);
4119         }
4120
4121         /* We need to wait for a vblank before we can disable the plane. */
4122         intel_wait_for_vblank(dev, crtc->pipe);
4123 }
4124
4125 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4126 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4127 {
4128         struct drm_device *dev = crtc->dev;
4129         struct drm_i915_private *dev_priv = dev->dev_private;
4130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4131         enum pipe pipe = intel_crtc->pipe;
4132         int palreg = PALETTE(pipe);
4133         int i;
4134         bool reenable_ips = false;
4135
4136         /* The clocks have to be on to load the palette. */
4137         if (!crtc->enabled || !intel_crtc->active)
4138                 return;
4139
4140         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4141                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4142                         assert_dsi_pll_enabled(dev_priv);
4143                 else
4144                         assert_pll_enabled(dev_priv, pipe);
4145         }
4146
4147         /* use legacy palette for Ironlake */
4148         if (!HAS_GMCH_DISPLAY(dev))
4149                 palreg = LGC_PALETTE(pipe);
4150
4151         /* Workaround : Do not read or write the pipe palette/gamma data while
4152          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4153          */
4154         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4155             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4156              GAMMA_MODE_MODE_SPLIT)) {
4157                 hsw_disable_ips(intel_crtc);
4158                 reenable_ips = true;
4159         }
4160
4161         for (i = 0; i < 256; i++) {
4162                 I915_WRITE(palreg + 4 * i,
4163                            (intel_crtc->lut_r[i] << 16) |
4164                            (intel_crtc->lut_g[i] << 8) |
4165                            intel_crtc->lut_b[i]);
4166         }
4167
4168         if (reenable_ips)
4169                 hsw_enable_ips(intel_crtc);
4170 }
4171
4172 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4173 {
4174         if (!enable && intel_crtc->overlay) {
4175                 struct drm_device *dev = intel_crtc->base.dev;
4176                 struct drm_i915_private *dev_priv = dev->dev_private;
4177
4178                 mutex_lock(&dev->struct_mutex);
4179                 dev_priv->mm.interruptible = false;
4180                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4181                 dev_priv->mm.interruptible = true;
4182                 mutex_unlock(&dev->struct_mutex);
4183         }
4184
4185         /* Let userspace switch the overlay on again. In most cases userspace
4186          * has to recompute where to put it anyway.
4187          */
4188 }
4189
4190 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4191 {
4192         struct drm_device *dev = crtc->dev;
4193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4194         int pipe = intel_crtc->pipe;
4195
4196         intel_enable_primary_hw_plane(crtc->primary, crtc);
4197         intel_enable_planes(crtc);
4198         intel_crtc_update_cursor(crtc, true);
4199         intel_crtc_dpms_overlay(intel_crtc, true);
4200
4201         hsw_enable_ips(intel_crtc);
4202
4203         mutex_lock(&dev->struct_mutex);
4204         intel_fbc_update(dev);
4205         mutex_unlock(&dev->struct_mutex);
4206
4207         /*
4208          * FIXME: Once we grow proper nuclear flip support out of this we need
4209          * to compute the mask of flip planes precisely. For the time being
4210          * consider this a flip from a NULL plane.
4211          */
4212         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4213 }
4214
4215 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4216 {
4217         struct drm_device *dev = crtc->dev;
4218         struct drm_i915_private *dev_priv = dev->dev_private;
4219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220         int pipe = intel_crtc->pipe;
4221         int plane = intel_crtc->plane;
4222
4223         intel_crtc_wait_for_pending_flips(crtc);
4224
4225         if (dev_priv->fbc.plane == plane)
4226                 intel_fbc_disable(dev);
4227
4228         hsw_disable_ips(intel_crtc);
4229
4230         intel_crtc_dpms_overlay(intel_crtc, false);
4231         intel_crtc_update_cursor(crtc, false);
4232         intel_disable_planes(crtc);
4233         intel_disable_primary_hw_plane(crtc->primary, crtc);
4234
4235         /*
4236          * FIXME: Once we grow proper nuclear flip support out of this we need
4237          * to compute the mask of flip planes precisely. For the time being
4238          * consider this a flip to a NULL plane.
4239          */
4240         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4241 }
4242
4243 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4244 {
4245         struct drm_device *dev = crtc->dev;
4246         struct drm_i915_private *dev_priv = dev->dev_private;
4247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4248         struct intel_encoder *encoder;
4249         int pipe = intel_crtc->pipe;
4250
4251         WARN_ON(!crtc->enabled);
4252
4253         if (intel_crtc->active)
4254                 return;
4255
4256         if (intel_crtc->config.has_pch_encoder)
4257                 intel_prepare_shared_dpll(intel_crtc);
4258
4259         if (intel_crtc->config.has_dp_encoder)
4260                 intel_dp_set_m_n(intel_crtc);
4261
4262         intel_set_pipe_timings(intel_crtc);
4263
4264         if (intel_crtc->config.has_pch_encoder) {
4265                 intel_cpu_transcoder_set_m_n(intel_crtc,
4266                                      &intel_crtc->config.fdi_m_n, NULL);
4267         }
4268
4269         ironlake_set_pipeconf(crtc);
4270
4271         intel_crtc->active = true;
4272
4273         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4274         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4275
4276         for_each_encoder_on_crtc(dev, crtc, encoder)
4277                 if (encoder->pre_enable)
4278                         encoder->pre_enable(encoder);
4279
4280         if (intel_crtc->config.has_pch_encoder) {
4281                 /* Note: FDI PLL enabling _must_ be done before we enable the
4282                  * cpu pipes, hence this is separate from all the other fdi/pch
4283                  * enabling. */
4284                 ironlake_fdi_pll_enable(intel_crtc);
4285         } else {
4286                 assert_fdi_tx_disabled(dev_priv, pipe);
4287                 assert_fdi_rx_disabled(dev_priv, pipe);
4288         }
4289
4290         ironlake_pfit_enable(intel_crtc);
4291
4292         /*
4293          * On ILK+ LUT must be loaded before the pipe is running but with
4294          * clocks enabled
4295          */
4296         intel_crtc_load_lut(crtc);
4297
4298         intel_update_watermarks(crtc);
4299         intel_enable_pipe(intel_crtc);
4300
4301         if (intel_crtc->config.has_pch_encoder)
4302                 ironlake_pch_enable(crtc);
4303
4304         for_each_encoder_on_crtc(dev, crtc, encoder)
4305                 encoder->enable(encoder);
4306
4307         if (HAS_PCH_CPT(dev))
4308                 cpt_verify_modeset(dev, intel_crtc->pipe);
4309
4310         assert_vblank_disabled(crtc);
4311         drm_crtc_vblank_on(crtc);
4312
4313         intel_crtc_enable_planes(crtc);
4314 }
4315
4316 /* IPS only exists on ULT machines and is tied to pipe A. */
4317 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4318 {
4319         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4320 }
4321
4322 /*
4323  * This implements the workaround described in the "notes" section of the mode
4324  * set sequence documentation. When going from no pipes or single pipe to
4325  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4326  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4327  */
4328 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4329 {
4330         struct drm_device *dev = crtc->base.dev;
4331         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4332
4333         /* We want to get the other_active_crtc only if there's only 1 other
4334          * active crtc. */
4335         for_each_intel_crtc(dev, crtc_it) {
4336                 if (!crtc_it->active || crtc_it == crtc)
4337                         continue;
4338
4339                 if (other_active_crtc)
4340                         return;
4341
4342                 other_active_crtc = crtc_it;
4343         }
4344         if (!other_active_crtc)
4345                 return;
4346
4347         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4348         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4349 }
4350
4351 static void haswell_crtc_enable(struct drm_crtc *crtc)
4352 {
4353         struct drm_device *dev = crtc->dev;
4354         struct drm_i915_private *dev_priv = dev->dev_private;
4355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4356         struct intel_encoder *encoder;
4357         int pipe = intel_crtc->pipe;
4358
4359         WARN_ON(!crtc->enabled);
4360
4361         if (intel_crtc->active)
4362                 return;
4363
4364         if (intel_crtc_to_shared_dpll(intel_crtc))
4365                 intel_enable_shared_dpll(intel_crtc);
4366
4367         if (intel_crtc->config.has_dp_encoder)
4368                 intel_dp_set_m_n(intel_crtc);
4369
4370         intel_set_pipe_timings(intel_crtc);
4371
4372         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4373                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4374                            intel_crtc->config.pixel_multiplier - 1);
4375         }
4376
4377         if (intel_crtc->config.has_pch_encoder) {
4378                 intel_cpu_transcoder_set_m_n(intel_crtc,
4379                                      &intel_crtc->config.fdi_m_n, NULL);
4380         }
4381
4382         haswell_set_pipeconf(crtc);
4383
4384         intel_set_pipe_csc(crtc);
4385
4386         intel_crtc->active = true;
4387
4388         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4389         for_each_encoder_on_crtc(dev, crtc, encoder)
4390                 if (encoder->pre_enable)
4391                         encoder->pre_enable(encoder);
4392
4393         if (intel_crtc->config.has_pch_encoder) {
4394                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4395                                                       true);
4396                 dev_priv->display.fdi_link_train(crtc);
4397         }
4398
4399         intel_ddi_enable_pipe_clock(intel_crtc);
4400
4401         if (IS_SKYLAKE(dev))
4402                 skylake_pfit_enable(intel_crtc);
4403         else
4404                 ironlake_pfit_enable(intel_crtc);
4405
4406         /*
4407          * On ILK+ LUT must be loaded before the pipe is running but with
4408          * clocks enabled
4409          */
4410         intel_crtc_load_lut(crtc);
4411
4412         intel_ddi_set_pipe_settings(crtc);
4413         intel_ddi_enable_transcoder_func(crtc);
4414
4415         intel_update_watermarks(crtc);
4416         intel_enable_pipe(intel_crtc);
4417
4418         if (intel_crtc->config.has_pch_encoder)
4419                 lpt_pch_enable(crtc);
4420
4421         if (intel_crtc->config.dp_encoder_is_mst)
4422                 intel_ddi_set_vc_payload_alloc(crtc, true);
4423
4424         for_each_encoder_on_crtc(dev, crtc, encoder) {
4425                 encoder->enable(encoder);
4426                 intel_opregion_notify_encoder(encoder, true);
4427         }
4428
4429         assert_vblank_disabled(crtc);
4430         drm_crtc_vblank_on(crtc);
4431
4432         /* If we change the relative order between pipe/planes enabling, we need
4433          * to change the workaround. */
4434         haswell_mode_set_planes_workaround(intel_crtc);
4435         intel_crtc_enable_planes(crtc);
4436 }
4437
4438 static void skylake_pfit_disable(struct intel_crtc *crtc)
4439 {
4440         struct drm_device *dev = crtc->base.dev;
4441         struct drm_i915_private *dev_priv = dev->dev_private;
4442         int pipe = crtc->pipe;
4443
4444         /* To avoid upsetting the power well on haswell only disable the pfit if
4445          * it's in use. The hw state code will make sure we get this right. */
4446         if (crtc->config.pch_pfit.enabled) {
4447                 I915_WRITE(PS_CTL(pipe), 0);
4448                 I915_WRITE(PS_WIN_POS(pipe), 0);
4449                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4450         }
4451 }
4452
4453 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4454 {
4455         struct drm_device *dev = crtc->base.dev;
4456         struct drm_i915_private *dev_priv = dev->dev_private;
4457         int pipe = crtc->pipe;
4458
4459         /* To avoid upsetting the power well on haswell only disable the pfit if
4460          * it's in use. The hw state code will make sure we get this right. */
4461         if (crtc->config.pch_pfit.enabled) {
4462                 I915_WRITE(PF_CTL(pipe), 0);
4463                 I915_WRITE(PF_WIN_POS(pipe), 0);
4464                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4465         }
4466 }
4467
4468 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4469 {
4470         struct drm_device *dev = crtc->dev;
4471         struct drm_i915_private *dev_priv = dev->dev_private;
4472         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4473         struct intel_encoder *encoder;
4474         int pipe = intel_crtc->pipe;
4475         u32 reg, temp;
4476
4477         if (!intel_crtc->active)
4478                 return;
4479
4480         intel_crtc_disable_planes(crtc);
4481
4482         drm_crtc_vblank_off(crtc);
4483         assert_vblank_disabled(crtc);
4484
4485         for_each_encoder_on_crtc(dev, crtc, encoder)
4486                 encoder->disable(encoder);
4487
4488         if (intel_crtc->config.has_pch_encoder)
4489                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4490
4491         intel_disable_pipe(intel_crtc);
4492
4493         ironlake_pfit_disable(intel_crtc);
4494
4495         for_each_encoder_on_crtc(dev, crtc, encoder)
4496                 if (encoder->post_disable)
4497                         encoder->post_disable(encoder);
4498
4499         if (intel_crtc->config.has_pch_encoder) {
4500                 ironlake_fdi_disable(crtc);
4501
4502                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4503
4504                 if (HAS_PCH_CPT(dev)) {
4505                         /* disable TRANS_DP_CTL */
4506                         reg = TRANS_DP_CTL(pipe);
4507                         temp = I915_READ(reg);
4508                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4509                                   TRANS_DP_PORT_SEL_MASK);
4510                         temp |= TRANS_DP_PORT_SEL_NONE;
4511                         I915_WRITE(reg, temp);
4512
4513                         /* disable DPLL_SEL */
4514                         temp = I915_READ(PCH_DPLL_SEL);
4515                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4516                         I915_WRITE(PCH_DPLL_SEL, temp);
4517                 }
4518
4519                 /* disable PCH DPLL */
4520                 intel_disable_shared_dpll(intel_crtc);
4521
4522                 ironlake_fdi_pll_disable(intel_crtc);
4523         }
4524
4525         intel_crtc->active = false;
4526         intel_update_watermarks(crtc);
4527
4528         mutex_lock(&dev->struct_mutex);
4529         intel_fbc_update(dev);
4530         mutex_unlock(&dev->struct_mutex);
4531 }
4532
4533 static void haswell_crtc_disable(struct drm_crtc *crtc)
4534 {
4535         struct drm_device *dev = crtc->dev;
4536         struct drm_i915_private *dev_priv = dev->dev_private;
4537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538         struct intel_encoder *encoder;
4539         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4540
4541         if (!intel_crtc->active)
4542                 return;
4543
4544         intel_crtc_disable_planes(crtc);
4545
4546         drm_crtc_vblank_off(crtc);
4547         assert_vblank_disabled(crtc);
4548
4549         for_each_encoder_on_crtc(dev, crtc, encoder) {
4550                 intel_opregion_notify_encoder(encoder, false);
4551                 encoder->disable(encoder);
4552         }
4553
4554         if (intel_crtc->config.has_pch_encoder)
4555                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4556                                                       false);
4557         intel_disable_pipe(intel_crtc);
4558
4559         if (intel_crtc->config.dp_encoder_is_mst)
4560                 intel_ddi_set_vc_payload_alloc(crtc, false);
4561
4562         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4563
4564         if (IS_SKYLAKE(dev))
4565                 skylake_pfit_disable(intel_crtc);
4566         else
4567                 ironlake_pfit_disable(intel_crtc);
4568
4569         intel_ddi_disable_pipe_clock(intel_crtc);
4570
4571         if (intel_crtc->config.has_pch_encoder) {
4572                 lpt_disable_pch_transcoder(dev_priv);
4573                 intel_ddi_fdi_disable(crtc);
4574         }
4575
4576         for_each_encoder_on_crtc(dev, crtc, encoder)
4577                 if (encoder->post_disable)
4578                         encoder->post_disable(encoder);
4579
4580         intel_crtc->active = false;
4581         intel_update_watermarks(crtc);
4582
4583         mutex_lock(&dev->struct_mutex);
4584         intel_fbc_update(dev);
4585         mutex_unlock(&dev->struct_mutex);
4586
4587         if (intel_crtc_to_shared_dpll(intel_crtc))
4588                 intel_disable_shared_dpll(intel_crtc);
4589 }
4590
4591 static void ironlake_crtc_off(struct drm_crtc *crtc)
4592 {
4593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4594         intel_put_shared_dpll(intel_crtc);
4595 }
4596
4597
4598 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4599 {
4600         struct drm_device *dev = crtc->base.dev;
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602         struct intel_crtc_config *pipe_config = &crtc->config;
4603
4604         if (!crtc->config.gmch_pfit.control)
4605                 return;
4606
4607         /*
4608          * The panel fitter should only be adjusted whilst the pipe is disabled,
4609          * according to register description and PRM.
4610          */
4611         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4612         assert_pipe_disabled(dev_priv, crtc->pipe);
4613
4614         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4615         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4616
4617         /* Border color in case we don't scale up to the full screen. Black by
4618          * default, change to something else for debugging. */
4619         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4620 }
4621
4622 static enum intel_display_power_domain port_to_power_domain(enum port port)
4623 {
4624         switch (port) {
4625         case PORT_A:
4626                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4627         case PORT_B:
4628                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4629         case PORT_C:
4630                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4631         case PORT_D:
4632                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4633         default:
4634                 WARN_ON_ONCE(1);
4635                 return POWER_DOMAIN_PORT_OTHER;
4636         }
4637 }
4638
4639 #define for_each_power_domain(domain, mask)                             \
4640         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4641                 if ((1 << (domain)) & (mask))
4642
4643 enum intel_display_power_domain
4644 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4645 {
4646         struct drm_device *dev = intel_encoder->base.dev;
4647         struct intel_digital_port *intel_dig_port;
4648
4649         switch (intel_encoder->type) {
4650         case INTEL_OUTPUT_UNKNOWN:
4651                 /* Only DDI platforms should ever use this output type */
4652                 WARN_ON_ONCE(!HAS_DDI(dev));
4653         case INTEL_OUTPUT_DISPLAYPORT:
4654         case INTEL_OUTPUT_HDMI:
4655         case INTEL_OUTPUT_EDP:
4656                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4657                 return port_to_power_domain(intel_dig_port->port);
4658         case INTEL_OUTPUT_DP_MST:
4659                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4660                 return port_to_power_domain(intel_dig_port->port);
4661         case INTEL_OUTPUT_ANALOG:
4662                 return POWER_DOMAIN_PORT_CRT;
4663         case INTEL_OUTPUT_DSI:
4664                 return POWER_DOMAIN_PORT_DSI;
4665         default:
4666                 return POWER_DOMAIN_PORT_OTHER;
4667         }
4668 }
4669
4670 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4671 {
4672         struct drm_device *dev = crtc->dev;
4673         struct intel_encoder *intel_encoder;
4674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4675         enum pipe pipe = intel_crtc->pipe;
4676         unsigned long mask;
4677         enum transcoder transcoder;
4678
4679         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4680
4681         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4682         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4683         if (intel_crtc->config.pch_pfit.enabled ||
4684             intel_crtc->config.pch_pfit.force_thru)
4685                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4686
4687         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4688                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4689
4690         return mask;
4691 }
4692
4693 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4694 {
4695         struct drm_i915_private *dev_priv = dev->dev_private;
4696         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4697         struct intel_crtc *crtc;
4698
4699         /*
4700          * First get all needed power domains, then put all unneeded, to avoid
4701          * any unnecessary toggling of the power wells.
4702          */
4703         for_each_intel_crtc(dev, crtc) {
4704                 enum intel_display_power_domain domain;
4705
4706                 if (!crtc->base.enabled)
4707                         continue;
4708
4709                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4710
4711                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4712                         intel_display_power_get(dev_priv, domain);
4713         }
4714
4715         if (dev_priv->display.modeset_global_resources)
4716                 dev_priv->display.modeset_global_resources(dev);
4717
4718         for_each_intel_crtc(dev, crtc) {
4719                 enum intel_display_power_domain domain;
4720
4721                 for_each_power_domain(domain, crtc->enabled_power_domains)
4722                         intel_display_power_put(dev_priv, domain);
4723
4724                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4725         }
4726
4727         intel_display_set_init_power(dev_priv, false);
4728 }
4729
4730 /* returns HPLL frequency in kHz */
4731 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4732 {
4733         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4734
4735         /* Obtain SKU information */
4736         mutex_lock(&dev_priv->dpio_lock);
4737         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4738                 CCK_FUSE_HPLL_FREQ_MASK;
4739         mutex_unlock(&dev_priv->dpio_lock);
4740
4741         return vco_freq[hpll_freq] * 1000;
4742 }
4743
4744 static void vlv_update_cdclk(struct drm_device *dev)
4745 {
4746         struct drm_i915_private *dev_priv = dev->dev_private;
4747
4748         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4749         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4750                          dev_priv->vlv_cdclk_freq);
4751
4752         /*
4753          * Program the gmbus_freq based on the cdclk frequency.
4754          * BSpec erroneously claims we should aim for 4MHz, but
4755          * in fact 1MHz is the correct frequency.
4756          */
4757         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4758 }
4759
4760 /* Adjust CDclk dividers to allow high res or save power if possible */
4761 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4762 {
4763         struct drm_i915_private *dev_priv = dev->dev_private;
4764         u32 val, cmd;
4765
4766         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4767
4768         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4769                 cmd = 2;
4770         else if (cdclk == 266667)
4771                 cmd = 1;
4772         else
4773                 cmd = 0;
4774
4775         mutex_lock(&dev_priv->rps.hw_lock);
4776         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4777         val &= ~DSPFREQGUAR_MASK;
4778         val |= (cmd << DSPFREQGUAR_SHIFT);
4779         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4780         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4781                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4782                      50)) {
4783                 DRM_ERROR("timed out waiting for CDclk change\n");
4784         }
4785         mutex_unlock(&dev_priv->rps.hw_lock);
4786
4787         if (cdclk == 400000) {
4788                 u32 divider;
4789
4790                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4791
4792                 mutex_lock(&dev_priv->dpio_lock);
4793                 /* adjust cdclk divider */
4794                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4795                 val &= ~DISPLAY_FREQUENCY_VALUES;
4796                 val |= divider;
4797                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4798
4799                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4800                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4801                              50))
4802                         DRM_ERROR("timed out waiting for CDclk change\n");
4803                 mutex_unlock(&dev_priv->dpio_lock);
4804         }
4805
4806         mutex_lock(&dev_priv->dpio_lock);
4807         /* adjust self-refresh exit latency value */
4808         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4809         val &= ~0x7f;
4810
4811         /*
4812          * For high bandwidth configs, we set a higher latency in the bunit
4813          * so that the core display fetch happens in time to avoid underruns.
4814          */
4815         if (cdclk == 400000)
4816                 val |= 4500 / 250; /* 4.5 usec */
4817         else
4818                 val |= 3000 / 250; /* 3.0 usec */
4819         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4820         mutex_unlock(&dev_priv->dpio_lock);
4821
4822         vlv_update_cdclk(dev);
4823 }
4824
4825 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4826 {
4827         struct drm_i915_private *dev_priv = dev->dev_private;
4828         u32 val, cmd;
4829
4830         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4831
4832         switch (cdclk) {
4833         case 400000:
4834                 cmd = 3;
4835                 break;
4836         case 333333:
4837         case 320000:
4838                 cmd = 2;
4839                 break;
4840         case 266667:
4841                 cmd = 1;
4842                 break;
4843         case 200000:
4844                 cmd = 0;
4845                 break;
4846         default:
4847                 MISSING_CASE(cdclk);
4848                 return;
4849         }
4850
4851         mutex_lock(&dev_priv->rps.hw_lock);
4852         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4853         val &= ~DSPFREQGUAR_MASK_CHV;
4854         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4855         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4856         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4857                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4858                      50)) {
4859                 DRM_ERROR("timed out waiting for CDclk change\n");
4860         }
4861         mutex_unlock(&dev_priv->rps.hw_lock);
4862
4863         vlv_update_cdclk(dev);
4864 }
4865
4866 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4867                                  int max_pixclk)
4868 {
4869         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4870
4871         /* FIXME: Punit isn't quite ready yet */
4872         if (IS_CHERRYVIEW(dev_priv->dev))
4873                 return 400000;
4874
4875         /*
4876          * Really only a few cases to deal with, as only 4 CDclks are supported:
4877          *   200MHz
4878          *   267MHz
4879          *   320/333MHz (depends on HPLL freq)
4880          *   400MHz
4881          * So we check to see whether we're above 90% of the lower bin and
4882          * adjust if needed.
4883          *
4884          * We seem to get an unstable or solid color picture at 200MHz.
4885          * Not sure what's wrong. For now use 200MHz only when all pipes
4886          * are off.
4887          */
4888         if (max_pixclk > freq_320*9/10)
4889                 return 400000;
4890         else if (max_pixclk > 266667*9/10)
4891                 return freq_320;
4892         else if (max_pixclk > 0)
4893                 return 266667;
4894         else
4895                 return 200000;
4896 }
4897
4898 /* compute the max pixel clock for new configuration */
4899 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4900 {
4901         struct drm_device *dev = dev_priv->dev;
4902         struct intel_crtc *intel_crtc;
4903         int max_pixclk = 0;
4904
4905         for_each_intel_crtc(dev, intel_crtc) {
4906                 if (intel_crtc->new_enabled)
4907                         max_pixclk = max(max_pixclk,
4908                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4909         }
4910
4911         return max_pixclk;
4912 }
4913
4914 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4915                                             unsigned *prepare_pipes)
4916 {
4917         struct drm_i915_private *dev_priv = dev->dev_private;
4918         struct intel_crtc *intel_crtc;
4919         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4920
4921         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4922             dev_priv->vlv_cdclk_freq)
4923                 return;
4924
4925         /* disable/enable all currently active pipes while we change cdclk */
4926         for_each_intel_crtc(dev, intel_crtc)
4927                 if (intel_crtc->base.enabled)
4928                         *prepare_pipes |= (1 << intel_crtc->pipe);
4929 }
4930
4931 static void valleyview_modeset_global_resources(struct drm_device *dev)
4932 {
4933         struct drm_i915_private *dev_priv = dev->dev_private;
4934         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4935         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4936
4937         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4938                 /*
4939                  * FIXME: We can end up here with all power domains off, yet
4940                  * with a CDCLK frequency other than the minimum. To account
4941                  * for this take the PIPE-A power domain, which covers the HW
4942                  * blocks needed for the following programming. This can be
4943                  * removed once it's guaranteed that we get here either with
4944                  * the minimum CDCLK set, or the required power domains
4945                  * enabled.
4946                  */
4947                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
4948
4949                 if (IS_CHERRYVIEW(dev))
4950                         cherryview_set_cdclk(dev, req_cdclk);
4951                 else
4952                         valleyview_set_cdclk(dev, req_cdclk);
4953
4954                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
4955         }
4956 }
4957
4958 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4959 {
4960         struct drm_device *dev = crtc->dev;
4961         struct drm_i915_private *dev_priv = to_i915(dev);
4962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4963         struct intel_encoder *encoder;
4964         int pipe = intel_crtc->pipe;
4965         bool is_dsi;
4966
4967         WARN_ON(!crtc->enabled);
4968
4969         if (intel_crtc->active)
4970                 return;
4971
4972         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4973
4974         if (!is_dsi) {
4975                 if (IS_CHERRYVIEW(dev))
4976                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4977                 else
4978                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4979         }
4980
4981         if (intel_crtc->config.has_dp_encoder)
4982                 intel_dp_set_m_n(intel_crtc);
4983
4984         intel_set_pipe_timings(intel_crtc);
4985
4986         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4987                 struct drm_i915_private *dev_priv = dev->dev_private;
4988
4989                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4990                 I915_WRITE(CHV_CANVAS(pipe), 0);
4991         }
4992
4993         i9xx_set_pipeconf(intel_crtc);
4994
4995         intel_crtc->active = true;
4996
4997         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4998
4999         for_each_encoder_on_crtc(dev, crtc, encoder)
5000                 if (encoder->pre_pll_enable)
5001                         encoder->pre_pll_enable(encoder);
5002
5003         if (!is_dsi) {
5004                 if (IS_CHERRYVIEW(dev))
5005                         chv_enable_pll(intel_crtc, &intel_crtc->config);
5006                 else
5007                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
5008         }
5009
5010         for_each_encoder_on_crtc(dev, crtc, encoder)
5011                 if (encoder->pre_enable)
5012                         encoder->pre_enable(encoder);
5013
5014         i9xx_pfit_enable(intel_crtc);
5015
5016         intel_crtc_load_lut(crtc);
5017
5018         intel_update_watermarks(crtc);
5019         intel_enable_pipe(intel_crtc);
5020
5021         for_each_encoder_on_crtc(dev, crtc, encoder)
5022                 encoder->enable(encoder);
5023
5024         assert_vblank_disabled(crtc);
5025         drm_crtc_vblank_on(crtc);
5026
5027         intel_crtc_enable_planes(crtc);
5028
5029         /* Underruns don't raise interrupts, so check manually. */
5030         i9xx_check_fifo_underruns(dev_priv);
5031 }
5032
5033 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5034 {
5035         struct drm_device *dev = crtc->base.dev;
5036         struct drm_i915_private *dev_priv = dev->dev_private;
5037
5038         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
5039         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
5040 }
5041
5042 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5043 {
5044         struct drm_device *dev = crtc->dev;
5045         struct drm_i915_private *dev_priv = to_i915(dev);
5046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5047         struct intel_encoder *encoder;
5048         int pipe = intel_crtc->pipe;
5049
5050         WARN_ON(!crtc->enabled);
5051
5052         if (intel_crtc->active)
5053                 return;
5054
5055         i9xx_set_pll_dividers(intel_crtc);
5056
5057         if (intel_crtc->config.has_dp_encoder)
5058                 intel_dp_set_m_n(intel_crtc);
5059
5060         intel_set_pipe_timings(intel_crtc);
5061
5062         i9xx_set_pipeconf(intel_crtc);
5063
5064         intel_crtc->active = true;
5065
5066         if (!IS_GEN2(dev))
5067                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5068
5069         for_each_encoder_on_crtc(dev, crtc, encoder)
5070                 if (encoder->pre_enable)
5071                         encoder->pre_enable(encoder);
5072
5073         i9xx_enable_pll(intel_crtc);
5074
5075         i9xx_pfit_enable(intel_crtc);
5076
5077         intel_crtc_load_lut(crtc);
5078
5079         intel_update_watermarks(crtc);
5080         intel_enable_pipe(intel_crtc);
5081
5082         for_each_encoder_on_crtc(dev, crtc, encoder)
5083                 encoder->enable(encoder);
5084
5085         assert_vblank_disabled(crtc);
5086         drm_crtc_vblank_on(crtc);
5087
5088         intel_crtc_enable_planes(crtc);
5089
5090         /*
5091          * Gen2 reports pipe underruns whenever all planes are disabled.
5092          * So don't enable underrun reporting before at least some planes
5093          * are enabled.
5094          * FIXME: Need to fix the logic to work when we turn off all planes
5095          * but leave the pipe running.
5096          */
5097         if (IS_GEN2(dev))
5098                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5099
5100         /* Underruns don't raise interrupts, so check manually. */
5101         i9xx_check_fifo_underruns(dev_priv);
5102 }
5103
5104 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5105 {
5106         struct drm_device *dev = crtc->base.dev;
5107         struct drm_i915_private *dev_priv = dev->dev_private;
5108
5109         if (!crtc->config.gmch_pfit.control)
5110                 return;
5111
5112         assert_pipe_disabled(dev_priv, crtc->pipe);
5113
5114         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5115                          I915_READ(PFIT_CONTROL));
5116         I915_WRITE(PFIT_CONTROL, 0);
5117 }
5118
5119 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5120 {
5121         struct drm_device *dev = crtc->dev;
5122         struct drm_i915_private *dev_priv = dev->dev_private;
5123         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5124         struct intel_encoder *encoder;
5125         int pipe = intel_crtc->pipe;
5126
5127         if (!intel_crtc->active)
5128                 return;
5129
5130         /*
5131          * Gen2 reports pipe underruns whenever all planes are disabled.
5132          * So diasble underrun reporting before all the planes get disabled.
5133          * FIXME: Need to fix the logic to work when we turn off all planes
5134          * but leave the pipe running.
5135          */
5136         if (IS_GEN2(dev))
5137                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5138
5139         /*
5140          * Vblank time updates from the shadow to live plane control register
5141          * are blocked if the memory self-refresh mode is active at that
5142          * moment. So to make sure the plane gets truly disabled, disable
5143          * first the self-refresh mode. The self-refresh enable bit in turn
5144          * will be checked/applied by the HW only at the next frame start
5145          * event which is after the vblank start event, so we need to have a
5146          * wait-for-vblank between disabling the plane and the pipe.
5147          */
5148         intel_set_memory_cxsr(dev_priv, false);
5149         intel_crtc_disable_planes(crtc);
5150
5151         /*
5152          * On gen2 planes are double buffered but the pipe isn't, so we must
5153          * wait for planes to fully turn off before disabling the pipe.
5154          * We also need to wait on all gmch platforms because of the
5155          * self-refresh mode constraint explained above.
5156          */
5157         intel_wait_for_vblank(dev, pipe);
5158
5159         drm_crtc_vblank_off(crtc);
5160         assert_vblank_disabled(crtc);
5161
5162         for_each_encoder_on_crtc(dev, crtc, encoder)
5163                 encoder->disable(encoder);
5164
5165         intel_disable_pipe(intel_crtc);
5166
5167         i9xx_pfit_disable(intel_crtc);
5168
5169         for_each_encoder_on_crtc(dev, crtc, encoder)
5170                 if (encoder->post_disable)
5171                         encoder->post_disable(encoder);
5172
5173         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5174                 if (IS_CHERRYVIEW(dev))
5175                         chv_disable_pll(dev_priv, pipe);
5176                 else if (IS_VALLEYVIEW(dev))
5177                         vlv_disable_pll(dev_priv, pipe);
5178                 else
5179                         i9xx_disable_pll(intel_crtc);
5180         }
5181
5182         if (!IS_GEN2(dev))
5183                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5184
5185         intel_crtc->active = false;
5186         intel_update_watermarks(crtc);
5187
5188         mutex_lock(&dev->struct_mutex);
5189         intel_fbc_update(dev);
5190         mutex_unlock(&dev->struct_mutex);
5191 }
5192
5193 static void i9xx_crtc_off(struct drm_crtc *crtc)
5194 {
5195 }
5196
5197 /* Master function to enable/disable CRTC and corresponding power wells */
5198 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5199 {
5200         struct drm_device *dev = crtc->dev;
5201         struct drm_i915_private *dev_priv = dev->dev_private;
5202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5203         enum intel_display_power_domain domain;
5204         unsigned long domains;
5205
5206         if (enable) {
5207                 if (!intel_crtc->active) {
5208                         domains = get_crtc_power_domains(crtc);
5209                         for_each_power_domain(domain, domains)
5210                                 intel_display_power_get(dev_priv, domain);
5211                         intel_crtc->enabled_power_domains = domains;
5212
5213                         dev_priv->display.crtc_enable(crtc);
5214                 }
5215         } else {
5216                 if (intel_crtc->active) {
5217                         dev_priv->display.crtc_disable(crtc);
5218
5219                         domains = intel_crtc->enabled_power_domains;
5220                         for_each_power_domain(domain, domains)
5221                                 intel_display_power_put(dev_priv, domain);
5222                         intel_crtc->enabled_power_domains = 0;
5223                 }
5224         }
5225 }
5226
5227 /**
5228  * Sets the power management mode of the pipe and plane.
5229  */
5230 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5231 {
5232         struct drm_device *dev = crtc->dev;
5233         struct intel_encoder *intel_encoder;
5234         bool enable = false;
5235
5236         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5237                 enable |= intel_encoder->connectors_active;
5238
5239         intel_crtc_control(crtc, enable);
5240 }
5241
5242 static void intel_crtc_disable(struct drm_crtc *crtc)
5243 {
5244         struct drm_device *dev = crtc->dev;
5245         struct drm_connector *connector;
5246         struct drm_i915_private *dev_priv = dev->dev_private;
5247
5248         /* crtc should still be enabled when we disable it. */
5249         WARN_ON(!crtc->enabled);
5250
5251         dev_priv->display.crtc_disable(crtc);
5252         dev_priv->display.off(crtc);
5253
5254         crtc->primary->funcs->disable_plane(crtc->primary);
5255
5256         /* Update computed state. */
5257         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5258                 if (!connector->encoder || !connector->encoder->crtc)
5259                         continue;
5260
5261                 if (connector->encoder->crtc != crtc)
5262                         continue;
5263
5264                 connector->dpms = DRM_MODE_DPMS_OFF;
5265                 to_intel_encoder(connector->encoder)->connectors_active = false;
5266         }
5267 }
5268
5269 void intel_encoder_destroy(struct drm_encoder *encoder)
5270 {
5271         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5272
5273         drm_encoder_cleanup(encoder);
5274         kfree(intel_encoder);
5275 }
5276
5277 /* Simple dpms helper for encoders with just one connector, no cloning and only
5278  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5279  * state of the entire output pipe. */
5280 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5281 {
5282         if (mode == DRM_MODE_DPMS_ON) {
5283                 encoder->connectors_active = true;
5284
5285                 intel_crtc_update_dpms(encoder->base.crtc);
5286         } else {
5287                 encoder->connectors_active = false;
5288
5289                 intel_crtc_update_dpms(encoder->base.crtc);
5290         }
5291 }
5292
5293 /* Cross check the actual hw state with our own modeset state tracking (and it's
5294  * internal consistency). */
5295 static void intel_connector_check_state(struct intel_connector *connector)
5296 {
5297         if (connector->get_hw_state(connector)) {
5298                 struct intel_encoder *encoder = connector->encoder;
5299                 struct drm_crtc *crtc;
5300                 bool encoder_enabled;
5301                 enum pipe pipe;
5302
5303                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5304                               connector->base.base.id,
5305                               connector->base.name);
5306
5307                 /* there is no real hw state for MST connectors */
5308                 if (connector->mst_port)
5309                         return;
5310
5311                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5312                      "wrong connector dpms state\n");
5313                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5314                      "active connector not linked to encoder\n");
5315
5316                 if (encoder) {
5317                         I915_STATE_WARN(!encoder->connectors_active,
5318                              "encoder->connectors_active not set\n");
5319
5320                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5321                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5322                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5323                                 return;
5324
5325                         crtc = encoder->base.crtc;
5326
5327                         I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5328                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5329                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5330                              "encoder active on the wrong pipe\n");
5331                 }
5332         }
5333 }
5334
5335 /* Even simpler default implementation, if there's really no special case to
5336  * consider. */
5337 void intel_connector_dpms(struct drm_connector *connector, int mode)
5338 {
5339         /* All the simple cases only support two dpms states. */
5340         if (mode != DRM_MODE_DPMS_ON)
5341                 mode = DRM_MODE_DPMS_OFF;
5342
5343         if (mode == connector->dpms)
5344                 return;
5345
5346         connector->dpms = mode;
5347
5348         /* Only need to change hw state when actually enabled */
5349         if (connector->encoder)
5350                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5351
5352         intel_modeset_check_state(connector->dev);
5353 }
5354
5355 /* Simple connector->get_hw_state implementation for encoders that support only
5356  * one connector and no cloning and hence the encoder state determines the state
5357  * of the connector. */
5358 bool intel_connector_get_hw_state(struct intel_connector *connector)
5359 {
5360         enum pipe pipe = 0;
5361         struct intel_encoder *encoder = connector->encoder;
5362
5363         return encoder->get_hw_state(encoder, &pipe);
5364 }
5365
5366 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5367                                      struct intel_crtc_config *pipe_config)
5368 {
5369         struct drm_i915_private *dev_priv = dev->dev_private;
5370         struct intel_crtc *pipe_B_crtc =
5371                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5372
5373         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5374                       pipe_name(pipe), pipe_config->fdi_lanes);
5375         if (pipe_config->fdi_lanes > 4) {
5376                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5377                               pipe_name(pipe), pipe_config->fdi_lanes);
5378                 return false;
5379         }
5380
5381         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5382                 if (pipe_config->fdi_lanes > 2) {
5383                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5384                                       pipe_config->fdi_lanes);
5385                         return false;
5386                 } else {
5387                         return true;
5388                 }
5389         }
5390
5391         if (INTEL_INFO(dev)->num_pipes == 2)
5392                 return true;
5393
5394         /* Ivybridge 3 pipe is really complicated */
5395         switch (pipe) {
5396         case PIPE_A:
5397                 return true;
5398         case PIPE_B:
5399                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5400                     pipe_config->fdi_lanes > 2) {
5401                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5402                                       pipe_name(pipe), pipe_config->fdi_lanes);
5403                         return false;
5404                 }
5405                 return true;
5406         case PIPE_C:
5407                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5408                     pipe_B_crtc->config.fdi_lanes <= 2) {
5409                         if (pipe_config->fdi_lanes > 2) {
5410                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5411                                               pipe_name(pipe), pipe_config->fdi_lanes);
5412                                 return false;
5413                         }
5414                 } else {
5415                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5416                         return false;
5417                 }
5418                 return true;
5419         default:
5420                 BUG();
5421         }
5422 }
5423
5424 #define RETRY 1
5425 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5426                                        struct intel_crtc_config *pipe_config)
5427 {
5428         struct drm_device *dev = intel_crtc->base.dev;
5429         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5430         int lane, link_bw, fdi_dotclock;
5431         bool setup_ok, needs_recompute = false;
5432
5433 retry:
5434         /* FDI is a binary signal running at ~2.7GHz, encoding
5435          * each output octet as 10 bits. The actual frequency
5436          * is stored as a divider into a 100MHz clock, and the
5437          * mode pixel clock is stored in units of 1KHz.
5438          * Hence the bw of each lane in terms of the mode signal
5439          * is:
5440          */
5441         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5442
5443         fdi_dotclock = adjusted_mode->crtc_clock;
5444
5445         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5446                                            pipe_config->pipe_bpp);
5447
5448         pipe_config->fdi_lanes = lane;
5449
5450         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5451                                link_bw, &pipe_config->fdi_m_n);
5452
5453         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5454                                             intel_crtc->pipe, pipe_config);
5455         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5456                 pipe_config->pipe_bpp -= 2*3;
5457                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5458                               pipe_config->pipe_bpp);
5459                 needs_recompute = true;
5460                 pipe_config->bw_constrained = true;
5461
5462                 goto retry;
5463         }
5464
5465         if (needs_recompute)
5466                 return RETRY;
5467
5468         return setup_ok ? 0 : -EINVAL;
5469 }
5470
5471 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5472                                    struct intel_crtc_config *pipe_config)
5473 {
5474         pipe_config->ips_enabled = i915.enable_ips &&
5475                                    hsw_crtc_supports_ips(crtc) &&
5476                                    pipe_config->pipe_bpp <= 24;
5477 }
5478
5479 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5480                                      struct intel_crtc_config *pipe_config)
5481 {
5482         struct drm_device *dev = crtc->base.dev;
5483         struct drm_i915_private *dev_priv = dev->dev_private;
5484         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5485
5486         /* FIXME should check pixel clock limits on all platforms */
5487         if (INTEL_INFO(dev)->gen < 4) {
5488                 int clock_limit =
5489                         dev_priv->display.get_display_clock_speed(dev);
5490
5491                 /*
5492                  * Enable pixel doubling when the dot clock
5493                  * is > 90% of the (display) core speed.
5494                  *
5495                  * GDG double wide on either pipe,
5496                  * otherwise pipe A only.
5497                  */
5498                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5499                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5500                         clock_limit *= 2;
5501                         pipe_config->double_wide = true;
5502                 }
5503
5504                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5505                         return -EINVAL;
5506         }
5507
5508         /*
5509          * Pipe horizontal size must be even in:
5510          * - DVO ganged mode
5511          * - LVDS dual channel mode
5512          * - Double wide pipe
5513          */
5514         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5515              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5516                 pipe_config->pipe_src_w &= ~1;
5517
5518         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5519          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5520          */
5521         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5522                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5523                 return -EINVAL;
5524
5525         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5526                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5527         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5528                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5529                  * for lvds. */
5530                 pipe_config->pipe_bpp = 8*3;
5531         }
5532
5533         if (HAS_IPS(dev))
5534                 hsw_compute_ips_config(crtc, pipe_config);
5535
5536         if (pipe_config->has_pch_encoder)
5537                 return ironlake_fdi_compute_config(crtc, pipe_config);
5538
5539         return 0;
5540 }
5541
5542 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5543 {
5544         struct drm_i915_private *dev_priv = dev->dev_private;
5545         u32 val;
5546         int divider;
5547
5548         /* FIXME: Punit isn't quite ready yet */
5549         if (IS_CHERRYVIEW(dev))
5550                 return 400000;
5551
5552         if (dev_priv->hpll_freq == 0)
5553                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5554
5555         mutex_lock(&dev_priv->dpio_lock);
5556         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5557         mutex_unlock(&dev_priv->dpio_lock);
5558
5559         divider = val & DISPLAY_FREQUENCY_VALUES;
5560
5561         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5562              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5563              "cdclk change in progress\n");
5564
5565         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5566 }
5567
5568 static int i945_get_display_clock_speed(struct drm_device *dev)
5569 {
5570         return 400000;
5571 }
5572
5573 static int i915_get_display_clock_speed(struct drm_device *dev)
5574 {
5575         return 333000;
5576 }
5577
5578 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5579 {
5580         return 200000;
5581 }
5582
5583 static int pnv_get_display_clock_speed(struct drm_device *dev)
5584 {
5585         u16 gcfgc = 0;
5586
5587         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5588
5589         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5590         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5591                 return 267000;
5592         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5593                 return 333000;
5594         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5595                 return 444000;
5596         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5597                 return 200000;
5598         default:
5599                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5600         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5601                 return 133000;
5602         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5603                 return 167000;
5604         }
5605 }
5606
5607 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5608 {
5609         u16 gcfgc = 0;
5610
5611         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5612
5613         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5614                 return 133000;
5615         else {
5616                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5617                 case GC_DISPLAY_CLOCK_333_MHZ:
5618                         return 333000;
5619                 default:
5620                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5621                         return 190000;
5622                 }
5623         }
5624 }
5625
5626 static int i865_get_display_clock_speed(struct drm_device *dev)
5627 {
5628         return 266000;
5629 }
5630
5631 static int i855_get_display_clock_speed(struct drm_device *dev)
5632 {
5633         u16 hpllcc = 0;
5634         /* Assume that the hardware is in the high speed state.  This
5635          * should be the default.
5636          */
5637         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5638         case GC_CLOCK_133_200:
5639         case GC_CLOCK_100_200:
5640                 return 200000;
5641         case GC_CLOCK_166_250:
5642                 return 250000;
5643         case GC_CLOCK_100_133:
5644                 return 133000;
5645         }
5646
5647         /* Shouldn't happen */
5648         return 0;
5649 }
5650
5651 static int i830_get_display_clock_speed(struct drm_device *dev)
5652 {
5653         return 133000;
5654 }
5655
5656 static void
5657 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5658 {
5659         while (*num > DATA_LINK_M_N_MASK ||
5660                *den > DATA_LINK_M_N_MASK) {
5661                 *num >>= 1;
5662                 *den >>= 1;
5663         }
5664 }
5665
5666 static void compute_m_n(unsigned int m, unsigned int n,
5667                         uint32_t *ret_m, uint32_t *ret_n)
5668 {
5669         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5670         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5671         intel_reduce_m_n_ratio(ret_m, ret_n);
5672 }
5673
5674 void
5675 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5676                        int pixel_clock, int link_clock,
5677                        struct intel_link_m_n *m_n)
5678 {
5679         m_n->tu = 64;
5680
5681         compute_m_n(bits_per_pixel * pixel_clock,
5682                     link_clock * nlanes * 8,
5683                     &m_n->gmch_m, &m_n->gmch_n);
5684
5685         compute_m_n(pixel_clock, link_clock,
5686                     &m_n->link_m, &m_n->link_n);
5687 }
5688
5689 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5690 {
5691         if (i915.panel_use_ssc >= 0)
5692                 return i915.panel_use_ssc != 0;
5693         return dev_priv->vbt.lvds_use_ssc
5694                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5695 }
5696
5697 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5698 {
5699         struct drm_device *dev = crtc->base.dev;
5700         struct drm_i915_private *dev_priv = dev->dev_private;
5701         int refclk;
5702
5703         if (IS_VALLEYVIEW(dev)) {
5704                 refclk = 100000;
5705         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5706             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5707                 refclk = dev_priv->vbt.lvds_ssc_freq;
5708                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5709         } else if (!IS_GEN2(dev)) {
5710                 refclk = 96000;
5711         } else {
5712                 refclk = 48000;
5713         }
5714
5715         return refclk;
5716 }
5717
5718 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5719 {
5720         return (1 << dpll->n) << 16 | dpll->m2;
5721 }
5722
5723 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5724 {
5725         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5726 }
5727
5728 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5729                                      intel_clock_t *reduced_clock)
5730 {
5731         struct drm_device *dev = crtc->base.dev;
5732         u32 fp, fp2 = 0;
5733
5734         if (IS_PINEVIEW(dev)) {
5735                 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
5736                 if (reduced_clock)
5737                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5738         } else {
5739                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
5740                 if (reduced_clock)
5741                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5742         }
5743
5744         crtc->new_config->dpll_hw_state.fp0 = fp;
5745
5746         crtc->lowfreq_avail = false;
5747         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5748             reduced_clock && i915.powersave) {
5749                 crtc->new_config->dpll_hw_state.fp1 = fp2;
5750                 crtc->lowfreq_avail = true;
5751         } else {
5752                 crtc->new_config->dpll_hw_state.fp1 = fp;
5753         }
5754 }
5755
5756 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5757                 pipe)
5758 {
5759         u32 reg_val;
5760
5761         /*
5762          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5763          * and set it to a reasonable value instead.
5764          */
5765         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5766         reg_val &= 0xffffff00;
5767         reg_val |= 0x00000030;
5768         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5769
5770         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5771         reg_val &= 0x8cffffff;
5772         reg_val = 0x8c000000;
5773         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5774
5775         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5776         reg_val &= 0xffffff00;
5777         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5778
5779         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5780         reg_val &= 0x00ffffff;
5781         reg_val |= 0xb0000000;
5782         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5783 }
5784
5785 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5786                                          struct intel_link_m_n *m_n)
5787 {
5788         struct drm_device *dev = crtc->base.dev;
5789         struct drm_i915_private *dev_priv = dev->dev_private;
5790         int pipe = crtc->pipe;
5791
5792         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5793         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5794         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5795         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5796 }
5797
5798 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5799                                          struct intel_link_m_n *m_n,
5800                                          struct intel_link_m_n *m2_n2)
5801 {
5802         struct drm_device *dev = crtc->base.dev;
5803         struct drm_i915_private *dev_priv = dev->dev_private;
5804         int pipe = crtc->pipe;
5805         enum transcoder transcoder = crtc->config.cpu_transcoder;
5806
5807         if (INTEL_INFO(dev)->gen >= 5) {
5808                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5809                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5810                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5811                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5812                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5813                  * for gen < 8) and if DRRS is supported (to make sure the
5814                  * registers are not unnecessarily accessed).
5815                  */
5816                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5817                         crtc->config.has_drrs) {
5818                         I915_WRITE(PIPE_DATA_M2(transcoder),
5819                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5820                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5821                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5822                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5823                 }
5824         } else {
5825                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5826                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5827                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5828                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5829         }
5830 }
5831
5832 void intel_dp_set_m_n(struct intel_crtc *crtc)
5833 {
5834         if (crtc->config.has_pch_encoder)
5835                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5836         else
5837                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5838                                                    &crtc->config.dp_m2_n2);
5839 }
5840
5841 static void vlv_update_pll(struct intel_crtc *crtc,
5842                            struct intel_crtc_config *pipe_config)
5843 {
5844         u32 dpll, dpll_md;
5845
5846         /*
5847          * Enable DPIO clock input. We should never disable the reference
5848          * clock for pipe B, since VGA hotplug / manual detection depends
5849          * on it.
5850          */
5851         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5852                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5853         /* We should never disable this, set it here for state tracking */
5854         if (crtc->pipe == PIPE_B)
5855                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5856         dpll |= DPLL_VCO_ENABLE;
5857         pipe_config->dpll_hw_state.dpll = dpll;
5858
5859         dpll_md = (pipe_config->pixel_multiplier - 1)
5860                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5861         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5862 }
5863
5864 static void vlv_prepare_pll(struct intel_crtc *crtc,
5865                             const struct intel_crtc_config *pipe_config)
5866 {
5867         struct drm_device *dev = crtc->base.dev;
5868         struct drm_i915_private *dev_priv = dev->dev_private;
5869         int pipe = crtc->pipe;
5870         u32 mdiv;
5871         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5872         u32 coreclk, reg_val;
5873
5874         mutex_lock(&dev_priv->dpio_lock);
5875
5876         bestn = pipe_config->dpll.n;
5877         bestm1 = pipe_config->dpll.m1;
5878         bestm2 = pipe_config->dpll.m2;
5879         bestp1 = pipe_config->dpll.p1;
5880         bestp2 = pipe_config->dpll.p2;
5881
5882         /* See eDP HDMI DPIO driver vbios notes doc */
5883
5884         /* PLL B needs special handling */
5885         if (pipe == PIPE_B)
5886                 vlv_pllb_recal_opamp(dev_priv, pipe);
5887
5888         /* Set up Tx target for periodic Rcomp update */
5889         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5890
5891         /* Disable target IRef on PLL */
5892         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5893         reg_val &= 0x00ffffff;
5894         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5895
5896         /* Disable fast lock */
5897         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5898
5899         /* Set idtafcrecal before PLL is enabled */
5900         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5901         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5902         mdiv |= ((bestn << DPIO_N_SHIFT));
5903         mdiv |= (1 << DPIO_K_SHIFT);
5904
5905         /*
5906          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5907          * but we don't support that).
5908          * Note: don't use the DAC post divider as it seems unstable.
5909          */
5910         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5911         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5912
5913         mdiv |= DPIO_ENABLE_CALIBRATION;
5914         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5915
5916         /* Set HBR and RBR LPF coefficients */
5917         if (pipe_config->port_clock == 162000 ||
5918             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5919             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5920                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5921                                  0x009f0003);
5922         else
5923                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5924                                  0x00d0000f);
5925
5926         if (crtc->config.has_dp_encoder) {
5927                 /* Use SSC source */
5928                 if (pipe == PIPE_A)
5929                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5930                                          0x0df40000);
5931                 else
5932                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5933                                          0x0df70000);
5934         } else { /* HDMI or VGA */
5935                 /* Use bend source */
5936                 if (pipe == PIPE_A)
5937                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5938                                          0x0df70000);
5939                 else
5940                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5941                                          0x0df40000);
5942         }
5943
5944         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5945         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5946         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5947             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5948                 coreclk |= 0x01000000;
5949         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5950
5951         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5952         mutex_unlock(&dev_priv->dpio_lock);
5953 }
5954
5955 static void chv_update_pll(struct intel_crtc *crtc,
5956                            struct intel_crtc_config *pipe_config)
5957 {
5958         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5959                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5960                 DPLL_VCO_ENABLE;
5961         if (crtc->pipe != PIPE_A)
5962                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5963
5964         pipe_config->dpll_hw_state.dpll_md =
5965                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5966 }
5967
5968 static void chv_prepare_pll(struct intel_crtc *crtc,
5969                             const struct intel_crtc_config *pipe_config)
5970 {
5971         struct drm_device *dev = crtc->base.dev;
5972         struct drm_i915_private *dev_priv = dev->dev_private;
5973         int pipe = crtc->pipe;
5974         int dpll_reg = DPLL(crtc->pipe);
5975         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5976         u32 loopfilter, intcoeff;
5977         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5978         int refclk;
5979
5980         bestn = pipe_config->dpll.n;
5981         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5982         bestm1 = pipe_config->dpll.m1;
5983         bestm2 = pipe_config->dpll.m2 >> 22;
5984         bestp1 = pipe_config->dpll.p1;
5985         bestp2 = pipe_config->dpll.p2;
5986
5987         /*
5988          * Enable Refclk and SSC
5989          */
5990         I915_WRITE(dpll_reg,
5991                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5992
5993         mutex_lock(&dev_priv->dpio_lock);
5994
5995         /* p1 and p2 divider */
5996         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5997                         5 << DPIO_CHV_S1_DIV_SHIFT |
5998                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5999                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6000                         1 << DPIO_CHV_K_DIV_SHIFT);
6001
6002         /* Feedback post-divider - m2 */
6003         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6004
6005         /* Feedback refclk divider - n and m1 */
6006         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6007                         DPIO_CHV_M1_DIV_BY_2 |
6008                         1 << DPIO_CHV_N_DIV_SHIFT);
6009
6010         /* M2 fraction division */
6011         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6012
6013         /* M2 fraction division enable */
6014         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6015                        DPIO_CHV_FRAC_DIV_EN |
6016                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6017
6018         /* Loop filter */
6019         refclk = i9xx_get_refclk(crtc, 0);
6020         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6021                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6022         if (refclk == 100000)
6023                 intcoeff = 11;
6024         else if (refclk == 38400)
6025                 intcoeff = 10;
6026         else
6027                 intcoeff = 9;
6028         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6029         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6030
6031         /* AFC Recal */
6032         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6033                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6034                         DPIO_AFC_RECAL);
6035
6036         mutex_unlock(&dev_priv->dpio_lock);
6037 }
6038
6039 /**
6040  * vlv_force_pll_on - forcibly enable just the PLL
6041  * @dev_priv: i915 private structure
6042  * @pipe: pipe PLL to enable
6043  * @dpll: PLL configuration
6044  *
6045  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6046  * in cases where we need the PLL enabled even when @pipe is not going to
6047  * be enabled.
6048  */
6049 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6050                       const struct dpll *dpll)
6051 {
6052         struct intel_crtc *crtc =
6053                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6054         struct intel_crtc_config pipe_config = {
6055                 .pixel_multiplier = 1,
6056                 .dpll = *dpll,
6057         };
6058
6059         if (IS_CHERRYVIEW(dev)) {
6060                 chv_update_pll(crtc, &pipe_config);
6061                 chv_prepare_pll(crtc, &pipe_config);
6062                 chv_enable_pll(crtc, &pipe_config);
6063         } else {
6064                 vlv_update_pll(crtc, &pipe_config);
6065                 vlv_prepare_pll(crtc, &pipe_config);
6066                 vlv_enable_pll(crtc, &pipe_config);
6067         }
6068 }
6069
6070 /**
6071  * vlv_force_pll_off - forcibly disable just the PLL
6072  * @dev_priv: i915 private structure
6073  * @pipe: pipe PLL to disable
6074  *
6075  * Disable the PLL for @pipe. To be used in cases where we need
6076  * the PLL enabled even when @pipe is not going to be enabled.
6077  */
6078 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6079 {
6080         if (IS_CHERRYVIEW(dev))
6081                 chv_disable_pll(to_i915(dev), pipe);
6082         else
6083                 vlv_disable_pll(to_i915(dev), pipe);
6084 }
6085
6086 static void i9xx_update_pll(struct intel_crtc *crtc,
6087                             intel_clock_t *reduced_clock,
6088                             int num_connectors)
6089 {
6090         struct drm_device *dev = crtc->base.dev;
6091         struct drm_i915_private *dev_priv = dev->dev_private;
6092         u32 dpll;
6093         bool is_sdvo;
6094         struct dpll *clock = &crtc->new_config->dpll;
6095
6096         i9xx_update_pll_dividers(crtc, reduced_clock);
6097
6098         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6099                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6100
6101         dpll = DPLL_VGA_MODE_DIS;
6102
6103         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6104                 dpll |= DPLLB_MODE_LVDS;
6105         else
6106                 dpll |= DPLLB_MODE_DAC_SERIAL;
6107
6108         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6109                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6110                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6111         }
6112
6113         if (is_sdvo)
6114                 dpll |= DPLL_SDVO_HIGH_SPEED;
6115
6116         if (crtc->new_config->has_dp_encoder)
6117                 dpll |= DPLL_SDVO_HIGH_SPEED;
6118
6119         /* compute bitmask from p1 value */
6120         if (IS_PINEVIEW(dev))
6121                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6122         else {
6123                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6124                 if (IS_G4X(dev) && reduced_clock)
6125                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6126         }
6127         switch (clock->p2) {
6128         case 5:
6129                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6130                 break;
6131         case 7:
6132                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6133                 break;
6134         case 10:
6135                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6136                 break;
6137         case 14:
6138                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6139                 break;
6140         }
6141         if (INTEL_INFO(dev)->gen >= 4)
6142                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6143
6144         if (crtc->new_config->sdvo_tv_clock)
6145                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6146         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6147                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6148                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6149         else
6150                 dpll |= PLL_REF_INPUT_DREFCLK;
6151
6152         dpll |= DPLL_VCO_ENABLE;
6153         crtc->new_config->dpll_hw_state.dpll = dpll;
6154
6155         if (INTEL_INFO(dev)->gen >= 4) {
6156                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6157                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6158                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6159         }
6160 }
6161
6162 static void i8xx_update_pll(struct intel_crtc *crtc,
6163                             intel_clock_t *reduced_clock,
6164                             int num_connectors)
6165 {
6166         struct drm_device *dev = crtc->base.dev;
6167         struct drm_i915_private *dev_priv = dev->dev_private;
6168         u32 dpll;
6169         struct dpll *clock = &crtc->new_config->dpll;
6170
6171         i9xx_update_pll_dividers(crtc, reduced_clock);
6172
6173         dpll = DPLL_VGA_MODE_DIS;
6174
6175         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6176                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6177         } else {
6178                 if (clock->p1 == 2)
6179                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6180                 else
6181                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6182                 if (clock->p2 == 4)
6183                         dpll |= PLL_P2_DIVIDE_BY_4;
6184         }
6185
6186         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6187                 dpll |= DPLL_DVO_2X_MODE;
6188
6189         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6190                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6191                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6192         else
6193                 dpll |= PLL_REF_INPUT_DREFCLK;
6194
6195         dpll |= DPLL_VCO_ENABLE;
6196         crtc->new_config->dpll_hw_state.dpll = dpll;
6197 }
6198
6199 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6200 {
6201         struct drm_device *dev = intel_crtc->base.dev;
6202         struct drm_i915_private *dev_priv = dev->dev_private;
6203         enum pipe pipe = intel_crtc->pipe;
6204         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6205         struct drm_display_mode *adjusted_mode =
6206                 &intel_crtc->config.adjusted_mode;
6207         uint32_t crtc_vtotal, crtc_vblank_end;
6208         int vsyncshift = 0;
6209
6210         /* We need to be careful not to changed the adjusted mode, for otherwise
6211          * the hw state checker will get angry at the mismatch. */
6212         crtc_vtotal = adjusted_mode->crtc_vtotal;
6213         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6214
6215         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6216                 /* the chip adds 2 halflines automatically */
6217                 crtc_vtotal -= 1;
6218                 crtc_vblank_end -= 1;
6219
6220                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6221                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6222                 else
6223                         vsyncshift = adjusted_mode->crtc_hsync_start -
6224                                 adjusted_mode->crtc_htotal / 2;
6225                 if (vsyncshift < 0)
6226                         vsyncshift += adjusted_mode->crtc_htotal;
6227         }
6228
6229         if (INTEL_INFO(dev)->gen > 3)
6230                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6231
6232         I915_WRITE(HTOTAL(cpu_transcoder),
6233                    (adjusted_mode->crtc_hdisplay - 1) |
6234                    ((adjusted_mode->crtc_htotal - 1) << 16));
6235         I915_WRITE(HBLANK(cpu_transcoder),
6236                    (adjusted_mode->crtc_hblank_start - 1) |
6237                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6238         I915_WRITE(HSYNC(cpu_transcoder),
6239                    (adjusted_mode->crtc_hsync_start - 1) |
6240                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6241
6242         I915_WRITE(VTOTAL(cpu_transcoder),
6243                    (adjusted_mode->crtc_vdisplay - 1) |
6244                    ((crtc_vtotal - 1) << 16));
6245         I915_WRITE(VBLANK(cpu_transcoder),
6246                    (adjusted_mode->crtc_vblank_start - 1) |
6247                    ((crtc_vblank_end - 1) << 16));
6248         I915_WRITE(VSYNC(cpu_transcoder),
6249                    (adjusted_mode->crtc_vsync_start - 1) |
6250                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6251
6252         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6253          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6254          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6255          * bits. */
6256         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6257             (pipe == PIPE_B || pipe == PIPE_C))
6258                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6259
6260         /* pipesrc controls the size that is scaled from, which should
6261          * always be the user's requested size.
6262          */
6263         I915_WRITE(PIPESRC(pipe),
6264                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6265                    (intel_crtc->config.pipe_src_h - 1));
6266 }
6267
6268 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6269                                    struct intel_crtc_config *pipe_config)
6270 {
6271         struct drm_device *dev = crtc->base.dev;
6272         struct drm_i915_private *dev_priv = dev->dev_private;
6273         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6274         uint32_t tmp;
6275
6276         tmp = I915_READ(HTOTAL(cpu_transcoder));
6277         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6278         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6279         tmp = I915_READ(HBLANK(cpu_transcoder));
6280         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6281         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6282         tmp = I915_READ(HSYNC(cpu_transcoder));
6283         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6284         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6285
6286         tmp = I915_READ(VTOTAL(cpu_transcoder));
6287         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6288         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6289         tmp = I915_READ(VBLANK(cpu_transcoder));
6290         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6291         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6292         tmp = I915_READ(VSYNC(cpu_transcoder));
6293         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6294         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6295
6296         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6297                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6298                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6299                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6300         }
6301
6302         tmp = I915_READ(PIPESRC(crtc->pipe));
6303         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6304         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6305
6306         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6307         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6308 }
6309
6310 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6311                                  struct intel_crtc_config *pipe_config)
6312 {
6313         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6314         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6315         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6316         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6317
6318         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6319         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6320         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6321         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6322
6323         mode->flags = pipe_config->adjusted_mode.flags;
6324
6325         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6326         mode->flags |= pipe_config->adjusted_mode.flags;
6327 }
6328
6329 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6330 {
6331         struct drm_device *dev = intel_crtc->base.dev;
6332         struct drm_i915_private *dev_priv = dev->dev_private;
6333         uint32_t pipeconf;
6334
6335         pipeconf = 0;
6336
6337         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6338             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6339                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6340
6341         if (intel_crtc->config.double_wide)
6342                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6343
6344         /* only g4x and later have fancy bpc/dither controls */
6345         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6346                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6347                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6348                         pipeconf |= PIPECONF_DITHER_EN |
6349                                     PIPECONF_DITHER_TYPE_SP;
6350
6351                 switch (intel_crtc->config.pipe_bpp) {
6352                 case 18:
6353                         pipeconf |= PIPECONF_6BPC;
6354                         break;
6355                 case 24:
6356                         pipeconf |= PIPECONF_8BPC;
6357                         break;
6358                 case 30:
6359                         pipeconf |= PIPECONF_10BPC;
6360                         break;
6361                 default:
6362                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6363                         BUG();
6364                 }
6365         }
6366
6367         if (HAS_PIPE_CXSR(dev)) {
6368                 if (intel_crtc->lowfreq_avail) {
6369                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6370                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6371                 } else {
6372                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6373                 }
6374         }
6375
6376         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6377                 if (INTEL_INFO(dev)->gen < 4 ||
6378                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6379                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6380                 else
6381                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6382         } else
6383                 pipeconf |= PIPECONF_PROGRESSIVE;
6384
6385         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6386                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6387
6388         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6389         POSTING_READ(PIPECONF(intel_crtc->pipe));
6390 }
6391
6392 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6393 {
6394         struct drm_device *dev = crtc->base.dev;
6395         struct drm_i915_private *dev_priv = dev->dev_private;
6396         int refclk, num_connectors = 0;
6397         intel_clock_t clock, reduced_clock;
6398         bool ok, has_reduced_clock = false;
6399         bool is_lvds = false, is_dsi = false;
6400         struct intel_encoder *encoder;
6401         const intel_limit_t *limit;
6402
6403         for_each_intel_encoder(dev, encoder) {
6404                 if (encoder->new_crtc != crtc)
6405                         continue;
6406
6407                 switch (encoder->type) {
6408                 case INTEL_OUTPUT_LVDS:
6409                         is_lvds = true;
6410                         break;
6411                 case INTEL_OUTPUT_DSI:
6412                         is_dsi = true;
6413                         break;
6414                 default:
6415                         break;
6416                 }
6417
6418                 num_connectors++;
6419         }
6420
6421         if (is_dsi)
6422                 return 0;
6423
6424         if (!crtc->new_config->clock_set) {
6425                 refclk = i9xx_get_refclk(crtc, num_connectors);
6426
6427                 /*
6428                  * Returns a set of divisors for the desired target clock with
6429                  * the given refclk, or FALSE.  The returned values represent
6430                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6431                  * 2) / p1 / p2.
6432                  */
6433                 limit = intel_limit(crtc, refclk);
6434                 ok = dev_priv->display.find_dpll(limit, crtc,
6435                                                  crtc->new_config->port_clock,
6436                                                  refclk, NULL, &clock);
6437                 if (!ok) {
6438                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6439                         return -EINVAL;
6440                 }
6441
6442                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6443                         /*
6444                          * Ensure we match the reduced clock's P to the target
6445                          * clock.  If the clocks don't match, we can't switch
6446                          * the display clock by using the FP0/FP1. In such case
6447                          * we will disable the LVDS downclock feature.
6448                          */
6449                         has_reduced_clock =
6450                                 dev_priv->display.find_dpll(limit, crtc,
6451                                                             dev_priv->lvds_downclock,
6452                                                             refclk, &clock,
6453                                                             &reduced_clock);
6454                 }
6455                 /* Compat-code for transition, will disappear. */
6456                 crtc->new_config->dpll.n = clock.n;
6457                 crtc->new_config->dpll.m1 = clock.m1;
6458                 crtc->new_config->dpll.m2 = clock.m2;
6459                 crtc->new_config->dpll.p1 = clock.p1;
6460                 crtc->new_config->dpll.p2 = clock.p2;
6461         }
6462
6463         if (IS_GEN2(dev)) {
6464                 i8xx_update_pll(crtc,
6465                                 has_reduced_clock ? &reduced_clock : NULL,
6466                                 num_connectors);
6467         } else if (IS_CHERRYVIEW(dev)) {
6468                 chv_update_pll(crtc, crtc->new_config);
6469         } else if (IS_VALLEYVIEW(dev)) {
6470                 vlv_update_pll(crtc, crtc->new_config);
6471         } else {
6472                 i9xx_update_pll(crtc,
6473                                 has_reduced_clock ? &reduced_clock : NULL,
6474                                 num_connectors);
6475         }
6476
6477         return 0;
6478 }
6479
6480 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6481                                  struct intel_crtc_config *pipe_config)
6482 {
6483         struct drm_device *dev = crtc->base.dev;
6484         struct drm_i915_private *dev_priv = dev->dev_private;
6485         uint32_t tmp;
6486
6487         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6488                 return;
6489
6490         tmp = I915_READ(PFIT_CONTROL);
6491         if (!(tmp & PFIT_ENABLE))
6492                 return;
6493
6494         /* Check whether the pfit is attached to our pipe. */
6495         if (INTEL_INFO(dev)->gen < 4) {
6496                 if (crtc->pipe != PIPE_B)
6497                         return;
6498         } else {
6499                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6500                         return;
6501         }
6502
6503         pipe_config->gmch_pfit.control = tmp;
6504         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6505         if (INTEL_INFO(dev)->gen < 5)
6506                 pipe_config->gmch_pfit.lvds_border_bits =
6507                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6508 }
6509
6510 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6511                                struct intel_crtc_config *pipe_config)
6512 {
6513         struct drm_device *dev = crtc->base.dev;
6514         struct drm_i915_private *dev_priv = dev->dev_private;
6515         int pipe = pipe_config->cpu_transcoder;
6516         intel_clock_t clock;
6517         u32 mdiv;
6518         int refclk = 100000;
6519
6520         /* In case of MIPI DPLL will not even be used */
6521         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6522                 return;
6523
6524         mutex_lock(&dev_priv->dpio_lock);
6525         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6526         mutex_unlock(&dev_priv->dpio_lock);
6527
6528         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6529         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6530         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6531         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6532         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6533
6534         vlv_clock(refclk, &clock);
6535
6536         /* clock.dot is the fast clock */
6537         pipe_config->port_clock = clock.dot / 5;
6538 }
6539
6540 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6541                                   struct intel_plane_config *plane_config)
6542 {
6543         struct drm_device *dev = crtc->base.dev;
6544         struct drm_i915_private *dev_priv = dev->dev_private;
6545         u32 val, base, offset;
6546         int pipe = crtc->pipe, plane = crtc->plane;
6547         int fourcc, pixel_format;
6548         int aligned_height;
6549
6550         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6551         if (!crtc->base.primary->fb) {
6552                 DRM_DEBUG_KMS("failed to alloc fb\n");
6553                 return;
6554         }
6555
6556         val = I915_READ(DSPCNTR(plane));
6557
6558         if (INTEL_INFO(dev)->gen >= 4)
6559                 if (val & DISPPLANE_TILED)
6560                         plane_config->tiled = true;
6561
6562         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6563         fourcc = intel_format_to_fourcc(pixel_format);
6564         crtc->base.primary->fb->pixel_format = fourcc;
6565         crtc->base.primary->fb->bits_per_pixel =
6566                 drm_format_plane_cpp(fourcc, 0) * 8;
6567
6568         if (INTEL_INFO(dev)->gen >= 4) {
6569                 if (plane_config->tiled)
6570                         offset = I915_READ(DSPTILEOFF(plane));
6571                 else
6572                         offset = I915_READ(DSPLINOFF(plane));
6573                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6574         } else {
6575                 base = I915_READ(DSPADDR(plane));
6576         }
6577         plane_config->base = base;
6578
6579         val = I915_READ(PIPESRC(pipe));
6580         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6581         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6582
6583         val = I915_READ(DSPSTRIDE(pipe));
6584         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6585
6586         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6587                                             plane_config->tiled);
6588
6589         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6590                                         aligned_height);
6591
6592         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6593                       pipe, plane, crtc->base.primary->fb->width,
6594                       crtc->base.primary->fb->height,
6595                       crtc->base.primary->fb->bits_per_pixel, base,
6596                       crtc->base.primary->fb->pitches[0],
6597                       plane_config->size);
6598
6599 }
6600
6601 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6602                                struct intel_crtc_config *pipe_config)
6603 {
6604         struct drm_device *dev = crtc->base.dev;
6605         struct drm_i915_private *dev_priv = dev->dev_private;
6606         int pipe = pipe_config->cpu_transcoder;
6607         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6608         intel_clock_t clock;
6609         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6610         int refclk = 100000;
6611
6612         mutex_lock(&dev_priv->dpio_lock);
6613         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6614         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6615         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6616         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6617         mutex_unlock(&dev_priv->dpio_lock);
6618
6619         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6620         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6621         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6622         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6623         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6624
6625         chv_clock(refclk, &clock);
6626
6627         /* clock.dot is the fast clock */
6628         pipe_config->port_clock = clock.dot / 5;
6629 }
6630
6631 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6632                                  struct intel_crtc_config *pipe_config)
6633 {
6634         struct drm_device *dev = crtc->base.dev;
6635         struct drm_i915_private *dev_priv = dev->dev_private;
6636         uint32_t tmp;
6637
6638         if (!intel_display_power_is_enabled(dev_priv,
6639                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6640                 return false;
6641
6642         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6643         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6644
6645         tmp = I915_READ(PIPECONF(crtc->pipe));
6646         if (!(tmp & PIPECONF_ENABLE))
6647                 return false;
6648
6649         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6650                 switch (tmp & PIPECONF_BPC_MASK) {
6651                 case PIPECONF_6BPC:
6652                         pipe_config->pipe_bpp = 18;
6653                         break;
6654                 case PIPECONF_8BPC:
6655                         pipe_config->pipe_bpp = 24;
6656                         break;
6657                 case PIPECONF_10BPC:
6658                         pipe_config->pipe_bpp = 30;
6659                         break;
6660                 default:
6661                         break;
6662                 }
6663         }
6664
6665         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6666                 pipe_config->limited_color_range = true;
6667
6668         if (INTEL_INFO(dev)->gen < 4)
6669                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6670
6671         intel_get_pipe_timings(crtc, pipe_config);
6672
6673         i9xx_get_pfit_config(crtc, pipe_config);
6674
6675         if (INTEL_INFO(dev)->gen >= 4) {
6676                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6677                 pipe_config->pixel_multiplier =
6678                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6679                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6680                 pipe_config->dpll_hw_state.dpll_md = tmp;
6681         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6682                 tmp = I915_READ(DPLL(crtc->pipe));
6683                 pipe_config->pixel_multiplier =
6684                         ((tmp & SDVO_MULTIPLIER_MASK)
6685                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6686         } else {
6687                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6688                  * port and will be fixed up in the encoder->get_config
6689                  * function. */
6690                 pipe_config->pixel_multiplier = 1;
6691         }
6692         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6693         if (!IS_VALLEYVIEW(dev)) {
6694                 /*
6695                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6696                  * on 830. Filter it out here so that we don't
6697                  * report errors due to that.
6698                  */
6699                 if (IS_I830(dev))
6700                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6701
6702                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6703                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6704         } else {
6705                 /* Mask out read-only status bits. */
6706                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6707                                                      DPLL_PORTC_READY_MASK |
6708                                                      DPLL_PORTB_READY_MASK);
6709         }
6710
6711         if (IS_CHERRYVIEW(dev))
6712                 chv_crtc_clock_get(crtc, pipe_config);
6713         else if (IS_VALLEYVIEW(dev))
6714                 vlv_crtc_clock_get(crtc, pipe_config);
6715         else
6716                 i9xx_crtc_clock_get(crtc, pipe_config);
6717
6718         return true;
6719 }
6720
6721 static void ironlake_init_pch_refclk(struct drm_device *dev)
6722 {
6723         struct drm_i915_private *dev_priv = dev->dev_private;
6724         struct intel_encoder *encoder;
6725         u32 val, final;
6726         bool has_lvds = false;
6727         bool has_cpu_edp = false;
6728         bool has_panel = false;
6729         bool has_ck505 = false;
6730         bool can_ssc = false;
6731
6732         /* We need to take the global config into account */
6733         for_each_intel_encoder(dev, encoder) {
6734                 switch (encoder->type) {
6735                 case INTEL_OUTPUT_LVDS:
6736                         has_panel = true;
6737                         has_lvds = true;
6738                         break;
6739                 case INTEL_OUTPUT_EDP:
6740                         has_panel = true;
6741                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6742                                 has_cpu_edp = true;
6743                         break;
6744                 default:
6745                         break;
6746                 }
6747         }
6748
6749         if (HAS_PCH_IBX(dev)) {
6750                 has_ck505 = dev_priv->vbt.display_clock_mode;
6751                 can_ssc = has_ck505;
6752         } else {
6753                 has_ck505 = false;
6754                 can_ssc = true;
6755         }
6756
6757         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6758                       has_panel, has_lvds, has_ck505);
6759
6760         /* Ironlake: try to setup display ref clock before DPLL
6761          * enabling. This is only under driver's control after
6762          * PCH B stepping, previous chipset stepping should be
6763          * ignoring this setting.
6764          */
6765         val = I915_READ(PCH_DREF_CONTROL);
6766
6767         /* As we must carefully and slowly disable/enable each source in turn,
6768          * compute the final state we want first and check if we need to
6769          * make any changes at all.
6770          */
6771         final = val;
6772         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6773         if (has_ck505)
6774                 final |= DREF_NONSPREAD_CK505_ENABLE;
6775         else
6776                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6777
6778         final &= ~DREF_SSC_SOURCE_MASK;
6779         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6780         final &= ~DREF_SSC1_ENABLE;
6781
6782         if (has_panel) {
6783                 final |= DREF_SSC_SOURCE_ENABLE;
6784
6785                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6786                         final |= DREF_SSC1_ENABLE;
6787
6788                 if (has_cpu_edp) {
6789                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6790                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6791                         else
6792                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6793                 } else
6794                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6795         } else {
6796                 final |= DREF_SSC_SOURCE_DISABLE;
6797                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6798         }
6799
6800         if (final == val)
6801                 return;
6802
6803         /* Always enable nonspread source */
6804         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6805
6806         if (has_ck505)
6807                 val |= DREF_NONSPREAD_CK505_ENABLE;
6808         else
6809                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6810
6811         if (has_panel) {
6812                 val &= ~DREF_SSC_SOURCE_MASK;
6813                 val |= DREF_SSC_SOURCE_ENABLE;
6814
6815                 /* SSC must be turned on before enabling the CPU output  */
6816                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6817                         DRM_DEBUG_KMS("Using SSC on panel\n");
6818                         val |= DREF_SSC1_ENABLE;
6819                 } else
6820                         val &= ~DREF_SSC1_ENABLE;
6821
6822                 /* Get SSC going before enabling the outputs */
6823                 I915_WRITE(PCH_DREF_CONTROL, val);
6824                 POSTING_READ(PCH_DREF_CONTROL);
6825                 udelay(200);
6826
6827                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6828
6829                 /* Enable CPU source on CPU attached eDP */
6830                 if (has_cpu_edp) {
6831                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6832                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6833                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6834                         } else
6835                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6836                 } else
6837                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6838
6839                 I915_WRITE(PCH_DREF_CONTROL, val);
6840                 POSTING_READ(PCH_DREF_CONTROL);
6841                 udelay(200);
6842         } else {
6843                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6844
6845                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6846
6847                 /* Turn off CPU output */
6848                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6849
6850                 I915_WRITE(PCH_DREF_CONTROL, val);
6851                 POSTING_READ(PCH_DREF_CONTROL);
6852                 udelay(200);
6853
6854                 /* Turn off the SSC source */
6855                 val &= ~DREF_SSC_SOURCE_MASK;
6856                 val |= DREF_SSC_SOURCE_DISABLE;
6857
6858                 /* Turn off SSC1 */
6859                 val &= ~DREF_SSC1_ENABLE;
6860
6861                 I915_WRITE(PCH_DREF_CONTROL, val);
6862                 POSTING_READ(PCH_DREF_CONTROL);
6863                 udelay(200);
6864         }
6865
6866         BUG_ON(val != final);
6867 }
6868
6869 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6870 {
6871         uint32_t tmp;
6872
6873         tmp = I915_READ(SOUTH_CHICKEN2);
6874         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6875         I915_WRITE(SOUTH_CHICKEN2, tmp);
6876
6877         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6878                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6879                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6880
6881         tmp = I915_READ(SOUTH_CHICKEN2);
6882         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6883         I915_WRITE(SOUTH_CHICKEN2, tmp);
6884
6885         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6886                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6887                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6888 }
6889
6890 /* WaMPhyProgramming:hsw */
6891 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6892 {
6893         uint32_t tmp;
6894
6895         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6896         tmp &= ~(0xFF << 24);
6897         tmp |= (0x12 << 24);
6898         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6899
6900         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6901         tmp |= (1 << 11);
6902         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6903
6904         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6905         tmp |= (1 << 11);
6906         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6907
6908         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6909         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6910         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6911
6912         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6913         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6914         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6915
6916         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6917         tmp &= ~(7 << 13);
6918         tmp |= (5 << 13);
6919         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6920
6921         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6922         tmp &= ~(7 << 13);
6923         tmp |= (5 << 13);
6924         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6925
6926         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6927         tmp &= ~0xFF;
6928         tmp |= 0x1C;
6929         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6930
6931         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6932         tmp &= ~0xFF;
6933         tmp |= 0x1C;
6934         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6935
6936         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6937         tmp &= ~(0xFF << 16);
6938         tmp |= (0x1C << 16);
6939         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6940
6941         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6942         tmp &= ~(0xFF << 16);
6943         tmp |= (0x1C << 16);
6944         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6945
6946         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6947         tmp |= (1 << 27);
6948         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6949
6950         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6951         tmp |= (1 << 27);
6952         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6953
6954         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6955         tmp &= ~(0xF << 28);
6956         tmp |= (4 << 28);
6957         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6958
6959         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6960         tmp &= ~(0xF << 28);
6961         tmp |= (4 << 28);
6962         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6963 }
6964
6965 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6966  * Programming" based on the parameters passed:
6967  * - Sequence to enable CLKOUT_DP
6968  * - Sequence to enable CLKOUT_DP without spread
6969  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6970  */
6971 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6972                                  bool with_fdi)
6973 {
6974         struct drm_i915_private *dev_priv = dev->dev_private;
6975         uint32_t reg, tmp;
6976
6977         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6978                 with_spread = true;
6979         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6980                  with_fdi, "LP PCH doesn't have FDI\n"))
6981                 with_fdi = false;
6982
6983         mutex_lock(&dev_priv->dpio_lock);
6984
6985         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6986         tmp &= ~SBI_SSCCTL_DISABLE;
6987         tmp |= SBI_SSCCTL_PATHALT;
6988         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6989
6990         udelay(24);
6991
6992         if (with_spread) {
6993                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6994                 tmp &= ~SBI_SSCCTL_PATHALT;
6995                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6996
6997                 if (with_fdi) {
6998                         lpt_reset_fdi_mphy(dev_priv);
6999                         lpt_program_fdi_mphy(dev_priv);
7000                 }
7001         }
7002
7003         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7004                SBI_GEN0 : SBI_DBUFF0;
7005         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7006         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7007         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7008
7009         mutex_unlock(&dev_priv->dpio_lock);
7010 }
7011
7012 /* Sequence to disable CLKOUT_DP */
7013 static void lpt_disable_clkout_dp(struct drm_device *dev)
7014 {
7015         struct drm_i915_private *dev_priv = dev->dev_private;
7016         uint32_t reg, tmp;
7017
7018         mutex_lock(&dev_priv->dpio_lock);
7019
7020         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7021                SBI_GEN0 : SBI_DBUFF0;
7022         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7023         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7024         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7025
7026         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7027         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7028                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7029                         tmp |= SBI_SSCCTL_PATHALT;
7030                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7031                         udelay(32);
7032                 }
7033                 tmp |= SBI_SSCCTL_DISABLE;
7034                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7035         }
7036
7037         mutex_unlock(&dev_priv->dpio_lock);
7038 }
7039
7040 static void lpt_init_pch_refclk(struct drm_device *dev)
7041 {
7042         struct intel_encoder *encoder;
7043         bool has_vga = false;
7044
7045         for_each_intel_encoder(dev, encoder) {
7046                 switch (encoder->type) {
7047                 case INTEL_OUTPUT_ANALOG:
7048                         has_vga = true;
7049                         break;
7050                 default:
7051                         break;
7052                 }
7053         }
7054
7055         if (has_vga)
7056                 lpt_enable_clkout_dp(dev, true, true);
7057         else
7058                 lpt_disable_clkout_dp(dev);
7059 }
7060
7061 /*
7062  * Initialize reference clocks when the driver loads
7063  */
7064 void intel_init_pch_refclk(struct drm_device *dev)
7065 {
7066         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7067                 ironlake_init_pch_refclk(dev);
7068         else if (HAS_PCH_LPT(dev))
7069                 lpt_init_pch_refclk(dev);
7070 }
7071
7072 static int ironlake_get_refclk(struct drm_crtc *crtc)
7073 {
7074         struct drm_device *dev = crtc->dev;
7075         struct drm_i915_private *dev_priv = dev->dev_private;
7076         struct intel_encoder *encoder;
7077         int num_connectors = 0;
7078         bool is_lvds = false;
7079
7080         for_each_intel_encoder(dev, encoder) {
7081                 if (encoder->new_crtc != to_intel_crtc(crtc))
7082                         continue;
7083
7084                 switch (encoder->type) {
7085                 case INTEL_OUTPUT_LVDS:
7086                         is_lvds = true;
7087                         break;
7088                 default:
7089                         break;
7090                 }
7091                 num_connectors++;
7092         }
7093
7094         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7095                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7096                               dev_priv->vbt.lvds_ssc_freq);
7097                 return dev_priv->vbt.lvds_ssc_freq;
7098         }
7099
7100         return 120000;
7101 }
7102
7103 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7104 {
7105         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7107         int pipe = intel_crtc->pipe;
7108         uint32_t val;
7109
7110         val = 0;
7111
7112         switch (intel_crtc->config.pipe_bpp) {
7113         case 18:
7114                 val |= PIPECONF_6BPC;
7115                 break;
7116         case 24:
7117                 val |= PIPECONF_8BPC;
7118                 break;
7119         case 30:
7120                 val |= PIPECONF_10BPC;
7121                 break;
7122         case 36:
7123                 val |= PIPECONF_12BPC;
7124                 break;
7125         default:
7126                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7127                 BUG();
7128         }
7129
7130         if (intel_crtc->config.dither)
7131                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7132
7133         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7134                 val |= PIPECONF_INTERLACED_ILK;
7135         else
7136                 val |= PIPECONF_PROGRESSIVE;
7137
7138         if (intel_crtc->config.limited_color_range)
7139                 val |= PIPECONF_COLOR_RANGE_SELECT;
7140
7141         I915_WRITE(PIPECONF(pipe), val);
7142         POSTING_READ(PIPECONF(pipe));
7143 }
7144
7145 /*
7146  * Set up the pipe CSC unit.
7147  *
7148  * Currently only full range RGB to limited range RGB conversion
7149  * is supported, but eventually this should handle various
7150  * RGB<->YCbCr scenarios as well.
7151  */
7152 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7153 {
7154         struct drm_device *dev = crtc->dev;
7155         struct drm_i915_private *dev_priv = dev->dev_private;
7156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7157         int pipe = intel_crtc->pipe;
7158         uint16_t coeff = 0x7800; /* 1.0 */
7159
7160         /*
7161          * TODO: Check what kind of values actually come out of the pipe
7162          * with these coeff/postoff values and adjust to get the best
7163          * accuracy. Perhaps we even need to take the bpc value into
7164          * consideration.
7165          */
7166
7167         if (intel_crtc->config.limited_color_range)
7168                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7169
7170         /*
7171          * GY/GU and RY/RU should be the other way around according
7172          * to BSpec, but reality doesn't agree. Just set them up in
7173          * a way that results in the correct picture.
7174          */
7175         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7176         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7177
7178         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7179         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7180
7181         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7182         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7183
7184         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7185         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7186         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7187
7188         if (INTEL_INFO(dev)->gen > 6) {
7189                 uint16_t postoff = 0;
7190
7191                 if (intel_crtc->config.limited_color_range)
7192                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7193
7194                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7195                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7196                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7197
7198                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7199         } else {
7200                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7201
7202                 if (intel_crtc->config.limited_color_range)
7203                         mode |= CSC_BLACK_SCREEN_OFFSET;
7204
7205                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7206         }
7207 }
7208
7209 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7210 {
7211         struct drm_device *dev = crtc->dev;
7212         struct drm_i915_private *dev_priv = dev->dev_private;
7213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7214         enum pipe pipe = intel_crtc->pipe;
7215         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7216         uint32_t val;
7217
7218         val = 0;
7219
7220         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7221                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7222
7223         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7224                 val |= PIPECONF_INTERLACED_ILK;
7225         else
7226                 val |= PIPECONF_PROGRESSIVE;
7227
7228         I915_WRITE(PIPECONF(cpu_transcoder), val);
7229         POSTING_READ(PIPECONF(cpu_transcoder));
7230
7231         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7232         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7233
7234         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7235                 val = 0;
7236
7237                 switch (intel_crtc->config.pipe_bpp) {
7238                 case 18:
7239                         val |= PIPEMISC_DITHER_6_BPC;
7240                         break;
7241                 case 24:
7242                         val |= PIPEMISC_DITHER_8_BPC;
7243                         break;
7244                 case 30:
7245                         val |= PIPEMISC_DITHER_10_BPC;
7246                         break;
7247                 case 36:
7248                         val |= PIPEMISC_DITHER_12_BPC;
7249                         break;
7250                 default:
7251                         /* Case prevented by pipe_config_set_bpp. */
7252                         BUG();
7253                 }
7254
7255                 if (intel_crtc->config.dither)
7256                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7257
7258                 I915_WRITE(PIPEMISC(pipe), val);
7259         }
7260 }
7261
7262 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7263                                     intel_clock_t *clock,
7264                                     bool *has_reduced_clock,
7265                                     intel_clock_t *reduced_clock)
7266 {
7267         struct drm_device *dev = crtc->dev;
7268         struct drm_i915_private *dev_priv = dev->dev_private;
7269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7270         int refclk;
7271         const intel_limit_t *limit;
7272         bool ret, is_lvds = false;
7273
7274         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7275
7276         refclk = ironlake_get_refclk(crtc);
7277
7278         /*
7279          * Returns a set of divisors for the desired target clock with the given
7280          * refclk, or FALSE.  The returned values represent the clock equation:
7281          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7282          */
7283         limit = intel_limit(intel_crtc, refclk);
7284         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7285                                           intel_crtc->new_config->port_clock,
7286                                           refclk, NULL, clock);
7287         if (!ret)
7288                 return false;
7289
7290         if (is_lvds && dev_priv->lvds_downclock_avail) {
7291                 /*
7292                  * Ensure we match the reduced clock's P to the target clock.
7293                  * If the clocks don't match, we can't switch the display clock
7294                  * by using the FP0/FP1. In such case we will disable the LVDS
7295                  * downclock feature.
7296                 */
7297                 *has_reduced_clock =
7298                         dev_priv->display.find_dpll(limit, intel_crtc,
7299                                                     dev_priv->lvds_downclock,
7300                                                     refclk, clock,
7301                                                     reduced_clock);
7302         }
7303
7304         return true;
7305 }
7306
7307 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7308 {
7309         /*
7310          * Account for spread spectrum to avoid
7311          * oversubscribing the link. Max center spread
7312          * is 2.5%; use 5% for safety's sake.
7313          */
7314         u32 bps = target_clock * bpp * 21 / 20;
7315         return DIV_ROUND_UP(bps, link_bw * 8);
7316 }
7317
7318 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7319 {
7320         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7321 }
7322
7323 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7324                                       u32 *fp,
7325                                       intel_clock_t *reduced_clock, u32 *fp2)
7326 {
7327         struct drm_crtc *crtc = &intel_crtc->base;
7328         struct drm_device *dev = crtc->dev;
7329         struct drm_i915_private *dev_priv = dev->dev_private;
7330         struct intel_encoder *intel_encoder;
7331         uint32_t dpll;
7332         int factor, num_connectors = 0;
7333         bool is_lvds = false, is_sdvo = false;
7334
7335         for_each_intel_encoder(dev, intel_encoder) {
7336                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7337                         continue;
7338
7339                 switch (intel_encoder->type) {
7340                 case INTEL_OUTPUT_LVDS:
7341                         is_lvds = true;
7342                         break;
7343                 case INTEL_OUTPUT_SDVO:
7344                 case INTEL_OUTPUT_HDMI:
7345                         is_sdvo = true;
7346                         break;
7347                 default:
7348                         break;
7349                 }
7350
7351                 num_connectors++;
7352         }
7353
7354         /* Enable autotuning of the PLL clock (if permissible) */
7355         factor = 21;
7356         if (is_lvds) {
7357                 if ((intel_panel_use_ssc(dev_priv) &&
7358                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7359                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7360                         factor = 25;
7361         } else if (intel_crtc->new_config->sdvo_tv_clock)
7362                 factor = 20;
7363
7364         if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7365                 *fp |= FP_CB_TUNE;
7366
7367         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7368                 *fp2 |= FP_CB_TUNE;
7369
7370         dpll = 0;
7371
7372         if (is_lvds)
7373                 dpll |= DPLLB_MODE_LVDS;
7374         else
7375                 dpll |= DPLLB_MODE_DAC_SERIAL;
7376
7377         dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7378                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7379
7380         if (is_sdvo)
7381                 dpll |= DPLL_SDVO_HIGH_SPEED;
7382         if (intel_crtc->new_config->has_dp_encoder)
7383                 dpll |= DPLL_SDVO_HIGH_SPEED;
7384
7385         /* compute bitmask from p1 value */
7386         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7387         /* also FPA1 */
7388         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7389
7390         switch (intel_crtc->new_config->dpll.p2) {
7391         case 5:
7392                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7393                 break;
7394         case 7:
7395                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7396                 break;
7397         case 10:
7398                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7399                 break;
7400         case 14:
7401                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7402                 break;
7403         }
7404
7405         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7406                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7407         else
7408                 dpll |= PLL_REF_INPUT_DREFCLK;
7409
7410         return dpll | DPLL_VCO_ENABLE;
7411 }
7412
7413 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7414 {
7415         struct drm_device *dev = crtc->base.dev;
7416         intel_clock_t clock, reduced_clock;
7417         u32 dpll = 0, fp = 0, fp2 = 0;
7418         bool ok, has_reduced_clock = false;
7419         bool is_lvds = false;
7420         struct intel_shared_dpll *pll;
7421
7422         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7423
7424         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7425              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7426
7427         ok = ironlake_compute_clocks(&crtc->base, &clock,
7428                                      &has_reduced_clock, &reduced_clock);
7429         if (!ok && !crtc->new_config->clock_set) {
7430                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7431                 return -EINVAL;
7432         }
7433         /* Compat-code for transition, will disappear. */
7434         if (!crtc->new_config->clock_set) {
7435                 crtc->new_config->dpll.n = clock.n;
7436                 crtc->new_config->dpll.m1 = clock.m1;
7437                 crtc->new_config->dpll.m2 = clock.m2;
7438                 crtc->new_config->dpll.p1 = clock.p1;
7439                 crtc->new_config->dpll.p2 = clock.p2;
7440         }
7441
7442         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7443         if (crtc->new_config->has_pch_encoder) {
7444                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7445                 if (has_reduced_clock)
7446                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7447
7448                 dpll = ironlake_compute_dpll(crtc,
7449                                              &fp, &reduced_clock,
7450                                              has_reduced_clock ? &fp2 : NULL);
7451
7452                 crtc->new_config->dpll_hw_state.dpll = dpll;
7453                 crtc->new_config->dpll_hw_state.fp0 = fp;
7454                 if (has_reduced_clock)
7455                         crtc->new_config->dpll_hw_state.fp1 = fp2;
7456                 else
7457                         crtc->new_config->dpll_hw_state.fp1 = fp;
7458
7459                 pll = intel_get_shared_dpll(crtc);
7460                 if (pll == NULL) {
7461                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7462                                          pipe_name(crtc->pipe));
7463                         return -EINVAL;
7464                 }
7465         }
7466
7467         if (is_lvds && has_reduced_clock && i915.powersave)
7468                 crtc->lowfreq_avail = true;
7469         else
7470                 crtc->lowfreq_avail = false;
7471
7472         return 0;
7473 }
7474
7475 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7476                                          struct intel_link_m_n *m_n)
7477 {
7478         struct drm_device *dev = crtc->base.dev;
7479         struct drm_i915_private *dev_priv = dev->dev_private;
7480         enum pipe pipe = crtc->pipe;
7481
7482         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7483         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7484         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7485                 & ~TU_SIZE_MASK;
7486         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7487         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7488                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7489 }
7490
7491 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7492                                          enum transcoder transcoder,
7493                                          struct intel_link_m_n *m_n,
7494                                          struct intel_link_m_n *m2_n2)
7495 {
7496         struct drm_device *dev = crtc->base.dev;
7497         struct drm_i915_private *dev_priv = dev->dev_private;
7498         enum pipe pipe = crtc->pipe;
7499
7500         if (INTEL_INFO(dev)->gen >= 5) {
7501                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7502                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7503                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7504                         & ~TU_SIZE_MASK;
7505                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7506                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7507                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7508                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7509                  * gen < 8) and if DRRS is supported (to make sure the
7510                  * registers are not unnecessarily read).
7511                  */
7512                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7513                         crtc->config.has_drrs) {
7514                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7515                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7516                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7517                                         & ~TU_SIZE_MASK;
7518                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7519                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7520                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7521                 }
7522         } else {
7523                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7524                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7525                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7526                         & ~TU_SIZE_MASK;
7527                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7528                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7529                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7530         }
7531 }
7532
7533 void intel_dp_get_m_n(struct intel_crtc *crtc,
7534                       struct intel_crtc_config *pipe_config)
7535 {
7536         if (crtc->config.has_pch_encoder)
7537                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7538         else
7539                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7540                                              &pipe_config->dp_m_n,
7541                                              &pipe_config->dp_m2_n2);
7542 }
7543
7544 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7545                                         struct intel_crtc_config *pipe_config)
7546 {
7547         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7548                                      &pipe_config->fdi_m_n, NULL);
7549 }
7550
7551 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7552                                     struct intel_crtc_config *pipe_config)
7553 {
7554         struct drm_device *dev = crtc->base.dev;
7555         struct drm_i915_private *dev_priv = dev->dev_private;
7556         uint32_t tmp;
7557
7558         tmp = I915_READ(PS_CTL(crtc->pipe));
7559
7560         if (tmp & PS_ENABLE) {
7561                 pipe_config->pch_pfit.enabled = true;
7562                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7563                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7564         }
7565 }
7566
7567 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7568                                      struct intel_crtc_config *pipe_config)
7569 {
7570         struct drm_device *dev = crtc->base.dev;
7571         struct drm_i915_private *dev_priv = dev->dev_private;
7572         uint32_t tmp;
7573
7574         tmp = I915_READ(PF_CTL(crtc->pipe));
7575
7576         if (tmp & PF_ENABLE) {
7577                 pipe_config->pch_pfit.enabled = true;
7578                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7579                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7580
7581                 /* We currently do not free assignements of panel fitters on
7582                  * ivb/hsw (since we don't use the higher upscaling modes which
7583                  * differentiates them) so just WARN about this case for now. */
7584                 if (IS_GEN7(dev)) {
7585                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7586                                 PF_PIPE_SEL_IVB(crtc->pipe));
7587                 }
7588         }
7589 }
7590
7591 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7592                                       struct intel_plane_config *plane_config)
7593 {
7594         struct drm_device *dev = crtc->base.dev;
7595         struct drm_i915_private *dev_priv = dev->dev_private;
7596         u32 val, base, offset;
7597         int pipe = crtc->pipe, plane = crtc->plane;
7598         int fourcc, pixel_format;
7599         int aligned_height;
7600
7601         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7602         if (!crtc->base.primary->fb) {
7603                 DRM_DEBUG_KMS("failed to alloc fb\n");
7604                 return;
7605         }
7606
7607         val = I915_READ(DSPCNTR(plane));
7608
7609         if (INTEL_INFO(dev)->gen >= 4)
7610                 if (val & DISPPLANE_TILED)
7611                         plane_config->tiled = true;
7612
7613         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7614         fourcc = intel_format_to_fourcc(pixel_format);
7615         crtc->base.primary->fb->pixel_format = fourcc;
7616         crtc->base.primary->fb->bits_per_pixel =
7617                 drm_format_plane_cpp(fourcc, 0) * 8;
7618
7619         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7620         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7621                 offset = I915_READ(DSPOFFSET(plane));
7622         } else {
7623                 if (plane_config->tiled)
7624                         offset = I915_READ(DSPTILEOFF(plane));
7625                 else
7626                         offset = I915_READ(DSPLINOFF(plane));
7627         }
7628         plane_config->base = base;
7629
7630         val = I915_READ(PIPESRC(pipe));
7631         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7632         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7633
7634         val = I915_READ(DSPSTRIDE(pipe));
7635         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7636
7637         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7638                                             plane_config->tiled);
7639
7640         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7641                                         aligned_height);
7642
7643         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7644                       pipe, plane, crtc->base.primary->fb->width,
7645                       crtc->base.primary->fb->height,
7646                       crtc->base.primary->fb->bits_per_pixel, base,
7647                       crtc->base.primary->fb->pitches[0],
7648                       plane_config->size);
7649 }
7650
7651 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7652                                      struct intel_crtc_config *pipe_config)
7653 {
7654         struct drm_device *dev = crtc->base.dev;
7655         struct drm_i915_private *dev_priv = dev->dev_private;
7656         uint32_t tmp;
7657
7658         if (!intel_display_power_is_enabled(dev_priv,
7659                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7660                 return false;
7661
7662         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7663         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7664
7665         tmp = I915_READ(PIPECONF(crtc->pipe));
7666         if (!(tmp & PIPECONF_ENABLE))
7667                 return false;
7668
7669         switch (tmp & PIPECONF_BPC_MASK) {
7670         case PIPECONF_6BPC:
7671                 pipe_config->pipe_bpp = 18;
7672                 break;
7673         case PIPECONF_8BPC:
7674                 pipe_config->pipe_bpp = 24;
7675                 break;
7676         case PIPECONF_10BPC:
7677                 pipe_config->pipe_bpp = 30;
7678                 break;
7679         case PIPECONF_12BPC:
7680                 pipe_config->pipe_bpp = 36;
7681                 break;
7682         default:
7683                 break;
7684         }
7685
7686         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7687                 pipe_config->limited_color_range = true;
7688
7689         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7690                 struct intel_shared_dpll *pll;
7691
7692                 pipe_config->has_pch_encoder = true;
7693
7694                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7695                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7696                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7697
7698                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7699
7700                 if (HAS_PCH_IBX(dev_priv->dev)) {
7701                         pipe_config->shared_dpll =
7702                                 (enum intel_dpll_id) crtc->pipe;
7703                 } else {
7704                         tmp = I915_READ(PCH_DPLL_SEL);
7705                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7706                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7707                         else
7708                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7709                 }
7710
7711                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7712
7713                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7714                                            &pipe_config->dpll_hw_state));
7715
7716                 tmp = pipe_config->dpll_hw_state.dpll;
7717                 pipe_config->pixel_multiplier =
7718                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7719                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7720
7721                 ironlake_pch_clock_get(crtc, pipe_config);
7722         } else {
7723                 pipe_config->pixel_multiplier = 1;
7724         }
7725
7726         intel_get_pipe_timings(crtc, pipe_config);
7727
7728         ironlake_get_pfit_config(crtc, pipe_config);
7729
7730         return true;
7731 }
7732
7733 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7734 {
7735         struct drm_device *dev = dev_priv->dev;
7736         struct intel_crtc *crtc;
7737
7738         for_each_intel_crtc(dev, crtc)
7739                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7740                      pipe_name(crtc->pipe));
7741
7742         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7743         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7744         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7745         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7746         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7747         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7748              "CPU PWM1 enabled\n");
7749         if (IS_HASWELL(dev))
7750                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7751                      "CPU PWM2 enabled\n");
7752         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7753              "PCH PWM1 enabled\n");
7754         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7755              "Utility pin enabled\n");
7756         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7757
7758         /*
7759          * In theory we can still leave IRQs enabled, as long as only the HPD
7760          * interrupts remain enabled. We used to check for that, but since it's
7761          * gen-specific and since we only disable LCPLL after we fully disable
7762          * the interrupts, the check below should be enough.
7763          */
7764         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7765 }
7766
7767 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7768 {
7769         struct drm_device *dev = dev_priv->dev;
7770
7771         if (IS_HASWELL(dev))
7772                 return I915_READ(D_COMP_HSW);
7773         else
7774                 return I915_READ(D_COMP_BDW);
7775 }
7776
7777 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7778 {
7779         struct drm_device *dev = dev_priv->dev;
7780
7781         if (IS_HASWELL(dev)) {
7782                 mutex_lock(&dev_priv->rps.hw_lock);
7783                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7784                                             val))
7785                         DRM_ERROR("Failed to write to D_COMP\n");
7786                 mutex_unlock(&dev_priv->rps.hw_lock);
7787         } else {
7788                 I915_WRITE(D_COMP_BDW, val);
7789                 POSTING_READ(D_COMP_BDW);
7790         }
7791 }
7792
7793 /*
7794  * This function implements pieces of two sequences from BSpec:
7795  * - Sequence for display software to disable LCPLL
7796  * - Sequence for display software to allow package C8+
7797  * The steps implemented here are just the steps that actually touch the LCPLL
7798  * register. Callers should take care of disabling all the display engine
7799  * functions, doing the mode unset, fixing interrupts, etc.
7800  */
7801 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7802                               bool switch_to_fclk, bool allow_power_down)
7803 {
7804         uint32_t val;
7805
7806         assert_can_disable_lcpll(dev_priv);
7807
7808         val = I915_READ(LCPLL_CTL);
7809
7810         if (switch_to_fclk) {
7811                 val |= LCPLL_CD_SOURCE_FCLK;
7812                 I915_WRITE(LCPLL_CTL, val);
7813
7814                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7815                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7816                         DRM_ERROR("Switching to FCLK failed\n");
7817
7818                 val = I915_READ(LCPLL_CTL);
7819         }
7820
7821         val |= LCPLL_PLL_DISABLE;
7822         I915_WRITE(LCPLL_CTL, val);
7823         POSTING_READ(LCPLL_CTL);
7824
7825         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7826                 DRM_ERROR("LCPLL still locked\n");
7827
7828         val = hsw_read_dcomp(dev_priv);
7829         val |= D_COMP_COMP_DISABLE;
7830         hsw_write_dcomp(dev_priv, val);
7831         ndelay(100);
7832
7833         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7834                      1))
7835                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7836
7837         if (allow_power_down) {
7838                 val = I915_READ(LCPLL_CTL);
7839                 val |= LCPLL_POWER_DOWN_ALLOW;
7840                 I915_WRITE(LCPLL_CTL, val);
7841                 POSTING_READ(LCPLL_CTL);
7842         }
7843 }
7844
7845 /*
7846  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7847  * source.
7848  */
7849 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7850 {
7851         uint32_t val;
7852
7853         val = I915_READ(LCPLL_CTL);
7854
7855         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7856                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7857                 return;
7858
7859         /*
7860          * Make sure we're not on PC8 state before disabling PC8, otherwise
7861          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7862          *
7863          * The other problem is that hsw_restore_lcpll() is called as part of
7864          * the runtime PM resume sequence, so we can't just call
7865          * gen6_gt_force_wake_get() because that function calls
7866          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7867          * while we are on the resume sequence. So to solve this problem we have
7868          * to call special forcewake code that doesn't touch runtime PM and
7869          * doesn't enable the forcewake delayed work.
7870          */
7871         spin_lock_irq(&dev_priv->uncore.lock);
7872         if (dev_priv->uncore.forcewake_count++ == 0)
7873                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7874         spin_unlock_irq(&dev_priv->uncore.lock);
7875
7876         if (val & LCPLL_POWER_DOWN_ALLOW) {
7877                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7878                 I915_WRITE(LCPLL_CTL, val);
7879                 POSTING_READ(LCPLL_CTL);
7880         }
7881
7882         val = hsw_read_dcomp(dev_priv);
7883         val |= D_COMP_COMP_FORCE;
7884         val &= ~D_COMP_COMP_DISABLE;
7885         hsw_write_dcomp(dev_priv, val);
7886
7887         val = I915_READ(LCPLL_CTL);
7888         val &= ~LCPLL_PLL_DISABLE;
7889         I915_WRITE(LCPLL_CTL, val);
7890
7891         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7892                 DRM_ERROR("LCPLL not locked yet\n");
7893
7894         if (val & LCPLL_CD_SOURCE_FCLK) {
7895                 val = I915_READ(LCPLL_CTL);
7896                 val &= ~LCPLL_CD_SOURCE_FCLK;
7897                 I915_WRITE(LCPLL_CTL, val);
7898
7899                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7900                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7901                         DRM_ERROR("Switching back to LCPLL failed\n");
7902         }
7903
7904         /* See the big comment above. */
7905         spin_lock_irq(&dev_priv->uncore.lock);
7906         if (--dev_priv->uncore.forcewake_count == 0)
7907                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7908         spin_unlock_irq(&dev_priv->uncore.lock);
7909 }
7910
7911 /*
7912  * Package states C8 and deeper are really deep PC states that can only be
7913  * reached when all the devices on the system allow it, so even if the graphics
7914  * device allows PC8+, it doesn't mean the system will actually get to these
7915  * states. Our driver only allows PC8+ when going into runtime PM.
7916  *
7917  * The requirements for PC8+ are that all the outputs are disabled, the power
7918  * well is disabled and most interrupts are disabled, and these are also
7919  * requirements for runtime PM. When these conditions are met, we manually do
7920  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7921  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7922  * hang the machine.
7923  *
7924  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7925  * the state of some registers, so when we come back from PC8+ we need to
7926  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7927  * need to take care of the registers kept by RC6. Notice that this happens even
7928  * if we don't put the device in PCI D3 state (which is what currently happens
7929  * because of the runtime PM support).
7930  *
7931  * For more, read "Display Sequences for Package C8" on the hardware
7932  * documentation.
7933  */
7934 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7935 {
7936         struct drm_device *dev = dev_priv->dev;
7937         uint32_t val;
7938
7939         DRM_DEBUG_KMS("Enabling package C8+\n");
7940
7941         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7942                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7943                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7944                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7945         }
7946
7947         lpt_disable_clkout_dp(dev);
7948         hsw_disable_lcpll(dev_priv, true, true);
7949 }
7950
7951 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7952 {
7953         struct drm_device *dev = dev_priv->dev;
7954         uint32_t val;
7955
7956         DRM_DEBUG_KMS("Disabling package C8+\n");
7957
7958         hsw_restore_lcpll(dev_priv);
7959         lpt_init_pch_refclk(dev);
7960
7961         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7962                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7963                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7964                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7965         }
7966
7967         intel_prepare_ddi(dev);
7968 }
7969
7970 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7971 {
7972         if (!intel_ddi_pll_select(crtc))
7973                 return -EINVAL;
7974
7975         crtc->lowfreq_avail = false;
7976
7977         return 0;
7978 }
7979
7980 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
7981                                 enum port port,
7982                                 struct intel_crtc_config *pipe_config)
7983 {
7984         u32 temp, dpll_ctl1;
7985
7986         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
7987         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
7988
7989         switch (pipe_config->ddi_pll_sel) {
7990         case SKL_DPLL0:
7991                 /*
7992                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
7993                  * of the shared DPLL framework and thus needs to be read out
7994                  * separately
7995                  */
7996                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
7997                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
7998                 break;
7999         case SKL_DPLL1:
8000                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8001                 break;
8002         case SKL_DPLL2:
8003                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8004                 break;
8005         case SKL_DPLL3:
8006                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8007                 break;
8008         }
8009 }
8010
8011 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8012                                 enum port port,
8013                                 struct intel_crtc_config *pipe_config)
8014 {
8015         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8016
8017         switch (pipe_config->ddi_pll_sel) {
8018         case PORT_CLK_SEL_WRPLL1:
8019                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8020                 break;
8021         case PORT_CLK_SEL_WRPLL2:
8022                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8023                 break;
8024         }
8025 }
8026
8027 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8028                                        struct intel_crtc_config *pipe_config)
8029 {
8030         struct drm_device *dev = crtc->base.dev;
8031         struct drm_i915_private *dev_priv = dev->dev_private;
8032         struct intel_shared_dpll *pll;
8033         enum port port;
8034         uint32_t tmp;
8035
8036         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8037
8038         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8039
8040         if (IS_SKYLAKE(dev))
8041                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8042         else
8043                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8044
8045         if (pipe_config->shared_dpll >= 0) {
8046                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8047
8048                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8049                                            &pipe_config->dpll_hw_state));
8050         }
8051
8052         /*
8053          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8054          * DDI E. So just check whether this pipe is wired to DDI E and whether
8055          * the PCH transcoder is on.
8056          */
8057         if (INTEL_INFO(dev)->gen < 9 &&
8058             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8059                 pipe_config->has_pch_encoder = true;
8060
8061                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8062                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8063                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8064
8065                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8066         }
8067 }
8068
8069 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8070                                     struct intel_crtc_config *pipe_config)
8071 {
8072         struct drm_device *dev = crtc->base.dev;
8073         struct drm_i915_private *dev_priv = dev->dev_private;
8074         enum intel_display_power_domain pfit_domain;
8075         uint32_t tmp;
8076
8077         if (!intel_display_power_is_enabled(dev_priv,
8078                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8079                 return false;
8080
8081         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8082         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8083
8084         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8085         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8086                 enum pipe trans_edp_pipe;
8087                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8088                 default:
8089                         WARN(1, "unknown pipe linked to edp transcoder\n");
8090                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8091                 case TRANS_DDI_EDP_INPUT_A_ON:
8092                         trans_edp_pipe = PIPE_A;
8093                         break;
8094                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8095                         trans_edp_pipe = PIPE_B;
8096                         break;
8097                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8098                         trans_edp_pipe = PIPE_C;
8099                         break;
8100                 }
8101
8102                 if (trans_edp_pipe == crtc->pipe)
8103                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8104         }
8105
8106         if (!intel_display_power_is_enabled(dev_priv,
8107                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8108                 return false;
8109
8110         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8111         if (!(tmp & PIPECONF_ENABLE))
8112                 return false;
8113
8114         haswell_get_ddi_port_state(crtc, pipe_config);
8115
8116         intel_get_pipe_timings(crtc, pipe_config);
8117
8118         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8119         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8120                 if (IS_SKYLAKE(dev))
8121                         skylake_get_pfit_config(crtc, pipe_config);
8122                 else
8123                         ironlake_get_pfit_config(crtc, pipe_config);
8124         }
8125
8126         if (IS_HASWELL(dev))
8127                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8128                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8129
8130         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8131                 pipe_config->pixel_multiplier =
8132                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8133         } else {
8134                 pipe_config->pixel_multiplier = 1;
8135         }
8136
8137         return true;
8138 }
8139
8140 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8141 {
8142         struct drm_device *dev = crtc->dev;
8143         struct drm_i915_private *dev_priv = dev->dev_private;
8144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8145         uint32_t cntl = 0, size = 0;
8146
8147         if (base) {
8148                 unsigned int width = intel_crtc->cursor_width;
8149                 unsigned int height = intel_crtc->cursor_height;
8150                 unsigned int stride = roundup_pow_of_two(width) * 4;
8151
8152                 switch (stride) {
8153                 default:
8154                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8155                                   width, stride);
8156                         stride = 256;
8157                         /* fallthrough */
8158                 case 256:
8159                 case 512:
8160                 case 1024:
8161                 case 2048:
8162                         break;
8163                 }
8164
8165                 cntl |= CURSOR_ENABLE |
8166                         CURSOR_GAMMA_ENABLE |
8167                         CURSOR_FORMAT_ARGB |
8168                         CURSOR_STRIDE(stride);
8169
8170                 size = (height << 12) | width;
8171         }
8172
8173         if (intel_crtc->cursor_cntl != 0 &&
8174             (intel_crtc->cursor_base != base ||
8175              intel_crtc->cursor_size != size ||
8176              intel_crtc->cursor_cntl != cntl)) {
8177                 /* On these chipsets we can only modify the base/size/stride
8178                  * whilst the cursor is disabled.
8179                  */
8180                 I915_WRITE(_CURACNTR, 0);
8181                 POSTING_READ(_CURACNTR);
8182                 intel_crtc->cursor_cntl = 0;
8183         }
8184
8185         if (intel_crtc->cursor_base != base) {
8186                 I915_WRITE(_CURABASE, base);
8187                 intel_crtc->cursor_base = base;
8188         }
8189
8190         if (intel_crtc->cursor_size != size) {
8191                 I915_WRITE(CURSIZE, size);
8192                 intel_crtc->cursor_size = size;
8193         }
8194
8195         if (intel_crtc->cursor_cntl != cntl) {
8196                 I915_WRITE(_CURACNTR, cntl);
8197                 POSTING_READ(_CURACNTR);
8198                 intel_crtc->cursor_cntl = cntl;
8199         }
8200 }
8201
8202 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8203 {
8204         struct drm_device *dev = crtc->dev;
8205         struct drm_i915_private *dev_priv = dev->dev_private;
8206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8207         int pipe = intel_crtc->pipe;
8208         uint32_t cntl;
8209
8210         cntl = 0;
8211         if (base) {
8212                 cntl = MCURSOR_GAMMA_ENABLE;
8213                 switch (intel_crtc->cursor_width) {
8214                         case 64:
8215                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8216                                 break;
8217                         case 128:
8218                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8219                                 break;
8220                         case 256:
8221                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8222                                 break;
8223                         default:
8224                                 MISSING_CASE(intel_crtc->cursor_width);
8225                                 return;
8226                 }
8227                 cntl |= pipe << 28; /* Connect to correct pipe */
8228
8229                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8230                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8231         }
8232
8233         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8234                 cntl |= CURSOR_ROTATE_180;
8235
8236         if (intel_crtc->cursor_cntl != cntl) {
8237                 I915_WRITE(CURCNTR(pipe), cntl);
8238                 POSTING_READ(CURCNTR(pipe));
8239                 intel_crtc->cursor_cntl = cntl;
8240         }
8241
8242         /* and commit changes on next vblank */
8243         I915_WRITE(CURBASE(pipe), base);
8244         POSTING_READ(CURBASE(pipe));
8245
8246         intel_crtc->cursor_base = base;
8247 }
8248
8249 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8250 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8251                                      bool on)
8252 {
8253         struct drm_device *dev = crtc->dev;
8254         struct drm_i915_private *dev_priv = dev->dev_private;
8255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8256         int pipe = intel_crtc->pipe;
8257         int x = crtc->cursor_x;
8258         int y = crtc->cursor_y;
8259         u32 base = 0, pos = 0;
8260
8261         if (on)
8262                 base = intel_crtc->cursor_addr;
8263
8264         if (x >= intel_crtc->config.pipe_src_w)
8265                 base = 0;
8266
8267         if (y >= intel_crtc->config.pipe_src_h)
8268                 base = 0;
8269
8270         if (x < 0) {
8271                 if (x + intel_crtc->cursor_width <= 0)
8272                         base = 0;
8273
8274                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8275                 x = -x;
8276         }
8277         pos |= x << CURSOR_X_SHIFT;
8278
8279         if (y < 0) {
8280                 if (y + intel_crtc->cursor_height <= 0)
8281                         base = 0;
8282
8283                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8284                 y = -y;
8285         }
8286         pos |= y << CURSOR_Y_SHIFT;
8287
8288         if (base == 0 && intel_crtc->cursor_base == 0)
8289                 return;
8290
8291         I915_WRITE(CURPOS(pipe), pos);
8292
8293         /* ILK+ do this automagically */
8294         if (HAS_GMCH_DISPLAY(dev) &&
8295                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8296                 base += (intel_crtc->cursor_height *
8297                         intel_crtc->cursor_width - 1) * 4;
8298         }
8299
8300         if (IS_845G(dev) || IS_I865G(dev))
8301                 i845_update_cursor(crtc, base);
8302         else
8303                 i9xx_update_cursor(crtc, base);
8304 }
8305
8306 static bool cursor_size_ok(struct drm_device *dev,
8307                            uint32_t width, uint32_t height)
8308 {
8309         if (width == 0 || height == 0)
8310                 return false;
8311
8312         /*
8313          * 845g/865g are special in that they are only limited by
8314          * the width of their cursors, the height is arbitrary up to
8315          * the precision of the register. Everything else requires
8316          * square cursors, limited to a few power-of-two sizes.
8317          */
8318         if (IS_845G(dev) || IS_I865G(dev)) {
8319                 if ((width & 63) != 0)
8320                         return false;
8321
8322                 if (width > (IS_845G(dev) ? 64 : 512))
8323                         return false;
8324
8325                 if (height > 1023)
8326                         return false;
8327         } else {
8328                 switch (width | height) {
8329                 case 256:
8330                 case 128:
8331                         if (IS_GEN2(dev))
8332                                 return false;
8333                 case 64:
8334                         break;
8335                 default:
8336                         return false;
8337                 }
8338         }
8339
8340         return true;
8341 }
8342
8343 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8344                                  u16 *blue, uint32_t start, uint32_t size)
8345 {
8346         int end = (start + size > 256) ? 256 : start + size, i;
8347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8348
8349         for (i = start; i < end; i++) {
8350                 intel_crtc->lut_r[i] = red[i] >> 8;
8351                 intel_crtc->lut_g[i] = green[i] >> 8;
8352                 intel_crtc->lut_b[i] = blue[i] >> 8;
8353         }
8354
8355         intel_crtc_load_lut(crtc);
8356 }
8357
8358 /* VESA 640x480x72Hz mode to set on the pipe */
8359 static struct drm_display_mode load_detect_mode = {
8360         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8361                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8362 };
8363
8364 struct drm_framebuffer *
8365 __intel_framebuffer_create(struct drm_device *dev,
8366                            struct drm_mode_fb_cmd2 *mode_cmd,
8367                            struct drm_i915_gem_object *obj)
8368 {
8369         struct intel_framebuffer *intel_fb;
8370         int ret;
8371
8372         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8373         if (!intel_fb) {
8374                 drm_gem_object_unreference(&obj->base);
8375                 return ERR_PTR(-ENOMEM);
8376         }
8377
8378         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8379         if (ret)
8380                 goto err;
8381
8382         return &intel_fb->base;
8383 err:
8384         drm_gem_object_unreference(&obj->base);
8385         kfree(intel_fb);
8386
8387         return ERR_PTR(ret);
8388 }
8389
8390 static struct drm_framebuffer *
8391 intel_framebuffer_create(struct drm_device *dev,
8392                          struct drm_mode_fb_cmd2 *mode_cmd,
8393                          struct drm_i915_gem_object *obj)
8394 {
8395         struct drm_framebuffer *fb;
8396         int ret;
8397
8398         ret = i915_mutex_lock_interruptible(dev);
8399         if (ret)
8400                 return ERR_PTR(ret);
8401         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8402         mutex_unlock(&dev->struct_mutex);
8403
8404         return fb;
8405 }
8406
8407 static u32
8408 intel_framebuffer_pitch_for_width(int width, int bpp)
8409 {
8410         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8411         return ALIGN(pitch, 64);
8412 }
8413
8414 static u32
8415 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8416 {
8417         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8418         return PAGE_ALIGN(pitch * mode->vdisplay);
8419 }
8420
8421 static struct drm_framebuffer *
8422 intel_framebuffer_create_for_mode(struct drm_device *dev,
8423                                   struct drm_display_mode *mode,
8424                                   int depth, int bpp)
8425 {
8426         struct drm_i915_gem_object *obj;
8427         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8428
8429         obj = i915_gem_alloc_object(dev,
8430                                     intel_framebuffer_size_for_mode(mode, bpp));
8431         if (obj == NULL)
8432                 return ERR_PTR(-ENOMEM);
8433
8434         mode_cmd.width = mode->hdisplay;
8435         mode_cmd.height = mode->vdisplay;
8436         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8437                                                                 bpp);
8438         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8439
8440         return intel_framebuffer_create(dev, &mode_cmd, obj);
8441 }
8442
8443 static struct drm_framebuffer *
8444 mode_fits_in_fbdev(struct drm_device *dev,
8445                    struct drm_display_mode *mode)
8446 {
8447 #ifdef CONFIG_DRM_I915_FBDEV
8448         struct drm_i915_private *dev_priv = dev->dev_private;
8449         struct drm_i915_gem_object *obj;
8450         struct drm_framebuffer *fb;
8451
8452         if (!dev_priv->fbdev)
8453                 return NULL;
8454
8455         if (!dev_priv->fbdev->fb)
8456                 return NULL;
8457
8458         obj = dev_priv->fbdev->fb->obj;
8459         BUG_ON(!obj);
8460
8461         fb = &dev_priv->fbdev->fb->base;
8462         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8463                                                                fb->bits_per_pixel))
8464                 return NULL;
8465
8466         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8467                 return NULL;
8468
8469         return fb;
8470 #else
8471         return NULL;
8472 #endif
8473 }
8474
8475 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8476                                 struct drm_display_mode *mode,
8477                                 struct intel_load_detect_pipe *old,
8478                                 struct drm_modeset_acquire_ctx *ctx)
8479 {
8480         struct intel_crtc *intel_crtc;
8481         struct intel_encoder *intel_encoder =
8482                 intel_attached_encoder(connector);
8483         struct drm_crtc *possible_crtc;
8484         struct drm_encoder *encoder = &intel_encoder->base;
8485         struct drm_crtc *crtc = NULL;
8486         struct drm_device *dev = encoder->dev;
8487         struct drm_framebuffer *fb;
8488         struct drm_mode_config *config = &dev->mode_config;
8489         int ret, i = -1;
8490
8491         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8492                       connector->base.id, connector->name,
8493                       encoder->base.id, encoder->name);
8494
8495 retry:
8496         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8497         if (ret)
8498                 goto fail_unlock;
8499
8500         /*
8501          * Algorithm gets a little messy:
8502          *
8503          *   - if the connector already has an assigned crtc, use it (but make
8504          *     sure it's on first)
8505          *
8506          *   - try to find the first unused crtc that can drive this connector,
8507          *     and use that if we find one
8508          */
8509
8510         /* See if we already have a CRTC for this connector */
8511         if (encoder->crtc) {
8512                 crtc = encoder->crtc;
8513
8514                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8515                 if (ret)
8516                         goto fail_unlock;
8517                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8518                 if (ret)
8519                         goto fail_unlock;
8520
8521                 old->dpms_mode = connector->dpms;
8522                 old->load_detect_temp = false;
8523
8524                 /* Make sure the crtc and connector are running */
8525                 if (connector->dpms != DRM_MODE_DPMS_ON)
8526                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8527
8528                 return true;
8529         }
8530
8531         /* Find an unused one (if possible) */
8532         for_each_crtc(dev, possible_crtc) {
8533                 i++;
8534                 if (!(encoder->possible_crtcs & (1 << i)))
8535                         continue;
8536                 if (possible_crtc->enabled)
8537                         continue;
8538                 /* This can occur when applying the pipe A quirk on resume. */
8539                 if (to_intel_crtc(possible_crtc)->new_enabled)
8540                         continue;
8541
8542                 crtc = possible_crtc;
8543                 break;
8544         }
8545
8546         /*
8547          * If we didn't find an unused CRTC, don't use any.
8548          */
8549         if (!crtc) {
8550                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8551                 goto fail_unlock;
8552         }
8553
8554         ret = drm_modeset_lock(&crtc->mutex, ctx);
8555         if (ret)
8556                 goto fail_unlock;
8557         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8558         if (ret)
8559                 goto fail_unlock;
8560         intel_encoder->new_crtc = to_intel_crtc(crtc);
8561         to_intel_connector(connector)->new_encoder = intel_encoder;
8562
8563         intel_crtc = to_intel_crtc(crtc);
8564         intel_crtc->new_enabled = true;
8565         intel_crtc->new_config = &intel_crtc->config;
8566         old->dpms_mode = connector->dpms;
8567         old->load_detect_temp = true;
8568         old->release_fb = NULL;
8569
8570         if (!mode)
8571                 mode = &load_detect_mode;
8572
8573         /* We need a framebuffer large enough to accommodate all accesses
8574          * that the plane may generate whilst we perform load detection.
8575          * We can not rely on the fbcon either being present (we get called
8576          * during its initialisation to detect all boot displays, or it may
8577          * not even exist) or that it is large enough to satisfy the
8578          * requested mode.
8579          */
8580         fb = mode_fits_in_fbdev(dev, mode);
8581         if (fb == NULL) {
8582                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8583                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8584                 old->release_fb = fb;
8585         } else
8586                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8587         if (IS_ERR(fb)) {
8588                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8589                 goto fail;
8590         }
8591
8592         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8593                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8594                 if (old->release_fb)
8595                         old->release_fb->funcs->destroy(old->release_fb);
8596                 goto fail;
8597         }
8598
8599         /* let the connector get through one full cycle before testing */
8600         intel_wait_for_vblank(dev, intel_crtc->pipe);
8601         return true;
8602
8603  fail:
8604         intel_crtc->new_enabled = crtc->enabled;
8605         if (intel_crtc->new_enabled)
8606                 intel_crtc->new_config = &intel_crtc->config;
8607         else
8608                 intel_crtc->new_config = NULL;
8609 fail_unlock:
8610         if (ret == -EDEADLK) {
8611                 drm_modeset_backoff(ctx);
8612                 goto retry;
8613         }
8614
8615         return false;
8616 }
8617
8618 void intel_release_load_detect_pipe(struct drm_connector *connector,
8619                                     struct intel_load_detect_pipe *old)
8620 {
8621         struct intel_encoder *intel_encoder =
8622                 intel_attached_encoder(connector);
8623         struct drm_encoder *encoder = &intel_encoder->base;
8624         struct drm_crtc *crtc = encoder->crtc;
8625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8626
8627         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8628                       connector->base.id, connector->name,
8629                       encoder->base.id, encoder->name);
8630
8631         if (old->load_detect_temp) {
8632                 to_intel_connector(connector)->new_encoder = NULL;
8633                 intel_encoder->new_crtc = NULL;
8634                 intel_crtc->new_enabled = false;
8635                 intel_crtc->new_config = NULL;
8636                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8637
8638                 if (old->release_fb) {
8639                         drm_framebuffer_unregister_private(old->release_fb);
8640                         drm_framebuffer_unreference(old->release_fb);
8641                 }
8642
8643                 return;
8644         }
8645
8646         /* Switch crtc and encoder back off if necessary */
8647         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8648                 connector->funcs->dpms(connector, old->dpms_mode);
8649 }
8650
8651 static int i9xx_pll_refclk(struct drm_device *dev,
8652                            const struct intel_crtc_config *pipe_config)
8653 {
8654         struct drm_i915_private *dev_priv = dev->dev_private;
8655         u32 dpll = pipe_config->dpll_hw_state.dpll;
8656
8657         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8658                 return dev_priv->vbt.lvds_ssc_freq;
8659         else if (HAS_PCH_SPLIT(dev))
8660                 return 120000;
8661         else if (!IS_GEN2(dev))
8662                 return 96000;
8663         else
8664                 return 48000;
8665 }
8666
8667 /* Returns the clock of the currently programmed mode of the given pipe. */
8668 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8669                                 struct intel_crtc_config *pipe_config)
8670 {
8671         struct drm_device *dev = crtc->base.dev;
8672         struct drm_i915_private *dev_priv = dev->dev_private;
8673         int pipe = pipe_config->cpu_transcoder;
8674         u32 dpll = pipe_config->dpll_hw_state.dpll;
8675         u32 fp;
8676         intel_clock_t clock;
8677         int refclk = i9xx_pll_refclk(dev, pipe_config);
8678
8679         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8680                 fp = pipe_config->dpll_hw_state.fp0;
8681         else
8682                 fp = pipe_config->dpll_hw_state.fp1;
8683
8684         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8685         if (IS_PINEVIEW(dev)) {
8686                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8687                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8688         } else {
8689                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8690                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8691         }
8692
8693         if (!IS_GEN2(dev)) {
8694                 if (IS_PINEVIEW(dev))
8695                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8696                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8697                 else
8698                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8699                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8700
8701                 switch (dpll & DPLL_MODE_MASK) {
8702                 case DPLLB_MODE_DAC_SERIAL:
8703                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8704                                 5 : 10;
8705                         break;
8706                 case DPLLB_MODE_LVDS:
8707                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8708                                 7 : 14;
8709                         break;
8710                 default:
8711                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8712                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8713                         return;
8714                 }
8715
8716                 if (IS_PINEVIEW(dev))
8717                         pineview_clock(refclk, &clock);
8718                 else
8719                         i9xx_clock(refclk, &clock);
8720         } else {
8721                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8722                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8723
8724                 if (is_lvds) {
8725                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8726                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8727
8728                         if (lvds & LVDS_CLKB_POWER_UP)
8729                                 clock.p2 = 7;
8730                         else
8731                                 clock.p2 = 14;
8732                 } else {
8733                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8734                                 clock.p1 = 2;
8735                         else {
8736                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8737                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8738                         }
8739                         if (dpll & PLL_P2_DIVIDE_BY_4)
8740                                 clock.p2 = 4;
8741                         else
8742                                 clock.p2 = 2;
8743                 }
8744
8745                 i9xx_clock(refclk, &clock);
8746         }
8747
8748         /*
8749          * This value includes pixel_multiplier. We will use
8750          * port_clock to compute adjusted_mode.crtc_clock in the
8751          * encoder's get_config() function.
8752          */
8753         pipe_config->port_clock = clock.dot;
8754 }
8755
8756 int intel_dotclock_calculate(int link_freq,
8757                              const struct intel_link_m_n *m_n)
8758 {
8759         /*
8760          * The calculation for the data clock is:
8761          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8762          * But we want to avoid losing precison if possible, so:
8763          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8764          *
8765          * and the link clock is simpler:
8766          * link_clock = (m * link_clock) / n
8767          */
8768
8769         if (!m_n->link_n)
8770                 return 0;
8771
8772         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8773 }
8774
8775 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8776                                    struct intel_crtc_config *pipe_config)
8777 {
8778         struct drm_device *dev = crtc->base.dev;
8779
8780         /* read out port_clock from the DPLL */
8781         i9xx_crtc_clock_get(crtc, pipe_config);
8782
8783         /*
8784          * This value does not include pixel_multiplier.
8785          * We will check that port_clock and adjusted_mode.crtc_clock
8786          * agree once we know their relationship in the encoder's
8787          * get_config() function.
8788          */
8789         pipe_config->adjusted_mode.crtc_clock =
8790                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8791                                          &pipe_config->fdi_m_n);
8792 }
8793
8794 /** Returns the currently programmed mode of the given pipe. */
8795 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8796                                              struct drm_crtc *crtc)
8797 {
8798         struct drm_i915_private *dev_priv = dev->dev_private;
8799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8800         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8801         struct drm_display_mode *mode;
8802         struct intel_crtc_config pipe_config;
8803         int htot = I915_READ(HTOTAL(cpu_transcoder));
8804         int hsync = I915_READ(HSYNC(cpu_transcoder));
8805         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8806         int vsync = I915_READ(VSYNC(cpu_transcoder));
8807         enum pipe pipe = intel_crtc->pipe;
8808
8809         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8810         if (!mode)
8811                 return NULL;
8812
8813         /*
8814          * Construct a pipe_config sufficient for getting the clock info
8815          * back out of crtc_clock_get.
8816          *
8817          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8818          * to use a real value here instead.
8819          */
8820         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8821         pipe_config.pixel_multiplier = 1;
8822         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8823         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8824         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8825         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8826
8827         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8828         mode->hdisplay = (htot & 0xffff) + 1;
8829         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8830         mode->hsync_start = (hsync & 0xffff) + 1;
8831         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8832         mode->vdisplay = (vtot & 0xffff) + 1;
8833         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8834         mode->vsync_start = (vsync & 0xffff) + 1;
8835         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8836
8837         drm_mode_set_name(mode);
8838
8839         return mode;
8840 }
8841
8842 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8843 {
8844         struct drm_device *dev = crtc->dev;
8845         struct drm_i915_private *dev_priv = dev->dev_private;
8846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8847
8848         if (!HAS_GMCH_DISPLAY(dev))
8849                 return;
8850
8851         if (!dev_priv->lvds_downclock_avail)
8852                 return;
8853
8854         /*
8855          * Since this is called by a timer, we should never get here in
8856          * the manual case.
8857          */
8858         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8859                 int pipe = intel_crtc->pipe;
8860                 int dpll_reg = DPLL(pipe);
8861                 int dpll;
8862
8863                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8864
8865                 assert_panel_unlocked(dev_priv, pipe);
8866
8867                 dpll = I915_READ(dpll_reg);
8868                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8869                 I915_WRITE(dpll_reg, dpll);
8870                 intel_wait_for_vblank(dev, pipe);
8871                 dpll = I915_READ(dpll_reg);
8872                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8873                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8874         }
8875
8876 }
8877
8878 void intel_mark_busy(struct drm_device *dev)
8879 {
8880         struct drm_i915_private *dev_priv = dev->dev_private;
8881
8882         if (dev_priv->mm.busy)
8883                 return;
8884
8885         intel_runtime_pm_get(dev_priv);
8886         i915_update_gfx_val(dev_priv);
8887         dev_priv->mm.busy = true;
8888 }
8889
8890 void intel_mark_idle(struct drm_device *dev)
8891 {
8892         struct drm_i915_private *dev_priv = dev->dev_private;
8893         struct drm_crtc *crtc;
8894
8895         if (!dev_priv->mm.busy)
8896                 return;
8897
8898         dev_priv->mm.busy = false;
8899
8900         if (!i915.powersave)
8901                 goto out;
8902
8903         for_each_crtc(dev, crtc) {
8904                 if (!crtc->primary->fb)
8905                         continue;
8906
8907                 intel_decrease_pllclock(crtc);
8908         }
8909
8910         if (INTEL_INFO(dev)->gen >= 6)
8911                 gen6_rps_idle(dev->dev_private);
8912
8913 out:
8914         intel_runtime_pm_put(dev_priv);
8915 }
8916
8917 static void intel_crtc_destroy(struct drm_crtc *crtc)
8918 {
8919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8920         struct drm_device *dev = crtc->dev;
8921         struct intel_unpin_work *work;
8922
8923         spin_lock_irq(&dev->event_lock);
8924         work = intel_crtc->unpin_work;
8925         intel_crtc->unpin_work = NULL;
8926         spin_unlock_irq(&dev->event_lock);
8927
8928         if (work) {
8929                 cancel_work_sync(&work->work);
8930                 kfree(work);
8931         }
8932
8933         drm_crtc_cleanup(crtc);
8934
8935         kfree(intel_crtc);
8936 }
8937
8938 static void intel_unpin_work_fn(struct work_struct *__work)
8939 {
8940         struct intel_unpin_work *work =
8941                 container_of(__work, struct intel_unpin_work, work);
8942         struct drm_device *dev = work->crtc->dev;
8943         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8944
8945         mutex_lock(&dev->struct_mutex);
8946         intel_unpin_fb_obj(work->old_fb_obj);
8947         drm_gem_object_unreference(&work->pending_flip_obj->base);
8948         drm_gem_object_unreference(&work->old_fb_obj->base);
8949
8950         intel_fbc_update(dev);
8951
8952         if (work->flip_queued_req)
8953                 i915_gem_request_assign(&work->flip_queued_req, NULL);
8954         mutex_unlock(&dev->struct_mutex);
8955
8956         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8957
8958         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8959         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8960
8961         kfree(work);
8962 }
8963
8964 static void do_intel_finish_page_flip(struct drm_device *dev,
8965                                       struct drm_crtc *crtc)
8966 {
8967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8968         struct intel_unpin_work *work;
8969         unsigned long flags;
8970
8971         /* Ignore early vblank irqs */
8972         if (intel_crtc == NULL)
8973                 return;
8974
8975         /*
8976          * This is called both by irq handlers and the reset code (to complete
8977          * lost pageflips) so needs the full irqsave spinlocks.
8978          */
8979         spin_lock_irqsave(&dev->event_lock, flags);
8980         work = intel_crtc->unpin_work;
8981
8982         /* Ensure we don't miss a work->pending update ... */
8983         smp_rmb();
8984
8985         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8986                 spin_unlock_irqrestore(&dev->event_lock, flags);
8987                 return;
8988         }
8989
8990         page_flip_completed(intel_crtc);
8991
8992         spin_unlock_irqrestore(&dev->event_lock, flags);
8993 }
8994
8995 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8996 {
8997         struct drm_i915_private *dev_priv = dev->dev_private;
8998         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8999
9000         do_intel_finish_page_flip(dev, crtc);
9001 }
9002
9003 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9004 {
9005         struct drm_i915_private *dev_priv = dev->dev_private;
9006         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9007
9008         do_intel_finish_page_flip(dev, crtc);
9009 }
9010
9011 /* Is 'a' after or equal to 'b'? */
9012 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9013 {
9014         return !((a - b) & 0x80000000);
9015 }
9016
9017 static bool page_flip_finished(struct intel_crtc *crtc)
9018 {
9019         struct drm_device *dev = crtc->base.dev;
9020         struct drm_i915_private *dev_priv = dev->dev_private;
9021
9022         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9023             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9024                 return true;
9025
9026         /*
9027          * The relevant registers doen't exist on pre-ctg.
9028          * As the flip done interrupt doesn't trigger for mmio
9029          * flips on gmch platforms, a flip count check isn't
9030          * really needed there. But since ctg has the registers,
9031          * include it in the check anyway.
9032          */
9033         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9034                 return true;
9035
9036         /*
9037          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9038          * used the same base address. In that case the mmio flip might
9039          * have completed, but the CS hasn't even executed the flip yet.
9040          *
9041          * A flip count check isn't enough as the CS might have updated
9042          * the base address just after start of vblank, but before we
9043          * managed to process the interrupt. This means we'd complete the
9044          * CS flip too soon.
9045          *
9046          * Combining both checks should get us a good enough result. It may
9047          * still happen that the CS flip has been executed, but has not
9048          * yet actually completed. But in case the base address is the same
9049          * anyway, we don't really care.
9050          */
9051         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9052                 crtc->unpin_work->gtt_offset &&
9053                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9054                                     crtc->unpin_work->flip_count);
9055 }
9056
9057 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9058 {
9059         struct drm_i915_private *dev_priv = dev->dev_private;
9060         struct intel_crtc *intel_crtc =
9061                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9062         unsigned long flags;
9063
9064
9065         /*
9066          * This is called both by irq handlers and the reset code (to complete
9067          * lost pageflips) so needs the full irqsave spinlocks.
9068          *
9069          * NB: An MMIO update of the plane base pointer will also
9070          * generate a page-flip completion irq, i.e. every modeset
9071          * is also accompanied by a spurious intel_prepare_page_flip().
9072          */
9073         spin_lock_irqsave(&dev->event_lock, flags);
9074         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9075                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9076         spin_unlock_irqrestore(&dev->event_lock, flags);
9077 }
9078
9079 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9080 {
9081         /* Ensure that the work item is consistent when activating it ... */
9082         smp_wmb();
9083         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9084         /* and that it is marked active as soon as the irq could fire. */
9085         smp_wmb();
9086 }
9087
9088 static int intel_gen2_queue_flip(struct drm_device *dev,
9089                                  struct drm_crtc *crtc,
9090                                  struct drm_framebuffer *fb,
9091                                  struct drm_i915_gem_object *obj,
9092                                  struct intel_engine_cs *ring,
9093                                  uint32_t flags)
9094 {
9095         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9096         u32 flip_mask;
9097         int ret;
9098
9099         ret = intel_ring_begin(ring, 6);
9100         if (ret)
9101                 return ret;
9102
9103         /* Can't queue multiple flips, so wait for the previous
9104          * one to finish before executing the next.
9105          */
9106         if (intel_crtc->plane)
9107                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9108         else
9109                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9110         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9111         intel_ring_emit(ring, MI_NOOP);
9112         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9113                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9114         intel_ring_emit(ring, fb->pitches[0]);
9115         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9116         intel_ring_emit(ring, 0); /* aux display base address, unused */
9117
9118         intel_mark_page_flip_active(intel_crtc);
9119         __intel_ring_advance(ring);
9120         return 0;
9121 }
9122
9123 static int intel_gen3_queue_flip(struct drm_device *dev,
9124                                  struct drm_crtc *crtc,
9125                                  struct drm_framebuffer *fb,
9126                                  struct drm_i915_gem_object *obj,
9127                                  struct intel_engine_cs *ring,
9128                                  uint32_t flags)
9129 {
9130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9131         u32 flip_mask;
9132         int ret;
9133
9134         ret = intel_ring_begin(ring, 6);
9135         if (ret)
9136                 return ret;
9137
9138         if (intel_crtc->plane)
9139                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9140         else
9141                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9142         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9143         intel_ring_emit(ring, MI_NOOP);
9144         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9145                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9146         intel_ring_emit(ring, fb->pitches[0]);
9147         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9148         intel_ring_emit(ring, MI_NOOP);
9149
9150         intel_mark_page_flip_active(intel_crtc);
9151         __intel_ring_advance(ring);
9152         return 0;
9153 }
9154
9155 static int intel_gen4_queue_flip(struct drm_device *dev,
9156                                  struct drm_crtc *crtc,
9157                                  struct drm_framebuffer *fb,
9158                                  struct drm_i915_gem_object *obj,
9159                                  struct intel_engine_cs *ring,
9160                                  uint32_t flags)
9161 {
9162         struct drm_i915_private *dev_priv = dev->dev_private;
9163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9164         uint32_t pf, pipesrc;
9165         int ret;
9166
9167         ret = intel_ring_begin(ring, 4);
9168         if (ret)
9169                 return ret;
9170
9171         /* i965+ uses the linear or tiled offsets from the
9172          * Display Registers (which do not change across a page-flip)
9173          * so we need only reprogram the base address.
9174          */
9175         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9176                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9177         intel_ring_emit(ring, fb->pitches[0]);
9178         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9179                         obj->tiling_mode);
9180
9181         /* XXX Enabling the panel-fitter across page-flip is so far
9182          * untested on non-native modes, so ignore it for now.
9183          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9184          */
9185         pf = 0;
9186         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9187         intel_ring_emit(ring, pf | pipesrc);
9188
9189         intel_mark_page_flip_active(intel_crtc);
9190         __intel_ring_advance(ring);
9191         return 0;
9192 }
9193
9194 static int intel_gen6_queue_flip(struct drm_device *dev,
9195                                  struct drm_crtc *crtc,
9196                                  struct drm_framebuffer *fb,
9197                                  struct drm_i915_gem_object *obj,
9198                                  struct intel_engine_cs *ring,
9199                                  uint32_t flags)
9200 {
9201         struct drm_i915_private *dev_priv = dev->dev_private;
9202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9203         uint32_t pf, pipesrc;
9204         int ret;
9205
9206         ret = intel_ring_begin(ring, 4);
9207         if (ret)
9208                 return ret;
9209
9210         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9211                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9212         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9213         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9214
9215         /* Contrary to the suggestions in the documentation,
9216          * "Enable Panel Fitter" does not seem to be required when page
9217          * flipping with a non-native mode, and worse causes a normal
9218          * modeset to fail.
9219          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9220          */
9221         pf = 0;
9222         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9223         intel_ring_emit(ring, pf | pipesrc);
9224
9225         intel_mark_page_flip_active(intel_crtc);
9226         __intel_ring_advance(ring);
9227         return 0;
9228 }
9229
9230 static int intel_gen7_queue_flip(struct drm_device *dev,
9231                                  struct drm_crtc *crtc,
9232                                  struct drm_framebuffer *fb,
9233                                  struct drm_i915_gem_object *obj,
9234                                  struct intel_engine_cs *ring,
9235                                  uint32_t flags)
9236 {
9237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9238         uint32_t plane_bit = 0;
9239         int len, ret;
9240
9241         switch (intel_crtc->plane) {
9242         case PLANE_A:
9243                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9244                 break;
9245         case PLANE_B:
9246                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9247                 break;
9248         case PLANE_C:
9249                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9250                 break;
9251         default:
9252                 WARN_ONCE(1, "unknown plane in flip command\n");
9253                 return -ENODEV;
9254         }
9255
9256         len = 4;
9257         if (ring->id == RCS) {
9258                 len += 6;
9259                 /*
9260                  * On Gen 8, SRM is now taking an extra dword to accommodate
9261                  * 48bits addresses, and we need a NOOP for the batch size to
9262                  * stay even.
9263                  */
9264                 if (IS_GEN8(dev))
9265                         len += 2;
9266         }
9267
9268         /*
9269          * BSpec MI_DISPLAY_FLIP for IVB:
9270          * "The full packet must be contained within the same cache line."
9271          *
9272          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9273          * cacheline, if we ever start emitting more commands before
9274          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9275          * then do the cacheline alignment, and finally emit the
9276          * MI_DISPLAY_FLIP.
9277          */
9278         ret = intel_ring_cacheline_align(ring);
9279         if (ret)
9280                 return ret;
9281
9282         ret = intel_ring_begin(ring, len);
9283         if (ret)
9284                 return ret;
9285
9286         /* Unmask the flip-done completion message. Note that the bspec says that
9287          * we should do this for both the BCS and RCS, and that we must not unmask
9288          * more than one flip event at any time (or ensure that one flip message
9289          * can be sent by waiting for flip-done prior to queueing new flips).
9290          * Experimentation says that BCS works despite DERRMR masking all
9291          * flip-done completion events and that unmasking all planes at once
9292          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9293          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9294          */
9295         if (ring->id == RCS) {
9296                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9297                 intel_ring_emit(ring, DERRMR);
9298                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9299                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9300                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9301                 if (IS_GEN8(dev))
9302                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9303                                               MI_SRM_LRM_GLOBAL_GTT);
9304                 else
9305                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9306                                               MI_SRM_LRM_GLOBAL_GTT);
9307                 intel_ring_emit(ring, DERRMR);
9308                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9309                 if (IS_GEN8(dev)) {
9310                         intel_ring_emit(ring, 0);
9311                         intel_ring_emit(ring, MI_NOOP);
9312                 }
9313         }
9314
9315         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9316         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9317         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9318         intel_ring_emit(ring, (MI_NOOP));
9319
9320         intel_mark_page_flip_active(intel_crtc);
9321         __intel_ring_advance(ring);
9322         return 0;
9323 }
9324
9325 static bool use_mmio_flip(struct intel_engine_cs *ring,
9326                           struct drm_i915_gem_object *obj)
9327 {
9328         /*
9329          * This is not being used for older platforms, because
9330          * non-availability of flip done interrupt forces us to use
9331          * CS flips. Older platforms derive flip done using some clever
9332          * tricks involving the flip_pending status bits and vblank irqs.
9333          * So using MMIO flips there would disrupt this mechanism.
9334          */
9335
9336         if (ring == NULL)
9337                 return true;
9338
9339         if (INTEL_INFO(ring->dev)->gen < 5)
9340                 return false;
9341
9342         if (i915.use_mmio_flip < 0)
9343                 return false;
9344         else if (i915.use_mmio_flip > 0)
9345                 return true;
9346         else if (i915.enable_execlists)
9347                 return true;
9348         else
9349                 return ring != i915_gem_request_get_ring(obj->last_read_req);
9350 }
9351
9352 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9353 {
9354         struct drm_device *dev = intel_crtc->base.dev;
9355         struct drm_i915_private *dev_priv = dev->dev_private;
9356         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9357         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9358         struct drm_i915_gem_object *obj = intel_fb->obj;
9359         const enum pipe pipe = intel_crtc->pipe;
9360         u32 ctl, stride;
9361
9362         ctl = I915_READ(PLANE_CTL(pipe, 0));
9363         ctl &= ~PLANE_CTL_TILED_MASK;
9364         if (obj->tiling_mode == I915_TILING_X)
9365                 ctl |= PLANE_CTL_TILED_X;
9366
9367         /*
9368          * The stride is either expressed as a multiple of 64 bytes chunks for
9369          * linear buffers or in number of tiles for tiled buffers.
9370          */
9371         stride = fb->pitches[0] >> 6;
9372         if (obj->tiling_mode == I915_TILING_X)
9373                 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9374
9375         /*
9376          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9377          * PLANE_SURF updates, the update is then guaranteed to be atomic.
9378          */
9379         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9380         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9381
9382         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9383         POSTING_READ(PLANE_SURF(pipe, 0));
9384 }
9385
9386 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9387 {
9388         struct drm_device *dev = intel_crtc->base.dev;
9389         struct drm_i915_private *dev_priv = dev->dev_private;
9390         struct intel_framebuffer *intel_fb =
9391                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9392         struct drm_i915_gem_object *obj = intel_fb->obj;
9393         u32 dspcntr;
9394         u32 reg;
9395
9396         reg = DSPCNTR(intel_crtc->plane);
9397         dspcntr = I915_READ(reg);
9398
9399         if (obj->tiling_mode != I915_TILING_NONE)
9400                 dspcntr |= DISPPLANE_TILED;
9401         else
9402                 dspcntr &= ~DISPPLANE_TILED;
9403
9404         I915_WRITE(reg, dspcntr);
9405
9406         I915_WRITE(DSPSURF(intel_crtc->plane),
9407                    intel_crtc->unpin_work->gtt_offset);
9408         POSTING_READ(DSPSURF(intel_crtc->plane));
9409
9410 }
9411
9412 /*
9413  * XXX: This is the temporary way to update the plane registers until we get
9414  * around to using the usual plane update functions for MMIO flips
9415  */
9416 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9417 {
9418         struct drm_device *dev = intel_crtc->base.dev;
9419         bool atomic_update;
9420         u32 start_vbl_count;
9421
9422         intel_mark_page_flip_active(intel_crtc);
9423
9424         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9425
9426         if (INTEL_INFO(dev)->gen >= 9)
9427                 skl_do_mmio_flip(intel_crtc);
9428         else
9429                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9430                 ilk_do_mmio_flip(intel_crtc);
9431
9432         if (atomic_update)
9433                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9434 }
9435
9436 static void intel_mmio_flip_work_func(struct work_struct *work)
9437 {
9438         struct intel_crtc *crtc =
9439                 container_of(work, struct intel_crtc, mmio_flip.work);
9440         struct intel_mmio_flip *mmio_flip;
9441
9442         mmio_flip = &crtc->mmio_flip;
9443         if (mmio_flip->req)
9444                 WARN_ON(__i915_wait_request(mmio_flip->req,
9445                                             crtc->reset_counter,
9446                                             false, NULL, NULL) != 0);
9447
9448         intel_do_mmio_flip(crtc);
9449         if (mmio_flip->req) {
9450                 mutex_lock(&crtc->base.dev->struct_mutex);
9451                 i915_gem_request_assign(&mmio_flip->req, NULL);
9452                 mutex_unlock(&crtc->base.dev->struct_mutex);
9453         }
9454 }
9455
9456 static int intel_queue_mmio_flip(struct drm_device *dev,
9457                                  struct drm_crtc *crtc,
9458                                  struct drm_framebuffer *fb,
9459                                  struct drm_i915_gem_object *obj,
9460                                  struct intel_engine_cs *ring,
9461                                  uint32_t flags)
9462 {
9463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9464
9465         i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9466                                 obj->last_write_req);
9467
9468         schedule_work(&intel_crtc->mmio_flip.work);
9469
9470         return 0;
9471 }
9472
9473 static int intel_gen9_queue_flip(struct drm_device *dev,
9474                                  struct drm_crtc *crtc,
9475                                  struct drm_framebuffer *fb,
9476                                  struct drm_i915_gem_object *obj,
9477                                  struct intel_engine_cs *ring,
9478                                  uint32_t flags)
9479 {
9480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9481         uint32_t plane = 0, stride;
9482         int ret;
9483
9484         switch(intel_crtc->pipe) {
9485         case PIPE_A:
9486                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9487                 break;
9488         case PIPE_B:
9489                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9490                 break;
9491         case PIPE_C:
9492                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9493                 break;
9494         default:
9495                 WARN_ONCE(1, "unknown plane in flip command\n");
9496                 return -ENODEV;
9497         }
9498
9499         switch (obj->tiling_mode) {
9500         case I915_TILING_NONE:
9501                 stride = fb->pitches[0] >> 6;
9502                 break;
9503         case I915_TILING_X:
9504                 stride = fb->pitches[0] >> 9;
9505                 break;
9506         default:
9507                 WARN_ONCE(1, "unknown tiling in flip command\n");
9508                 return -ENODEV;
9509         }
9510
9511         ret = intel_ring_begin(ring, 10);
9512         if (ret)
9513                 return ret;
9514
9515         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9516         intel_ring_emit(ring, DERRMR);
9517         intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9518                                 DERRMR_PIPEB_PRI_FLIP_DONE |
9519                                 DERRMR_PIPEC_PRI_FLIP_DONE));
9520         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9521                               MI_SRM_LRM_GLOBAL_GTT);
9522         intel_ring_emit(ring, DERRMR);
9523         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9524         intel_ring_emit(ring, 0);
9525
9526         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9527         intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9528         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9529
9530         intel_mark_page_flip_active(intel_crtc);
9531         __intel_ring_advance(ring);
9532
9533         return 0;
9534 }
9535
9536 static int intel_default_queue_flip(struct drm_device *dev,
9537                                     struct drm_crtc *crtc,
9538                                     struct drm_framebuffer *fb,
9539                                     struct drm_i915_gem_object *obj,
9540                                     struct intel_engine_cs *ring,
9541                                     uint32_t flags)
9542 {
9543         return -ENODEV;
9544 }
9545
9546 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9547                                          struct drm_crtc *crtc)
9548 {
9549         struct drm_i915_private *dev_priv = dev->dev_private;
9550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9551         struct intel_unpin_work *work = intel_crtc->unpin_work;
9552         u32 addr;
9553
9554         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9555                 return true;
9556
9557         if (!work->enable_stall_check)
9558                 return false;
9559
9560         if (work->flip_ready_vblank == 0) {
9561                 if (work->flip_queued_req &&
9562                     !i915_gem_request_completed(work->flip_queued_req, true))
9563                         return false;
9564
9565                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9566         }
9567
9568         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9569                 return false;
9570
9571         /* Potential stall - if we see that the flip has happened,
9572          * assume a missed interrupt. */
9573         if (INTEL_INFO(dev)->gen >= 4)
9574                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9575         else
9576                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9577
9578         /* There is a potential issue here with a false positive after a flip
9579          * to the same address. We could address this by checking for a
9580          * non-incrementing frame counter.
9581          */
9582         return addr == work->gtt_offset;
9583 }
9584
9585 void intel_check_page_flip(struct drm_device *dev, int pipe)
9586 {
9587         struct drm_i915_private *dev_priv = dev->dev_private;
9588         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9589         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9590
9591         WARN_ON(!in_irq());
9592
9593         if (crtc == NULL)
9594                 return;
9595
9596         spin_lock(&dev->event_lock);
9597         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9598                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9599                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9600                 page_flip_completed(intel_crtc);
9601         }
9602         spin_unlock(&dev->event_lock);
9603 }
9604
9605 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9606                                 struct drm_framebuffer *fb,
9607                                 struct drm_pending_vblank_event *event,
9608                                 uint32_t page_flip_flags)
9609 {
9610         struct drm_device *dev = crtc->dev;
9611         struct drm_i915_private *dev_priv = dev->dev_private;
9612         struct drm_framebuffer *old_fb = crtc->primary->fb;
9613         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9615         struct drm_plane *primary = crtc->primary;
9616         struct intel_plane *intel_plane = to_intel_plane(primary);
9617         enum pipe pipe = intel_crtc->pipe;
9618         struct intel_unpin_work *work;
9619         struct intel_engine_cs *ring;
9620         int ret;
9621
9622         /*
9623          * drm_mode_page_flip_ioctl() should already catch this, but double
9624          * check to be safe.  In the future we may enable pageflipping from
9625          * a disabled primary plane.
9626          */
9627         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9628                 return -EBUSY;
9629
9630         /* Can't change pixel format via MI display flips. */
9631         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9632                 return -EINVAL;
9633
9634         /*
9635          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9636          * Note that pitch changes could also affect these register.
9637          */
9638         if (INTEL_INFO(dev)->gen > 3 &&
9639             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9640              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9641                 return -EINVAL;
9642
9643         if (i915_terminally_wedged(&dev_priv->gpu_error))
9644                 goto out_hang;
9645
9646         work = kzalloc(sizeof(*work), GFP_KERNEL);
9647         if (work == NULL)
9648                 return -ENOMEM;
9649
9650         work->event = event;
9651         work->crtc = crtc;
9652         work->old_fb_obj = intel_fb_obj(old_fb);
9653         INIT_WORK(&work->work, intel_unpin_work_fn);
9654
9655         ret = drm_crtc_vblank_get(crtc);
9656         if (ret)
9657                 goto free_work;
9658
9659         /* We borrow the event spin lock for protecting unpin_work */
9660         spin_lock_irq(&dev->event_lock);
9661         if (intel_crtc->unpin_work) {
9662                 /* Before declaring the flip queue wedged, check if
9663                  * the hardware completed the operation behind our backs.
9664                  */
9665                 if (__intel_pageflip_stall_check(dev, crtc)) {
9666                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9667                         page_flip_completed(intel_crtc);
9668                 } else {
9669                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9670                         spin_unlock_irq(&dev->event_lock);
9671
9672                         drm_crtc_vblank_put(crtc);
9673                         kfree(work);
9674                         return -EBUSY;
9675                 }
9676         }
9677         intel_crtc->unpin_work = work;
9678         spin_unlock_irq(&dev->event_lock);
9679
9680         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9681                 flush_workqueue(dev_priv->wq);
9682
9683         ret = i915_mutex_lock_interruptible(dev);
9684         if (ret)
9685                 goto cleanup;
9686
9687         /* Reference the objects for the scheduled work. */
9688         drm_gem_object_reference(&work->old_fb_obj->base);
9689         drm_gem_object_reference(&obj->base);
9690
9691         crtc->primary->fb = fb;
9692
9693         work->pending_flip_obj = obj;
9694
9695         atomic_inc(&intel_crtc->unpin_work_count);
9696         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9697
9698         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9699                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9700
9701         if (IS_VALLEYVIEW(dev)) {
9702                 ring = &dev_priv->ring[BCS];
9703                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9704                         /* vlv: DISPLAY_FLIP fails to change tiling */
9705                         ring = NULL;
9706         } else if (IS_IVYBRIDGE(dev)) {
9707                 ring = &dev_priv->ring[BCS];
9708         } else if (INTEL_INFO(dev)->gen >= 7) {
9709                 ring = i915_gem_request_get_ring(obj->last_read_req);
9710                 if (ring == NULL || ring->id != RCS)
9711                         ring = &dev_priv->ring[BCS];
9712         } else {
9713                 ring = &dev_priv->ring[RCS];
9714         }
9715
9716         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9717         if (ret)
9718                 goto cleanup_pending;
9719
9720         work->gtt_offset =
9721                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9722
9723         if (use_mmio_flip(ring, obj)) {
9724                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9725                                             page_flip_flags);
9726                 if (ret)
9727                         goto cleanup_unpin;
9728
9729                 i915_gem_request_assign(&work->flip_queued_req,
9730                                         obj->last_write_req);
9731         } else {
9732                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9733                                                    page_flip_flags);
9734                 if (ret)
9735                         goto cleanup_unpin;
9736
9737                 i915_gem_request_assign(&work->flip_queued_req,
9738                                         intel_ring_get_request(ring));
9739         }
9740
9741         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9742         work->enable_stall_check = true;
9743
9744         i915_gem_track_fb(work->old_fb_obj, obj,
9745                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9746
9747         intel_fbc_disable(dev);
9748         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9749         mutex_unlock(&dev->struct_mutex);
9750
9751         trace_i915_flip_request(intel_crtc->plane, obj);
9752
9753         return 0;
9754
9755 cleanup_unpin:
9756         intel_unpin_fb_obj(obj);
9757 cleanup_pending:
9758         atomic_dec(&intel_crtc->unpin_work_count);
9759         crtc->primary->fb = old_fb;
9760         drm_gem_object_unreference(&work->old_fb_obj->base);
9761         drm_gem_object_unreference(&obj->base);
9762         mutex_unlock(&dev->struct_mutex);
9763
9764 cleanup:
9765         spin_lock_irq(&dev->event_lock);
9766         intel_crtc->unpin_work = NULL;
9767         spin_unlock_irq(&dev->event_lock);
9768
9769         drm_crtc_vblank_put(crtc);
9770 free_work:
9771         kfree(work);
9772
9773         if (ret == -EIO) {
9774 out_hang:
9775                 ret = primary->funcs->update_plane(primary, crtc, fb,
9776                                                    intel_plane->crtc_x,
9777                                                    intel_plane->crtc_y,
9778                                                    intel_plane->crtc_h,
9779                                                    intel_plane->crtc_w,
9780                                                    intel_plane->src_x,
9781                                                    intel_plane->src_y,
9782                                                    intel_plane->src_h,
9783                                                    intel_plane->src_w);
9784                 if (ret == 0 && event) {
9785                         spin_lock_irq(&dev->event_lock);
9786                         drm_send_vblank_event(dev, pipe, event);
9787                         spin_unlock_irq(&dev->event_lock);
9788                 }
9789         }
9790         return ret;
9791 }
9792
9793 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9794         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9795         .load_lut = intel_crtc_load_lut,
9796 };
9797
9798 /**
9799  * intel_modeset_update_staged_output_state
9800  *
9801  * Updates the staged output configuration state, e.g. after we've read out the
9802  * current hw state.
9803  */
9804 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9805 {
9806         struct intel_crtc *crtc;
9807         struct intel_encoder *encoder;
9808         struct intel_connector *connector;
9809
9810         list_for_each_entry(connector, &dev->mode_config.connector_list,
9811                             base.head) {
9812                 connector->new_encoder =
9813                         to_intel_encoder(connector->base.encoder);
9814         }
9815
9816         for_each_intel_encoder(dev, encoder) {
9817                 encoder->new_crtc =
9818                         to_intel_crtc(encoder->base.crtc);
9819         }
9820
9821         for_each_intel_crtc(dev, crtc) {
9822                 crtc->new_enabled = crtc->base.enabled;
9823
9824                 if (crtc->new_enabled)
9825                         crtc->new_config = &crtc->config;
9826                 else
9827                         crtc->new_config = NULL;
9828         }
9829 }
9830
9831 /**
9832  * intel_modeset_commit_output_state
9833  *
9834  * This function copies the stage display pipe configuration to the real one.
9835  */
9836 static void intel_modeset_commit_output_state(struct drm_device *dev)
9837 {
9838         struct intel_crtc *crtc;
9839         struct intel_encoder *encoder;
9840         struct intel_connector *connector;
9841
9842         list_for_each_entry(connector, &dev->mode_config.connector_list,
9843                             base.head) {
9844                 connector->base.encoder = &connector->new_encoder->base;
9845         }
9846
9847         for_each_intel_encoder(dev, encoder) {
9848                 encoder->base.crtc = &encoder->new_crtc->base;
9849         }
9850
9851         for_each_intel_crtc(dev, crtc) {
9852                 crtc->base.enabled = crtc->new_enabled;
9853         }
9854 }
9855
9856 static void
9857 connected_sink_compute_bpp(struct intel_connector *connector,
9858                            struct intel_crtc_config *pipe_config)
9859 {
9860         int bpp = pipe_config->pipe_bpp;
9861
9862         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9863                 connector->base.base.id,
9864                 connector->base.name);
9865
9866         /* Don't use an invalid EDID bpc value */
9867         if (connector->base.display_info.bpc &&
9868             connector->base.display_info.bpc * 3 < bpp) {
9869                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9870                               bpp, connector->base.display_info.bpc*3);
9871                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9872         }
9873
9874         /* Clamp bpp to 8 on screens without EDID 1.4 */
9875         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9876                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9877                               bpp);
9878                 pipe_config->pipe_bpp = 24;
9879         }
9880 }
9881
9882 static int
9883 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9884                           struct drm_framebuffer *fb,
9885                           struct intel_crtc_config *pipe_config)
9886 {
9887         struct drm_device *dev = crtc->base.dev;
9888         struct intel_connector *connector;
9889         int bpp;
9890
9891         switch (fb->pixel_format) {
9892         case DRM_FORMAT_C8:
9893                 bpp = 8*3; /* since we go through a colormap */
9894                 break;
9895         case DRM_FORMAT_XRGB1555:
9896         case DRM_FORMAT_ARGB1555:
9897                 /* checked in intel_framebuffer_init already */
9898                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9899                         return -EINVAL;
9900         case DRM_FORMAT_RGB565:
9901                 bpp = 6*3; /* min is 18bpp */
9902                 break;
9903         case DRM_FORMAT_XBGR8888:
9904         case DRM_FORMAT_ABGR8888:
9905                 /* checked in intel_framebuffer_init already */
9906                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9907                         return -EINVAL;
9908         case DRM_FORMAT_XRGB8888:
9909         case DRM_FORMAT_ARGB8888:
9910                 bpp = 8*3;
9911                 break;
9912         case DRM_FORMAT_XRGB2101010:
9913         case DRM_FORMAT_ARGB2101010:
9914         case DRM_FORMAT_XBGR2101010:
9915         case DRM_FORMAT_ABGR2101010:
9916                 /* checked in intel_framebuffer_init already */
9917                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9918                         return -EINVAL;
9919                 bpp = 10*3;
9920                 break;
9921         /* TODO: gen4+ supports 16 bpc floating point, too. */
9922         default:
9923                 DRM_DEBUG_KMS("unsupported depth\n");
9924                 return -EINVAL;
9925         }
9926
9927         pipe_config->pipe_bpp = bpp;
9928
9929         /* Clamp display bpp to EDID value */
9930         list_for_each_entry(connector, &dev->mode_config.connector_list,
9931                             base.head) {
9932                 if (!connector->new_encoder ||
9933                     connector->new_encoder->new_crtc != crtc)
9934                         continue;
9935
9936                 connected_sink_compute_bpp(connector, pipe_config);
9937         }
9938
9939         return bpp;
9940 }
9941
9942 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9943 {
9944         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9945                         "type: 0x%x flags: 0x%x\n",
9946                 mode->crtc_clock,
9947                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9948                 mode->crtc_hsync_end, mode->crtc_htotal,
9949                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9950                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9951 }
9952
9953 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9954                                    struct intel_crtc_config *pipe_config,
9955                                    const char *context)
9956 {
9957         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9958                       context, pipe_name(crtc->pipe));
9959
9960         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9961         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9962                       pipe_config->pipe_bpp, pipe_config->dither);
9963         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9964                       pipe_config->has_pch_encoder,
9965                       pipe_config->fdi_lanes,
9966                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9967                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9968                       pipe_config->fdi_m_n.tu);
9969         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9970                       pipe_config->has_dp_encoder,
9971                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9972                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9973                       pipe_config->dp_m_n.tu);
9974
9975         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9976                       pipe_config->has_dp_encoder,
9977                       pipe_config->dp_m2_n2.gmch_m,
9978                       pipe_config->dp_m2_n2.gmch_n,
9979                       pipe_config->dp_m2_n2.link_m,
9980                       pipe_config->dp_m2_n2.link_n,
9981                       pipe_config->dp_m2_n2.tu);
9982
9983         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
9984                       pipe_config->has_audio,
9985                       pipe_config->has_infoframe);
9986
9987         DRM_DEBUG_KMS("requested mode:\n");
9988         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9989         DRM_DEBUG_KMS("adjusted mode:\n");
9990         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9991         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9992         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9993         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9994                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9995         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9996                       pipe_config->gmch_pfit.control,
9997                       pipe_config->gmch_pfit.pgm_ratios,
9998                       pipe_config->gmch_pfit.lvds_border_bits);
9999         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10000                       pipe_config->pch_pfit.pos,
10001                       pipe_config->pch_pfit.size,
10002                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10003         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10004         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10005 }
10006
10007 static bool encoders_cloneable(const struct intel_encoder *a,
10008                                const struct intel_encoder *b)
10009 {
10010         /* masks could be asymmetric, so check both ways */
10011         return a == b || (a->cloneable & (1 << b->type) &&
10012                           b->cloneable & (1 << a->type));
10013 }
10014
10015 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10016                                          struct intel_encoder *encoder)
10017 {
10018         struct drm_device *dev = crtc->base.dev;
10019         struct intel_encoder *source_encoder;
10020
10021         for_each_intel_encoder(dev, source_encoder) {
10022                 if (source_encoder->new_crtc != crtc)
10023                         continue;
10024
10025                 if (!encoders_cloneable(encoder, source_encoder))
10026                         return false;
10027         }
10028
10029         return true;
10030 }
10031
10032 static bool check_encoder_cloning(struct intel_crtc *crtc)
10033 {
10034         struct drm_device *dev = crtc->base.dev;
10035         struct intel_encoder *encoder;
10036
10037         for_each_intel_encoder(dev, encoder) {
10038                 if (encoder->new_crtc != crtc)
10039                         continue;
10040
10041                 if (!check_single_encoder_cloning(crtc, encoder))
10042                         return false;
10043         }
10044
10045         return true;
10046 }
10047
10048 static bool check_digital_port_conflicts(struct drm_device *dev)
10049 {
10050         struct intel_connector *connector;
10051         unsigned int used_ports = 0;
10052
10053         /*
10054          * Walk the connector list instead of the encoder
10055          * list to detect the problem on ddi platforms
10056          * where there's just one encoder per digital port.
10057          */
10058         list_for_each_entry(connector,
10059                             &dev->mode_config.connector_list, base.head) {
10060                 struct intel_encoder *encoder = connector->new_encoder;
10061
10062                 if (!encoder)
10063                         continue;
10064
10065                 WARN_ON(!encoder->new_crtc);
10066
10067                 switch (encoder->type) {
10068                         unsigned int port_mask;
10069                 case INTEL_OUTPUT_UNKNOWN:
10070                         if (WARN_ON(!HAS_DDI(dev)))
10071                                 break;
10072                 case INTEL_OUTPUT_DISPLAYPORT:
10073                 case INTEL_OUTPUT_HDMI:
10074                 case INTEL_OUTPUT_EDP:
10075                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10076
10077                         /* the same port mustn't appear more than once */
10078                         if (used_ports & port_mask)
10079                                 return false;
10080
10081                         used_ports |= port_mask;
10082                 default:
10083                         break;
10084                 }
10085         }
10086
10087         return true;
10088 }
10089
10090 static struct intel_crtc_config *
10091 intel_modeset_pipe_config(struct drm_crtc *crtc,
10092                           struct drm_framebuffer *fb,
10093                           struct drm_display_mode *mode)
10094 {
10095         struct drm_device *dev = crtc->dev;
10096         struct intel_encoder *encoder;
10097         struct intel_crtc_config *pipe_config;
10098         int plane_bpp, ret = -EINVAL;
10099         bool retry = true;
10100
10101         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10102                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10103                 return ERR_PTR(-EINVAL);
10104         }
10105
10106         if (!check_digital_port_conflicts(dev)) {
10107                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10108                 return ERR_PTR(-EINVAL);
10109         }
10110
10111         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10112         if (!pipe_config)
10113                 return ERR_PTR(-ENOMEM);
10114
10115         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10116         drm_mode_copy(&pipe_config->requested_mode, mode);
10117
10118         pipe_config->cpu_transcoder =
10119                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10120         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10121
10122         /*
10123          * Sanitize sync polarity flags based on requested ones. If neither
10124          * positive or negative polarity is requested, treat this as meaning
10125          * negative polarity.
10126          */
10127         if (!(pipe_config->adjusted_mode.flags &
10128               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10129                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10130
10131         if (!(pipe_config->adjusted_mode.flags &
10132               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10133                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10134
10135         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10136          * plane pixel format and any sink constraints into account. Returns the
10137          * source plane bpp so that dithering can be selected on mismatches
10138          * after encoders and crtc also have had their say. */
10139         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10140                                               fb, pipe_config);
10141         if (plane_bpp < 0)
10142                 goto fail;
10143
10144         /*
10145          * Determine the real pipe dimensions. Note that stereo modes can
10146          * increase the actual pipe size due to the frame doubling and
10147          * insertion of additional space for blanks between the frame. This
10148          * is stored in the crtc timings. We use the requested mode to do this
10149          * computation to clearly distinguish it from the adjusted mode, which
10150          * can be changed by the connectors in the below retry loop.
10151          */
10152         drm_crtc_get_hv_timing(&pipe_config->requested_mode,
10153                                &pipe_config->pipe_src_w,
10154                                &pipe_config->pipe_src_h);
10155
10156 encoder_retry:
10157         /* Ensure the port clock defaults are reset when retrying. */
10158         pipe_config->port_clock = 0;
10159         pipe_config->pixel_multiplier = 1;
10160
10161         /* Fill in default crtc timings, allow encoders to overwrite them. */
10162         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10163
10164         /* Pass our mode to the connectors and the CRTC to give them a chance to
10165          * adjust it according to limitations or connector properties, and also
10166          * a chance to reject the mode entirely.
10167          */
10168         for_each_intel_encoder(dev, encoder) {
10169
10170                 if (&encoder->new_crtc->base != crtc)
10171                         continue;
10172
10173                 if (!(encoder->compute_config(encoder, pipe_config))) {
10174                         DRM_DEBUG_KMS("Encoder config failure\n");
10175                         goto fail;
10176                 }
10177         }
10178
10179         /* Set default port clock if not overwritten by the encoder. Needs to be
10180          * done afterwards in case the encoder adjusts the mode. */
10181         if (!pipe_config->port_clock)
10182                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10183                         * pipe_config->pixel_multiplier;
10184
10185         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10186         if (ret < 0) {
10187                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10188                 goto fail;
10189         }
10190
10191         if (ret == RETRY) {
10192                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10193                         ret = -EINVAL;
10194                         goto fail;
10195                 }
10196
10197                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10198                 retry = false;
10199                 goto encoder_retry;
10200         }
10201
10202         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10203         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10204                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10205
10206         return pipe_config;
10207 fail:
10208         kfree(pipe_config);
10209         return ERR_PTR(ret);
10210 }
10211
10212 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10213  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10214 static void
10215 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10216                              unsigned *prepare_pipes, unsigned *disable_pipes)
10217 {
10218         struct intel_crtc *intel_crtc;
10219         struct drm_device *dev = crtc->dev;
10220         struct intel_encoder *encoder;
10221         struct intel_connector *connector;
10222         struct drm_crtc *tmp_crtc;
10223
10224         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10225
10226         /* Check which crtcs have changed outputs connected to them, these need
10227          * to be part of the prepare_pipes mask. We don't (yet) support global
10228          * modeset across multiple crtcs, so modeset_pipes will only have one
10229          * bit set at most. */
10230         list_for_each_entry(connector, &dev->mode_config.connector_list,
10231                             base.head) {
10232                 if (connector->base.encoder == &connector->new_encoder->base)
10233                         continue;
10234
10235                 if (connector->base.encoder) {
10236                         tmp_crtc = connector->base.encoder->crtc;
10237
10238                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10239                 }
10240
10241                 if (connector->new_encoder)
10242                         *prepare_pipes |=
10243                                 1 << connector->new_encoder->new_crtc->pipe;
10244         }
10245
10246         for_each_intel_encoder(dev, encoder) {
10247                 if (encoder->base.crtc == &encoder->new_crtc->base)
10248                         continue;
10249
10250                 if (encoder->base.crtc) {
10251                         tmp_crtc = encoder->base.crtc;
10252
10253                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10254                 }
10255
10256                 if (encoder->new_crtc)
10257                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10258         }
10259
10260         /* Check for pipes that will be enabled/disabled ... */
10261         for_each_intel_crtc(dev, intel_crtc) {
10262                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10263                         continue;
10264
10265                 if (!intel_crtc->new_enabled)
10266                         *disable_pipes |= 1 << intel_crtc->pipe;
10267                 else
10268                         *prepare_pipes |= 1 << intel_crtc->pipe;
10269         }
10270
10271
10272         /* set_mode is also used to update properties on life display pipes. */
10273         intel_crtc = to_intel_crtc(crtc);
10274         if (intel_crtc->new_enabled)
10275                 *prepare_pipes |= 1 << intel_crtc->pipe;
10276
10277         /*
10278          * For simplicity do a full modeset on any pipe where the output routing
10279          * changed. We could be more clever, but that would require us to be
10280          * more careful with calling the relevant encoder->mode_set functions.
10281          */
10282         if (*prepare_pipes)
10283                 *modeset_pipes = *prepare_pipes;
10284
10285         /* ... and mask these out. */
10286         *modeset_pipes &= ~(*disable_pipes);
10287         *prepare_pipes &= ~(*disable_pipes);
10288
10289         /*
10290          * HACK: We don't (yet) fully support global modesets. intel_set_config
10291          * obies this rule, but the modeset restore mode of
10292          * intel_modeset_setup_hw_state does not.
10293          */
10294         *modeset_pipes &= 1 << intel_crtc->pipe;
10295         *prepare_pipes &= 1 << intel_crtc->pipe;
10296
10297         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10298                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10299 }
10300
10301 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10302 {
10303         struct drm_encoder *encoder;
10304         struct drm_device *dev = crtc->dev;
10305
10306         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10307                 if (encoder->crtc == crtc)
10308                         return true;
10309
10310         return false;
10311 }
10312
10313 static void
10314 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10315 {
10316         struct drm_i915_private *dev_priv = dev->dev_private;
10317         struct intel_encoder *intel_encoder;
10318         struct intel_crtc *intel_crtc;
10319         struct drm_connector *connector;
10320
10321         intel_shared_dpll_commit(dev_priv);
10322
10323         for_each_intel_encoder(dev, intel_encoder) {
10324                 if (!intel_encoder->base.crtc)
10325                         continue;
10326
10327                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10328
10329                 if (prepare_pipes & (1 << intel_crtc->pipe))
10330                         intel_encoder->connectors_active = false;
10331         }
10332
10333         intel_modeset_commit_output_state(dev);
10334
10335         /* Double check state. */
10336         for_each_intel_crtc(dev, intel_crtc) {
10337                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10338                 WARN_ON(intel_crtc->new_config &&
10339                         intel_crtc->new_config != &intel_crtc->config);
10340                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10341         }
10342
10343         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10344                 if (!connector->encoder || !connector->encoder->crtc)
10345                         continue;
10346
10347                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10348
10349                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10350                         struct drm_property *dpms_property =
10351                                 dev->mode_config.dpms_property;
10352
10353                         connector->dpms = DRM_MODE_DPMS_ON;
10354                         drm_object_property_set_value(&connector->base,
10355                                                          dpms_property,
10356                                                          DRM_MODE_DPMS_ON);
10357
10358                         intel_encoder = to_intel_encoder(connector->encoder);
10359                         intel_encoder->connectors_active = true;
10360                 }
10361         }
10362
10363 }
10364
10365 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10366 {
10367         int diff;
10368
10369         if (clock1 == clock2)
10370                 return true;
10371
10372         if (!clock1 || !clock2)
10373                 return false;
10374
10375         diff = abs(clock1 - clock2);
10376
10377         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10378                 return true;
10379
10380         return false;
10381 }
10382
10383 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10384         list_for_each_entry((intel_crtc), \
10385                             &(dev)->mode_config.crtc_list, \
10386                             base.head) \
10387                 if (mask & (1 <<(intel_crtc)->pipe))
10388
10389 static bool
10390 intel_pipe_config_compare(struct drm_device *dev,
10391                           struct intel_crtc_config *current_config,
10392                           struct intel_crtc_config *pipe_config)
10393 {
10394 #define PIPE_CONF_CHECK_X(name) \
10395         if (current_config->name != pipe_config->name) { \
10396                 DRM_ERROR("mismatch in " #name " " \
10397                           "(expected 0x%08x, found 0x%08x)\n", \
10398                           current_config->name, \
10399                           pipe_config->name); \
10400                 return false; \
10401         }
10402
10403 #define PIPE_CONF_CHECK_I(name) \
10404         if (current_config->name != pipe_config->name) { \
10405                 DRM_ERROR("mismatch in " #name " " \
10406                           "(expected %i, found %i)\n", \
10407                           current_config->name, \
10408                           pipe_config->name); \
10409                 return false; \
10410         }
10411
10412 /* This is required for BDW+ where there is only one set of registers for
10413  * switching between high and low RR.
10414  * This macro can be used whenever a comparison has to be made between one
10415  * hw state and multiple sw state variables.
10416  */
10417 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10418         if ((current_config->name != pipe_config->name) && \
10419                 (current_config->alt_name != pipe_config->name)) { \
10420                         DRM_ERROR("mismatch in " #name " " \
10421                                   "(expected %i or %i, found %i)\n", \
10422                                   current_config->name, \
10423                                   current_config->alt_name, \
10424                                   pipe_config->name); \
10425                         return false; \
10426         }
10427
10428 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10429         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10430                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10431                           "(expected %i, found %i)\n", \
10432                           current_config->name & (mask), \
10433                           pipe_config->name & (mask)); \
10434                 return false; \
10435         }
10436
10437 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10438         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10439                 DRM_ERROR("mismatch in " #name " " \
10440                           "(expected %i, found %i)\n", \
10441                           current_config->name, \
10442                           pipe_config->name); \
10443                 return false; \
10444         }
10445
10446 #define PIPE_CONF_QUIRK(quirk)  \
10447         ((current_config->quirks | pipe_config->quirks) & (quirk))
10448
10449         PIPE_CONF_CHECK_I(cpu_transcoder);
10450
10451         PIPE_CONF_CHECK_I(has_pch_encoder);
10452         PIPE_CONF_CHECK_I(fdi_lanes);
10453         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10454         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10455         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10456         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10457         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10458
10459         PIPE_CONF_CHECK_I(has_dp_encoder);
10460
10461         if (INTEL_INFO(dev)->gen < 8) {
10462                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10463                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10464                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10465                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10466                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10467
10468                 if (current_config->has_drrs) {
10469                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10470                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10471                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10472                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10473                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10474                 }
10475         } else {
10476                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10477                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10478                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10479                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10480                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10481         }
10482
10483         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10484         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10485         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10486         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10487         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10488         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10489
10490         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10491         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10492         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10493         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10494         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10495         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10496
10497         PIPE_CONF_CHECK_I(pixel_multiplier);
10498         PIPE_CONF_CHECK_I(has_hdmi_sink);
10499         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10500             IS_VALLEYVIEW(dev))
10501                 PIPE_CONF_CHECK_I(limited_color_range);
10502         PIPE_CONF_CHECK_I(has_infoframe);
10503
10504         PIPE_CONF_CHECK_I(has_audio);
10505
10506         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10507                               DRM_MODE_FLAG_INTERLACE);
10508
10509         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10510                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10511                                       DRM_MODE_FLAG_PHSYNC);
10512                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10513                                       DRM_MODE_FLAG_NHSYNC);
10514                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10515                                       DRM_MODE_FLAG_PVSYNC);
10516                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10517                                       DRM_MODE_FLAG_NVSYNC);
10518         }
10519
10520         PIPE_CONF_CHECK_I(pipe_src_w);
10521         PIPE_CONF_CHECK_I(pipe_src_h);
10522
10523         /*
10524          * FIXME: BIOS likes to set up a cloned config with lvds+external
10525          * screen. Since we don't yet re-compute the pipe config when moving
10526          * just the lvds port away to another pipe the sw tracking won't match.
10527          *
10528          * Proper atomic modesets with recomputed global state will fix this.
10529          * Until then just don't check gmch state for inherited modes.
10530          */
10531         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10532                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10533                 /* pfit ratios are autocomputed by the hw on gen4+ */
10534                 if (INTEL_INFO(dev)->gen < 4)
10535                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10536                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10537         }
10538
10539         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10540         if (current_config->pch_pfit.enabled) {
10541                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10542                 PIPE_CONF_CHECK_I(pch_pfit.size);
10543         }
10544
10545         /* BDW+ don't expose a synchronous way to read the state */
10546         if (IS_HASWELL(dev))
10547                 PIPE_CONF_CHECK_I(ips_enabled);
10548
10549         PIPE_CONF_CHECK_I(double_wide);
10550
10551         PIPE_CONF_CHECK_X(ddi_pll_sel);
10552
10553         PIPE_CONF_CHECK_I(shared_dpll);
10554         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10555         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10556         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10557         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10558         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10559         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10560         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10561         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10562
10563         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10564                 PIPE_CONF_CHECK_I(pipe_bpp);
10565
10566         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10567         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10568
10569 #undef PIPE_CONF_CHECK_X
10570 #undef PIPE_CONF_CHECK_I
10571 #undef PIPE_CONF_CHECK_I_ALT
10572 #undef PIPE_CONF_CHECK_FLAGS
10573 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10574 #undef PIPE_CONF_QUIRK
10575
10576         return true;
10577 }
10578
10579 static void check_wm_state(struct drm_device *dev)
10580 {
10581         struct drm_i915_private *dev_priv = dev->dev_private;
10582         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10583         struct intel_crtc *intel_crtc;
10584         int plane;
10585
10586         if (INTEL_INFO(dev)->gen < 9)
10587                 return;
10588
10589         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10590         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10591
10592         for_each_intel_crtc(dev, intel_crtc) {
10593                 struct skl_ddb_entry *hw_entry, *sw_entry;
10594                 const enum pipe pipe = intel_crtc->pipe;
10595
10596                 if (!intel_crtc->active)
10597                         continue;
10598
10599                 /* planes */
10600                 for_each_plane(pipe, plane) {
10601                         hw_entry = &hw_ddb.plane[pipe][plane];
10602                         sw_entry = &sw_ddb->plane[pipe][plane];
10603
10604                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10605                                 continue;
10606
10607                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10608                                   "(expected (%u,%u), found (%u,%u))\n",
10609                                   pipe_name(pipe), plane + 1,
10610                                   sw_entry->start, sw_entry->end,
10611                                   hw_entry->start, hw_entry->end);
10612                 }
10613
10614                 /* cursor */
10615                 hw_entry = &hw_ddb.cursor[pipe];
10616                 sw_entry = &sw_ddb->cursor[pipe];
10617
10618                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10619                         continue;
10620
10621                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10622                           "(expected (%u,%u), found (%u,%u))\n",
10623                           pipe_name(pipe),
10624                           sw_entry->start, sw_entry->end,
10625                           hw_entry->start, hw_entry->end);
10626         }
10627 }
10628
10629 static void
10630 check_connector_state(struct drm_device *dev)
10631 {
10632         struct intel_connector *connector;
10633
10634         list_for_each_entry(connector, &dev->mode_config.connector_list,
10635                             base.head) {
10636                 /* This also checks the encoder/connector hw state with the
10637                  * ->get_hw_state callbacks. */
10638                 intel_connector_check_state(connector);
10639
10640                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10641                      "connector's staged encoder doesn't match current encoder\n");
10642         }
10643 }
10644
10645 static void
10646 check_encoder_state(struct drm_device *dev)
10647 {
10648         struct intel_encoder *encoder;
10649         struct intel_connector *connector;
10650
10651         for_each_intel_encoder(dev, encoder) {
10652                 bool enabled = false;
10653                 bool active = false;
10654                 enum pipe pipe, tracked_pipe;
10655
10656                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10657                               encoder->base.base.id,
10658                               encoder->base.name);
10659
10660                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10661                      "encoder's stage crtc doesn't match current crtc\n");
10662                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10663                      "encoder's active_connectors set, but no crtc\n");
10664
10665                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10666                                     base.head) {
10667                         if (connector->base.encoder != &encoder->base)
10668                                 continue;
10669                         enabled = true;
10670                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10671                                 active = true;
10672                 }
10673                 /*
10674                  * for MST connectors if we unplug the connector is gone
10675                  * away but the encoder is still connected to a crtc
10676                  * until a modeset happens in response to the hotplug.
10677                  */
10678                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10679                         continue;
10680
10681                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10682                      "encoder's enabled state mismatch "
10683                      "(expected %i, found %i)\n",
10684                      !!encoder->base.crtc, enabled);
10685                 I915_STATE_WARN(active && !encoder->base.crtc,
10686                      "active encoder with no crtc\n");
10687
10688                 I915_STATE_WARN(encoder->connectors_active != active,
10689                      "encoder's computed active state doesn't match tracked active state "
10690                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10691
10692                 active = encoder->get_hw_state(encoder, &pipe);
10693                 I915_STATE_WARN(active != encoder->connectors_active,
10694                      "encoder's hw state doesn't match sw tracking "
10695                      "(expected %i, found %i)\n",
10696                      encoder->connectors_active, active);
10697
10698                 if (!encoder->base.crtc)
10699                         continue;
10700
10701                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10702                 I915_STATE_WARN(active && pipe != tracked_pipe,
10703                      "active encoder's pipe doesn't match"
10704                      "(expected %i, found %i)\n",
10705                      tracked_pipe, pipe);
10706
10707         }
10708 }
10709
10710 static void
10711 check_crtc_state(struct drm_device *dev)
10712 {
10713         struct drm_i915_private *dev_priv = dev->dev_private;
10714         struct intel_crtc *crtc;
10715         struct intel_encoder *encoder;
10716         struct intel_crtc_config pipe_config;
10717
10718         for_each_intel_crtc(dev, crtc) {
10719                 bool enabled = false;
10720                 bool active = false;
10721
10722                 memset(&pipe_config, 0, sizeof(pipe_config));
10723
10724                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10725                               crtc->base.base.id);
10726
10727                 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10728                      "active crtc, but not enabled in sw tracking\n");
10729
10730                 for_each_intel_encoder(dev, encoder) {
10731                         if (encoder->base.crtc != &crtc->base)
10732                                 continue;
10733                         enabled = true;
10734                         if (encoder->connectors_active)
10735                                 active = true;
10736                 }
10737
10738                 I915_STATE_WARN(active != crtc->active,
10739                      "crtc's computed active state doesn't match tracked active state "
10740                      "(expected %i, found %i)\n", active, crtc->active);
10741                 I915_STATE_WARN(enabled != crtc->base.enabled,
10742                      "crtc's computed enabled state doesn't match tracked enabled state "
10743                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10744
10745                 active = dev_priv->display.get_pipe_config(crtc,
10746                                                            &pipe_config);
10747
10748                 /* hw state is inconsistent with the pipe quirk */
10749                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10750                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10751                         active = crtc->active;
10752
10753                 for_each_intel_encoder(dev, encoder) {
10754                         enum pipe pipe;
10755                         if (encoder->base.crtc != &crtc->base)
10756                                 continue;
10757                         if (encoder->get_hw_state(encoder, &pipe))
10758                                 encoder->get_config(encoder, &pipe_config);
10759                 }
10760
10761                 I915_STATE_WARN(crtc->active != active,
10762                      "crtc active state doesn't match with hw state "
10763                      "(expected %i, found %i)\n", crtc->active, active);
10764
10765                 if (active &&
10766                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10767                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
10768                         intel_dump_pipe_config(crtc, &pipe_config,
10769                                                "[hw state]");
10770                         intel_dump_pipe_config(crtc, &crtc->config,
10771                                                "[sw state]");
10772                 }
10773         }
10774 }
10775
10776 static void
10777 check_shared_dpll_state(struct drm_device *dev)
10778 {
10779         struct drm_i915_private *dev_priv = dev->dev_private;
10780         struct intel_crtc *crtc;
10781         struct intel_dpll_hw_state dpll_hw_state;
10782         int i;
10783
10784         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10785                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10786                 int enabled_crtcs = 0, active_crtcs = 0;
10787                 bool active;
10788
10789                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10790
10791                 DRM_DEBUG_KMS("%s\n", pll->name);
10792
10793                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10794
10795                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10796                      "more active pll users than references: %i vs %i\n",
10797                      pll->active, hweight32(pll->config.crtc_mask));
10798                 I915_STATE_WARN(pll->active && !pll->on,
10799                      "pll in active use but not on in sw tracking\n");
10800                 I915_STATE_WARN(pll->on && !pll->active,
10801                      "pll in on but not on in use in sw tracking\n");
10802                 I915_STATE_WARN(pll->on != active,
10803                      "pll on state mismatch (expected %i, found %i)\n",
10804                      pll->on, active);
10805
10806                 for_each_intel_crtc(dev, crtc) {
10807                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10808                                 enabled_crtcs++;
10809                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10810                                 active_crtcs++;
10811                 }
10812                 I915_STATE_WARN(pll->active != active_crtcs,
10813                      "pll active crtcs mismatch (expected %i, found %i)\n",
10814                      pll->active, active_crtcs);
10815                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10816                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10817                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10818
10819                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10820                                        sizeof(dpll_hw_state)),
10821                      "pll hw state mismatch\n");
10822         }
10823 }
10824
10825 void
10826 intel_modeset_check_state(struct drm_device *dev)
10827 {
10828         check_wm_state(dev);
10829         check_connector_state(dev);
10830         check_encoder_state(dev);
10831         check_crtc_state(dev);
10832         check_shared_dpll_state(dev);
10833 }
10834
10835 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10836                                      int dotclock)
10837 {
10838         /*
10839          * FDI already provided one idea for the dotclock.
10840          * Yell if the encoder disagrees.
10841          */
10842         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10843              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10844              pipe_config->adjusted_mode.crtc_clock, dotclock);
10845 }
10846
10847 static void update_scanline_offset(struct intel_crtc *crtc)
10848 {
10849         struct drm_device *dev = crtc->base.dev;
10850
10851         /*
10852          * The scanline counter increments at the leading edge of hsync.
10853          *
10854          * On most platforms it starts counting from vtotal-1 on the
10855          * first active line. That means the scanline counter value is
10856          * always one less than what we would expect. Ie. just after
10857          * start of vblank, which also occurs at start of hsync (on the
10858          * last active line), the scanline counter will read vblank_start-1.
10859          *
10860          * On gen2 the scanline counter starts counting from 1 instead
10861          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10862          * to keep the value positive), instead of adding one.
10863          *
10864          * On HSW+ the behaviour of the scanline counter depends on the output
10865          * type. For DP ports it behaves like most other platforms, but on HDMI
10866          * there's an extra 1 line difference. So we need to add two instead of
10867          * one to the value.
10868          */
10869         if (IS_GEN2(dev)) {
10870                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10871                 int vtotal;
10872
10873                 vtotal = mode->crtc_vtotal;
10874                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10875                         vtotal /= 2;
10876
10877                 crtc->scanline_offset = vtotal - 1;
10878         } else if (HAS_DDI(dev) &&
10879                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10880                 crtc->scanline_offset = 2;
10881         } else
10882                 crtc->scanline_offset = 1;
10883 }
10884
10885 static struct intel_crtc_config *
10886 intel_modeset_compute_config(struct drm_crtc *crtc,
10887                              struct drm_display_mode *mode,
10888                              struct drm_framebuffer *fb,
10889                              unsigned *modeset_pipes,
10890                              unsigned *prepare_pipes,
10891                              unsigned *disable_pipes)
10892 {
10893         struct intel_crtc_config *pipe_config = NULL;
10894
10895         intel_modeset_affected_pipes(crtc, modeset_pipes,
10896                                      prepare_pipes, disable_pipes);
10897
10898         if ((*modeset_pipes) == 0)
10899                 goto out;
10900
10901         /*
10902          * Note this needs changes when we start tracking multiple modes
10903          * and crtcs.  At that point we'll need to compute the whole config
10904          * (i.e. one pipe_config for each crtc) rather than just the one
10905          * for this crtc.
10906          */
10907         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10908         if (IS_ERR(pipe_config)) {
10909                 goto out;
10910         }
10911         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10912                                "[modeset]");
10913
10914 out:
10915         return pipe_config;
10916 }
10917
10918 static int __intel_set_mode(struct drm_crtc *crtc,
10919                             struct drm_display_mode *mode,
10920                             int x, int y, struct drm_framebuffer *fb,
10921                             struct intel_crtc_config *pipe_config,
10922                             unsigned modeset_pipes,
10923                             unsigned prepare_pipes,
10924                             unsigned disable_pipes)
10925 {
10926         struct drm_device *dev = crtc->dev;
10927         struct drm_i915_private *dev_priv = dev->dev_private;
10928         struct drm_display_mode *saved_mode;
10929         struct intel_crtc *intel_crtc;
10930         int ret = 0;
10931
10932         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10933         if (!saved_mode)
10934                 return -ENOMEM;
10935
10936         *saved_mode = crtc->mode;
10937
10938         if (modeset_pipes)
10939                 to_intel_crtc(crtc)->new_config = pipe_config;
10940
10941         /*
10942          * See if the config requires any additional preparation, e.g.
10943          * to adjust global state with pipes off.  We need to do this
10944          * here so we can get the modeset_pipe updated config for the new
10945          * mode set on this crtc.  For other crtcs we need to use the
10946          * adjusted_mode bits in the crtc directly.
10947          */
10948         if (IS_VALLEYVIEW(dev)) {
10949                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10950
10951                 /* may have added more to prepare_pipes than we should */
10952                 prepare_pipes &= ~disable_pipes;
10953         }
10954
10955         if (dev_priv->display.crtc_compute_clock) {
10956                 unsigned clear_pipes = modeset_pipes | disable_pipes;
10957
10958                 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10959                 if (ret)
10960                         goto done;
10961
10962                 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10963                         ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10964                         if (ret) {
10965                                 intel_shared_dpll_abort_config(dev_priv);
10966                                 goto done;
10967                         }
10968                 }
10969         }
10970
10971         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10972                 intel_crtc_disable(&intel_crtc->base);
10973
10974         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10975                 if (intel_crtc->base.enabled)
10976                         dev_priv->display.crtc_disable(&intel_crtc->base);
10977         }
10978
10979         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10980          * to set it here already despite that we pass it down the callchain.
10981          *
10982          * Note we'll need to fix this up when we start tracking multiple
10983          * pipes; here we assume a single modeset_pipe and only track the
10984          * single crtc and mode.
10985          */
10986         if (modeset_pipes) {
10987                 crtc->mode = *mode;
10988                 /* mode_set/enable/disable functions rely on a correct pipe
10989                  * config. */
10990                 to_intel_crtc(crtc)->config = *pipe_config;
10991                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10992
10993                 /*
10994                  * Calculate and store various constants which
10995                  * are later needed by vblank and swap-completion
10996                  * timestamping. They are derived from true hwmode.
10997                  */
10998                 drm_calc_timestamping_constants(crtc,
10999                                                 &pipe_config->adjusted_mode);
11000         }
11001
11002         /* Only after disabling all output pipelines that will be changed can we
11003          * update the the output configuration. */
11004         intel_modeset_update_state(dev, prepare_pipes);
11005
11006         modeset_update_crtc_power_domains(dev);
11007
11008         /* Set up the DPLL and any encoders state that needs to adjust or depend
11009          * on the DPLL.
11010          */
11011         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11012                 struct drm_plane *primary = intel_crtc->base.primary;
11013                 int vdisplay, hdisplay;
11014
11015                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11016                 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11017                                                    fb, 0, 0,
11018                                                    hdisplay, vdisplay,
11019                                                    x << 16, y << 16,
11020                                                    hdisplay << 16, vdisplay << 16);
11021         }
11022
11023         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11024         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11025                 update_scanline_offset(intel_crtc);
11026
11027                 dev_priv->display.crtc_enable(&intel_crtc->base);
11028         }
11029
11030         /* FIXME: add subpixel order */
11031 done:
11032         if (ret && crtc->enabled)
11033                 crtc->mode = *saved_mode;
11034
11035         kfree(pipe_config);
11036         kfree(saved_mode);
11037         return ret;
11038 }
11039
11040 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11041                                 struct drm_display_mode *mode,
11042                                 int x, int y, struct drm_framebuffer *fb,
11043                                 struct intel_crtc_config *pipe_config,
11044                                 unsigned modeset_pipes,
11045                                 unsigned prepare_pipes,
11046                                 unsigned disable_pipes)
11047 {
11048         int ret;
11049
11050         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11051                                prepare_pipes, disable_pipes);
11052
11053         if (ret == 0)
11054                 intel_modeset_check_state(crtc->dev);
11055
11056         return ret;
11057 }
11058
11059 static int intel_set_mode(struct drm_crtc *crtc,
11060                           struct drm_display_mode *mode,
11061                           int x, int y, struct drm_framebuffer *fb)
11062 {
11063         struct intel_crtc_config *pipe_config;
11064         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11065
11066         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11067                                                    &modeset_pipes,
11068                                                    &prepare_pipes,
11069                                                    &disable_pipes);
11070
11071         if (IS_ERR(pipe_config))
11072                 return PTR_ERR(pipe_config);
11073
11074         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11075                                     modeset_pipes, prepare_pipes,
11076                                     disable_pipes);
11077 }
11078
11079 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11080 {
11081         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11082 }
11083
11084 #undef for_each_intel_crtc_masked
11085
11086 static void intel_set_config_free(struct intel_set_config *config)
11087 {
11088         if (!config)
11089                 return;
11090
11091         kfree(config->save_connector_encoders);
11092         kfree(config->save_encoder_crtcs);
11093         kfree(config->save_crtc_enabled);
11094         kfree(config);
11095 }
11096
11097 static int intel_set_config_save_state(struct drm_device *dev,
11098                                        struct intel_set_config *config)
11099 {
11100         struct drm_crtc *crtc;
11101         struct drm_encoder *encoder;
11102         struct drm_connector *connector;
11103         int count;
11104
11105         config->save_crtc_enabled =
11106                 kcalloc(dev->mode_config.num_crtc,
11107                         sizeof(bool), GFP_KERNEL);
11108         if (!config->save_crtc_enabled)
11109                 return -ENOMEM;
11110
11111         config->save_encoder_crtcs =
11112                 kcalloc(dev->mode_config.num_encoder,
11113                         sizeof(struct drm_crtc *), GFP_KERNEL);
11114         if (!config->save_encoder_crtcs)
11115                 return -ENOMEM;
11116
11117         config->save_connector_encoders =
11118                 kcalloc(dev->mode_config.num_connector,
11119                         sizeof(struct drm_encoder *), GFP_KERNEL);
11120         if (!config->save_connector_encoders)
11121                 return -ENOMEM;
11122
11123         /* Copy data. Note that driver private data is not affected.
11124          * Should anything bad happen only the expected state is
11125          * restored, not the drivers personal bookkeeping.
11126          */
11127         count = 0;
11128         for_each_crtc(dev, crtc) {
11129                 config->save_crtc_enabled[count++] = crtc->enabled;
11130         }
11131
11132         count = 0;
11133         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11134                 config->save_encoder_crtcs[count++] = encoder->crtc;
11135         }
11136
11137         count = 0;
11138         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11139                 config->save_connector_encoders[count++] = connector->encoder;
11140         }
11141
11142         return 0;
11143 }
11144
11145 static void intel_set_config_restore_state(struct drm_device *dev,
11146                                            struct intel_set_config *config)
11147 {
11148         struct intel_crtc *crtc;
11149         struct intel_encoder *encoder;
11150         struct intel_connector *connector;
11151         int count;
11152
11153         count = 0;
11154         for_each_intel_crtc(dev, crtc) {
11155                 crtc->new_enabled = config->save_crtc_enabled[count++];
11156
11157                 if (crtc->new_enabled)
11158                         crtc->new_config = &crtc->config;
11159                 else
11160                         crtc->new_config = NULL;
11161         }
11162
11163         count = 0;
11164         for_each_intel_encoder(dev, encoder) {
11165                 encoder->new_crtc =
11166                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11167         }
11168
11169         count = 0;
11170         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11171                 connector->new_encoder =
11172                         to_intel_encoder(config->save_connector_encoders[count++]);
11173         }
11174 }
11175
11176 static bool
11177 is_crtc_connector_off(struct drm_mode_set *set)
11178 {
11179         int i;
11180
11181         if (set->num_connectors == 0)
11182                 return false;
11183
11184         if (WARN_ON(set->connectors == NULL))
11185                 return false;
11186
11187         for (i = 0; i < set->num_connectors; i++)
11188                 if (set->connectors[i]->encoder &&
11189                     set->connectors[i]->encoder->crtc == set->crtc &&
11190                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11191                         return true;
11192
11193         return false;
11194 }
11195
11196 static void
11197 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11198                                       struct intel_set_config *config)
11199 {
11200
11201         /* We should be able to check here if the fb has the same properties
11202          * and then just flip_or_move it */
11203         if (is_crtc_connector_off(set)) {
11204                 config->mode_changed = true;
11205         } else if (set->crtc->primary->fb != set->fb) {
11206                 /*
11207                  * If we have no fb, we can only flip as long as the crtc is
11208                  * active, otherwise we need a full mode set.  The crtc may
11209                  * be active if we've only disabled the primary plane, or
11210                  * in fastboot situations.
11211                  */
11212                 if (set->crtc->primary->fb == NULL) {
11213                         struct intel_crtc *intel_crtc =
11214                                 to_intel_crtc(set->crtc);
11215
11216                         if (intel_crtc->active) {
11217                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11218                                 config->fb_changed = true;
11219                         } else {
11220                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11221                                 config->mode_changed = true;
11222                         }
11223                 } else if (set->fb == NULL) {
11224                         config->mode_changed = true;
11225                 } else if (set->fb->pixel_format !=
11226                            set->crtc->primary->fb->pixel_format) {
11227                         config->mode_changed = true;
11228                 } else {
11229                         config->fb_changed = true;
11230                 }
11231         }
11232
11233         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11234                 config->fb_changed = true;
11235
11236         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11237                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11238                 drm_mode_debug_printmodeline(&set->crtc->mode);
11239                 drm_mode_debug_printmodeline(set->mode);
11240                 config->mode_changed = true;
11241         }
11242
11243         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11244                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11245 }
11246
11247 static int
11248 intel_modeset_stage_output_state(struct drm_device *dev,
11249                                  struct drm_mode_set *set,
11250                                  struct intel_set_config *config)
11251 {
11252         struct intel_connector *connector;
11253         struct intel_encoder *encoder;
11254         struct intel_crtc *crtc;
11255         int ro;
11256
11257         /* The upper layers ensure that we either disable a crtc or have a list
11258          * of connectors. For paranoia, double-check this. */
11259         WARN_ON(!set->fb && (set->num_connectors != 0));
11260         WARN_ON(set->fb && (set->num_connectors == 0));
11261
11262         list_for_each_entry(connector, &dev->mode_config.connector_list,
11263                             base.head) {
11264                 /* Otherwise traverse passed in connector list and get encoders
11265                  * for them. */
11266                 for (ro = 0; ro < set->num_connectors; ro++) {
11267                         if (set->connectors[ro] == &connector->base) {
11268                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11269                                 break;
11270                         }
11271                 }
11272
11273                 /* If we disable the crtc, disable all its connectors. Also, if
11274                  * the connector is on the changing crtc but not on the new
11275                  * connector list, disable it. */
11276                 if ((!set->fb || ro == set->num_connectors) &&
11277                     connector->base.encoder &&
11278                     connector->base.encoder->crtc == set->crtc) {
11279                         connector->new_encoder = NULL;
11280
11281                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11282                                 connector->base.base.id,
11283                                 connector->base.name);
11284                 }
11285
11286
11287                 if (&connector->new_encoder->base != connector->base.encoder) {
11288                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11289                         config->mode_changed = true;
11290                 }
11291         }
11292         /* connector->new_encoder is now updated for all connectors. */
11293
11294         /* Update crtc of enabled connectors. */
11295         list_for_each_entry(connector, &dev->mode_config.connector_list,
11296                             base.head) {
11297                 struct drm_crtc *new_crtc;
11298
11299                 if (!connector->new_encoder)
11300                         continue;
11301
11302                 new_crtc = connector->new_encoder->base.crtc;
11303
11304                 for (ro = 0; ro < set->num_connectors; ro++) {
11305                         if (set->connectors[ro] == &connector->base)
11306                                 new_crtc = set->crtc;
11307                 }
11308
11309                 /* Make sure the new CRTC will work with the encoder */
11310                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11311                                          new_crtc)) {
11312                         return -EINVAL;
11313                 }
11314                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11315
11316                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11317                         connector->base.base.id,
11318                         connector->base.name,
11319                         new_crtc->base.id);
11320         }
11321
11322         /* Check for any encoders that needs to be disabled. */
11323         for_each_intel_encoder(dev, encoder) {
11324                 int num_connectors = 0;
11325                 list_for_each_entry(connector,
11326                                     &dev->mode_config.connector_list,
11327                                     base.head) {
11328                         if (connector->new_encoder == encoder) {
11329                                 WARN_ON(!connector->new_encoder->new_crtc);
11330                                 num_connectors++;
11331                         }
11332                 }
11333
11334                 if (num_connectors == 0)
11335                         encoder->new_crtc = NULL;
11336                 else if (num_connectors > 1)
11337                         return -EINVAL;
11338
11339                 /* Only now check for crtc changes so we don't miss encoders
11340                  * that will be disabled. */
11341                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11342                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11343                         config->mode_changed = true;
11344                 }
11345         }
11346         /* Now we've also updated encoder->new_crtc for all encoders. */
11347         list_for_each_entry(connector, &dev->mode_config.connector_list,
11348                             base.head) {
11349                 if (connector->new_encoder)
11350                         if (connector->new_encoder != connector->encoder)
11351                                 connector->encoder = connector->new_encoder;
11352         }
11353         for_each_intel_crtc(dev, crtc) {
11354                 crtc->new_enabled = false;
11355
11356                 for_each_intel_encoder(dev, encoder) {
11357                         if (encoder->new_crtc == crtc) {
11358                                 crtc->new_enabled = true;
11359                                 break;
11360                         }
11361                 }
11362
11363                 if (crtc->new_enabled != crtc->base.enabled) {
11364                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11365                                       crtc->new_enabled ? "en" : "dis");
11366                         config->mode_changed = true;
11367                 }
11368
11369                 if (crtc->new_enabled)
11370                         crtc->new_config = &crtc->config;
11371                 else
11372                         crtc->new_config = NULL;
11373         }
11374
11375         return 0;
11376 }
11377
11378 static void disable_crtc_nofb(struct intel_crtc *crtc)
11379 {
11380         struct drm_device *dev = crtc->base.dev;
11381         struct intel_encoder *encoder;
11382         struct intel_connector *connector;
11383
11384         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11385                       pipe_name(crtc->pipe));
11386
11387         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11388                 if (connector->new_encoder &&
11389                     connector->new_encoder->new_crtc == crtc)
11390                         connector->new_encoder = NULL;
11391         }
11392
11393         for_each_intel_encoder(dev, encoder) {
11394                 if (encoder->new_crtc == crtc)
11395                         encoder->new_crtc = NULL;
11396         }
11397
11398         crtc->new_enabled = false;
11399         crtc->new_config = NULL;
11400 }
11401
11402 static int intel_crtc_set_config(struct drm_mode_set *set)
11403 {
11404         struct drm_device *dev;
11405         struct drm_mode_set save_set;
11406         struct intel_set_config *config;
11407         struct intel_crtc_config *pipe_config;
11408         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11409         int ret;
11410
11411         BUG_ON(!set);
11412         BUG_ON(!set->crtc);
11413         BUG_ON(!set->crtc->helper_private);
11414
11415         /* Enforce sane interface api - has been abused by the fb helper. */
11416         BUG_ON(!set->mode && set->fb);
11417         BUG_ON(set->fb && set->num_connectors == 0);
11418
11419         if (set->fb) {
11420                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11421                                 set->crtc->base.id, set->fb->base.id,
11422                                 (int)set->num_connectors, set->x, set->y);
11423         } else {
11424                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11425         }
11426
11427         dev = set->crtc->dev;
11428
11429         ret = -ENOMEM;
11430         config = kzalloc(sizeof(*config), GFP_KERNEL);
11431         if (!config)
11432                 goto out_config;
11433
11434         ret = intel_set_config_save_state(dev, config);
11435         if (ret)
11436                 goto out_config;
11437
11438         save_set.crtc = set->crtc;
11439         save_set.mode = &set->crtc->mode;
11440         save_set.x = set->crtc->x;
11441         save_set.y = set->crtc->y;
11442         save_set.fb = set->crtc->primary->fb;
11443
11444         /* Compute whether we need a full modeset, only an fb base update or no
11445          * change at all. In the future we might also check whether only the
11446          * mode changed, e.g. for LVDS where we only change the panel fitter in
11447          * such cases. */
11448         intel_set_config_compute_mode_changes(set, config);
11449
11450         ret = intel_modeset_stage_output_state(dev, set, config);
11451         if (ret)
11452                 goto fail;
11453
11454         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11455                                                    set->fb,
11456                                                    &modeset_pipes,
11457                                                    &prepare_pipes,
11458                                                    &disable_pipes);
11459         if (IS_ERR(pipe_config)) {
11460                 ret = PTR_ERR(pipe_config);
11461                 goto fail;
11462         } else if (pipe_config) {
11463                 if (pipe_config->has_audio !=
11464                     to_intel_crtc(set->crtc)->config.has_audio)
11465                         config->mode_changed = true;
11466
11467                 /*
11468                  * Note we have an issue here with infoframes: current code
11469                  * only updates them on the full mode set path per hw
11470                  * requirements.  So here we should be checking for any
11471                  * required changes and forcing a mode set.
11472                  */
11473         }
11474
11475         /* set_mode will free it in the mode_changed case */
11476         if (!config->mode_changed)
11477                 kfree(pipe_config);
11478
11479         intel_update_pipe_size(to_intel_crtc(set->crtc));
11480
11481         if (config->mode_changed) {
11482                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11483                                            set->x, set->y, set->fb, pipe_config,
11484                                            modeset_pipes, prepare_pipes,
11485                                            disable_pipes);
11486         } else if (config->fb_changed) {
11487                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11488                 struct drm_plane *primary = set->crtc->primary;
11489                 int vdisplay, hdisplay;
11490
11491                 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11492                 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11493                                                    0, 0, hdisplay, vdisplay,
11494                                                    set->x << 16, set->y << 16,
11495                                                    hdisplay << 16, vdisplay << 16);
11496
11497                 /*
11498                  * We need to make sure the primary plane is re-enabled if it
11499                  * has previously been turned off.
11500                  */
11501                 if (!intel_crtc->primary_enabled && ret == 0) {
11502                         WARN_ON(!intel_crtc->active);
11503                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11504                 }
11505
11506                 /*
11507                  * In the fastboot case this may be our only check of the
11508                  * state after boot.  It would be better to only do it on
11509                  * the first update, but we don't have a nice way of doing that
11510                  * (and really, set_config isn't used much for high freq page
11511                  * flipping, so increasing its cost here shouldn't be a big
11512                  * deal).
11513                  */
11514                 if (i915.fastboot && ret == 0)
11515                         intel_modeset_check_state(set->crtc->dev);
11516         }
11517
11518         if (ret) {
11519                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11520                               set->crtc->base.id, ret);
11521 fail:
11522                 intel_set_config_restore_state(dev, config);
11523
11524                 /*
11525                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11526                  * force the pipe off to avoid oopsing in the modeset code
11527                  * due to fb==NULL. This should only happen during boot since
11528                  * we don't yet reconstruct the FB from the hardware state.
11529                  */
11530                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11531                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11532
11533                 /* Try to restore the config */
11534                 if (config->mode_changed &&
11535                     intel_set_mode(save_set.crtc, save_set.mode,
11536                                    save_set.x, save_set.y, save_set.fb))
11537                         DRM_ERROR("failed to restore config after modeset failure\n");
11538         }
11539
11540 out_config:
11541         intel_set_config_free(config);
11542         return ret;
11543 }
11544
11545 static const struct drm_crtc_funcs intel_crtc_funcs = {
11546         .gamma_set = intel_crtc_gamma_set,
11547         .set_config = intel_crtc_set_config,
11548         .destroy = intel_crtc_destroy,
11549         .page_flip = intel_crtc_page_flip,
11550 };
11551
11552 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11553                                       struct intel_shared_dpll *pll,
11554                                       struct intel_dpll_hw_state *hw_state)
11555 {
11556         uint32_t val;
11557
11558         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11559                 return false;
11560
11561         val = I915_READ(PCH_DPLL(pll->id));
11562         hw_state->dpll = val;
11563         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11564         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11565
11566         return val & DPLL_VCO_ENABLE;
11567 }
11568
11569 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11570                                   struct intel_shared_dpll *pll)
11571 {
11572         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11573         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11574 }
11575
11576 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11577                                 struct intel_shared_dpll *pll)
11578 {
11579         /* PCH refclock must be enabled first */
11580         ibx_assert_pch_refclk_enabled(dev_priv);
11581
11582         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11583
11584         /* Wait for the clocks to stabilize. */
11585         POSTING_READ(PCH_DPLL(pll->id));
11586         udelay(150);
11587
11588         /* The pixel multiplier can only be updated once the
11589          * DPLL is enabled and the clocks are stable.
11590          *
11591          * So write it again.
11592          */
11593         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11594         POSTING_READ(PCH_DPLL(pll->id));
11595         udelay(200);
11596 }
11597
11598 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11599                                  struct intel_shared_dpll *pll)
11600 {
11601         struct drm_device *dev = dev_priv->dev;
11602         struct intel_crtc *crtc;
11603
11604         /* Make sure no transcoder isn't still depending on us. */
11605         for_each_intel_crtc(dev, crtc) {
11606                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11607                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11608         }
11609
11610         I915_WRITE(PCH_DPLL(pll->id), 0);
11611         POSTING_READ(PCH_DPLL(pll->id));
11612         udelay(200);
11613 }
11614
11615 static char *ibx_pch_dpll_names[] = {
11616         "PCH DPLL A",
11617         "PCH DPLL B",
11618 };
11619
11620 static void ibx_pch_dpll_init(struct drm_device *dev)
11621 {
11622         struct drm_i915_private *dev_priv = dev->dev_private;
11623         int i;
11624
11625         dev_priv->num_shared_dpll = 2;
11626
11627         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11628                 dev_priv->shared_dplls[i].id = i;
11629                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11630                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11631                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11632                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11633                 dev_priv->shared_dplls[i].get_hw_state =
11634                         ibx_pch_dpll_get_hw_state;
11635         }
11636 }
11637
11638 static void intel_shared_dpll_init(struct drm_device *dev)
11639 {
11640         struct drm_i915_private *dev_priv = dev->dev_private;
11641
11642         if (HAS_DDI(dev))
11643                 intel_ddi_pll_init(dev);
11644         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11645                 ibx_pch_dpll_init(dev);
11646         else
11647                 dev_priv->num_shared_dpll = 0;
11648
11649         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11650 }
11651
11652 /**
11653  * intel_prepare_plane_fb - Prepare fb for usage on plane
11654  * @plane: drm plane to prepare for
11655  * @fb: framebuffer to prepare for presentation
11656  *
11657  * Prepares a framebuffer for usage on a display plane.  Generally this
11658  * involves pinning the underlying object and updating the frontbuffer tracking
11659  * bits.  Some older platforms need special physical address handling for
11660  * cursor planes.
11661  *
11662  * Returns 0 on success, negative error code on failure.
11663  */
11664 int
11665 intel_prepare_plane_fb(struct drm_plane *plane,
11666                        struct drm_framebuffer *fb)
11667 {
11668         struct drm_device *dev = plane->dev;
11669         struct intel_plane *intel_plane = to_intel_plane(plane);
11670         enum pipe pipe = intel_plane->pipe;
11671         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11672         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11673         unsigned frontbuffer_bits = 0;
11674         int ret = 0;
11675
11676         if (WARN_ON(fb == plane->fb || !obj))
11677                 return 0;
11678
11679         switch (plane->type) {
11680         case DRM_PLANE_TYPE_PRIMARY:
11681                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11682                 break;
11683         case DRM_PLANE_TYPE_CURSOR:
11684                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11685                 break;
11686         case DRM_PLANE_TYPE_OVERLAY:
11687                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11688                 break;
11689         }
11690
11691         mutex_lock(&dev->struct_mutex);
11692
11693         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11694             INTEL_INFO(dev)->cursor_needs_physical) {
11695                 int align = IS_I830(dev) ? 16 * 1024 : 256;
11696                 ret = i915_gem_object_attach_phys(obj, align);
11697                 if (ret)
11698                         DRM_DEBUG_KMS("failed to attach phys object\n");
11699         } else {
11700                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11701         }
11702
11703         if (ret == 0)
11704                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11705
11706         mutex_unlock(&dev->struct_mutex);
11707
11708         return ret;
11709 }
11710
11711 /**
11712  * intel_cleanup_plane_fb - Cleans up an fb after plane use
11713  * @plane: drm plane to clean up for
11714  * @fb: old framebuffer that was on plane
11715  *
11716  * Cleans up a framebuffer that has just been removed from a plane.
11717  */
11718 void
11719 intel_cleanup_plane_fb(struct drm_plane *plane,
11720                        struct drm_framebuffer *fb)
11721 {
11722         struct drm_device *dev = plane->dev;
11723         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11724
11725         if (WARN_ON(!obj))
11726                 return;
11727
11728         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11729             !INTEL_INFO(dev)->cursor_needs_physical) {
11730                 mutex_lock(&dev->struct_mutex);
11731                 intel_unpin_fb_obj(obj);
11732                 mutex_unlock(&dev->struct_mutex);
11733         }
11734 }
11735
11736 static int
11737 intel_check_primary_plane(struct drm_plane *plane,
11738                           struct intel_plane_state *state)
11739 {
11740         struct drm_crtc *crtc = state->base.crtc;
11741         struct drm_framebuffer *fb = state->base.fb;
11742         struct drm_rect *dest = &state->dst;
11743         struct drm_rect *src = &state->src;
11744         const struct drm_rect *clip = &state->clip;
11745         int ret;
11746
11747         ret = drm_plane_helper_check_update(plane, crtc, fb,
11748                                             src, dest, clip,
11749                                             DRM_PLANE_HELPER_NO_SCALING,
11750                                             DRM_PLANE_HELPER_NO_SCALING,
11751                                             false, true, &state->visible);
11752         if (ret)
11753                 return ret;
11754
11755         intel_crtc_wait_for_pending_flips(crtc);
11756         if (intel_crtc_has_pending_flip(crtc)) {
11757                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11758                 return -EBUSY;
11759         }
11760
11761         return 0;
11762 }
11763
11764 static void
11765 intel_commit_primary_plane(struct drm_plane *plane,
11766                            struct intel_plane_state *state)
11767 {
11768         struct drm_crtc *crtc = state->base.crtc;
11769         struct drm_framebuffer *fb = state->base.fb;
11770         struct drm_device *dev = plane->dev;
11771         struct drm_i915_private *dev_priv = dev->dev_private;
11772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11773         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11774         struct intel_plane *intel_plane = to_intel_plane(plane);
11775         struct drm_rect *src = &state->src;
11776         enum pipe pipe = intel_plane->pipe;
11777
11778         if (!fb) {
11779                 /*
11780                  * 'prepare' is never called when plane is being disabled, so
11781                  * we need to handle frontbuffer tracking here
11782                  */
11783                 mutex_lock(&dev->struct_mutex);
11784                 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11785                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
11786                 mutex_unlock(&dev->struct_mutex);
11787         }
11788
11789         plane->fb = fb;
11790         crtc->x = src->x1 >> 16;
11791         crtc->y = src->y1 >> 16;
11792
11793         intel_plane->crtc_x = state->orig_dst.x1;
11794         intel_plane->crtc_y = state->orig_dst.y1;
11795         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11796         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11797         intel_plane->src_x = state->orig_src.x1;
11798         intel_plane->src_y = state->orig_src.y1;
11799         intel_plane->src_w = drm_rect_width(&state->orig_src);
11800         intel_plane->src_h = drm_rect_height(&state->orig_src);
11801         intel_plane->obj = obj;
11802
11803         if (intel_crtc->active) {
11804                 /*
11805                  * FBC does not work on some platforms for rotated
11806                  * planes, so disable it when rotation is not 0 and
11807                  * update it when rotation is set back to 0.
11808                  *
11809                  * FIXME: This is redundant with the fbc update done in
11810                  * the primary plane enable function except that that
11811                  * one is done too late. We eventually need to unify
11812                  * this.
11813                  */
11814                 if (intel_crtc->primary_enabled &&
11815                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11816                     dev_priv->fbc.plane == intel_crtc->plane &&
11817                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11818                         intel_fbc_disable(dev);
11819                 }
11820
11821                 if (state->visible) {
11822                         bool was_enabled = intel_crtc->primary_enabled;
11823
11824                         /* FIXME: kill this fastboot hack */
11825                         intel_update_pipe_size(intel_crtc);
11826
11827                         intel_crtc->primary_enabled = true;
11828
11829                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11830                                         crtc->x, crtc->y);
11831
11832                         /*
11833                          * BDW signals flip done immediately if the plane
11834                          * is disabled, even if the plane enable is already
11835                          * armed to occur at the next vblank :(
11836                          */
11837                         if (IS_BROADWELL(dev) && !was_enabled)
11838                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11839                 } else {
11840                         /*
11841                          * If clipping results in a non-visible primary plane,
11842                          * we'll disable the primary plane.  Note that this is
11843                          * a bit different than what happens if userspace
11844                          * explicitly disables the plane by passing fb=0
11845                          * because plane->fb still gets set and pinned.
11846                          */
11847                         intel_disable_primary_hw_plane(plane, crtc);
11848                 }
11849
11850                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11851
11852                 mutex_lock(&dev->struct_mutex);
11853                 intel_fbc_update(dev);
11854                 mutex_unlock(&dev->struct_mutex);
11855         }
11856 }
11857
11858 int
11859 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
11860                    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11861                    unsigned int crtc_w, unsigned int crtc_h,
11862                    uint32_t src_x, uint32_t src_y,
11863                    uint32_t src_w, uint32_t src_h)
11864 {
11865         struct drm_device *dev = plane->dev;
11866         struct drm_i915_private *dev_priv = dev->dev_private;
11867         struct drm_framebuffer *old_fb = plane->fb;
11868         struct intel_plane_state state;
11869         struct intel_plane *intel_plane = to_intel_plane(plane);
11870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11871         int ret;
11872
11873         state.base.crtc = crtc ? crtc : plane->crtc;
11874         state.base.fb = fb;
11875
11876         /* sample coordinates in 16.16 fixed point */
11877         state.src.x1 = src_x;
11878         state.src.x2 = src_x + src_w;
11879         state.src.y1 = src_y;
11880         state.src.y2 = src_y + src_h;
11881
11882         /* integer pixels */
11883         state.dst.x1 = crtc_x;
11884         state.dst.x2 = crtc_x + crtc_w;
11885         state.dst.y1 = crtc_y;
11886         state.dst.y2 = crtc_y + crtc_h;
11887
11888         state.clip.x1 = 0;
11889         state.clip.y1 = 0;
11890         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11891         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11892
11893         state.orig_src = state.src;
11894         state.orig_dst = state.dst;
11895
11896         ret = intel_plane->check_plane(plane, &state);
11897         if (ret)
11898                 return ret;
11899
11900         if (fb != old_fb && fb) {
11901                 ret = intel_prepare_plane_fb(plane, fb);
11902                 if (ret)
11903                         return ret;
11904         }
11905
11906         intel_runtime_pm_get(dev_priv);
11907         intel_plane->commit_plane(plane, &state);
11908         intel_runtime_pm_put(dev_priv);
11909
11910         if (fb != old_fb && old_fb) {
11911                 if (intel_crtc->active)
11912                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11913                 intel_cleanup_plane_fb(plane, old_fb);
11914         }
11915
11916         plane->fb = fb;
11917
11918         return 0;
11919 }
11920
11921 /**
11922  * intel_disable_plane - disable a plane
11923  * @plane: plane to disable
11924  *
11925  * General disable handler for all plane types.
11926  */
11927 int
11928 intel_disable_plane(struct drm_plane *plane)
11929 {
11930         if (!plane->fb)
11931                 return 0;
11932
11933         if (WARN_ON(!plane->crtc))
11934                 return -EINVAL;
11935
11936         return plane->funcs->update_plane(plane, plane->crtc, NULL,
11937                                           0, 0, 0, 0, 0, 0, 0, 0);
11938 }
11939
11940 /* Common destruction function for both primary and cursor planes */
11941 static void intel_plane_destroy(struct drm_plane *plane)
11942 {
11943         struct intel_plane *intel_plane = to_intel_plane(plane);
11944         drm_plane_cleanup(plane);
11945         kfree(intel_plane);
11946 }
11947
11948 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11949         .update_plane = intel_update_plane,
11950         .disable_plane = intel_disable_plane,
11951         .destroy = intel_plane_destroy,
11952         .set_property = intel_plane_set_property
11953 };
11954
11955 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11956                                                     int pipe)
11957 {
11958         struct intel_plane *primary;
11959         const uint32_t *intel_primary_formats;
11960         int num_formats;
11961
11962         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11963         if (primary == NULL)
11964                 return NULL;
11965
11966         primary->can_scale = false;
11967         primary->max_downscale = 1;
11968         primary->pipe = pipe;
11969         primary->plane = pipe;
11970         primary->rotation = BIT(DRM_ROTATE_0);
11971         primary->check_plane = intel_check_primary_plane;
11972         primary->commit_plane = intel_commit_primary_plane;
11973         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11974                 primary->plane = !pipe;
11975
11976         if (INTEL_INFO(dev)->gen <= 3) {
11977                 intel_primary_formats = intel_primary_formats_gen2;
11978                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11979         } else {
11980                 intel_primary_formats = intel_primary_formats_gen4;
11981                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11982         }
11983
11984         drm_universal_plane_init(dev, &primary->base, 0,
11985                                  &intel_primary_plane_funcs,
11986                                  intel_primary_formats, num_formats,
11987                                  DRM_PLANE_TYPE_PRIMARY);
11988
11989         if (INTEL_INFO(dev)->gen >= 4) {
11990                 if (!dev->mode_config.rotation_property)
11991                         dev->mode_config.rotation_property =
11992                                 drm_mode_create_rotation_property(dev,
11993                                                         BIT(DRM_ROTATE_0) |
11994                                                         BIT(DRM_ROTATE_180));
11995                 if (dev->mode_config.rotation_property)
11996                         drm_object_attach_property(&primary->base.base,
11997                                 dev->mode_config.rotation_property,
11998                                 primary->rotation);
11999         }
12000
12001         return &primary->base;
12002 }
12003
12004 static int
12005 intel_check_cursor_plane(struct drm_plane *plane,
12006                          struct intel_plane_state *state)
12007 {
12008         struct drm_crtc *crtc = state->base.crtc;
12009         struct drm_device *dev = crtc->dev;
12010         struct drm_framebuffer *fb = state->base.fb;
12011         struct drm_rect *dest = &state->dst;
12012         struct drm_rect *src = &state->src;
12013         const struct drm_rect *clip = &state->clip;
12014         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12015         int crtc_w, crtc_h;
12016         unsigned stride;
12017         int ret;
12018
12019         ret = drm_plane_helper_check_update(plane, crtc, fb,
12020                                             src, dest, clip,
12021                                             DRM_PLANE_HELPER_NO_SCALING,
12022                                             DRM_PLANE_HELPER_NO_SCALING,
12023                                             true, true, &state->visible);
12024         if (ret)
12025                 return ret;
12026
12027
12028         /* if we want to turn off the cursor ignore width and height */
12029         if (!obj)
12030                 return 0;
12031
12032         /* Check for which cursor types we support */
12033         crtc_w = drm_rect_width(&state->orig_dst);
12034         crtc_h = drm_rect_height(&state->orig_dst);
12035         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
12036                 DRM_DEBUG("Cursor dimension not supported\n");
12037                 return -EINVAL;
12038         }
12039
12040         stride = roundup_pow_of_two(crtc_w) * 4;
12041         if (obj->base.size < stride * crtc_h) {
12042                 DRM_DEBUG_KMS("buffer is too small\n");
12043                 return -ENOMEM;
12044         }
12045
12046         if (fb == crtc->cursor->fb)
12047                 return 0;
12048
12049         /* we only need to pin inside GTT if cursor is non-phy */
12050         mutex_lock(&dev->struct_mutex);
12051         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12052                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12053                 ret = -EINVAL;
12054         }
12055         mutex_unlock(&dev->struct_mutex);
12056
12057         return ret;
12058 }
12059
12060 static void
12061 intel_commit_cursor_plane(struct drm_plane *plane,
12062                           struct intel_plane_state *state)
12063 {
12064         struct drm_crtc *crtc = state->base.crtc;
12065         struct drm_device *dev = crtc->dev;
12066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12067         struct intel_plane *intel_plane = to_intel_plane(plane);
12068         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12069         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12070         enum pipe pipe = intel_crtc->pipe;
12071         unsigned old_width;
12072         uint32_t addr;
12073
12074         plane->fb = state->base.fb;
12075         crtc->cursor_x = state->orig_dst.x1;
12076         crtc->cursor_y = state->orig_dst.y1;
12077
12078         intel_plane->crtc_x = state->orig_dst.x1;
12079         intel_plane->crtc_y = state->orig_dst.y1;
12080         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
12081         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
12082         intel_plane->src_x = state->orig_src.x1;
12083         intel_plane->src_y = state->orig_src.y1;
12084         intel_plane->src_w = drm_rect_width(&state->orig_src);
12085         intel_plane->src_h = drm_rect_height(&state->orig_src);
12086         intel_plane->obj = obj;
12087
12088         if (intel_crtc->cursor_bo == obj)
12089                 goto update;
12090
12091         /*
12092          * 'prepare' is only called when fb != NULL; we still need to update
12093          * frontbuffer tracking for the 'disable' case here.
12094          */
12095         if (!obj) {
12096                 mutex_lock(&dev->struct_mutex);
12097                 i915_gem_track_fb(old_obj, NULL,
12098                                   INTEL_FRONTBUFFER_CURSOR(pipe));
12099                 mutex_unlock(&dev->struct_mutex);
12100         }
12101
12102         if (!obj)
12103                 addr = 0;
12104         else if (!INTEL_INFO(dev)->cursor_needs_physical)
12105                 addr = i915_gem_obj_ggtt_offset(obj);
12106         else
12107                 addr = obj->phys_handle->busaddr;
12108
12109         intel_crtc->cursor_addr = addr;
12110         intel_crtc->cursor_bo = obj;
12111 update:
12112         old_width = intel_crtc->cursor_width;
12113
12114         intel_crtc->cursor_width = drm_rect_width(&state->orig_dst);
12115         intel_crtc->cursor_height = drm_rect_height(&state->orig_dst);
12116
12117         if (intel_crtc->active) {
12118                 if (old_width != intel_crtc->cursor_width)
12119                         intel_update_watermarks(crtc);
12120                 intel_crtc_update_cursor(crtc, state->visible);
12121
12122                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
12123         }
12124 }
12125
12126 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12127         .update_plane = intel_update_plane,
12128         .disable_plane = intel_disable_plane,
12129         .destroy = intel_plane_destroy,
12130         .set_property = intel_plane_set_property,
12131 };
12132
12133 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12134                                                    int pipe)
12135 {
12136         struct intel_plane *cursor;
12137
12138         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12139         if (cursor == NULL)
12140                 return NULL;
12141
12142         cursor->can_scale = false;
12143         cursor->max_downscale = 1;
12144         cursor->pipe = pipe;
12145         cursor->plane = pipe;
12146         cursor->rotation = BIT(DRM_ROTATE_0);
12147         cursor->check_plane = intel_check_cursor_plane;
12148         cursor->commit_plane = intel_commit_cursor_plane;
12149
12150         drm_universal_plane_init(dev, &cursor->base, 0,
12151                                  &intel_cursor_plane_funcs,
12152                                  intel_cursor_formats,
12153                                  ARRAY_SIZE(intel_cursor_formats),
12154                                  DRM_PLANE_TYPE_CURSOR);
12155
12156         if (INTEL_INFO(dev)->gen >= 4) {
12157                 if (!dev->mode_config.rotation_property)
12158                         dev->mode_config.rotation_property =
12159                                 drm_mode_create_rotation_property(dev,
12160                                                         BIT(DRM_ROTATE_0) |
12161                                                         BIT(DRM_ROTATE_180));
12162                 if (dev->mode_config.rotation_property)
12163                         drm_object_attach_property(&cursor->base.base,
12164                                 dev->mode_config.rotation_property,
12165                                 cursor->rotation);
12166         }
12167
12168         return &cursor->base;
12169 }
12170
12171 static void intel_crtc_init(struct drm_device *dev, int pipe)
12172 {
12173         struct drm_i915_private *dev_priv = dev->dev_private;
12174         struct intel_crtc *intel_crtc;
12175         struct drm_plane *primary = NULL;
12176         struct drm_plane *cursor = NULL;
12177         int i, ret;
12178
12179         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12180         if (intel_crtc == NULL)
12181                 return;
12182
12183         primary = intel_primary_plane_create(dev, pipe);
12184         if (!primary)
12185                 goto fail;
12186
12187         cursor = intel_cursor_plane_create(dev, pipe);
12188         if (!cursor)
12189                 goto fail;
12190
12191         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12192                                         cursor, &intel_crtc_funcs);
12193         if (ret)
12194                 goto fail;
12195
12196         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12197         for (i = 0; i < 256; i++) {
12198                 intel_crtc->lut_r[i] = i;
12199                 intel_crtc->lut_g[i] = i;
12200                 intel_crtc->lut_b[i] = i;
12201         }
12202
12203         /*
12204          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12205          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12206          */
12207         intel_crtc->pipe = pipe;
12208         intel_crtc->plane = pipe;
12209         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12210                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12211                 intel_crtc->plane = !pipe;
12212         }
12213
12214         intel_crtc->cursor_base = ~0;
12215         intel_crtc->cursor_cntl = ~0;
12216         intel_crtc->cursor_size = ~0;
12217
12218         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12219                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12220         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12221         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12222
12223         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12224
12225         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12226
12227         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12228         return;
12229
12230 fail:
12231         if (primary)
12232                 drm_plane_cleanup(primary);
12233         if (cursor)
12234                 drm_plane_cleanup(cursor);
12235         kfree(intel_crtc);
12236 }
12237
12238 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12239 {
12240         struct drm_encoder *encoder = connector->base.encoder;
12241         struct drm_device *dev = connector->base.dev;
12242
12243         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12244
12245         if (!encoder || WARN_ON(!encoder->crtc))
12246                 return INVALID_PIPE;
12247
12248         return to_intel_crtc(encoder->crtc)->pipe;
12249 }
12250
12251 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12252                                 struct drm_file *file)
12253 {
12254         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12255         struct drm_crtc *drmmode_crtc;
12256         struct intel_crtc *crtc;
12257
12258         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12259                 return -ENODEV;
12260
12261         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12262
12263         if (!drmmode_crtc) {
12264                 DRM_ERROR("no such CRTC id\n");
12265                 return -ENOENT;
12266         }
12267
12268         crtc = to_intel_crtc(drmmode_crtc);
12269         pipe_from_crtc_id->pipe = crtc->pipe;
12270
12271         return 0;
12272 }
12273
12274 static int intel_encoder_clones(struct intel_encoder *encoder)
12275 {
12276         struct drm_device *dev = encoder->base.dev;
12277         struct intel_encoder *source_encoder;
12278         int index_mask = 0;
12279         int entry = 0;
12280
12281         for_each_intel_encoder(dev, source_encoder) {
12282                 if (encoders_cloneable(encoder, source_encoder))
12283                         index_mask |= (1 << entry);
12284
12285                 entry++;
12286         }
12287
12288         return index_mask;
12289 }
12290
12291 static bool has_edp_a(struct drm_device *dev)
12292 {
12293         struct drm_i915_private *dev_priv = dev->dev_private;
12294
12295         if (!IS_MOBILE(dev))
12296                 return false;
12297
12298         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12299                 return false;
12300
12301         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12302                 return false;
12303
12304         return true;
12305 }
12306
12307 static bool intel_crt_present(struct drm_device *dev)
12308 {
12309         struct drm_i915_private *dev_priv = dev->dev_private;
12310
12311         if (INTEL_INFO(dev)->gen >= 9)
12312                 return false;
12313
12314         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12315                 return false;
12316
12317         if (IS_CHERRYVIEW(dev))
12318                 return false;
12319
12320         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12321                 return false;
12322
12323         return true;
12324 }
12325
12326 static void intel_setup_outputs(struct drm_device *dev)
12327 {
12328         struct drm_i915_private *dev_priv = dev->dev_private;
12329         struct intel_encoder *encoder;
12330         bool dpd_is_edp = false;
12331
12332         intel_lvds_init(dev);
12333
12334         if (intel_crt_present(dev))
12335                 intel_crt_init(dev);
12336
12337         if (HAS_DDI(dev)) {
12338                 int found;
12339
12340                 /* Haswell uses DDI functions to detect digital outputs */
12341                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12342                 /* DDI A only supports eDP */
12343                 if (found)
12344                         intel_ddi_init(dev, PORT_A);
12345
12346                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12347                  * register */
12348                 found = I915_READ(SFUSE_STRAP);
12349
12350                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12351                         intel_ddi_init(dev, PORT_B);
12352                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12353                         intel_ddi_init(dev, PORT_C);
12354                 if (found & SFUSE_STRAP_DDID_DETECTED)
12355                         intel_ddi_init(dev, PORT_D);
12356         } else if (HAS_PCH_SPLIT(dev)) {
12357                 int found;
12358                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12359
12360                 if (has_edp_a(dev))
12361                         intel_dp_init(dev, DP_A, PORT_A);
12362
12363                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12364                         /* PCH SDVOB multiplex with HDMIB */
12365                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12366                         if (!found)
12367                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12368                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12369                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12370                 }
12371
12372                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12373                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12374
12375                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12376                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12377
12378                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12379                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12380
12381                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12382                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12383         } else if (IS_VALLEYVIEW(dev)) {
12384                 /*
12385                  * The DP_DETECTED bit is the latched state of the DDC
12386                  * SDA pin at boot. However since eDP doesn't require DDC
12387                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12388                  * eDP ports may have been muxed to an alternate function.
12389                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12390                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12391                  * detect eDP ports.
12392                  */
12393                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12394                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12395                                         PORT_B);
12396                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12397                     intel_dp_is_edp(dev, PORT_B))
12398                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12399
12400                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12401                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12402                                         PORT_C);
12403                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12404                     intel_dp_is_edp(dev, PORT_C))
12405                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12406
12407                 if (IS_CHERRYVIEW(dev)) {
12408                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12409                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12410                                                 PORT_D);
12411                         /* eDP not supported on port D, so don't check VBT */
12412                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12413                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12414                 }
12415
12416                 intel_dsi_init(dev);
12417         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12418                 bool found = false;
12419
12420                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12421                         DRM_DEBUG_KMS("probing SDVOB\n");
12422                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12423                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12424                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12425                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12426                         }
12427
12428                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12429                                 intel_dp_init(dev, DP_B, PORT_B);
12430                 }
12431
12432                 /* Before G4X SDVOC doesn't have its own detect register */
12433
12434                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12435                         DRM_DEBUG_KMS("probing SDVOC\n");
12436                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12437                 }
12438
12439                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12440
12441                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12442                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12443                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12444                         }
12445                         if (SUPPORTS_INTEGRATED_DP(dev))
12446                                 intel_dp_init(dev, DP_C, PORT_C);
12447                 }
12448
12449                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12450                     (I915_READ(DP_D) & DP_DETECTED))
12451                         intel_dp_init(dev, DP_D, PORT_D);
12452         } else if (IS_GEN2(dev))
12453                 intel_dvo_init(dev);
12454
12455         if (SUPPORTS_TV(dev))
12456                 intel_tv_init(dev);
12457
12458         intel_psr_init(dev);
12459
12460         for_each_intel_encoder(dev, encoder) {
12461                 encoder->base.possible_crtcs = encoder->crtc_mask;
12462                 encoder->base.possible_clones =
12463                         intel_encoder_clones(encoder);
12464         }
12465
12466         intel_init_pch_refclk(dev);
12467
12468         drm_helper_move_panel_connectors_to_head(dev);
12469 }
12470
12471 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12472 {
12473         struct drm_device *dev = fb->dev;
12474         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12475
12476         drm_framebuffer_cleanup(fb);
12477         mutex_lock(&dev->struct_mutex);
12478         WARN_ON(!intel_fb->obj->framebuffer_references--);
12479         drm_gem_object_unreference(&intel_fb->obj->base);
12480         mutex_unlock(&dev->struct_mutex);
12481         kfree(intel_fb);
12482 }
12483
12484 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12485                                                 struct drm_file *file,
12486                                                 unsigned int *handle)
12487 {
12488         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12489         struct drm_i915_gem_object *obj = intel_fb->obj;
12490
12491         return drm_gem_handle_create(file, &obj->base, handle);
12492 }
12493
12494 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12495         .destroy = intel_user_framebuffer_destroy,
12496         .create_handle = intel_user_framebuffer_create_handle,
12497 };
12498
12499 static int intel_framebuffer_init(struct drm_device *dev,
12500                                   struct intel_framebuffer *intel_fb,
12501                                   struct drm_mode_fb_cmd2 *mode_cmd,
12502                                   struct drm_i915_gem_object *obj)
12503 {
12504         int aligned_height;
12505         int pitch_limit;
12506         int ret;
12507
12508         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12509
12510         if (obj->tiling_mode == I915_TILING_Y) {
12511                 DRM_DEBUG("hardware does not support tiling Y\n");
12512                 return -EINVAL;
12513         }
12514
12515         if (mode_cmd->pitches[0] & 63) {
12516                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12517                           mode_cmd->pitches[0]);
12518                 return -EINVAL;
12519         }
12520
12521         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12522                 pitch_limit = 32*1024;
12523         } else if (INTEL_INFO(dev)->gen >= 4) {
12524                 if (obj->tiling_mode)
12525                         pitch_limit = 16*1024;
12526                 else
12527                         pitch_limit = 32*1024;
12528         } else if (INTEL_INFO(dev)->gen >= 3) {
12529                 if (obj->tiling_mode)
12530                         pitch_limit = 8*1024;
12531                 else
12532                         pitch_limit = 16*1024;
12533         } else
12534                 /* XXX DSPC is limited to 4k tiled */
12535                 pitch_limit = 8*1024;
12536
12537         if (mode_cmd->pitches[0] > pitch_limit) {
12538                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12539                           obj->tiling_mode ? "tiled" : "linear",
12540                           mode_cmd->pitches[0], pitch_limit);
12541                 return -EINVAL;
12542         }
12543
12544         if (obj->tiling_mode != I915_TILING_NONE &&
12545             mode_cmd->pitches[0] != obj->stride) {
12546                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12547                           mode_cmd->pitches[0], obj->stride);
12548                 return -EINVAL;
12549         }
12550
12551         /* Reject formats not supported by any plane early. */
12552         switch (mode_cmd->pixel_format) {
12553         case DRM_FORMAT_C8:
12554         case DRM_FORMAT_RGB565:
12555         case DRM_FORMAT_XRGB8888:
12556         case DRM_FORMAT_ARGB8888:
12557                 break;
12558         case DRM_FORMAT_XRGB1555:
12559         case DRM_FORMAT_ARGB1555:
12560                 if (INTEL_INFO(dev)->gen > 3) {
12561                         DRM_DEBUG("unsupported pixel format: %s\n",
12562                                   drm_get_format_name(mode_cmd->pixel_format));
12563                         return -EINVAL;
12564                 }
12565                 break;
12566         case DRM_FORMAT_XBGR8888:
12567         case DRM_FORMAT_ABGR8888:
12568         case DRM_FORMAT_XRGB2101010:
12569         case DRM_FORMAT_ARGB2101010:
12570         case DRM_FORMAT_XBGR2101010:
12571         case DRM_FORMAT_ABGR2101010:
12572                 if (INTEL_INFO(dev)->gen < 4) {
12573                         DRM_DEBUG("unsupported pixel format: %s\n",
12574                                   drm_get_format_name(mode_cmd->pixel_format));
12575                         return -EINVAL;
12576                 }
12577                 break;
12578         case DRM_FORMAT_YUYV:
12579         case DRM_FORMAT_UYVY:
12580         case DRM_FORMAT_YVYU:
12581         case DRM_FORMAT_VYUY:
12582                 if (INTEL_INFO(dev)->gen < 5) {
12583                         DRM_DEBUG("unsupported pixel format: %s\n",
12584                                   drm_get_format_name(mode_cmd->pixel_format));
12585                         return -EINVAL;
12586                 }
12587                 break;
12588         default:
12589                 DRM_DEBUG("unsupported pixel format: %s\n",
12590                           drm_get_format_name(mode_cmd->pixel_format));
12591                 return -EINVAL;
12592         }
12593
12594         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12595         if (mode_cmd->offsets[0] != 0)
12596                 return -EINVAL;
12597
12598         aligned_height = intel_align_height(dev, mode_cmd->height,
12599                                             obj->tiling_mode);
12600         /* FIXME drm helper for size checks (especially planar formats)? */
12601         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12602                 return -EINVAL;
12603
12604         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12605         intel_fb->obj = obj;
12606         intel_fb->obj->framebuffer_references++;
12607
12608         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12609         if (ret) {
12610                 DRM_ERROR("framebuffer init failed %d\n", ret);
12611                 return ret;
12612         }
12613
12614         return 0;
12615 }
12616
12617 static struct drm_framebuffer *
12618 intel_user_framebuffer_create(struct drm_device *dev,
12619                               struct drm_file *filp,
12620                               struct drm_mode_fb_cmd2 *mode_cmd)
12621 {
12622         struct drm_i915_gem_object *obj;
12623
12624         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12625                                                 mode_cmd->handles[0]));
12626         if (&obj->base == NULL)
12627                 return ERR_PTR(-ENOENT);
12628
12629         return intel_framebuffer_create(dev, mode_cmd, obj);
12630 }
12631
12632 #ifndef CONFIG_DRM_I915_FBDEV
12633 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12634 {
12635 }
12636 #endif
12637
12638 static const struct drm_mode_config_funcs intel_mode_funcs = {
12639         .fb_create = intel_user_framebuffer_create,
12640         .output_poll_changed = intel_fbdev_output_poll_changed,
12641 };
12642
12643 /* Set up chip specific display functions */
12644 static void intel_init_display(struct drm_device *dev)
12645 {
12646         struct drm_i915_private *dev_priv = dev->dev_private;
12647
12648         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12649                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12650         else if (IS_CHERRYVIEW(dev))
12651                 dev_priv->display.find_dpll = chv_find_best_dpll;
12652         else if (IS_VALLEYVIEW(dev))
12653                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12654         else if (IS_PINEVIEW(dev))
12655                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12656         else
12657                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12658
12659         if (HAS_DDI(dev)) {
12660                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12661                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12662                 dev_priv->display.crtc_compute_clock =
12663                         haswell_crtc_compute_clock;
12664                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12665                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12666                 dev_priv->display.off = ironlake_crtc_off;
12667                 if (INTEL_INFO(dev)->gen >= 9)
12668                         dev_priv->display.update_primary_plane =
12669                                 skylake_update_primary_plane;
12670                 else
12671                         dev_priv->display.update_primary_plane =
12672                                 ironlake_update_primary_plane;
12673         } else if (HAS_PCH_SPLIT(dev)) {
12674                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12675                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12676                 dev_priv->display.crtc_compute_clock =
12677                         ironlake_crtc_compute_clock;
12678                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12679                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12680                 dev_priv->display.off = ironlake_crtc_off;
12681                 dev_priv->display.update_primary_plane =
12682                         ironlake_update_primary_plane;
12683         } else if (IS_VALLEYVIEW(dev)) {
12684                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12685                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12686                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12687                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12688                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12689                 dev_priv->display.off = i9xx_crtc_off;
12690                 dev_priv->display.update_primary_plane =
12691                         i9xx_update_primary_plane;
12692         } else {
12693                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12694                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12695                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12696                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12697                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12698                 dev_priv->display.off = i9xx_crtc_off;
12699                 dev_priv->display.update_primary_plane =
12700                         i9xx_update_primary_plane;
12701         }
12702
12703         /* Returns the core display clock speed */
12704         if (IS_VALLEYVIEW(dev))
12705                 dev_priv->display.get_display_clock_speed =
12706                         valleyview_get_display_clock_speed;
12707         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12708                 dev_priv->display.get_display_clock_speed =
12709                         i945_get_display_clock_speed;
12710         else if (IS_I915G(dev))
12711                 dev_priv->display.get_display_clock_speed =
12712                         i915_get_display_clock_speed;
12713         else if (IS_I945GM(dev) || IS_845G(dev))
12714                 dev_priv->display.get_display_clock_speed =
12715                         i9xx_misc_get_display_clock_speed;
12716         else if (IS_PINEVIEW(dev))
12717                 dev_priv->display.get_display_clock_speed =
12718                         pnv_get_display_clock_speed;
12719         else if (IS_I915GM(dev))
12720                 dev_priv->display.get_display_clock_speed =
12721                         i915gm_get_display_clock_speed;
12722         else if (IS_I865G(dev))
12723                 dev_priv->display.get_display_clock_speed =
12724                         i865_get_display_clock_speed;
12725         else if (IS_I85X(dev))
12726                 dev_priv->display.get_display_clock_speed =
12727                         i855_get_display_clock_speed;
12728         else /* 852, 830 */
12729                 dev_priv->display.get_display_clock_speed =
12730                         i830_get_display_clock_speed;
12731
12732         if (IS_GEN5(dev)) {
12733                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12734         } else if (IS_GEN6(dev)) {
12735                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12736         } else if (IS_IVYBRIDGE(dev)) {
12737                 /* FIXME: detect B0+ stepping and use auto training */
12738                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12739                 dev_priv->display.modeset_global_resources =
12740                         ivb_modeset_global_resources;
12741         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12742                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12743         } else if (IS_VALLEYVIEW(dev)) {
12744                 dev_priv->display.modeset_global_resources =
12745                         valleyview_modeset_global_resources;
12746         }
12747
12748         /* Default just returns -ENODEV to indicate unsupported */
12749         dev_priv->display.queue_flip = intel_default_queue_flip;
12750
12751         switch (INTEL_INFO(dev)->gen) {
12752         case 2:
12753                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12754                 break;
12755
12756         case 3:
12757                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12758                 break;
12759
12760         case 4:
12761         case 5:
12762                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12763                 break;
12764
12765         case 6:
12766                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12767                 break;
12768         case 7:
12769         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12770                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12771                 break;
12772         case 9:
12773                 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12774                 break;
12775         }
12776
12777         intel_panel_init_backlight_funcs(dev);
12778
12779         mutex_init(&dev_priv->pps_mutex);
12780 }
12781
12782 /*
12783  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12784  * resume, or other times.  This quirk makes sure that's the case for
12785  * affected systems.
12786  */
12787 static void quirk_pipea_force(struct drm_device *dev)
12788 {
12789         struct drm_i915_private *dev_priv = dev->dev_private;
12790
12791         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12792         DRM_INFO("applying pipe a force quirk\n");
12793 }
12794
12795 static void quirk_pipeb_force(struct drm_device *dev)
12796 {
12797         struct drm_i915_private *dev_priv = dev->dev_private;
12798
12799         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12800         DRM_INFO("applying pipe b force quirk\n");
12801 }
12802
12803 /*
12804  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12805  */
12806 static void quirk_ssc_force_disable(struct drm_device *dev)
12807 {
12808         struct drm_i915_private *dev_priv = dev->dev_private;
12809         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12810         DRM_INFO("applying lvds SSC disable quirk\n");
12811 }
12812
12813 /*
12814  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12815  * brightness value
12816  */
12817 static void quirk_invert_brightness(struct drm_device *dev)
12818 {
12819         struct drm_i915_private *dev_priv = dev->dev_private;
12820         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12821         DRM_INFO("applying inverted panel brightness quirk\n");
12822 }
12823
12824 /* Some VBT's incorrectly indicate no backlight is present */
12825 static void quirk_backlight_present(struct drm_device *dev)
12826 {
12827         struct drm_i915_private *dev_priv = dev->dev_private;
12828         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12829         DRM_INFO("applying backlight present quirk\n");
12830 }
12831
12832 struct intel_quirk {
12833         int device;
12834         int subsystem_vendor;
12835         int subsystem_device;
12836         void (*hook)(struct drm_device *dev);
12837 };
12838
12839 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12840 struct intel_dmi_quirk {
12841         void (*hook)(struct drm_device *dev);
12842         const struct dmi_system_id (*dmi_id_list)[];
12843 };
12844
12845 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12846 {
12847         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12848         return 1;
12849 }
12850
12851 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12852         {
12853                 .dmi_id_list = &(const struct dmi_system_id[]) {
12854                         {
12855                                 .callback = intel_dmi_reverse_brightness,
12856                                 .ident = "NCR Corporation",
12857                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12858                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12859                                 },
12860                         },
12861                         { }  /* terminating entry */
12862                 },
12863                 .hook = quirk_invert_brightness,
12864         },
12865 };
12866
12867 static struct intel_quirk intel_quirks[] = {
12868         /* HP Mini needs pipe A force quirk (LP: #322104) */
12869         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12870
12871         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12872         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12873
12874         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12875         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12876
12877         /* 830 needs to leave pipe A & dpll A up */
12878         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12879
12880         /* 830 needs to leave pipe B & dpll B up */
12881         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12882
12883         /* Lenovo U160 cannot use SSC on LVDS */
12884         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12885
12886         /* Sony Vaio Y cannot use SSC on LVDS */
12887         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12888
12889         /* Acer Aspire 5734Z must invert backlight brightness */
12890         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12891
12892         /* Acer/eMachines G725 */
12893         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12894
12895         /* Acer/eMachines e725 */
12896         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12897
12898         /* Acer/Packard Bell NCL20 */
12899         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12900
12901         /* Acer Aspire 4736Z */
12902         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12903
12904         /* Acer Aspire 5336 */
12905         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12906
12907         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12908         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12909
12910         /* Acer C720 Chromebook (Core i3 4005U) */
12911         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12912
12913         /* Apple Macbook 2,1 (Core 2 T7400) */
12914         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
12915
12916         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12917         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12918
12919         /* HP Chromebook 14 (Celeron 2955U) */
12920         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12921 };
12922
12923 static void intel_init_quirks(struct drm_device *dev)
12924 {
12925         struct pci_dev *d = dev->pdev;
12926         int i;
12927
12928         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12929                 struct intel_quirk *q = &intel_quirks[i];
12930
12931                 if (d->device == q->device &&
12932                     (d->subsystem_vendor == q->subsystem_vendor ||
12933                      q->subsystem_vendor == PCI_ANY_ID) &&
12934                     (d->subsystem_device == q->subsystem_device ||
12935                      q->subsystem_device == PCI_ANY_ID))
12936                         q->hook(dev);
12937         }
12938         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12939                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12940                         intel_dmi_quirks[i].hook(dev);
12941         }
12942 }
12943
12944 /* Disable the VGA plane that we never use */
12945 static void i915_disable_vga(struct drm_device *dev)
12946 {
12947         struct drm_i915_private *dev_priv = dev->dev_private;
12948         u8 sr1;
12949         u32 vga_reg = i915_vgacntrl_reg(dev);
12950
12951         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12952         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12953         outb(SR01, VGA_SR_INDEX);
12954         sr1 = inb(VGA_SR_DATA);
12955         outb(sr1 | 1<<5, VGA_SR_DATA);
12956         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12957         udelay(300);
12958
12959         /*
12960          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12961          * from S3 without preserving (some of?) the other bits.
12962          */
12963         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12964         POSTING_READ(vga_reg);
12965 }
12966
12967 void intel_modeset_init_hw(struct drm_device *dev)
12968 {
12969         intel_prepare_ddi(dev);
12970
12971         if (IS_VALLEYVIEW(dev))
12972                 vlv_update_cdclk(dev);
12973
12974         intel_init_clock_gating(dev);
12975
12976         intel_enable_gt_powersave(dev);
12977 }
12978
12979 void intel_modeset_init(struct drm_device *dev)
12980 {
12981         struct drm_i915_private *dev_priv = dev->dev_private;
12982         int sprite, ret;
12983         enum pipe pipe;
12984         struct intel_crtc *crtc;
12985
12986         drm_mode_config_init(dev);
12987
12988         dev->mode_config.min_width = 0;
12989         dev->mode_config.min_height = 0;
12990
12991         dev->mode_config.preferred_depth = 24;
12992         dev->mode_config.prefer_shadow = 1;
12993
12994         dev->mode_config.funcs = &intel_mode_funcs;
12995
12996         intel_init_quirks(dev);
12997
12998         intel_init_pm(dev);
12999
13000         if (INTEL_INFO(dev)->num_pipes == 0)
13001                 return;
13002
13003         intel_init_display(dev);
13004         intel_init_audio(dev);
13005
13006         if (IS_GEN2(dev)) {
13007                 dev->mode_config.max_width = 2048;
13008                 dev->mode_config.max_height = 2048;
13009         } else if (IS_GEN3(dev)) {
13010                 dev->mode_config.max_width = 4096;
13011                 dev->mode_config.max_height = 4096;
13012         } else {
13013                 dev->mode_config.max_width = 8192;
13014                 dev->mode_config.max_height = 8192;
13015         }
13016
13017         if (IS_845G(dev) || IS_I865G(dev)) {
13018                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13019                 dev->mode_config.cursor_height = 1023;
13020         } else if (IS_GEN2(dev)) {
13021                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13022                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13023         } else {
13024                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13025                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13026         }
13027
13028         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13029
13030         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13031                       INTEL_INFO(dev)->num_pipes,
13032                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13033
13034         for_each_pipe(dev_priv, pipe) {
13035                 intel_crtc_init(dev, pipe);
13036                 for_each_sprite(pipe, sprite) {
13037                         ret = intel_plane_init(dev, pipe, sprite);
13038                         if (ret)
13039                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13040                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13041                 }
13042         }
13043
13044         intel_init_dpio(dev);
13045
13046         intel_shared_dpll_init(dev);
13047
13048         /* save the BIOS value before clobbering it */
13049         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13050         /* Just disable it once at startup */
13051         i915_disable_vga(dev);
13052         intel_setup_outputs(dev);
13053
13054         /* Just in case the BIOS is doing something questionable. */
13055         intel_fbc_disable(dev);
13056
13057         drm_modeset_lock_all(dev);
13058         intel_modeset_setup_hw_state(dev, false);
13059         drm_modeset_unlock_all(dev);
13060
13061         for_each_intel_crtc(dev, crtc) {
13062                 if (!crtc->active)
13063                         continue;
13064
13065                 /*
13066                  * Note that reserving the BIOS fb up front prevents us
13067                  * from stuffing other stolen allocations like the ring
13068                  * on top.  This prevents some ugliness at boot time, and
13069                  * can even allow for smooth boot transitions if the BIOS
13070                  * fb is large enough for the active pipe configuration.
13071                  */
13072                 if (dev_priv->display.get_plane_config) {
13073                         dev_priv->display.get_plane_config(crtc,
13074                                                            &crtc->plane_config);
13075                         /*
13076                          * If the fb is shared between multiple heads, we'll
13077                          * just get the first one.
13078                          */
13079                         intel_find_plane_obj(crtc, &crtc->plane_config);
13080                 }
13081         }
13082 }
13083
13084 static void intel_enable_pipe_a(struct drm_device *dev)
13085 {
13086         struct intel_connector *connector;
13087         struct drm_connector *crt = NULL;
13088         struct intel_load_detect_pipe load_detect_temp;
13089         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13090
13091         /* We can't just switch on the pipe A, we need to set things up with a
13092          * proper mode and output configuration. As a gross hack, enable pipe A
13093          * by enabling the load detect pipe once. */
13094         list_for_each_entry(connector,
13095                             &dev->mode_config.connector_list,
13096                             base.head) {
13097                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13098                         crt = &connector->base;
13099                         break;
13100                 }
13101         }
13102
13103         if (!crt)
13104                 return;
13105
13106         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13107                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13108 }
13109
13110 static bool
13111 intel_check_plane_mapping(struct intel_crtc *crtc)
13112 {
13113         struct drm_device *dev = crtc->base.dev;
13114         struct drm_i915_private *dev_priv = dev->dev_private;
13115         u32 reg, val;
13116
13117         if (INTEL_INFO(dev)->num_pipes == 1)
13118                 return true;
13119
13120         reg = DSPCNTR(!crtc->plane);
13121         val = I915_READ(reg);
13122
13123         if ((val & DISPLAY_PLANE_ENABLE) &&
13124             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13125                 return false;
13126
13127         return true;
13128 }
13129
13130 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13131 {
13132         struct drm_device *dev = crtc->base.dev;
13133         struct drm_i915_private *dev_priv = dev->dev_private;
13134         u32 reg;
13135
13136         /* Clear any frame start delays used for debugging left by the BIOS */
13137         reg = PIPECONF(crtc->config.cpu_transcoder);
13138         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13139
13140         /* restore vblank interrupts to correct state */
13141         if (crtc->active) {
13142                 update_scanline_offset(crtc);
13143                 drm_vblank_on(dev, crtc->pipe);
13144         } else
13145                 drm_vblank_off(dev, crtc->pipe);
13146
13147         /* We need to sanitize the plane -> pipe mapping first because this will
13148          * disable the crtc (and hence change the state) if it is wrong. Note
13149          * that gen4+ has a fixed plane -> pipe mapping.  */
13150         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13151                 struct intel_connector *connector;
13152                 bool plane;
13153
13154                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13155                               crtc->base.base.id);
13156
13157                 /* Pipe has the wrong plane attached and the plane is active.
13158                  * Temporarily change the plane mapping and disable everything
13159                  * ...  */
13160                 plane = crtc->plane;
13161                 crtc->plane = !plane;
13162                 crtc->primary_enabled = true;
13163                 dev_priv->display.crtc_disable(&crtc->base);
13164                 crtc->plane = plane;
13165
13166                 /* ... and break all links. */
13167                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13168                                     base.head) {
13169                         if (connector->encoder->base.crtc != &crtc->base)
13170                                 continue;
13171
13172                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13173                         connector->base.encoder = NULL;
13174                 }
13175                 /* multiple connectors may have the same encoder:
13176                  *  handle them and break crtc link separately */
13177                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13178                                     base.head)
13179                         if (connector->encoder->base.crtc == &crtc->base) {
13180                                 connector->encoder->base.crtc = NULL;
13181                                 connector->encoder->connectors_active = false;
13182                         }
13183
13184                 WARN_ON(crtc->active);
13185                 crtc->base.enabled = false;
13186         }
13187
13188         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13189             crtc->pipe == PIPE_A && !crtc->active) {
13190                 /* BIOS forgot to enable pipe A, this mostly happens after
13191                  * resume. Force-enable the pipe to fix this, the update_dpms
13192                  * call below we restore the pipe to the right state, but leave
13193                  * the required bits on. */
13194                 intel_enable_pipe_a(dev);
13195         }
13196
13197         /* Adjust the state of the output pipe according to whether we
13198          * have active connectors/encoders. */
13199         intel_crtc_update_dpms(&crtc->base);
13200
13201         if (crtc->active != crtc->base.enabled) {
13202                 struct intel_encoder *encoder;
13203
13204                 /* This can happen either due to bugs in the get_hw_state
13205                  * functions or because the pipe is force-enabled due to the
13206                  * pipe A quirk. */
13207                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13208                               crtc->base.base.id,
13209                               crtc->base.enabled ? "enabled" : "disabled",
13210                               crtc->active ? "enabled" : "disabled");
13211
13212                 crtc->base.enabled = crtc->active;
13213
13214                 /* Because we only establish the connector -> encoder ->
13215                  * crtc links if something is active, this means the
13216                  * crtc is now deactivated. Break the links. connector
13217                  * -> encoder links are only establish when things are
13218                  *  actually up, hence no need to break them. */
13219                 WARN_ON(crtc->active);
13220
13221                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13222                         WARN_ON(encoder->connectors_active);
13223                         encoder->base.crtc = NULL;
13224                 }
13225         }
13226
13227         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13228                 /*
13229                  * We start out with underrun reporting disabled to avoid races.
13230                  * For correct bookkeeping mark this on active crtcs.
13231                  *
13232                  * Also on gmch platforms we dont have any hardware bits to
13233                  * disable the underrun reporting. Which means we need to start
13234                  * out with underrun reporting disabled also on inactive pipes,
13235                  * since otherwise we'll complain about the garbage we read when
13236                  * e.g. coming up after runtime pm.
13237                  *
13238                  * No protection against concurrent access is required - at
13239                  * worst a fifo underrun happens which also sets this to false.
13240                  */
13241                 crtc->cpu_fifo_underrun_disabled = true;
13242                 crtc->pch_fifo_underrun_disabled = true;
13243         }
13244 }
13245
13246 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13247 {
13248         struct intel_connector *connector;
13249         struct drm_device *dev = encoder->base.dev;
13250
13251         /* We need to check both for a crtc link (meaning that the
13252          * encoder is active and trying to read from a pipe) and the
13253          * pipe itself being active. */
13254         bool has_active_crtc = encoder->base.crtc &&
13255                 to_intel_crtc(encoder->base.crtc)->active;
13256
13257         if (encoder->connectors_active && !has_active_crtc) {
13258                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13259                               encoder->base.base.id,
13260                               encoder->base.name);
13261
13262                 /* Connector is active, but has no active pipe. This is
13263                  * fallout from our resume register restoring. Disable
13264                  * the encoder manually again. */
13265                 if (encoder->base.crtc) {
13266                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13267                                       encoder->base.base.id,
13268                                       encoder->base.name);
13269                         encoder->disable(encoder);
13270                         if (encoder->post_disable)
13271                                 encoder->post_disable(encoder);
13272                 }
13273                 encoder->base.crtc = NULL;
13274                 encoder->connectors_active = false;
13275
13276                 /* Inconsistent output/port/pipe state happens presumably due to
13277                  * a bug in one of the get_hw_state functions. Or someplace else
13278                  * in our code, like the register restore mess on resume. Clamp
13279                  * things to off as a safer default. */
13280                 list_for_each_entry(connector,
13281                                     &dev->mode_config.connector_list,
13282                                     base.head) {
13283                         if (connector->encoder != encoder)
13284                                 continue;
13285                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13286                         connector->base.encoder = NULL;
13287                 }
13288         }
13289         /* Enabled encoders without active connectors will be fixed in
13290          * the crtc fixup. */
13291 }
13292
13293 void i915_redisable_vga_power_on(struct drm_device *dev)
13294 {
13295         struct drm_i915_private *dev_priv = dev->dev_private;
13296         u32 vga_reg = i915_vgacntrl_reg(dev);
13297
13298         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13299                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13300                 i915_disable_vga(dev);
13301         }
13302 }
13303
13304 void i915_redisable_vga(struct drm_device *dev)
13305 {
13306         struct drm_i915_private *dev_priv = dev->dev_private;
13307
13308         /* This function can be called both from intel_modeset_setup_hw_state or
13309          * at a very early point in our resume sequence, where the power well
13310          * structures are not yet restored. Since this function is at a very
13311          * paranoid "someone might have enabled VGA while we were not looking"
13312          * level, just check if the power well is enabled instead of trying to
13313          * follow the "don't touch the power well if we don't need it" policy
13314          * the rest of the driver uses. */
13315         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13316                 return;
13317
13318         i915_redisable_vga_power_on(dev);
13319 }
13320
13321 static bool primary_get_hw_state(struct intel_crtc *crtc)
13322 {
13323         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13324
13325         if (!crtc->active)
13326                 return false;
13327
13328         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13329 }
13330
13331 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13332 {
13333         struct drm_i915_private *dev_priv = dev->dev_private;
13334         enum pipe pipe;
13335         struct intel_crtc *crtc;
13336         struct intel_encoder *encoder;
13337         struct intel_connector *connector;
13338         int i;
13339
13340         for_each_intel_crtc(dev, crtc) {
13341                 memset(&crtc->config, 0, sizeof(crtc->config));
13342
13343                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13344
13345                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13346                                                                  &crtc->config);
13347
13348                 crtc->base.enabled = crtc->active;
13349                 crtc->primary_enabled = primary_get_hw_state(crtc);
13350
13351                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13352                               crtc->base.base.id,
13353                               crtc->active ? "enabled" : "disabled");
13354         }
13355
13356         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13357                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13358
13359                 pll->on = pll->get_hw_state(dev_priv, pll,
13360                                             &pll->config.hw_state);
13361                 pll->active = 0;
13362                 pll->config.crtc_mask = 0;
13363                 for_each_intel_crtc(dev, crtc) {
13364                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13365                                 pll->active++;
13366                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13367                         }
13368                 }
13369
13370                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13371                               pll->name, pll->config.crtc_mask, pll->on);
13372
13373                 if (pll->config.crtc_mask)
13374                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13375         }
13376
13377         for_each_intel_encoder(dev, encoder) {
13378                 pipe = 0;
13379
13380                 if (encoder->get_hw_state(encoder, &pipe)) {
13381                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13382                         encoder->base.crtc = &crtc->base;
13383                         encoder->get_config(encoder, &crtc->config);
13384                 } else {
13385                         encoder->base.crtc = NULL;
13386                 }
13387
13388                 encoder->connectors_active = false;
13389                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13390                               encoder->base.base.id,
13391                               encoder->base.name,
13392                               encoder->base.crtc ? "enabled" : "disabled",
13393                               pipe_name(pipe));
13394         }
13395
13396         list_for_each_entry(connector, &dev->mode_config.connector_list,
13397                             base.head) {
13398                 if (connector->get_hw_state(connector)) {
13399                         connector->base.dpms = DRM_MODE_DPMS_ON;
13400                         connector->encoder->connectors_active = true;
13401                         connector->base.encoder = &connector->encoder->base;
13402                 } else {
13403                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13404                         connector->base.encoder = NULL;
13405                 }
13406                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13407                               connector->base.base.id,
13408                               connector->base.name,
13409                               connector->base.encoder ? "enabled" : "disabled");
13410         }
13411 }
13412
13413 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13414  * and i915 state tracking structures. */
13415 void intel_modeset_setup_hw_state(struct drm_device *dev,
13416                                   bool force_restore)
13417 {
13418         struct drm_i915_private *dev_priv = dev->dev_private;
13419         enum pipe pipe;
13420         struct intel_crtc *crtc;
13421         struct intel_encoder *encoder;
13422         int i;
13423
13424         intel_modeset_readout_hw_state(dev);
13425
13426         /*
13427          * Now that we have the config, copy it to each CRTC struct
13428          * Note that this could go away if we move to using crtc_config
13429          * checking everywhere.
13430          */
13431         for_each_intel_crtc(dev, crtc) {
13432                 if (crtc->active && i915.fastboot) {
13433                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13434                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13435                                       crtc->base.base.id);
13436                         drm_mode_debug_printmodeline(&crtc->base.mode);
13437                 }
13438         }
13439
13440         /* HW state is read out, now we need to sanitize this mess. */
13441         for_each_intel_encoder(dev, encoder) {
13442                 intel_sanitize_encoder(encoder);
13443         }
13444
13445         for_each_pipe(dev_priv, pipe) {
13446                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13447                 intel_sanitize_crtc(crtc);
13448                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13449         }
13450
13451         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13452                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13453
13454                 if (!pll->on || pll->active)
13455                         continue;
13456
13457                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13458
13459                 pll->disable(dev_priv, pll);
13460                 pll->on = false;
13461         }
13462
13463         if (IS_GEN9(dev))
13464                 skl_wm_get_hw_state(dev);
13465         else if (HAS_PCH_SPLIT(dev))
13466                 ilk_wm_get_hw_state(dev);
13467
13468         if (force_restore) {
13469                 i915_redisable_vga(dev);
13470
13471                 /*
13472                  * We need to use raw interfaces for restoring state to avoid
13473                  * checking (bogus) intermediate states.
13474                  */
13475                 for_each_pipe(dev_priv, pipe) {
13476                         struct drm_crtc *crtc =
13477                                 dev_priv->pipe_to_crtc_mapping[pipe];
13478
13479                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13480                                        crtc->primary->fb);
13481                 }
13482         } else {
13483                 intel_modeset_update_staged_output_state(dev);
13484         }
13485
13486         intel_modeset_check_state(dev);
13487 }
13488
13489 void intel_modeset_gem_init(struct drm_device *dev)
13490 {
13491         struct drm_i915_private *dev_priv = dev->dev_private;
13492         struct drm_crtc *c;
13493         struct drm_i915_gem_object *obj;
13494
13495         mutex_lock(&dev->struct_mutex);
13496         intel_init_gt_powersave(dev);
13497         mutex_unlock(&dev->struct_mutex);
13498
13499         /*
13500          * There may be no VBT; and if the BIOS enabled SSC we can
13501          * just keep using it to avoid unnecessary flicker.  Whereas if the
13502          * BIOS isn't using it, don't assume it will work even if the VBT
13503          * indicates as much.
13504          */
13505         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13506                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13507                                                 DREF_SSC1_ENABLE);
13508
13509         intel_modeset_init_hw(dev);
13510
13511         intel_setup_overlay(dev);
13512
13513         /*
13514          * Make sure any fbs we allocated at startup are properly
13515          * pinned & fenced.  When we do the allocation it's too early
13516          * for this.
13517          */
13518         mutex_lock(&dev->struct_mutex);
13519         for_each_crtc(dev, c) {
13520                 obj = intel_fb_obj(c->primary->fb);
13521                 if (obj == NULL)
13522                         continue;
13523
13524                 if (intel_pin_and_fence_fb_obj(c->primary,
13525                                                c->primary->fb,
13526                                                NULL)) {
13527                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13528                                   to_intel_crtc(c)->pipe);
13529                         drm_framebuffer_unreference(c->primary->fb);
13530                         c->primary->fb = NULL;
13531                 }
13532         }
13533         mutex_unlock(&dev->struct_mutex);
13534
13535         intel_backlight_register(dev);
13536 }
13537
13538 void intel_connector_unregister(struct intel_connector *intel_connector)
13539 {
13540         struct drm_connector *connector = &intel_connector->base;
13541
13542         intel_panel_destroy_backlight(connector);
13543         drm_connector_unregister(connector);
13544 }
13545
13546 void intel_modeset_cleanup(struct drm_device *dev)
13547 {
13548         struct drm_i915_private *dev_priv = dev->dev_private;
13549         struct drm_connector *connector;
13550
13551         intel_disable_gt_powersave(dev);
13552
13553         intel_backlight_unregister(dev);
13554
13555         /*
13556          * Interrupts and polling as the first thing to avoid creating havoc.
13557          * Too much stuff here (turning of connectors, ...) would
13558          * experience fancy races otherwise.
13559          */
13560         intel_irq_uninstall(dev_priv);
13561
13562         /*
13563          * Due to the hpd irq storm handling the hotplug work can re-arm the
13564          * poll handlers. Hence disable polling after hpd handling is shut down.
13565          */
13566         drm_kms_helper_poll_fini(dev);
13567
13568         mutex_lock(&dev->struct_mutex);
13569
13570         intel_unregister_dsm_handler();
13571
13572         intel_fbc_disable(dev);
13573
13574         ironlake_teardown_rc6(dev);
13575
13576         mutex_unlock(&dev->struct_mutex);
13577
13578         /* flush any delayed tasks or pending work */
13579         flush_scheduled_work();
13580
13581         /* destroy the backlight and sysfs files before encoders/connectors */
13582         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13583                 struct intel_connector *intel_connector;
13584
13585                 intel_connector = to_intel_connector(connector);
13586                 intel_connector->unregister(intel_connector);
13587         }
13588
13589         drm_mode_config_cleanup(dev);
13590
13591         intel_cleanup_overlay(dev);
13592
13593         mutex_lock(&dev->struct_mutex);
13594         intel_cleanup_gt_powersave(dev);
13595         mutex_unlock(&dev->struct_mutex);
13596 }
13597
13598 /*
13599  * Return which encoder is currently attached for connector.
13600  */
13601 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13602 {
13603         return &intel_attached_encoder(connector)->base;
13604 }
13605
13606 void intel_connector_attach_encoder(struct intel_connector *connector,
13607                                     struct intel_encoder *encoder)
13608 {
13609         connector->encoder = encoder;
13610         drm_mode_connector_attach_encoder(&connector->base,
13611                                           &encoder->base);
13612 }
13613
13614 /*
13615  * set vga decode state - true == enable VGA decode
13616  */
13617 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13618 {
13619         struct drm_i915_private *dev_priv = dev->dev_private;
13620         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13621         u16 gmch_ctrl;
13622
13623         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13624                 DRM_ERROR("failed to read control word\n");
13625                 return -EIO;
13626         }
13627
13628         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13629                 return 0;
13630
13631         if (state)
13632                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13633         else
13634                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13635
13636         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13637                 DRM_ERROR("failed to write control word\n");
13638                 return -EIO;
13639         }
13640
13641         return 0;
13642 }
13643
13644 struct intel_display_error_state {
13645
13646         u32 power_well_driver;
13647
13648         int num_transcoders;
13649
13650         struct intel_cursor_error_state {
13651                 u32 control;
13652                 u32 position;
13653                 u32 base;
13654                 u32 size;
13655         } cursor[I915_MAX_PIPES];
13656
13657         struct intel_pipe_error_state {
13658                 bool power_domain_on;
13659                 u32 source;
13660                 u32 stat;
13661         } pipe[I915_MAX_PIPES];
13662
13663         struct intel_plane_error_state {
13664                 u32 control;
13665                 u32 stride;
13666                 u32 size;
13667                 u32 pos;
13668                 u32 addr;
13669                 u32 surface;
13670                 u32 tile_offset;
13671         } plane[I915_MAX_PIPES];
13672
13673         struct intel_transcoder_error_state {
13674                 bool power_domain_on;
13675                 enum transcoder cpu_transcoder;
13676
13677                 u32 conf;
13678
13679                 u32 htotal;
13680                 u32 hblank;
13681                 u32 hsync;
13682                 u32 vtotal;
13683                 u32 vblank;
13684                 u32 vsync;
13685         } transcoder[4];
13686 };
13687
13688 struct intel_display_error_state *
13689 intel_display_capture_error_state(struct drm_device *dev)
13690 {
13691         struct drm_i915_private *dev_priv = dev->dev_private;
13692         struct intel_display_error_state *error;
13693         int transcoders[] = {
13694                 TRANSCODER_A,
13695                 TRANSCODER_B,
13696                 TRANSCODER_C,
13697                 TRANSCODER_EDP,
13698         };
13699         int i;
13700
13701         if (INTEL_INFO(dev)->num_pipes == 0)
13702                 return NULL;
13703
13704         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13705         if (error == NULL)
13706                 return NULL;
13707
13708         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13709                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13710
13711         for_each_pipe(dev_priv, i) {
13712                 error->pipe[i].power_domain_on =
13713                         __intel_display_power_is_enabled(dev_priv,
13714                                                          POWER_DOMAIN_PIPE(i));
13715                 if (!error->pipe[i].power_domain_on)
13716                         continue;
13717
13718                 error->cursor[i].control = I915_READ(CURCNTR(i));
13719                 error->cursor[i].position = I915_READ(CURPOS(i));
13720                 error->cursor[i].base = I915_READ(CURBASE(i));
13721
13722                 error->plane[i].control = I915_READ(DSPCNTR(i));
13723                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13724                 if (INTEL_INFO(dev)->gen <= 3) {
13725                         error->plane[i].size = I915_READ(DSPSIZE(i));
13726                         error->plane[i].pos = I915_READ(DSPPOS(i));
13727                 }
13728                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13729                         error->plane[i].addr = I915_READ(DSPADDR(i));
13730                 if (INTEL_INFO(dev)->gen >= 4) {
13731                         error->plane[i].surface = I915_READ(DSPSURF(i));
13732                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13733                 }
13734
13735                 error->pipe[i].source = I915_READ(PIPESRC(i));
13736
13737                 if (HAS_GMCH_DISPLAY(dev))
13738                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13739         }
13740
13741         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13742         if (HAS_DDI(dev_priv->dev))
13743                 error->num_transcoders++; /* Account for eDP. */
13744
13745         for (i = 0; i < error->num_transcoders; i++) {
13746                 enum transcoder cpu_transcoder = transcoders[i];
13747
13748                 error->transcoder[i].power_domain_on =
13749                         __intel_display_power_is_enabled(dev_priv,
13750                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13751                 if (!error->transcoder[i].power_domain_on)
13752                         continue;
13753
13754                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13755
13756                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13757                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13758                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13759                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13760                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13761                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13762                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13763         }
13764
13765         return error;
13766 }
13767
13768 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13769
13770 void
13771 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13772                                 struct drm_device *dev,
13773                                 struct intel_display_error_state *error)
13774 {
13775         struct drm_i915_private *dev_priv = dev->dev_private;
13776         int i;
13777
13778         if (!error)
13779                 return;
13780
13781         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13782         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13783                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13784                            error->power_well_driver);
13785         for_each_pipe(dev_priv, i) {
13786                 err_printf(m, "Pipe [%d]:\n", i);
13787                 err_printf(m, "  Power: %s\n",
13788                            error->pipe[i].power_domain_on ? "on" : "off");
13789                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13790                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13791
13792                 err_printf(m, "Plane [%d]:\n", i);
13793                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13794                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13795                 if (INTEL_INFO(dev)->gen <= 3) {
13796                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13797                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13798                 }
13799                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13800                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13801                 if (INTEL_INFO(dev)->gen >= 4) {
13802                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13803                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13804                 }
13805
13806                 err_printf(m, "Cursor [%d]:\n", i);
13807                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13808                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13809                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13810         }
13811
13812         for (i = 0; i < error->num_transcoders; i++) {
13813                 err_printf(m, "CPU transcoder: %c\n",
13814                            transcoder_name(error->transcoder[i].cpu_transcoder));
13815                 err_printf(m, "  Power: %s\n",
13816                            error->transcoder[i].power_domain_on ? "on" : "off");
13817                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13818                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13819                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13820                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13821                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13822                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13823                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13824         }
13825 }
13826
13827 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13828 {
13829         struct intel_crtc *crtc;
13830
13831         for_each_intel_crtc(dev, crtc) {
13832                 struct intel_unpin_work *work;
13833
13834                 spin_lock_irq(&dev->event_lock);
13835
13836                 work = crtc->unpin_work;
13837
13838                 if (work && work->event &&
13839                     work->event->base.file_priv == file) {
13840                         kfree(work->event);
13841                         work->event = NULL;
13842                 }
13843
13844                 spin_unlock_irq(&dev->event_lock);
13845         }
13846 }