drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int clock;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { 162000,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { 270000,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { 162000,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { 270000,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { 162000,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { 270000,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int default_rates[] = { 162000, 270000, 540000 };
  99
 100 /**
 101  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 102  * @intel_dp: DP struct
 103  *
 104  * If a CPU or PCH DP output is attached to an eDP panel, this function
 105  * will return true, and false otherwise.
 106  */
 107 static bool is_edp(struct intel_dp *intel_dp)
 108 {
 109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 110
 111         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 112 }
 113
 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 115 {
 116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 117
 118         return intel_dig_port->base.base.dev;
 119 }
 120
 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 122 {
 123         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 124 }
 125
 126 static void intel_dp_link_down(struct intel_dp *intel_dp);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 130 static void vlv_steal_power_sequencer(struct drm_device *dev,
 131                                       enum pipe pipe);
 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 133
 134 static int
 135 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 136 {
 137         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 138
 139         switch (max_link_bw) {
 140         case DP_LINK_BW_1_62:
 141         case DP_LINK_BW_2_7:
 142         case DP_LINK_BW_5_4:
 143                 break;
 144         default:
 145                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 146                      max_link_bw);
 147                 max_link_bw = DP_LINK_BW_1_62;
 148                 break;
 149         }
 150         return max_link_bw;
 151 }
 152
 153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 154 {
 155         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 156         u8 source_max, sink_max;
 157
 158         source_max = intel_dig_port->max_lanes;
 159         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 160
 161         return min(source_max, sink_max);
 162 }
 163
 164 /*
 165  * The units on the numbers in the next two are... bizarre.  Examples will
 166  * make it clearer; this one parallels an example in the eDP spec.
 167  *
 168  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 169  *
 170  *     270000 * 1 * 8 / 10 == 216000
 171  *
 172  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 173  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 174  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 175  * 119000.  At 18bpp that's 2142000 kilobits per second.
 176  *
 177  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 178  * get the result in decakilobits instead of kilobits.
 179  */
 180
 181 static int
 182 intel_dp_link_required(int pixel_clock, int bpp)
 183 {
 184         return (pixel_clock * bpp + 9) / 10;
 185 }
 186
 187 static int
 188 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 189 {
 190         return (max_link_clock * max_lanes * 8) / 10;
 191 }
 192
 193 static enum drm_mode_status
 194 intel_dp_mode_valid(struct drm_connector *connector,
 195                     struct drm_display_mode *mode)
 196 {
 197         struct intel_dp *intel_dp = intel_attached_dp(connector);
 198         struct intel_connector *intel_connector = to_intel_connector(connector);
 199         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 200         int target_clock = mode->clock;
 201         int max_rate, mode_rate, max_lanes, max_link_clock;
 202         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 203
 204         if (is_edp(intel_dp) && fixed_mode) {
 205                 if (mode->hdisplay > fixed_mode->hdisplay)
 206                         return MODE_PANEL;
 207
 208                 if (mode->vdisplay > fixed_mode->vdisplay)
 209                         return MODE_PANEL;
 210
 211                 target_clock = fixed_mode->clock;
 212         }
 213
 214         max_link_clock = intel_dp_max_link_rate(intel_dp);
 215         max_lanes = intel_dp_max_lane_count(intel_dp);
 216
 217         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 218         mode_rate = intel_dp_link_required(target_clock, 18);
 219
 220         if (mode_rate > max_rate || target_clock > max_dotclk)
 221                 return MODE_CLOCK_HIGH;
 222
 223         if (mode->clock < 10000)
 224                 return MODE_CLOCK_LOW;
 225
 226         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 227                 return MODE_H_ILLEGAL;
 228
 229         return MODE_OK;
 230 }
 231
 232 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 233 {
 234         int     i;
 235         uint32_t v = 0;
 236
 237         if (src_bytes > 4)
 238                 src_bytes = 4;
 239         for (i = 0; i < src_bytes; i++)
 240                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 241         return v;
 242 }
 243
 244 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 245 {
 246         int i;
 247         if (dst_bytes > 4)
 248                 dst_bytes = 4;
 249         for (i = 0; i < dst_bytes; i++)
 250                 dst[i] = src >> ((3-i) * 8);
 251 }
 252
 253 static void
 254 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 255                                     struct intel_dp *intel_dp);
 256 static void
 257 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 258                                               struct intel_dp *intel_dp);
 259
 260 static void pps_lock(struct intel_dp *intel_dp)
 261 {
 262         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 263         struct intel_encoder *encoder = &intel_dig_port->base;
 264         struct drm_device *dev = encoder->base.dev;
 265         struct drm_i915_private *dev_priv = to_i915(dev);
 266         enum intel_display_power_domain power_domain;
 267
 268         /*
 269          * See vlv_power_sequencer_reset() why we need
 270          * a power domain reference here.
 271          */
 272         power_domain = intel_display_port_aux_power_domain(encoder);
 273         intel_display_power_get(dev_priv, power_domain);
 274
 275         mutex_lock(&dev_priv->pps_mutex);
 276 }
 277
 278 static void pps_unlock(struct intel_dp *intel_dp)
 279 {
 280         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 281         struct intel_encoder *encoder = &intel_dig_port->base;
 282         struct drm_device *dev = encoder->base.dev;
 283         struct drm_i915_private *dev_priv = to_i915(dev);
 284         enum intel_display_power_domain power_domain;
 285
 286         mutex_unlock(&dev_priv->pps_mutex);
 287
 288         power_domain = intel_display_port_aux_power_domain(encoder);
 289         intel_display_power_put(dev_priv, power_domain);
 290 }
 291
 292 static void
 293 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 294 {
 295         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 296         struct drm_device *dev = intel_dig_port->base.base.dev;
 297         struct drm_i915_private *dev_priv = to_i915(dev);
 298         enum pipe pipe = intel_dp->pps_pipe;
 299         bool pll_enabled, release_cl_override = false;
 300         enum dpio_phy phy = DPIO_PHY(pipe);
 301         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 302         uint32_t DP;
 303
 304         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 305                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 306                  pipe_name(pipe), port_name(intel_dig_port->port)))
 307                 return;
 308
 309         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 310                       pipe_name(pipe), port_name(intel_dig_port->port));
 311
 312         /* Preserve the BIOS-computed detected bit. This is
 313          * supposed to be read-only.
 314          */
 315         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 316         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 317         DP |= DP_PORT_WIDTH(1);
 318         DP |= DP_LINK_TRAIN_PAT_1;
 319
 320         if (IS_CHERRYVIEW(dev))
 321                 DP |= DP_PIPE_SELECT_CHV(pipe);
 322         else if (pipe == PIPE_B)
 323                 DP |= DP_PIPEB_SELECT;
 324
 325         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 326
 327         /*
 328          * The DPLL for the pipe must be enabled for this to work.
 329          * So enable temporarily it if it's not already enabled.
 330          */
 331         if (!pll_enabled) {
 332                 release_cl_override = IS_CHERRYVIEW(dev) &&
 333                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 334
 335                 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 336                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 337                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 338                                   pipe_name(pipe));
 339                         return;
 340                 }
 341         }
 342
 343         /*
 344          * Similar magic as in intel_dp_enable_port().
 345          * We _must_ do this port enable + disable trick
 346          * to make this power seqeuencer lock onto the port.
 347          * Otherwise even VDD force bit won't work.
 348          */
 349         I915_WRITE(intel_dp->output_reg, DP);
 350         POSTING_READ(intel_dp->output_reg);
 351
 352         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 353         POSTING_READ(intel_dp->output_reg);
 354
 355         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 356         POSTING_READ(intel_dp->output_reg);
 357
 358         if (!pll_enabled) {
 359                 vlv_force_pll_off(dev, pipe);
 360
 361                 if (release_cl_override)
 362                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 363         }
 364 }
 365
 366 static enum pipe
 367 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 368 {
 369         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 370         struct drm_device *dev = intel_dig_port->base.base.dev;
 371         struct drm_i915_private *dev_priv = to_i915(dev);
 372         struct intel_encoder *encoder;
 373         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 374         enum pipe pipe;
 375
 376         lockdep_assert_held(&dev_priv->pps_mutex);
 377
 378         /* We should never land here with regular DP ports */
 379         WARN_ON(!is_edp(intel_dp));
 380
 381         if (intel_dp->pps_pipe != INVALID_PIPE)
 382                 return intel_dp->pps_pipe;
 383
 384         /*
 385          * We don't have power sequencer currently.
 386          * Pick one that's not used by other ports.
 387          */
 388         for_each_intel_encoder(dev, encoder) {
 389                 struct intel_dp *tmp;
 390
 391                 if (encoder->type != INTEL_OUTPUT_EDP)
 392                         continue;
 393
 394                 tmp = enc_to_intel_dp(&encoder->base);
 395
 396                 if (tmp->pps_pipe != INVALID_PIPE)
 397                         pipes &= ~(1 << tmp->pps_pipe);
 398         }
 399
 400         /*
 401          * Didn't find one. This should not happen since there
 402          * are two power sequencers and up to two eDP ports.
 403          */
 404         if (WARN_ON(pipes == 0))
 405                 pipe = PIPE_A;
 406         else
 407                 pipe = ffs(pipes) - 1;
 408
 409         vlv_steal_power_sequencer(dev, pipe);
 410         intel_dp->pps_pipe = pipe;
 411
 412         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 413                       pipe_name(intel_dp->pps_pipe),
 414                       port_name(intel_dig_port->port));
 415
 416         /* init power sequencer on this pipe and port */
 417         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 418         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 419
 420         /*
 421          * Even vdd force doesn't work until we've made
 422          * the power sequencer lock in on the port.
 423          */
 424         vlv_power_sequencer_kick(intel_dp);
 425
 426         return intel_dp->pps_pipe;
 427 }
 428
 429 static int
 430 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 431 {
 432         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 433         struct drm_device *dev = intel_dig_port->base.base.dev;
 434         struct drm_i915_private *dev_priv = to_i915(dev);
 435
 436         lockdep_assert_held(&dev_priv->pps_mutex);
 437
 438         /* We should never land here with regular DP ports */
 439         WARN_ON(!is_edp(intel_dp));
 440
 441         /*
 442          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 443          * mapping needs to be retrieved from VBT, for now just hard-code to
 444          * use instance #0 always.
 445          */
 446         if (!intel_dp->pps_reset)
 447                 return 0;
 448
 449         intel_dp->pps_reset = false;
 450
 451         /*
 452          * Only the HW needs to be reprogrammed, the SW state is fixed and
 453          * has been setup during connector init.
 454          */
 455         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 456
 457         return 0;
 458 }
 459
 460 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 461                                enum pipe pipe);
 462
 463 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 464                                enum pipe pipe)
 465 {
 466         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 467 }
 468
 469 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 470                                 enum pipe pipe)
 471 {
 472         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 473 }
 474
 475 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 476                          enum pipe pipe)
 477 {
 478         return true;
 479 }
 480
 481 static enum pipe
 482 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 483                      enum port port,
 484                      vlv_pipe_check pipe_check)
 485 {
 486         enum pipe pipe;
 487
 488         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 489                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 490                         PANEL_PORT_SELECT_MASK;
 491
 492                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 493                         continue;
 494
 495                 if (!pipe_check(dev_priv, pipe))
 496                         continue;
 497
 498                 return pipe;
 499         }
 500
 501         return INVALID_PIPE;
 502 }
 503
 504 static void
 505 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 506 {
 507         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 508         struct drm_device *dev = intel_dig_port->base.base.dev;
 509         struct drm_i915_private *dev_priv = to_i915(dev);
 510         enum port port = intel_dig_port->port;
 511
 512         lockdep_assert_held(&dev_priv->pps_mutex);
 513
 514         /* try to find a pipe with this port selected */
 515         /* first pick one where the panel is on */
 516         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 517                                                   vlv_pipe_has_pp_on);
 518         /* didn't find one? pick one where vdd is on */
 519         if (intel_dp->pps_pipe == INVALID_PIPE)
 520                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 521                                                           vlv_pipe_has_vdd_on);
 522         /* didn't find one? pick one with just the correct port */
 523         if (intel_dp->pps_pipe == INVALID_PIPE)
 524                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 525                                                           vlv_pipe_any);
 526
 527         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 528         if (intel_dp->pps_pipe == INVALID_PIPE) {
 529                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 530                               port_name(port));
 531                 return;
 532         }
 533
 534         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 535                       port_name(port), pipe_name(intel_dp->pps_pipe));
 536
 537         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 538         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 539 }
 540
 541 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 542 {
 543         struct drm_device *dev = &dev_priv->drm;
 544         struct intel_encoder *encoder;
 545
 546         if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 547                     !IS_BROXTON(dev)))
 548                 return;
 549
 550         /*
 551          * We can't grab pps_mutex here due to deadlock with power_domain
 552          * mutex when power_domain functions are called while holding pps_mutex.
 553          * That also means that in order to use pps_pipe the code needs to
 554          * hold both a power domain reference and pps_mutex, and the power domain
 555          * reference get/put must be done while _not_ holding pps_mutex.
 556          * pps_{lock,unlock}() do these steps in the correct order, so one
 557          * should use them always.
 558          */
 559
 560         for_each_intel_encoder(dev, encoder) {
 561                 struct intel_dp *intel_dp;
 562
 563                 if (encoder->type != INTEL_OUTPUT_EDP)
 564                         continue;
 565
 566                 intel_dp = enc_to_intel_dp(&encoder->base);
 567                 if (IS_BROXTON(dev))
 568                         intel_dp->pps_reset = true;
 569                 else
 570                         intel_dp->pps_pipe = INVALID_PIPE;
 571         }
 572 }
 573
 574 struct pps_registers {
 575         i915_reg_t pp_ctrl;
 576         i915_reg_t pp_stat;
 577         i915_reg_t pp_on;
 578         i915_reg_t pp_off;
 579         i915_reg_t pp_div;
 580 };
 581
 582 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 583                                     struct intel_dp *intel_dp,
 584                                     struct pps_registers *regs)
 585 {
 586         memset(regs, 0, sizeof(*regs));
 587
 588         if (IS_BROXTON(dev_priv)) {
 589                 int idx = bxt_power_sequencer_idx(intel_dp);
 590
 591                 regs->pp_ctrl = BXT_PP_CONTROL(idx);
 592                 regs->pp_stat = BXT_PP_STATUS(idx);
 593                 regs->pp_on = BXT_PP_ON_DELAYS(idx);
 594                 regs->pp_off = BXT_PP_OFF_DELAYS(idx);
 595         } else if (HAS_PCH_SPLIT(dev_priv)) {
 596                 regs->pp_ctrl = PCH_PP_CONTROL;
 597                 regs->pp_stat = PCH_PP_STATUS;
 598                 regs->pp_on = PCH_PP_ON_DELAYS;
 599                 regs->pp_off = PCH_PP_OFF_DELAYS;
 600                 regs->pp_div = PCH_PP_DIVISOR;
 601         } else {
 602                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 603
 604                 regs->pp_ctrl = VLV_PIPE_PP_CONTROL(pipe);
 605                 regs->pp_stat = VLV_PIPE_PP_STATUS(pipe);
 606                 regs->pp_on = VLV_PIPE_PP_ON_DELAYS(pipe);
 607                 regs->pp_off = VLV_PIPE_PP_OFF_DELAYS(pipe);
 608                 regs->pp_div = VLV_PIPE_PP_DIVISOR(pipe);
 609         }
 610 }
 611
 612 static i915_reg_t
 613 _pp_ctrl_reg(struct intel_dp *intel_dp)
 614 {
 615         struct pps_registers regs;
 616
 617         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 618                                 &regs);
 619
 620         return regs.pp_ctrl;
 621 }
 622
 623 static i915_reg_t
 624 _pp_stat_reg(struct intel_dp *intel_dp)
 625 {
 626         struct pps_registers regs;
 627
 628         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 629                                 &regs);
 630
 631         return regs.pp_stat;
 632 }
 633
 634 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 635    This function only applicable when panel PM state is not to be tracked */
 636 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 637                               void *unused)
 638 {
 639         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 640                                                  edp_notifier);
 641         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 642         struct drm_i915_private *dev_priv = to_i915(dev);
 643
 644         if (!is_edp(intel_dp) || code != SYS_RESTART)
 645                 return 0;
 646
 647         pps_lock(intel_dp);
 648
 649         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 650                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 651                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 652                 u32 pp_div;
 653
 654                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 655                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 656                 pp_div = I915_READ(pp_div_reg);
 657                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 658
 659                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 660                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 661                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 662                 msleep(intel_dp->panel_power_cycle_delay);
 663         }
 664
 665         pps_unlock(intel_dp);
 666
 667         return 0;
 668 }
 669
 670 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 671 {
 672         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 673         struct drm_i915_private *dev_priv = to_i915(dev);
 674
 675         lockdep_assert_held(&dev_priv->pps_mutex);
 676
 677         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 678             intel_dp->pps_pipe == INVALID_PIPE)
 679                 return false;
 680
 681         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 682 }
 683
 684 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 685 {
 686         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 687         struct drm_i915_private *dev_priv = to_i915(dev);
 688
 689         lockdep_assert_held(&dev_priv->pps_mutex);
 690
 691         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 692             intel_dp->pps_pipe == INVALID_PIPE)
 693                 return false;
 694
 695         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 696 }
 697
 698 static void
 699 intel_dp_check_edp(struct intel_dp *intel_dp)
 700 {
 701         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 702         struct drm_i915_private *dev_priv = to_i915(dev);
 703
 704         if (!is_edp(intel_dp))
 705                 return;
 706
 707         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 708                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 709                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 710                               I915_READ(_pp_stat_reg(intel_dp)),
 711                               I915_READ(_pp_ctrl_reg(intel_dp)));
 712         }
 713 }
 714
 715 static uint32_t
 716 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 717 {
 718         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 719         struct drm_device *dev = intel_dig_port->base.base.dev;
 720         struct drm_i915_private *dev_priv = to_i915(dev);
 721         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 722         uint32_t status;
 723         bool done;
 724
 725 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 726         if (has_aux_irq)
 727                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 728                                           msecs_to_jiffies_timeout(10));
 729         else
 730                 done = wait_for(C, 10) == 0;
 731         if (!done)
 732                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 733                           has_aux_irq);
 734 #undef C
 735
 736         return status;
 737 }
 738
 739 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 740 {
 741         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 742         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 743
 744         if (index)
 745                 return 0;
 746
 747         /*
 748          * The clock divider is based off the hrawclk, and would like to run at
 749          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 750          */
 751         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 752 }
 753
 754 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 755 {
 756         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 757         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 758
 759         if (index)
 760                 return 0;
 761
 762         /*
 763          * The clock divider is based off the cdclk or PCH rawclk, and would
 764          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 765          * divide by 2000 and use that
 766          */
 767         if (intel_dig_port->port == PORT_A)
 768                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 769         else
 770                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 771 }
 772
 773 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 774 {
 775         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 776         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 777
 778         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 779                 /* Workaround for non-ULT HSW */
 780                 switch (index) {
 781                 case 0: return 63;
 782                 case 1: return 72;
 783                 default: return 0;
 784                 }
 785         }
 786
 787         return ilk_get_aux_clock_divider(intel_dp, index);
 788 }
 789
 790 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 791 {
 792         /*
 793          * SKL doesn't need us to program the AUX clock divider (Hardware will
 794          * derive the clock from CDCLK automatically). We still implement the
 795          * get_aux_clock_divider vfunc to plug-in into the existing code.
 796          */
 797         return index ? 0 : 1;
 798 }
 799
 800 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 801                                      bool has_aux_irq,
 802                                      int send_bytes,
 803                                      uint32_t aux_clock_divider)
 804 {
 805         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 806         struct drm_device *dev = intel_dig_port->base.base.dev;
 807         uint32_t precharge, timeout;
 808
 809         if (IS_GEN6(dev))
 810                 precharge = 3;
 811         else
 812                 precharge = 5;
 813
 814         if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
 815                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 816         else
 817                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 818
 819         return DP_AUX_CH_CTL_SEND_BUSY |
 820                DP_AUX_CH_CTL_DONE |
 821                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 822                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 823                timeout |
 824                DP_AUX_CH_CTL_RECEIVE_ERROR |
 825                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 826                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 827                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 828 }
 829
 830 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 831                                       bool has_aux_irq,
 832                                       int send_bytes,
 833                                       uint32_t unused)
 834 {
 835         return DP_AUX_CH_CTL_SEND_BUSY |
 836                DP_AUX_CH_CTL_DONE |
 837                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 838                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 839                DP_AUX_CH_CTL_TIME_OUT_1600us |
 840                DP_AUX_CH_CTL_RECEIVE_ERROR |
 841                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 842                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
 843                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 844 }
 845
 846 static int
 847 intel_dp_aux_ch(struct intel_dp *intel_dp,
 848                 const uint8_t *send, int send_bytes,
 849                 uint8_t *recv, int recv_size)
 850 {
 851         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 852         struct drm_device *dev = intel_dig_port->base.base.dev;
 853         struct drm_i915_private *dev_priv = to_i915(dev);
 854         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 855         uint32_t aux_clock_divider;
 856         int i, ret, recv_bytes;
 857         uint32_t status;
 858         int try, clock = 0;
 859         bool has_aux_irq = HAS_AUX_IRQ(dev);
 860         bool vdd;
 861
 862         pps_lock(intel_dp);
 863
 864         /*
 865          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 866          * In such cases we want to leave VDD enabled and it's up to upper layers
 867          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 868          * ourselves.
 869          */
 870         vdd = edp_panel_vdd_on(intel_dp);
 871
 872         /* dp aux is extremely sensitive to irq latency, hence request the
 873          * lowest possible wakeup latency and so prevent the cpu from going into
 874          * deep sleep states.
 875          */
 876         pm_qos_update_request(&dev_priv->pm_qos, 0);
 877
 878         intel_dp_check_edp(intel_dp);
 879
 880         /* Try to wait for any previous AUX channel activity */
 881         for (try = 0; try < 3; try++) {
 882                 status = I915_READ_NOTRACE(ch_ctl);
 883                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 884                         break;
 885                 msleep(1);
 886         }
 887
 888         if (try == 3) {
 889                 static u32 last_status = -1;
 890                 const u32 status = I915_READ(ch_ctl);
 891
 892                 if (status != last_status) {
 893                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
 894                              status);
 895                         last_status = status;
 896                 }
 897
 898                 ret = -EBUSY;
 899                 goto out;
 900         }
 901
 902         /* Only 5 data registers! */
 903         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 904                 ret = -E2BIG;
 905                 goto out;
 906         }
 907
 908         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 909                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 910                                                           has_aux_irq,
 911                                                           send_bytes,
 912                                                           aux_clock_divider);
 913
 914                 /* Must try at least 3 times according to DP spec */
 915                 for (try = 0; try < 5; try++) {
 916                         /* Load the send data into the aux channel data registers */
 917                         for (i = 0; i < send_bytes; i += 4)
 918                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
 919                                            intel_dp_pack_aux(send + i,
 920                                                              send_bytes - i));
 921
 922                         /* Send the command and wait for it to complete */
 923                         I915_WRITE(ch_ctl, send_ctl);
 924
 925                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 926
 927                         /* Clear done status and any errors */
 928                         I915_WRITE(ch_ctl,
 929                                    status |
 930                                    DP_AUX_CH_CTL_DONE |
 931                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 932                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 933
 934                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 935                                 continue;
 936
 937                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 938                          *   400us delay required for errors and timeouts
 939                          *   Timeout errors from the HW already meet this
 940                          *   requirement so skip to next iteration
 941                          */
 942                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 943                                 usleep_range(400, 500);
 944                                 continue;
 945                         }
 946                         if (status & DP_AUX_CH_CTL_DONE)
 947                                 goto done;
 948                 }
 949         }
 950
 951         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 952                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 953                 ret = -EBUSY;
 954                 goto out;
 955         }
 956
 957 done:
 958         /* Check for timeout or receive error.
 959          * Timeouts occur when the sink is not connected
 960          */
 961         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 962                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 963                 ret = -EIO;
 964                 goto out;
 965         }
 966
 967         /* Timeouts occur when the device isn't connected, so they're
 968          * "normal" -- don't fill the kernel log with these */
 969         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 970                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 971                 ret = -ETIMEDOUT;
 972                 goto out;
 973         }
 974
 975         /* Unload any bytes sent back from the other side */
 976         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 977                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 978
 979         /*
 980          * By BSpec: "Message sizes of 0 or >20 are not allowed."
 981          * We have no idea of what happened so we return -EBUSY so
 982          * drm layer takes care for the necessary retries.
 983          */
 984         if (recv_bytes == 0 || recv_bytes > 20) {
 985                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
 986                               recv_bytes);
 987                 /*
 988                  * FIXME: This patch was created on top of a series that
 989                  * organize the retries at drm level. There EBUSY should
 990                  * also take care for 1ms wait before retrying.
 991                  * That aux retries re-org is still needed and after that is
 992                  * merged we remove this sleep from here.
 993                  */
 994                 usleep_range(1000, 1500);
 995                 ret = -EBUSY;
 996                 goto out;
 997         }
 998
 999         if (recv_bytes > recv_size)
1000                 recv_bytes = recv_size;
1001
1002         for (i = 0; i < recv_bytes; i += 4)
1003                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1004                                     recv + i, recv_bytes - i);
1005
1006         ret = recv_bytes;
1007 out:
1008         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1009
1010         if (vdd)
1011                 edp_panel_vdd_off(intel_dp, false);
1012
1013         pps_unlock(intel_dp);
1014
1015         return ret;
1016 }
1017
1018 #define BARE_ADDRESS_SIZE       3
1019 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1020 static ssize_t
1021 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1022 {
1023         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1024         uint8_t txbuf[20], rxbuf[20];
1025         size_t txsize, rxsize;
1026         int ret;
1027
1028         txbuf[0] = (msg->request << 4) |
1029                 ((msg->address >> 16) & 0xf);
1030         txbuf[1] = (msg->address >> 8) & 0xff;
1031         txbuf[2] = msg->address & 0xff;
1032         txbuf[3] = msg->size - 1;
1033
1034         switch (msg->request & ~DP_AUX_I2C_MOT) {
1035         case DP_AUX_NATIVE_WRITE:
1036         case DP_AUX_I2C_WRITE:
1037         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1038                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1039                 rxsize = 2; /* 0 or 1 data bytes */
1040
1041                 if (WARN_ON(txsize > 20))
1042                         return -E2BIG;
1043
1044                 WARN_ON(!msg->buffer != !msg->size);
1045
1046                 if (msg->buffer)
1047                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1048
1049                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1050                 if (ret > 0) {
1051                         msg->reply = rxbuf[0] >> 4;
1052
1053                         if (ret > 1) {
1054                                 /* Number of bytes written in a short write. */
1055                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1056                         } else {
1057                                 /* Return payload size. */
1058                                 ret = msg->size;
1059                         }
1060                 }
1061                 break;
1062
1063         case DP_AUX_NATIVE_READ:
1064         case DP_AUX_I2C_READ:
1065                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1066                 rxsize = msg->size + 1;
1067
1068                 if (WARN_ON(rxsize > 20))
1069                         return -E2BIG;
1070
1071                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1072                 if (ret > 0) {
1073                         msg->reply = rxbuf[0] >> 4;
1074                         /*
1075                          * Assume happy day, and copy the data. The caller is
1076                          * expected to check msg->reply before touching it.
1077                          *
1078                          * Return payload size.
1079                          */
1080                         ret--;
1081                         memcpy(msg->buffer, rxbuf + 1, ret);
1082                 }
1083                 break;
1084
1085         default:
1086                 ret = -EINVAL;
1087                 break;
1088         }
1089
1090         return ret;
1091 }
1092
1093 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1094                                        enum port port)
1095 {
1096         switch (port) {
1097         case PORT_B:
1098         case PORT_C:
1099         case PORT_D:
1100                 return DP_AUX_CH_CTL(port);
1101         default:
1102                 MISSING_CASE(port);
1103                 return DP_AUX_CH_CTL(PORT_B);
1104         }
1105 }
1106
1107 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1108                                         enum port port, int index)
1109 {
1110         switch (port) {
1111         case PORT_B:
1112         case PORT_C:
1113         case PORT_D:
1114                 return DP_AUX_CH_DATA(port, index);
1115         default:
1116                 MISSING_CASE(port);
1117                 return DP_AUX_CH_DATA(PORT_B, index);
1118         }
1119 }
1120
1121 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1122                                        enum port port)
1123 {
1124         switch (port) {
1125         case PORT_A:
1126                 return DP_AUX_CH_CTL(port);
1127         case PORT_B:
1128         case PORT_C:
1129         case PORT_D:
1130                 return PCH_DP_AUX_CH_CTL(port);
1131         default:
1132                 MISSING_CASE(port);
1133                 return DP_AUX_CH_CTL(PORT_A);
1134         }
1135 }
1136
1137 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1138                                         enum port port, int index)
1139 {
1140         switch (port) {
1141         case PORT_A:
1142                 return DP_AUX_CH_DATA(port, index);
1143         case PORT_B:
1144         case PORT_C:
1145         case PORT_D:
1146                 return PCH_DP_AUX_CH_DATA(port, index);
1147         default:
1148                 MISSING_CASE(port);
1149                 return DP_AUX_CH_DATA(PORT_A, index);
1150         }
1151 }
1152
1153 /*
1154  * On SKL we don't have Aux for port E so we rely
1155  * on VBT to set a proper alternate aux channel.
1156  */
1157 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1158 {
1159         const struct ddi_vbt_port_info *info =
1160                 &dev_priv->vbt.ddi_port_info[PORT_E];
1161
1162         switch (info->alternate_aux_channel) {
1163         case DP_AUX_A:
1164                 return PORT_A;
1165         case DP_AUX_B:
1166                 return PORT_B;
1167         case DP_AUX_C:
1168                 return PORT_C;
1169         case DP_AUX_D:
1170                 return PORT_D;
1171         default:
1172                 MISSING_CASE(info->alternate_aux_channel);
1173                 return PORT_A;
1174         }
1175 }
1176
1177 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1178                                        enum port port)
1179 {
1180         if (port == PORT_E)
1181                 port = skl_porte_aux_port(dev_priv);
1182
1183         switch (port) {
1184         case PORT_A:
1185         case PORT_B:
1186         case PORT_C:
1187         case PORT_D:
1188                 return DP_AUX_CH_CTL(port);
1189         default:
1190                 MISSING_CASE(port);
1191                 return DP_AUX_CH_CTL(PORT_A);
1192         }
1193 }
1194
1195 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1196                                         enum port port, int index)
1197 {
1198         if (port == PORT_E)
1199                 port = skl_porte_aux_port(dev_priv);
1200
1201         switch (port) {
1202         case PORT_A:
1203         case PORT_B:
1204         case PORT_C:
1205         case PORT_D:
1206                 return DP_AUX_CH_DATA(port, index);
1207         default:
1208                 MISSING_CASE(port);
1209                 return DP_AUX_CH_DATA(PORT_A, index);
1210         }
1211 }
1212
1213 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1214                                          enum port port)
1215 {
1216         if (INTEL_INFO(dev_priv)->gen >= 9)
1217                 return skl_aux_ctl_reg(dev_priv, port);
1218         else if (HAS_PCH_SPLIT(dev_priv))
1219                 return ilk_aux_ctl_reg(dev_priv, port);
1220         else
1221                 return g4x_aux_ctl_reg(dev_priv, port);
1222 }
1223
1224 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1225                                           enum port port, int index)
1226 {
1227         if (INTEL_INFO(dev_priv)->gen >= 9)
1228                 return skl_aux_data_reg(dev_priv, port, index);
1229         else if (HAS_PCH_SPLIT(dev_priv))
1230                 return ilk_aux_data_reg(dev_priv, port, index);
1231         else
1232                 return g4x_aux_data_reg(dev_priv, port, index);
1233 }
1234
1235 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1236 {
1237         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1238         enum port port = dp_to_dig_port(intel_dp)->port;
1239         int i;
1240
1241         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1242         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1243                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1244 }
1245
1246 static void
1247 intel_dp_aux_fini(struct intel_dp *intel_dp)
1248 {
1249         kfree(intel_dp->aux.name);
1250 }
1251
1252 static void
1253 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1254 {
1255         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1256         enum port port = intel_dig_port->port;
1257
1258         intel_aux_reg_init(intel_dp);
1259         drm_dp_aux_init(&intel_dp->aux);
1260
1261         /* Failure to allocate our preferred name is not critical */
1262         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1263         intel_dp->aux.transfer = intel_dp_aux_transfer;
1264 }
1265
1266 static int
1267 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1268 {
1269         if (intel_dp->num_sink_rates) {
1270                 *sink_rates = intel_dp->sink_rates;
1271                 return intel_dp->num_sink_rates;
1272         }
1273
1274         *sink_rates = default_rates;
1275
1276         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1277 }
1278
1279 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1280 {
1281         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1282         struct drm_device *dev = dig_port->base.base.dev;
1283
1284         /* WaDisableHBR2:skl */
1285         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1286                 return false;
1287
1288         if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1289             (INTEL_INFO(dev)->gen >= 9))
1290                 return true;
1291         else
1292                 return false;
1293 }
1294
1295 static int
1296 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1297 {
1298         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1299         struct drm_device *dev = dig_port->base.base.dev;
1300         int size;
1301
1302         if (IS_BROXTON(dev)) {
1303                 *source_rates = bxt_rates;
1304                 size = ARRAY_SIZE(bxt_rates);
1305         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1306                 *source_rates = skl_rates;
1307                 size = ARRAY_SIZE(skl_rates);
1308         } else {
1309                 *source_rates = default_rates;
1310                 size = ARRAY_SIZE(default_rates);
1311         }
1312
1313         /* This depends on the fact that 5.4 is last value in the array */
1314         if (!intel_dp_source_supports_hbr2(intel_dp))
1315                 size--;
1316
1317         return size;
1318 }
1319
1320 static void
1321 intel_dp_set_clock(struct intel_encoder *encoder,
1322                    struct intel_crtc_state *pipe_config)
1323 {
1324         struct drm_device *dev = encoder->base.dev;
1325         const struct dp_link_dpll *divisor = NULL;
1326         int i, count = 0;
1327
1328         if (IS_G4X(dev)) {
1329                 divisor = gen4_dpll;
1330                 count = ARRAY_SIZE(gen4_dpll);
1331         } else if (HAS_PCH_SPLIT(dev)) {
1332                 divisor = pch_dpll;
1333                 count = ARRAY_SIZE(pch_dpll);
1334         } else if (IS_CHERRYVIEW(dev)) {
1335                 divisor = chv_dpll;
1336                 count = ARRAY_SIZE(chv_dpll);
1337         } else if (IS_VALLEYVIEW(dev)) {
1338                 divisor = vlv_dpll;
1339                 count = ARRAY_SIZE(vlv_dpll);
1340         }
1341
1342         if (divisor && count) {
1343                 for (i = 0; i < count; i++) {
1344                         if (pipe_config->port_clock == divisor[i].clock) {
1345                                 pipe_config->dpll = divisor[i].dpll;
1346                                 pipe_config->clock_set = true;
1347                                 break;
1348                         }
1349                 }
1350         }
1351 }
1352
1353 static int intersect_rates(const int *source_rates, int source_len,
1354                            const int *sink_rates, int sink_len,
1355                            int *common_rates)
1356 {
1357         int i = 0, j = 0, k = 0;
1358
1359         while (i < source_len && j < sink_len) {
1360                 if (source_rates[i] == sink_rates[j]) {
1361                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1362                                 return k;
1363                         common_rates[k] = source_rates[i];
1364                         ++k;
1365                         ++i;
1366                         ++j;
1367                 } else if (source_rates[i] < sink_rates[j]) {
1368                         ++i;
1369                 } else {
1370                         ++j;
1371                 }
1372         }
1373         return k;
1374 }
1375
1376 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1377                                  int *common_rates)
1378 {
1379         const int *source_rates, *sink_rates;
1380         int source_len, sink_len;
1381
1382         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1383         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1384
1385         return intersect_rates(source_rates, source_len,
1386                                sink_rates, sink_len,
1387                                common_rates);
1388 }
1389
1390 static void snprintf_int_array(char *str, size_t len,
1391                                const int *array, int nelem)
1392 {
1393         int i;
1394
1395         str[0] = '\0';
1396
1397         for (i = 0; i < nelem; i++) {
1398                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1399                 if (r >= len)
1400                         return;
1401                 str += r;
1402                 len -= r;
1403         }
1404 }
1405
1406 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1407 {
1408         const int *source_rates, *sink_rates;
1409         int source_len, sink_len, common_len;
1410         int common_rates[DP_MAX_SUPPORTED_RATES];
1411         char str[128]; /* FIXME: too big for stack? */
1412
1413         if ((drm_debug & DRM_UT_KMS) == 0)
1414                 return;
1415
1416         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1417         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1418         DRM_DEBUG_KMS("source rates: %s\n", str);
1419
1420         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1421         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1422         DRM_DEBUG_KMS("sink rates: %s\n", str);
1423
1424         common_len = intel_dp_common_rates(intel_dp, common_rates);
1425         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1426         DRM_DEBUG_KMS("common rates: %s\n", str);
1427 }
1428
1429 static int rate_to_index(int find, const int *rates)
1430 {
1431         int i = 0;
1432
1433         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1434                 if (find == rates[i])
1435                         break;
1436
1437         return i;
1438 }
1439
1440 int
1441 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1442 {
1443         int rates[DP_MAX_SUPPORTED_RATES] = {};
1444         int len;
1445
1446         len = intel_dp_common_rates(intel_dp, rates);
1447         if (WARN_ON(len <= 0))
1448                 return 162000;
1449
1450         return rates[rate_to_index(0, rates) - 1];
1451 }
1452
1453 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1454 {
1455         return rate_to_index(rate, intel_dp->sink_rates);
1456 }
1457
1458 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1459                            uint8_t *link_bw, uint8_t *rate_select)
1460 {
1461         if (intel_dp->num_sink_rates) {
1462                 *link_bw = 0;
1463                 *rate_select =
1464                         intel_dp_rate_select(intel_dp, port_clock);
1465         } else {
1466                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1467                 *rate_select = 0;
1468         }
1469 }
1470
1471 bool
1472 intel_dp_compute_config(struct intel_encoder *encoder,
1473                         struct intel_crtc_state *pipe_config)
1474 {
1475         struct drm_device *dev = encoder->base.dev;
1476         struct drm_i915_private *dev_priv = to_i915(dev);
1477         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1478         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1479         enum port port = dp_to_dig_port(intel_dp)->port;
1480         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1481         struct intel_connector *intel_connector = intel_dp->attached_connector;
1482         int lane_count, clock;
1483         int min_lane_count = 1;
1484         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1485         /* Conveniently, the link BW constants become indices with a shift...*/
1486         int min_clock = 0;
1487         int max_clock;
1488         int bpp, mode_rate;
1489         int link_avail, link_clock;
1490         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1491         int common_len;
1492         uint8_t link_bw, rate_select;
1493
1494         common_len = intel_dp_common_rates(intel_dp, common_rates);
1495
1496         /* No common link rates between source and sink */
1497         WARN_ON(common_len <= 0);
1498
1499         max_clock = common_len - 1;
1500
1501         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1502                 pipe_config->has_pch_encoder = true;
1503
1504         pipe_config->has_drrs = false;
1505         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1506
1507         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1508                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1509                                        adjusted_mode);
1510
1511                 if (INTEL_INFO(dev)->gen >= 9) {
1512                         int ret;
1513                         ret = skl_update_scaler_crtc(pipe_config);
1514                         if (ret)
1515                                 return ret;
1516                 }
1517
1518                 if (HAS_GMCH_DISPLAY(dev))
1519                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1520                                                  intel_connector->panel.fitting_mode);
1521                 else
1522                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1523                                                 intel_connector->panel.fitting_mode);
1524         }
1525
1526         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1527                 return false;
1528
1529         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1530                       "max bw %d pixel clock %iKHz\n",
1531                       max_lane_count, common_rates[max_clock],
1532                       adjusted_mode->crtc_clock);
1533
1534         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1535          * bpc in between. */
1536         bpp = pipe_config->pipe_bpp;
1537         if (is_edp(intel_dp)) {
1538
1539                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1540                 if (intel_connector->base.display_info.bpc == 0 &&
1541                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1542                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1543                                       dev_priv->vbt.edp.bpp);
1544                         bpp = dev_priv->vbt.edp.bpp;
1545                 }
1546
1547                 /*
1548                  * Use the maximum clock and number of lanes the eDP panel
1549                  * advertizes being capable of. The panels are generally
1550                  * designed to support only a single clock and lane
1551                  * configuration, and typically these values correspond to the
1552                  * native resolution of the panel.
1553                  */
1554                 min_lane_count = max_lane_count;
1555                 min_clock = max_clock;
1556         }
1557
1558         for (; bpp >= 6*3; bpp -= 2*3) {
1559                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1560                                                    bpp);
1561
1562                 for (clock = min_clock; clock <= max_clock; clock++) {
1563                         for (lane_count = min_lane_count;
1564                                 lane_count <= max_lane_count;
1565                                 lane_count <<= 1) {
1566
1567                                 link_clock = common_rates[clock];
1568                                 link_avail = intel_dp_max_data_rate(link_clock,
1569                                                                     lane_count);
1570
1571                                 if (mode_rate <= link_avail) {
1572                                         goto found;
1573                                 }
1574                         }
1575                 }
1576         }
1577
1578         return false;
1579
1580 found:
1581         if (intel_dp->color_range_auto) {
1582                 /*
1583                  * See:
1584                  * CEA-861-E - 5.1 Default Encoding Parameters
1585                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1586                  */
1587                 pipe_config->limited_color_range =
1588                         bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1589         } else {
1590                 pipe_config->limited_color_range =
1591                         intel_dp->limited_color_range;
1592         }
1593
1594         pipe_config->lane_count = lane_count;
1595
1596         pipe_config->pipe_bpp = bpp;
1597         pipe_config->port_clock = common_rates[clock];
1598
1599         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1600                               &link_bw, &rate_select);
1601
1602         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1603                       link_bw, rate_select, pipe_config->lane_count,
1604                       pipe_config->port_clock, bpp);
1605         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1606                       mode_rate, link_avail);
1607
1608         intel_link_compute_m_n(bpp, lane_count,
1609                                adjusted_mode->crtc_clock,
1610                                pipe_config->port_clock,
1611                                &pipe_config->dp_m_n);
1612
1613         if (intel_connector->panel.downclock_mode != NULL &&
1614                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1615                         pipe_config->has_drrs = true;
1616                         intel_link_compute_m_n(bpp, lane_count,
1617                                 intel_connector->panel.downclock_mode->clock,
1618                                 pipe_config->port_clock,
1619                                 &pipe_config->dp_m2_n2);
1620         }
1621
1622         /*
1623          * DPLL0 VCO may need to be adjusted to get the correct
1624          * clock for eDP. This will affect cdclk as well.
1625          */
1626         if (is_edp(intel_dp) &&
1627             (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1628                 int vco;
1629
1630                 switch (pipe_config->port_clock / 2) {
1631                 case 108000:
1632                 case 216000:
1633                         vco = 8640000;
1634                         break;
1635                 default:
1636                         vco = 8100000;
1637                         break;
1638                 }
1639
1640                 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1641         }
1642
1643         if (!HAS_DDI(dev))
1644                 intel_dp_set_clock(encoder, pipe_config);
1645
1646         return true;
1647 }
1648
1649 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1650                               const struct intel_crtc_state *pipe_config)
1651 {
1652         intel_dp->link_rate = pipe_config->port_clock;
1653         intel_dp->lane_count = pipe_config->lane_count;
1654 }
1655
1656 static void intel_dp_prepare(struct intel_encoder *encoder)
1657 {
1658         struct drm_device *dev = encoder->base.dev;
1659         struct drm_i915_private *dev_priv = to_i915(dev);
1660         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1661         enum port port = dp_to_dig_port(intel_dp)->port;
1662         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1663         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1664
1665         intel_dp_set_link_params(intel_dp, crtc->config);
1666
1667         /*
1668          * There are four kinds of DP registers:
1669          *
1670          *      IBX PCH
1671          *      SNB CPU
1672          *      IVB CPU
1673          *      CPT PCH
1674          *
1675          * IBX PCH and CPU are the same for almost everything,
1676          * except that the CPU DP PLL is configured in this
1677          * register
1678          *
1679          * CPT PCH is quite different, having many bits moved
1680          * to the TRANS_DP_CTL register instead. That
1681          * configuration happens (oddly) in ironlake_pch_enable
1682          */
1683
1684         /* Preserve the BIOS-computed detected bit. This is
1685          * supposed to be read-only.
1686          */
1687         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1688
1689         /* Handle DP bits in common between all three register formats */
1690         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1691         intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1692
1693         /* Split out the IBX/CPU vs CPT settings */
1694
1695         if (IS_GEN7(dev) && port == PORT_A) {
1696                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1697                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1698                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1699                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1700                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1701
1702                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1703                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1704
1705                 intel_dp->DP |= crtc->pipe << 29;
1706         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1707                 u32 trans_dp;
1708
1709                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1710
1711                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1712                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1713                         trans_dp |= TRANS_DP_ENH_FRAMING;
1714                 else
1715                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1716                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1717         } else {
1718                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1719                     !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
1720                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1721
1722                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1723                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1724                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1725                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1726                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1727
1728                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1729                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1730
1731                 if (IS_CHERRYVIEW(dev))
1732                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1733                 else if (crtc->pipe == PIPE_B)
1734                         intel_dp->DP |= DP_PIPEB_SELECT;
1735         }
1736 }
1737
1738 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1739 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1740
1741 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1742 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1743
1744 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1745 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1746
1747 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1748                                    struct intel_dp *intel_dp);
1749
1750 static void wait_panel_status(struct intel_dp *intel_dp,
1751                                        u32 mask,
1752                                        u32 value)
1753 {
1754         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1755         struct drm_i915_private *dev_priv = to_i915(dev);
1756         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1757
1758         lockdep_assert_held(&dev_priv->pps_mutex);
1759
1760         intel_pps_verify_state(dev_priv, intel_dp);
1761
1762         pp_stat_reg = _pp_stat_reg(intel_dp);
1763         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1764
1765         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1766                         mask, value,
1767                         I915_READ(pp_stat_reg),
1768                         I915_READ(pp_ctrl_reg));
1769
1770         if (intel_wait_for_register(dev_priv,
1771                                     pp_stat_reg, mask, value,
1772                                     5000))
1773                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1774                                 I915_READ(pp_stat_reg),
1775                                 I915_READ(pp_ctrl_reg));
1776
1777         DRM_DEBUG_KMS("Wait complete\n");
1778 }
1779
1780 static void wait_panel_on(struct intel_dp *intel_dp)
1781 {
1782         DRM_DEBUG_KMS("Wait for panel power on\n");
1783         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1784 }
1785
1786 static void wait_panel_off(struct intel_dp *intel_dp)
1787 {
1788         DRM_DEBUG_KMS("Wait for panel power off time\n");
1789         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1790 }
1791
1792 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1793 {
1794         ktime_t panel_power_on_time;
1795         s64 panel_power_off_duration;
1796
1797         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1798
1799         /* take the difference of currrent time and panel power off time
1800          * and then make panel wait for t11_t12 if needed. */
1801         panel_power_on_time = ktime_get_boottime();
1802         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1803
1804         /* When we disable the VDD override bit last we have to do the manual
1805          * wait. */
1806         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1807                 wait_remaining_ms_from_jiffies(jiffies,
1808                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1809
1810         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1811 }
1812
1813 static void wait_backlight_on(struct intel_dp *intel_dp)
1814 {
1815         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1816                                        intel_dp->backlight_on_delay);
1817 }
1818
1819 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1820 {
1821         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1822                                        intel_dp->backlight_off_delay);
1823 }
1824
1825 /* Read the current pp_control value, unlocking the register if it
1826  * is locked
1827  */
1828
1829 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1830 {
1831         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1832         struct drm_i915_private *dev_priv = to_i915(dev);
1833         u32 control;
1834
1835         lockdep_assert_held(&dev_priv->pps_mutex);
1836
1837         control = I915_READ(_pp_ctrl_reg(intel_dp));
1838         if (!IS_BROXTON(dev)) {
1839                 control &= ~PANEL_UNLOCK_MASK;
1840                 control |= PANEL_UNLOCK_REGS;
1841         }
1842         return control;
1843 }
1844
1845 /*
1846  * Must be paired with edp_panel_vdd_off().
1847  * Must hold pps_mutex around the whole on/off sequence.
1848  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1849  */
1850 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1851 {
1852         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1853         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1854         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1855         struct drm_i915_private *dev_priv = to_i915(dev);
1856         enum intel_display_power_domain power_domain;
1857         u32 pp;
1858         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1859         bool need_to_disable = !intel_dp->want_panel_vdd;
1860
1861         lockdep_assert_held(&dev_priv->pps_mutex);
1862
1863         if (!is_edp(intel_dp))
1864                 return false;
1865
1866         cancel_delayed_work(&intel_dp->panel_vdd_work);
1867         intel_dp->want_panel_vdd = true;
1868
1869         if (edp_have_panel_vdd(intel_dp))
1870                 return need_to_disable;
1871
1872         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1873         intel_display_power_get(dev_priv, power_domain);
1874
1875         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1876                       port_name(intel_dig_port->port));
1877
1878         if (!edp_have_panel_power(intel_dp))
1879                 wait_panel_power_cycle(intel_dp);
1880
1881         pp = ironlake_get_pp_control(intel_dp);
1882         pp |= EDP_FORCE_VDD;
1883
1884         pp_stat_reg = _pp_stat_reg(intel_dp);
1885         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1886
1887         I915_WRITE(pp_ctrl_reg, pp);
1888         POSTING_READ(pp_ctrl_reg);
1889         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1890                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1891         /*
1892          * If the panel wasn't on, delay before accessing aux channel
1893          */
1894         if (!edp_have_panel_power(intel_dp)) {
1895                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1896                               port_name(intel_dig_port->port));
1897                 msleep(intel_dp->panel_power_up_delay);
1898         }
1899
1900         return need_to_disable;
1901 }
1902
1903 /*
1904  * Must be paired with intel_edp_panel_vdd_off() or
1905  * intel_edp_panel_off().
1906  * Nested calls to these functions are not allowed since
1907  * we drop the lock. Caller must use some higher level
1908  * locking to prevent nested calls from other threads.
1909  */
1910 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1911 {
1912         bool vdd;
1913
1914         if (!is_edp(intel_dp))
1915                 return;
1916
1917         pps_lock(intel_dp);
1918         vdd = edp_panel_vdd_on(intel_dp);
1919         pps_unlock(intel_dp);
1920
1921         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1922              port_name(dp_to_dig_port(intel_dp)->port));
1923 }
1924
1925 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1926 {
1927         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1928         struct drm_i915_private *dev_priv = to_i915(dev);
1929         struct intel_digital_port *intel_dig_port =
1930                 dp_to_dig_port(intel_dp);
1931         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1932         enum intel_display_power_domain power_domain;
1933         u32 pp;
1934         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1935
1936         lockdep_assert_held(&dev_priv->pps_mutex);
1937
1938         WARN_ON(intel_dp->want_panel_vdd);
1939
1940         if (!edp_have_panel_vdd(intel_dp))
1941                 return;
1942
1943         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1944                       port_name(intel_dig_port->port));
1945
1946         pp = ironlake_get_pp_control(intel_dp);
1947         pp &= ~EDP_FORCE_VDD;
1948
1949         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1950         pp_stat_reg = _pp_stat_reg(intel_dp);
1951
1952         I915_WRITE(pp_ctrl_reg, pp);
1953         POSTING_READ(pp_ctrl_reg);
1954
1955         /* Make sure sequencer is idle before allowing subsequent activity */
1956         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1957         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1958
1959         if ((pp & POWER_TARGET_ON) == 0)
1960                 intel_dp->panel_power_off_time = ktime_get_boottime();
1961
1962         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1963         intel_display_power_put(dev_priv, power_domain);
1964 }
1965
1966 static void edp_panel_vdd_work(struct work_struct *__work)
1967 {
1968         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1969                                                  struct intel_dp, panel_vdd_work);
1970
1971         pps_lock(intel_dp);
1972         if (!intel_dp->want_panel_vdd)
1973                 edp_panel_vdd_off_sync(intel_dp);
1974         pps_unlock(intel_dp);
1975 }
1976
1977 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1978 {
1979         unsigned long delay;
1980
1981         /*
1982          * Queue the timer to fire a long time from now (relative to the power
1983          * down delay) to keep the panel power up across a sequence of
1984          * operations.
1985          */
1986         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1987         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1988 }
1989
1990 /*
1991  * Must be paired with edp_panel_vdd_on().
1992  * Must hold pps_mutex around the whole on/off sequence.
1993  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1994  */
1995 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1996 {
1997         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1998
1999         lockdep_assert_held(&dev_priv->pps_mutex);
2000
2001         if (!is_edp(intel_dp))
2002                 return;
2003
2004         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2005              port_name(dp_to_dig_port(intel_dp)->port));
2006
2007         intel_dp->want_panel_vdd = false;
2008
2009         if (sync)
2010                 edp_panel_vdd_off_sync(intel_dp);
2011         else
2012                 edp_panel_vdd_schedule_off(intel_dp);
2013 }
2014
2015 static void edp_panel_on(struct intel_dp *intel_dp)
2016 {
2017         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2018         struct drm_i915_private *dev_priv = to_i915(dev);
2019         u32 pp;
2020         i915_reg_t pp_ctrl_reg;
2021
2022         lockdep_assert_held(&dev_priv->pps_mutex);
2023
2024         if (!is_edp(intel_dp))
2025                 return;
2026
2027         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2028                       port_name(dp_to_dig_port(intel_dp)->port));
2029
2030         if (WARN(edp_have_panel_power(intel_dp),
2031                  "eDP port %c panel power already on\n",
2032                  port_name(dp_to_dig_port(intel_dp)->port)))
2033                 return;
2034
2035         wait_panel_power_cycle(intel_dp);
2036
2037         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2038         pp = ironlake_get_pp_control(intel_dp);
2039         if (IS_GEN5(dev)) {
2040                 /* ILK workaround: disable reset around power sequence */
2041                 pp &= ~PANEL_POWER_RESET;
2042                 I915_WRITE(pp_ctrl_reg, pp);
2043                 POSTING_READ(pp_ctrl_reg);
2044         }
2045
2046         pp |= POWER_TARGET_ON;
2047         if (!IS_GEN5(dev))
2048                 pp |= PANEL_POWER_RESET;
2049
2050         I915_WRITE(pp_ctrl_reg, pp);
2051         POSTING_READ(pp_ctrl_reg);
2052
2053         wait_panel_on(intel_dp);
2054         intel_dp->last_power_on = jiffies;
2055
2056         if (IS_GEN5(dev)) {
2057                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2058                 I915_WRITE(pp_ctrl_reg, pp);
2059                 POSTING_READ(pp_ctrl_reg);
2060         }
2061 }
2062
2063 void intel_edp_panel_on(struct intel_dp *intel_dp)
2064 {
2065         if (!is_edp(intel_dp))
2066                 return;
2067
2068         pps_lock(intel_dp);
2069         edp_panel_on(intel_dp);
2070         pps_unlock(intel_dp);
2071 }
2072
2073
2074 static void edp_panel_off(struct intel_dp *intel_dp)
2075 {
2076         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2077         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2078         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2079         struct drm_i915_private *dev_priv = to_i915(dev);
2080         enum intel_display_power_domain power_domain;
2081         u32 pp;
2082         i915_reg_t pp_ctrl_reg;
2083
2084         lockdep_assert_held(&dev_priv->pps_mutex);
2085
2086         if (!is_edp(intel_dp))
2087                 return;
2088
2089         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2090                       port_name(dp_to_dig_port(intel_dp)->port));
2091
2092         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2093              port_name(dp_to_dig_port(intel_dp)->port));
2094
2095         pp = ironlake_get_pp_control(intel_dp);
2096         /* We need to switch off panel power _and_ force vdd, for otherwise some
2097          * panels get very unhappy and cease to work. */
2098         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2099                 EDP_BLC_ENABLE);
2100
2101         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2102
2103         intel_dp->want_panel_vdd = false;
2104
2105         I915_WRITE(pp_ctrl_reg, pp);
2106         POSTING_READ(pp_ctrl_reg);
2107
2108         intel_dp->panel_power_off_time = ktime_get_boottime();
2109         wait_panel_off(intel_dp);
2110
2111         /* We got a reference when we enabled the VDD. */
2112         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2113         intel_display_power_put(dev_priv, power_domain);
2114 }
2115
2116 void intel_edp_panel_off(struct intel_dp *intel_dp)
2117 {
2118         if (!is_edp(intel_dp))
2119                 return;
2120
2121         pps_lock(intel_dp);
2122         edp_panel_off(intel_dp);
2123         pps_unlock(intel_dp);
2124 }
2125
2126 /* Enable backlight in the panel power control. */
2127 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2128 {
2129         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2130         struct drm_device *dev = intel_dig_port->base.base.dev;
2131         struct drm_i915_private *dev_priv = to_i915(dev);
2132         u32 pp;
2133         i915_reg_t pp_ctrl_reg;
2134
2135         /*
2136          * If we enable the backlight right away following a panel power
2137          * on, we may see slight flicker as the panel syncs with the eDP
2138          * link.  So delay a bit to make sure the image is solid before
2139          * allowing it to appear.
2140          */
2141         wait_backlight_on(intel_dp);
2142
2143         pps_lock(intel_dp);
2144
2145         pp = ironlake_get_pp_control(intel_dp);
2146         pp |= EDP_BLC_ENABLE;
2147
2148         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2149
2150         I915_WRITE(pp_ctrl_reg, pp);
2151         POSTING_READ(pp_ctrl_reg);
2152
2153         pps_unlock(intel_dp);
2154 }
2155
2156 /* Enable backlight PWM and backlight PP control. */
2157 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2158 {
2159         if (!is_edp(intel_dp))
2160                 return;
2161
2162         DRM_DEBUG_KMS("\n");
2163
2164         intel_panel_enable_backlight(intel_dp->attached_connector);
2165         _intel_edp_backlight_on(intel_dp);
2166 }
2167
2168 /* Disable backlight in the panel power control. */
2169 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2170 {
2171         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2172         struct drm_i915_private *dev_priv = to_i915(dev);
2173         u32 pp;
2174         i915_reg_t pp_ctrl_reg;
2175
2176         if (!is_edp(intel_dp))
2177                 return;
2178
2179         pps_lock(intel_dp);
2180
2181         pp = ironlake_get_pp_control(intel_dp);
2182         pp &= ~EDP_BLC_ENABLE;
2183
2184         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2185
2186         I915_WRITE(pp_ctrl_reg, pp);
2187         POSTING_READ(pp_ctrl_reg);
2188
2189         pps_unlock(intel_dp);
2190
2191         intel_dp->last_backlight_off = jiffies;
2192         edp_wait_backlight_off(intel_dp);
2193 }
2194
2195 /* Disable backlight PP control and backlight PWM. */
2196 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2197 {
2198         if (!is_edp(intel_dp))
2199                 return;
2200
2201         DRM_DEBUG_KMS("\n");
2202
2203         _intel_edp_backlight_off(intel_dp);
2204         intel_panel_disable_backlight(intel_dp->attached_connector);
2205 }
2206
2207 /*
2208  * Hook for controlling the panel power control backlight through the bl_power
2209  * sysfs attribute. Take care to handle multiple calls.
2210  */
2211 static void intel_edp_backlight_power(struct intel_connector *connector,
2212                                       bool enable)
2213 {
2214         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2215         bool is_enabled;
2216
2217         pps_lock(intel_dp);
2218         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2219         pps_unlock(intel_dp);
2220
2221         if (is_enabled == enable)
2222                 return;
2223
2224         DRM_DEBUG_KMS("panel power control backlight %s\n",
2225                       enable ? "enable" : "disable");
2226
2227         if (enable)
2228                 _intel_edp_backlight_on(intel_dp);
2229         else
2230                 _intel_edp_backlight_off(intel_dp);
2231 }
2232
2233 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2234 {
2235         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2236         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2237         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2238
2239         I915_STATE_WARN(cur_state != state,
2240                         "DP port %c state assertion failure (expected %s, current %s)\n",
2241                         port_name(dig_port->port),
2242                         onoff(state), onoff(cur_state));
2243 }
2244 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2245
2246 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2247 {
2248         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2249
2250         I915_STATE_WARN(cur_state != state,
2251                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2252                         onoff(state), onoff(cur_state));
2253 }
2254 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2255 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2256
2257 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2258 {
2259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2260         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2261         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2262
2263         assert_pipe_disabled(dev_priv, crtc->pipe);
2264         assert_dp_port_disabled(intel_dp);
2265         assert_edp_pll_disabled(dev_priv);
2266
2267         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2268                       crtc->config->port_clock);
2269
2270         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2271
2272         if (crtc->config->port_clock == 162000)
2273                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2274         else
2275                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2276
2277         I915_WRITE(DP_A, intel_dp->DP);
2278         POSTING_READ(DP_A);
2279         udelay(500);
2280
2281         /*
2282          * [DevILK] Work around required when enabling DP PLL
2283          * while a pipe is enabled going to FDI:
2284          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2285          * 2. Program DP PLL enable
2286          */
2287         if (IS_GEN5(dev_priv))
2288                 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
2289
2290         intel_dp->DP |= DP_PLL_ENABLE;
2291
2292         I915_WRITE(DP_A, intel_dp->DP);
2293         POSTING_READ(DP_A);
2294         udelay(200);
2295 }
2296
2297 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2298 {
2299         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2300         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2301         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2302
2303         assert_pipe_disabled(dev_priv, crtc->pipe);
2304         assert_dp_port_disabled(intel_dp);
2305         assert_edp_pll_enabled(dev_priv);
2306
2307         DRM_DEBUG_KMS("disabling eDP PLL\n");
2308
2309         intel_dp->DP &= ~DP_PLL_ENABLE;
2310
2311         I915_WRITE(DP_A, intel_dp->DP);
2312         POSTING_READ(DP_A);
2313         udelay(200);
2314 }
2315
2316 /* If the sink supports it, try to set the power state appropriately */
2317 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2318 {
2319         int ret, i;
2320
2321         /* Should have a valid DPCD by this point */
2322         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2323                 return;
2324
2325         if (mode != DRM_MODE_DPMS_ON) {
2326                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2327                                          DP_SET_POWER_D3);
2328         } else {
2329                 /*
2330                  * When turning on, we need to retry for 1ms to give the sink
2331                  * time to wake up.
2332                  */
2333                 for (i = 0; i < 3; i++) {
2334                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2335                                                  DP_SET_POWER_D0);
2336                         if (ret == 1)
2337                                 break;
2338                         msleep(1);
2339                 }
2340         }
2341
2342         if (ret != 1)
2343                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2344                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2345 }
2346
2347 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2348                                   enum pipe *pipe)
2349 {
2350         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2351         enum port port = dp_to_dig_port(intel_dp)->port;
2352         struct drm_device *dev = encoder->base.dev;
2353         struct drm_i915_private *dev_priv = to_i915(dev);
2354         enum intel_display_power_domain power_domain;
2355         u32 tmp;
2356         bool ret;
2357
2358         power_domain = intel_display_port_power_domain(encoder);
2359         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2360                 return false;
2361
2362         ret = false;
2363
2364         tmp = I915_READ(intel_dp->output_reg);
2365
2366         if (!(tmp & DP_PORT_EN))
2367                 goto out;
2368
2369         if (IS_GEN7(dev) && port == PORT_A) {
2370                 *pipe = PORT_TO_PIPE_CPT(tmp);
2371         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2372                 enum pipe p;
2373
2374                 for_each_pipe(dev_priv, p) {
2375                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2376                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2377                                 *pipe = p;
2378                                 ret = true;
2379
2380                                 goto out;
2381                         }
2382                 }
2383
2384                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2385                               i915_mmio_reg_offset(intel_dp->output_reg));
2386         } else if (IS_CHERRYVIEW(dev)) {
2387                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2388         } else {
2389                 *pipe = PORT_TO_PIPE(tmp);
2390         }
2391
2392         ret = true;
2393
2394 out:
2395         intel_display_power_put(dev_priv, power_domain);
2396
2397         return ret;
2398 }
2399
2400 static void intel_dp_get_config(struct intel_encoder *encoder,
2401                                 struct intel_crtc_state *pipe_config)
2402 {
2403         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2404         u32 tmp, flags = 0;
2405         struct drm_device *dev = encoder->base.dev;
2406         struct drm_i915_private *dev_priv = to_i915(dev);
2407         enum port port = dp_to_dig_port(intel_dp)->port;
2408         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2409
2410         tmp = I915_READ(intel_dp->output_reg);
2411
2412         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2413
2414         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2415                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2416
2417                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2418                         flags |= DRM_MODE_FLAG_PHSYNC;
2419                 else
2420                         flags |= DRM_MODE_FLAG_NHSYNC;
2421
2422                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2423                         flags |= DRM_MODE_FLAG_PVSYNC;
2424                 else
2425                         flags |= DRM_MODE_FLAG_NVSYNC;
2426         } else {
2427                 if (tmp & DP_SYNC_HS_HIGH)
2428                         flags |= DRM_MODE_FLAG_PHSYNC;
2429                 else
2430                         flags |= DRM_MODE_FLAG_NHSYNC;
2431
2432                 if (tmp & DP_SYNC_VS_HIGH)
2433                         flags |= DRM_MODE_FLAG_PVSYNC;
2434                 else
2435                         flags |= DRM_MODE_FLAG_NVSYNC;
2436         }
2437
2438         pipe_config->base.adjusted_mode.flags |= flags;
2439
2440         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2441             !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2442                 pipe_config->limited_color_range = true;
2443
2444         pipe_config->lane_count =
2445                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2446
2447         intel_dp_get_m_n(crtc, pipe_config);
2448
2449         if (port == PORT_A) {
2450                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2451                         pipe_config->port_clock = 162000;
2452                 else
2453                         pipe_config->port_clock = 270000;
2454         }
2455
2456         pipe_config->base.adjusted_mode.crtc_clock =
2457                 intel_dotclock_calculate(pipe_config->port_clock,
2458                                          &pipe_config->dp_m_n);
2459
2460         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2461             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2462                 /*
2463                  * This is a big fat ugly hack.
2464                  *
2465                  * Some machines in UEFI boot mode provide us a VBT that has 18
2466                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2467                  * unknown we fail to light up. Yet the same BIOS boots up with
2468                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2469                  * max, not what it tells us to use.
2470                  *
2471                  * Note: This will still be broken if the eDP panel is not lit
2472                  * up by the BIOS, and thus we can't get the mode at module
2473                  * load.
2474                  */
2475                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2476                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2477                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2478         }
2479 }
2480
2481 static void intel_disable_dp(struct intel_encoder *encoder)
2482 {
2483         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2484         struct drm_device *dev = encoder->base.dev;
2485         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2486
2487         if (crtc->config->has_audio)
2488                 intel_audio_codec_disable(encoder);
2489
2490         if (HAS_PSR(dev) && !HAS_DDI(dev))
2491                 intel_psr_disable(intel_dp);
2492
2493         /* Make sure the panel is off before trying to change the mode. But also
2494          * ensure that we have vdd while we switch off the panel. */
2495         intel_edp_panel_vdd_on(intel_dp);
2496         intel_edp_backlight_off(intel_dp);
2497         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2498         intel_edp_panel_off(intel_dp);
2499
2500         /* disable the port before the pipe on g4x */
2501         if (INTEL_INFO(dev)->gen < 5)
2502                 intel_dp_link_down(intel_dp);
2503 }
2504
2505 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2506 {
2507         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2508         enum port port = dp_to_dig_port(intel_dp)->port;
2509
2510         intel_dp_link_down(intel_dp);
2511
2512         /* Only ilk+ has port A */
2513         if (port == PORT_A)
2514                 ironlake_edp_pll_off(intel_dp);
2515 }
2516
2517 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2518 {
2519         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2520
2521         intel_dp_link_down(intel_dp);
2522 }
2523
2524 static void chv_post_disable_dp(struct intel_encoder *encoder)
2525 {
2526         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2527         struct drm_device *dev = encoder->base.dev;
2528         struct drm_i915_private *dev_priv = to_i915(dev);
2529
2530         intel_dp_link_down(intel_dp);
2531
2532         mutex_lock(&dev_priv->sb_lock);
2533
2534         /* Assert data lane reset */
2535         chv_data_lane_soft_reset(encoder, true);
2536
2537         mutex_unlock(&dev_priv->sb_lock);
2538 }
2539
2540 static void
2541 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2542                          uint32_t *DP,
2543                          uint8_t dp_train_pat)
2544 {
2545         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2546         struct drm_device *dev = intel_dig_port->base.base.dev;
2547         struct drm_i915_private *dev_priv = to_i915(dev);
2548         enum port port = intel_dig_port->port;
2549
2550         if (HAS_DDI(dev)) {
2551                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2552
2553                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2554                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2555                 else
2556                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2557
2558                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2559                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2560                 case DP_TRAINING_PATTERN_DISABLE:
2561                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2562
2563                         break;
2564                 case DP_TRAINING_PATTERN_1:
2565                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2566                         break;
2567                 case DP_TRAINING_PATTERN_2:
2568                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2569                         break;
2570                 case DP_TRAINING_PATTERN_3:
2571                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2572                         break;
2573                 }
2574                 I915_WRITE(DP_TP_CTL(port), temp);
2575
2576         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2577                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2578                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2579
2580                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2581                 case DP_TRAINING_PATTERN_DISABLE:
2582                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2583                         break;
2584                 case DP_TRAINING_PATTERN_1:
2585                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2586                         break;
2587                 case DP_TRAINING_PATTERN_2:
2588                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2589                         break;
2590                 case DP_TRAINING_PATTERN_3:
2591                         DRM_ERROR("DP training pattern 3 not supported\n");
2592                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2593                         break;
2594                 }
2595
2596         } else {
2597                 if (IS_CHERRYVIEW(dev))
2598                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2599                 else
2600                         *DP &= ~DP_LINK_TRAIN_MASK;
2601
2602                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2603                 case DP_TRAINING_PATTERN_DISABLE:
2604                         *DP |= DP_LINK_TRAIN_OFF;
2605                         break;
2606                 case DP_TRAINING_PATTERN_1:
2607                         *DP |= DP_LINK_TRAIN_PAT_1;
2608                         break;
2609                 case DP_TRAINING_PATTERN_2:
2610                         *DP |= DP_LINK_TRAIN_PAT_2;
2611                         break;
2612                 case DP_TRAINING_PATTERN_3:
2613                         if (IS_CHERRYVIEW(dev)) {
2614                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2615                         } else {
2616                                 DRM_ERROR("DP training pattern 3 not supported\n");
2617                                 *DP |= DP_LINK_TRAIN_PAT_2;
2618                         }
2619                         break;
2620                 }
2621         }
2622 }
2623
2624 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2625 {
2626         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2627         struct drm_i915_private *dev_priv = to_i915(dev);
2628         struct intel_crtc *crtc =
2629                 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2630
2631         /* enable with pattern 1 (as per spec) */
2632         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2633                                  DP_TRAINING_PATTERN_1);
2634
2635         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2636         POSTING_READ(intel_dp->output_reg);
2637
2638         /*
2639          * Magic for VLV/CHV. We _must_ first set up the register
2640          * without actually enabling the port, and then do another
2641          * write to enable the port. Otherwise link training will
2642          * fail when the power sequencer is freshly used for this port.
2643          */
2644         intel_dp->DP |= DP_PORT_EN;
2645         if (crtc->config->has_audio)
2646                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2647
2648         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2649         POSTING_READ(intel_dp->output_reg);
2650 }
2651
2652 static void intel_enable_dp(struct intel_encoder *encoder)
2653 {
2654         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2655         struct drm_device *dev = encoder->base.dev;
2656         struct drm_i915_private *dev_priv = to_i915(dev);
2657         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2658         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2659         enum pipe pipe = crtc->pipe;
2660
2661         if (WARN_ON(dp_reg & DP_PORT_EN))
2662                 return;
2663
2664         pps_lock(intel_dp);
2665
2666         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2667                 vlv_init_panel_power_sequencer(intel_dp);
2668
2669         intel_dp_enable_port(intel_dp);
2670
2671         edp_panel_vdd_on(intel_dp);
2672         edp_panel_on(intel_dp);
2673         edp_panel_vdd_off(intel_dp, true);
2674
2675         pps_unlock(intel_dp);
2676
2677         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2678                 unsigned int lane_mask = 0x0;
2679
2680                 if (IS_CHERRYVIEW(dev))
2681                         lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2682
2683                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2684                                     lane_mask);
2685         }
2686
2687         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2688         intel_dp_start_link_train(intel_dp);
2689         intel_dp_stop_link_train(intel_dp);
2690
2691         if (crtc->config->has_audio) {
2692                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2693                                  pipe_name(pipe));
2694                 intel_audio_codec_enable(encoder);
2695         }
2696 }
2697
2698 static void g4x_enable_dp(struct intel_encoder *encoder)
2699 {
2700         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2701
2702         intel_enable_dp(encoder);
2703         intel_edp_backlight_on(intel_dp);
2704 }
2705
2706 static void vlv_enable_dp(struct intel_encoder *encoder)
2707 {
2708         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2709
2710         intel_edp_backlight_on(intel_dp);
2711         intel_psr_enable(intel_dp);
2712 }
2713
2714 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2715 {
2716         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2717         enum port port = dp_to_dig_port(intel_dp)->port;
2718
2719         intel_dp_prepare(encoder);
2720
2721         /* Only ilk+ has port A */
2722         if (port == PORT_A)
2723                 ironlake_edp_pll_on(intel_dp);
2724 }
2725
2726 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2727 {
2728         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2729         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2730         enum pipe pipe = intel_dp->pps_pipe;
2731         i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2732
2733         edp_panel_vdd_off_sync(intel_dp);
2734
2735         /*
2736          * VLV seems to get confused when multiple power seqeuencers
2737          * have the same port selected (even if only one has power/vdd
2738          * enabled). The failure manifests as vlv_wait_port_ready() failing
2739          * CHV on the other hand doesn't seem to mind having the same port
2740          * selected in multiple power seqeuencers, but let's clear the
2741          * port select always when logically disconnecting a power sequencer
2742          * from a port.
2743          */
2744         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2745                       pipe_name(pipe), port_name(intel_dig_port->port));
2746         I915_WRITE(pp_on_reg, 0);
2747         POSTING_READ(pp_on_reg);
2748
2749         intel_dp->pps_pipe = INVALID_PIPE;
2750 }
2751
2752 static void vlv_steal_power_sequencer(struct drm_device *dev,
2753                                       enum pipe pipe)
2754 {
2755         struct drm_i915_private *dev_priv = to_i915(dev);
2756         struct intel_encoder *encoder;
2757
2758         lockdep_assert_held(&dev_priv->pps_mutex);
2759
2760         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2761                 return;
2762
2763         for_each_intel_encoder(dev, encoder) {
2764                 struct intel_dp *intel_dp;
2765                 enum port port;
2766
2767                 if (encoder->type != INTEL_OUTPUT_EDP)
2768                         continue;
2769
2770                 intel_dp = enc_to_intel_dp(&encoder->base);
2771                 port = dp_to_dig_port(intel_dp)->port;
2772
2773                 if (intel_dp->pps_pipe != pipe)
2774                         continue;
2775
2776                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2777                               pipe_name(pipe), port_name(port));
2778
2779                 WARN(encoder->base.crtc,
2780                      "stealing pipe %c power sequencer from active eDP port %c\n",
2781                      pipe_name(pipe), port_name(port));
2782
2783                 /* make sure vdd is off before we steal it */
2784                 vlv_detach_power_sequencer(intel_dp);
2785         }
2786 }
2787
2788 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2789 {
2790         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2791         struct intel_encoder *encoder = &intel_dig_port->base;
2792         struct drm_device *dev = encoder->base.dev;
2793         struct drm_i915_private *dev_priv = to_i915(dev);
2794         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2795
2796         lockdep_assert_held(&dev_priv->pps_mutex);
2797
2798         if (!is_edp(intel_dp))
2799                 return;
2800
2801         if (intel_dp->pps_pipe == crtc->pipe)
2802                 return;
2803
2804         /*
2805          * If another power sequencer was being used on this
2806          * port previously make sure to turn off vdd there while
2807          * we still have control of it.
2808          */
2809         if (intel_dp->pps_pipe != INVALID_PIPE)
2810                 vlv_detach_power_sequencer(intel_dp);
2811
2812         /*
2813          * We may be stealing the power
2814          * sequencer from another port.
2815          */
2816         vlv_steal_power_sequencer(dev, crtc->pipe);
2817
2818         /* now it's all ours */
2819         intel_dp->pps_pipe = crtc->pipe;
2820
2821         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2822                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2823
2824         /* init power sequencer on this pipe and port */
2825         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2826         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2827 }
2828
2829 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2830 {
2831         vlv_phy_pre_encoder_enable(encoder);
2832
2833         intel_enable_dp(encoder);
2834 }
2835
2836 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2837 {
2838         intel_dp_prepare(encoder);
2839
2840         vlv_phy_pre_pll_enable(encoder);
2841 }
2842
2843 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2844 {
2845         chv_phy_pre_encoder_enable(encoder);
2846
2847         intel_enable_dp(encoder);
2848
2849         /* Second common lane will stay alive on its own now */
2850         chv_phy_release_cl2_override(encoder);
2851 }
2852
2853 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2854 {
2855         intel_dp_prepare(encoder);
2856
2857         chv_phy_pre_pll_enable(encoder);
2858 }
2859
2860 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
2861 {
2862         chv_phy_post_pll_disable(encoder);
2863 }
2864
2865 /*
2866  * Fetch AUX CH registers 0x202 - 0x207 which contain
2867  * link status information
2868  */
2869 bool
2870 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2871 {
2872         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2873                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2874 }
2875
2876 /* These are source-specific values. */
2877 uint8_t
2878 intel_dp_voltage_max(struct intel_dp *intel_dp)
2879 {
2880         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2881         struct drm_i915_private *dev_priv = to_i915(dev);
2882         enum port port = dp_to_dig_port(intel_dp)->port;
2883
2884         if (IS_BROXTON(dev))
2885                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2886         else if (INTEL_INFO(dev)->gen >= 9) {
2887                 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2888                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2889                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2890         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2891                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2892         else if (IS_GEN7(dev) && port == PORT_A)
2893                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2894         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2895                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2896         else
2897                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2898 }
2899
2900 uint8_t
2901 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2902 {
2903         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2904         enum port port = dp_to_dig_port(intel_dp)->port;
2905
2906         if (INTEL_INFO(dev)->gen >= 9) {
2907                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2908                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2909                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2910                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2911                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2912                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2913                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2914                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2915                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2916                 default:
2917                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2918                 }
2919         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2920                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2921                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2922                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2923                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2924                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2925                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2926                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2927                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2928                 default:
2929                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2930                 }
2931         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2932                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2933                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2934                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2935                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2936                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2937                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2938                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2939                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2940                 default:
2941                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2942                 }
2943         } else if (IS_GEN7(dev) && port == PORT_A) {
2944                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2945                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2946                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2947                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2948                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2949                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2950                 default:
2951                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2952                 }
2953         } else {
2954                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2955                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2956                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2957                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2958                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2959                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2960                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2961                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2962                 default:
2963                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2964                 }
2965         }
2966 }
2967
2968 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
2969 {
2970         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2971         unsigned long demph_reg_value, preemph_reg_value,
2972                 uniqtranscale_reg_value;
2973         uint8_t train_set = intel_dp->train_set[0];
2974
2975         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2976         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2977                 preemph_reg_value = 0x0004000;
2978                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2979                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2980                         demph_reg_value = 0x2B405555;
2981                         uniqtranscale_reg_value = 0x552AB83A;
2982                         break;
2983                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2984                         demph_reg_value = 0x2B404040;
2985                         uniqtranscale_reg_value = 0x5548B83A;
2986                         break;
2987                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2988                         demph_reg_value = 0x2B245555;
2989                         uniqtranscale_reg_value = 0x5560B83A;
2990                         break;
2991                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2992                         demph_reg_value = 0x2B405555;
2993                         uniqtranscale_reg_value = 0x5598DA3A;
2994                         break;
2995                 default:
2996                         return 0;
2997                 }
2998                 break;
2999         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3000                 preemph_reg_value = 0x0002000;
3001                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3002                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3003                         demph_reg_value = 0x2B404040;
3004                         uniqtranscale_reg_value = 0x5552B83A;
3005                         break;
3006                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3007                         demph_reg_value = 0x2B404848;
3008                         uniqtranscale_reg_value = 0x5580B83A;
3009                         break;
3010                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3011                         demph_reg_value = 0x2B404040;
3012                         uniqtranscale_reg_value = 0x55ADDA3A;
3013                         break;
3014                 default:
3015                         return 0;
3016                 }
3017                 break;
3018         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3019                 preemph_reg_value = 0x0000000;
3020                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3021                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3022                         demph_reg_value = 0x2B305555;
3023                         uniqtranscale_reg_value = 0x5570B83A;
3024                         break;
3025                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3026                         demph_reg_value = 0x2B2B4040;
3027                         uniqtranscale_reg_value = 0x55ADDA3A;
3028                         break;
3029                 default:
3030                         return 0;
3031                 }
3032                 break;
3033         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3034                 preemph_reg_value = 0x0006000;
3035                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3036                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3037                         demph_reg_value = 0x1B405555;
3038                         uniqtranscale_reg_value = 0x55ADDA3A;
3039                         break;
3040                 default:
3041                         return 0;
3042                 }
3043                 break;
3044         default:
3045                 return 0;
3046         }
3047
3048         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3049                                  uniqtranscale_reg_value, 0);
3050
3051         return 0;
3052 }
3053
3054 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3055 {
3056         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3057         u32 deemph_reg_value, margin_reg_value;
3058         bool uniq_trans_scale = false;
3059         uint8_t train_set = intel_dp->train_set[0];
3060
3061         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3062         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3063                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3064                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3065                         deemph_reg_value = 128;
3066                         margin_reg_value = 52;
3067                         break;
3068                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3069                         deemph_reg_value = 128;
3070                         margin_reg_value = 77;
3071                         break;
3072                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3073                         deemph_reg_value = 128;
3074                         margin_reg_value = 102;
3075                         break;
3076                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3077                         deemph_reg_value = 128;
3078                         margin_reg_value = 154;
3079                         uniq_trans_scale = true;
3080                         break;
3081                 default:
3082                         return 0;
3083                 }
3084                 break;
3085         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3086                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3087                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3088                         deemph_reg_value = 85;
3089                         margin_reg_value = 78;
3090                         break;
3091                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3092                         deemph_reg_value = 85;
3093                         margin_reg_value = 116;
3094                         break;
3095                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3096                         deemph_reg_value = 85;
3097                         margin_reg_value = 154;
3098                         break;
3099                 default:
3100                         return 0;
3101                 }
3102                 break;
3103         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3104                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3105                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3106                         deemph_reg_value = 64;
3107                         margin_reg_value = 104;
3108                         break;
3109                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3110                         deemph_reg_value = 64;
3111                         margin_reg_value = 154;
3112                         break;
3113                 default:
3114                         return 0;
3115                 }
3116                 break;
3117         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3118                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3119                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3120                         deemph_reg_value = 43;
3121                         margin_reg_value = 154;
3122                         break;
3123                 default:
3124                         return 0;
3125                 }
3126                 break;
3127         default:
3128                 return 0;
3129         }
3130
3131         chv_set_phy_signal_level(encoder, deemph_reg_value,
3132                                  margin_reg_value, uniq_trans_scale);
3133
3134         return 0;
3135 }
3136
3137 static uint32_t
3138 gen4_signal_levels(uint8_t train_set)
3139 {
3140         uint32_t        signal_levels = 0;
3141
3142         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3143         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3144         default:
3145                 signal_levels |= DP_VOLTAGE_0_4;
3146                 break;
3147         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3148                 signal_levels |= DP_VOLTAGE_0_6;
3149                 break;
3150         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3151                 signal_levels |= DP_VOLTAGE_0_8;
3152                 break;
3153         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3154                 signal_levels |= DP_VOLTAGE_1_2;
3155                 break;
3156         }
3157         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3158         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3159         default:
3160                 signal_levels |= DP_PRE_EMPHASIS_0;
3161                 break;
3162         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3163                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3164                 break;
3165         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3166                 signal_levels |= DP_PRE_EMPHASIS_6;
3167                 break;
3168         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3169                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3170                 break;
3171         }
3172         return signal_levels;
3173 }
3174
3175 /* Gen6's DP voltage swing and pre-emphasis control */
3176 static uint32_t
3177 gen6_edp_signal_levels(uint8_t train_set)
3178 {
3179         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3180                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3181         switch (signal_levels) {
3182         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3183         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3184                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3185         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3186                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3187         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3188         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3189                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3190         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3191         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3192                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3193         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3194         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3195                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3196         default:
3197                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3198                               "0x%x\n", signal_levels);
3199                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3200         }
3201 }
3202
3203 /* Gen7's DP voltage swing and pre-emphasis control */
3204 static uint32_t
3205 gen7_edp_signal_levels(uint8_t train_set)
3206 {
3207         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3208                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3209         switch (signal_levels) {
3210         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3211                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3212         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3213                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3214         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3215                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3216
3217         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3218                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3219         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3220                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3221
3222         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3223                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3224         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3225                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3226
3227         default:
3228                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3229                               "0x%x\n", signal_levels);
3230                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3231         }
3232 }
3233
3234 void
3235 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3236 {
3237         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3238         enum port port = intel_dig_port->port;
3239         struct drm_device *dev = intel_dig_port->base.base.dev;
3240         struct drm_i915_private *dev_priv = to_i915(dev);
3241         uint32_t signal_levels, mask = 0;
3242         uint8_t train_set = intel_dp->train_set[0];
3243
3244         if (HAS_DDI(dev)) {
3245                 signal_levels = ddi_signal_levels(intel_dp);
3246
3247                 if (IS_BROXTON(dev))
3248                         signal_levels = 0;
3249                 else
3250                         mask = DDI_BUF_EMP_MASK;
3251         } else if (IS_CHERRYVIEW(dev)) {
3252                 signal_levels = chv_signal_levels(intel_dp);
3253         } else if (IS_VALLEYVIEW(dev)) {
3254                 signal_levels = vlv_signal_levels(intel_dp);
3255         } else if (IS_GEN7(dev) && port == PORT_A) {
3256                 signal_levels = gen7_edp_signal_levels(train_set);
3257                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3258         } else if (IS_GEN6(dev) && port == PORT_A) {
3259                 signal_levels = gen6_edp_signal_levels(train_set);
3260                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3261         } else {
3262                 signal_levels = gen4_signal_levels(train_set);
3263                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3264         }
3265
3266         if (mask)
3267                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3268
3269         DRM_DEBUG_KMS("Using vswing level %d\n",
3270                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3271         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3272                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3273                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3274
3275         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3276
3277         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3278         POSTING_READ(intel_dp->output_reg);
3279 }
3280
3281 void
3282 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3283                                        uint8_t dp_train_pat)
3284 {
3285         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3286         struct drm_i915_private *dev_priv =
3287                 to_i915(intel_dig_port->base.base.dev);
3288
3289         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3290
3291         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3292         POSTING_READ(intel_dp->output_reg);
3293 }
3294
3295 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3296 {
3297         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3298         struct drm_device *dev = intel_dig_port->base.base.dev;
3299         struct drm_i915_private *dev_priv = to_i915(dev);
3300         enum port port = intel_dig_port->port;
3301         uint32_t val;
3302
3303         if (!HAS_DDI(dev))
3304                 return;
3305
3306         val = I915_READ(DP_TP_CTL(port));
3307         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3308         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3309         I915_WRITE(DP_TP_CTL(port), val);
3310
3311         /*
3312          * On PORT_A we can have only eDP in SST mode. There the only reason
3313          * we need to set idle transmission mode is to work around a HW issue
3314          * where we enable the pipe while not in idle link-training mode.
3315          * In this case there is requirement to wait for a minimum number of
3316          * idle patterns to be sent.
3317          */
3318         if (port == PORT_A)
3319                 return;
3320
3321         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3322                                     DP_TP_STATUS_IDLE_DONE,
3323                                     DP_TP_STATUS_IDLE_DONE,
3324                                     1))
3325                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3326 }
3327
3328 static void
3329 intel_dp_link_down(struct intel_dp *intel_dp)
3330 {
3331         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3332         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3333         enum port port = intel_dig_port->port;
3334         struct drm_device *dev = intel_dig_port->base.base.dev;
3335         struct drm_i915_private *dev_priv = to_i915(dev);
3336         uint32_t DP = intel_dp->DP;
3337
3338         if (WARN_ON(HAS_DDI(dev)))
3339                 return;
3340
3341         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3342                 return;
3343
3344         DRM_DEBUG_KMS("\n");
3345
3346         if ((IS_GEN7(dev) && port == PORT_A) ||
3347             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3348                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3349                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3350         } else {
3351                 if (IS_CHERRYVIEW(dev))
3352                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3353                 else
3354                         DP &= ~DP_LINK_TRAIN_MASK;
3355                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3356         }
3357         I915_WRITE(intel_dp->output_reg, DP);
3358         POSTING_READ(intel_dp->output_reg);
3359
3360         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3361         I915_WRITE(intel_dp->output_reg, DP);
3362         POSTING_READ(intel_dp->output_reg);
3363
3364         /*
3365          * HW workaround for IBX, we need to move the port
3366          * to transcoder A after disabling it to allow the
3367          * matching HDMI port to be enabled on transcoder A.
3368          */
3369         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3370                 /*
3371                  * We get CPU/PCH FIFO underruns on the other pipe when
3372                  * doing the workaround. Sweep them under the rug.
3373                  */
3374                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3375                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3376
3377                 /* always enable with pattern 1 (as per spec) */
3378                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3379                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3380                 I915_WRITE(intel_dp->output_reg, DP);
3381                 POSTING_READ(intel_dp->output_reg);
3382
3383                 DP &= ~DP_PORT_EN;
3384                 I915_WRITE(intel_dp->output_reg, DP);
3385                 POSTING_READ(intel_dp->output_reg);
3386
3387                 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
3388                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3389                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3390         }
3391
3392         msleep(intel_dp->panel_power_down_delay);
3393
3394         intel_dp->DP = DP;
3395 }
3396
3397 static bool
3398 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3399 {
3400         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3401         struct drm_device *dev = dig_port->base.base.dev;
3402         struct drm_i915_private *dev_priv = to_i915(dev);
3403
3404         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3405                              sizeof(intel_dp->dpcd)) < 0)
3406                 return false; /* aux transfer failed */
3407
3408         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3409
3410         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3411                 return false; /* DPCD not present */
3412
3413         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3414                              &intel_dp->sink_count, 1) < 0)
3415                 return false;
3416
3417         /*
3418          * Sink count can change between short pulse hpd hence
3419          * a member variable in intel_dp will track any changes
3420          * between short pulse interrupts.
3421          */
3422         intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3423
3424         /*
3425          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3426          * a dongle is present but no display. Unless we require to know
3427          * if a dongle is present or not, we don't need to update
3428          * downstream port information. So, an early return here saves
3429          * time from performing other operations which are not required.
3430          */
3431         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3432                 return false;
3433
3434         /* Check if the panel supports PSR */
3435         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3436         if (is_edp(intel_dp)) {
3437                 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3438                                  intel_dp->psr_dpcd,
3439                                  sizeof(intel_dp->psr_dpcd));
3440                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3441                         dev_priv->psr.sink_support = true;
3442                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3443                 }
3444
3445                 if (INTEL_INFO(dev)->gen >= 9 &&
3446                         (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3447                         uint8_t frame_sync_cap;
3448
3449                         dev_priv->psr.sink_support = true;
3450                         drm_dp_dpcd_read(&intel_dp->aux,
3451                                          DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3452                                          &frame_sync_cap, 1);
3453                         dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3454                         /* PSR2 needs frame sync as well */
3455                         dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3456                         DRM_DEBUG_KMS("PSR2 %s on sink",
3457                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
3458                 }
3459
3460                 /* Read the eDP Display control capabilities registers */
3461                 memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
3462                 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3463                                 (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3464                                                 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3465                                                                 sizeof(intel_dp->edp_dpcd)))
3466                         DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3467                                         intel_dp->edp_dpcd);
3468         }
3469
3470         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3471                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
3472                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
3473
3474         /* Intermediate frequency support */
3475         if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
3476                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3477                 int i;
3478
3479                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3480                                 sink_rates, sizeof(sink_rates));
3481
3482                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3483                         int val = le16_to_cpu(sink_rates[i]);
3484
3485                         if (val == 0)
3486                                 break;
3487
3488                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3489                         intel_dp->sink_rates[i] = (val * 200) / 10;
3490                 }
3491                 intel_dp->num_sink_rates = i;
3492         }
3493
3494         intel_dp_print_rates(intel_dp);
3495
3496         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3497               DP_DWN_STRM_PORT_PRESENT))
3498                 return true; /* native DP sink */
3499
3500         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3501                 return true; /* no per-port downstream info */
3502
3503         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3504                              intel_dp->downstream_ports,
3505                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3506                 return false; /* downstream port status fetch failed */
3507
3508         return true;
3509 }
3510
3511 static void
3512 intel_dp_probe_oui(struct intel_dp *intel_dp)
3513 {
3514         u8 buf[3];
3515
3516         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3517                 return;
3518
3519         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3520                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3521                               buf[0], buf[1], buf[2]);
3522
3523         if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3524                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3525                               buf[0], buf[1], buf[2]);
3526 }
3527
3528 static bool
3529 intel_dp_probe_mst(struct intel_dp *intel_dp)
3530 {
3531         u8 buf[1];
3532
3533         if (!i915.enable_dp_mst)
3534                 return false;
3535
3536         if (!intel_dp->can_mst)
3537                 return false;
3538
3539         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3540                 return false;
3541
3542         if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3543                 if (buf[0] & DP_MST_CAP) {
3544                         DRM_DEBUG_KMS("Sink is MST capable\n");
3545                         intel_dp->is_mst = true;
3546                 } else {
3547                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3548                         intel_dp->is_mst = false;
3549                 }
3550         }
3551
3552         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3553         return intel_dp->is_mst;
3554 }
3555
3556 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3557 {
3558         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3559         struct drm_device *dev = dig_port->base.base.dev;
3560         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3561         u8 buf;
3562         int ret = 0;
3563         int count = 0;
3564         int attempts = 10;
3565
3566         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3567                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3568                 ret = -EIO;
3569                 goto out;
3570         }
3571
3572         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3573                                buf & ~DP_TEST_SINK_START) < 0) {
3574                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3575                 ret = -EIO;
3576                 goto out;
3577         }
3578
3579         do {
3580                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3581
3582                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3583                                       DP_TEST_SINK_MISC, &buf) < 0) {
3584                         ret = -EIO;
3585                         goto out;
3586                 }
3587                 count = buf & DP_TEST_COUNT_MASK;
3588         } while (--attempts && count);
3589
3590         if (attempts == 0) {
3591                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3592                 ret = -ETIMEDOUT;
3593         }
3594
3595  out:
3596         hsw_enable_ips(intel_crtc);
3597         return ret;
3598 }
3599
3600 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3601 {
3602         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3603         struct drm_device *dev = dig_port->base.base.dev;
3604         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3605         u8 buf;
3606         int ret;
3607
3608         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3609                 return -EIO;
3610
3611         if (!(buf & DP_TEST_CRC_SUPPORTED))
3612                 return -ENOTTY;
3613
3614         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3615                 return -EIO;
3616
3617         if (buf & DP_TEST_SINK_START) {
3618                 ret = intel_dp_sink_crc_stop(intel_dp);
3619                 if (ret)
3620                         return ret;
3621         }
3622
3623         hsw_disable_ips(intel_crtc);
3624
3625         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3626                                buf | DP_TEST_SINK_START) < 0) {
3627                 hsw_enable_ips(intel_crtc);
3628                 return -EIO;
3629         }
3630
3631         intel_wait_for_vblank(dev, intel_crtc->pipe);
3632         return 0;
3633 }
3634
3635 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3636 {
3637         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3638         struct drm_device *dev = dig_port->base.base.dev;
3639         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3640         u8 buf;
3641         int count, ret;
3642         int attempts = 6;
3643
3644         ret = intel_dp_sink_crc_start(intel_dp);
3645         if (ret)
3646                 return ret;
3647
3648         do {
3649                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3650
3651                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3652                                       DP_TEST_SINK_MISC, &buf) < 0) {
3653                         ret = -EIO;
3654                         goto stop;
3655                 }
3656                 count = buf & DP_TEST_COUNT_MASK;
3657
3658         } while (--attempts && count == 0);
3659
3660         if (attempts == 0) {
3661                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3662                 ret = -ETIMEDOUT;
3663                 goto stop;
3664         }
3665
3666         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3667                 ret = -EIO;
3668                 goto stop;
3669         }
3670
3671 stop:
3672         intel_dp_sink_crc_stop(intel_dp);
3673         return ret;
3674 }
3675
3676 static bool
3677 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3678 {
3679         return drm_dp_dpcd_read(&intel_dp->aux,
3680                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3681                                        sink_irq_vector, 1) == 1;
3682 }
3683
3684 static bool
3685 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3686 {
3687         int ret;
3688
3689         ret = drm_dp_dpcd_read(&intel_dp->aux,
3690                                              DP_SINK_COUNT_ESI,
3691                                              sink_irq_vector, 14);
3692         if (ret != 14)
3693                 return false;
3694
3695         return true;
3696 }
3697
3698 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3699 {
3700         uint8_t test_result = DP_TEST_ACK;
3701         return test_result;
3702 }
3703
3704 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3705 {
3706         uint8_t test_result = DP_TEST_NAK;
3707         return test_result;
3708 }
3709
3710 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3711 {
3712         uint8_t test_result = DP_TEST_NAK;
3713         struct intel_connector *intel_connector = intel_dp->attached_connector;
3714         struct drm_connector *connector = &intel_connector->base;
3715
3716         if (intel_connector->detect_edid == NULL ||
3717             connector->edid_corrupt ||
3718             intel_dp->aux.i2c_defer_count > 6) {
3719                 /* Check EDID read for NACKs, DEFERs and corruption
3720                  * (DP CTS 1.2 Core r1.1)
3721                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3722                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3723                  *    4.2.2.6 : EDID corruption detected
3724                  * Use failsafe mode for all cases
3725                  */
3726                 if (intel_dp->aux.i2c_nack_count > 0 ||
3727                         intel_dp->aux.i2c_defer_count > 0)
3728                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3729                                       intel_dp->aux.i2c_nack_count,
3730                                       intel_dp->aux.i2c_defer_count);
3731                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3732         } else {
3733                 struct edid *block = intel_connector->detect_edid;
3734
3735                 /* We have to write the checksum
3736                  * of the last block read
3737                  */
3738                 block += intel_connector->detect_edid->extensions;
3739
3740                 if (!drm_dp_dpcd_write(&intel_dp->aux,
3741                                         DP_TEST_EDID_CHECKSUM,
3742                                         &block->checksum,
3743                                         1))
3744                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3745
3746                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3747                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3748         }
3749
3750         /* Set test active flag here so userspace doesn't interrupt things */
3751         intel_dp->compliance_test_active = 1;
3752
3753         return test_result;
3754 }
3755
3756 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3757 {
3758         uint8_t test_result = DP_TEST_NAK;
3759         return test_result;
3760 }
3761
3762 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3763 {
3764         uint8_t response = DP_TEST_NAK;
3765         uint8_t rxdata = 0;
3766         int status = 0;
3767
3768         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3769         if (status <= 0) {
3770                 DRM_DEBUG_KMS("Could not read test request from sink\n");
3771                 goto update_status;
3772         }
3773
3774         switch (rxdata) {
3775         case DP_TEST_LINK_TRAINING:
3776                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3777                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3778                 response = intel_dp_autotest_link_training(intel_dp);
3779                 break;
3780         case DP_TEST_LINK_VIDEO_PATTERN:
3781                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3782                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3783                 response = intel_dp_autotest_video_pattern(intel_dp);
3784                 break;
3785         case DP_TEST_LINK_EDID_READ:
3786                 DRM_DEBUG_KMS("EDID test requested\n");
3787                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3788                 response = intel_dp_autotest_edid(intel_dp);
3789                 break;
3790         case DP_TEST_LINK_PHY_TEST_PATTERN:
3791                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3792                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3793                 response = intel_dp_autotest_phy_pattern(intel_dp);
3794                 break;
3795         default:
3796                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3797                 break;
3798         }
3799
3800 update_status:
3801         status = drm_dp_dpcd_write(&intel_dp->aux,
3802                                    DP_TEST_RESPONSE,
3803                                    &response, 1);
3804         if (status <= 0)
3805                 DRM_DEBUG_KMS("Could not write test response to sink\n");
3806 }
3807
3808 static int
3809 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3810 {
3811         bool bret;
3812
3813         if (intel_dp->is_mst) {
3814                 u8 esi[16] = { 0 };
3815                 int ret = 0;
3816                 int retry;
3817                 bool handled;
3818                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3819 go_again:
3820                 if (bret == true) {
3821
3822                         /* check link status - esi[10] = 0x200c */
3823                         if (intel_dp->active_mst_links &&
3824                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3825                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3826                                 intel_dp_start_link_train(intel_dp);
3827                                 intel_dp_stop_link_train(intel_dp);
3828                         }
3829
3830                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
3831                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3832
3833                         if (handled) {
3834                                 for (retry = 0; retry < 3; retry++) {
3835                                         int wret;
3836                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3837                                                                  DP_SINK_COUNT_ESI+1,
3838                                                                  &esi[1], 3);
3839                                         if (wret == 3) {
3840                                                 break;
3841                                         }
3842                                 }
3843
3844                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3845                                 if (bret == true) {
3846                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3847                                         goto go_again;
3848                                 }
3849                         } else
3850                                 ret = 0;
3851
3852                         return ret;
3853                 } else {
3854                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3855                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3856                         intel_dp->is_mst = false;
3857                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3858                         /* send a hotplug event */
3859                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3860                 }
3861         }
3862         return -EINVAL;
3863 }
3864
3865 static void
3866 intel_dp_check_link_status(struct intel_dp *intel_dp)
3867 {
3868         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3869         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3870         u8 link_status[DP_LINK_STATUS_SIZE];
3871
3872         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3873
3874         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3875                 DRM_ERROR("Failed to get link status\n");
3876                 return;
3877         }
3878
3879         if (!intel_encoder->base.crtc)
3880                 return;
3881
3882         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3883                 return;
3884
3885         /* if link training is requested we should perform it always */
3886         if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3887             (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3888                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3889                               intel_encoder->base.name);
3890                 intel_dp_start_link_train(intel_dp);
3891                 intel_dp_stop_link_train(intel_dp);
3892         }
3893 }
3894
3895 /*
3896  * According to DP spec
3897  * 5.1.2:
3898  *  1. Read DPCD
3899  *  2. Configure link according to Receiver Capabilities
3900  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3901  *  4. Check link status on receipt of hot-plug interrupt
3902  *
3903  * intel_dp_short_pulse -  handles short pulse interrupts
3904  * when full detection is not required.
3905  * Returns %true if short pulse is handled and full detection
3906  * is NOT required and %false otherwise.
3907  */
3908 static bool
3909 intel_dp_short_pulse(struct intel_dp *intel_dp)
3910 {
3911         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3912         u8 sink_irq_vector;
3913         u8 old_sink_count = intel_dp->sink_count;
3914         bool ret;
3915
3916         /*
3917          * Clearing compliance test variables to allow capturing
3918          * of values for next automated test request.
3919          */
3920         intel_dp->compliance_test_active = 0;
3921         intel_dp->compliance_test_type = 0;
3922         intel_dp->compliance_test_data = 0;
3923
3924         /*
3925          * Now read the DPCD to see if it's actually running
3926          * If the current value of sink count doesn't match with
3927          * the value that was stored earlier or dpcd read failed
3928          * we need to do full detection
3929          */
3930         ret = intel_dp_get_dpcd(intel_dp);
3931
3932         if ((old_sink_count != intel_dp->sink_count) || !ret) {
3933                 /* No need to proceed if we are going to do full detect */
3934                 return false;
3935         }
3936
3937         /* Try to read the source of the interrupt */
3938         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3939             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3940                 /* Clear interrupt source */
3941                 drm_dp_dpcd_writeb(&intel_dp->aux,
3942                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3943                                    sink_irq_vector);
3944
3945                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3946                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
3947                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3948                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3949         }
3950
3951         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3952         intel_dp_check_link_status(intel_dp);
3953         drm_modeset_unlock(&dev->mode_config.connection_mutex);
3954
3955         return true;
3956 }
3957
3958 /* XXX this is probably wrong for multiple downstream ports */
3959 static enum drm_connector_status
3960 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3961 {
3962         uint8_t *dpcd = intel_dp->dpcd;
3963         uint8_t type;
3964
3965         if (!intel_dp_get_dpcd(intel_dp))
3966                 return connector_status_disconnected;
3967
3968         if (is_edp(intel_dp))
3969                 return connector_status_connected;
3970
3971         /* if there's no downstream port, we're done */
3972         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3973                 return connector_status_connected;
3974
3975         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3976         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3977             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3978
3979                 return intel_dp->sink_count ?
3980                 connector_status_connected : connector_status_disconnected;
3981         }
3982
3983         /* If no HPD, poke DDC gently */
3984         if (drm_probe_ddc(&intel_dp->aux.ddc))
3985                 return connector_status_connected;
3986
3987         /* Well we tried, say unknown for unreliable port types */
3988         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3989                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3990                 if (type == DP_DS_PORT_TYPE_VGA ||
3991                     type == DP_DS_PORT_TYPE_NON_EDID)
3992                         return connector_status_unknown;
3993         } else {
3994                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3995                         DP_DWN_STRM_PORT_TYPE_MASK;
3996                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3997                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3998                         return connector_status_unknown;
3999         }
4000
4001         /* Anything else is out of spec, warn and ignore */
4002         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4003         return connector_status_disconnected;
4004 }
4005
4006 static enum drm_connector_status
4007 edp_detect(struct intel_dp *intel_dp)
4008 {
4009         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4010         enum drm_connector_status status;
4011
4012         status = intel_panel_detect(dev);
4013         if (status == connector_status_unknown)
4014                 status = connector_status_connected;
4015
4016         return status;
4017 }
4018
4019 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4020                                        struct intel_digital_port *port)
4021 {
4022         u32 bit;
4023
4024         switch (port->port) {
4025         case PORT_A:
4026                 return true;
4027         case PORT_B:
4028                 bit = SDE_PORTB_HOTPLUG;
4029                 break;
4030         case PORT_C:
4031                 bit = SDE_PORTC_HOTPLUG;
4032                 break;
4033         case PORT_D:
4034                 bit = SDE_PORTD_HOTPLUG;
4035                 break;
4036         default:
4037                 MISSING_CASE(port->port);
4038                 return false;
4039         }
4040
4041         return I915_READ(SDEISR) & bit;
4042 }
4043
4044 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4045                                        struct intel_digital_port *port)
4046 {
4047         u32 bit;
4048
4049         switch (port->port) {
4050         case PORT_A:
4051                 return true;
4052         case PORT_B:
4053                 bit = SDE_PORTB_HOTPLUG_CPT;
4054                 break;
4055         case PORT_C:
4056                 bit = SDE_PORTC_HOTPLUG_CPT;
4057                 break;
4058         case PORT_D:
4059                 bit = SDE_PORTD_HOTPLUG_CPT;
4060                 break;
4061         case PORT_E:
4062                 bit = SDE_PORTE_HOTPLUG_SPT;
4063                 break;
4064         default:
4065                 MISSING_CASE(port->port);
4066                 return false;
4067         }
4068
4069         return I915_READ(SDEISR) & bit;
4070 }
4071
4072 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4073                                        struct intel_digital_port *port)
4074 {
4075         u32 bit;
4076
4077         switch (port->port) {
4078         case PORT_B:
4079                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4080                 break;
4081         case PORT_C:
4082                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4083                 break;
4084         case PORT_D:
4085                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4086                 break;
4087         default:
4088                 MISSING_CASE(port->port);
4089                 return false;
4090         }
4091
4092         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4093 }
4094
4095 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4096                                         struct intel_digital_port *port)
4097 {
4098         u32 bit;
4099
4100         switch (port->port) {
4101         case PORT_B:
4102                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4103                 break;
4104         case PORT_C:
4105                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4106                 break;
4107         case PORT_D:
4108                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4109                 break;
4110         default:
4111                 MISSING_CASE(port->port);
4112                 return false;
4113         }
4114
4115         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4116 }
4117
4118 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4119                                        struct intel_digital_port *intel_dig_port)
4120 {
4121         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4122         enum port port;
4123         u32 bit;
4124
4125         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4126         switch (port) {
4127         case PORT_A:
4128                 bit = BXT_DE_PORT_HP_DDIA;
4129                 break;
4130         case PORT_B:
4131                 bit = BXT_DE_PORT_HP_DDIB;
4132                 break;
4133         case PORT_C:
4134                 bit = BXT_DE_PORT_HP_DDIC;
4135                 break;
4136         default:
4137                 MISSING_CASE(port);
4138                 return false;
4139         }
4140
4141         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4142 }
4143
4144 /*
4145  * intel_digital_port_connected - is the specified port connected?
4146  * @dev_priv: i915 private structure
4147  * @port: the port to test
4148  *
4149  * Return %true if @port is connected, %false otherwise.
4150  */
4151 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4152                                          struct intel_digital_port *port)
4153 {
4154         if (HAS_PCH_IBX(dev_priv))
4155                 return ibx_digital_port_connected(dev_priv, port);
4156         else if (HAS_PCH_SPLIT(dev_priv))
4157                 return cpt_digital_port_connected(dev_priv, port);
4158         else if (IS_BROXTON(dev_priv))
4159                 return bxt_digital_port_connected(dev_priv, port);
4160         else if (IS_GM45(dev_priv))
4161                 return gm45_digital_port_connected(dev_priv, port);
4162         else
4163                 return g4x_digital_port_connected(dev_priv, port);
4164 }
4165
4166 static struct edid *
4167 intel_dp_get_edid(struct intel_dp *intel_dp)
4168 {
4169         struct intel_connector *intel_connector = intel_dp->attached_connector;
4170
4171         /* use cached edid if we have one */
4172         if (intel_connector->edid) {
4173                 /* invalid edid */
4174                 if (IS_ERR(intel_connector->edid))
4175                         return NULL;
4176
4177                 return drm_edid_duplicate(intel_connector->edid);
4178         } else
4179                 return drm_get_edid(&intel_connector->base,
4180                                     &intel_dp->aux.ddc);
4181 }
4182
4183 static void
4184 intel_dp_set_edid(struct intel_dp *intel_dp)
4185 {
4186         struct intel_connector *intel_connector = intel_dp->attached_connector;
4187         struct edid *edid;
4188
4189         intel_dp_unset_edid(intel_dp);
4190         edid = intel_dp_get_edid(intel_dp);
4191         intel_connector->detect_edid = edid;
4192
4193         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4194                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4195         else
4196                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4197 }
4198
4199 static void
4200 intel_dp_unset_edid(struct intel_dp *intel_dp)
4201 {
4202         struct intel_connector *intel_connector = intel_dp->attached_connector;
4203
4204         kfree(intel_connector->detect_edid);
4205         intel_connector->detect_edid = NULL;
4206
4207         intel_dp->has_audio = false;
4208 }
4209
4210 static void
4211 intel_dp_long_pulse(struct intel_connector *intel_connector)
4212 {
4213         struct drm_connector *connector = &intel_connector->base;
4214         struct intel_dp *intel_dp = intel_attached_dp(connector);
4215         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4216         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4217         struct drm_device *dev = connector->dev;
4218         enum drm_connector_status status;
4219         enum intel_display_power_domain power_domain;
4220         bool ret;
4221         u8 sink_irq_vector;
4222
4223         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4224         intel_display_power_get(to_i915(dev), power_domain);
4225
4226         /* Can't disconnect eDP, but you can close the lid... */
4227         if (is_edp(intel_dp))
4228                 status = edp_detect(intel_dp);
4229         else if (intel_digital_port_connected(to_i915(dev),
4230                                               dp_to_dig_port(intel_dp)))
4231                 status = intel_dp_detect_dpcd(intel_dp);
4232         else
4233                 status = connector_status_disconnected;
4234
4235         if (status != connector_status_connected) {
4236                 intel_dp->compliance_test_active = 0;
4237                 intel_dp->compliance_test_type = 0;
4238                 intel_dp->compliance_test_data = 0;
4239
4240                 if (intel_dp->is_mst) {
4241                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4242                                       intel_dp->is_mst,
4243                                       intel_dp->mst_mgr.mst_state);
4244                         intel_dp->is_mst = false;
4245                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4246                                                         intel_dp->is_mst);
4247                 }
4248
4249                 goto out;
4250         }
4251
4252         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4253                 intel_encoder->type = INTEL_OUTPUT_DP;
4254
4255         intel_dp_probe_oui(intel_dp);
4256
4257         ret = intel_dp_probe_mst(intel_dp);
4258         if (ret) {
4259                 /*
4260                  * If we are in MST mode then this connector
4261                  * won't appear connected or have anything
4262                  * with EDID on it
4263                  */
4264                 status = connector_status_disconnected;
4265                 goto out;
4266         } else if (connector->status == connector_status_connected) {
4267                 /*
4268                  * If display was connected already and is still connected
4269                  * check links status, there has been known issues of
4270                  * link loss triggerring long pulse!!!!
4271                  */
4272                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4273                 intel_dp_check_link_status(intel_dp);
4274                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4275                 goto out;
4276         }
4277
4278         /*
4279          * Clearing NACK and defer counts to get their exact values
4280          * while reading EDID which are required by Compliance tests
4281          * 4.2.2.4 and 4.2.2.5
4282          */
4283         intel_dp->aux.i2c_nack_count = 0;
4284         intel_dp->aux.i2c_defer_count = 0;
4285
4286         intel_dp_set_edid(intel_dp);
4287
4288         status = connector_status_connected;
4289         intel_dp->detect_done = true;
4290
4291         /* Try to read the source of the interrupt */
4292         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4293             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4294                 /* Clear interrupt source */
4295                 drm_dp_dpcd_writeb(&intel_dp->aux,
4296                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4297                                    sink_irq_vector);
4298
4299                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4300                         intel_dp_handle_test_request(intel_dp);
4301                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4302                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4303         }
4304
4305 out:
4306         if ((status != connector_status_connected) &&
4307             (intel_dp->is_mst == false))
4308                 intel_dp_unset_edid(intel_dp);
4309
4310         intel_display_power_put(to_i915(dev), power_domain);
4311         return;
4312 }
4313
4314 static enum drm_connector_status
4315 intel_dp_detect(struct drm_connector *connector, bool force)
4316 {
4317         struct intel_dp *intel_dp = intel_attached_dp(connector);
4318         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4319         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4320         struct intel_connector *intel_connector = to_intel_connector(connector);
4321
4322         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4323                       connector->base.id, connector->name);
4324
4325         if (intel_dp->is_mst) {
4326                 /* MST devices are disconnected from a monitor POV */
4327                 intel_dp_unset_edid(intel_dp);
4328                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4329                         intel_encoder->type = INTEL_OUTPUT_DP;
4330                 return connector_status_disconnected;
4331         }
4332
4333         /* If full detect is not performed yet, do a full detect */
4334         if (!intel_dp->detect_done)
4335                 intel_dp_long_pulse(intel_dp->attached_connector);
4336
4337         intel_dp->detect_done = false;
4338
4339         if (is_edp(intel_dp) || intel_connector->detect_edid)
4340                 return connector_status_connected;
4341         else
4342                 return connector_status_disconnected;
4343 }
4344
4345 static void
4346 intel_dp_force(struct drm_connector *connector)
4347 {
4348         struct intel_dp *intel_dp = intel_attached_dp(connector);
4349         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4350         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4351         enum intel_display_power_domain power_domain;
4352
4353         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4354                       connector->base.id, connector->name);
4355         intel_dp_unset_edid(intel_dp);
4356
4357         if (connector->status != connector_status_connected)
4358                 return;
4359
4360         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4361         intel_display_power_get(dev_priv, power_domain);
4362
4363         intel_dp_set_edid(intel_dp);
4364
4365         intel_display_power_put(dev_priv, power_domain);
4366
4367         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4368                 intel_encoder->type = INTEL_OUTPUT_DP;
4369 }
4370
4371 static int intel_dp_get_modes(struct drm_connector *connector)
4372 {
4373         struct intel_connector *intel_connector = to_intel_connector(connector);
4374         struct edid *edid;
4375
4376         edid = intel_connector->detect_edid;
4377         if (edid) {
4378                 int ret = intel_connector_update_modes(connector, edid);
4379                 if (ret)
4380                         return ret;
4381         }
4382
4383         /* if eDP has no EDID, fall back to fixed mode */
4384         if (is_edp(intel_attached_dp(connector)) &&
4385             intel_connector->panel.fixed_mode) {
4386                 struct drm_display_mode *mode;
4387
4388                 mode = drm_mode_duplicate(connector->dev,
4389                                           intel_connector->panel.fixed_mode);
4390                 if (mode) {
4391                         drm_mode_probed_add(connector, mode);
4392                         return 1;
4393                 }
4394         }
4395
4396         return 0;
4397 }
4398
4399 static bool
4400 intel_dp_detect_audio(struct drm_connector *connector)
4401 {
4402         bool has_audio = false;
4403         struct edid *edid;
4404
4405         edid = to_intel_connector(connector)->detect_edid;
4406         if (edid)
4407                 has_audio = drm_detect_monitor_audio(edid);
4408
4409         return has_audio;
4410 }
4411
4412 static int
4413 intel_dp_set_property(struct drm_connector *connector,
4414                       struct drm_property *property,
4415                       uint64_t val)
4416 {
4417         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4418         struct intel_connector *intel_connector = to_intel_connector(connector);
4419         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4420         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4421         int ret;
4422
4423         ret = drm_object_property_set_value(&connector->base, property, val);
4424         if (ret)
4425                 return ret;
4426
4427         if (property == dev_priv->force_audio_property) {
4428                 int i = val;
4429                 bool has_audio;
4430
4431                 if (i == intel_dp->force_audio)
4432                         return 0;
4433
4434                 intel_dp->force_audio = i;
4435
4436                 if (i == HDMI_AUDIO_AUTO)
4437                         has_audio = intel_dp_detect_audio(connector);
4438                 else
4439                         has_audio = (i == HDMI_AUDIO_ON);
4440
4441                 if (has_audio == intel_dp->has_audio)
4442                         return 0;
4443
4444                 intel_dp->has_audio = has_audio;
4445                 goto done;
4446         }
4447
4448         if (property == dev_priv->broadcast_rgb_property) {
4449                 bool old_auto = intel_dp->color_range_auto;
4450                 bool old_range = intel_dp->limited_color_range;
4451
4452                 switch (val) {
4453                 case INTEL_BROADCAST_RGB_AUTO:
4454                         intel_dp->color_range_auto = true;
4455                         break;
4456                 case INTEL_BROADCAST_RGB_FULL:
4457                         intel_dp->color_range_auto = false;
4458                         intel_dp->limited_color_range = false;
4459                         break;
4460                 case INTEL_BROADCAST_RGB_LIMITED:
4461                         intel_dp->color_range_auto = false;
4462                         intel_dp->limited_color_range = true;
4463                         break;
4464                 default:
4465                         return -EINVAL;
4466                 }
4467
4468                 if (old_auto == intel_dp->color_range_auto &&
4469                     old_range == intel_dp->limited_color_range)
4470                         return 0;
4471
4472                 goto done;
4473         }
4474
4475         if (is_edp(intel_dp) &&
4476             property == connector->dev->mode_config.scaling_mode_property) {
4477                 if (val == DRM_MODE_SCALE_NONE) {
4478                         DRM_DEBUG_KMS("no scaling not supported\n");
4479                         return -EINVAL;
4480                 }
4481                 if (HAS_GMCH_DISPLAY(dev_priv) &&
4482                     val == DRM_MODE_SCALE_CENTER) {
4483                         DRM_DEBUG_KMS("centering not supported\n");
4484                         return -EINVAL;
4485                 }
4486
4487                 if (intel_connector->panel.fitting_mode == val) {
4488                         /* the eDP scaling property is not changed */
4489                         return 0;
4490                 }
4491                 intel_connector->panel.fitting_mode = val;
4492
4493                 goto done;
4494         }
4495
4496         return -EINVAL;
4497
4498 done:
4499         if (intel_encoder->base.crtc)
4500                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4501
4502         return 0;
4503 }
4504
4505 static int
4506 intel_dp_connector_register(struct drm_connector *connector)
4507 {
4508         struct intel_dp *intel_dp = intel_attached_dp(connector);
4509         int ret;
4510
4511         ret = intel_connector_register(connector);
4512         if (ret)
4513                 return ret;
4514
4515         i915_debugfs_connector_add(connector);
4516
4517         DRM_DEBUG_KMS("registering %s bus for %s\n",
4518                       intel_dp->aux.name, connector->kdev->kobj.name);
4519
4520         intel_dp->aux.dev = connector->kdev;
4521         return drm_dp_aux_register(&intel_dp->aux);
4522 }
4523
4524 static void
4525 intel_dp_connector_unregister(struct drm_connector *connector)
4526 {
4527         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4528         intel_connector_unregister(connector);
4529 }
4530
4531 static void
4532 intel_dp_connector_destroy(struct drm_connector *connector)
4533 {
4534         struct intel_connector *intel_connector = to_intel_connector(connector);
4535
4536         kfree(intel_connector->detect_edid);
4537
4538         if (!IS_ERR_OR_NULL(intel_connector->edid))
4539                 kfree(intel_connector->edid);
4540
4541         /* Can't call is_edp() since the encoder may have been destroyed
4542          * already. */
4543         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4544                 intel_panel_fini(&intel_connector->panel);
4545
4546         drm_connector_cleanup(connector);
4547         kfree(connector);
4548 }
4549
4550 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4551 {
4552         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4553         struct intel_dp *intel_dp = &intel_dig_port->dp;
4554
4555         intel_dp_mst_encoder_cleanup(intel_dig_port);
4556         if (is_edp(intel_dp)) {
4557                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4558                 /*
4559                  * vdd might still be enabled do to the delayed vdd off.
4560                  * Make sure vdd is actually turned off here.
4561                  */
4562                 pps_lock(intel_dp);
4563                 edp_panel_vdd_off_sync(intel_dp);
4564                 pps_unlock(intel_dp);
4565
4566                 if (intel_dp->edp_notifier.notifier_call) {
4567                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4568                         intel_dp->edp_notifier.notifier_call = NULL;
4569                 }
4570         }
4571
4572         intel_dp_aux_fini(intel_dp);
4573
4574         drm_encoder_cleanup(encoder);
4575         kfree(intel_dig_port);
4576 }
4577
4578 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4579 {
4580         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4581
4582         if (!is_edp(intel_dp))
4583                 return;
4584
4585         /*
4586          * vdd might still be enabled do to the delayed vdd off.
4587          * Make sure vdd is actually turned off here.
4588          */
4589         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4590         pps_lock(intel_dp);
4591         edp_panel_vdd_off_sync(intel_dp);
4592         pps_unlock(intel_dp);
4593 }
4594
4595 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4596 {
4597         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4598         struct drm_device *dev = intel_dig_port->base.base.dev;
4599         struct drm_i915_private *dev_priv = to_i915(dev);
4600         enum intel_display_power_domain power_domain;
4601
4602         lockdep_assert_held(&dev_priv->pps_mutex);
4603
4604         if (!edp_have_panel_vdd(intel_dp))
4605                 return;
4606
4607         /*
4608          * The VDD bit needs a power domain reference, so if the bit is
4609          * already enabled when we boot or resume, grab this reference and
4610          * schedule a vdd off, so we don't hold on to the reference
4611          * indefinitely.
4612          */
4613         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4614         power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4615         intel_display_power_get(dev_priv, power_domain);
4616
4617         edp_panel_vdd_schedule_off(intel_dp);
4618 }
4619
4620 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4621 {
4622         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4623         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4624
4625         if (!HAS_DDI(dev_priv))
4626                 intel_dp->DP = I915_READ(intel_dp->output_reg);
4627
4628         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4629                 return;
4630
4631         pps_lock(intel_dp);
4632
4633         /*
4634          * Read out the current power sequencer assignment,
4635          * in case the BIOS did something with it.
4636          */
4637         if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
4638                 vlv_initial_power_sequencer_setup(intel_dp);
4639
4640         intel_edp_panel_vdd_sanitize(intel_dp);
4641
4642         pps_unlock(intel_dp);
4643 }
4644
4645 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4646         .dpms = drm_atomic_helper_connector_dpms,
4647         .detect = intel_dp_detect,
4648         .force = intel_dp_force,
4649         .fill_modes = drm_helper_probe_single_connector_modes,
4650         .set_property = intel_dp_set_property,
4651         .atomic_get_property = intel_connector_atomic_get_property,
4652         .late_register = intel_dp_connector_register,
4653         .early_unregister = intel_dp_connector_unregister,
4654         .destroy = intel_dp_connector_destroy,
4655         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4656         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4657 };
4658
4659 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4660         .get_modes = intel_dp_get_modes,
4661         .mode_valid = intel_dp_mode_valid,
4662 };
4663
4664 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4665         .reset = intel_dp_encoder_reset,
4666         .destroy = intel_dp_encoder_destroy,
4667 };
4668
4669 enum irqreturn
4670 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4671 {
4672         struct intel_dp *intel_dp = &intel_dig_port->dp;
4673         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4674         struct drm_device *dev = intel_dig_port->base.base.dev;
4675         struct drm_i915_private *dev_priv = to_i915(dev);
4676         enum intel_display_power_domain power_domain;
4677         enum irqreturn ret = IRQ_NONE;
4678
4679         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4680             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4681                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
4682
4683         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4684                 /*
4685                  * vdd off can generate a long pulse on eDP which
4686                  * would require vdd on to handle it, and thus we
4687                  * would end up in an endless cycle of
4688                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4689                  */
4690                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4691                               port_name(intel_dig_port->port));
4692                 return IRQ_HANDLED;
4693         }
4694
4695         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4696                       port_name(intel_dig_port->port),
4697                       long_hpd ? "long" : "short");
4698
4699         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4700         intel_display_power_get(dev_priv, power_domain);
4701
4702         if (long_hpd) {
4703                 intel_dp_long_pulse(intel_dp->attached_connector);
4704                 if (intel_dp->is_mst)
4705                         ret = IRQ_HANDLED;
4706                 goto put_power;
4707
4708         } else {
4709                 if (intel_dp->is_mst) {
4710                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4711                                 /*
4712                                  * If we were in MST mode, and device is not
4713                                  * there, get out of MST mode
4714                                  */
4715                                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4716                                               intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4717                                 intel_dp->is_mst = false;
4718                                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4719                                                                 intel_dp->is_mst);
4720                                 goto put_power;
4721                         }
4722                 }
4723
4724                 if (!intel_dp->is_mst) {
4725                         if (!intel_dp_short_pulse(intel_dp)) {
4726                                 intel_dp_long_pulse(intel_dp->attached_connector);
4727                                 goto put_power;
4728                         }
4729                 }
4730         }
4731
4732         ret = IRQ_HANDLED;
4733
4734 put_power:
4735         intel_display_power_put(dev_priv, power_domain);
4736
4737         return ret;
4738 }
4739
4740 /* check the VBT to see whether the eDP is on another port */
4741 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4742 {
4743         struct drm_i915_private *dev_priv = to_i915(dev);
4744
4745         /*
4746          * eDP not supported on g4x. so bail out early just
4747          * for a bit extra safety in case the VBT is bonkers.
4748          */
4749         if (INTEL_INFO(dev)->gen < 5)
4750                 return false;
4751
4752         if (port == PORT_A)
4753                 return true;
4754
4755         return intel_bios_is_port_edp(dev_priv, port);
4756 }
4757
4758 void
4759 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4760 {
4761         struct intel_connector *intel_connector = to_intel_connector(connector);
4762
4763         intel_attach_force_audio_property(connector);
4764         intel_attach_broadcast_rgb_property(connector);
4765         intel_dp->color_range_auto = true;
4766
4767         if (is_edp(intel_dp)) {
4768                 drm_mode_create_scaling_mode_property(connector->dev);
4769                 drm_object_attach_property(
4770                         &connector->base,
4771                         connector->dev->mode_config.scaling_mode_property,
4772                         DRM_MODE_SCALE_ASPECT);
4773                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4774         }
4775 }
4776
4777 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4778 {
4779         intel_dp->panel_power_off_time = ktime_get_boottime();
4780         intel_dp->last_power_on = jiffies;
4781         intel_dp->last_backlight_off = jiffies;
4782 }
4783
4784 static void
4785 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4786                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
4787 {
4788         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4789         struct pps_registers regs;
4790
4791         intel_pps_get_registers(dev_priv, intel_dp, &regs);
4792
4793         /* Workaround: Need to write PP_CONTROL with the unlock key as
4794          * the very first thing. */
4795         pp_ctl = ironlake_get_pp_control(intel_dp);
4796
4797         pp_on = I915_READ(regs.pp_on);
4798         pp_off = I915_READ(regs.pp_off);
4799         if (!IS_BROXTON(dev_priv)) {
4800                 I915_WRITE(regs.pp_ctrl, pp_ctl);
4801                 pp_div = I915_READ(regs.pp_div);
4802         }
4803
4804         /* Pull timing values out of registers */
4805         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4806                      PANEL_POWER_UP_DELAY_SHIFT;
4807
4808         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4809                   PANEL_LIGHT_ON_DELAY_SHIFT;
4810
4811         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4812                   PANEL_LIGHT_OFF_DELAY_SHIFT;
4813
4814         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4815                    PANEL_POWER_DOWN_DELAY_SHIFT;
4816
4817         if (IS_BROXTON(dev_priv)) {
4818                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4819                         BXT_POWER_CYCLE_DELAY_SHIFT;
4820                 if (tmp > 0)
4821                         seq->t11_t12 = (tmp - 1) * 1000;
4822                 else
4823                         seq->t11_t12 = 0;
4824         } else {
4825                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4826                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4827         }
4828 }
4829
4830 static void
4831 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4832 {
4833         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4834                       state_name,
4835                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4836 }
4837
4838 static void
4839 intel_pps_verify_state(struct drm_i915_private *dev_priv,
4840                        struct intel_dp *intel_dp)
4841 {
4842         struct edp_power_seq hw;
4843         struct edp_power_seq *sw = &intel_dp->pps_delays;
4844
4845         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4846
4847         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4848             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4849                 DRM_ERROR("PPS state mismatch\n");
4850                 intel_pps_dump_state("sw", sw);
4851                 intel_pps_dump_state("hw", &hw);
4852         }
4853 }
4854
4855 static void
4856 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4857                                     struct intel_dp *intel_dp)
4858 {
4859         struct drm_i915_private *dev_priv = to_i915(dev);
4860         struct edp_power_seq cur, vbt, spec,
4861                 *final = &intel_dp->pps_delays;
4862
4863         lockdep_assert_held(&dev_priv->pps_mutex);
4864
4865         /* already initialized? */
4866         if (final->t11_t12 != 0)
4867                 return;
4868
4869         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
4870
4871         intel_pps_dump_state("cur", &cur);
4872
4873         vbt = dev_priv->vbt.edp.pps;
4874
4875         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4876          * our hw here, which are all in 100usec. */
4877         spec.t1_t3 = 210 * 10;
4878         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4879         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4880         spec.t10 = 500 * 10;
4881         /* This one is special and actually in units of 100ms, but zero
4882          * based in the hw (so we need to add 100 ms). But the sw vbt
4883          * table multiplies it with 1000 to make it in units of 100usec,
4884          * too. */
4885         spec.t11_t12 = (510 + 100) * 10;
4886
4887         intel_pps_dump_state("vbt", &vbt);
4888
4889         /* Use the max of the register settings and vbt. If both are
4890          * unset, fall back to the spec limits. */
4891 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
4892                                        spec.field : \
4893                                        max(cur.field, vbt.field))
4894         assign_final(t1_t3);
4895         assign_final(t8);
4896         assign_final(t9);
4897         assign_final(t10);
4898         assign_final(t11_t12);
4899 #undef assign_final
4900
4901 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
4902         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4903         intel_dp->backlight_on_delay = get_delay(t8);
4904         intel_dp->backlight_off_delay = get_delay(t9);
4905         intel_dp->panel_power_down_delay = get_delay(t10);
4906         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4907 #undef get_delay
4908
4909         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4910                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4911                       intel_dp->panel_power_cycle_delay);
4912
4913         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4914                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4915
4916         /*
4917          * We override the HW backlight delays to 1 because we do manual waits
4918          * on them. For T8, even BSpec recommends doing it. For T9, if we
4919          * don't do this, we'll end up waiting for the backlight off delay
4920          * twice: once when we do the manual sleep, and once when we disable
4921          * the panel and wait for the PP_STATUS bit to become zero.
4922          */
4923         final->t8 = 1;
4924         final->t9 = 1;
4925 }
4926
4927 static void
4928 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4929                                               struct intel_dp *intel_dp)
4930 {
4931         struct drm_i915_private *dev_priv = to_i915(dev);
4932         u32 pp_on, pp_off, pp_div, port_sel = 0;
4933         int div = dev_priv->rawclk_freq / 1000;
4934         struct pps_registers regs;
4935         enum port port = dp_to_dig_port(intel_dp)->port;
4936         const struct edp_power_seq *seq = &intel_dp->pps_delays;
4937
4938         lockdep_assert_held(&dev_priv->pps_mutex);
4939
4940         intel_pps_get_registers(dev_priv, intel_dp, &regs);
4941
4942         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4943                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
4944         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4945                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4946         /* Compute the divisor for the pp clock, simply match the Bspec
4947          * formula. */
4948         if (IS_BROXTON(dev)) {
4949                 pp_div = I915_READ(regs.pp_ctrl);
4950                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
4951                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
4952                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
4953         } else {
4954                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4955                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4956                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4957         }
4958
4959         /* Haswell doesn't have any port selection bits for the panel
4960          * power sequencer any more. */
4961         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4962                 port_sel = PANEL_PORT_SELECT_VLV(port);
4963         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4964                 if (port == PORT_A)
4965                         port_sel = PANEL_PORT_SELECT_DPA;
4966                 else
4967                         port_sel = PANEL_PORT_SELECT_DPD;
4968         }
4969
4970         pp_on |= port_sel;
4971
4972         I915_WRITE(regs.pp_on, pp_on);
4973         I915_WRITE(regs.pp_off, pp_off);
4974         if (IS_BROXTON(dev))
4975                 I915_WRITE(regs.pp_ctrl, pp_div);
4976         else
4977                 I915_WRITE(regs.pp_div, pp_div);
4978
4979         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4980                       I915_READ(regs.pp_on),
4981                       I915_READ(regs.pp_off),
4982                       IS_BROXTON(dev) ?
4983                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
4984                       I915_READ(regs.pp_div));
4985 }
4986
4987 /**
4988  * intel_dp_set_drrs_state - program registers for RR switch to take effect
4989  * @dev: DRM device
4990  * @refresh_rate: RR to be programmed
4991  *
4992  * This function gets called when refresh rate (RR) has to be changed from
4993  * one frequency to another. Switches can be between high and low RR
4994  * supported by the panel or to any other RR based on media playback (in
4995  * this case, RR value needs to be passed from user space).
4996  *
4997  * The caller of this function needs to take a lock on dev_priv->drrs.
4998  */
4999 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5000 {
5001         struct drm_i915_private *dev_priv = to_i915(dev);
5002         struct intel_encoder *encoder;
5003         struct intel_digital_port *dig_port = NULL;
5004         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5005         struct intel_crtc_state *config = NULL;
5006         struct intel_crtc *intel_crtc = NULL;
5007         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5008
5009         if (refresh_rate <= 0) {
5010                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5011                 return;
5012         }
5013
5014         if (intel_dp == NULL) {
5015                 DRM_DEBUG_KMS("DRRS not supported.\n");
5016                 return;
5017         }
5018
5019         /*
5020          * FIXME: This needs proper synchronization with psr state for some
5021          * platforms that cannot have PSR and DRRS enabled at the same time.
5022          */
5023
5024         dig_port = dp_to_dig_port(intel_dp);
5025         encoder = &dig_port->base;
5026         intel_crtc = to_intel_crtc(encoder->base.crtc);
5027
5028         if (!intel_crtc) {
5029                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5030                 return;
5031         }
5032
5033         config = intel_crtc->config;
5034
5035         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5036                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5037                 return;
5038         }
5039
5040         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5041                         refresh_rate)
5042                 index = DRRS_LOW_RR;
5043
5044         if (index == dev_priv->drrs.refresh_rate_type) {
5045                 DRM_DEBUG_KMS(
5046                         "DRRS requested for previously set RR...ignoring\n");
5047                 return;
5048         }
5049
5050         if (!intel_crtc->active) {
5051                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5052                 return;
5053         }
5054
5055         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5056                 switch (index) {
5057                 case DRRS_HIGH_RR:
5058                         intel_dp_set_m_n(intel_crtc, M1_N1);
5059                         break;
5060                 case DRRS_LOW_RR:
5061                         intel_dp_set_m_n(intel_crtc, M2_N2);
5062                         break;
5063                 case DRRS_MAX_RR:
5064                 default:
5065                         DRM_ERROR("Unsupported refreshrate type\n");
5066                 }
5067         } else if (INTEL_INFO(dev)->gen > 6) {
5068                 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5069                 u32 val;
5070
5071                 val = I915_READ(reg);
5072                 if (index > DRRS_HIGH_RR) {
5073                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5074                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5075                         else
5076                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5077                 } else {
5078                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5079                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5080                         else
5081                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5082                 }
5083                 I915_WRITE(reg, val);
5084         }
5085
5086         dev_priv->drrs.refresh_rate_type = index;
5087
5088         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5089 }
5090
5091 /**
5092  * intel_edp_drrs_enable - init drrs struct if supported
5093  * @intel_dp: DP struct
5094  *
5095  * Initializes frontbuffer_bits and drrs.dp
5096  */
5097 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5098 {
5099         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5100         struct drm_i915_private *dev_priv = to_i915(dev);
5101         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5102         struct drm_crtc *crtc = dig_port->base.base.crtc;
5103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5104
5105         if (!intel_crtc->config->has_drrs) {
5106                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5107                 return;
5108         }
5109
5110         mutex_lock(&dev_priv->drrs.mutex);
5111         if (WARN_ON(dev_priv->drrs.dp)) {
5112                 DRM_ERROR("DRRS already enabled\n");
5113                 goto unlock;
5114         }
5115
5116         dev_priv->drrs.busy_frontbuffer_bits = 0;
5117
5118         dev_priv->drrs.dp = intel_dp;
5119
5120 unlock:
5121         mutex_unlock(&dev_priv->drrs.mutex);
5122 }
5123
5124 /**
5125  * intel_edp_drrs_disable - Disable DRRS
5126  * @intel_dp: DP struct
5127  *
5128  */
5129 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5130 {
5131         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5132         struct drm_i915_private *dev_priv = to_i915(dev);
5133         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5134         struct drm_crtc *crtc = dig_port->base.base.crtc;
5135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5136
5137         if (!intel_crtc->config->has_drrs)
5138                 return;
5139
5140         mutex_lock(&dev_priv->drrs.mutex);
5141         if (!dev_priv->drrs.dp) {
5142                 mutex_unlock(&dev_priv->drrs.mutex);
5143                 return;
5144         }
5145
5146         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5147                 intel_dp_set_drrs_state(&dev_priv->drm,
5148                                         intel_dp->attached_connector->panel.
5149                                         fixed_mode->vrefresh);
5150
5151         dev_priv->drrs.dp = NULL;
5152         mutex_unlock(&dev_priv->drrs.mutex);
5153
5154         cancel_delayed_work_sync(&dev_priv->drrs.work);
5155 }
5156
5157 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5158 {
5159         struct drm_i915_private *dev_priv =
5160                 container_of(work, typeof(*dev_priv), drrs.work.work);
5161         struct intel_dp *intel_dp;
5162
5163         mutex_lock(&dev_priv->drrs.mutex);
5164
5165         intel_dp = dev_priv->drrs.dp;
5166
5167         if (!intel_dp)
5168                 goto unlock;
5169
5170         /*
5171          * The delayed work can race with an invalidate hence we need to
5172          * recheck.
5173          */
5174
5175         if (dev_priv->drrs.busy_frontbuffer_bits)
5176                 goto unlock;
5177
5178         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5179                 intel_dp_set_drrs_state(&dev_priv->drm,
5180                                         intel_dp->attached_connector->panel.
5181                                         downclock_mode->vrefresh);
5182
5183 unlock:
5184         mutex_unlock(&dev_priv->drrs.mutex);
5185 }
5186
5187 /**
5188  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5189  * @dev: DRM device
5190  * @frontbuffer_bits: frontbuffer plane tracking bits
5191  *
5192  * This function gets called everytime rendering on the given planes start.
5193  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5194  *
5195  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5196  */
5197 void intel_edp_drrs_invalidate(struct drm_device *dev,
5198                 unsigned frontbuffer_bits)
5199 {
5200         struct drm_i915_private *dev_priv = to_i915(dev);
5201         struct drm_crtc *crtc;
5202         enum pipe pipe;
5203
5204         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5205                 return;
5206
5207         cancel_delayed_work(&dev_priv->drrs.work);
5208
5209         mutex_lock(&dev_priv->drrs.mutex);
5210         if (!dev_priv->drrs.dp) {
5211                 mutex_unlock(&dev_priv->drrs.mutex);
5212                 return;
5213         }
5214
5215         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5216         pipe = to_intel_crtc(crtc)->pipe;
5217
5218         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5219         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5220
5221         /* invalidate means busy screen hence upclock */
5222         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5223                 intel_dp_set_drrs_state(&dev_priv->drm,
5224                                         dev_priv->drrs.dp->attached_connector->panel.
5225                                         fixed_mode->vrefresh);
5226
5227         mutex_unlock(&dev_priv->drrs.mutex);
5228 }
5229
5230 /**
5231  * intel_edp_drrs_flush - Restart Idleness DRRS
5232  * @dev: DRM device
5233  * @frontbuffer_bits: frontbuffer plane tracking bits
5234  *
5235  * This function gets called every time rendering on the given planes has
5236  * completed or flip on a crtc is completed. So DRRS should be upclocked
5237  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5238  * if no other planes are dirty.
5239  *
5240  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5241  */
5242 void intel_edp_drrs_flush(struct drm_device *dev,
5243                 unsigned frontbuffer_bits)
5244 {
5245         struct drm_i915_private *dev_priv = to_i915(dev);
5246         struct drm_crtc *crtc;
5247         enum pipe pipe;
5248
5249         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5250                 return;
5251
5252         cancel_delayed_work(&dev_priv->drrs.work);
5253
5254         mutex_lock(&dev_priv->drrs.mutex);
5255         if (!dev_priv->drrs.dp) {
5256                 mutex_unlock(&dev_priv->drrs.mutex);
5257                 return;
5258         }
5259
5260         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5261         pipe = to_intel_crtc(crtc)->pipe;
5262
5263         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5264         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5265
5266         /* flush means busy screen hence upclock */
5267         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5268                 intel_dp_set_drrs_state(&dev_priv->drm,
5269                                         dev_priv->drrs.dp->attached_connector->panel.
5270                                         fixed_mode->vrefresh);
5271
5272         /*
5273          * flush also means no more activity hence schedule downclock, if all
5274          * other fbs are quiescent too
5275          */
5276         if (!dev_priv->drrs.busy_frontbuffer_bits)
5277                 schedule_delayed_work(&dev_priv->drrs.work,
5278                                 msecs_to_jiffies(1000));
5279         mutex_unlock(&dev_priv->drrs.mutex);
5280 }
5281
5282 /**
5283  * DOC: Display Refresh Rate Switching (DRRS)
5284  *
5285  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5286  * which enables swtching between low and high refresh rates,
5287  * dynamically, based on the usage scenario. This feature is applicable
5288  * for internal panels.
5289  *
5290  * Indication that the panel supports DRRS is given by the panel EDID, which
5291  * would list multiple refresh rates for one resolution.
5292  *
5293  * DRRS is of 2 types - static and seamless.
5294  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5295  * (may appear as a blink on screen) and is used in dock-undock scenario.
5296  * Seamless DRRS involves changing RR without any visual effect to the user
5297  * and can be used during normal system usage. This is done by programming
5298  * certain registers.
5299  *
5300  * Support for static/seamless DRRS may be indicated in the VBT based on
5301  * inputs from the panel spec.
5302  *
5303  * DRRS saves power by switching to low RR based on usage scenarios.
5304  *
5305  * The implementation is based on frontbuffer tracking implementation.  When
5306  * there is a disturbance on the screen triggered by user activity or a periodic
5307  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5308  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5309  * made.
5310  *
5311  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5312  * and intel_edp_drrs_flush() are called.
5313  *
5314  * DRRS can be further extended to support other internal panels and also
5315  * the scenario of video playback wherein RR is set based on the rate
5316  * requested by userspace.
5317  */
5318
5319 /**
5320  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5321  * @intel_connector: eDP connector
5322  * @fixed_mode: preferred mode of panel
5323  *
5324  * This function is  called only once at driver load to initialize basic
5325  * DRRS stuff.
5326  *
5327  * Returns:
5328  * Downclock mode if panel supports it, else return NULL.
5329  * DRRS support is determined by the presence of downclock mode (apart
5330  * from VBT setting).
5331  */
5332 static struct drm_display_mode *
5333 intel_dp_drrs_init(struct intel_connector *intel_connector,
5334                 struct drm_display_mode *fixed_mode)
5335 {
5336         struct drm_connector *connector = &intel_connector->base;
5337         struct drm_device *dev = connector->dev;
5338         struct drm_i915_private *dev_priv = to_i915(dev);
5339         struct drm_display_mode *downclock_mode = NULL;
5340
5341         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5342         mutex_init(&dev_priv->drrs.mutex);
5343
5344         if (INTEL_INFO(dev)->gen <= 6) {
5345                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5346                 return NULL;
5347         }
5348
5349         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5350                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5351                 return NULL;
5352         }
5353
5354         downclock_mode = intel_find_panel_downclock
5355                                         (dev, fixed_mode, connector);
5356
5357         if (!downclock_mode) {
5358                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5359                 return NULL;
5360         }
5361
5362         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5363
5364         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5365         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5366         return downclock_mode;
5367 }
5368
5369 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5370                                      struct intel_connector *intel_connector)
5371 {
5372         struct drm_connector *connector = &intel_connector->base;
5373         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5374         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5375         struct drm_device *dev = intel_encoder->base.dev;
5376         struct drm_i915_private *dev_priv = to_i915(dev);
5377         struct drm_display_mode *fixed_mode = NULL;
5378         struct drm_display_mode *downclock_mode = NULL;
5379         bool has_dpcd;
5380         struct drm_display_mode *scan;
5381         struct edid *edid;
5382         enum pipe pipe = INVALID_PIPE;
5383
5384         if (!is_edp(intel_dp))
5385                 return true;
5386
5387         /*
5388          * On IBX/CPT we may get here with LVDS already registered. Since the
5389          * driver uses the only internal power sequencer available for both
5390          * eDP and LVDS bail out early in this case to prevent interfering
5391          * with an already powered-on LVDS power sequencer.
5392          */
5393         if (intel_get_lvds_encoder(dev)) {
5394                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5395                 DRM_INFO("LVDS was detected, not registering eDP\n");
5396
5397                 return false;
5398         }
5399
5400         pps_lock(intel_dp);
5401
5402         intel_dp_init_panel_power_timestamps(intel_dp);
5403
5404         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5405                 vlv_initial_power_sequencer_setup(intel_dp);
5406         } else {
5407                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5408                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5409         }
5410
5411         intel_edp_panel_vdd_sanitize(intel_dp);
5412
5413         pps_unlock(intel_dp);
5414
5415         /* Cache DPCD and EDID for edp. */
5416         has_dpcd = intel_dp_get_dpcd(intel_dp);
5417
5418         if (has_dpcd) {
5419                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5420                         dev_priv->no_aux_handshake =
5421                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5422                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5423         } else {
5424                 /* if this fails, presume the device is a ghost */
5425                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5426                 goto out_vdd_off;
5427         }
5428
5429         mutex_lock(&dev->mode_config.mutex);
5430         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5431         if (edid) {
5432                 if (drm_add_edid_modes(connector, edid)) {
5433                         drm_mode_connector_update_edid_property(connector,
5434                                                                 edid);
5435                         drm_edid_to_eld(connector, edid);
5436                 } else {
5437                         kfree(edid);
5438                         edid = ERR_PTR(-EINVAL);
5439                 }
5440         } else {
5441                 edid = ERR_PTR(-ENOENT);
5442         }
5443         intel_connector->edid = edid;
5444
5445         /* prefer fixed mode from EDID if available */
5446         list_for_each_entry(scan, &connector->probed_modes, head) {
5447                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5448                         fixed_mode = drm_mode_duplicate(dev, scan);
5449                         downclock_mode = intel_dp_drrs_init(
5450                                                 intel_connector, fixed_mode);
5451                         break;
5452                 }
5453         }
5454
5455         /* fallback to VBT if available for eDP */
5456         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5457                 fixed_mode = drm_mode_duplicate(dev,
5458                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5459                 if (fixed_mode) {
5460                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5461                         connector->display_info.width_mm = fixed_mode->width_mm;
5462                         connector->display_info.height_mm = fixed_mode->height_mm;
5463                 }
5464         }
5465         mutex_unlock(&dev->mode_config.mutex);
5466
5467         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5468                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5469                 register_reboot_notifier(&intel_dp->edp_notifier);
5470
5471                 /*
5472                  * Figure out the current pipe for the initial backlight setup.
5473                  * If the current pipe isn't valid, try the PPS pipe, and if that
5474                  * fails just assume pipe A.
5475                  */
5476                 if (IS_CHERRYVIEW(dev))
5477                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5478                 else
5479                         pipe = PORT_TO_PIPE(intel_dp->DP);
5480
5481                 if (pipe != PIPE_A && pipe != PIPE_B)
5482                         pipe = intel_dp->pps_pipe;
5483
5484                 if (pipe != PIPE_A && pipe != PIPE_B)
5485                         pipe = PIPE_A;
5486
5487                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5488                               pipe_name(pipe));
5489         }
5490
5491         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5492         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5493         intel_panel_setup_backlight(connector, pipe);
5494
5495         return true;
5496
5497 out_vdd_off:
5498         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5499         /*
5500          * vdd might still be enabled do to the delayed vdd off.
5501          * Make sure vdd is actually turned off here.
5502          */
5503         pps_lock(intel_dp);
5504         edp_panel_vdd_off_sync(intel_dp);
5505         pps_unlock(intel_dp);
5506
5507         return false;
5508 }
5509
5510 bool
5511 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5512                         struct intel_connector *intel_connector)
5513 {
5514         struct drm_connector *connector = &intel_connector->base;
5515         struct intel_dp *intel_dp = &intel_dig_port->dp;
5516         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5517         struct drm_device *dev = intel_encoder->base.dev;
5518         struct drm_i915_private *dev_priv = to_i915(dev);
5519         enum port port = intel_dig_port->port;
5520         int type;
5521
5522         if (WARN(intel_dig_port->max_lanes < 1,
5523                  "Not enough lanes (%d) for DP on port %c\n",
5524                  intel_dig_port->max_lanes, port_name(port)))
5525                 return false;
5526
5527         intel_dp->pps_pipe = INVALID_PIPE;
5528
5529         /* intel_dp vfuncs */
5530         if (INTEL_INFO(dev)->gen >= 9)
5531                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5532         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5533                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5534         else if (HAS_PCH_SPLIT(dev))
5535                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5536         else
5537                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5538
5539         if (INTEL_INFO(dev)->gen >= 9)
5540                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5541         else
5542                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5543
5544         if (HAS_DDI(dev))
5545                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5546
5547         /* Preserve the current hw state. */
5548         intel_dp->DP = I915_READ(intel_dp->output_reg);
5549         intel_dp->attached_connector = intel_connector;
5550
5551         if (intel_dp_is_edp(dev, port))
5552                 type = DRM_MODE_CONNECTOR_eDP;
5553         else
5554                 type = DRM_MODE_CONNECTOR_DisplayPort;
5555
5556         /*
5557          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5558          * for DP the encoder type can be set by the caller to
5559          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5560          */
5561         if (type == DRM_MODE_CONNECTOR_eDP)
5562                 intel_encoder->type = INTEL_OUTPUT_EDP;
5563
5564         /* eDP only on port B and/or C on vlv/chv */
5565         if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5566                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5567                 return false;
5568
5569         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5570                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5571                         port_name(port));
5572
5573         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5574         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5575
5576         connector->interlace_allowed = true;
5577         connector->doublescan_allowed = 0;
5578
5579         intel_dp_aux_init(intel_dp, intel_connector);
5580
5581         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5582                           edp_panel_vdd_work);
5583
5584         intel_connector_attach_encoder(intel_connector, intel_encoder);
5585
5586         if (HAS_DDI(dev))
5587                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5588         else
5589                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5590
5591         /* Set up the hotplug pin. */
5592         switch (port) {
5593         case PORT_A:
5594                 intel_encoder->hpd_pin = HPD_PORT_A;
5595                 break;
5596         case PORT_B:
5597                 intel_encoder->hpd_pin = HPD_PORT_B;
5598                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5599                         intel_encoder->hpd_pin = HPD_PORT_A;
5600                 break;
5601         case PORT_C:
5602                 intel_encoder->hpd_pin = HPD_PORT_C;
5603                 break;
5604         case PORT_D:
5605                 intel_encoder->hpd_pin = HPD_PORT_D;
5606                 break;
5607         case PORT_E:
5608                 intel_encoder->hpd_pin = HPD_PORT_E;
5609                 break;
5610         default:
5611                 BUG();
5612         }
5613
5614         /* init MST on ports that can support it */
5615         if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
5616             (port == PORT_B || port == PORT_C || port == PORT_D))
5617                 intel_dp_mst_encoder_init(intel_dig_port,
5618                                           intel_connector->base.base.id);
5619
5620         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5621                 intel_dp_aux_fini(intel_dp);
5622                 intel_dp_mst_encoder_cleanup(intel_dig_port);
5623                 goto fail;
5624         }
5625
5626         intel_dp_add_properties(intel_dp, connector);
5627
5628         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5629          * 0xd.  Failure to do so will result in spurious interrupts being
5630          * generated on the port when a cable is not attached.
5631          */
5632         if (IS_G4X(dev) && !IS_GM45(dev)) {
5633                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5634                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5635         }
5636
5637         return true;
5638
5639 fail:
5640         drm_connector_cleanup(connector);
5641
5642         return false;
5643 }
5644
5645 bool intel_dp_init(struct drm_device *dev,
5646                    i915_reg_t output_reg,
5647                    enum port port)
5648 {
5649         struct drm_i915_private *dev_priv = to_i915(dev);
5650         struct intel_digital_port *intel_dig_port;
5651         struct intel_encoder *intel_encoder;
5652         struct drm_encoder *encoder;
5653         struct intel_connector *intel_connector;
5654
5655         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5656         if (!intel_dig_port)
5657                 return false;
5658
5659         intel_connector = intel_connector_alloc();
5660         if (!intel_connector)
5661                 goto err_connector_alloc;
5662
5663         intel_encoder = &intel_dig_port->base;
5664         encoder = &intel_encoder->base;
5665
5666         if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5667                              DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
5668                 goto err_encoder_init;
5669
5670         intel_encoder->compute_config = intel_dp_compute_config;
5671         intel_encoder->disable = intel_disable_dp;
5672         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5673         intel_encoder->get_config = intel_dp_get_config;
5674         intel_encoder->suspend = intel_dp_encoder_suspend;
5675         if (IS_CHERRYVIEW(dev)) {
5676                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5677                 intel_encoder->pre_enable = chv_pre_enable_dp;
5678                 intel_encoder->enable = vlv_enable_dp;
5679                 intel_encoder->post_disable = chv_post_disable_dp;
5680                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5681         } else if (IS_VALLEYVIEW(dev)) {
5682                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5683                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5684                 intel_encoder->enable = vlv_enable_dp;
5685                 intel_encoder->post_disable = vlv_post_disable_dp;
5686         } else {
5687                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5688                 intel_encoder->enable = g4x_enable_dp;
5689                 if (INTEL_INFO(dev)->gen >= 5)
5690                         intel_encoder->post_disable = ilk_post_disable_dp;
5691         }
5692
5693         intel_dig_port->port = port;
5694         intel_dig_port->dp.output_reg = output_reg;
5695         intel_dig_port->max_lanes = 4;
5696
5697         intel_encoder->type = INTEL_OUTPUT_DP;
5698         if (IS_CHERRYVIEW(dev)) {
5699                 if (port == PORT_D)
5700                         intel_encoder->crtc_mask = 1 << 2;
5701                 else
5702                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5703         } else {
5704                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5705         }
5706         intel_encoder->cloneable = 0;
5707
5708         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5709         dev_priv->hotplug.irq_port[port] = intel_dig_port;
5710
5711         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5712                 goto err_init_connector;
5713
5714         return true;
5715
5716 err_init_connector:
5717         drm_encoder_cleanup(encoder);
5718 err_encoder_init:
5719         kfree(intel_connector);
5720 err_connector_alloc:
5721         kfree(intel_dig_port);
5722         return false;
5723 }
5724
5725 void intel_dp_mst_suspend(struct drm_device *dev)
5726 {
5727         struct drm_i915_private *dev_priv = to_i915(dev);
5728         int i;
5729
5730         /* disable MST */
5731         for (i = 0; i < I915_MAX_PORTS; i++) {
5732                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5733
5734                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5735                         continue;
5736
5737                 if (intel_dig_port->dp.is_mst)
5738                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5739         }
5740 }
5741
5742 void intel_dp_mst_resume(struct drm_device *dev)
5743 {
5744         struct drm_i915_private *dev_priv = to_i915(dev);
5745         int i;
5746
5747         for (i = 0; i < I915_MAX_PORTS; i++) {
5748                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5749                 int ret;
5750
5751                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5752                         continue;
5753
5754                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5755                 if (ret)
5756                         intel_dp_check_mst_status(&intel_dig_port->dp);
5757         }
5758 }