drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  56 {
  57         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  58
  59         return intel_dig_port->base.base.dev;
  60 }
  61
  62 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  63 {
  64         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  65 }
  66
  67 static void intel_dp_link_down(struct intel_dp *intel_dp);
  68
  69 static int
  70 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  71 {
  72         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  73
  74         switch (max_link_bw) {
  75         case DP_LINK_BW_1_62:
  76         case DP_LINK_BW_2_7:
  77                 break;
  78         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
  79                 max_link_bw = DP_LINK_BW_2_7;
  80                 break;
  81         default:
  82                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
  83                      max_link_bw);
  84                 max_link_bw = DP_LINK_BW_1_62;
  85                 break;
  86         }
  87         return max_link_bw;
  88 }
  89
  90 /*
  91  * The units on the numbers in the next two are... bizarre.  Examples will
  92  * make it clearer; this one parallels an example in the eDP spec.
  93  *
  94  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
  95  *
  96  *     270000 * 1 * 8 / 10 == 216000
  97  *
  98  * The actual data capacity of that configuration is 2.16Gbit/s, so the
  99  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 100  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 101  * 119000.  At 18bpp that's 2142000 kilobits per second.
 102  *
 103  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 104  * get the result in decakilobits instead of kilobits.
 105  */
 106
 107 static int
 108 intel_dp_link_required(int pixel_clock, int bpp)
 109 {
 110         return (pixel_clock * bpp + 9) / 10;
 111 }
 112
 113 static int
 114 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 115 {
 116         return (max_link_clock * max_lanes * 8) / 10;
 117 }
 118
 119 static int
 120 intel_dp_mode_valid(struct drm_connector *connector,
 121                     struct drm_display_mode *mode)
 122 {
 123         struct intel_dp *intel_dp = intel_attached_dp(connector);
 124         struct intel_connector *intel_connector = to_intel_connector(connector);
 125         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 126         int target_clock = mode->clock;
 127         int max_rate, mode_rate, max_lanes, max_link_clock;
 128
 129         if (is_edp(intel_dp) && fixed_mode) {
 130                 if (mode->hdisplay > fixed_mode->hdisplay)
 131                         return MODE_PANEL;
 132
 133                 if (mode->vdisplay > fixed_mode->vdisplay)
 134                         return MODE_PANEL;
 135
 136                 target_clock = fixed_mode->clock;
 137         }
 138
 139         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 140         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 141
 142         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 143         mode_rate = intel_dp_link_required(target_clock, 18);
 144
 145         if (mode_rate > max_rate)
 146                 return MODE_CLOCK_HIGH;
 147
 148         if (mode->clock < 10000)
 149                 return MODE_CLOCK_LOW;
 150
 151         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 152                 return MODE_H_ILLEGAL;
 153
 154         return MODE_OK;
 155 }
 156
 157 static uint32_t
 158 pack_aux(uint8_t *src, int src_bytes)
 159 {
 160         int     i;
 161         uint32_t v = 0;
 162
 163         if (src_bytes > 4)
 164                 src_bytes = 4;
 165         for (i = 0; i < src_bytes; i++)
 166                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 167         return v;
 168 }
 169
 170 static void
 171 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 172 {
 173         int i;
 174         if (dst_bytes > 4)
 175                 dst_bytes = 4;
 176         for (i = 0; i < dst_bytes; i++)
 177                 dst[i] = src >> ((3-i) * 8);
 178 }
 179
 180 /* hrawclock is 1/4 the FSB frequency */
 181 static int
 182 intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 188         if (IS_VALLEYVIEW(dev))
 189                 return 200;
 190
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100;
 195         case CLKCFG_FSB_533:
 196                 return 133;
 197         case CLKCFG_FSB_667:
 198                 return 166;
 199         case CLKCFG_FSB_800:
 200                 return 200;
 201         case CLKCFG_FSB_1067:
 202                 return 266;
 203         case CLKCFG_FSB_1333:
 204                 return 333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400;
 209         default:
 210                 return 133;
 211         }
 212 }
 213
 214 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 215 {
 216         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 217         struct drm_i915_private *dev_priv = dev->dev_private;
 218         u32 pp_stat_reg;
 219
 220         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 221         return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 222 }
 223
 224 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 225 {
 226         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 227         struct drm_i915_private *dev_priv = dev->dev_private;
 228         u32 pp_ctrl_reg;
 229
 230         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 231         return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 232 }
 233
 234 static void
 235 intel_dp_check_edp(struct intel_dp *intel_dp)
 236 {
 237         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 238         struct drm_i915_private *dev_priv = dev->dev_private;
 239         u32 pp_stat_reg, pp_ctrl_reg;
 240
 241         if (!is_edp(intel_dp))
 242                 return;
 243
 244         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 245         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 246
 247         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 248                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 249                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 250                                 I915_READ(pp_stat_reg),
 251                                 I915_READ(pp_ctrl_reg));
 252         }
 253 }
 254
 255 static uint32_t
 256 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 257 {
 258         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 259         struct drm_device *dev = intel_dig_port->base.base.dev;
 260         struct drm_i915_private *dev_priv = dev->dev_private;
 261         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 262         uint32_t status;
 263         bool done;
 264
 265 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 266         if (has_aux_irq)
 267                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 268                                           msecs_to_jiffies_timeout(10));
 269         else
 270                 done = wait_for_atomic(C, 10) == 0;
 271         if (!done)
 272                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 273                           has_aux_irq);
 274 #undef C
 275
 276         return status;
 277 }
 278
 279 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
 280                                       int index)
 281 {
 282         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 283         struct drm_device *dev = intel_dig_port->base.base.dev;
 284         struct drm_i915_private *dev_priv = dev->dev_private;
 285
 286         /* The clock divider is based off the hrawclk,
 287          * and would like to run at 2MHz. So, take the
 288          * hrawclk value and divide by 2 and use that
 289          *
 290          * Note that PCH attached eDP panels should use a 125MHz input
 291          * clock divider.
 292          */
 293         if (IS_VALLEYVIEW(dev)) {
 294                 return index ? 0 : 100;
 295         } else if (intel_dig_port->port == PORT_A) {
 296                 if (index)
 297                         return 0;
 298                 if (HAS_DDI(dev))
 299                         return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 300                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 301                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 302                 else
 303                         return 225; /* eDP input clock at 450Mhz */
 304         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 305                 /* Workaround for non-ULT HSW */
 306                 switch (index) {
 307                 case 0: return 63;
 308                 case 1: return 72;
 309                 default: return 0;
 310                 }
 311         } else if (HAS_PCH_SPLIT(dev)) {
 312                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 313         } else {
 314                 return index ? 0 :intel_hrawclk(dev) / 2;
 315         }
 316 }
 317
 318 static int
 319 intel_dp_aux_ch(struct intel_dp *intel_dp,
 320                 uint8_t *send, int send_bytes,
 321                 uint8_t *recv, int recv_size)
 322 {
 323         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 324         struct drm_device *dev = intel_dig_port->base.base.dev;
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 327         uint32_t ch_data = ch_ctl + 4;
 328         uint32_t aux_clock_divider;
 329         int i, ret, recv_bytes;
 330         uint32_t status;
 331         int try, precharge, clock = 0;
 332         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 333
 334         /* dp aux is extremely sensitive to irq latency, hence request the
 335          * lowest possible wakeup latency and so prevent the cpu from going into
 336          * deep sleep states.
 337          */
 338         pm_qos_update_request(&dev_priv->pm_qos, 0);
 339
 340         intel_dp_check_edp(intel_dp);
 341
 342         if (IS_GEN6(dev))
 343                 precharge = 3;
 344         else
 345                 precharge = 5;
 346
 347         intel_aux_display_runtime_get(dev_priv);
 348
 349         /* Try to wait for any previous AUX channel activity */
 350         for (try = 0; try < 3; try++) {
 351                 status = I915_READ_NOTRACE(ch_ctl);
 352                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 353                         break;
 354                 msleep(1);
 355         }
 356
 357         if (try == 3) {
 358                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 359                      I915_READ(ch_ctl));
 360                 ret = -EBUSY;
 361                 goto out;
 362         }
 363
 364         while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
 365                 /* Must try at least 3 times according to DP spec */
 366                 for (try = 0; try < 5; try++) {
 367                         /* Load the send data into the aux channel data registers */
 368                         for (i = 0; i < send_bytes; i += 4)
 369                                 I915_WRITE(ch_data + i,
 370                                            pack_aux(send + i, send_bytes - i));
 371
 372                         /* Send the command and wait for it to complete */
 373                         I915_WRITE(ch_ctl,
 374                                    DP_AUX_CH_CTL_SEND_BUSY |
 375                                    (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 376                                    DP_AUX_CH_CTL_TIME_OUT_400us |
 377                                    (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 378                                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 379                                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 380                                    DP_AUX_CH_CTL_DONE |
 381                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 382                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 383
 384                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 385
 386                         /* Clear done status and any errors */
 387                         I915_WRITE(ch_ctl,
 388                                    status |
 389                                    DP_AUX_CH_CTL_DONE |
 390                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 391                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 392
 393                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 394                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 395                                 continue;
 396                         if (status & DP_AUX_CH_CTL_DONE)
 397                                 break;
 398                 }
 399                 if (status & DP_AUX_CH_CTL_DONE)
 400                         break;
 401         }
 402
 403         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 404                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 405                 ret = -EBUSY;
 406                 goto out;
 407         }
 408
 409         /* Check for timeout or receive error.
 410          * Timeouts occur when the sink is not connected
 411          */
 412         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 413                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 414                 ret = -EIO;
 415                 goto out;
 416         }
 417
 418         /* Timeouts occur when the device isn't connected, so they're
 419          * "normal" -- don't fill the kernel log with these */
 420         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 421                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 422                 ret = -ETIMEDOUT;
 423                 goto out;
 424         }
 425
 426         /* Unload any bytes sent back from the other side */
 427         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 428                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 429         if (recv_bytes > recv_size)
 430                 recv_bytes = recv_size;
 431
 432         for (i = 0; i < recv_bytes; i += 4)
 433                 unpack_aux(I915_READ(ch_data + i),
 434                            recv + i, recv_bytes - i);
 435
 436         ret = recv_bytes;
 437 out:
 438         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 439         intel_aux_display_runtime_put(dev_priv);
 440
 441         return ret;
 442 }
 443
 444 /* Write data to the aux channel in native mode */
 445 static int
 446 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 447                           uint16_t address, uint8_t *send, int send_bytes)
 448 {
 449         int ret;
 450         uint8_t msg[20];
 451         int msg_bytes;
 452         uint8_t ack;
 453
 454         intel_dp_check_edp(intel_dp);
 455         if (send_bytes > 16)
 456                 return -1;
 457         msg[0] = AUX_NATIVE_WRITE << 4;
 458         msg[1] = address >> 8;
 459         msg[2] = address & 0xff;
 460         msg[3] = send_bytes - 1;
 461         memcpy(&msg[4], send, send_bytes);
 462         msg_bytes = send_bytes + 4;
 463         for (;;) {
 464                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 465                 if (ret < 0)
 466                         return ret;
 467                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 468                         break;
 469                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 470                         udelay(100);
 471                 else
 472                         return -EIO;
 473         }
 474         return send_bytes;
 475 }
 476
 477 /* Write a single byte to the aux channel in native mode */
 478 static int
 479 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 480                             uint16_t address, uint8_t byte)
 481 {
 482         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 483 }
 484
 485 /* read bytes from a native aux channel */
 486 static int
 487 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 488                          uint16_t address, uint8_t *recv, int recv_bytes)
 489 {
 490         uint8_t msg[4];
 491         int msg_bytes;
 492         uint8_t reply[20];
 493         int reply_bytes;
 494         uint8_t ack;
 495         int ret;
 496
 497         intel_dp_check_edp(intel_dp);
 498         msg[0] = AUX_NATIVE_READ << 4;
 499         msg[1] = address >> 8;
 500         msg[2] = address & 0xff;
 501         msg[3] = recv_bytes - 1;
 502
 503         msg_bytes = 4;
 504         reply_bytes = recv_bytes + 1;
 505
 506         for (;;) {
 507                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 508                                       reply, reply_bytes);
 509                 if (ret == 0)
 510                         return -EPROTO;
 511                 if (ret < 0)
 512                         return ret;
 513                 ack = reply[0];
 514                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 515                         memcpy(recv, reply + 1, ret - 1);
 516                         return ret - 1;
 517                 }
 518                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 519                         udelay(100);
 520                 else
 521                         return -EIO;
 522         }
 523 }
 524
 525 static int
 526 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 527                     uint8_t write_byte, uint8_t *read_byte)
 528 {
 529         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 530         struct intel_dp *intel_dp = container_of(adapter,
 531                                                 struct intel_dp,
 532                                                 adapter);
 533         uint16_t address = algo_data->address;
 534         uint8_t msg[5];
 535         uint8_t reply[2];
 536         unsigned retry;
 537         int msg_bytes;
 538         int reply_bytes;
 539         int ret;
 540
 541         intel_dp_check_edp(intel_dp);
 542         /* Set up the command byte */
 543         if (mode & MODE_I2C_READ)
 544                 msg[0] = AUX_I2C_READ << 4;
 545         else
 546                 msg[0] = AUX_I2C_WRITE << 4;
 547
 548         if (!(mode & MODE_I2C_STOP))
 549                 msg[0] |= AUX_I2C_MOT << 4;
 550
 551         msg[1] = address >> 8;
 552         msg[2] = address;
 553
 554         switch (mode) {
 555         case MODE_I2C_WRITE:
 556                 msg[3] = 0;
 557                 msg[4] = write_byte;
 558                 msg_bytes = 5;
 559                 reply_bytes = 1;
 560                 break;
 561         case MODE_I2C_READ:
 562                 msg[3] = 0;
 563                 msg_bytes = 4;
 564                 reply_bytes = 2;
 565                 break;
 566         default:
 567                 msg_bytes = 3;
 568                 reply_bytes = 1;
 569                 break;
 570         }
 571
 572         for (retry = 0; retry < 5; retry++) {
 573                 ret = intel_dp_aux_ch(intel_dp,
 574                                       msg, msg_bytes,
 575                                       reply, reply_bytes);
 576                 if (ret < 0) {
 577                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 578                         return ret;
 579                 }
 580
 581                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 582                 case AUX_NATIVE_REPLY_ACK:
 583                         /* I2C-over-AUX Reply field is only valid
 584                          * when paired with AUX ACK.
 585                          */
 586                         break;
 587                 case AUX_NATIVE_REPLY_NACK:
 588                         DRM_DEBUG_KMS("aux_ch native nack\n");
 589                         return -EREMOTEIO;
 590                 case AUX_NATIVE_REPLY_DEFER:
 591                         /*
 592                          * For now, just give more slack to branch devices. We
 593                          * could check the DPCD for I2C bit rate capabilities,
 594                          * and if available, adjust the interval. We could also
 595                          * be more careful with DP-to-Legacy adapters where a
 596                          * long legacy cable may force very low I2C bit rates.
 597                          */
 598                         if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 599                             DP_DWN_STRM_PORT_PRESENT)
 600                                 usleep_range(500, 600);
 601                         else
 602                                 usleep_range(300, 400);
 603                         continue;
 604                 default:
 605                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 606                                   reply[0]);
 607                         return -EREMOTEIO;
 608                 }
 609
 610                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 611                 case AUX_I2C_REPLY_ACK:
 612                         if (mode == MODE_I2C_READ) {
 613                                 *read_byte = reply[1];
 614                         }
 615                         return reply_bytes - 1;
 616                 case AUX_I2C_REPLY_NACK:
 617                         DRM_DEBUG_KMS("aux_i2c nack\n");
 618                         return -EREMOTEIO;
 619                 case AUX_I2C_REPLY_DEFER:
 620                         DRM_DEBUG_KMS("aux_i2c defer\n");
 621                         udelay(100);
 622                         break;
 623                 default:
 624                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 625                         return -EREMOTEIO;
 626                 }
 627         }
 628
 629         DRM_ERROR("too many retries, giving up\n");
 630         return -EREMOTEIO;
 631 }
 632
 633 static int
 634 intel_dp_i2c_init(struct intel_dp *intel_dp,
 635                   struct intel_connector *intel_connector, const char *name)
 636 {
 637         int     ret;
 638
 639         DRM_DEBUG_KMS("i2c_init %s\n", name);
 640         intel_dp->algo.running = false;
 641         intel_dp->algo.address = 0;
 642         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 643
 644         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 645         intel_dp->adapter.owner = THIS_MODULE;
 646         intel_dp->adapter.class = I2C_CLASS_DDC;
 647         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 648         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 649         intel_dp->adapter.algo_data = &intel_dp->algo;
 650         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 651
 652         ironlake_edp_panel_vdd_on(intel_dp);
 653         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 654         ironlake_edp_panel_vdd_off(intel_dp, false);
 655         return ret;
 656 }
 657
 658 static void
 659 intel_dp_set_clock(struct intel_encoder *encoder,
 660                    struct intel_crtc_config *pipe_config, int link_bw)
 661 {
 662         struct drm_device *dev = encoder->base.dev;
 663
 664         if (IS_G4X(dev)) {
 665                 if (link_bw == DP_LINK_BW_1_62) {
 666                         pipe_config->dpll.p1 = 2;
 667                         pipe_config->dpll.p2 = 10;
 668                         pipe_config->dpll.n = 2;
 669                         pipe_config->dpll.m1 = 23;
 670                         pipe_config->dpll.m2 = 8;
 671                 } else {
 672                         pipe_config->dpll.p1 = 1;
 673                         pipe_config->dpll.p2 = 10;
 674                         pipe_config->dpll.n = 1;
 675                         pipe_config->dpll.m1 = 14;
 676                         pipe_config->dpll.m2 = 2;
 677                 }
 678                 pipe_config->clock_set = true;
 679         } else if (IS_HASWELL(dev)) {
 680                 /* Haswell has special-purpose DP DDI clocks. */
 681         } else if (HAS_PCH_SPLIT(dev)) {
 682                 if (link_bw == DP_LINK_BW_1_62) {
 683                         pipe_config->dpll.n = 1;
 684                         pipe_config->dpll.p1 = 2;
 685                         pipe_config->dpll.p2 = 10;
 686                         pipe_config->dpll.m1 = 12;
 687                         pipe_config->dpll.m2 = 9;
 688                 } else {
 689                         pipe_config->dpll.n = 2;
 690                         pipe_config->dpll.p1 = 1;
 691                         pipe_config->dpll.p2 = 10;
 692                         pipe_config->dpll.m1 = 14;
 693                         pipe_config->dpll.m2 = 8;
 694                 }
 695                 pipe_config->clock_set = true;
 696         } else if (IS_VALLEYVIEW(dev)) {
 697                 /* FIXME: Need to figure out optimized DP clocks for vlv. */
 698         }
 699 }
 700
 701 bool
 702 intel_dp_compute_config(struct intel_encoder *encoder,
 703                         struct intel_crtc_config *pipe_config)
 704 {
 705         struct drm_device *dev = encoder->base.dev;
 706         struct drm_i915_private *dev_priv = dev->dev_private;
 707         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 708         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 709         enum port port = dp_to_dig_port(intel_dp)->port;
 710         struct intel_crtc *intel_crtc = encoder->new_crtc;
 711         struct intel_connector *intel_connector = intel_dp->attached_connector;
 712         int lane_count, clock;
 713         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 714         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 715         int bpp, mode_rate;
 716         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 717         int link_avail, link_clock;
 718
 719         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 720                 pipe_config->has_pch_encoder = true;
 721
 722         pipe_config->has_dp_encoder = true;
 723
 724         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 725                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 726                                        adjusted_mode);
 727                 if (!HAS_PCH_SPLIT(dev))
 728                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 729                                                  intel_connector->panel.fitting_mode);
 730                 else
 731                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 732                                                 intel_connector->panel.fitting_mode);
 733         }
 734
 735         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 736                 return false;
 737
 738         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 739                       "max bw %02x pixel clock %iKHz\n",
 740                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 741
 742         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 743          * bpc in between. */
 744         bpp = pipe_config->pipe_bpp;
 745         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
 746                 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 747                               dev_priv->vbt.edp_bpp);
 748                 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
 749         }
 750
 751         for (; bpp >= 6*3; bpp -= 2*3) {
 752                 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 753
 754                 for (clock = 0; clock <= max_clock; clock++) {
 755                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 756                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 757                                 link_avail = intel_dp_max_data_rate(link_clock,
 758                                                                     lane_count);
 759
 760                                 if (mode_rate <= link_avail) {
 761                                         goto found;
 762                                 }
 763                         }
 764                 }
 765         }
 766
 767         return false;
 768
 769 found:
 770         if (intel_dp->color_range_auto) {
 771                 /*
 772                  * See:
 773                  * CEA-861-E - 5.1 Default Encoding Parameters
 774                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 775                  */
 776                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 777                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 778                 else
 779                         intel_dp->color_range = 0;
 780         }
 781
 782         if (intel_dp->color_range)
 783                 pipe_config->limited_color_range = true;
 784
 785         intel_dp->link_bw = bws[clock];
 786         intel_dp->lane_count = lane_count;
 787         pipe_config->pipe_bpp = bpp;
 788         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 789
 790         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 791                       intel_dp->link_bw, intel_dp->lane_count,
 792                       pipe_config->port_clock, bpp);
 793         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 794                       mode_rate, link_avail);
 795
 796         intel_link_compute_m_n(bpp, lane_count,
 797                                adjusted_mode->clock, pipe_config->port_clock,
 798                                &pipe_config->dp_m_n);
 799
 800         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 801
 802         return true;
 803 }
 804
 805 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 806 {
 807         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 808         intel_dp->link_configuration[0] = intel_dp->link_bw;
 809         intel_dp->link_configuration[1] = intel_dp->lane_count;
 810         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 811         /*
 812          * Check for DPCD version > 1.1 and enhanced framing support
 813          */
 814         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 815             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 816                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 817         }
 818 }
 819
 820 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 821 {
 822         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 823         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 824         struct drm_device *dev = crtc->base.dev;
 825         struct drm_i915_private *dev_priv = dev->dev_private;
 826         u32 dpa_ctl;
 827
 828         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 829         dpa_ctl = I915_READ(DP_A);
 830         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 831
 832         if (crtc->config.port_clock == 162000) {
 833                 /* For a long time we've carried around a ILK-DevA w/a for the
 834                  * 160MHz clock. If we're really unlucky, it's still required.
 835                  */
 836                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 837                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 838                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 839         } else {
 840                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 841                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 842         }
 843
 844         I915_WRITE(DP_A, dpa_ctl);
 845
 846         POSTING_READ(DP_A);
 847         udelay(500);
 848 }
 849
 850 static void intel_dp_mode_set(struct intel_encoder *encoder)
 851 {
 852         struct drm_device *dev = encoder->base.dev;
 853         struct drm_i915_private *dev_priv = dev->dev_private;
 854         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 855         enum port port = dp_to_dig_port(intel_dp)->port;
 856         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 857         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 858
 859         /*
 860          * There are four kinds of DP registers:
 861          *
 862          *      IBX PCH
 863          *      SNB CPU
 864          *      IVB CPU
 865          *      CPT PCH
 866          *
 867          * IBX PCH and CPU are the same for almost everything,
 868          * except that the CPU DP PLL is configured in this
 869          * register
 870          *
 871          * CPT PCH is quite different, having many bits moved
 872          * to the TRANS_DP_CTL register instead. That
 873          * configuration happens (oddly) in ironlake_pch_enable
 874          */
 875
 876         /* Preserve the BIOS-computed detected bit. This is
 877          * supposed to be read-only.
 878          */
 879         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 880
 881         /* Handle DP bits in common between all three register formats */
 882         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 883         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 884
 885         if (intel_dp->has_audio) {
 886                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 887                                  pipe_name(crtc->pipe));
 888                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 889                 intel_write_eld(&encoder->base, adjusted_mode);
 890         }
 891
 892         intel_dp_init_link_config(intel_dp);
 893
 894         /* Split out the IBX/CPU vs CPT settings */
 895
 896         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 897                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 898                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 899                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 900                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 901                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 902
 903                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 904                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 905
 906                 intel_dp->DP |= crtc->pipe << 29;
 907         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 908                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 909                         intel_dp->DP |= intel_dp->color_range;
 910
 911                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 912                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 913                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 914                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 915                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 916
 917                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 918                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 919
 920                 if (crtc->pipe == 1)
 921                         intel_dp->DP |= DP_PIPEB_SELECT;
 922         } else {
 923                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 924         }
 925
 926         if (port == PORT_A && !IS_VALLEYVIEW(dev))
 927                 ironlake_set_pll_cpu_edp(intel_dp);
 928 }
 929
 930 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 931 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 932
 933 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 934 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 935
 936 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 937 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 938
 939 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 940                                        u32 mask,
 941                                        u32 value)
 942 {
 943         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 944         struct drm_i915_private *dev_priv = dev->dev_private;
 945         u32 pp_stat_reg, pp_ctrl_reg;
 946
 947         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 948         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 949
 950         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 951                         mask, value,
 952                         I915_READ(pp_stat_reg),
 953                         I915_READ(pp_ctrl_reg));
 954
 955         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 956                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 957                                 I915_READ(pp_stat_reg),
 958                                 I915_READ(pp_ctrl_reg));
 959         }
 960 }
 961
 962 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 963 {
 964         DRM_DEBUG_KMS("Wait for panel power on\n");
 965         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 966 }
 967
 968 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 969 {
 970         DRM_DEBUG_KMS("Wait for panel power off time\n");
 971         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 972 }
 973
 974 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 975 {
 976         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 977         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 978 }
 979
 980
 981 /* Read the current pp_control value, unlocking the register if it
 982  * is locked
 983  */
 984
 985 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 986 {
 987         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 988         struct drm_i915_private *dev_priv = dev->dev_private;
 989         u32 control;
 990         u32 pp_ctrl_reg;
 991
 992         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 993         control = I915_READ(pp_ctrl_reg);
 994
 995         control &= ~PANEL_UNLOCK_MASK;
 996         control |= PANEL_UNLOCK_REGS;
 997         return control;
 998 }
 999
1000 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1001 {
1002         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1003         struct drm_i915_private *dev_priv = dev->dev_private;
1004         u32 pp;
1005         u32 pp_stat_reg, pp_ctrl_reg;
1006
1007         if (!is_edp(intel_dp))
1008                 return;
1009         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1010
1011         WARN(intel_dp->want_panel_vdd,
1012              "eDP VDD already requested on\n");
1013
1014         intel_dp->want_panel_vdd = true;
1015
1016         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1017                 DRM_DEBUG_KMS("eDP VDD already on\n");
1018                 return;
1019         }
1020
1021         if (!ironlake_edp_have_panel_power(intel_dp))
1022                 ironlake_wait_panel_power_cycle(intel_dp);
1023
1024         pp = ironlake_get_pp_control(intel_dp);
1025         pp |= EDP_FORCE_VDD;
1026
1027         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1028         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1029
1030         I915_WRITE(pp_ctrl_reg, pp);
1031         POSTING_READ(pp_ctrl_reg);
1032         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1033                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1034         /*
1035          * If the panel wasn't on, delay before accessing aux channel
1036          */
1037         if (!ironlake_edp_have_panel_power(intel_dp)) {
1038                 DRM_DEBUG_KMS("eDP was not running\n");
1039                 msleep(intel_dp->panel_power_up_delay);
1040         }
1041 }
1042
1043 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1044 {
1045         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1046         struct drm_i915_private *dev_priv = dev->dev_private;
1047         u32 pp;
1048         u32 pp_stat_reg, pp_ctrl_reg;
1049
1050         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1051
1052         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1053                 pp = ironlake_get_pp_control(intel_dp);
1054                 pp &= ~EDP_FORCE_VDD;
1055
1056                 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1057                 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1058
1059                 I915_WRITE(pp_ctrl_reg, pp);
1060                 POSTING_READ(pp_ctrl_reg);
1061
1062                 /* Make sure sequencer is idle before allowing subsequent activity */
1063                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1064                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1065                 msleep(intel_dp->panel_power_down_delay);
1066         }
1067 }
1068
1069 static void ironlake_panel_vdd_work(struct work_struct *__work)
1070 {
1071         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1072                                                  struct intel_dp, panel_vdd_work);
1073         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1074
1075         mutex_lock(&dev->mode_config.mutex);
1076         ironlake_panel_vdd_off_sync(intel_dp);
1077         mutex_unlock(&dev->mode_config.mutex);
1078 }
1079
1080 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1081 {
1082         if (!is_edp(intel_dp))
1083                 return;
1084
1085         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1086         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1087
1088         intel_dp->want_panel_vdd = false;
1089
1090         if (sync) {
1091                 ironlake_panel_vdd_off_sync(intel_dp);
1092         } else {
1093                 /*
1094                  * Queue the timer to fire a long
1095                  * time from now (relative to the power down delay)
1096                  * to keep the panel power up across a sequence of operations
1097                  */
1098                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1099                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1100         }
1101 }
1102
1103 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1104 {
1105         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1106         struct drm_i915_private *dev_priv = dev->dev_private;
1107         u32 pp;
1108         u32 pp_ctrl_reg;
1109
1110         if (!is_edp(intel_dp))
1111                 return;
1112
1113         DRM_DEBUG_KMS("Turn eDP power on\n");
1114
1115         if (ironlake_edp_have_panel_power(intel_dp)) {
1116                 DRM_DEBUG_KMS("eDP power already on\n");
1117                 return;
1118         }
1119
1120         ironlake_wait_panel_power_cycle(intel_dp);
1121
1122         pp = ironlake_get_pp_control(intel_dp);
1123         if (IS_GEN5(dev)) {
1124                 /* ILK workaround: disable reset around power sequence */
1125                 pp &= ~PANEL_POWER_RESET;
1126                 I915_WRITE(PCH_PP_CONTROL, pp);
1127                 POSTING_READ(PCH_PP_CONTROL);
1128         }
1129
1130         pp |= POWER_TARGET_ON;
1131         if (!IS_GEN5(dev))
1132                 pp |= PANEL_POWER_RESET;
1133
1134         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1135
1136         I915_WRITE(pp_ctrl_reg, pp);
1137         POSTING_READ(pp_ctrl_reg);
1138
1139         ironlake_wait_panel_on(intel_dp);
1140
1141         if (IS_GEN5(dev)) {
1142                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1143                 I915_WRITE(PCH_PP_CONTROL, pp);
1144                 POSTING_READ(PCH_PP_CONTROL);
1145         }
1146 }
1147
1148 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1149 {
1150         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152         u32 pp;
1153         u32 pp_ctrl_reg;
1154
1155         if (!is_edp(intel_dp))
1156                 return;
1157
1158         DRM_DEBUG_KMS("Turn eDP power off\n");
1159
1160         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1161
1162         pp = ironlake_get_pp_control(intel_dp);
1163         /* We need to switch off panel power _and_ force vdd, for otherwise some
1164          * panels get very unhappy and cease to work. */
1165         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1166
1167         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1168
1169         I915_WRITE(pp_ctrl_reg, pp);
1170         POSTING_READ(pp_ctrl_reg);
1171
1172         intel_dp->want_panel_vdd = false;
1173
1174         ironlake_wait_panel_off(intel_dp);
1175 }
1176
1177 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1178 {
1179         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1180         struct drm_device *dev = intel_dig_port->base.base.dev;
1181         struct drm_i915_private *dev_priv = dev->dev_private;
1182         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1183         u32 pp;
1184         u32 pp_ctrl_reg;
1185
1186         if (!is_edp(intel_dp))
1187                 return;
1188
1189         DRM_DEBUG_KMS("\n");
1190         /*
1191          * If we enable the backlight right away following a panel power
1192          * on, we may see slight flicker as the panel syncs with the eDP
1193          * link.  So delay a bit to make sure the image is solid before
1194          * allowing it to appear.
1195          */
1196         msleep(intel_dp->backlight_on_delay);
1197         pp = ironlake_get_pp_control(intel_dp);
1198         pp |= EDP_BLC_ENABLE;
1199
1200         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1201
1202         I915_WRITE(pp_ctrl_reg, pp);
1203         POSTING_READ(pp_ctrl_reg);
1204
1205         intel_panel_enable_backlight(dev, pipe);
1206 }
1207
1208 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1209 {
1210         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1211         struct drm_i915_private *dev_priv = dev->dev_private;
1212         u32 pp;
1213         u32 pp_ctrl_reg;
1214
1215         if (!is_edp(intel_dp))
1216                 return;
1217
1218         intel_panel_disable_backlight(dev);
1219
1220         DRM_DEBUG_KMS("\n");
1221         pp = ironlake_get_pp_control(intel_dp);
1222         pp &= ~EDP_BLC_ENABLE;
1223
1224         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1225
1226         I915_WRITE(pp_ctrl_reg, pp);
1227         POSTING_READ(pp_ctrl_reg);
1228         msleep(intel_dp->backlight_off_delay);
1229 }
1230
1231 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1232 {
1233         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1234         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1235         struct drm_device *dev = crtc->dev;
1236         struct drm_i915_private *dev_priv = dev->dev_private;
1237         u32 dpa_ctl;
1238
1239         assert_pipe_disabled(dev_priv,
1240                              to_intel_crtc(crtc)->pipe);
1241
1242         DRM_DEBUG_KMS("\n");
1243         dpa_ctl = I915_READ(DP_A);
1244         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1245         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1246
1247         /* We don't adjust intel_dp->DP while tearing down the link, to
1248          * facilitate link retraining (e.g. after hotplug). Hence clear all
1249          * enable bits here to ensure that we don't enable too much. */
1250         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1251         intel_dp->DP |= DP_PLL_ENABLE;
1252         I915_WRITE(DP_A, intel_dp->DP);
1253         POSTING_READ(DP_A);
1254         udelay(200);
1255 }
1256
1257 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1258 {
1259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1260         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1261         struct drm_device *dev = crtc->dev;
1262         struct drm_i915_private *dev_priv = dev->dev_private;
1263         u32 dpa_ctl;
1264
1265         assert_pipe_disabled(dev_priv,
1266                              to_intel_crtc(crtc)->pipe);
1267
1268         dpa_ctl = I915_READ(DP_A);
1269         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1270              "dp pll off, should be on\n");
1271         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1272
1273         /* We can't rely on the value tracked for the DP register in
1274          * intel_dp->DP because link_down must not change that (otherwise link
1275          * re-training will fail. */
1276         dpa_ctl &= ~DP_PLL_ENABLE;
1277         I915_WRITE(DP_A, dpa_ctl);
1278         POSTING_READ(DP_A);
1279         udelay(200);
1280 }
1281
1282 /* If the sink supports it, try to set the power state appropriately */
1283 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1284 {
1285         int ret, i;
1286
1287         /* Should have a valid DPCD by this point */
1288         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1289                 return;
1290
1291         if (mode != DRM_MODE_DPMS_ON) {
1292                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1293                                                   DP_SET_POWER_D3);
1294                 if (ret != 1)
1295                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1296         } else {
1297                 /*
1298                  * When turning on, we need to retry for 1ms to give the sink
1299                  * time to wake up.
1300                  */
1301                 for (i = 0; i < 3; i++) {
1302                         ret = intel_dp_aux_native_write_1(intel_dp,
1303                                                           DP_SET_POWER,
1304                                                           DP_SET_POWER_D0);
1305                         if (ret == 1)
1306                                 break;
1307                         msleep(1);
1308                 }
1309         }
1310 }
1311
1312 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1313                                   enum pipe *pipe)
1314 {
1315         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1316         enum port port = dp_to_dig_port(intel_dp)->port;
1317         struct drm_device *dev = encoder->base.dev;
1318         struct drm_i915_private *dev_priv = dev->dev_private;
1319         u32 tmp = I915_READ(intel_dp->output_reg);
1320
1321         if (!(tmp & DP_PORT_EN))
1322                 return false;
1323
1324         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1325                 *pipe = PORT_TO_PIPE_CPT(tmp);
1326         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1327                 *pipe = PORT_TO_PIPE(tmp);
1328         } else {
1329                 u32 trans_sel;
1330                 u32 trans_dp;
1331                 int i;
1332
1333                 switch (intel_dp->output_reg) {
1334                 case PCH_DP_B:
1335                         trans_sel = TRANS_DP_PORT_SEL_B;
1336                         break;
1337                 case PCH_DP_C:
1338                         trans_sel = TRANS_DP_PORT_SEL_C;
1339                         break;
1340                 case PCH_DP_D:
1341                         trans_sel = TRANS_DP_PORT_SEL_D;
1342                         break;
1343                 default:
1344                         return true;
1345                 }
1346
1347                 for_each_pipe(i) {
1348                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1349                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1350                                 *pipe = i;
1351                                 return true;
1352                         }
1353                 }
1354
1355                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1356                               intel_dp->output_reg);
1357         }
1358
1359         return true;
1360 }
1361
1362 static void intel_dp_get_config(struct intel_encoder *encoder,
1363                                 struct intel_crtc_config *pipe_config)
1364 {
1365         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1366         u32 tmp, flags = 0;
1367         struct drm_device *dev = encoder->base.dev;
1368         struct drm_i915_private *dev_priv = dev->dev_private;
1369         enum port port = dp_to_dig_port(intel_dp)->port;
1370         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1371
1372         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1373                 tmp = I915_READ(intel_dp->output_reg);
1374                 if (tmp & DP_SYNC_HS_HIGH)
1375                         flags |= DRM_MODE_FLAG_PHSYNC;
1376                 else
1377                         flags |= DRM_MODE_FLAG_NHSYNC;
1378
1379                 if (tmp & DP_SYNC_VS_HIGH)
1380                         flags |= DRM_MODE_FLAG_PVSYNC;
1381                 else
1382                         flags |= DRM_MODE_FLAG_NVSYNC;
1383         } else {
1384                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1385                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1386                         flags |= DRM_MODE_FLAG_PHSYNC;
1387                 else
1388                         flags |= DRM_MODE_FLAG_NHSYNC;
1389
1390                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1391                         flags |= DRM_MODE_FLAG_PVSYNC;
1392                 else
1393                         flags |= DRM_MODE_FLAG_NVSYNC;
1394         }
1395
1396         pipe_config->adjusted_mode.flags |= flags;
1397
1398         if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1399                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1400                         pipe_config->port_clock = 162000;
1401                 else
1402                         pipe_config->port_clock = 270000;
1403         }
1404
1405         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1406             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1407                 /*
1408                  * This is a big fat ugly hack.
1409                  *
1410                  * Some machines in UEFI boot mode provide us a VBT that has 18
1411                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1412                  * unknown we fail to light up. Yet the same BIOS boots up with
1413                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1414                  * max, not what it tells us to use.
1415                  *
1416                  * Note: This will still be broken if the eDP panel is not lit
1417                  * up by the BIOS, and thus we can't get the mode at module
1418                  * load.
1419                  */
1420                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1421                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1422                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1423         }
1424 }
1425
1426 static bool is_edp_psr(struct intel_dp *intel_dp)
1427 {
1428         return is_edp(intel_dp) &&
1429                 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1430 }
1431
1432 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1433 {
1434         struct drm_i915_private *dev_priv = dev->dev_private;
1435
1436         if (!IS_HASWELL(dev))
1437                 return false;
1438
1439         return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1440 }
1441
1442 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1443                                     struct edp_vsc_psr *vsc_psr)
1444 {
1445         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1446         struct drm_device *dev = dig_port->base.base.dev;
1447         struct drm_i915_private *dev_priv = dev->dev_private;
1448         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1449         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1450         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1451         uint32_t *data = (uint32_t *) vsc_psr;
1452         unsigned int i;
1453
1454         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1455            the video DIP being updated before program video DIP data buffer
1456            registers for DIP being updated. */
1457         I915_WRITE(ctl_reg, 0);
1458         POSTING_READ(ctl_reg);
1459
1460         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1461                 if (i < sizeof(struct edp_vsc_psr))
1462                         I915_WRITE(data_reg + i, *data++);
1463                 else
1464                         I915_WRITE(data_reg + i, 0);
1465         }
1466
1467         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1468         POSTING_READ(ctl_reg);
1469 }
1470
1471 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1472 {
1473         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1474         struct drm_i915_private *dev_priv = dev->dev_private;
1475         struct edp_vsc_psr psr_vsc;
1476
1477         if (intel_dp->psr_setup_done)
1478                 return;
1479
1480         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1481         memset(&psr_vsc, 0, sizeof(psr_vsc));
1482         psr_vsc.sdp_header.HB0 = 0;
1483         psr_vsc.sdp_header.HB1 = 0x7;
1484         psr_vsc.sdp_header.HB2 = 0x2;
1485         psr_vsc.sdp_header.HB3 = 0x8;
1486         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1487
1488         /* Avoid continuous PSR exit by masking memup and hpd */
1489         I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1490                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1491
1492         intel_dp->psr_setup_done = true;
1493 }
1494
1495 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1496 {
1497         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1500         int precharge = 0x3;
1501         int msg_size = 5;       /* Header(4) + Message(1) */
1502
1503         /* Enable PSR in sink */
1504         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1505                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1506                                             DP_PSR_ENABLE &
1507                                             ~DP_PSR_MAIN_LINK_ACTIVE);
1508         else
1509                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1510                                             DP_PSR_ENABLE |
1511                                             DP_PSR_MAIN_LINK_ACTIVE);
1512
1513         /* Setup AUX registers */
1514         I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1515         I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1516         I915_WRITE(EDP_PSR_AUX_CTL,
1517                    DP_AUX_CH_CTL_TIME_OUT_400us |
1518                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1519                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1520                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1521 }
1522
1523 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1524 {
1525         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1526         struct drm_i915_private *dev_priv = dev->dev_private;
1527         uint32_t max_sleep_time = 0x1f;
1528         uint32_t idle_frames = 1;
1529         uint32_t val = 0x0;
1530
1531         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1532                 val |= EDP_PSR_LINK_STANDBY;
1533                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1534                 val |= EDP_PSR_TP1_TIME_0us;
1535                 val |= EDP_PSR_SKIP_AUX_EXIT;
1536         } else
1537                 val |= EDP_PSR_LINK_DISABLE;
1538
1539         I915_WRITE(EDP_PSR_CTL, val |
1540                    EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1541                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1542                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1543                    EDP_PSR_ENABLE);
1544 }
1545
1546 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1547 {
1548         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1549         struct drm_device *dev = dig_port->base.base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         struct drm_crtc *crtc = dig_port->base.base.crtc;
1552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1553         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1554         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1555
1556         if (!IS_HASWELL(dev)) {
1557                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1558                 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1559                 return false;
1560         }
1561
1562         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1563             (dig_port->port != PORT_A)) {
1564                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1565                 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1566                 return false;
1567         }
1568
1569         if (!is_edp_psr(intel_dp)) {
1570                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1571                 dev_priv->no_psr_reason = PSR_NO_SINK;
1572                 return false;
1573         }
1574
1575         if (!i915_enable_psr) {
1576                 DRM_DEBUG_KMS("PSR disable by flag\n");
1577                 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1578                 return false;
1579         }
1580
1581         crtc = dig_port->base.base.crtc;
1582         if (crtc == NULL) {
1583                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1584                 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1585                 return false;
1586         }
1587
1588         intel_crtc = to_intel_crtc(crtc);
1589         if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1590                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1591                 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1592                 return false;
1593         }
1594
1595         obj = to_intel_framebuffer(crtc->fb)->obj;
1596         if (obj->tiling_mode != I915_TILING_X ||
1597             obj->fence_reg == I915_FENCE_REG_NONE) {
1598                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1599                 dev_priv->no_psr_reason = PSR_NOT_TILED;
1600                 return false;
1601         }
1602
1603         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1604                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1605                 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1606                 return false;
1607         }
1608
1609         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1610             S3D_ENABLE) {
1611                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1612                 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1613                 return false;
1614         }
1615
1616         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1617                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1618                 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1619                 return false;
1620         }
1621
1622         return true;
1623 }
1624
1625 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1626 {
1627         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1628
1629         if (!intel_edp_psr_match_conditions(intel_dp) ||
1630             intel_edp_is_psr_enabled(dev))
1631                 return;
1632
1633         /* Setup PSR once */
1634         intel_edp_psr_setup(intel_dp);
1635
1636         /* Enable PSR on the panel */
1637         intel_edp_psr_enable_sink(intel_dp);
1638
1639         /* Enable PSR on the host */
1640         intel_edp_psr_enable_source(intel_dp);
1641 }
1642
1643 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1644 {
1645         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1646
1647         if (intel_edp_psr_match_conditions(intel_dp) &&
1648             !intel_edp_is_psr_enabled(dev))
1649                 intel_edp_psr_do_enable(intel_dp);
1650 }
1651
1652 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1653 {
1654         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1655         struct drm_i915_private *dev_priv = dev->dev_private;
1656
1657         if (!intel_edp_is_psr_enabled(dev))
1658                 return;
1659
1660         I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1661
1662         /* Wait till PSR is idle */
1663         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1664                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1665                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1666 }
1667
1668 void intel_edp_psr_update(struct drm_device *dev)
1669 {
1670         struct intel_encoder *encoder;
1671         struct intel_dp *intel_dp = NULL;
1672
1673         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1674                 if (encoder->type == INTEL_OUTPUT_EDP) {
1675                         intel_dp = enc_to_intel_dp(&encoder->base);
1676
1677                         if (!is_edp_psr(intel_dp))
1678                                 return;
1679
1680                         if (!intel_edp_psr_match_conditions(intel_dp))
1681                                 intel_edp_psr_disable(intel_dp);
1682                         else
1683                                 if (!intel_edp_is_psr_enabled(dev))
1684                                         intel_edp_psr_do_enable(intel_dp);
1685                 }
1686 }
1687
1688 static void intel_disable_dp(struct intel_encoder *encoder)
1689 {
1690         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1691         enum port port = dp_to_dig_port(intel_dp)->port;
1692         struct drm_device *dev = encoder->base.dev;
1693
1694         /* Make sure the panel is off before trying to change the mode. But also
1695          * ensure that we have vdd while we switch off the panel. */
1696         ironlake_edp_panel_vdd_on(intel_dp);
1697         ironlake_edp_backlight_off(intel_dp);
1698         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1699         ironlake_edp_panel_off(intel_dp);
1700
1701         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1702         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1703                 intel_dp_link_down(intel_dp);
1704 }
1705
1706 static void intel_post_disable_dp(struct intel_encoder *encoder)
1707 {
1708         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1709         enum port port = dp_to_dig_port(intel_dp)->port;
1710         struct drm_device *dev = encoder->base.dev;
1711
1712         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1713                 intel_dp_link_down(intel_dp);
1714                 if (!IS_VALLEYVIEW(dev))
1715                         ironlake_edp_pll_off(intel_dp);
1716         }
1717 }
1718
1719 static void intel_enable_dp(struct intel_encoder *encoder)
1720 {
1721         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1722         struct drm_device *dev = encoder->base.dev;
1723         struct drm_i915_private *dev_priv = dev->dev_private;
1724         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1725
1726         if (WARN_ON(dp_reg & DP_PORT_EN))
1727                 return;
1728
1729         ironlake_edp_panel_vdd_on(intel_dp);
1730         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1731         intel_dp_start_link_train(intel_dp);
1732         ironlake_edp_panel_on(intel_dp);
1733         ironlake_edp_panel_vdd_off(intel_dp, true);
1734         intel_dp_complete_link_train(intel_dp);
1735         intel_dp_stop_link_train(intel_dp);
1736         ironlake_edp_backlight_on(intel_dp);
1737 }
1738
1739 static void vlv_enable_dp(struct intel_encoder *encoder)
1740 {
1741 }
1742
1743 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1744 {
1745         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1746         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1747
1748         if (dport->port == PORT_A)
1749                 ironlake_edp_pll_on(intel_dp);
1750 }
1751
1752 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1753 {
1754         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1755         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1756         struct drm_device *dev = encoder->base.dev;
1757         struct drm_i915_private *dev_priv = dev->dev_private;
1758         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1759         int port = vlv_dport_to_channel(dport);
1760         int pipe = intel_crtc->pipe;
1761         u32 val;
1762
1763         mutex_lock(&dev_priv->dpio_lock);
1764
1765         val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1766         val = 0;
1767         if (pipe)
1768                 val |= (1<<21);
1769         else
1770                 val &= ~(1<<21);
1771         val |= 0x001000c4;
1772         vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1773         vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1774         vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
1775
1776         mutex_unlock(&dev_priv->dpio_lock);
1777
1778         intel_enable_dp(encoder);
1779
1780         vlv_wait_port_ready(dev_priv, port);
1781 }
1782
1783 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1784 {
1785         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1786         struct drm_device *dev = encoder->base.dev;
1787         struct drm_i915_private *dev_priv = dev->dev_private;
1788         int port = vlv_dport_to_channel(dport);
1789
1790         if (!IS_VALLEYVIEW(dev))
1791                 return;
1792
1793         /* Program Tx lane resets to default */
1794         mutex_lock(&dev_priv->dpio_lock);
1795         vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1796                          DPIO_PCS_TX_LANE2_RESET |
1797                          DPIO_PCS_TX_LANE1_RESET);
1798         vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1799                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1800                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1801                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1802                                  DPIO_PCS_CLK_SOFT_RESET);
1803
1804         /* Fix up inter-pair skew failure */
1805         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1806         vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1807         vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1808         mutex_unlock(&dev_priv->dpio_lock);
1809 }
1810
1811 /*
1812  * Native read with retry for link status and receiver capability reads for
1813  * cases where the sink may still be asleep.
1814  */
1815 static bool
1816 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1817                                uint8_t *recv, int recv_bytes)
1818 {
1819         int ret, i;
1820
1821         /*
1822          * Sinks are *supposed* to come up within 1ms from an off state,
1823          * but we're also supposed to retry 3 times per the spec.
1824          */
1825         for (i = 0; i < 3; i++) {
1826                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1827                                                recv_bytes);
1828                 if (ret == recv_bytes)
1829                         return true;
1830                 msleep(1);
1831         }
1832
1833         return false;
1834 }
1835
1836 /*
1837  * Fetch AUX CH registers 0x202 - 0x207 which contain
1838  * link status information
1839  */
1840 static bool
1841 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1842 {
1843         return intel_dp_aux_native_read_retry(intel_dp,
1844                                               DP_LANE0_1_STATUS,
1845                                               link_status,
1846                                               DP_LINK_STATUS_SIZE);
1847 }
1848
1849 #if 0
1850 static char     *voltage_names[] = {
1851         "0.4V", "0.6V", "0.8V", "1.2V"
1852 };
1853 static char     *pre_emph_names[] = {
1854         "0dB", "3.5dB", "6dB", "9.5dB"
1855 };
1856 static char     *link_train_names[] = {
1857         "pattern 1", "pattern 2", "idle", "off"
1858 };
1859 #endif
1860
1861 /*
1862  * These are source-specific values; current Intel hardware supports
1863  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1864  */
1865
1866 static uint8_t
1867 intel_dp_voltage_max(struct intel_dp *intel_dp)
1868 {
1869         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1870         enum port port = dp_to_dig_port(intel_dp)->port;
1871
1872         if (IS_VALLEYVIEW(dev))
1873                 return DP_TRAIN_VOLTAGE_SWING_1200;
1874         else if (IS_GEN7(dev) && port == PORT_A)
1875                 return DP_TRAIN_VOLTAGE_SWING_800;
1876         else if (HAS_PCH_CPT(dev) && port != PORT_A)
1877                 return DP_TRAIN_VOLTAGE_SWING_1200;
1878         else
1879                 return DP_TRAIN_VOLTAGE_SWING_800;
1880 }
1881
1882 static uint8_t
1883 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1884 {
1885         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1886         enum port port = dp_to_dig_port(intel_dp)->port;
1887
1888         if (HAS_DDI(dev)) {
1889                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1890                 case DP_TRAIN_VOLTAGE_SWING_400:
1891                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1892                 case DP_TRAIN_VOLTAGE_SWING_600:
1893                         return DP_TRAIN_PRE_EMPHASIS_6;
1894                 case DP_TRAIN_VOLTAGE_SWING_800:
1895                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1896                 case DP_TRAIN_VOLTAGE_SWING_1200:
1897                 default:
1898                         return DP_TRAIN_PRE_EMPHASIS_0;
1899                 }
1900         } else if (IS_VALLEYVIEW(dev)) {
1901                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1902                 case DP_TRAIN_VOLTAGE_SWING_400:
1903                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1904                 case DP_TRAIN_VOLTAGE_SWING_600:
1905                         return DP_TRAIN_PRE_EMPHASIS_6;
1906                 case DP_TRAIN_VOLTAGE_SWING_800:
1907                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1908                 case DP_TRAIN_VOLTAGE_SWING_1200:
1909                 default:
1910                         return DP_TRAIN_PRE_EMPHASIS_0;
1911                 }
1912         } else if (IS_GEN7(dev) && port == PORT_A) {
1913                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1914                 case DP_TRAIN_VOLTAGE_SWING_400:
1915                         return DP_TRAIN_PRE_EMPHASIS_6;
1916                 case DP_TRAIN_VOLTAGE_SWING_600:
1917                 case DP_TRAIN_VOLTAGE_SWING_800:
1918                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1919                 default:
1920                         return DP_TRAIN_PRE_EMPHASIS_0;
1921                 }
1922         } else {
1923                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1924                 case DP_TRAIN_VOLTAGE_SWING_400:
1925                         return DP_TRAIN_PRE_EMPHASIS_6;
1926                 case DP_TRAIN_VOLTAGE_SWING_600:
1927                         return DP_TRAIN_PRE_EMPHASIS_6;
1928                 case DP_TRAIN_VOLTAGE_SWING_800:
1929                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1930                 case DP_TRAIN_VOLTAGE_SWING_1200:
1931                 default:
1932                         return DP_TRAIN_PRE_EMPHASIS_0;
1933                 }
1934         }
1935 }
1936
1937 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1938 {
1939         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1940         struct drm_i915_private *dev_priv = dev->dev_private;
1941         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1942         unsigned long demph_reg_value, preemph_reg_value,
1943                 uniqtranscale_reg_value;
1944         uint8_t train_set = intel_dp->train_set[0];
1945         int port = vlv_dport_to_channel(dport);
1946
1947         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1948         case DP_TRAIN_PRE_EMPHASIS_0:
1949                 preemph_reg_value = 0x0004000;
1950                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1951                 case DP_TRAIN_VOLTAGE_SWING_400:
1952                         demph_reg_value = 0x2B405555;
1953                         uniqtranscale_reg_value = 0x552AB83A;
1954                         break;
1955                 case DP_TRAIN_VOLTAGE_SWING_600:
1956                         demph_reg_value = 0x2B404040;
1957                         uniqtranscale_reg_value = 0x5548B83A;
1958                         break;
1959                 case DP_TRAIN_VOLTAGE_SWING_800:
1960                         demph_reg_value = 0x2B245555;
1961                         uniqtranscale_reg_value = 0x5560B83A;
1962                         break;
1963                 case DP_TRAIN_VOLTAGE_SWING_1200:
1964                         demph_reg_value = 0x2B405555;
1965                         uniqtranscale_reg_value = 0x5598DA3A;
1966                         break;
1967                 default:
1968                         return 0;
1969                 }
1970                 break;
1971         case DP_TRAIN_PRE_EMPHASIS_3_5:
1972                 preemph_reg_value = 0x0002000;
1973                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1974                 case DP_TRAIN_VOLTAGE_SWING_400:
1975                         demph_reg_value = 0x2B404040;
1976                         uniqtranscale_reg_value = 0x5552B83A;
1977                         break;
1978                 case DP_TRAIN_VOLTAGE_SWING_600:
1979                         demph_reg_value = 0x2B404848;
1980                         uniqtranscale_reg_value = 0x5580B83A;
1981                         break;
1982                 case DP_TRAIN_VOLTAGE_SWING_800:
1983                         demph_reg_value = 0x2B404040;
1984                         uniqtranscale_reg_value = 0x55ADDA3A;
1985                         break;
1986                 default:
1987                         return 0;
1988                 }
1989                 break;
1990         case DP_TRAIN_PRE_EMPHASIS_6:
1991                 preemph_reg_value = 0x0000000;
1992                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1993                 case DP_TRAIN_VOLTAGE_SWING_400:
1994                         demph_reg_value = 0x2B305555;
1995                         uniqtranscale_reg_value = 0x5570B83A;
1996                         break;
1997                 case DP_TRAIN_VOLTAGE_SWING_600:
1998                         demph_reg_value = 0x2B2B4040;
1999                         uniqtranscale_reg_value = 0x55ADDA3A;
2000                         break;
2001                 default:
2002                         return 0;
2003                 }
2004                 break;
2005         case DP_TRAIN_PRE_EMPHASIS_9_5:
2006                 preemph_reg_value = 0x0006000;
2007                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2008                 case DP_TRAIN_VOLTAGE_SWING_400:
2009                         demph_reg_value = 0x1B405555;
2010                         uniqtranscale_reg_value = 0x55ADDA3A;
2011                         break;
2012                 default:
2013                         return 0;
2014                 }
2015                 break;
2016         default:
2017                 return 0;
2018         }
2019
2020         mutex_lock(&dev_priv->dpio_lock);
2021         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
2022         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2023         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
2024                          uniqtranscale_reg_value);
2025         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2026         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
2027         vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2028         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
2029         mutex_unlock(&dev_priv->dpio_lock);
2030
2031         return 0;
2032 }
2033
2034 static void
2035 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2036 {
2037         uint8_t v = 0;
2038         uint8_t p = 0;
2039         int lane;
2040         uint8_t voltage_max;
2041         uint8_t preemph_max;
2042
2043         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2044                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2045                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2046
2047                 if (this_v > v)
2048                         v = this_v;
2049                 if (this_p > p)
2050                         p = this_p;
2051         }
2052
2053         voltage_max = intel_dp_voltage_max(intel_dp);
2054         if (v >= voltage_max)
2055                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2056
2057         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2058         if (p >= preemph_max)
2059                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2060
2061         for (lane = 0; lane < 4; lane++)
2062                 intel_dp->train_set[lane] = v | p;
2063 }
2064
2065 static uint32_t
2066 intel_gen4_signal_levels(uint8_t train_set)
2067 {
2068         uint32_t        signal_levels = 0;
2069
2070         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2071         case DP_TRAIN_VOLTAGE_SWING_400:
2072         default:
2073                 signal_levels |= DP_VOLTAGE_0_4;
2074                 break;
2075         case DP_TRAIN_VOLTAGE_SWING_600:
2076                 signal_levels |= DP_VOLTAGE_0_6;
2077                 break;
2078         case DP_TRAIN_VOLTAGE_SWING_800:
2079                 signal_levels |= DP_VOLTAGE_0_8;
2080                 break;
2081         case DP_TRAIN_VOLTAGE_SWING_1200:
2082                 signal_levels |= DP_VOLTAGE_1_2;
2083                 break;
2084         }
2085         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2086         case DP_TRAIN_PRE_EMPHASIS_0:
2087         default:
2088                 signal_levels |= DP_PRE_EMPHASIS_0;
2089                 break;
2090         case DP_TRAIN_PRE_EMPHASIS_3_5:
2091                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2092                 break;
2093         case DP_TRAIN_PRE_EMPHASIS_6:
2094                 signal_levels |= DP_PRE_EMPHASIS_6;
2095                 break;
2096         case DP_TRAIN_PRE_EMPHASIS_9_5:
2097                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2098                 break;
2099         }
2100         return signal_levels;
2101 }
2102
2103 /* Gen6's DP voltage swing and pre-emphasis control */
2104 static uint32_t
2105 intel_gen6_edp_signal_levels(uint8_t train_set)
2106 {
2107         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2108                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2109         switch (signal_levels) {
2110         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2111         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2112                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2113         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2114                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2115         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2116         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2117                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2118         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2119         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2120                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2121         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2122         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2123                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2124         default:
2125                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2126                               "0x%x\n", signal_levels);
2127                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2128         }
2129 }
2130
2131 /* Gen7's DP voltage swing and pre-emphasis control */
2132 static uint32_t
2133 intel_gen7_edp_signal_levels(uint8_t train_set)
2134 {
2135         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2136                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2137         switch (signal_levels) {
2138         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2139                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2140         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2141                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2142         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2143                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2144
2145         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2146                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2147         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2148                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2149
2150         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2151                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2152         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2153                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2154
2155         default:
2156                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2157                               "0x%x\n", signal_levels);
2158                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2159         }
2160 }
2161
2162 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2163 static uint32_t
2164 intel_hsw_signal_levels(uint8_t train_set)
2165 {
2166         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2167                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2168         switch (signal_levels) {
2169         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2170                 return DDI_BUF_EMP_400MV_0DB_HSW;
2171         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2172                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2173         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2174                 return DDI_BUF_EMP_400MV_6DB_HSW;
2175         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2176                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2177
2178         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2179                 return DDI_BUF_EMP_600MV_0DB_HSW;
2180         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2181                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2182         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2183                 return DDI_BUF_EMP_600MV_6DB_HSW;
2184
2185         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2186                 return DDI_BUF_EMP_800MV_0DB_HSW;
2187         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2188                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2189         default:
2190                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2191                               "0x%x\n", signal_levels);
2192                 return DDI_BUF_EMP_400MV_0DB_HSW;
2193         }
2194 }
2195
2196 /* Properly updates "DP" with the correct signal levels. */
2197 static void
2198 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2199 {
2200         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2201         enum port port = intel_dig_port->port;
2202         struct drm_device *dev = intel_dig_port->base.base.dev;
2203         uint32_t signal_levels, mask;
2204         uint8_t train_set = intel_dp->train_set[0];
2205
2206         if (HAS_DDI(dev)) {
2207                 signal_levels = intel_hsw_signal_levels(train_set);
2208                 mask = DDI_BUF_EMP_MASK;
2209         } else if (IS_VALLEYVIEW(dev)) {
2210                 signal_levels = intel_vlv_signal_levels(intel_dp);
2211                 mask = 0;
2212         } else if (IS_GEN7(dev) && port == PORT_A) {
2213                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2214                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2215         } else if (IS_GEN6(dev) && port == PORT_A) {
2216                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2217                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2218         } else {
2219                 signal_levels = intel_gen4_signal_levels(train_set);
2220                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2221         }
2222
2223         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2224
2225         *DP = (*DP & ~mask) | signal_levels;
2226 }
2227
2228 static bool
2229 intel_dp_set_link_train(struct intel_dp *intel_dp,
2230                         uint32_t dp_reg_value,
2231                         uint8_t dp_train_pat)
2232 {
2233         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2234         struct drm_device *dev = intel_dig_port->base.base.dev;
2235         struct drm_i915_private *dev_priv = dev->dev_private;
2236         enum port port = intel_dig_port->port;
2237         int ret;
2238
2239         if (HAS_DDI(dev)) {
2240                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2241
2242                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2243                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2244                 else
2245                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2246
2247                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2248                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2249                 case DP_TRAINING_PATTERN_DISABLE:
2250                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2251
2252                         break;
2253                 case DP_TRAINING_PATTERN_1:
2254                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2255                         break;
2256                 case DP_TRAINING_PATTERN_2:
2257                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2258                         break;
2259                 case DP_TRAINING_PATTERN_3:
2260                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2261                         break;
2262                 }
2263                 I915_WRITE(DP_TP_CTL(port), temp);
2264
2265         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2266                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2267
2268                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2269                 case DP_TRAINING_PATTERN_DISABLE:
2270                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2271                         break;
2272                 case DP_TRAINING_PATTERN_1:
2273                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2274                         break;
2275                 case DP_TRAINING_PATTERN_2:
2276                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2277                         break;
2278                 case DP_TRAINING_PATTERN_3:
2279                         DRM_ERROR("DP training pattern 3 not supported\n");
2280                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2281                         break;
2282                 }
2283
2284         } else {
2285                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2286
2287                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2288                 case DP_TRAINING_PATTERN_DISABLE:
2289                         dp_reg_value |= DP_LINK_TRAIN_OFF;
2290                         break;
2291                 case DP_TRAINING_PATTERN_1:
2292                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2293                         break;
2294                 case DP_TRAINING_PATTERN_2:
2295                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2296                         break;
2297                 case DP_TRAINING_PATTERN_3:
2298                         DRM_ERROR("DP training pattern 3 not supported\n");
2299                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2300                         break;
2301                 }
2302         }
2303
2304         I915_WRITE(intel_dp->output_reg, dp_reg_value);
2305         POSTING_READ(intel_dp->output_reg);
2306
2307         intel_dp_aux_native_write_1(intel_dp,
2308                                     DP_TRAINING_PATTERN_SET,
2309                                     dp_train_pat);
2310
2311         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2312             DP_TRAINING_PATTERN_DISABLE) {
2313                 ret = intel_dp_aux_native_write(intel_dp,
2314                                                 DP_TRAINING_LANE0_SET,
2315                                                 intel_dp->train_set,
2316                                                 intel_dp->lane_count);
2317                 if (ret != intel_dp->lane_count)
2318                         return false;
2319         }
2320
2321         return true;
2322 }
2323
2324 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2325 {
2326         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2327         struct drm_device *dev = intel_dig_port->base.base.dev;
2328         struct drm_i915_private *dev_priv = dev->dev_private;
2329         enum port port = intel_dig_port->port;
2330         uint32_t val;
2331
2332         if (!HAS_DDI(dev))
2333                 return;
2334
2335         val = I915_READ(DP_TP_CTL(port));
2336         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2337         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2338         I915_WRITE(DP_TP_CTL(port), val);
2339
2340         /*
2341          * On PORT_A we can have only eDP in SST mode. There the only reason
2342          * we need to set idle transmission mode is to work around a HW issue
2343          * where we enable the pipe while not in idle link-training mode.
2344          * In this case there is requirement to wait for a minimum number of
2345          * idle patterns to be sent.
2346          */
2347         if (port == PORT_A)
2348                 return;
2349
2350         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2351                      1))
2352                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2353 }
2354
2355 /* Enable corresponding port and start training pattern 1 */
2356 void
2357 intel_dp_start_link_train(struct intel_dp *intel_dp)
2358 {
2359         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2360         struct drm_device *dev = encoder->dev;
2361         int i;
2362         uint8_t voltage;
2363         int voltage_tries, loop_tries;
2364         uint32_t DP = intel_dp->DP;
2365
2366         if (HAS_DDI(dev))
2367                 intel_ddi_prepare_link_retrain(encoder);
2368
2369         /* Write the link configuration data */
2370         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2371                                   intel_dp->link_configuration,
2372                                   DP_LINK_CONFIGURATION_SIZE);
2373
2374         DP |= DP_PORT_EN;
2375
2376         memset(intel_dp->train_set, 0, 4);
2377         voltage = 0xff;
2378         voltage_tries = 0;
2379         loop_tries = 0;
2380         for (;;) {
2381                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2382                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2383
2384                 intel_dp_set_signal_levels(intel_dp, &DP);
2385
2386                 /* Set training pattern 1 */
2387                 if (!intel_dp_set_link_train(intel_dp, DP,
2388                                              DP_TRAINING_PATTERN_1 |
2389                                              DP_LINK_SCRAMBLING_DISABLE))
2390                         break;
2391
2392                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2393                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2394                         DRM_ERROR("failed to get link status\n");
2395                         break;
2396                 }
2397
2398                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2399                         DRM_DEBUG_KMS("clock recovery OK\n");
2400                         break;
2401                 }
2402
2403                 /* Check to see if we've tried the max voltage */
2404                 for (i = 0; i < intel_dp->lane_count; i++)
2405                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2406                                 break;
2407                 if (i == intel_dp->lane_count) {
2408                         ++loop_tries;
2409                         if (loop_tries == 5) {
2410                                 DRM_DEBUG_KMS("too many full retries, give up\n");
2411                                 break;
2412                         }
2413                         memset(intel_dp->train_set, 0, 4);
2414                         voltage_tries = 0;
2415                         continue;
2416                 }
2417
2418                 /* Check to see if we've tried the same voltage 5 times */
2419                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2420                         ++voltage_tries;
2421                         if (voltage_tries == 5) {
2422                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2423                                 break;
2424                         }
2425                 } else
2426                         voltage_tries = 0;
2427                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2428
2429                 /* Compute new intel_dp->train_set as requested by target */
2430                 intel_get_adjust_train(intel_dp, link_status);
2431         }
2432
2433         intel_dp->DP = DP;
2434 }
2435
2436 void
2437 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2438 {
2439         bool channel_eq = false;
2440         int tries, cr_tries;
2441         uint32_t DP = intel_dp->DP;
2442
2443         /* channel equalization */
2444         tries = 0;
2445         cr_tries = 0;
2446         channel_eq = false;
2447         for (;;) {
2448                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2449
2450                 if (cr_tries > 5) {
2451                         DRM_ERROR("failed to train DP, aborting\n");
2452                         intel_dp_link_down(intel_dp);
2453                         break;
2454                 }
2455
2456                 intel_dp_set_signal_levels(intel_dp, &DP);
2457
2458                 /* channel eq pattern */
2459                 if (!intel_dp_set_link_train(intel_dp, DP,
2460                                              DP_TRAINING_PATTERN_2 |
2461                                              DP_LINK_SCRAMBLING_DISABLE))
2462                         break;
2463
2464                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2465                 if (!intel_dp_get_link_status(intel_dp, link_status))
2466                         break;
2467
2468                 /* Make sure clock is still ok */
2469                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2470                         intel_dp_start_link_train(intel_dp);
2471                         cr_tries++;
2472                         continue;
2473                 }
2474
2475                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2476                         channel_eq = true;
2477                         break;
2478                 }
2479
2480                 /* Try 5 times, then try clock recovery if that fails */
2481                 if (tries > 5) {
2482                         intel_dp_link_down(intel_dp);
2483                         intel_dp_start_link_train(intel_dp);
2484                         tries = 0;
2485                         cr_tries++;
2486                         continue;
2487                 }
2488
2489                 /* Compute new intel_dp->train_set as requested by target */
2490                 intel_get_adjust_train(intel_dp, link_status);
2491                 ++tries;
2492         }
2493
2494         intel_dp_set_idle_link_train(intel_dp);
2495
2496         intel_dp->DP = DP;
2497
2498         if (channel_eq)
2499                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2500
2501 }
2502
2503 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2504 {
2505         intel_dp_set_link_train(intel_dp, intel_dp->DP,
2506                                 DP_TRAINING_PATTERN_DISABLE);
2507 }
2508
2509 static void
2510 intel_dp_link_down(struct intel_dp *intel_dp)
2511 {
2512         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2513         enum port port = intel_dig_port->port;
2514         struct drm_device *dev = intel_dig_port->base.base.dev;
2515         struct drm_i915_private *dev_priv = dev->dev_private;
2516         struct intel_crtc *intel_crtc =
2517                 to_intel_crtc(intel_dig_port->base.base.crtc);
2518         uint32_t DP = intel_dp->DP;
2519
2520         /*
2521          * DDI code has a strict mode set sequence and we should try to respect
2522          * it, otherwise we might hang the machine in many different ways. So we
2523          * really should be disabling the port only on a complete crtc_disable
2524          * sequence. This function is just called under two conditions on DDI
2525          * code:
2526          * - Link train failed while doing crtc_enable, and on this case we
2527          *   really should respect the mode set sequence and wait for a
2528          *   crtc_disable.
2529          * - Someone turned the monitor off and intel_dp_check_link_status
2530          *   called us. We don't need to disable the whole port on this case, so
2531          *   when someone turns the monitor on again,
2532          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2533          *   train.
2534          */
2535         if (HAS_DDI(dev))
2536                 return;
2537
2538         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2539                 return;
2540
2541         DRM_DEBUG_KMS("\n");
2542
2543         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2544                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2545                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2546         } else {
2547                 DP &= ~DP_LINK_TRAIN_MASK;
2548                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2549         }
2550         POSTING_READ(intel_dp->output_reg);
2551
2552         /* We don't really know why we're doing this */
2553         intel_wait_for_vblank(dev, intel_crtc->pipe);
2554
2555         if (HAS_PCH_IBX(dev) &&
2556             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2557                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2558
2559                 /* Hardware workaround: leaving our transcoder select
2560                  * set to transcoder B while it's off will prevent the
2561                  * corresponding HDMI output on transcoder A.
2562                  *
2563                  * Combine this with another hardware workaround:
2564                  * transcoder select bit can only be cleared while the
2565                  * port is enabled.
2566                  */
2567                 DP &= ~DP_PIPEB_SELECT;
2568                 I915_WRITE(intel_dp->output_reg, DP);
2569
2570                 /* Changes to enable or select take place the vblank
2571                  * after being written.
2572                  */
2573                 if (WARN_ON(crtc == NULL)) {
2574                         /* We should never try to disable a port without a crtc
2575                          * attached. For paranoia keep the code around for a
2576                          * bit. */
2577                         POSTING_READ(intel_dp->output_reg);
2578                         msleep(50);
2579                 } else
2580                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2581         }
2582
2583         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2584         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2585         POSTING_READ(intel_dp->output_reg);
2586         msleep(intel_dp->panel_power_down_delay);
2587 }
2588
2589 static bool
2590 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2591 {
2592         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2593
2594         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2595                                            sizeof(intel_dp->dpcd)) == 0)
2596                 return false; /* aux transfer failed */
2597
2598         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2599                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2600         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2601
2602         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2603                 return false; /* DPCD not present */
2604
2605         /* Check if the panel supports PSR */
2606         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2607         intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2608                                        intel_dp->psr_dpcd,
2609                                        sizeof(intel_dp->psr_dpcd));
2610         if (is_edp_psr(intel_dp))
2611                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2612         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2613               DP_DWN_STRM_PORT_PRESENT))
2614                 return true; /* native DP sink */
2615
2616         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2617                 return true; /* no per-port downstream info */
2618
2619         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2620                                            intel_dp->downstream_ports,
2621                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2622                 return false; /* downstream port status fetch failed */
2623
2624         return true;
2625 }
2626
2627 static void
2628 intel_dp_probe_oui(struct intel_dp *intel_dp)
2629 {
2630         u8 buf[3];
2631
2632         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2633                 return;
2634
2635         ironlake_edp_panel_vdd_on(intel_dp);
2636
2637         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2638                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2639                               buf[0], buf[1], buf[2]);
2640
2641         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2642                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2643                               buf[0], buf[1], buf[2]);
2644
2645         ironlake_edp_panel_vdd_off(intel_dp, false);
2646 }
2647
2648 static bool
2649 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2650 {
2651         int ret;
2652
2653         ret = intel_dp_aux_native_read_retry(intel_dp,
2654                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2655                                              sink_irq_vector, 1);
2656         if (!ret)
2657                 return false;
2658
2659         return true;
2660 }
2661
2662 static void
2663 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2664 {
2665         /* NAK by default */
2666         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2667 }
2668
2669 /*
2670  * According to DP spec
2671  * 5.1.2:
2672  *  1. Read DPCD
2673  *  2. Configure link according to Receiver Capabilities
2674  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2675  *  4. Check link status on receipt of hot-plug interrupt
2676  */
2677
2678 void
2679 intel_dp_check_link_status(struct intel_dp *intel_dp)
2680 {
2681         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2682         u8 sink_irq_vector;
2683         u8 link_status[DP_LINK_STATUS_SIZE];
2684
2685         if (!intel_encoder->connectors_active)
2686                 return;
2687
2688         if (WARN_ON(!intel_encoder->base.crtc))
2689                 return;
2690
2691         /* Try to read receiver status if the link appears to be up */
2692         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2693                 intel_dp_link_down(intel_dp);
2694                 return;
2695         }
2696
2697         /* Now read the DPCD to see if it's actually running */
2698         if (!intel_dp_get_dpcd(intel_dp)) {
2699                 intel_dp_link_down(intel_dp);
2700                 return;
2701         }
2702
2703         /* Try to read the source of the interrupt */
2704         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2705             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2706                 /* Clear interrupt source */
2707                 intel_dp_aux_native_write_1(intel_dp,
2708                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2709                                             sink_irq_vector);
2710
2711                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2712                         intel_dp_handle_test_request(intel_dp);
2713                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2714                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2715         }
2716
2717         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2718                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2719                               drm_get_encoder_name(&intel_encoder->base));
2720                 intel_dp_start_link_train(intel_dp);
2721                 intel_dp_complete_link_train(intel_dp);
2722                 intel_dp_stop_link_train(intel_dp);
2723         }
2724 }
2725
2726 /* XXX this is probably wrong for multiple downstream ports */
2727 static enum drm_connector_status
2728 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2729 {
2730         uint8_t *dpcd = intel_dp->dpcd;
2731         bool hpd;
2732         uint8_t type;
2733
2734         if (!intel_dp_get_dpcd(intel_dp))
2735                 return connector_status_disconnected;
2736
2737         /* if there's no downstream port, we're done */
2738         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2739                 return connector_status_connected;
2740
2741         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2742         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2743         if (hpd) {
2744                 uint8_t reg;
2745                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2746                                                     &reg, 1))
2747                         return connector_status_unknown;
2748                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2749                                               : connector_status_disconnected;
2750         }
2751
2752         /* If no HPD, poke DDC gently */
2753         if (drm_probe_ddc(&intel_dp->adapter))
2754                 return connector_status_connected;
2755
2756         /* Well we tried, say unknown for unreliable port types */
2757         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2758         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2759                 return connector_status_unknown;
2760
2761         /* Anything else is out of spec, warn and ignore */
2762         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2763         return connector_status_disconnected;
2764 }
2765
2766 static enum drm_connector_status
2767 ironlake_dp_detect(struct intel_dp *intel_dp)
2768 {
2769         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2772         enum drm_connector_status status;
2773
2774         /* Can't disconnect eDP, but you can close the lid... */
2775         if (is_edp(intel_dp)) {
2776                 status = intel_panel_detect(dev);
2777                 if (status == connector_status_unknown)
2778                         status = connector_status_connected;
2779                 return status;
2780         }
2781
2782         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2783                 return connector_status_disconnected;
2784
2785         return intel_dp_detect_dpcd(intel_dp);
2786 }
2787
2788 static enum drm_connector_status
2789 g4x_dp_detect(struct intel_dp *intel_dp)
2790 {
2791         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2792         struct drm_i915_private *dev_priv = dev->dev_private;
2793         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2794         uint32_t bit;
2795
2796         /* Can't disconnect eDP, but you can close the lid... */
2797         if (is_edp(intel_dp)) {
2798                 enum drm_connector_status status;
2799
2800                 status = intel_panel_detect(dev);
2801                 if (status == connector_status_unknown)
2802                         status = connector_status_connected;
2803                 return status;
2804         }
2805
2806         switch (intel_dig_port->port) {
2807         case PORT_B:
2808                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2809                 break;
2810         case PORT_C:
2811                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2812                 break;
2813         case PORT_D:
2814                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2815                 break;
2816         default:
2817                 return connector_status_unknown;
2818         }
2819
2820         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2821                 return connector_status_disconnected;
2822
2823         return intel_dp_detect_dpcd(intel_dp);
2824 }
2825
2826 static struct edid *
2827 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2828 {
2829         struct intel_connector *intel_connector = to_intel_connector(connector);
2830
2831         /* use cached edid if we have one */
2832         if (intel_connector->edid) {
2833                 struct edid *edid;
2834                 int size;
2835
2836                 /* invalid edid */
2837                 if (IS_ERR(intel_connector->edid))
2838                         return NULL;
2839
2840                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2841                 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2842                 if (!edid)
2843                         return NULL;
2844
2845                 return edid;
2846         }
2847
2848         return drm_get_edid(connector, adapter);
2849 }
2850
2851 static int
2852 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2853 {
2854         struct intel_connector *intel_connector = to_intel_connector(connector);
2855
2856         /* use cached edid if we have one */
2857         if (intel_connector->edid) {
2858                 /* invalid edid */
2859                 if (IS_ERR(intel_connector->edid))
2860                         return 0;
2861
2862                 return intel_connector_update_modes(connector,
2863                                                     intel_connector->edid);
2864         }
2865
2866         return intel_ddc_get_modes(connector, adapter);
2867 }
2868
2869 static enum drm_connector_status
2870 intel_dp_detect(struct drm_connector *connector, bool force)
2871 {
2872         struct intel_dp *intel_dp = intel_attached_dp(connector);
2873         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2874         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2875         struct drm_device *dev = connector->dev;
2876         enum drm_connector_status status;
2877         struct edid *edid = NULL;
2878
2879         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2880                       connector->base.id, drm_get_connector_name(connector));
2881
2882         intel_dp->has_audio = false;
2883
2884         if (HAS_PCH_SPLIT(dev))
2885                 status = ironlake_dp_detect(intel_dp);
2886         else
2887                 status = g4x_dp_detect(intel_dp);
2888
2889         if (status != connector_status_connected)
2890                 return status;
2891
2892         intel_dp_probe_oui(intel_dp);
2893
2894         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2895                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2896         } else {
2897                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2898                 if (edid) {
2899                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2900                         kfree(edid);
2901                 }
2902         }
2903
2904         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2905                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2906         return connector_status_connected;
2907 }
2908
2909 static int intel_dp_get_modes(struct drm_connector *connector)
2910 {
2911         struct intel_dp *intel_dp = intel_attached_dp(connector);
2912         struct intel_connector *intel_connector = to_intel_connector(connector);
2913         struct drm_device *dev = connector->dev;
2914         int ret;
2915
2916         /* We should parse the EDID data and find out if it has an audio sink
2917          */
2918
2919         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2920         if (ret)
2921                 return ret;
2922
2923         /* if eDP has no EDID, fall back to fixed mode */
2924         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2925                 struct drm_display_mode *mode;
2926                 mode = drm_mode_duplicate(dev,
2927                                           intel_connector->panel.fixed_mode);
2928                 if (mode) {
2929                         drm_mode_probed_add(connector, mode);
2930                         return 1;
2931                 }
2932         }
2933         return 0;
2934 }
2935
2936 static bool
2937 intel_dp_detect_audio(struct drm_connector *connector)
2938 {
2939         struct intel_dp *intel_dp = intel_attached_dp(connector);
2940         struct edid *edid;
2941         bool has_audio = false;
2942
2943         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2944         if (edid) {
2945                 has_audio = drm_detect_monitor_audio(edid);
2946                 kfree(edid);
2947         }
2948
2949         return has_audio;
2950 }
2951
2952 static int
2953 intel_dp_set_property(struct drm_connector *connector,
2954                       struct drm_property *property,
2955                       uint64_t val)
2956 {
2957         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2958         struct intel_connector *intel_connector = to_intel_connector(connector);
2959         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2960         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2961         int ret;
2962
2963         ret = drm_object_property_set_value(&connector->base, property, val);
2964         if (ret)
2965                 return ret;
2966
2967         if (property == dev_priv->force_audio_property) {
2968                 int i = val;
2969                 bool has_audio;
2970
2971                 if (i == intel_dp->force_audio)
2972                         return 0;
2973
2974                 intel_dp->force_audio = i;
2975
2976                 if (i == HDMI_AUDIO_AUTO)
2977                         has_audio = intel_dp_detect_audio(connector);
2978                 else
2979                         has_audio = (i == HDMI_AUDIO_ON);
2980
2981                 if (has_audio == intel_dp->has_audio)
2982                         return 0;
2983
2984                 intel_dp->has_audio = has_audio;
2985                 goto done;
2986         }
2987
2988         if (property == dev_priv->broadcast_rgb_property) {
2989                 bool old_auto = intel_dp->color_range_auto;
2990                 uint32_t old_range = intel_dp->color_range;
2991
2992                 switch (val) {
2993                 case INTEL_BROADCAST_RGB_AUTO:
2994                         intel_dp->color_range_auto = true;
2995                         break;
2996                 case INTEL_BROADCAST_RGB_FULL:
2997                         intel_dp->color_range_auto = false;
2998                         intel_dp->color_range = 0;
2999                         break;
3000                 case INTEL_BROADCAST_RGB_LIMITED:
3001                         intel_dp->color_range_auto = false;
3002                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3003                         break;
3004                 default:
3005                         return -EINVAL;
3006                 }
3007
3008                 if (old_auto == intel_dp->color_range_auto &&
3009                     old_range == intel_dp->color_range)
3010                         return 0;
3011
3012                 goto done;
3013         }
3014
3015         if (is_edp(intel_dp) &&
3016             property == connector->dev->mode_config.scaling_mode_property) {
3017                 if (val == DRM_MODE_SCALE_NONE) {
3018                         DRM_DEBUG_KMS("no scaling not supported\n");
3019                         return -EINVAL;
3020                 }
3021
3022                 if (intel_connector->panel.fitting_mode == val) {
3023                         /* the eDP scaling property is not changed */
3024                         return 0;
3025                 }
3026                 intel_connector->panel.fitting_mode = val;
3027
3028                 goto done;
3029         }
3030
3031         return -EINVAL;
3032
3033 done:
3034         if (intel_encoder->base.crtc)
3035                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3036
3037         return 0;
3038 }
3039
3040 static void
3041 intel_dp_connector_destroy(struct drm_connector *connector)
3042 {
3043         struct intel_connector *intel_connector = to_intel_connector(connector);
3044
3045         if (!IS_ERR_OR_NULL(intel_connector->edid))
3046                 kfree(intel_connector->edid);
3047
3048         /* Can't call is_edp() since the encoder may have been destroyed
3049          * already. */
3050         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3051                 intel_panel_fini(&intel_connector->panel);
3052
3053         drm_sysfs_connector_remove(connector);
3054         drm_connector_cleanup(connector);
3055         kfree(connector);
3056 }
3057
3058 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3059 {
3060         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3061         struct intel_dp *intel_dp = &intel_dig_port->dp;
3062         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3063
3064         i2c_del_adapter(&intel_dp->adapter);
3065         drm_encoder_cleanup(encoder);
3066         if (is_edp(intel_dp)) {
3067                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3068                 mutex_lock(&dev->mode_config.mutex);
3069                 ironlake_panel_vdd_off_sync(intel_dp);
3070                 mutex_unlock(&dev->mode_config.mutex);
3071         }
3072         kfree(intel_dig_port);
3073 }
3074
3075 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3076         .dpms = intel_connector_dpms,
3077         .detect = intel_dp_detect,
3078         .fill_modes = drm_helper_probe_single_connector_modes,
3079         .set_property = intel_dp_set_property,
3080         .destroy = intel_dp_connector_destroy,
3081 };
3082
3083 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3084         .get_modes = intel_dp_get_modes,
3085         .mode_valid = intel_dp_mode_valid,
3086         .best_encoder = intel_best_encoder,
3087 };
3088
3089 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3090         .destroy = intel_dp_encoder_destroy,
3091 };
3092
3093 static void
3094 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3095 {
3096         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3097
3098         intel_dp_check_link_status(intel_dp);
3099 }
3100
3101 /* Return which DP Port should be selected for Transcoder DP control */
3102 int
3103 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3104 {
3105         struct drm_device *dev = crtc->dev;
3106         struct intel_encoder *intel_encoder;
3107         struct intel_dp *intel_dp;
3108
3109         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3110                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3111
3112                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3113                     intel_encoder->type == INTEL_OUTPUT_EDP)
3114                         return intel_dp->output_reg;
3115         }
3116
3117         return -1;
3118 }
3119
3120 /* check the VBT to see whether the eDP is on DP-D port */
3121 bool intel_dpd_is_edp(struct drm_device *dev)
3122 {
3123         struct drm_i915_private *dev_priv = dev->dev_private;
3124         struct child_device_config *p_child;
3125         int i;
3126
3127         if (!dev_priv->vbt.child_dev_num)
3128                 return false;
3129
3130         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3131                 p_child = dev_priv->vbt.child_dev + i;
3132
3133                 if (p_child->dvo_port == PORT_IDPD &&
3134                     p_child->device_type == DEVICE_TYPE_eDP)
3135                         return true;
3136         }
3137         return false;
3138 }
3139
3140 static void
3141 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3142 {
3143         struct intel_connector *intel_connector = to_intel_connector(connector);
3144
3145         intel_attach_force_audio_property(connector);
3146         intel_attach_broadcast_rgb_property(connector);
3147         intel_dp->color_range_auto = true;
3148
3149         if (is_edp(intel_dp)) {
3150                 drm_mode_create_scaling_mode_property(connector->dev);
3151                 drm_object_attach_property(
3152                         &connector->base,
3153                         connector->dev->mode_config.scaling_mode_property,
3154                         DRM_MODE_SCALE_ASPECT);
3155                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3156         }
3157 }
3158
3159 static void
3160 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3161                                     struct intel_dp *intel_dp,
3162                                     struct edp_power_seq *out)
3163 {
3164         struct drm_i915_private *dev_priv = dev->dev_private;
3165         struct edp_power_seq cur, vbt, spec, final;
3166         u32 pp_on, pp_off, pp_div, pp;
3167         int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3168
3169         if (HAS_PCH_SPLIT(dev)) {
3170                 pp_control_reg = PCH_PP_CONTROL;
3171                 pp_on_reg = PCH_PP_ON_DELAYS;
3172                 pp_off_reg = PCH_PP_OFF_DELAYS;
3173                 pp_div_reg = PCH_PP_DIVISOR;
3174         } else {
3175                 pp_control_reg = PIPEA_PP_CONTROL;
3176                 pp_on_reg = PIPEA_PP_ON_DELAYS;
3177                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3178                 pp_div_reg = PIPEA_PP_DIVISOR;
3179         }
3180
3181         /* Workaround: Need to write PP_CONTROL with the unlock key as
3182          * the very first thing. */
3183         pp = ironlake_get_pp_control(intel_dp);
3184         I915_WRITE(pp_control_reg, pp);
3185
3186         pp_on = I915_READ(pp_on_reg);
3187         pp_off = I915_READ(pp_off_reg);
3188         pp_div = I915_READ(pp_div_reg);
3189
3190         /* Pull timing values out of registers */
3191         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3192                 PANEL_POWER_UP_DELAY_SHIFT;
3193
3194         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3195                 PANEL_LIGHT_ON_DELAY_SHIFT;
3196
3197         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3198                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3199
3200         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3201                 PANEL_POWER_DOWN_DELAY_SHIFT;
3202
3203         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3204                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3205
3206         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3207                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3208
3209         vbt = dev_priv->vbt.edp_pps;
3210
3211         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3212          * our hw here, which are all in 100usec. */
3213         spec.t1_t3 = 210 * 10;
3214         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3215         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3216         spec.t10 = 500 * 10;
3217         /* This one is special and actually in units of 100ms, but zero
3218          * based in the hw (so we need to add 100 ms). But the sw vbt
3219          * table multiplies it with 1000 to make it in units of 100usec,
3220          * too. */
3221         spec.t11_t12 = (510 + 100) * 10;
3222
3223         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3224                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3225
3226         /* Use the max of the register settings and vbt. If both are
3227          * unset, fall back to the spec limits. */
3228 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3229                                        spec.field : \
3230                                        max(cur.field, vbt.field))
3231         assign_final(t1_t3);
3232         assign_final(t8);
3233         assign_final(t9);
3234         assign_final(t10);
3235         assign_final(t11_t12);
3236 #undef assign_final
3237
3238 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3239         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3240         intel_dp->backlight_on_delay = get_delay(t8);
3241         intel_dp->backlight_off_delay = get_delay(t9);
3242         intel_dp->panel_power_down_delay = get_delay(t10);
3243         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3244 #undef get_delay
3245
3246         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3247                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3248                       intel_dp->panel_power_cycle_delay);
3249
3250         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3251                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3252
3253         if (out)
3254                 *out = final;
3255 }
3256
3257 static void
3258 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3259                                               struct intel_dp *intel_dp,
3260                                               struct edp_power_seq *seq)
3261 {
3262         struct drm_i915_private *dev_priv = dev->dev_private;
3263         u32 pp_on, pp_off, pp_div, port_sel = 0;
3264         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3265         int pp_on_reg, pp_off_reg, pp_div_reg;
3266
3267         if (HAS_PCH_SPLIT(dev)) {
3268                 pp_on_reg = PCH_PP_ON_DELAYS;
3269                 pp_off_reg = PCH_PP_OFF_DELAYS;
3270                 pp_div_reg = PCH_PP_DIVISOR;
3271         } else {
3272                 pp_on_reg = PIPEA_PP_ON_DELAYS;
3273                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3274                 pp_div_reg = PIPEA_PP_DIVISOR;
3275         }
3276
3277         /* And finally store the new values in the power sequencer. */
3278         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3279                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3280         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3281                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3282         /* Compute the divisor for the pp clock, simply match the Bspec
3283          * formula. */
3284         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3285         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3286                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3287
3288         /* Haswell doesn't have any port selection bits for the panel
3289          * power sequencer any more. */
3290         if (IS_VALLEYVIEW(dev)) {
3291                 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3292         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3293                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3294                         port_sel = PANEL_POWER_PORT_DP_A;
3295                 else
3296                         port_sel = PANEL_POWER_PORT_DP_D;
3297         }
3298
3299         pp_on |= port_sel;
3300
3301         I915_WRITE(pp_on_reg, pp_on);
3302         I915_WRITE(pp_off_reg, pp_off);
3303         I915_WRITE(pp_div_reg, pp_div);
3304
3305         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3306                       I915_READ(pp_on_reg),
3307                       I915_READ(pp_off_reg),
3308                       I915_READ(pp_div_reg));
3309 }
3310
3311 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3312                                      struct intel_connector *intel_connector)
3313 {
3314         struct drm_connector *connector = &intel_connector->base;
3315         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3316         struct drm_device *dev = intel_dig_port->base.base.dev;
3317         struct drm_i915_private *dev_priv = dev->dev_private;
3318         struct drm_display_mode *fixed_mode = NULL;
3319         struct edp_power_seq power_seq = { 0 };
3320         bool has_dpcd;
3321         struct drm_display_mode *scan;
3322         struct edid *edid;
3323
3324         if (!is_edp(intel_dp))
3325                 return true;
3326
3327         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3328
3329         /* Cache DPCD and EDID for edp. */
3330         ironlake_edp_panel_vdd_on(intel_dp);
3331         has_dpcd = intel_dp_get_dpcd(intel_dp);
3332         ironlake_edp_panel_vdd_off(intel_dp, false);
3333
3334         if (has_dpcd) {
3335                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3336                         dev_priv->no_aux_handshake =
3337                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3338                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3339         } else {
3340                 /* if this fails, presume the device is a ghost */
3341                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3342                 return false;
3343         }
3344
3345         /* We now know it's not a ghost, init power sequence regs. */
3346         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3347                                                       &power_seq);
3348
3349         ironlake_edp_panel_vdd_on(intel_dp);
3350         edid = drm_get_edid(connector, &intel_dp->adapter);
3351         if (edid) {
3352                 if (drm_add_edid_modes(connector, edid)) {
3353                         drm_mode_connector_update_edid_property(connector,
3354                                                                 edid);
3355                         drm_edid_to_eld(connector, edid);
3356                 } else {
3357                         kfree(edid);
3358                         edid = ERR_PTR(-EINVAL);
3359                 }
3360         } else {
3361                 edid = ERR_PTR(-ENOENT);
3362         }
3363         intel_connector->edid = edid;
3364
3365         /* prefer fixed mode from EDID if available */
3366         list_for_each_entry(scan, &connector->probed_modes, head) {
3367                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3368                         fixed_mode = drm_mode_duplicate(dev, scan);
3369                         break;
3370                 }
3371         }
3372
3373         /* fallback to VBT if available for eDP */
3374         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3375                 fixed_mode = drm_mode_duplicate(dev,
3376                                         dev_priv->vbt.lfp_lvds_vbt_mode);
3377                 if (fixed_mode)
3378                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3379         }
3380
3381         ironlake_edp_panel_vdd_off(intel_dp, false);
3382
3383         intel_panel_init(&intel_connector->panel, fixed_mode);
3384         intel_panel_setup_backlight(connector);
3385
3386         return true;
3387 }
3388
3389 bool
3390 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3391                         struct intel_connector *intel_connector)
3392 {
3393         struct drm_connector *connector = &intel_connector->base;
3394         struct intel_dp *intel_dp = &intel_dig_port->dp;
3395         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3396         struct drm_device *dev = intel_encoder->base.dev;
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         enum port port = intel_dig_port->port;
3399         const char *name = NULL;
3400         int type, error;
3401
3402         /* Preserve the current hw state. */
3403         intel_dp->DP = I915_READ(intel_dp->output_reg);
3404         intel_dp->attached_connector = intel_connector;
3405
3406         type = DRM_MODE_CONNECTOR_DisplayPort;
3407         /*
3408          * FIXME : We need to initialize built-in panels before external panels.
3409          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3410          */
3411         switch (port) {
3412         case PORT_A:
3413                 type = DRM_MODE_CONNECTOR_eDP;
3414                 break;
3415         case PORT_C:
3416                 if (IS_VALLEYVIEW(dev))
3417                         type = DRM_MODE_CONNECTOR_eDP;
3418                 break;
3419         case PORT_D:
3420                 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3421                         type = DRM_MODE_CONNECTOR_eDP;
3422                 break;
3423         default:        /* silence GCC warning */
3424                 break;
3425         }
3426
3427         /*
3428          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3429          * for DP the encoder type can be set by the caller to
3430          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3431          */
3432         if (type == DRM_MODE_CONNECTOR_eDP)
3433                 intel_encoder->type = INTEL_OUTPUT_EDP;
3434
3435         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3436                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3437                         port_name(port));
3438
3439         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3440         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3441
3442         connector->interlace_allowed = true;
3443         connector->doublescan_allowed = 0;
3444
3445         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3446                           ironlake_panel_vdd_work);
3447
3448         intel_connector_attach_encoder(intel_connector, intel_encoder);
3449         drm_sysfs_connector_add(connector);
3450
3451         if (HAS_DDI(dev))
3452                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3453         else
3454                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3455
3456         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3457         if (HAS_DDI(dev)) {
3458                 switch (intel_dig_port->port) {
3459                 case PORT_A:
3460                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3461                         break;
3462                 case PORT_B:
3463                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3464                         break;
3465                 case PORT_C:
3466                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3467                         break;
3468                 case PORT_D:
3469                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3470                         break;
3471                 default:
3472                         BUG();
3473                 }
3474         }
3475
3476         /* Set up the DDC bus. */
3477         switch (port) {
3478         case PORT_A:
3479                 intel_encoder->hpd_pin = HPD_PORT_A;
3480                 name = "DPDDC-A";
3481                 break;
3482         case PORT_B:
3483                 intel_encoder->hpd_pin = HPD_PORT_B;
3484                 name = "DPDDC-B";
3485                 break;
3486         case PORT_C:
3487                 intel_encoder->hpd_pin = HPD_PORT_C;
3488                 name = "DPDDC-C";
3489                 break;
3490         case PORT_D:
3491                 intel_encoder->hpd_pin = HPD_PORT_D;
3492                 name = "DPDDC-D";
3493                 break;
3494         default:
3495                 BUG();
3496         }
3497
3498         error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3499         WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3500              error, port_name(port));
3501
3502         intel_dp->psr_setup_done = false;
3503
3504         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3505                 i2c_del_adapter(&intel_dp->adapter);
3506                 if (is_edp(intel_dp)) {
3507                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3508                         mutex_lock(&dev->mode_config.mutex);
3509                         ironlake_panel_vdd_off_sync(intel_dp);
3510                         mutex_unlock(&dev->mode_config.mutex);
3511                 }
3512                 drm_sysfs_connector_remove(connector);
3513                 drm_connector_cleanup(connector);
3514                 return false;
3515         }
3516
3517         intel_dp_add_properties(intel_dp, connector);
3518
3519         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3520          * 0xd.  Failure to do so will result in spurious interrupts being
3521          * generated on the port when a cable is not attached.
3522          */
3523         if (IS_G4X(dev) && !IS_GM45(dev)) {
3524                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3525                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3526         }
3527
3528         return true;
3529 }
3530
3531 void
3532 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3533 {
3534         struct intel_digital_port *intel_dig_port;
3535         struct intel_encoder *intel_encoder;
3536         struct drm_encoder *encoder;
3537         struct intel_connector *intel_connector;
3538
3539         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3540         if (!intel_dig_port)
3541                 return;
3542
3543         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3544         if (!intel_connector) {
3545                 kfree(intel_dig_port);
3546                 return;
3547         }
3548
3549         intel_encoder = &intel_dig_port->base;
3550         encoder = &intel_encoder->base;
3551
3552         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3553                          DRM_MODE_ENCODER_TMDS);
3554
3555         intel_encoder->compute_config = intel_dp_compute_config;
3556         intel_encoder->mode_set = intel_dp_mode_set;
3557         intel_encoder->disable = intel_disable_dp;
3558         intel_encoder->post_disable = intel_post_disable_dp;
3559         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3560         intel_encoder->get_config = intel_dp_get_config;
3561         if (IS_VALLEYVIEW(dev)) {
3562                 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3563                 intel_encoder->pre_enable = vlv_pre_enable_dp;
3564                 intel_encoder->enable = vlv_enable_dp;
3565         } else {
3566                 intel_encoder->pre_enable = intel_pre_enable_dp;
3567                 intel_encoder->enable = intel_enable_dp;
3568         }
3569
3570         intel_dig_port->port = port;
3571         intel_dig_port->dp.output_reg = output_reg;
3572
3573         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3574         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3575         intel_encoder->cloneable = false;
3576         intel_encoder->hot_plug = intel_dp_hot_plug;
3577
3578         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3579                 drm_encoder_cleanup(encoder);
3580                 kfree(intel_dig_port);
3581                 kfree(intel_connector);
3582         }
3583 }