drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int clock;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { 162000,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { 270000,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { 162000,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { 270000,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { 162000,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { 270000,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int default_rates[] = { 162000, 270000, 540000 };
  99
 100 /**
 101  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 102  * @intel_dp: DP struct
 103  *
 104  * If a CPU or PCH DP output is attached to an eDP panel, this function
 105  * will return true, and false otherwise.
 106  */
 107 static bool is_edp(struct intel_dp *intel_dp)
 108 {
 109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 110
 111         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 112 }
 113
 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 115 {
 116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 117
 118         return intel_dig_port->base.base.dev;
 119 }
 120
 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 122 {
 123         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 124 }
 125
 126 static void intel_dp_link_down(struct intel_dp *intel_dp);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 130 static void vlv_steal_power_sequencer(struct drm_device *dev,
 131                                       enum pipe pipe);
 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 133
 134 static int
 135 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 136 {
 137         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 138
 139         switch (max_link_bw) {
 140         case DP_LINK_BW_1_62:
 141         case DP_LINK_BW_2_7:
 142         case DP_LINK_BW_5_4:
 143                 break;
 144         default:
 145                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 146                      max_link_bw);
 147                 max_link_bw = DP_LINK_BW_1_62;
 148                 break;
 149         }
 150         return max_link_bw;
 151 }
 152
 153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 154 {
 155         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 156         u8 source_max, sink_max;
 157
 158         source_max = intel_dig_port->max_lanes;
 159         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 160
 161         return min(source_max, sink_max);
 162 }
 163
 164 /*
 165  * The units on the numbers in the next two are... bizarre.  Examples will
 166  * make it clearer; this one parallels an example in the eDP spec.
 167  *
 168  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 169  *
 170  *     270000 * 1 * 8 / 10 == 216000
 171  *
 172  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 173  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 174  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 175  * 119000.  At 18bpp that's 2142000 kilobits per second.
 176  *
 177  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 178  * get the result in decakilobits instead of kilobits.
 179  */
 180
 181 static int
 182 intel_dp_link_required(int pixel_clock, int bpp)
 183 {
 184         return (pixel_clock * bpp + 9) / 10;
 185 }
 186
 187 static int
 188 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 189 {
 190         return (max_link_clock * max_lanes * 8) / 10;
 191 }
 192
 193 static enum drm_mode_status
 194 intel_dp_mode_valid(struct drm_connector *connector,
 195                     struct drm_display_mode *mode)
 196 {
 197         struct intel_dp *intel_dp = intel_attached_dp(connector);
 198         struct intel_connector *intel_connector = to_intel_connector(connector);
 199         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 200         int target_clock = mode->clock;
 201         int max_rate, mode_rate, max_lanes, max_link_clock;
 202         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 203
 204         if (is_edp(intel_dp) && fixed_mode) {
 205                 if (mode->hdisplay > fixed_mode->hdisplay)
 206                         return MODE_PANEL;
 207
 208                 if (mode->vdisplay > fixed_mode->vdisplay)
 209                         return MODE_PANEL;
 210
 211                 target_clock = fixed_mode->clock;
 212         }
 213
 214         max_link_clock = intel_dp_max_link_rate(intel_dp);
 215         max_lanes = intel_dp_max_lane_count(intel_dp);
 216
 217         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 218         mode_rate = intel_dp_link_required(target_clock, 18);
 219
 220         if (mode_rate > max_rate || target_clock > max_dotclk)
 221                 return MODE_CLOCK_HIGH;
 222
 223         if (mode->clock < 10000)
 224                 return MODE_CLOCK_LOW;
 225
 226         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 227                 return MODE_H_ILLEGAL;
 228
 229         return MODE_OK;
 230 }
 231
 232 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 233 {
 234         int     i;
 235         uint32_t v = 0;
 236
 237         if (src_bytes > 4)
 238                 src_bytes = 4;
 239         for (i = 0; i < src_bytes; i++)
 240                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 241         return v;
 242 }
 243
 244 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 245 {
 246         int i;
 247         if (dst_bytes > 4)
 248                 dst_bytes = 4;
 249         for (i = 0; i < dst_bytes; i++)
 250                 dst[i] = src >> ((3-i) * 8);
 251 }
 252
 253 static void
 254 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 255                                     struct intel_dp *intel_dp);
 256 static void
 257 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 258                                               struct intel_dp *intel_dp);
 259
 260 static void pps_lock(struct intel_dp *intel_dp)
 261 {
 262         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 263         struct intel_encoder *encoder = &intel_dig_port->base;
 264         struct drm_device *dev = encoder->base.dev;
 265         struct drm_i915_private *dev_priv = to_i915(dev);
 266         enum intel_display_power_domain power_domain;
 267
 268         /*
 269          * See vlv_power_sequencer_reset() why we need
 270          * a power domain reference here.
 271          */
 272         power_domain = intel_display_port_aux_power_domain(encoder);
 273         intel_display_power_get(dev_priv, power_domain);
 274
 275         mutex_lock(&dev_priv->pps_mutex);
 276 }
 277
 278 static void pps_unlock(struct intel_dp *intel_dp)
 279 {
 280         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 281         struct intel_encoder *encoder = &intel_dig_port->base;
 282         struct drm_device *dev = encoder->base.dev;
 283         struct drm_i915_private *dev_priv = to_i915(dev);
 284         enum intel_display_power_domain power_domain;
 285
 286         mutex_unlock(&dev_priv->pps_mutex);
 287
 288         power_domain = intel_display_port_aux_power_domain(encoder);
 289         intel_display_power_put(dev_priv, power_domain);
 290 }
 291
 292 static void
 293 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 294 {
 295         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 296         struct drm_device *dev = intel_dig_port->base.base.dev;
 297         struct drm_i915_private *dev_priv = to_i915(dev);
 298         enum pipe pipe = intel_dp->pps_pipe;
 299         bool pll_enabled, release_cl_override = false;
 300         enum dpio_phy phy = DPIO_PHY(pipe);
 301         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 302         uint32_t DP;
 303
 304         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 305                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 306                  pipe_name(pipe), port_name(intel_dig_port->port)))
 307                 return;
 308
 309         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 310                       pipe_name(pipe), port_name(intel_dig_port->port));
 311
 312         /* Preserve the BIOS-computed detected bit. This is
 313          * supposed to be read-only.
 314          */
 315         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 316         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 317         DP |= DP_PORT_WIDTH(1);
 318         DP |= DP_LINK_TRAIN_PAT_1;
 319
 320         if (IS_CHERRYVIEW(dev))
 321                 DP |= DP_PIPE_SELECT_CHV(pipe);
 322         else if (pipe == PIPE_B)
 323                 DP |= DP_PIPEB_SELECT;
 324
 325         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 326
 327         /*
 328          * The DPLL for the pipe must be enabled for this to work.
 329          * So enable temporarily it if it's not already enabled.
 330          */
 331         if (!pll_enabled) {
 332                 release_cl_override = IS_CHERRYVIEW(dev) &&
 333                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 334
 335                 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 336                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 337                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 338                                   pipe_name(pipe));
 339                         return;
 340                 }
 341         }
 342
 343         /*
 344          * Similar magic as in intel_dp_enable_port().
 345          * We _must_ do this port enable + disable trick
 346          * to make this power seqeuencer lock onto the port.
 347          * Otherwise even VDD force bit won't work.
 348          */
 349         I915_WRITE(intel_dp->output_reg, DP);
 350         POSTING_READ(intel_dp->output_reg);
 351
 352         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 353         POSTING_READ(intel_dp->output_reg);
 354
 355         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 356         POSTING_READ(intel_dp->output_reg);
 357
 358         if (!pll_enabled) {
 359                 vlv_force_pll_off(dev, pipe);
 360
 361                 if (release_cl_override)
 362                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 363         }
 364 }
 365
 366 static enum pipe
 367 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 368 {
 369         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 370         struct drm_device *dev = intel_dig_port->base.base.dev;
 371         struct drm_i915_private *dev_priv = to_i915(dev);
 372         struct intel_encoder *encoder;
 373         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 374         enum pipe pipe;
 375
 376         lockdep_assert_held(&dev_priv->pps_mutex);
 377
 378         /* We should never land here with regular DP ports */
 379         WARN_ON(!is_edp(intel_dp));
 380
 381         if (intel_dp->pps_pipe != INVALID_PIPE)
 382                 return intel_dp->pps_pipe;
 383
 384         /*
 385          * We don't have power sequencer currently.
 386          * Pick one that's not used by other ports.
 387          */
 388         for_each_intel_encoder(dev, encoder) {
 389                 struct intel_dp *tmp;
 390
 391                 if (encoder->type != INTEL_OUTPUT_EDP)
 392                         continue;
 393
 394                 tmp = enc_to_intel_dp(&encoder->base);
 395
 396                 if (tmp->pps_pipe != INVALID_PIPE)
 397                         pipes &= ~(1 << tmp->pps_pipe);
 398         }
 399
 400         /*
 401          * Didn't find one. This should not happen since there
 402          * are two power sequencers and up to two eDP ports.
 403          */
 404         if (WARN_ON(pipes == 0))
 405                 pipe = PIPE_A;
 406         else
 407                 pipe = ffs(pipes) - 1;
 408
 409         vlv_steal_power_sequencer(dev, pipe);
 410         intel_dp->pps_pipe = pipe;
 411
 412         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 413                       pipe_name(intel_dp->pps_pipe),
 414                       port_name(intel_dig_port->port));
 415
 416         /* init power sequencer on this pipe and port */
 417         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 418         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 419
 420         /*
 421          * Even vdd force doesn't work until we've made
 422          * the power sequencer lock in on the port.
 423          */
 424         vlv_power_sequencer_kick(intel_dp);
 425
 426         return intel_dp->pps_pipe;
 427 }
 428
 429 static int
 430 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 431 {
 432         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 433         struct drm_device *dev = intel_dig_port->base.base.dev;
 434         struct drm_i915_private *dev_priv = to_i915(dev);
 435
 436         lockdep_assert_held(&dev_priv->pps_mutex);
 437
 438         /* We should never land here with regular DP ports */
 439         WARN_ON(!is_edp(intel_dp));
 440
 441         /*
 442          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 443          * mapping needs to be retrieved from VBT, for now just hard-code to
 444          * use instance #0 always.
 445          */
 446         if (!intel_dp->pps_reset)
 447                 return 0;
 448
 449         intel_dp->pps_reset = false;
 450
 451         /*
 452          * Only the HW needs to be reprogrammed, the SW state is fixed and
 453          * has been setup during connector init.
 454          */
 455         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 456
 457         return 0;
 458 }
 459
 460 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 461                                enum pipe pipe);
 462
 463 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 464                                enum pipe pipe)
 465 {
 466         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 467 }
 468
 469 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 470                                 enum pipe pipe)
 471 {
 472         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 473 }
 474
 475 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 476                          enum pipe pipe)
 477 {
 478         return true;
 479 }
 480
 481 static enum pipe
 482 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 483                      enum port port,
 484                      vlv_pipe_check pipe_check)
 485 {
 486         enum pipe pipe;
 487
 488         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 489                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 490                         PANEL_PORT_SELECT_MASK;
 491
 492                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 493                         continue;
 494
 495                 if (!pipe_check(dev_priv, pipe))
 496                         continue;
 497
 498                 return pipe;
 499         }
 500
 501         return INVALID_PIPE;
 502 }
 503
 504 static void
 505 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 506 {
 507         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 508         struct drm_device *dev = intel_dig_port->base.base.dev;
 509         struct drm_i915_private *dev_priv = to_i915(dev);
 510         enum port port = intel_dig_port->port;
 511
 512         lockdep_assert_held(&dev_priv->pps_mutex);
 513
 514         /* try to find a pipe with this port selected */
 515         /* first pick one where the panel is on */
 516         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 517                                                   vlv_pipe_has_pp_on);
 518         /* didn't find one? pick one where vdd is on */
 519         if (intel_dp->pps_pipe == INVALID_PIPE)
 520                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 521                                                           vlv_pipe_has_vdd_on);
 522         /* didn't find one? pick one with just the correct port */
 523         if (intel_dp->pps_pipe == INVALID_PIPE)
 524                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 525                                                           vlv_pipe_any);
 526
 527         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 528         if (intel_dp->pps_pipe == INVALID_PIPE) {
 529                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 530                               port_name(port));
 531                 return;
 532         }
 533
 534         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 535                       port_name(port), pipe_name(intel_dp->pps_pipe));
 536
 537         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 538         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 539 }
 540
 541 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 542 {
 543         struct drm_device *dev = &dev_priv->drm;
 544         struct intel_encoder *encoder;
 545
 546         if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 547                     !IS_BROXTON(dev)))
 548                 return;
 549
 550         /*
 551          * We can't grab pps_mutex here due to deadlock with power_domain
 552          * mutex when power_domain functions are called while holding pps_mutex.
 553          * That also means that in order to use pps_pipe the code needs to
 554          * hold both a power domain reference and pps_mutex, and the power domain
 555          * reference get/put must be done while _not_ holding pps_mutex.
 556          * pps_{lock,unlock}() do these steps in the correct order, so one
 557          * should use them always.
 558          */
 559
 560         for_each_intel_encoder(dev, encoder) {
 561                 struct intel_dp *intel_dp;
 562
 563                 if (encoder->type != INTEL_OUTPUT_EDP)
 564                         continue;
 565
 566                 intel_dp = enc_to_intel_dp(&encoder->base);
 567                 if (IS_BROXTON(dev))
 568                         intel_dp->pps_reset = true;
 569                 else
 570                         intel_dp->pps_pipe = INVALID_PIPE;
 571         }
 572 }
 573
 574 struct pps_registers {
 575         i915_reg_t pp_ctrl;
 576         i915_reg_t pp_stat;
 577         i915_reg_t pp_on;
 578         i915_reg_t pp_off;
 579         i915_reg_t pp_div;
 580 };
 581
 582 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 583                                     struct intel_dp *intel_dp,
 584                                     struct pps_registers *regs)
 585 {
 586         memset(regs, 0, sizeof(*regs));
 587
 588         if (IS_BROXTON(dev_priv)) {
 589                 int idx = bxt_power_sequencer_idx(intel_dp);
 590
 591                 regs->pp_ctrl = BXT_PP_CONTROL(idx);
 592                 regs->pp_stat = BXT_PP_STATUS(idx);
 593                 regs->pp_on = BXT_PP_ON_DELAYS(idx);
 594                 regs->pp_off = BXT_PP_OFF_DELAYS(idx);
 595         } else if (HAS_PCH_SPLIT(dev_priv)) {
 596                 regs->pp_ctrl = PCH_PP_CONTROL;
 597                 regs->pp_stat = PCH_PP_STATUS;
 598                 regs->pp_on = PCH_PP_ON_DELAYS;
 599                 regs->pp_off = PCH_PP_OFF_DELAYS;
 600                 regs->pp_div = PCH_PP_DIVISOR;
 601         } else {
 602                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 603
 604                 regs->pp_ctrl = VLV_PIPE_PP_CONTROL(pipe);
 605                 regs->pp_stat = VLV_PIPE_PP_STATUS(pipe);
 606                 regs->pp_on = VLV_PIPE_PP_ON_DELAYS(pipe);
 607                 regs->pp_off = VLV_PIPE_PP_OFF_DELAYS(pipe);
 608                 regs->pp_div = VLV_PIPE_PP_DIVISOR(pipe);
 609         }
 610 }
 611
 612 static i915_reg_t
 613 _pp_ctrl_reg(struct intel_dp *intel_dp)
 614 {
 615         struct pps_registers regs;
 616
 617         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 618                                 &regs);
 619
 620         return regs.pp_ctrl;
 621 }
 622
 623 static i915_reg_t
 624 _pp_stat_reg(struct intel_dp *intel_dp)
 625 {
 626         struct pps_registers regs;
 627
 628         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 629                                 &regs);
 630
 631         return regs.pp_stat;
 632 }
 633
 634 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 635    This function only applicable when panel PM state is not to be tracked */
 636 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 637                               void *unused)
 638 {
 639         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 640                                                  edp_notifier);
 641         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 642         struct drm_i915_private *dev_priv = to_i915(dev);
 643
 644         if (!is_edp(intel_dp) || code != SYS_RESTART)
 645                 return 0;
 646
 647         pps_lock(intel_dp);
 648
 649         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 650                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 651                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 652                 u32 pp_div;
 653
 654                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 655                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 656                 pp_div = I915_READ(pp_div_reg);
 657                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 658
 659                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 660                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 661                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 662                 msleep(intel_dp->panel_power_cycle_delay);
 663         }
 664
 665         pps_unlock(intel_dp);
 666
 667         return 0;
 668 }
 669
 670 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 671 {
 672         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 673         struct drm_i915_private *dev_priv = to_i915(dev);
 674
 675         lockdep_assert_held(&dev_priv->pps_mutex);
 676
 677         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 678             intel_dp->pps_pipe == INVALID_PIPE)
 679                 return false;
 680
 681         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 682 }
 683
 684 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 685 {
 686         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 687         struct drm_i915_private *dev_priv = to_i915(dev);
 688
 689         lockdep_assert_held(&dev_priv->pps_mutex);
 690
 691         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 692             intel_dp->pps_pipe == INVALID_PIPE)
 693                 return false;
 694
 695         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 696 }
 697
 698 static void
 699 intel_dp_check_edp(struct intel_dp *intel_dp)
 700 {
 701         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 702         struct drm_i915_private *dev_priv = to_i915(dev);
 703
 704         if (!is_edp(intel_dp))
 705                 return;
 706
 707         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 708                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 709                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 710                               I915_READ(_pp_stat_reg(intel_dp)),
 711                               I915_READ(_pp_ctrl_reg(intel_dp)));
 712         }
 713 }
 714
 715 static uint32_t
 716 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 717 {
 718         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 719         struct drm_device *dev = intel_dig_port->base.base.dev;
 720         struct drm_i915_private *dev_priv = to_i915(dev);
 721         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 722         uint32_t status;
 723         bool done;
 724
 725 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 726         if (has_aux_irq)
 727                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 728                                           msecs_to_jiffies_timeout(10));
 729         else
 730                 done = wait_for(C, 10) == 0;
 731         if (!done)
 732                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 733                           has_aux_irq);
 734 #undef C
 735
 736         return status;
 737 }
 738
 739 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 740 {
 741         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 742         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 743
 744         if (index)
 745                 return 0;
 746
 747         /*
 748          * The clock divider is based off the hrawclk, and would like to run at
 749          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 750          */
 751         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 752 }
 753
 754 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 755 {
 756         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 757         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 758
 759         if (index)
 760                 return 0;
 761
 762         /*
 763          * The clock divider is based off the cdclk or PCH rawclk, and would
 764          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 765          * divide by 2000 and use that
 766          */
 767         if (intel_dig_port->port == PORT_A)
 768                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 769         else
 770                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 771 }
 772
 773 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 774 {
 775         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 776         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 777
 778         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 779                 /* Workaround for non-ULT HSW */
 780                 switch (index) {
 781                 case 0: return 63;
 782                 case 1: return 72;
 783                 default: return 0;
 784                 }
 785         }
 786
 787         return ilk_get_aux_clock_divider(intel_dp, index);
 788 }
 789
 790 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 791 {
 792         /*
 793          * SKL doesn't need us to program the AUX clock divider (Hardware will
 794          * derive the clock from CDCLK automatically). We still implement the
 795          * get_aux_clock_divider vfunc to plug-in into the existing code.
 796          */
 797         return index ? 0 : 1;
 798 }
 799
 800 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 801                                      bool has_aux_irq,
 802                                      int send_bytes,
 803                                      uint32_t aux_clock_divider)
 804 {
 805         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 806         struct drm_device *dev = intel_dig_port->base.base.dev;
 807         uint32_t precharge, timeout;
 808
 809         if (IS_GEN6(dev))
 810                 precharge = 3;
 811         else
 812                 precharge = 5;
 813
 814         if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
 815                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 816         else
 817                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 818
 819         return DP_AUX_CH_CTL_SEND_BUSY |
 820                DP_AUX_CH_CTL_DONE |
 821                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 822                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 823                timeout |
 824                DP_AUX_CH_CTL_RECEIVE_ERROR |
 825                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 826                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 827                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 828 }
 829
 830 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 831                                       bool has_aux_irq,
 832                                       int send_bytes,
 833                                       uint32_t unused)
 834 {
 835         return DP_AUX_CH_CTL_SEND_BUSY |
 836                DP_AUX_CH_CTL_DONE |
 837                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 838                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 839                DP_AUX_CH_CTL_TIME_OUT_1600us |
 840                DP_AUX_CH_CTL_RECEIVE_ERROR |
 841                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 842                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
 843                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 844 }
 845
 846 static int
 847 intel_dp_aux_ch(struct intel_dp *intel_dp,
 848                 const uint8_t *send, int send_bytes,
 849                 uint8_t *recv, int recv_size)
 850 {
 851         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 852         struct drm_device *dev = intel_dig_port->base.base.dev;
 853         struct drm_i915_private *dev_priv = to_i915(dev);
 854         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 855         uint32_t aux_clock_divider;
 856         int i, ret, recv_bytes;
 857         uint32_t status;
 858         int try, clock = 0;
 859         bool has_aux_irq = HAS_AUX_IRQ(dev);
 860         bool vdd;
 861
 862         pps_lock(intel_dp);
 863
 864         /*
 865          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 866          * In such cases we want to leave VDD enabled and it's up to upper layers
 867          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 868          * ourselves.
 869          */
 870         vdd = edp_panel_vdd_on(intel_dp);
 871
 872         /* dp aux is extremely sensitive to irq latency, hence request the
 873          * lowest possible wakeup latency and so prevent the cpu from going into
 874          * deep sleep states.
 875          */
 876         pm_qos_update_request(&dev_priv->pm_qos, 0);
 877
 878         intel_dp_check_edp(intel_dp);
 879
 880         /* Try to wait for any previous AUX channel activity */
 881         for (try = 0; try < 3; try++) {
 882                 status = I915_READ_NOTRACE(ch_ctl);
 883                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 884                         break;
 885                 msleep(1);
 886         }
 887
 888         if (try == 3) {
 889                 static u32 last_status = -1;
 890                 const u32 status = I915_READ(ch_ctl);
 891
 892                 if (status != last_status) {
 893                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
 894                              status);
 895                         last_status = status;
 896                 }
 897
 898                 ret = -EBUSY;
 899                 goto out;
 900         }
 901
 902         /* Only 5 data registers! */
 903         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 904                 ret = -E2BIG;
 905                 goto out;
 906         }
 907
 908         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 909                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 910                                                           has_aux_irq,
 911                                                           send_bytes,
 912                                                           aux_clock_divider);
 913
 914                 /* Must try at least 3 times according to DP spec */
 915                 for (try = 0; try < 5; try++) {
 916                         /* Load the send data into the aux channel data registers */
 917                         for (i = 0; i < send_bytes; i += 4)
 918                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
 919                                            intel_dp_pack_aux(send + i,
 920                                                              send_bytes - i));
 921
 922                         /* Send the command and wait for it to complete */
 923                         I915_WRITE(ch_ctl, send_ctl);
 924
 925                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 926
 927                         /* Clear done status and any errors */
 928                         I915_WRITE(ch_ctl,
 929                                    status |
 930                                    DP_AUX_CH_CTL_DONE |
 931                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 932                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 933
 934                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 935                                 continue;
 936
 937                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 938                          *   400us delay required for errors and timeouts
 939                          *   Timeout errors from the HW already meet this
 940                          *   requirement so skip to next iteration
 941                          */
 942                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 943                                 usleep_range(400, 500);
 944                                 continue;
 945                         }
 946                         if (status & DP_AUX_CH_CTL_DONE)
 947                                 goto done;
 948                 }
 949         }
 950
 951         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 952                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 953                 ret = -EBUSY;
 954                 goto out;
 955         }
 956
 957 done:
 958         /* Check for timeout or receive error.
 959          * Timeouts occur when the sink is not connected
 960          */
 961         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 962                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 963                 ret = -EIO;
 964                 goto out;
 965         }
 966
 967         /* Timeouts occur when the device isn't connected, so they're
 968          * "normal" -- don't fill the kernel log with these */
 969         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 970                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 971                 ret = -ETIMEDOUT;
 972                 goto out;
 973         }
 974
 975         /* Unload any bytes sent back from the other side */
 976         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 977                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 978
 979         /*
 980          * By BSpec: "Message sizes of 0 or >20 are not allowed."
 981          * We have no idea of what happened so we return -EBUSY so
 982          * drm layer takes care for the necessary retries.
 983          */
 984         if (recv_bytes == 0 || recv_bytes > 20) {
 985                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
 986                               recv_bytes);
 987                 /*
 988                  * FIXME: This patch was created on top of a series that
 989                  * organize the retries at drm level. There EBUSY should
 990                  * also take care for 1ms wait before retrying.
 991                  * That aux retries re-org is still needed and after that is
 992                  * merged we remove this sleep from here.
 993                  */
 994                 usleep_range(1000, 1500);
 995                 ret = -EBUSY;
 996                 goto out;
 997         }
 998
 999         if (recv_bytes > recv_size)
1000                 recv_bytes = recv_size;
1001
1002         for (i = 0; i < recv_bytes; i += 4)
1003                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1004                                     recv + i, recv_bytes - i);
1005
1006         ret = recv_bytes;
1007 out:
1008         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1009
1010         if (vdd)
1011                 edp_panel_vdd_off(intel_dp, false);
1012
1013         pps_unlock(intel_dp);
1014
1015         return ret;
1016 }
1017
1018 #define BARE_ADDRESS_SIZE       3
1019 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1020 static ssize_t
1021 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1022 {
1023         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1024         uint8_t txbuf[20], rxbuf[20];
1025         size_t txsize, rxsize;
1026         int ret;
1027
1028         txbuf[0] = (msg->request << 4) |
1029                 ((msg->address >> 16) & 0xf);
1030         txbuf[1] = (msg->address >> 8) & 0xff;
1031         txbuf[2] = msg->address & 0xff;
1032         txbuf[3] = msg->size - 1;
1033
1034         switch (msg->request & ~DP_AUX_I2C_MOT) {
1035         case DP_AUX_NATIVE_WRITE:
1036         case DP_AUX_I2C_WRITE:
1037         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1038                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1039                 rxsize = 2; /* 0 or 1 data bytes */
1040
1041                 if (WARN_ON(txsize > 20))
1042                         return -E2BIG;
1043
1044                 if (msg->buffer)
1045                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1046                 else
1047                         WARN_ON(msg->size);
1048
1049                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1050                 if (ret > 0) {
1051                         msg->reply = rxbuf[0] >> 4;
1052
1053                         if (ret > 1) {
1054                                 /* Number of bytes written in a short write. */
1055                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1056                         } else {
1057                                 /* Return payload size. */
1058                                 ret = msg->size;
1059                         }
1060                 }
1061                 break;
1062
1063         case DP_AUX_NATIVE_READ:
1064         case DP_AUX_I2C_READ:
1065                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1066                 rxsize = msg->size + 1;
1067
1068                 if (WARN_ON(rxsize > 20))
1069                         return -E2BIG;
1070
1071                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1072                 if (ret > 0) {
1073                         msg->reply = rxbuf[0] >> 4;
1074                         /*
1075                          * Assume happy day, and copy the data. The caller is
1076                          * expected to check msg->reply before touching it.
1077                          *
1078                          * Return payload size.
1079                          */
1080                         ret--;
1081                         memcpy(msg->buffer, rxbuf + 1, ret);
1082                 }
1083                 break;
1084
1085         default:
1086                 ret = -EINVAL;
1087                 break;
1088         }
1089
1090         return ret;
1091 }
1092
1093 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1094                                        enum port port)
1095 {
1096         switch (port) {
1097         case PORT_B:
1098         case PORT_C:
1099         case PORT_D:
1100                 return DP_AUX_CH_CTL(port);
1101         default:
1102                 MISSING_CASE(port);
1103                 return DP_AUX_CH_CTL(PORT_B);
1104         }
1105 }
1106
1107 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1108                                         enum port port, int index)
1109 {
1110         switch (port) {
1111         case PORT_B:
1112         case PORT_C:
1113         case PORT_D:
1114                 return DP_AUX_CH_DATA(port, index);
1115         default:
1116                 MISSING_CASE(port);
1117                 return DP_AUX_CH_DATA(PORT_B, index);
1118         }
1119 }
1120
1121 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1122                                        enum port port)
1123 {
1124         switch (port) {
1125         case PORT_A:
1126                 return DP_AUX_CH_CTL(port);
1127         case PORT_B:
1128         case PORT_C:
1129         case PORT_D:
1130                 return PCH_DP_AUX_CH_CTL(port);
1131         default:
1132                 MISSING_CASE(port);
1133                 return DP_AUX_CH_CTL(PORT_A);
1134         }
1135 }
1136
1137 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1138                                         enum port port, int index)
1139 {
1140         switch (port) {
1141         case PORT_A:
1142                 return DP_AUX_CH_DATA(port, index);
1143         case PORT_B:
1144         case PORT_C:
1145         case PORT_D:
1146                 return PCH_DP_AUX_CH_DATA(port, index);
1147         default:
1148                 MISSING_CASE(port);
1149                 return DP_AUX_CH_DATA(PORT_A, index);
1150         }
1151 }
1152
1153 /*
1154  * On SKL we don't have Aux for port E so we rely
1155  * on VBT to set a proper alternate aux channel.
1156  */
1157 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1158 {
1159         const struct ddi_vbt_port_info *info =
1160                 &dev_priv->vbt.ddi_port_info[PORT_E];
1161
1162         switch (info->alternate_aux_channel) {
1163         case DP_AUX_A:
1164                 return PORT_A;
1165         case DP_AUX_B:
1166                 return PORT_B;
1167         case DP_AUX_C:
1168                 return PORT_C;
1169         case DP_AUX_D:
1170                 return PORT_D;
1171         default:
1172                 MISSING_CASE(info->alternate_aux_channel);
1173                 return PORT_A;
1174         }
1175 }
1176
1177 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1178                                        enum port port)
1179 {
1180         if (port == PORT_E)
1181                 port = skl_porte_aux_port(dev_priv);
1182
1183         switch (port) {
1184         case PORT_A:
1185         case PORT_B:
1186         case PORT_C:
1187         case PORT_D:
1188                 return DP_AUX_CH_CTL(port);
1189         default:
1190                 MISSING_CASE(port);
1191                 return DP_AUX_CH_CTL(PORT_A);
1192         }
1193 }
1194
1195 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1196                                         enum port port, int index)
1197 {
1198         if (port == PORT_E)
1199                 port = skl_porte_aux_port(dev_priv);
1200
1201         switch (port) {
1202         case PORT_A:
1203         case PORT_B:
1204         case PORT_C:
1205         case PORT_D:
1206                 return DP_AUX_CH_DATA(port, index);
1207         default:
1208                 MISSING_CASE(port);
1209                 return DP_AUX_CH_DATA(PORT_A, index);
1210         }
1211 }
1212
1213 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1214                                          enum port port)
1215 {
1216         if (INTEL_INFO(dev_priv)->gen >= 9)
1217                 return skl_aux_ctl_reg(dev_priv, port);
1218         else if (HAS_PCH_SPLIT(dev_priv))
1219                 return ilk_aux_ctl_reg(dev_priv, port);
1220         else
1221                 return g4x_aux_ctl_reg(dev_priv, port);
1222 }
1223
1224 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1225                                           enum port port, int index)
1226 {
1227         if (INTEL_INFO(dev_priv)->gen >= 9)
1228                 return skl_aux_data_reg(dev_priv, port, index);
1229         else if (HAS_PCH_SPLIT(dev_priv))
1230                 return ilk_aux_data_reg(dev_priv, port, index);
1231         else
1232                 return g4x_aux_data_reg(dev_priv, port, index);
1233 }
1234
1235 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1236 {
1237         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1238         enum port port = dp_to_dig_port(intel_dp)->port;
1239         int i;
1240
1241         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1242         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1243                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1244 }
1245
1246 static void
1247 intel_dp_aux_fini(struct intel_dp *intel_dp)
1248 {
1249         kfree(intel_dp->aux.name);
1250 }
1251
1252 static void
1253 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1254 {
1255         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1256         enum port port = intel_dig_port->port;
1257
1258         intel_aux_reg_init(intel_dp);
1259         drm_dp_aux_init(&intel_dp->aux);
1260
1261         /* Failure to allocate our preferred name is not critical */
1262         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1263         intel_dp->aux.transfer = intel_dp_aux_transfer;
1264 }
1265
1266 static int
1267 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1268 {
1269         if (intel_dp->num_sink_rates) {
1270                 *sink_rates = intel_dp->sink_rates;
1271                 return intel_dp->num_sink_rates;
1272         }
1273
1274         *sink_rates = default_rates;
1275
1276         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1277 }
1278
1279 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1280 {
1281         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1282         struct drm_device *dev = dig_port->base.base.dev;
1283
1284         /* WaDisableHBR2:skl */
1285         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1286                 return false;
1287
1288         if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1289             (INTEL_INFO(dev)->gen >= 9))
1290                 return true;
1291         else
1292                 return false;
1293 }
1294
1295 static int
1296 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1297 {
1298         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1299         struct drm_device *dev = dig_port->base.base.dev;
1300         int size;
1301
1302         if (IS_BROXTON(dev)) {
1303                 *source_rates = bxt_rates;
1304                 size = ARRAY_SIZE(bxt_rates);
1305         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1306                 *source_rates = skl_rates;
1307                 size = ARRAY_SIZE(skl_rates);
1308         } else {
1309                 *source_rates = default_rates;
1310                 size = ARRAY_SIZE(default_rates);
1311         }
1312
1313         /* This depends on the fact that 5.4 is last value in the array */
1314         if (!intel_dp_source_supports_hbr2(intel_dp))
1315                 size--;
1316
1317         return size;
1318 }
1319
1320 static void
1321 intel_dp_set_clock(struct intel_encoder *encoder,
1322                    struct intel_crtc_state *pipe_config)
1323 {
1324         struct drm_device *dev = encoder->base.dev;
1325         const struct dp_link_dpll *divisor = NULL;
1326         int i, count = 0;
1327
1328         if (IS_G4X(dev)) {
1329                 divisor = gen4_dpll;
1330                 count = ARRAY_SIZE(gen4_dpll);
1331         } else if (HAS_PCH_SPLIT(dev)) {
1332                 divisor = pch_dpll;
1333                 count = ARRAY_SIZE(pch_dpll);
1334         } else if (IS_CHERRYVIEW(dev)) {
1335                 divisor = chv_dpll;
1336                 count = ARRAY_SIZE(chv_dpll);
1337         } else if (IS_VALLEYVIEW(dev)) {
1338                 divisor = vlv_dpll;
1339                 count = ARRAY_SIZE(vlv_dpll);
1340         }
1341
1342         if (divisor && count) {
1343                 for (i = 0; i < count; i++) {
1344                         if (pipe_config->port_clock == divisor[i].clock) {
1345                                 pipe_config->dpll = divisor[i].dpll;
1346                                 pipe_config->clock_set = true;
1347                                 break;
1348                         }
1349                 }
1350         }
1351 }
1352
1353 static int intersect_rates(const int *source_rates, int source_len,
1354                            const int *sink_rates, int sink_len,
1355                            int *common_rates)
1356 {
1357         int i = 0, j = 0, k = 0;
1358
1359         while (i < source_len && j < sink_len) {
1360                 if (source_rates[i] == sink_rates[j]) {
1361                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1362                                 return k;
1363                         common_rates[k] = source_rates[i];
1364                         ++k;
1365                         ++i;
1366                         ++j;
1367                 } else if (source_rates[i] < sink_rates[j]) {
1368                         ++i;
1369                 } else {
1370                         ++j;
1371                 }
1372         }
1373         return k;
1374 }
1375
1376 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1377                                  int *common_rates)
1378 {
1379         const int *source_rates, *sink_rates;
1380         int source_len, sink_len;
1381
1382         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1383         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1384
1385         return intersect_rates(source_rates, source_len,
1386                                sink_rates, sink_len,
1387                                common_rates);
1388 }
1389
1390 static void snprintf_int_array(char *str, size_t len,
1391                                const int *array, int nelem)
1392 {
1393         int i;
1394
1395         str[0] = '\0';
1396
1397         for (i = 0; i < nelem; i++) {
1398                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1399                 if (r >= len)
1400                         return;
1401                 str += r;
1402                 len -= r;
1403         }
1404 }
1405
1406 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1407 {
1408         const int *source_rates, *sink_rates;
1409         int source_len, sink_len, common_len;
1410         int common_rates[DP_MAX_SUPPORTED_RATES];
1411         char str[128]; /* FIXME: too big for stack? */
1412
1413         if ((drm_debug & DRM_UT_KMS) == 0)
1414                 return;
1415
1416         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1417         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1418         DRM_DEBUG_KMS("source rates: %s\n", str);
1419
1420         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1421         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1422         DRM_DEBUG_KMS("sink rates: %s\n", str);
1423
1424         common_len = intel_dp_common_rates(intel_dp, common_rates);
1425         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1426         DRM_DEBUG_KMS("common rates: %s\n", str);
1427 }
1428
1429 static int rate_to_index(int find, const int *rates)
1430 {
1431         int i = 0;
1432
1433         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1434                 if (find == rates[i])
1435                         break;
1436
1437         return i;
1438 }
1439
1440 int
1441 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1442 {
1443         int rates[DP_MAX_SUPPORTED_RATES] = {};
1444         int len;
1445
1446         len = intel_dp_common_rates(intel_dp, rates);
1447         if (WARN_ON(len <= 0))
1448                 return 162000;
1449
1450         return rates[rate_to_index(0, rates) - 1];
1451 }
1452
1453 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1454 {
1455         return rate_to_index(rate, intel_dp->sink_rates);
1456 }
1457
1458 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1459                            uint8_t *link_bw, uint8_t *rate_select)
1460 {
1461         if (intel_dp->num_sink_rates) {
1462                 *link_bw = 0;
1463                 *rate_select =
1464                         intel_dp_rate_select(intel_dp, port_clock);
1465         } else {
1466                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1467                 *rate_select = 0;
1468         }
1469 }
1470
1471 bool
1472 intel_dp_compute_config(struct intel_encoder *encoder,
1473                         struct intel_crtc_state *pipe_config)
1474 {
1475         struct drm_device *dev = encoder->base.dev;
1476         struct drm_i915_private *dev_priv = to_i915(dev);
1477         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1478         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1479         enum port port = dp_to_dig_port(intel_dp)->port;
1480         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1481         struct intel_connector *intel_connector = intel_dp->attached_connector;
1482         int lane_count, clock;
1483         int min_lane_count = 1;
1484         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1485         /* Conveniently, the link BW constants become indices with a shift...*/
1486         int min_clock = 0;
1487         int max_clock;
1488         int bpp, mode_rate;
1489         int link_avail, link_clock;
1490         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1491         int common_len;
1492         uint8_t link_bw, rate_select;
1493
1494         common_len = intel_dp_common_rates(intel_dp, common_rates);
1495
1496         /* No common link rates between source and sink */
1497         WARN_ON(common_len <= 0);
1498
1499         max_clock = common_len - 1;
1500
1501         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1502                 pipe_config->has_pch_encoder = true;
1503
1504         pipe_config->has_dp_encoder = true;
1505         pipe_config->has_drrs = false;
1506         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1507
1508         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1509                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1510                                        adjusted_mode);
1511
1512                 if (INTEL_INFO(dev)->gen >= 9) {
1513                         int ret;
1514                         ret = skl_update_scaler_crtc(pipe_config);
1515                         if (ret)
1516                                 return ret;
1517                 }
1518
1519                 if (HAS_GMCH_DISPLAY(dev))
1520                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1521                                                  intel_connector->panel.fitting_mode);
1522                 else
1523                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1524                                                 intel_connector->panel.fitting_mode);
1525         }
1526
1527         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1528                 return false;
1529
1530         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1531                       "max bw %d pixel clock %iKHz\n",
1532                       max_lane_count, common_rates[max_clock],
1533                       adjusted_mode->crtc_clock);
1534
1535         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1536          * bpc in between. */
1537         bpp = pipe_config->pipe_bpp;
1538         if (is_edp(intel_dp)) {
1539
1540                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1541                 if (intel_connector->base.display_info.bpc == 0 &&
1542                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1543                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1544                                       dev_priv->vbt.edp.bpp);
1545                         bpp = dev_priv->vbt.edp.bpp;
1546                 }
1547
1548                 /*
1549                  * Use the maximum clock and number of lanes the eDP panel
1550                  * advertizes being capable of. The panels are generally
1551                  * designed to support only a single clock and lane
1552                  * configuration, and typically these values correspond to the
1553                  * native resolution of the panel.
1554                  */
1555                 min_lane_count = max_lane_count;
1556                 min_clock = max_clock;
1557         }
1558
1559         for (; bpp >= 6*3; bpp -= 2*3) {
1560                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1561                                                    bpp);
1562
1563                 for (clock = min_clock; clock <= max_clock; clock++) {
1564                         for (lane_count = min_lane_count;
1565                                 lane_count <= max_lane_count;
1566                                 lane_count <<= 1) {
1567
1568                                 link_clock = common_rates[clock];
1569                                 link_avail = intel_dp_max_data_rate(link_clock,
1570                                                                     lane_count);
1571
1572                                 if (mode_rate <= link_avail) {
1573                                         goto found;
1574                                 }
1575                         }
1576                 }
1577         }
1578
1579         return false;
1580
1581 found:
1582         if (intel_dp->color_range_auto) {
1583                 /*
1584                  * See:
1585                  * CEA-861-E - 5.1 Default Encoding Parameters
1586                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1587                  */
1588                 pipe_config->limited_color_range =
1589                         bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1590         } else {
1591                 pipe_config->limited_color_range =
1592                         intel_dp->limited_color_range;
1593         }
1594
1595         pipe_config->lane_count = lane_count;
1596
1597         pipe_config->pipe_bpp = bpp;
1598         pipe_config->port_clock = common_rates[clock];
1599
1600         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1601                               &link_bw, &rate_select);
1602
1603         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1604                       link_bw, rate_select, pipe_config->lane_count,
1605                       pipe_config->port_clock, bpp);
1606         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1607                       mode_rate, link_avail);
1608
1609         intel_link_compute_m_n(bpp, lane_count,
1610                                adjusted_mode->crtc_clock,
1611                                pipe_config->port_clock,
1612                                &pipe_config->dp_m_n);
1613
1614         if (intel_connector->panel.downclock_mode != NULL &&
1615                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1616                         pipe_config->has_drrs = true;
1617                         intel_link_compute_m_n(bpp, lane_count,
1618                                 intel_connector->panel.downclock_mode->clock,
1619                                 pipe_config->port_clock,
1620                                 &pipe_config->dp_m2_n2);
1621         }
1622
1623         /*
1624          * DPLL0 VCO may need to be adjusted to get the correct
1625          * clock for eDP. This will affect cdclk as well.
1626          */
1627         if (is_edp(intel_dp) &&
1628             (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1629                 int vco;
1630
1631                 switch (pipe_config->port_clock / 2) {
1632                 case 108000:
1633                 case 216000:
1634                         vco = 8640000;
1635                         break;
1636                 default:
1637                         vco = 8100000;
1638                         break;
1639                 }
1640
1641                 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1642         }
1643
1644         if (!HAS_DDI(dev))
1645                 intel_dp_set_clock(encoder, pipe_config);
1646
1647         return true;
1648 }
1649
1650 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1651                               const struct intel_crtc_state *pipe_config)
1652 {
1653         intel_dp->link_rate = pipe_config->port_clock;
1654         intel_dp->lane_count = pipe_config->lane_count;
1655 }
1656
1657 static void intel_dp_prepare(struct intel_encoder *encoder)
1658 {
1659         struct drm_device *dev = encoder->base.dev;
1660         struct drm_i915_private *dev_priv = to_i915(dev);
1661         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1662         enum port port = dp_to_dig_port(intel_dp)->port;
1663         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1664         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1665
1666         intel_dp_set_link_params(intel_dp, crtc->config);
1667
1668         /*
1669          * There are four kinds of DP registers:
1670          *
1671          *      IBX PCH
1672          *      SNB CPU
1673          *      IVB CPU
1674          *      CPT PCH
1675          *
1676          * IBX PCH and CPU are the same for almost everything,
1677          * except that the CPU DP PLL is configured in this
1678          * register
1679          *
1680          * CPT PCH is quite different, having many bits moved
1681          * to the TRANS_DP_CTL register instead. That
1682          * configuration happens (oddly) in ironlake_pch_enable
1683          */
1684
1685         /* Preserve the BIOS-computed detected bit. This is
1686          * supposed to be read-only.
1687          */
1688         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1689
1690         /* Handle DP bits in common between all three register formats */
1691         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1692         intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1693
1694         /* Split out the IBX/CPU vs CPT settings */
1695
1696         if (IS_GEN7(dev) && port == PORT_A) {
1697                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1698                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1699                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1700                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1701                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1702
1703                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1704                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1705
1706                 intel_dp->DP |= crtc->pipe << 29;
1707         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1708                 u32 trans_dp;
1709
1710                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1711
1712                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1713                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1714                         trans_dp |= TRANS_DP_ENH_FRAMING;
1715                 else
1716                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1717                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1718         } else {
1719                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1720                     !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
1721                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1722
1723                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1724                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1725                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1726                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1727                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1728
1729                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1730                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1731
1732                 if (IS_CHERRYVIEW(dev))
1733                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1734                 else if (crtc->pipe == PIPE_B)
1735                         intel_dp->DP |= DP_PIPEB_SELECT;
1736         }
1737 }
1738
1739 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1740 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1741
1742 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1743 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1744
1745 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1746 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1747
1748 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1749                                    struct intel_dp *intel_dp);
1750
1751 static void wait_panel_status(struct intel_dp *intel_dp,
1752                                        u32 mask,
1753                                        u32 value)
1754 {
1755         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1756         struct drm_i915_private *dev_priv = to_i915(dev);
1757         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1758
1759         lockdep_assert_held(&dev_priv->pps_mutex);
1760
1761         intel_pps_verify_state(dev_priv, intel_dp);
1762
1763         pp_stat_reg = _pp_stat_reg(intel_dp);
1764         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1765
1766         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1767                         mask, value,
1768                         I915_READ(pp_stat_reg),
1769                         I915_READ(pp_ctrl_reg));
1770
1771         if (intel_wait_for_register(dev_priv,
1772                                     pp_stat_reg, mask, value,
1773                                     5000))
1774                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1775                                 I915_READ(pp_stat_reg),
1776                                 I915_READ(pp_ctrl_reg));
1777
1778         DRM_DEBUG_KMS("Wait complete\n");
1779 }
1780
1781 static void wait_panel_on(struct intel_dp *intel_dp)
1782 {
1783         DRM_DEBUG_KMS("Wait for panel power on\n");
1784         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1785 }
1786
1787 static void wait_panel_off(struct intel_dp *intel_dp)
1788 {
1789         DRM_DEBUG_KMS("Wait for panel power off time\n");
1790         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1791 }
1792
1793 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1794 {
1795         ktime_t panel_power_on_time;
1796         s64 panel_power_off_duration;
1797
1798         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1799
1800         /* take the difference of currrent time and panel power off time
1801          * and then make panel wait for t11_t12 if needed. */
1802         panel_power_on_time = ktime_get_boottime();
1803         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1804
1805         /* When we disable the VDD override bit last we have to do the manual
1806          * wait. */
1807         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1808                 wait_remaining_ms_from_jiffies(jiffies,
1809                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1810
1811         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1812 }
1813
1814 static void wait_backlight_on(struct intel_dp *intel_dp)
1815 {
1816         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1817                                        intel_dp->backlight_on_delay);
1818 }
1819
1820 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1821 {
1822         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1823                                        intel_dp->backlight_off_delay);
1824 }
1825
1826 /* Read the current pp_control value, unlocking the register if it
1827  * is locked
1828  */
1829
1830 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1831 {
1832         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1833         struct drm_i915_private *dev_priv = to_i915(dev);
1834         u32 control;
1835
1836         lockdep_assert_held(&dev_priv->pps_mutex);
1837
1838         control = I915_READ(_pp_ctrl_reg(intel_dp));
1839         if (!IS_BROXTON(dev)) {
1840                 control &= ~PANEL_UNLOCK_MASK;
1841                 control |= PANEL_UNLOCK_REGS;
1842         }
1843         return control;
1844 }
1845
1846 /*
1847  * Must be paired with edp_panel_vdd_off().
1848  * Must hold pps_mutex around the whole on/off sequence.
1849  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1850  */
1851 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1852 {
1853         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1854         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1855         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1856         struct drm_i915_private *dev_priv = to_i915(dev);
1857         enum intel_display_power_domain power_domain;
1858         u32 pp;
1859         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1860         bool need_to_disable = !intel_dp->want_panel_vdd;
1861
1862         lockdep_assert_held(&dev_priv->pps_mutex);
1863
1864         if (!is_edp(intel_dp))
1865                 return false;
1866
1867         cancel_delayed_work(&intel_dp->panel_vdd_work);
1868         intel_dp->want_panel_vdd = true;
1869
1870         if (edp_have_panel_vdd(intel_dp))
1871                 return need_to_disable;
1872
1873         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1874         intel_display_power_get(dev_priv, power_domain);
1875
1876         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1877                       port_name(intel_dig_port->port));
1878
1879         if (!edp_have_panel_power(intel_dp))
1880                 wait_panel_power_cycle(intel_dp);
1881
1882         pp = ironlake_get_pp_control(intel_dp);
1883         pp |= EDP_FORCE_VDD;
1884
1885         pp_stat_reg = _pp_stat_reg(intel_dp);
1886         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1887
1888         I915_WRITE(pp_ctrl_reg, pp);
1889         POSTING_READ(pp_ctrl_reg);
1890         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1891                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1892         /*
1893          * If the panel wasn't on, delay before accessing aux channel
1894          */
1895         if (!edp_have_panel_power(intel_dp)) {
1896                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1897                               port_name(intel_dig_port->port));
1898                 msleep(intel_dp->panel_power_up_delay);
1899         }
1900
1901         return need_to_disable;
1902 }
1903
1904 /*
1905  * Must be paired with intel_edp_panel_vdd_off() or
1906  * intel_edp_panel_off().
1907  * Nested calls to these functions are not allowed since
1908  * we drop the lock. Caller must use some higher level
1909  * locking to prevent nested calls from other threads.
1910  */
1911 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1912 {
1913         bool vdd;
1914
1915         if (!is_edp(intel_dp))
1916                 return;
1917
1918         pps_lock(intel_dp);
1919         vdd = edp_panel_vdd_on(intel_dp);
1920         pps_unlock(intel_dp);
1921
1922         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1923              port_name(dp_to_dig_port(intel_dp)->port));
1924 }
1925
1926 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1927 {
1928         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1929         struct drm_i915_private *dev_priv = to_i915(dev);
1930         struct intel_digital_port *intel_dig_port =
1931                 dp_to_dig_port(intel_dp);
1932         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1933         enum intel_display_power_domain power_domain;
1934         u32 pp;
1935         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1936
1937         lockdep_assert_held(&dev_priv->pps_mutex);
1938
1939         WARN_ON(intel_dp->want_panel_vdd);
1940
1941         if (!edp_have_panel_vdd(intel_dp))
1942                 return;
1943
1944         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1945                       port_name(intel_dig_port->port));
1946
1947         pp = ironlake_get_pp_control(intel_dp);
1948         pp &= ~EDP_FORCE_VDD;
1949
1950         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1951         pp_stat_reg = _pp_stat_reg(intel_dp);
1952
1953         I915_WRITE(pp_ctrl_reg, pp);
1954         POSTING_READ(pp_ctrl_reg);
1955
1956         /* Make sure sequencer is idle before allowing subsequent activity */
1957         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1958         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1959
1960         if ((pp & POWER_TARGET_ON) == 0)
1961                 intel_dp->panel_power_off_time = ktime_get_boottime();
1962
1963         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1964         intel_display_power_put(dev_priv, power_domain);
1965 }
1966
1967 static void edp_panel_vdd_work(struct work_struct *__work)
1968 {
1969         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1970                                                  struct intel_dp, panel_vdd_work);
1971
1972         pps_lock(intel_dp);
1973         if (!intel_dp->want_panel_vdd)
1974                 edp_panel_vdd_off_sync(intel_dp);
1975         pps_unlock(intel_dp);
1976 }
1977
1978 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1979 {
1980         unsigned long delay;
1981
1982         /*
1983          * Queue the timer to fire a long time from now (relative to the power
1984          * down delay) to keep the panel power up across a sequence of
1985          * operations.
1986          */
1987         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1988         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1989 }
1990
1991 /*
1992  * Must be paired with edp_panel_vdd_on().
1993  * Must hold pps_mutex around the whole on/off sequence.
1994  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1995  */
1996 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1997 {
1998         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1999
2000         lockdep_assert_held(&dev_priv->pps_mutex);
2001
2002         if (!is_edp(intel_dp))
2003                 return;
2004
2005         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2006              port_name(dp_to_dig_port(intel_dp)->port));
2007
2008         intel_dp->want_panel_vdd = false;
2009
2010         if (sync)
2011                 edp_panel_vdd_off_sync(intel_dp);
2012         else
2013                 edp_panel_vdd_schedule_off(intel_dp);
2014 }
2015
2016 static void edp_panel_on(struct intel_dp *intel_dp)
2017 {
2018         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2019         struct drm_i915_private *dev_priv = to_i915(dev);
2020         u32 pp;
2021         i915_reg_t pp_ctrl_reg;
2022
2023         lockdep_assert_held(&dev_priv->pps_mutex);
2024
2025         if (!is_edp(intel_dp))
2026                 return;
2027
2028         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2029                       port_name(dp_to_dig_port(intel_dp)->port));
2030
2031         if (WARN(edp_have_panel_power(intel_dp),
2032                  "eDP port %c panel power already on\n",
2033                  port_name(dp_to_dig_port(intel_dp)->port)))
2034                 return;
2035
2036         wait_panel_power_cycle(intel_dp);
2037
2038         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2039         pp = ironlake_get_pp_control(intel_dp);
2040         if (IS_GEN5(dev)) {
2041                 /* ILK workaround: disable reset around power sequence */
2042                 pp &= ~PANEL_POWER_RESET;
2043                 I915_WRITE(pp_ctrl_reg, pp);
2044                 POSTING_READ(pp_ctrl_reg);
2045         }
2046
2047         pp |= POWER_TARGET_ON;
2048         if (!IS_GEN5(dev))
2049                 pp |= PANEL_POWER_RESET;
2050
2051         I915_WRITE(pp_ctrl_reg, pp);
2052         POSTING_READ(pp_ctrl_reg);
2053
2054         wait_panel_on(intel_dp);
2055         intel_dp->last_power_on = jiffies;
2056
2057         if (IS_GEN5(dev)) {
2058                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2059                 I915_WRITE(pp_ctrl_reg, pp);
2060                 POSTING_READ(pp_ctrl_reg);
2061         }
2062 }
2063
2064 void intel_edp_panel_on(struct intel_dp *intel_dp)
2065 {
2066         if (!is_edp(intel_dp))
2067                 return;
2068
2069         pps_lock(intel_dp);
2070         edp_panel_on(intel_dp);
2071         pps_unlock(intel_dp);
2072 }
2073
2074
2075 static void edp_panel_off(struct intel_dp *intel_dp)
2076 {
2077         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2078         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2079         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2080         struct drm_i915_private *dev_priv = to_i915(dev);
2081         enum intel_display_power_domain power_domain;
2082         u32 pp;
2083         i915_reg_t pp_ctrl_reg;
2084
2085         lockdep_assert_held(&dev_priv->pps_mutex);
2086
2087         if (!is_edp(intel_dp))
2088                 return;
2089
2090         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2091                       port_name(dp_to_dig_port(intel_dp)->port));
2092
2093         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2094              port_name(dp_to_dig_port(intel_dp)->port));
2095
2096         pp = ironlake_get_pp_control(intel_dp);
2097         /* We need to switch off panel power _and_ force vdd, for otherwise some
2098          * panels get very unhappy and cease to work. */
2099         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2100                 EDP_BLC_ENABLE);
2101
2102         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2103
2104         intel_dp->want_panel_vdd = false;
2105
2106         I915_WRITE(pp_ctrl_reg, pp);
2107         POSTING_READ(pp_ctrl_reg);
2108
2109         intel_dp->panel_power_off_time = ktime_get_boottime();
2110         wait_panel_off(intel_dp);
2111
2112         /* We got a reference when we enabled the VDD. */
2113         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2114         intel_display_power_put(dev_priv, power_domain);
2115 }
2116
2117 void intel_edp_panel_off(struct intel_dp *intel_dp)
2118 {
2119         if (!is_edp(intel_dp))
2120                 return;
2121
2122         pps_lock(intel_dp);
2123         edp_panel_off(intel_dp);
2124         pps_unlock(intel_dp);
2125 }
2126
2127 /* Enable backlight in the panel power control. */
2128 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2129 {
2130         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2131         struct drm_device *dev = intel_dig_port->base.base.dev;
2132         struct drm_i915_private *dev_priv = to_i915(dev);
2133         u32 pp;
2134         i915_reg_t pp_ctrl_reg;
2135
2136         /*
2137          * If we enable the backlight right away following a panel power
2138          * on, we may see slight flicker as the panel syncs with the eDP
2139          * link.  So delay a bit to make sure the image is solid before
2140          * allowing it to appear.
2141          */
2142         wait_backlight_on(intel_dp);
2143
2144         pps_lock(intel_dp);
2145
2146         pp = ironlake_get_pp_control(intel_dp);
2147         pp |= EDP_BLC_ENABLE;
2148
2149         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2150
2151         I915_WRITE(pp_ctrl_reg, pp);
2152         POSTING_READ(pp_ctrl_reg);
2153
2154         pps_unlock(intel_dp);
2155 }
2156
2157 /* Enable backlight PWM and backlight PP control. */
2158 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2159 {
2160         if (!is_edp(intel_dp))
2161                 return;
2162
2163         DRM_DEBUG_KMS("\n");
2164
2165         intel_panel_enable_backlight(intel_dp->attached_connector);
2166         _intel_edp_backlight_on(intel_dp);
2167 }
2168
2169 /* Disable backlight in the panel power control. */
2170 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2171 {
2172         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2173         struct drm_i915_private *dev_priv = to_i915(dev);
2174         u32 pp;
2175         i915_reg_t pp_ctrl_reg;
2176
2177         if (!is_edp(intel_dp))
2178                 return;
2179
2180         pps_lock(intel_dp);
2181
2182         pp = ironlake_get_pp_control(intel_dp);
2183         pp &= ~EDP_BLC_ENABLE;
2184
2185         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2186
2187         I915_WRITE(pp_ctrl_reg, pp);
2188         POSTING_READ(pp_ctrl_reg);
2189
2190         pps_unlock(intel_dp);
2191
2192         intel_dp->last_backlight_off = jiffies;
2193         edp_wait_backlight_off(intel_dp);
2194 }
2195
2196 /* Disable backlight PP control and backlight PWM. */
2197 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2198 {
2199         if (!is_edp(intel_dp))
2200                 return;
2201
2202         DRM_DEBUG_KMS("\n");
2203
2204         _intel_edp_backlight_off(intel_dp);
2205         intel_panel_disable_backlight(intel_dp->attached_connector);
2206 }
2207
2208 /*
2209  * Hook for controlling the panel power control backlight through the bl_power
2210  * sysfs attribute. Take care to handle multiple calls.
2211  */
2212 static void intel_edp_backlight_power(struct intel_connector *connector,
2213                                       bool enable)
2214 {
2215         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2216         bool is_enabled;
2217
2218         pps_lock(intel_dp);
2219         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2220         pps_unlock(intel_dp);
2221
2222         if (is_enabled == enable)
2223                 return;
2224
2225         DRM_DEBUG_KMS("panel power control backlight %s\n",
2226                       enable ? "enable" : "disable");
2227
2228         if (enable)
2229                 _intel_edp_backlight_on(intel_dp);
2230         else
2231                 _intel_edp_backlight_off(intel_dp);
2232 }
2233
2234 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2235 {
2236         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2237         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2238         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2239
2240         I915_STATE_WARN(cur_state != state,
2241                         "DP port %c state assertion failure (expected %s, current %s)\n",
2242                         port_name(dig_port->port),
2243                         onoff(state), onoff(cur_state));
2244 }
2245 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2246
2247 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2248 {
2249         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2250
2251         I915_STATE_WARN(cur_state != state,
2252                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2253                         onoff(state), onoff(cur_state));
2254 }
2255 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2256 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2257
2258 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2259 {
2260         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2261         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2262         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2263
2264         assert_pipe_disabled(dev_priv, crtc->pipe);
2265         assert_dp_port_disabled(intel_dp);
2266         assert_edp_pll_disabled(dev_priv);
2267
2268         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2269                       crtc->config->port_clock);
2270
2271         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2272
2273         if (crtc->config->port_clock == 162000)
2274                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2275         else
2276                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2277
2278         I915_WRITE(DP_A, intel_dp->DP);
2279         POSTING_READ(DP_A);
2280         udelay(500);
2281
2282         /*
2283          * [DevILK] Work around required when enabling DP PLL
2284          * while a pipe is enabled going to FDI:
2285          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2286          * 2. Program DP PLL enable
2287          */
2288         if (IS_GEN5(dev_priv))
2289                 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
2290
2291         intel_dp->DP |= DP_PLL_ENABLE;
2292
2293         I915_WRITE(DP_A, intel_dp->DP);
2294         POSTING_READ(DP_A);
2295         udelay(200);
2296 }
2297
2298 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2299 {
2300         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2301         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2302         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2303
2304         assert_pipe_disabled(dev_priv, crtc->pipe);
2305         assert_dp_port_disabled(intel_dp);
2306         assert_edp_pll_enabled(dev_priv);
2307
2308         DRM_DEBUG_KMS("disabling eDP PLL\n");
2309
2310         intel_dp->DP &= ~DP_PLL_ENABLE;
2311
2312         I915_WRITE(DP_A, intel_dp->DP);
2313         POSTING_READ(DP_A);
2314         udelay(200);
2315 }
2316
2317 /* If the sink supports it, try to set the power state appropriately */
2318 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2319 {
2320         int ret, i;
2321
2322         /* Should have a valid DPCD by this point */
2323         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2324                 return;
2325
2326         if (mode != DRM_MODE_DPMS_ON) {
2327                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2328                                          DP_SET_POWER_D3);
2329         } else {
2330                 /*
2331                  * When turning on, we need to retry for 1ms to give the sink
2332                  * time to wake up.
2333                  */
2334                 for (i = 0; i < 3; i++) {
2335                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2336                                                  DP_SET_POWER_D0);
2337                         if (ret == 1)
2338                                 break;
2339                         msleep(1);
2340                 }
2341         }
2342
2343         if (ret != 1)
2344                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2345                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2346 }
2347
2348 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2349                                   enum pipe *pipe)
2350 {
2351         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2352         enum port port = dp_to_dig_port(intel_dp)->port;
2353         struct drm_device *dev = encoder->base.dev;
2354         struct drm_i915_private *dev_priv = to_i915(dev);
2355         enum intel_display_power_domain power_domain;
2356         u32 tmp;
2357         bool ret;
2358
2359         power_domain = intel_display_port_power_domain(encoder);
2360         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2361                 return false;
2362
2363         ret = false;
2364
2365         tmp = I915_READ(intel_dp->output_reg);
2366
2367         if (!(tmp & DP_PORT_EN))
2368                 goto out;
2369
2370         if (IS_GEN7(dev) && port == PORT_A) {
2371                 *pipe = PORT_TO_PIPE_CPT(tmp);
2372         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2373                 enum pipe p;
2374
2375                 for_each_pipe(dev_priv, p) {
2376                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2377                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2378                                 *pipe = p;
2379                                 ret = true;
2380
2381                                 goto out;
2382                         }
2383                 }
2384
2385                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2386                               i915_mmio_reg_offset(intel_dp->output_reg));
2387         } else if (IS_CHERRYVIEW(dev)) {
2388                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2389         } else {
2390                 *pipe = PORT_TO_PIPE(tmp);
2391         }
2392
2393         ret = true;
2394
2395 out:
2396         intel_display_power_put(dev_priv, power_domain);
2397
2398         return ret;
2399 }
2400
2401 static void intel_dp_get_config(struct intel_encoder *encoder,
2402                                 struct intel_crtc_state *pipe_config)
2403 {
2404         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2405         u32 tmp, flags = 0;
2406         struct drm_device *dev = encoder->base.dev;
2407         struct drm_i915_private *dev_priv = to_i915(dev);
2408         enum port port = dp_to_dig_port(intel_dp)->port;
2409         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2410
2411         tmp = I915_READ(intel_dp->output_reg);
2412
2413         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2414
2415         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2416                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2417
2418                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2419                         flags |= DRM_MODE_FLAG_PHSYNC;
2420                 else
2421                         flags |= DRM_MODE_FLAG_NHSYNC;
2422
2423                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2424                         flags |= DRM_MODE_FLAG_PVSYNC;
2425                 else
2426                         flags |= DRM_MODE_FLAG_NVSYNC;
2427         } else {
2428                 if (tmp & DP_SYNC_HS_HIGH)
2429                         flags |= DRM_MODE_FLAG_PHSYNC;
2430                 else
2431                         flags |= DRM_MODE_FLAG_NHSYNC;
2432
2433                 if (tmp & DP_SYNC_VS_HIGH)
2434                         flags |= DRM_MODE_FLAG_PVSYNC;
2435                 else
2436                         flags |= DRM_MODE_FLAG_NVSYNC;
2437         }
2438
2439         pipe_config->base.adjusted_mode.flags |= flags;
2440
2441         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2442             !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2443                 pipe_config->limited_color_range = true;
2444
2445         pipe_config->has_dp_encoder = true;
2446
2447         pipe_config->lane_count =
2448                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2449
2450         intel_dp_get_m_n(crtc, pipe_config);
2451
2452         if (port == PORT_A) {
2453                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2454                         pipe_config->port_clock = 162000;
2455                 else
2456                         pipe_config->port_clock = 270000;
2457         }
2458
2459         pipe_config->base.adjusted_mode.crtc_clock =
2460                 intel_dotclock_calculate(pipe_config->port_clock,
2461                                          &pipe_config->dp_m_n);
2462
2463         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2464             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2465                 /*
2466                  * This is a big fat ugly hack.
2467                  *
2468                  * Some machines in UEFI boot mode provide us a VBT that has 18
2469                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2470                  * unknown we fail to light up. Yet the same BIOS boots up with
2471                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2472                  * max, not what it tells us to use.
2473                  *
2474                  * Note: This will still be broken if the eDP panel is not lit
2475                  * up by the BIOS, and thus we can't get the mode at module
2476                  * load.
2477                  */
2478                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2479                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2480                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2481         }
2482 }
2483
2484 static void intel_disable_dp(struct intel_encoder *encoder)
2485 {
2486         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2487         struct drm_device *dev = encoder->base.dev;
2488         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2489
2490         if (crtc->config->has_audio)
2491                 intel_audio_codec_disable(encoder);
2492
2493         if (HAS_PSR(dev) && !HAS_DDI(dev))
2494                 intel_psr_disable(intel_dp);
2495
2496         /* Make sure the panel is off before trying to change the mode. But also
2497          * ensure that we have vdd while we switch off the panel. */
2498         intel_edp_panel_vdd_on(intel_dp);
2499         intel_edp_backlight_off(intel_dp);
2500         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2501         intel_edp_panel_off(intel_dp);
2502
2503         /* disable the port before the pipe on g4x */
2504         if (INTEL_INFO(dev)->gen < 5)
2505                 intel_dp_link_down(intel_dp);
2506 }
2507
2508 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2509 {
2510         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2511         enum port port = dp_to_dig_port(intel_dp)->port;
2512
2513         intel_dp_link_down(intel_dp);
2514
2515         /* Only ilk+ has port A */
2516         if (port == PORT_A)
2517                 ironlake_edp_pll_off(intel_dp);
2518 }
2519
2520 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2521 {
2522         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2523
2524         intel_dp_link_down(intel_dp);
2525 }
2526
2527 static void chv_post_disable_dp(struct intel_encoder *encoder)
2528 {
2529         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2530         struct drm_device *dev = encoder->base.dev;
2531         struct drm_i915_private *dev_priv = to_i915(dev);
2532
2533         intel_dp_link_down(intel_dp);
2534
2535         mutex_lock(&dev_priv->sb_lock);
2536
2537         /* Assert data lane reset */
2538         chv_data_lane_soft_reset(encoder, true);
2539
2540         mutex_unlock(&dev_priv->sb_lock);
2541 }
2542
2543 static void
2544 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2545                          uint32_t *DP,
2546                          uint8_t dp_train_pat)
2547 {
2548         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2549         struct drm_device *dev = intel_dig_port->base.base.dev;
2550         struct drm_i915_private *dev_priv = to_i915(dev);
2551         enum port port = intel_dig_port->port;
2552
2553         if (HAS_DDI(dev)) {
2554                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2555
2556                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2557                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2558                 else
2559                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2560
2561                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2562                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2563                 case DP_TRAINING_PATTERN_DISABLE:
2564                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2565
2566                         break;
2567                 case DP_TRAINING_PATTERN_1:
2568                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2569                         break;
2570                 case DP_TRAINING_PATTERN_2:
2571                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2572                         break;
2573                 case DP_TRAINING_PATTERN_3:
2574                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2575                         break;
2576                 }
2577                 I915_WRITE(DP_TP_CTL(port), temp);
2578
2579         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2580                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2581                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2582
2583                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2584                 case DP_TRAINING_PATTERN_DISABLE:
2585                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2586                         break;
2587                 case DP_TRAINING_PATTERN_1:
2588                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2589                         break;
2590                 case DP_TRAINING_PATTERN_2:
2591                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2592                         break;
2593                 case DP_TRAINING_PATTERN_3:
2594                         DRM_ERROR("DP training pattern 3 not supported\n");
2595                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2596                         break;
2597                 }
2598
2599         } else {
2600                 if (IS_CHERRYVIEW(dev))
2601                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2602                 else
2603                         *DP &= ~DP_LINK_TRAIN_MASK;
2604
2605                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2606                 case DP_TRAINING_PATTERN_DISABLE:
2607                         *DP |= DP_LINK_TRAIN_OFF;
2608                         break;
2609                 case DP_TRAINING_PATTERN_1:
2610                         *DP |= DP_LINK_TRAIN_PAT_1;
2611                         break;
2612                 case DP_TRAINING_PATTERN_2:
2613                         *DP |= DP_LINK_TRAIN_PAT_2;
2614                         break;
2615                 case DP_TRAINING_PATTERN_3:
2616                         if (IS_CHERRYVIEW(dev)) {
2617                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2618                         } else {
2619                                 DRM_ERROR("DP training pattern 3 not supported\n");
2620                                 *DP |= DP_LINK_TRAIN_PAT_2;
2621                         }
2622                         break;
2623                 }
2624         }
2625 }
2626
2627 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2628 {
2629         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2630         struct drm_i915_private *dev_priv = to_i915(dev);
2631         struct intel_crtc *crtc =
2632                 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2633
2634         /* enable with pattern 1 (as per spec) */
2635         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2636                                  DP_TRAINING_PATTERN_1);
2637
2638         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2639         POSTING_READ(intel_dp->output_reg);
2640
2641         /*
2642          * Magic for VLV/CHV. We _must_ first set up the register
2643          * without actually enabling the port, and then do another
2644          * write to enable the port. Otherwise link training will
2645          * fail when the power sequencer is freshly used for this port.
2646          */
2647         intel_dp->DP |= DP_PORT_EN;
2648         if (crtc->config->has_audio)
2649                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2650
2651         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2652         POSTING_READ(intel_dp->output_reg);
2653 }
2654
2655 static void intel_enable_dp(struct intel_encoder *encoder)
2656 {
2657         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2658         struct drm_device *dev = encoder->base.dev;
2659         struct drm_i915_private *dev_priv = to_i915(dev);
2660         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2661         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2662         enum pipe pipe = crtc->pipe;
2663
2664         if (WARN_ON(dp_reg & DP_PORT_EN))
2665                 return;
2666
2667         pps_lock(intel_dp);
2668
2669         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2670                 vlv_init_panel_power_sequencer(intel_dp);
2671
2672         intel_dp_enable_port(intel_dp);
2673
2674         edp_panel_vdd_on(intel_dp);
2675         edp_panel_on(intel_dp);
2676         edp_panel_vdd_off(intel_dp, true);
2677
2678         pps_unlock(intel_dp);
2679
2680         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2681                 unsigned int lane_mask = 0x0;
2682
2683                 if (IS_CHERRYVIEW(dev))
2684                         lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2685
2686                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2687                                     lane_mask);
2688         }
2689
2690         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2691         intel_dp_start_link_train(intel_dp);
2692         intel_dp_stop_link_train(intel_dp);
2693
2694         if (crtc->config->has_audio) {
2695                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2696                                  pipe_name(pipe));
2697                 intel_audio_codec_enable(encoder);
2698         }
2699 }
2700
2701 static void g4x_enable_dp(struct intel_encoder *encoder)
2702 {
2703         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2704
2705         intel_enable_dp(encoder);
2706         intel_edp_backlight_on(intel_dp);
2707 }
2708
2709 static void vlv_enable_dp(struct intel_encoder *encoder)
2710 {
2711         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2712
2713         intel_edp_backlight_on(intel_dp);
2714         intel_psr_enable(intel_dp);
2715 }
2716
2717 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2718 {
2719         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2720         enum port port = dp_to_dig_port(intel_dp)->port;
2721
2722         intel_dp_prepare(encoder);
2723
2724         /* Only ilk+ has port A */
2725         if (port == PORT_A)
2726                 ironlake_edp_pll_on(intel_dp);
2727 }
2728
2729 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2730 {
2731         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2732         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2733         enum pipe pipe = intel_dp->pps_pipe;
2734         i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2735
2736         edp_panel_vdd_off_sync(intel_dp);
2737
2738         /*
2739          * VLV seems to get confused when multiple power seqeuencers
2740          * have the same port selected (even if only one has power/vdd
2741          * enabled). The failure manifests as vlv_wait_port_ready() failing
2742          * CHV on the other hand doesn't seem to mind having the same port
2743          * selected in multiple power seqeuencers, but let's clear the
2744          * port select always when logically disconnecting a power sequencer
2745          * from a port.
2746          */
2747         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2748                       pipe_name(pipe), port_name(intel_dig_port->port));
2749         I915_WRITE(pp_on_reg, 0);
2750         POSTING_READ(pp_on_reg);
2751
2752         intel_dp->pps_pipe = INVALID_PIPE;
2753 }
2754
2755 static void vlv_steal_power_sequencer(struct drm_device *dev,
2756                                       enum pipe pipe)
2757 {
2758         struct drm_i915_private *dev_priv = to_i915(dev);
2759         struct intel_encoder *encoder;
2760
2761         lockdep_assert_held(&dev_priv->pps_mutex);
2762
2763         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2764                 return;
2765
2766         for_each_intel_encoder(dev, encoder) {
2767                 struct intel_dp *intel_dp;
2768                 enum port port;
2769
2770                 if (encoder->type != INTEL_OUTPUT_EDP)
2771                         continue;
2772
2773                 intel_dp = enc_to_intel_dp(&encoder->base);
2774                 port = dp_to_dig_port(intel_dp)->port;
2775
2776                 if (intel_dp->pps_pipe != pipe)
2777                         continue;
2778
2779                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2780                               pipe_name(pipe), port_name(port));
2781
2782                 WARN(encoder->base.crtc,
2783                      "stealing pipe %c power sequencer from active eDP port %c\n",
2784                      pipe_name(pipe), port_name(port));
2785
2786                 /* make sure vdd is off before we steal it */
2787                 vlv_detach_power_sequencer(intel_dp);
2788         }
2789 }
2790
2791 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2792 {
2793         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2794         struct intel_encoder *encoder = &intel_dig_port->base;
2795         struct drm_device *dev = encoder->base.dev;
2796         struct drm_i915_private *dev_priv = to_i915(dev);
2797         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2798
2799         lockdep_assert_held(&dev_priv->pps_mutex);
2800
2801         if (!is_edp(intel_dp))
2802                 return;
2803
2804         if (intel_dp->pps_pipe == crtc->pipe)
2805                 return;
2806
2807         /*
2808          * If another power sequencer was being used on this
2809          * port previously make sure to turn off vdd there while
2810          * we still have control of it.
2811          */
2812         if (intel_dp->pps_pipe != INVALID_PIPE)
2813                 vlv_detach_power_sequencer(intel_dp);
2814
2815         /*
2816          * We may be stealing the power
2817          * sequencer from another port.
2818          */
2819         vlv_steal_power_sequencer(dev, crtc->pipe);
2820
2821         /* now it's all ours */
2822         intel_dp->pps_pipe = crtc->pipe;
2823
2824         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2825                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2826
2827         /* init power sequencer on this pipe and port */
2828         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2829         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2830 }
2831
2832 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2833 {
2834         vlv_phy_pre_encoder_enable(encoder);
2835
2836         intel_enable_dp(encoder);
2837 }
2838
2839 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2840 {
2841         intel_dp_prepare(encoder);
2842
2843         vlv_phy_pre_pll_enable(encoder);
2844 }
2845
2846 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2847 {
2848         chv_phy_pre_encoder_enable(encoder);
2849
2850         intel_enable_dp(encoder);
2851
2852         /* Second common lane will stay alive on its own now */
2853         chv_phy_release_cl2_override(encoder);
2854 }
2855
2856 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2857 {
2858         intel_dp_prepare(encoder);
2859
2860         chv_phy_pre_pll_enable(encoder);
2861 }
2862
2863 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
2864 {
2865         chv_phy_post_pll_disable(encoder);
2866 }
2867
2868 /*
2869  * Fetch AUX CH registers 0x202 - 0x207 which contain
2870  * link status information
2871  */
2872 bool
2873 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2874 {
2875         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2876                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2877 }
2878
2879 /* These are source-specific values. */
2880 uint8_t
2881 intel_dp_voltage_max(struct intel_dp *intel_dp)
2882 {
2883         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2884         struct drm_i915_private *dev_priv = to_i915(dev);
2885         enum port port = dp_to_dig_port(intel_dp)->port;
2886
2887         if (IS_BROXTON(dev))
2888                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2889         else if (INTEL_INFO(dev)->gen >= 9) {
2890                 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2891                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2892                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2893         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2894                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2895         else if (IS_GEN7(dev) && port == PORT_A)
2896                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2897         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2898                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2899         else
2900                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2901 }
2902
2903 uint8_t
2904 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2905 {
2906         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2907         enum port port = dp_to_dig_port(intel_dp)->port;
2908
2909         if (INTEL_INFO(dev)->gen >= 9) {
2910                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2911                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2912                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2913                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2914                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2915                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2916                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2917                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2918                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2919                 default:
2920                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2921                 }
2922         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2923                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2924                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2925                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2926                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2927                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2928                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2929                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2930                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2931                 default:
2932                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2933                 }
2934         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2935                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2936                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2937                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2938                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2939                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2940                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2941                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2942                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2943                 default:
2944                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2945                 }
2946         } else if (IS_GEN7(dev) && port == PORT_A) {
2947                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2948                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2949                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2950                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2951                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2952                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2953                 default:
2954                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2955                 }
2956         } else {
2957                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2958                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2959                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2960                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2961                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2962                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2963                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2964                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2965                 default:
2966                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2967                 }
2968         }
2969 }
2970
2971 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
2972 {
2973         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2974         unsigned long demph_reg_value, preemph_reg_value,
2975                 uniqtranscale_reg_value;
2976         uint8_t train_set = intel_dp->train_set[0];
2977
2978         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2979         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2980                 preemph_reg_value = 0x0004000;
2981                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2982                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2983                         demph_reg_value = 0x2B405555;
2984                         uniqtranscale_reg_value = 0x552AB83A;
2985                         break;
2986                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2987                         demph_reg_value = 0x2B404040;
2988                         uniqtranscale_reg_value = 0x5548B83A;
2989                         break;
2990                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2991                         demph_reg_value = 0x2B245555;
2992                         uniqtranscale_reg_value = 0x5560B83A;
2993                         break;
2994                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2995                         demph_reg_value = 0x2B405555;
2996                         uniqtranscale_reg_value = 0x5598DA3A;
2997                         break;
2998                 default:
2999                         return 0;
3000                 }
3001                 break;
3002         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3003                 preemph_reg_value = 0x0002000;
3004                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3005                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3006                         demph_reg_value = 0x2B404040;
3007                         uniqtranscale_reg_value = 0x5552B83A;
3008                         break;
3009                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3010                         demph_reg_value = 0x2B404848;
3011                         uniqtranscale_reg_value = 0x5580B83A;
3012                         break;
3013                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3014                         demph_reg_value = 0x2B404040;
3015                         uniqtranscale_reg_value = 0x55ADDA3A;
3016                         break;
3017                 default:
3018                         return 0;
3019                 }
3020                 break;
3021         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3022                 preemph_reg_value = 0x0000000;
3023                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3024                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3025                         demph_reg_value = 0x2B305555;
3026                         uniqtranscale_reg_value = 0x5570B83A;
3027                         break;
3028                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3029                         demph_reg_value = 0x2B2B4040;
3030                         uniqtranscale_reg_value = 0x55ADDA3A;
3031                         break;
3032                 default:
3033                         return 0;
3034                 }
3035                 break;
3036         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3037                 preemph_reg_value = 0x0006000;
3038                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3039                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3040                         demph_reg_value = 0x1B405555;
3041                         uniqtranscale_reg_value = 0x55ADDA3A;
3042                         break;
3043                 default:
3044                         return 0;
3045                 }
3046                 break;
3047         default:
3048                 return 0;
3049         }
3050
3051         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3052                                  uniqtranscale_reg_value, 0);
3053
3054         return 0;
3055 }
3056
3057 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3058 {
3059         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3060         u32 deemph_reg_value, margin_reg_value;
3061         bool uniq_trans_scale = false;
3062         uint8_t train_set = intel_dp->train_set[0];
3063
3064         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3065         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3066                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3067                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3068                         deemph_reg_value = 128;
3069                         margin_reg_value = 52;
3070                         break;
3071                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3072                         deemph_reg_value = 128;
3073                         margin_reg_value = 77;
3074                         break;
3075                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3076                         deemph_reg_value = 128;
3077                         margin_reg_value = 102;
3078                         break;
3079                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3080                         deemph_reg_value = 128;
3081                         margin_reg_value = 154;
3082                         uniq_trans_scale = true;
3083                         break;
3084                 default:
3085                         return 0;
3086                 }
3087                 break;
3088         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3089                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3090                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3091                         deemph_reg_value = 85;
3092                         margin_reg_value = 78;
3093                         break;
3094                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3095                         deemph_reg_value = 85;
3096                         margin_reg_value = 116;
3097                         break;
3098                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3099                         deemph_reg_value = 85;
3100                         margin_reg_value = 154;
3101                         break;
3102                 default:
3103                         return 0;
3104                 }
3105                 break;
3106         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3107                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3108                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3109                         deemph_reg_value = 64;
3110                         margin_reg_value = 104;
3111                         break;
3112                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3113                         deemph_reg_value = 64;
3114                         margin_reg_value = 154;
3115                         break;
3116                 default:
3117                         return 0;
3118                 }
3119                 break;
3120         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3121                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3122                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3123                         deemph_reg_value = 43;
3124                         margin_reg_value = 154;
3125                         break;
3126                 default:
3127                         return 0;
3128                 }
3129                 break;
3130         default:
3131                 return 0;
3132         }
3133
3134         chv_set_phy_signal_level(encoder, deemph_reg_value,
3135                                  margin_reg_value, uniq_trans_scale);
3136
3137         return 0;
3138 }
3139
3140 static uint32_t
3141 gen4_signal_levels(uint8_t train_set)
3142 {
3143         uint32_t        signal_levels = 0;
3144
3145         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3146         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3147         default:
3148                 signal_levels |= DP_VOLTAGE_0_4;
3149                 break;
3150         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3151                 signal_levels |= DP_VOLTAGE_0_6;
3152                 break;
3153         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3154                 signal_levels |= DP_VOLTAGE_0_8;
3155                 break;
3156         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3157                 signal_levels |= DP_VOLTAGE_1_2;
3158                 break;
3159         }
3160         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3161         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3162         default:
3163                 signal_levels |= DP_PRE_EMPHASIS_0;
3164                 break;
3165         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3166                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3167                 break;
3168         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3169                 signal_levels |= DP_PRE_EMPHASIS_6;
3170                 break;
3171         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3172                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3173                 break;
3174         }
3175         return signal_levels;
3176 }
3177
3178 /* Gen6's DP voltage swing and pre-emphasis control */
3179 static uint32_t
3180 gen6_edp_signal_levels(uint8_t train_set)
3181 {
3182         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3183                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3184         switch (signal_levels) {
3185         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3186         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3187                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3188         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3189                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3190         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3191         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3192                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3193         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3194         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3195                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3196         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3197         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3198                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3199         default:
3200                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3201                               "0x%x\n", signal_levels);
3202                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3203         }
3204 }
3205
3206 /* Gen7's DP voltage swing and pre-emphasis control */
3207 static uint32_t
3208 gen7_edp_signal_levels(uint8_t train_set)
3209 {
3210         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3211                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3212         switch (signal_levels) {
3213         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3214                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3215         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3216                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3217         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3218                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3219
3220         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3221                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3222         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3223                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3224
3225         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3226                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3227         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3228                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3229
3230         default:
3231                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3232                               "0x%x\n", signal_levels);
3233                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3234         }
3235 }
3236
3237 void
3238 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3239 {
3240         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3241         enum port port = intel_dig_port->port;
3242         struct drm_device *dev = intel_dig_port->base.base.dev;
3243         struct drm_i915_private *dev_priv = to_i915(dev);
3244         uint32_t signal_levels, mask = 0;
3245         uint8_t train_set = intel_dp->train_set[0];
3246
3247         if (HAS_DDI(dev)) {
3248                 signal_levels = ddi_signal_levels(intel_dp);
3249
3250                 if (IS_BROXTON(dev))
3251                         signal_levels = 0;
3252                 else
3253                         mask = DDI_BUF_EMP_MASK;
3254         } else if (IS_CHERRYVIEW(dev)) {
3255                 signal_levels = chv_signal_levels(intel_dp);
3256         } else if (IS_VALLEYVIEW(dev)) {
3257                 signal_levels = vlv_signal_levels(intel_dp);
3258         } else if (IS_GEN7(dev) && port == PORT_A) {
3259                 signal_levels = gen7_edp_signal_levels(train_set);
3260                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3261         } else if (IS_GEN6(dev) && port == PORT_A) {
3262                 signal_levels = gen6_edp_signal_levels(train_set);
3263                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3264         } else {
3265                 signal_levels = gen4_signal_levels(train_set);
3266                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3267         }
3268
3269         if (mask)
3270                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3271
3272         DRM_DEBUG_KMS("Using vswing level %d\n",
3273                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3274         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3275                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3276                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3277
3278         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3279
3280         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3281         POSTING_READ(intel_dp->output_reg);
3282 }
3283
3284 void
3285 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3286                                        uint8_t dp_train_pat)
3287 {
3288         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3289         struct drm_i915_private *dev_priv =
3290                 to_i915(intel_dig_port->base.base.dev);
3291
3292         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3293
3294         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3295         POSTING_READ(intel_dp->output_reg);
3296 }
3297
3298 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3299 {
3300         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3301         struct drm_device *dev = intel_dig_port->base.base.dev;
3302         struct drm_i915_private *dev_priv = to_i915(dev);
3303         enum port port = intel_dig_port->port;
3304         uint32_t val;
3305
3306         if (!HAS_DDI(dev))
3307                 return;
3308
3309         val = I915_READ(DP_TP_CTL(port));
3310         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3311         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3312         I915_WRITE(DP_TP_CTL(port), val);
3313
3314         /*
3315          * On PORT_A we can have only eDP in SST mode. There the only reason
3316          * we need to set idle transmission mode is to work around a HW issue
3317          * where we enable the pipe while not in idle link-training mode.
3318          * In this case there is requirement to wait for a minimum number of
3319          * idle patterns to be sent.
3320          */
3321         if (port == PORT_A)
3322                 return;
3323
3324         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3325                                     DP_TP_STATUS_IDLE_DONE,
3326                                     DP_TP_STATUS_IDLE_DONE,
3327                                     1))
3328                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3329 }
3330
3331 static void
3332 intel_dp_link_down(struct intel_dp *intel_dp)
3333 {
3334         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3335         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3336         enum port port = intel_dig_port->port;
3337         struct drm_device *dev = intel_dig_port->base.base.dev;
3338         struct drm_i915_private *dev_priv = to_i915(dev);
3339         uint32_t DP = intel_dp->DP;
3340
3341         if (WARN_ON(HAS_DDI(dev)))
3342                 return;
3343
3344         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3345                 return;
3346
3347         DRM_DEBUG_KMS("\n");
3348
3349         if ((IS_GEN7(dev) && port == PORT_A) ||
3350             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3351                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3352                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3353         } else {
3354                 if (IS_CHERRYVIEW(dev))
3355                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3356                 else
3357                         DP &= ~DP_LINK_TRAIN_MASK;
3358                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3359         }
3360         I915_WRITE(intel_dp->output_reg, DP);
3361         POSTING_READ(intel_dp->output_reg);
3362
3363         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3364         I915_WRITE(intel_dp->output_reg, DP);
3365         POSTING_READ(intel_dp->output_reg);
3366
3367         /*
3368          * HW workaround for IBX, we need to move the port
3369          * to transcoder A after disabling it to allow the
3370          * matching HDMI port to be enabled on transcoder A.
3371          */
3372         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3373                 /*
3374                  * We get CPU/PCH FIFO underruns on the other pipe when
3375                  * doing the workaround. Sweep them under the rug.
3376                  */
3377                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3378                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3379
3380                 /* always enable with pattern 1 (as per spec) */
3381                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3382                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3383                 I915_WRITE(intel_dp->output_reg, DP);
3384                 POSTING_READ(intel_dp->output_reg);
3385
3386                 DP &= ~DP_PORT_EN;
3387                 I915_WRITE(intel_dp->output_reg, DP);
3388                 POSTING_READ(intel_dp->output_reg);
3389
3390                 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
3391                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3392                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3393         }
3394
3395         msleep(intel_dp->panel_power_down_delay);
3396
3397         intel_dp->DP = DP;
3398 }
3399
3400 static bool
3401 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3402 {
3403         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3404         struct drm_device *dev = dig_port->base.base.dev;
3405         struct drm_i915_private *dev_priv = to_i915(dev);
3406
3407         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3408                              sizeof(intel_dp->dpcd)) < 0)
3409                 return false; /* aux transfer failed */
3410
3411         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3412
3413         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3414                 return false; /* DPCD not present */
3415
3416         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3417                              &intel_dp->sink_count, 1) < 0)
3418                 return false;
3419
3420         /*
3421          * Sink count can change between short pulse hpd hence
3422          * a member variable in intel_dp will track any changes
3423          * between short pulse interrupts.
3424          */
3425         intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3426
3427         /*
3428          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3429          * a dongle is present but no display. Unless we require to know
3430          * if a dongle is present or not, we don't need to update
3431          * downstream port information. So, an early return here saves
3432          * time from performing other operations which are not required.
3433          */
3434         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3435                 return false;
3436
3437         /* Check if the panel supports PSR */
3438         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3439         if (is_edp(intel_dp)) {
3440                 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3441                                  intel_dp->psr_dpcd,
3442                                  sizeof(intel_dp->psr_dpcd));
3443                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3444                         dev_priv->psr.sink_support = true;
3445                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3446                 }
3447
3448                 if (INTEL_INFO(dev)->gen >= 9 &&
3449                         (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3450                         uint8_t frame_sync_cap;
3451
3452                         dev_priv->psr.sink_support = true;
3453                         drm_dp_dpcd_read(&intel_dp->aux,
3454                                          DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3455                                          &frame_sync_cap, 1);
3456                         dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3457                         /* PSR2 needs frame sync as well */
3458                         dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3459                         DRM_DEBUG_KMS("PSR2 %s on sink",
3460                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
3461                 }
3462
3463                 /* Read the eDP Display control capabilities registers */
3464                 memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
3465                 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3466                                 (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3467                                                 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3468                                                                 sizeof(intel_dp->edp_dpcd)))
3469                         DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3470                                         intel_dp->edp_dpcd);
3471         }
3472
3473         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3474                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
3475                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
3476
3477         /* Intermediate frequency support */
3478         if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
3479                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3480                 int i;
3481
3482                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3483                                 sink_rates, sizeof(sink_rates));
3484
3485                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3486                         int val = le16_to_cpu(sink_rates[i]);
3487
3488                         if (val == 0)
3489                                 break;
3490
3491                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3492                         intel_dp->sink_rates[i] = (val * 200) / 10;
3493                 }
3494                 intel_dp->num_sink_rates = i;
3495         }
3496
3497         intel_dp_print_rates(intel_dp);
3498
3499         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3500               DP_DWN_STRM_PORT_PRESENT))
3501                 return true; /* native DP sink */
3502
3503         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3504                 return true; /* no per-port downstream info */
3505
3506         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3507                              intel_dp->downstream_ports,
3508                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3509                 return false; /* downstream port status fetch failed */
3510
3511         return true;
3512 }
3513
3514 static void
3515 intel_dp_probe_oui(struct intel_dp *intel_dp)
3516 {
3517         u8 buf[3];
3518
3519         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3520                 return;
3521
3522         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3523                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3524                               buf[0], buf[1], buf[2]);
3525
3526         if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3527                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3528                               buf[0], buf[1], buf[2]);
3529 }
3530
3531 static bool
3532 intel_dp_probe_mst(struct intel_dp *intel_dp)
3533 {
3534         u8 buf[1];
3535
3536         if (!i915.enable_dp_mst)
3537                 return false;
3538
3539         if (!intel_dp->can_mst)
3540                 return false;
3541
3542         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3543                 return false;
3544
3545         if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3546                 if (buf[0] & DP_MST_CAP) {
3547                         DRM_DEBUG_KMS("Sink is MST capable\n");
3548                         intel_dp->is_mst = true;
3549                 } else {
3550                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3551                         intel_dp->is_mst = false;
3552                 }
3553         }
3554
3555         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3556         return intel_dp->is_mst;
3557 }
3558
3559 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3560 {
3561         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3562         struct drm_device *dev = dig_port->base.base.dev;
3563         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3564         u8 buf;
3565         int ret = 0;
3566         int count = 0;
3567         int attempts = 10;
3568
3569         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3570                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3571                 ret = -EIO;
3572                 goto out;
3573         }
3574
3575         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3576                                buf & ~DP_TEST_SINK_START) < 0) {
3577                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3578                 ret = -EIO;
3579                 goto out;
3580         }
3581
3582         do {
3583                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3584
3585                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3586                                       DP_TEST_SINK_MISC, &buf) < 0) {
3587                         ret = -EIO;
3588                         goto out;
3589                 }
3590                 count = buf & DP_TEST_COUNT_MASK;
3591         } while (--attempts && count);
3592
3593         if (attempts == 0) {
3594                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3595                 ret = -ETIMEDOUT;
3596         }
3597
3598  out:
3599         hsw_enable_ips(intel_crtc);
3600         return ret;
3601 }
3602
3603 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3604 {
3605         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3606         struct drm_device *dev = dig_port->base.base.dev;
3607         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3608         u8 buf;
3609         int ret;
3610
3611         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3612                 return -EIO;
3613
3614         if (!(buf & DP_TEST_CRC_SUPPORTED))
3615                 return -ENOTTY;
3616
3617         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3618                 return -EIO;
3619
3620         if (buf & DP_TEST_SINK_START) {
3621                 ret = intel_dp_sink_crc_stop(intel_dp);
3622                 if (ret)
3623                         return ret;
3624         }
3625
3626         hsw_disable_ips(intel_crtc);
3627
3628         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3629                                buf | DP_TEST_SINK_START) < 0) {
3630                 hsw_enable_ips(intel_crtc);
3631                 return -EIO;
3632         }
3633
3634         intel_wait_for_vblank(dev, intel_crtc->pipe);
3635         return 0;
3636 }
3637
3638 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3639 {
3640         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3641         struct drm_device *dev = dig_port->base.base.dev;
3642         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3643         u8 buf;
3644         int count, ret;
3645         int attempts = 6;
3646
3647         ret = intel_dp_sink_crc_start(intel_dp);
3648         if (ret)
3649                 return ret;
3650
3651         do {
3652                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3653
3654                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3655                                       DP_TEST_SINK_MISC, &buf) < 0) {
3656                         ret = -EIO;
3657                         goto stop;
3658                 }
3659                 count = buf & DP_TEST_COUNT_MASK;
3660
3661         } while (--attempts && count == 0);
3662
3663         if (attempts == 0) {
3664                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3665                 ret = -ETIMEDOUT;
3666                 goto stop;
3667         }
3668
3669         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3670                 ret = -EIO;
3671                 goto stop;
3672         }
3673
3674 stop:
3675         intel_dp_sink_crc_stop(intel_dp);
3676         return ret;
3677 }
3678
3679 static bool
3680 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3681 {
3682         return drm_dp_dpcd_read(&intel_dp->aux,
3683                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3684                                        sink_irq_vector, 1) == 1;
3685 }
3686
3687 static bool
3688 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3689 {
3690         int ret;
3691
3692         ret = drm_dp_dpcd_read(&intel_dp->aux,
3693                                              DP_SINK_COUNT_ESI,
3694                                              sink_irq_vector, 14);
3695         if (ret != 14)
3696                 return false;
3697
3698         return true;
3699 }
3700
3701 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3702 {
3703         uint8_t test_result = DP_TEST_ACK;
3704         return test_result;
3705 }
3706
3707 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3708 {
3709         uint8_t test_result = DP_TEST_NAK;
3710         return test_result;
3711 }
3712
3713 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3714 {
3715         uint8_t test_result = DP_TEST_NAK;
3716         struct intel_connector *intel_connector = intel_dp->attached_connector;
3717         struct drm_connector *connector = &intel_connector->base;
3718
3719         if (intel_connector->detect_edid == NULL ||
3720             connector->edid_corrupt ||
3721             intel_dp->aux.i2c_defer_count > 6) {
3722                 /* Check EDID read for NACKs, DEFERs and corruption
3723                  * (DP CTS 1.2 Core r1.1)
3724                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3725                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3726                  *    4.2.2.6 : EDID corruption detected
3727                  * Use failsafe mode for all cases
3728                  */
3729                 if (intel_dp->aux.i2c_nack_count > 0 ||
3730                         intel_dp->aux.i2c_defer_count > 0)
3731                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3732                                       intel_dp->aux.i2c_nack_count,
3733                                       intel_dp->aux.i2c_defer_count);
3734                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3735         } else {
3736                 struct edid *block = intel_connector->detect_edid;
3737
3738                 /* We have to write the checksum
3739                  * of the last block read
3740                  */
3741                 block += intel_connector->detect_edid->extensions;
3742
3743                 if (!drm_dp_dpcd_write(&intel_dp->aux,
3744                                         DP_TEST_EDID_CHECKSUM,
3745                                         &block->checksum,
3746                                         1))
3747                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3748
3749                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3750                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3751         }
3752
3753         /* Set test active flag here so userspace doesn't interrupt things */
3754         intel_dp->compliance_test_active = 1;
3755
3756         return test_result;
3757 }
3758
3759 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3760 {
3761         uint8_t test_result = DP_TEST_NAK;
3762         return test_result;
3763 }
3764
3765 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3766 {
3767         uint8_t response = DP_TEST_NAK;
3768         uint8_t rxdata = 0;
3769         int status = 0;
3770
3771         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3772         if (status <= 0) {
3773                 DRM_DEBUG_KMS("Could not read test request from sink\n");
3774                 goto update_status;
3775         }
3776
3777         switch (rxdata) {
3778         case DP_TEST_LINK_TRAINING:
3779                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3780                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3781                 response = intel_dp_autotest_link_training(intel_dp);
3782                 break;
3783         case DP_TEST_LINK_VIDEO_PATTERN:
3784                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3785                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3786                 response = intel_dp_autotest_video_pattern(intel_dp);
3787                 break;
3788         case DP_TEST_LINK_EDID_READ:
3789                 DRM_DEBUG_KMS("EDID test requested\n");
3790                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3791                 response = intel_dp_autotest_edid(intel_dp);
3792                 break;
3793         case DP_TEST_LINK_PHY_TEST_PATTERN:
3794                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3795                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3796                 response = intel_dp_autotest_phy_pattern(intel_dp);
3797                 break;
3798         default:
3799                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3800                 break;
3801         }
3802
3803 update_status:
3804         status = drm_dp_dpcd_write(&intel_dp->aux,
3805                                    DP_TEST_RESPONSE,
3806                                    &response, 1);
3807         if (status <= 0)
3808                 DRM_DEBUG_KMS("Could not write test response to sink\n");
3809 }
3810
3811 static int
3812 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3813 {
3814         bool bret;
3815
3816         if (intel_dp->is_mst) {
3817                 u8 esi[16] = { 0 };
3818                 int ret = 0;
3819                 int retry;
3820                 bool handled;
3821                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3822 go_again:
3823                 if (bret == true) {
3824
3825                         /* check link status - esi[10] = 0x200c */
3826                         if (intel_dp->active_mst_links &&
3827                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3828                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3829                                 intel_dp_start_link_train(intel_dp);
3830                                 intel_dp_stop_link_train(intel_dp);
3831                         }
3832
3833                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
3834                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3835
3836                         if (handled) {
3837                                 for (retry = 0; retry < 3; retry++) {
3838                                         int wret;
3839                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3840                                                                  DP_SINK_COUNT_ESI+1,
3841                                                                  &esi[1], 3);
3842                                         if (wret == 3) {
3843                                                 break;
3844                                         }
3845                                 }
3846
3847                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3848                                 if (bret == true) {
3849                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3850                                         goto go_again;
3851                                 }
3852                         } else
3853                                 ret = 0;
3854
3855                         return ret;
3856                 } else {
3857                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3858                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3859                         intel_dp->is_mst = false;
3860                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3861                         /* send a hotplug event */
3862                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3863                 }
3864         }
3865         return -EINVAL;
3866 }
3867
3868 static void
3869 intel_dp_check_link_status(struct intel_dp *intel_dp)
3870 {
3871         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3872         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3873         u8 link_status[DP_LINK_STATUS_SIZE];
3874
3875         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3876
3877         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3878                 DRM_ERROR("Failed to get link status\n");
3879                 return;
3880         }
3881
3882         if (!intel_encoder->base.crtc)
3883                 return;
3884
3885         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3886                 return;
3887
3888         /* if link training is requested we should perform it always */
3889         if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3890             (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3891                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3892                               intel_encoder->base.name);
3893                 intel_dp_start_link_train(intel_dp);
3894                 intel_dp_stop_link_train(intel_dp);
3895         }
3896 }
3897
3898 /*
3899  * According to DP spec
3900  * 5.1.2:
3901  *  1. Read DPCD
3902  *  2. Configure link according to Receiver Capabilities
3903  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3904  *  4. Check link status on receipt of hot-plug interrupt
3905  *
3906  * intel_dp_short_pulse -  handles short pulse interrupts
3907  * when full detection is not required.
3908  * Returns %true if short pulse is handled and full detection
3909  * is NOT required and %false otherwise.
3910  */
3911 static bool
3912 intel_dp_short_pulse(struct intel_dp *intel_dp)
3913 {
3914         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3915         u8 sink_irq_vector;
3916         u8 old_sink_count = intel_dp->sink_count;
3917         bool ret;
3918
3919         /*
3920          * Clearing compliance test variables to allow capturing
3921          * of values for next automated test request.
3922          */
3923         intel_dp->compliance_test_active = 0;
3924         intel_dp->compliance_test_type = 0;
3925         intel_dp->compliance_test_data = 0;
3926
3927         /*
3928          * Now read the DPCD to see if it's actually running
3929          * If the current value of sink count doesn't match with
3930          * the value that was stored earlier or dpcd read failed
3931          * we need to do full detection
3932          */
3933         ret = intel_dp_get_dpcd(intel_dp);
3934
3935         if ((old_sink_count != intel_dp->sink_count) || !ret) {
3936                 /* No need to proceed if we are going to do full detect */
3937                 return false;
3938         }
3939
3940         /* Try to read the source of the interrupt */
3941         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3942             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3943                 /* Clear interrupt source */
3944                 drm_dp_dpcd_writeb(&intel_dp->aux,
3945                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3946                                    sink_irq_vector);
3947
3948                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3949                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
3950                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3951                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3952         }
3953
3954         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3955         intel_dp_check_link_status(intel_dp);
3956         drm_modeset_unlock(&dev->mode_config.connection_mutex);
3957
3958         return true;
3959 }
3960
3961 /* XXX this is probably wrong for multiple downstream ports */
3962 static enum drm_connector_status
3963 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3964 {
3965         uint8_t *dpcd = intel_dp->dpcd;
3966         uint8_t type;
3967
3968         if (!intel_dp_get_dpcd(intel_dp))
3969                 return connector_status_disconnected;
3970
3971         if (is_edp(intel_dp))
3972                 return connector_status_connected;
3973
3974         /* if there's no downstream port, we're done */
3975         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3976                 return connector_status_connected;
3977
3978         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3979         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3980             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3981
3982                 return intel_dp->sink_count ?
3983                 connector_status_connected : connector_status_disconnected;
3984         }
3985
3986         /* If no HPD, poke DDC gently */
3987         if (drm_probe_ddc(&intel_dp->aux.ddc))
3988                 return connector_status_connected;
3989
3990         /* Well we tried, say unknown for unreliable port types */
3991         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3992                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3993                 if (type == DP_DS_PORT_TYPE_VGA ||
3994                     type == DP_DS_PORT_TYPE_NON_EDID)
3995                         return connector_status_unknown;
3996         } else {
3997                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3998                         DP_DWN_STRM_PORT_TYPE_MASK;
3999                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4000                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4001                         return connector_status_unknown;
4002         }
4003
4004         /* Anything else is out of spec, warn and ignore */
4005         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4006         return connector_status_disconnected;
4007 }
4008
4009 static enum drm_connector_status
4010 edp_detect(struct intel_dp *intel_dp)
4011 {
4012         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4013         enum drm_connector_status status;
4014
4015         status = intel_panel_detect(dev);
4016         if (status == connector_status_unknown)
4017                 status = connector_status_connected;
4018
4019         return status;
4020 }
4021
4022 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4023                                        struct intel_digital_port *port)
4024 {
4025         u32 bit;
4026
4027         switch (port->port) {
4028         case PORT_A:
4029                 return true;
4030         case PORT_B:
4031                 bit = SDE_PORTB_HOTPLUG;
4032                 break;
4033         case PORT_C:
4034                 bit = SDE_PORTC_HOTPLUG;
4035                 break;
4036         case PORT_D:
4037                 bit = SDE_PORTD_HOTPLUG;
4038                 break;
4039         default:
4040                 MISSING_CASE(port->port);
4041                 return false;
4042         }
4043
4044         return I915_READ(SDEISR) & bit;
4045 }
4046
4047 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4048                                        struct intel_digital_port *port)
4049 {
4050         u32 bit;
4051
4052         switch (port->port) {
4053         case PORT_A:
4054                 return true;
4055         case PORT_B:
4056                 bit = SDE_PORTB_HOTPLUG_CPT;
4057                 break;
4058         case PORT_C:
4059                 bit = SDE_PORTC_HOTPLUG_CPT;
4060                 break;
4061         case PORT_D:
4062                 bit = SDE_PORTD_HOTPLUG_CPT;
4063                 break;
4064         case PORT_E:
4065                 bit = SDE_PORTE_HOTPLUG_SPT;
4066                 break;
4067         default:
4068                 MISSING_CASE(port->port);
4069                 return false;
4070         }
4071
4072         return I915_READ(SDEISR) & bit;
4073 }
4074
4075 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4076                                        struct intel_digital_port *port)
4077 {
4078         u32 bit;
4079
4080         switch (port->port) {
4081         case PORT_B:
4082                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4083                 break;
4084         case PORT_C:
4085                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4086                 break;
4087         case PORT_D:
4088                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4089                 break;
4090         default:
4091                 MISSING_CASE(port->port);
4092                 return false;
4093         }
4094
4095         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4096 }
4097
4098 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4099                                         struct intel_digital_port *port)
4100 {
4101         u32 bit;
4102
4103         switch (port->port) {
4104         case PORT_B:
4105                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4106                 break;
4107         case PORT_C:
4108                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4109                 break;
4110         case PORT_D:
4111                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4112                 break;
4113         default:
4114                 MISSING_CASE(port->port);
4115                 return false;
4116         }
4117
4118         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4119 }
4120
4121 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4122                                        struct intel_digital_port *intel_dig_port)
4123 {
4124         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4125         enum port port;
4126         u32 bit;
4127
4128         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4129         switch (port) {
4130         case PORT_A:
4131                 bit = BXT_DE_PORT_HP_DDIA;
4132                 break;
4133         case PORT_B:
4134                 bit = BXT_DE_PORT_HP_DDIB;
4135                 break;
4136         case PORT_C:
4137                 bit = BXT_DE_PORT_HP_DDIC;
4138                 break;
4139         default:
4140                 MISSING_CASE(port);
4141                 return false;
4142         }
4143
4144         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4145 }
4146
4147 /*
4148  * intel_digital_port_connected - is the specified port connected?
4149  * @dev_priv: i915 private structure
4150  * @port: the port to test
4151  *
4152  * Return %true if @port is connected, %false otherwise.
4153  */
4154 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4155                                          struct intel_digital_port *port)
4156 {
4157         if (HAS_PCH_IBX(dev_priv))
4158                 return ibx_digital_port_connected(dev_priv, port);
4159         else if (HAS_PCH_SPLIT(dev_priv))
4160                 return cpt_digital_port_connected(dev_priv, port);
4161         else if (IS_BROXTON(dev_priv))
4162                 return bxt_digital_port_connected(dev_priv, port);
4163         else if (IS_GM45(dev_priv))
4164                 return gm45_digital_port_connected(dev_priv, port);
4165         else
4166                 return g4x_digital_port_connected(dev_priv, port);
4167 }
4168
4169 static struct edid *
4170 intel_dp_get_edid(struct intel_dp *intel_dp)
4171 {
4172         struct intel_connector *intel_connector = intel_dp->attached_connector;
4173
4174         /* use cached edid if we have one */
4175         if (intel_connector->edid) {
4176                 /* invalid edid */
4177                 if (IS_ERR(intel_connector->edid))
4178                         return NULL;
4179
4180                 return drm_edid_duplicate(intel_connector->edid);
4181         } else
4182                 return drm_get_edid(&intel_connector->base,
4183                                     &intel_dp->aux.ddc);
4184 }
4185
4186 static void
4187 intel_dp_set_edid(struct intel_dp *intel_dp)
4188 {
4189         struct intel_connector *intel_connector = intel_dp->attached_connector;
4190         struct edid *edid;
4191
4192         intel_dp_unset_edid(intel_dp);
4193         edid = intel_dp_get_edid(intel_dp);
4194         intel_connector->detect_edid = edid;
4195
4196         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4197                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4198         else
4199                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4200 }
4201
4202 static void
4203 intel_dp_unset_edid(struct intel_dp *intel_dp)
4204 {
4205         struct intel_connector *intel_connector = intel_dp->attached_connector;
4206
4207         kfree(intel_connector->detect_edid);
4208         intel_connector->detect_edid = NULL;
4209
4210         intel_dp->has_audio = false;
4211 }
4212
4213 static void
4214 intel_dp_long_pulse(struct intel_connector *intel_connector)
4215 {
4216         struct drm_connector *connector = &intel_connector->base;
4217         struct intel_dp *intel_dp = intel_attached_dp(connector);
4218         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4219         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4220         struct drm_device *dev = connector->dev;
4221         enum drm_connector_status status;
4222         enum intel_display_power_domain power_domain;
4223         bool ret;
4224         u8 sink_irq_vector;
4225
4226         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4227         intel_display_power_get(to_i915(dev), power_domain);
4228
4229         /* Can't disconnect eDP, but you can close the lid... */
4230         if (is_edp(intel_dp))
4231                 status = edp_detect(intel_dp);
4232         else if (intel_digital_port_connected(to_i915(dev),
4233                                               dp_to_dig_port(intel_dp)))
4234                 status = intel_dp_detect_dpcd(intel_dp);
4235         else
4236                 status = connector_status_disconnected;
4237
4238         if (status != connector_status_connected) {
4239                 intel_dp->compliance_test_active = 0;
4240                 intel_dp->compliance_test_type = 0;
4241                 intel_dp->compliance_test_data = 0;
4242
4243                 if (intel_dp->is_mst) {
4244                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4245                                       intel_dp->is_mst,
4246                                       intel_dp->mst_mgr.mst_state);
4247                         intel_dp->is_mst = false;
4248                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4249                                                         intel_dp->is_mst);
4250                 }
4251
4252                 goto out;
4253         }
4254
4255         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4256                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4257
4258         intel_dp_probe_oui(intel_dp);
4259
4260         ret = intel_dp_probe_mst(intel_dp);
4261         if (ret) {
4262                 /*
4263                  * If we are in MST mode then this connector
4264                  * won't appear connected or have anything
4265                  * with EDID on it
4266                  */
4267                 status = connector_status_disconnected;
4268                 goto out;
4269         } else if (connector->status == connector_status_connected) {
4270                 /*
4271                  * If display was connected already and is still connected
4272                  * check links status, there has been known issues of
4273                  * link loss triggerring long pulse!!!!
4274                  */
4275                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4276                 intel_dp_check_link_status(intel_dp);
4277                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4278                 goto out;
4279         }
4280
4281         /*
4282          * Clearing NACK and defer counts to get their exact values
4283          * while reading EDID which are required by Compliance tests
4284          * 4.2.2.4 and 4.2.2.5
4285          */
4286         intel_dp->aux.i2c_nack_count = 0;
4287         intel_dp->aux.i2c_defer_count = 0;
4288
4289         intel_dp_set_edid(intel_dp);
4290
4291         status = connector_status_connected;
4292         intel_dp->detect_done = true;
4293
4294         /* Try to read the source of the interrupt */
4295         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4296             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4297                 /* Clear interrupt source */
4298                 drm_dp_dpcd_writeb(&intel_dp->aux,
4299                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4300                                    sink_irq_vector);
4301
4302                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4303                         intel_dp_handle_test_request(intel_dp);
4304                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4305                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4306         }
4307
4308 out:
4309         if ((status != connector_status_connected) &&
4310             (intel_dp->is_mst == false))
4311                 intel_dp_unset_edid(intel_dp);
4312
4313         intel_display_power_put(to_i915(dev), power_domain);
4314         return;
4315 }
4316
4317 static enum drm_connector_status
4318 intel_dp_detect(struct drm_connector *connector, bool force)
4319 {
4320         struct intel_dp *intel_dp = intel_attached_dp(connector);
4321         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4322         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4323         struct intel_connector *intel_connector = to_intel_connector(connector);
4324
4325         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4326                       connector->base.id, connector->name);
4327
4328         if (intel_dp->is_mst) {
4329                 /* MST devices are disconnected from a monitor POV */
4330                 intel_dp_unset_edid(intel_dp);
4331                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4332                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4333                 return connector_status_disconnected;
4334         }
4335
4336         /* If full detect is not performed yet, do a full detect */
4337         if (!intel_dp->detect_done)
4338                 intel_dp_long_pulse(intel_dp->attached_connector);
4339
4340         intel_dp->detect_done = false;
4341
4342         if (intel_connector->detect_edid)
4343                 return connector_status_connected;
4344         else
4345                 return connector_status_disconnected;
4346 }
4347
4348 static void
4349 intel_dp_force(struct drm_connector *connector)
4350 {
4351         struct intel_dp *intel_dp = intel_attached_dp(connector);
4352         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4353         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4354         enum intel_display_power_domain power_domain;
4355
4356         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4357                       connector->base.id, connector->name);
4358         intel_dp_unset_edid(intel_dp);
4359
4360         if (connector->status != connector_status_connected)
4361                 return;
4362
4363         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4364         intel_display_power_get(dev_priv, power_domain);
4365
4366         intel_dp_set_edid(intel_dp);
4367
4368         intel_display_power_put(dev_priv, power_domain);
4369
4370         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4371                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4372 }
4373
4374 static int intel_dp_get_modes(struct drm_connector *connector)
4375 {
4376         struct intel_connector *intel_connector = to_intel_connector(connector);
4377         struct edid *edid;
4378
4379         edid = intel_connector->detect_edid;
4380         if (edid) {
4381                 int ret = intel_connector_update_modes(connector, edid);
4382                 if (ret)
4383                         return ret;
4384         }
4385
4386         /* if eDP has no EDID, fall back to fixed mode */
4387         if (is_edp(intel_attached_dp(connector)) &&
4388             intel_connector->panel.fixed_mode) {
4389                 struct drm_display_mode *mode;
4390
4391                 mode = drm_mode_duplicate(connector->dev,
4392                                           intel_connector->panel.fixed_mode);
4393                 if (mode) {
4394                         drm_mode_probed_add(connector, mode);
4395                         return 1;
4396                 }
4397         }
4398
4399         return 0;
4400 }
4401
4402 static bool
4403 intel_dp_detect_audio(struct drm_connector *connector)
4404 {
4405         bool has_audio = false;
4406         struct edid *edid;
4407
4408         edid = to_intel_connector(connector)->detect_edid;
4409         if (edid)
4410                 has_audio = drm_detect_monitor_audio(edid);
4411
4412         return has_audio;
4413 }
4414
4415 static int
4416 intel_dp_set_property(struct drm_connector *connector,
4417                       struct drm_property *property,
4418                       uint64_t val)
4419 {
4420         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4421         struct intel_connector *intel_connector = to_intel_connector(connector);
4422         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4423         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4424         int ret;
4425
4426         ret = drm_object_property_set_value(&connector->base, property, val);
4427         if (ret)
4428                 return ret;
4429
4430         if (property == dev_priv->force_audio_property) {
4431                 int i = val;
4432                 bool has_audio;
4433
4434                 if (i == intel_dp->force_audio)
4435                         return 0;
4436
4437                 intel_dp->force_audio = i;
4438
4439                 if (i == HDMI_AUDIO_AUTO)
4440                         has_audio = intel_dp_detect_audio(connector);
4441                 else
4442                         has_audio = (i == HDMI_AUDIO_ON);
4443
4444                 if (has_audio == intel_dp->has_audio)
4445                         return 0;
4446
4447                 intel_dp->has_audio = has_audio;
4448                 goto done;
4449         }
4450
4451         if (property == dev_priv->broadcast_rgb_property) {
4452                 bool old_auto = intel_dp->color_range_auto;
4453                 bool old_range = intel_dp->limited_color_range;
4454
4455                 switch (val) {
4456                 case INTEL_BROADCAST_RGB_AUTO:
4457                         intel_dp->color_range_auto = true;
4458                         break;
4459                 case INTEL_BROADCAST_RGB_FULL:
4460                         intel_dp->color_range_auto = false;
4461                         intel_dp->limited_color_range = false;
4462                         break;
4463                 case INTEL_BROADCAST_RGB_LIMITED:
4464                         intel_dp->color_range_auto = false;
4465                         intel_dp->limited_color_range = true;
4466                         break;
4467                 default:
4468                         return -EINVAL;
4469                 }
4470
4471                 if (old_auto == intel_dp->color_range_auto &&
4472                     old_range == intel_dp->limited_color_range)
4473                         return 0;
4474
4475                 goto done;
4476         }
4477
4478         if (is_edp(intel_dp) &&
4479             property == connector->dev->mode_config.scaling_mode_property) {
4480                 if (val == DRM_MODE_SCALE_NONE) {
4481                         DRM_DEBUG_KMS("no scaling not supported\n");
4482                         return -EINVAL;
4483                 }
4484                 if (HAS_GMCH_DISPLAY(dev_priv) &&
4485                     val == DRM_MODE_SCALE_CENTER) {
4486                         DRM_DEBUG_KMS("centering not supported\n");
4487                         return -EINVAL;
4488                 }
4489
4490                 if (intel_connector->panel.fitting_mode == val) {
4491                         /* the eDP scaling property is not changed */
4492                         return 0;
4493                 }
4494                 intel_connector->panel.fitting_mode = val;
4495
4496                 goto done;
4497         }
4498
4499         return -EINVAL;
4500
4501 done:
4502         if (intel_encoder->base.crtc)
4503                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4504
4505         return 0;
4506 }
4507
4508 static int
4509 intel_dp_connector_register(struct drm_connector *connector)
4510 {
4511         struct intel_dp *intel_dp = intel_attached_dp(connector);
4512         int ret;
4513
4514         ret = intel_connector_register(connector);
4515         if (ret)
4516                 return ret;
4517
4518         i915_debugfs_connector_add(connector);
4519
4520         DRM_DEBUG_KMS("registering %s bus for %s\n",
4521                       intel_dp->aux.name, connector->kdev->kobj.name);
4522
4523         intel_dp->aux.dev = connector->kdev;
4524         return drm_dp_aux_register(&intel_dp->aux);
4525 }
4526
4527 static void
4528 intel_dp_connector_unregister(struct drm_connector *connector)
4529 {
4530         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4531         intel_connector_unregister(connector);
4532 }
4533
4534 static void
4535 intel_dp_connector_destroy(struct drm_connector *connector)
4536 {
4537         struct intel_connector *intel_connector = to_intel_connector(connector);
4538
4539         kfree(intel_connector->detect_edid);
4540
4541         if (!IS_ERR_OR_NULL(intel_connector->edid))
4542                 kfree(intel_connector->edid);
4543
4544         /* Can't call is_edp() since the encoder may have been destroyed
4545          * already. */
4546         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4547                 intel_panel_fini(&intel_connector->panel);
4548
4549         drm_connector_cleanup(connector);
4550         kfree(connector);
4551 }
4552
4553 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4554 {
4555         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4556         struct intel_dp *intel_dp = &intel_dig_port->dp;
4557
4558         intel_dp_mst_encoder_cleanup(intel_dig_port);
4559         if (is_edp(intel_dp)) {
4560                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4561                 /*
4562                  * vdd might still be enabled do to the delayed vdd off.
4563                  * Make sure vdd is actually turned off here.
4564                  */
4565                 pps_lock(intel_dp);
4566                 edp_panel_vdd_off_sync(intel_dp);
4567                 pps_unlock(intel_dp);
4568
4569                 if (intel_dp->edp_notifier.notifier_call) {
4570                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4571                         intel_dp->edp_notifier.notifier_call = NULL;
4572                 }
4573         }
4574
4575         intel_dp_aux_fini(intel_dp);
4576
4577         drm_encoder_cleanup(encoder);
4578         kfree(intel_dig_port);
4579 }
4580
4581 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4582 {
4583         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4584
4585         if (!is_edp(intel_dp))
4586                 return;
4587
4588         /*
4589          * vdd might still be enabled do to the delayed vdd off.
4590          * Make sure vdd is actually turned off here.
4591          */
4592         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4593         pps_lock(intel_dp);
4594         edp_panel_vdd_off_sync(intel_dp);
4595         pps_unlock(intel_dp);
4596 }
4597
4598 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4599 {
4600         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4601         struct drm_device *dev = intel_dig_port->base.base.dev;
4602         struct drm_i915_private *dev_priv = to_i915(dev);
4603         enum intel_display_power_domain power_domain;
4604
4605         lockdep_assert_held(&dev_priv->pps_mutex);
4606
4607         if (!edp_have_panel_vdd(intel_dp))
4608                 return;
4609
4610         /*
4611          * The VDD bit needs a power domain reference, so if the bit is
4612          * already enabled when we boot or resume, grab this reference and
4613          * schedule a vdd off, so we don't hold on to the reference
4614          * indefinitely.
4615          */
4616         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4617         power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4618         intel_display_power_get(dev_priv, power_domain);
4619
4620         edp_panel_vdd_schedule_off(intel_dp);
4621 }
4622
4623 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4624 {
4625         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4626         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4627
4628         if (!HAS_DDI(dev_priv))
4629                 intel_dp->DP = I915_READ(intel_dp->output_reg);
4630
4631         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4632                 return;
4633
4634         pps_lock(intel_dp);
4635
4636         /*
4637          * Read out the current power sequencer assignment,
4638          * in case the BIOS did something with it.
4639          */
4640         if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
4641                 vlv_initial_power_sequencer_setup(intel_dp);
4642
4643         intel_edp_panel_vdd_sanitize(intel_dp);
4644
4645         pps_unlock(intel_dp);
4646 }
4647
4648 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4649         .dpms = drm_atomic_helper_connector_dpms,
4650         .detect = intel_dp_detect,
4651         .force = intel_dp_force,
4652         .fill_modes = drm_helper_probe_single_connector_modes,
4653         .set_property = intel_dp_set_property,
4654         .atomic_get_property = intel_connector_atomic_get_property,
4655         .late_register = intel_dp_connector_register,
4656         .early_unregister = intel_dp_connector_unregister,
4657         .destroy = intel_dp_connector_destroy,
4658         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4659         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4660 };
4661
4662 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4663         .get_modes = intel_dp_get_modes,
4664         .mode_valid = intel_dp_mode_valid,
4665 };
4666
4667 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4668         .reset = intel_dp_encoder_reset,
4669         .destroy = intel_dp_encoder_destroy,
4670 };
4671
4672 enum irqreturn
4673 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4674 {
4675         struct intel_dp *intel_dp = &intel_dig_port->dp;
4676         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4677         struct drm_device *dev = intel_dig_port->base.base.dev;
4678         struct drm_i915_private *dev_priv = to_i915(dev);
4679         enum intel_display_power_domain power_domain;
4680         enum irqreturn ret = IRQ_NONE;
4681
4682         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4683             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4684                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4685
4686         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4687                 /*
4688                  * vdd off can generate a long pulse on eDP which
4689                  * would require vdd on to handle it, and thus we
4690                  * would end up in an endless cycle of
4691                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4692                  */
4693                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4694                               port_name(intel_dig_port->port));
4695                 return IRQ_HANDLED;
4696         }
4697
4698         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4699                       port_name(intel_dig_port->port),
4700                       long_hpd ? "long" : "short");
4701
4702         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4703         intel_display_power_get(dev_priv, power_domain);
4704
4705         if (long_hpd) {
4706                 intel_dp_long_pulse(intel_dp->attached_connector);
4707                 if (intel_dp->is_mst)
4708                         ret = IRQ_HANDLED;
4709                 goto put_power;
4710
4711         } else {
4712                 if (intel_dp->is_mst) {
4713                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4714                                 /*
4715                                  * If we were in MST mode, and device is not
4716                                  * there, get out of MST mode
4717                                  */
4718                                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4719                                               intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4720                                 intel_dp->is_mst = false;
4721                                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4722                                                                 intel_dp->is_mst);
4723                                 goto put_power;
4724                         }
4725                 }
4726
4727                 if (!intel_dp->is_mst) {
4728                         if (!intel_dp_short_pulse(intel_dp)) {
4729                                 intel_dp_long_pulse(intel_dp->attached_connector);
4730                                 goto put_power;
4731                         }
4732                 }
4733         }
4734
4735         ret = IRQ_HANDLED;
4736
4737 put_power:
4738         intel_display_power_put(dev_priv, power_domain);
4739
4740         return ret;
4741 }
4742
4743 /* check the VBT to see whether the eDP is on another port */
4744 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4745 {
4746         struct drm_i915_private *dev_priv = to_i915(dev);
4747
4748         /*
4749          * eDP not supported on g4x. so bail out early just
4750          * for a bit extra safety in case the VBT is bonkers.
4751          */
4752         if (INTEL_INFO(dev)->gen < 5)
4753                 return false;
4754
4755         if (port == PORT_A)
4756                 return true;
4757
4758         return intel_bios_is_port_edp(dev_priv, port);
4759 }
4760
4761 void
4762 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4763 {
4764         struct intel_connector *intel_connector = to_intel_connector(connector);
4765
4766         intel_attach_force_audio_property(connector);
4767         intel_attach_broadcast_rgb_property(connector);
4768         intel_dp->color_range_auto = true;
4769
4770         if (is_edp(intel_dp)) {
4771                 drm_mode_create_scaling_mode_property(connector->dev);
4772                 drm_object_attach_property(
4773                         &connector->base,
4774                         connector->dev->mode_config.scaling_mode_property,
4775                         DRM_MODE_SCALE_ASPECT);
4776                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4777         }
4778 }
4779
4780 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4781 {
4782         intel_dp->panel_power_off_time = ktime_get_boottime();
4783         intel_dp->last_power_on = jiffies;
4784         intel_dp->last_backlight_off = jiffies;
4785 }
4786
4787 static void
4788 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4789                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
4790 {
4791         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4792         struct pps_registers regs;
4793
4794         intel_pps_get_registers(dev_priv, intel_dp, &regs);
4795
4796         /* Workaround: Need to write PP_CONTROL with the unlock key as
4797          * the very first thing. */
4798         pp_ctl = ironlake_get_pp_control(intel_dp);
4799
4800         pp_on = I915_READ(regs.pp_on);
4801         pp_off = I915_READ(regs.pp_off);
4802         if (!IS_BROXTON(dev_priv)) {
4803                 I915_WRITE(regs.pp_ctrl, pp_ctl);
4804                 pp_div = I915_READ(regs.pp_div);
4805         }
4806
4807         /* Pull timing values out of registers */
4808         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4809                      PANEL_POWER_UP_DELAY_SHIFT;
4810
4811         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4812                   PANEL_LIGHT_ON_DELAY_SHIFT;
4813
4814         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4815                   PANEL_LIGHT_OFF_DELAY_SHIFT;
4816
4817         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4818                    PANEL_POWER_DOWN_DELAY_SHIFT;
4819
4820         if (IS_BROXTON(dev_priv)) {
4821                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4822                         BXT_POWER_CYCLE_DELAY_SHIFT;
4823                 if (tmp > 0)
4824                         seq->t11_t12 = (tmp - 1) * 1000;
4825                 else
4826                         seq->t11_t12 = 0;
4827         } else {
4828                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4829                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4830         }
4831 }
4832
4833 static void
4834 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4835 {
4836         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4837                       state_name,
4838                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4839 }
4840
4841 static void
4842 intel_pps_verify_state(struct drm_i915_private *dev_priv,
4843                        struct intel_dp *intel_dp)
4844 {
4845         struct edp_power_seq hw;
4846         struct edp_power_seq *sw = &intel_dp->pps_delays;
4847
4848         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4849
4850         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4851             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4852                 DRM_ERROR("PPS state mismatch\n");
4853                 intel_pps_dump_state("sw", sw);
4854                 intel_pps_dump_state("hw", &hw);
4855         }
4856 }
4857
4858 static void
4859 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4860                                     struct intel_dp *intel_dp)
4861 {
4862         struct drm_i915_private *dev_priv = to_i915(dev);
4863         struct edp_power_seq cur, vbt, spec,
4864                 *final = &intel_dp->pps_delays;
4865
4866         lockdep_assert_held(&dev_priv->pps_mutex);
4867
4868         /* already initialized? */
4869         if (final->t11_t12 != 0)
4870                 return;
4871
4872         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
4873
4874         intel_pps_dump_state("cur", &cur);
4875
4876         vbt = dev_priv->vbt.edp.pps;
4877
4878         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4879          * our hw here, which are all in 100usec. */
4880         spec.t1_t3 = 210 * 10;
4881         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4882         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4883         spec.t10 = 500 * 10;
4884         /* This one is special and actually in units of 100ms, but zero
4885          * based in the hw (so we need to add 100 ms). But the sw vbt
4886          * table multiplies it with 1000 to make it in units of 100usec,
4887          * too. */
4888         spec.t11_t12 = (510 + 100) * 10;
4889
4890         intel_pps_dump_state("vbt", &vbt);
4891
4892         /* Use the max of the register settings and vbt. If both are
4893          * unset, fall back to the spec limits. */
4894 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
4895                                        spec.field : \
4896                                        max(cur.field, vbt.field))
4897         assign_final(t1_t3);
4898         assign_final(t8);
4899         assign_final(t9);
4900         assign_final(t10);
4901         assign_final(t11_t12);
4902 #undef assign_final
4903
4904 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
4905         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4906         intel_dp->backlight_on_delay = get_delay(t8);
4907         intel_dp->backlight_off_delay = get_delay(t9);
4908         intel_dp->panel_power_down_delay = get_delay(t10);
4909         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4910 #undef get_delay
4911
4912         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4913                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4914                       intel_dp->panel_power_cycle_delay);
4915
4916         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4917                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4918
4919         /*
4920          * We override the HW backlight delays to 1 because we do manual waits
4921          * on them. For T8, even BSpec recommends doing it. For T9, if we
4922          * don't do this, we'll end up waiting for the backlight off delay
4923          * twice: once when we do the manual sleep, and once when we disable
4924          * the panel and wait for the PP_STATUS bit to become zero.
4925          */
4926         final->t8 = 1;
4927         final->t9 = 1;
4928 }
4929
4930 static void
4931 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4932                                               struct intel_dp *intel_dp)
4933 {
4934         struct drm_i915_private *dev_priv = to_i915(dev);
4935         u32 pp_on, pp_off, pp_div, port_sel = 0;
4936         int div = dev_priv->rawclk_freq / 1000;
4937         struct pps_registers regs;
4938         enum port port = dp_to_dig_port(intel_dp)->port;
4939         const struct edp_power_seq *seq = &intel_dp->pps_delays;
4940
4941         lockdep_assert_held(&dev_priv->pps_mutex);
4942
4943         intel_pps_get_registers(dev_priv, intel_dp, &regs);
4944
4945         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4946                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
4947         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4948                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4949         /* Compute the divisor for the pp clock, simply match the Bspec
4950          * formula. */
4951         if (IS_BROXTON(dev)) {
4952                 pp_div = I915_READ(regs.pp_ctrl);
4953                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
4954                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
4955                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
4956         } else {
4957                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4958                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4959                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4960         }
4961
4962         /* Haswell doesn't have any port selection bits for the panel
4963          * power sequencer any more. */
4964         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4965                 port_sel = PANEL_PORT_SELECT_VLV(port);
4966         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4967                 if (port == PORT_A)
4968                         port_sel = PANEL_PORT_SELECT_DPA;
4969                 else
4970                         port_sel = PANEL_PORT_SELECT_DPD;
4971         }
4972
4973         pp_on |= port_sel;
4974
4975         I915_WRITE(regs.pp_on, pp_on);
4976         I915_WRITE(regs.pp_off, pp_off);
4977         if (IS_BROXTON(dev))
4978                 I915_WRITE(regs.pp_ctrl, pp_div);
4979         else
4980                 I915_WRITE(regs.pp_div, pp_div);
4981
4982         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4983                       I915_READ(regs.pp_on),
4984                       I915_READ(regs.pp_off),
4985                       IS_BROXTON(dev) ?
4986                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
4987                       I915_READ(regs.pp_div));
4988 }
4989
4990 /**
4991  * intel_dp_set_drrs_state - program registers for RR switch to take effect
4992  * @dev: DRM device
4993  * @refresh_rate: RR to be programmed
4994  *
4995  * This function gets called when refresh rate (RR) has to be changed from
4996  * one frequency to another. Switches can be between high and low RR
4997  * supported by the panel or to any other RR based on media playback (in
4998  * this case, RR value needs to be passed from user space).
4999  *
5000  * The caller of this function needs to take a lock on dev_priv->drrs.
5001  */
5002 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5003 {
5004         struct drm_i915_private *dev_priv = to_i915(dev);
5005         struct intel_encoder *encoder;
5006         struct intel_digital_port *dig_port = NULL;
5007         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5008         struct intel_crtc_state *config = NULL;
5009         struct intel_crtc *intel_crtc = NULL;
5010         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5011
5012         if (refresh_rate <= 0) {
5013                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5014                 return;
5015         }
5016
5017         if (intel_dp == NULL) {
5018                 DRM_DEBUG_KMS("DRRS not supported.\n");
5019                 return;
5020         }
5021
5022         /*
5023          * FIXME: This needs proper synchronization with psr state for some
5024          * platforms that cannot have PSR and DRRS enabled at the same time.
5025          */
5026
5027         dig_port = dp_to_dig_port(intel_dp);
5028         encoder = &dig_port->base;
5029         intel_crtc = to_intel_crtc(encoder->base.crtc);
5030
5031         if (!intel_crtc) {
5032                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5033                 return;
5034         }
5035
5036         config = intel_crtc->config;
5037
5038         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5039                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5040                 return;
5041         }
5042
5043         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5044                         refresh_rate)
5045                 index = DRRS_LOW_RR;
5046
5047         if (index == dev_priv->drrs.refresh_rate_type) {
5048                 DRM_DEBUG_KMS(
5049                         "DRRS requested for previously set RR...ignoring\n");
5050                 return;
5051         }
5052
5053         if (!intel_crtc->active) {
5054                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5055                 return;
5056         }
5057
5058         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5059                 switch (index) {
5060                 case DRRS_HIGH_RR:
5061                         intel_dp_set_m_n(intel_crtc, M1_N1);
5062                         break;
5063                 case DRRS_LOW_RR:
5064                         intel_dp_set_m_n(intel_crtc, M2_N2);
5065                         break;
5066                 case DRRS_MAX_RR:
5067                 default:
5068                         DRM_ERROR("Unsupported refreshrate type\n");
5069                 }
5070         } else if (INTEL_INFO(dev)->gen > 6) {
5071                 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5072                 u32 val;
5073
5074                 val = I915_READ(reg);
5075                 if (index > DRRS_HIGH_RR) {
5076                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5077                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5078                         else
5079                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5080                 } else {
5081                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5082                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5083                         else
5084                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5085                 }
5086                 I915_WRITE(reg, val);
5087         }
5088
5089         dev_priv->drrs.refresh_rate_type = index;
5090
5091         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5092 }
5093
5094 /**
5095  * intel_edp_drrs_enable - init drrs struct if supported
5096  * @intel_dp: DP struct
5097  *
5098  * Initializes frontbuffer_bits and drrs.dp
5099  */
5100 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5101 {
5102         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5103         struct drm_i915_private *dev_priv = to_i915(dev);
5104         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5105         struct drm_crtc *crtc = dig_port->base.base.crtc;
5106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5107
5108         if (!intel_crtc->config->has_drrs) {
5109                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5110                 return;
5111         }
5112
5113         mutex_lock(&dev_priv->drrs.mutex);
5114         if (WARN_ON(dev_priv->drrs.dp)) {
5115                 DRM_ERROR("DRRS already enabled\n");
5116                 goto unlock;
5117         }
5118
5119         dev_priv->drrs.busy_frontbuffer_bits = 0;
5120
5121         dev_priv->drrs.dp = intel_dp;
5122
5123 unlock:
5124         mutex_unlock(&dev_priv->drrs.mutex);
5125 }
5126
5127 /**
5128  * intel_edp_drrs_disable - Disable DRRS
5129  * @intel_dp: DP struct
5130  *
5131  */
5132 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5133 {
5134         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5135         struct drm_i915_private *dev_priv = to_i915(dev);
5136         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5137         struct drm_crtc *crtc = dig_port->base.base.crtc;
5138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5139
5140         if (!intel_crtc->config->has_drrs)
5141                 return;
5142
5143         mutex_lock(&dev_priv->drrs.mutex);
5144         if (!dev_priv->drrs.dp) {
5145                 mutex_unlock(&dev_priv->drrs.mutex);
5146                 return;
5147         }
5148
5149         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5150                 intel_dp_set_drrs_state(&dev_priv->drm,
5151                                         intel_dp->attached_connector->panel.
5152                                         fixed_mode->vrefresh);
5153
5154         dev_priv->drrs.dp = NULL;
5155         mutex_unlock(&dev_priv->drrs.mutex);
5156
5157         cancel_delayed_work_sync(&dev_priv->drrs.work);
5158 }
5159
5160 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5161 {
5162         struct drm_i915_private *dev_priv =
5163                 container_of(work, typeof(*dev_priv), drrs.work.work);
5164         struct intel_dp *intel_dp;
5165
5166         mutex_lock(&dev_priv->drrs.mutex);
5167
5168         intel_dp = dev_priv->drrs.dp;
5169
5170         if (!intel_dp)
5171                 goto unlock;
5172
5173         /*
5174          * The delayed work can race with an invalidate hence we need to
5175          * recheck.
5176          */
5177
5178         if (dev_priv->drrs.busy_frontbuffer_bits)
5179                 goto unlock;
5180
5181         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5182                 intel_dp_set_drrs_state(&dev_priv->drm,
5183                                         intel_dp->attached_connector->panel.
5184                                         downclock_mode->vrefresh);
5185
5186 unlock:
5187         mutex_unlock(&dev_priv->drrs.mutex);
5188 }
5189
5190 /**
5191  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5192  * @dev: DRM device
5193  * @frontbuffer_bits: frontbuffer plane tracking bits
5194  *
5195  * This function gets called everytime rendering on the given planes start.
5196  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5197  *
5198  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5199  */
5200 void intel_edp_drrs_invalidate(struct drm_device *dev,
5201                 unsigned frontbuffer_bits)
5202 {
5203         struct drm_i915_private *dev_priv = to_i915(dev);
5204         struct drm_crtc *crtc;
5205         enum pipe pipe;
5206
5207         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5208                 return;
5209
5210         cancel_delayed_work(&dev_priv->drrs.work);
5211
5212         mutex_lock(&dev_priv->drrs.mutex);
5213         if (!dev_priv->drrs.dp) {
5214                 mutex_unlock(&dev_priv->drrs.mutex);
5215                 return;
5216         }
5217
5218         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5219         pipe = to_intel_crtc(crtc)->pipe;
5220
5221         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5222         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5223
5224         /* invalidate means busy screen hence upclock */
5225         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5226                 intel_dp_set_drrs_state(&dev_priv->drm,
5227                                         dev_priv->drrs.dp->attached_connector->panel.
5228                                         fixed_mode->vrefresh);
5229
5230         mutex_unlock(&dev_priv->drrs.mutex);
5231 }
5232
5233 /**
5234  * intel_edp_drrs_flush - Restart Idleness DRRS
5235  * @dev: DRM device
5236  * @frontbuffer_bits: frontbuffer plane tracking bits
5237  *
5238  * This function gets called every time rendering on the given planes has
5239  * completed or flip on a crtc is completed. So DRRS should be upclocked
5240  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5241  * if no other planes are dirty.
5242  *
5243  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5244  */
5245 void intel_edp_drrs_flush(struct drm_device *dev,
5246                 unsigned frontbuffer_bits)
5247 {
5248         struct drm_i915_private *dev_priv = to_i915(dev);
5249         struct drm_crtc *crtc;
5250         enum pipe pipe;
5251
5252         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5253                 return;
5254
5255         cancel_delayed_work(&dev_priv->drrs.work);
5256
5257         mutex_lock(&dev_priv->drrs.mutex);
5258         if (!dev_priv->drrs.dp) {
5259                 mutex_unlock(&dev_priv->drrs.mutex);
5260                 return;
5261         }
5262
5263         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5264         pipe = to_intel_crtc(crtc)->pipe;
5265
5266         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5267         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5268
5269         /* flush means busy screen hence upclock */
5270         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5271                 intel_dp_set_drrs_state(&dev_priv->drm,
5272                                         dev_priv->drrs.dp->attached_connector->panel.
5273                                         fixed_mode->vrefresh);
5274
5275         /*
5276          * flush also means no more activity hence schedule downclock, if all
5277          * other fbs are quiescent too
5278          */
5279         if (!dev_priv->drrs.busy_frontbuffer_bits)
5280                 schedule_delayed_work(&dev_priv->drrs.work,
5281                                 msecs_to_jiffies(1000));
5282         mutex_unlock(&dev_priv->drrs.mutex);
5283 }
5284
5285 /**
5286  * DOC: Display Refresh Rate Switching (DRRS)
5287  *
5288  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5289  * which enables swtching between low and high refresh rates,
5290  * dynamically, based on the usage scenario. This feature is applicable
5291  * for internal panels.
5292  *
5293  * Indication that the panel supports DRRS is given by the panel EDID, which
5294  * would list multiple refresh rates for one resolution.
5295  *
5296  * DRRS is of 2 types - static and seamless.
5297  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5298  * (may appear as a blink on screen) and is used in dock-undock scenario.
5299  * Seamless DRRS involves changing RR without any visual effect to the user
5300  * and can be used during normal system usage. This is done by programming
5301  * certain registers.
5302  *
5303  * Support for static/seamless DRRS may be indicated in the VBT based on
5304  * inputs from the panel spec.
5305  *
5306  * DRRS saves power by switching to low RR based on usage scenarios.
5307  *
5308  * The implementation is based on frontbuffer tracking implementation.  When
5309  * there is a disturbance on the screen triggered by user activity or a periodic
5310  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5311  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5312  * made.
5313  *
5314  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5315  * and intel_edp_drrs_flush() are called.
5316  *
5317  * DRRS can be further extended to support other internal panels and also
5318  * the scenario of video playback wherein RR is set based on the rate
5319  * requested by userspace.
5320  */
5321
5322 /**
5323  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5324  * @intel_connector: eDP connector
5325  * @fixed_mode: preferred mode of panel
5326  *
5327  * This function is  called only once at driver load to initialize basic
5328  * DRRS stuff.
5329  *
5330  * Returns:
5331  * Downclock mode if panel supports it, else return NULL.
5332  * DRRS support is determined by the presence of downclock mode (apart
5333  * from VBT setting).
5334  */
5335 static struct drm_display_mode *
5336 intel_dp_drrs_init(struct intel_connector *intel_connector,
5337                 struct drm_display_mode *fixed_mode)
5338 {
5339         struct drm_connector *connector = &intel_connector->base;
5340         struct drm_device *dev = connector->dev;
5341         struct drm_i915_private *dev_priv = to_i915(dev);
5342         struct drm_display_mode *downclock_mode = NULL;
5343
5344         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5345         mutex_init(&dev_priv->drrs.mutex);
5346
5347         if (INTEL_INFO(dev)->gen <= 6) {
5348                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5349                 return NULL;
5350         }
5351
5352         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5353                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5354                 return NULL;
5355         }
5356
5357         downclock_mode = intel_find_panel_downclock
5358                                         (dev, fixed_mode, connector);
5359
5360         if (!downclock_mode) {
5361                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5362                 return NULL;
5363         }
5364
5365         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5366
5367         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5368         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5369         return downclock_mode;
5370 }
5371
5372 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5373                                      struct intel_connector *intel_connector)
5374 {
5375         struct drm_connector *connector = &intel_connector->base;
5376         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5377         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5378         struct drm_device *dev = intel_encoder->base.dev;
5379         struct drm_i915_private *dev_priv = to_i915(dev);
5380         struct drm_display_mode *fixed_mode = NULL;
5381         struct drm_display_mode *downclock_mode = NULL;
5382         bool has_dpcd;
5383         struct drm_display_mode *scan;
5384         struct edid *edid;
5385         enum pipe pipe = INVALID_PIPE;
5386
5387         if (!is_edp(intel_dp))
5388                 return true;
5389
5390         /*
5391          * On IBX/CPT we may get here with LVDS already registered. Since the
5392          * driver uses the only internal power sequencer available for both
5393          * eDP and LVDS bail out early in this case to prevent interfering
5394          * with an already powered-on LVDS power sequencer.
5395          */
5396         if (intel_get_lvds_encoder(dev)) {
5397                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5398                 DRM_INFO("LVDS was detected, not registering eDP\n");
5399
5400                 return false;
5401         }
5402
5403         pps_lock(intel_dp);
5404
5405         intel_dp_init_panel_power_timestamps(intel_dp);
5406
5407         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5408                 vlv_initial_power_sequencer_setup(intel_dp);
5409         } else {
5410                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5411                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5412         }
5413
5414         intel_edp_panel_vdd_sanitize(intel_dp);
5415
5416         pps_unlock(intel_dp);
5417
5418         /* Cache DPCD and EDID for edp. */
5419         has_dpcd = intel_dp_get_dpcd(intel_dp);
5420
5421         if (has_dpcd) {
5422                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5423                         dev_priv->no_aux_handshake =
5424                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5425                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5426         } else {
5427                 /* if this fails, presume the device is a ghost */
5428                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5429                 goto out_vdd_off;
5430         }
5431
5432         mutex_lock(&dev->mode_config.mutex);
5433         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5434         if (edid) {
5435                 if (drm_add_edid_modes(connector, edid)) {
5436                         drm_mode_connector_update_edid_property(connector,
5437                                                                 edid);
5438                         drm_edid_to_eld(connector, edid);
5439                 } else {
5440                         kfree(edid);
5441                         edid = ERR_PTR(-EINVAL);
5442                 }
5443         } else {
5444                 edid = ERR_PTR(-ENOENT);
5445         }
5446         intel_connector->edid = edid;
5447
5448         /* prefer fixed mode from EDID if available */
5449         list_for_each_entry(scan, &connector->probed_modes, head) {
5450                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5451                         fixed_mode = drm_mode_duplicate(dev, scan);
5452                         downclock_mode = intel_dp_drrs_init(
5453                                                 intel_connector, fixed_mode);
5454                         break;
5455                 }
5456         }
5457
5458         /* fallback to VBT if available for eDP */
5459         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5460                 fixed_mode = drm_mode_duplicate(dev,
5461                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5462                 if (fixed_mode) {
5463                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5464                         connector->display_info.width_mm = fixed_mode->width_mm;
5465                         connector->display_info.height_mm = fixed_mode->height_mm;
5466                 }
5467         }
5468         mutex_unlock(&dev->mode_config.mutex);
5469
5470         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5471                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5472                 register_reboot_notifier(&intel_dp->edp_notifier);
5473
5474                 /*
5475                  * Figure out the current pipe for the initial backlight setup.
5476                  * If the current pipe isn't valid, try the PPS pipe, and if that
5477                  * fails just assume pipe A.
5478                  */
5479                 if (IS_CHERRYVIEW(dev))
5480                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5481                 else
5482                         pipe = PORT_TO_PIPE(intel_dp->DP);
5483
5484                 if (pipe != PIPE_A && pipe != PIPE_B)
5485                         pipe = intel_dp->pps_pipe;
5486
5487                 if (pipe != PIPE_A && pipe != PIPE_B)
5488                         pipe = PIPE_A;
5489
5490                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5491                               pipe_name(pipe));
5492         }
5493
5494         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5495         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5496         intel_panel_setup_backlight(connector, pipe);
5497
5498         return true;
5499
5500 out_vdd_off:
5501         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5502         /*
5503          * vdd might still be enabled do to the delayed vdd off.
5504          * Make sure vdd is actually turned off here.
5505          */
5506         pps_lock(intel_dp);
5507         edp_panel_vdd_off_sync(intel_dp);
5508         pps_unlock(intel_dp);
5509
5510         return false;
5511 }
5512
5513 bool
5514 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5515                         struct intel_connector *intel_connector)
5516 {
5517         struct drm_connector *connector = &intel_connector->base;
5518         struct intel_dp *intel_dp = &intel_dig_port->dp;
5519         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5520         struct drm_device *dev = intel_encoder->base.dev;
5521         struct drm_i915_private *dev_priv = to_i915(dev);
5522         enum port port = intel_dig_port->port;
5523         int type;
5524
5525         if (WARN(intel_dig_port->max_lanes < 1,
5526                  "Not enough lanes (%d) for DP on port %c\n",
5527                  intel_dig_port->max_lanes, port_name(port)))
5528                 return false;
5529
5530         intel_dp->pps_pipe = INVALID_PIPE;
5531
5532         /* intel_dp vfuncs */
5533         if (INTEL_INFO(dev)->gen >= 9)
5534                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5535         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5536                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5537         else if (HAS_PCH_SPLIT(dev))
5538                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5539         else
5540                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5541
5542         if (INTEL_INFO(dev)->gen >= 9)
5543                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5544         else
5545                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5546
5547         if (HAS_DDI(dev))
5548                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5549
5550         /* Preserve the current hw state. */
5551         intel_dp->DP = I915_READ(intel_dp->output_reg);
5552         intel_dp->attached_connector = intel_connector;
5553
5554         if (intel_dp_is_edp(dev, port))
5555                 type = DRM_MODE_CONNECTOR_eDP;
5556         else
5557                 type = DRM_MODE_CONNECTOR_DisplayPort;
5558
5559         /*
5560          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5561          * for DP the encoder type can be set by the caller to
5562          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5563          */
5564         if (type == DRM_MODE_CONNECTOR_eDP)
5565                 intel_encoder->type = INTEL_OUTPUT_EDP;
5566
5567         /* eDP only on port B and/or C on vlv/chv */
5568         if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5569                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5570                 return false;
5571
5572         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5573                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5574                         port_name(port));
5575
5576         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5577         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5578
5579         connector->interlace_allowed = true;
5580         connector->doublescan_allowed = 0;
5581
5582         intel_dp_aux_init(intel_dp, intel_connector);
5583
5584         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5585                           edp_panel_vdd_work);
5586
5587         intel_connector_attach_encoder(intel_connector, intel_encoder);
5588
5589         if (HAS_DDI(dev))
5590                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5591         else
5592                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5593
5594         /* Set up the hotplug pin. */
5595         switch (port) {
5596         case PORT_A:
5597                 intel_encoder->hpd_pin = HPD_PORT_A;
5598                 break;
5599         case PORT_B:
5600                 intel_encoder->hpd_pin = HPD_PORT_B;
5601                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5602                         intel_encoder->hpd_pin = HPD_PORT_A;
5603                 break;
5604         case PORT_C:
5605                 intel_encoder->hpd_pin = HPD_PORT_C;
5606                 break;
5607         case PORT_D:
5608                 intel_encoder->hpd_pin = HPD_PORT_D;
5609                 break;
5610         case PORT_E:
5611                 intel_encoder->hpd_pin = HPD_PORT_E;
5612                 break;
5613         default:
5614                 BUG();
5615         }
5616
5617         /* init MST on ports that can support it */
5618         if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
5619             (port == PORT_B || port == PORT_C || port == PORT_D))
5620                 intel_dp_mst_encoder_init(intel_dig_port,
5621                                           intel_connector->base.base.id);
5622
5623         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5624                 intel_dp_aux_fini(intel_dp);
5625                 intel_dp_mst_encoder_cleanup(intel_dig_port);
5626                 goto fail;
5627         }
5628
5629         intel_dp_add_properties(intel_dp, connector);
5630
5631         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5632          * 0xd.  Failure to do so will result in spurious interrupts being
5633          * generated on the port when a cable is not attached.
5634          */
5635         if (IS_G4X(dev) && !IS_GM45(dev)) {
5636                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5637                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5638         }
5639
5640         return true;
5641
5642 fail:
5643         drm_connector_cleanup(connector);
5644
5645         return false;
5646 }
5647
5648 bool intel_dp_init(struct drm_device *dev,
5649                    i915_reg_t output_reg,
5650                    enum port port)
5651 {
5652         struct drm_i915_private *dev_priv = to_i915(dev);
5653         struct intel_digital_port *intel_dig_port;
5654         struct intel_encoder *intel_encoder;
5655         struct drm_encoder *encoder;
5656         struct intel_connector *intel_connector;
5657
5658         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5659         if (!intel_dig_port)
5660                 return false;
5661
5662         intel_connector = intel_connector_alloc();
5663         if (!intel_connector)
5664                 goto err_connector_alloc;
5665
5666         intel_encoder = &intel_dig_port->base;
5667         encoder = &intel_encoder->base;
5668
5669         if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5670                              DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
5671                 goto err_encoder_init;
5672
5673         intel_encoder->compute_config = intel_dp_compute_config;
5674         intel_encoder->disable = intel_disable_dp;
5675         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5676         intel_encoder->get_config = intel_dp_get_config;
5677         intel_encoder->suspend = intel_dp_encoder_suspend;
5678         if (IS_CHERRYVIEW(dev)) {
5679                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5680                 intel_encoder->pre_enable = chv_pre_enable_dp;
5681                 intel_encoder->enable = vlv_enable_dp;
5682                 intel_encoder->post_disable = chv_post_disable_dp;
5683                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5684         } else if (IS_VALLEYVIEW(dev)) {
5685                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5686                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5687                 intel_encoder->enable = vlv_enable_dp;
5688                 intel_encoder->post_disable = vlv_post_disable_dp;
5689         } else {
5690                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5691                 intel_encoder->enable = g4x_enable_dp;
5692                 if (INTEL_INFO(dev)->gen >= 5)
5693                         intel_encoder->post_disable = ilk_post_disable_dp;
5694         }
5695
5696         intel_dig_port->port = port;
5697         intel_dig_port->dp.output_reg = output_reg;
5698         intel_dig_port->max_lanes = 4;
5699
5700         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5701         if (IS_CHERRYVIEW(dev)) {
5702                 if (port == PORT_D)
5703                         intel_encoder->crtc_mask = 1 << 2;
5704                 else
5705                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5706         } else {
5707                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5708         }
5709         intel_encoder->cloneable = 0;
5710
5711         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5712         dev_priv->hotplug.irq_port[port] = intel_dig_port;
5713
5714         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5715                 goto err_init_connector;
5716
5717         return true;
5718
5719 err_init_connector:
5720         drm_encoder_cleanup(encoder);
5721 err_encoder_init:
5722         kfree(intel_connector);
5723 err_connector_alloc:
5724         kfree(intel_dig_port);
5725         return false;
5726 }
5727
5728 void intel_dp_mst_suspend(struct drm_device *dev)
5729 {
5730         struct drm_i915_private *dev_priv = to_i915(dev);
5731         int i;
5732
5733         /* disable MST */
5734         for (i = 0; i < I915_MAX_PORTS; i++) {
5735                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5736
5737                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5738                         continue;
5739
5740                 if (intel_dig_port->dp.is_mst)
5741                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5742         }
5743 }
5744
5745 void intel_dp_mst_resume(struct drm_device *dev)
5746 {
5747         struct drm_i915_private *dev_priv = to_i915(dev);
5748         int i;
5749
5750         for (i = 0; i < I915_MAX_PORTS; i++) {
5751                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5752                 int ret;
5753
5754                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5755                         continue;
5756
5757                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5758                 if (ret)
5759                         intel_dp_check_mst_status(&intel_dig_port->dp);
5760         }
5761 }