drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 struct dp_link_dpll {
  45         int link_bw;
  46         struct dpll dpll;
  47 };
  48
  49 static const struct dp_link_dpll gen4_dpll[] = {
  50         { DP_LINK_BW_1_62,
  51                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  52         { DP_LINK_BW_2_7,
  53                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  54 };
  55
  56 static const struct dp_link_dpll pch_dpll[] = {
  57         { DP_LINK_BW_1_62,
  58                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  59         { DP_LINK_BW_2_7,
  60                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  61 };
  62
  63 static const struct dp_link_dpll vlv_dpll[] = {
  64         { DP_LINK_BW_1_62,
  65                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  66         { DP_LINK_BW_2_7,
  67                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  68 };
  69
  70 /*
  71  * CHV supports eDP 1.4 that have  more link rates.
  72  * Below only provides the fixed rate but exclude variable rate.
  73  */
  74 static const struct dp_link_dpll chv_dpll[] = {
  75         /*
  76          * CHV requires to program fractional division for m2.
  77          * m2 is stored in fixed point format using formula below
  78          * (m2_int << 22) | m2_fraction
  79          */
  80         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  81                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  82         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  83                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  84         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  85                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  86 };
  87
  88 /**
  89  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  90  * @intel_dp: DP struct
  91  *
  92  * If a CPU or PCH DP output is attached to an eDP panel, this function
  93  * will return true, and false otherwise.
  94  */
  95 static bool is_edp(struct intel_dp *intel_dp)
  96 {
  97         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  98
  99         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 100 }
 101
 102 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 103 {
 104         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 105
 106         return intel_dig_port->base.base.dev;
 107 }
 108
 109 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 110 {
 111         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 112 }
 113
 114 static void intel_dp_link_down(struct intel_dp *intel_dp);
 115 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 116 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 117 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 118 static void vlv_steal_power_sequencer(struct drm_device *dev,
 119                                       enum pipe pipe);
 120
 121 int
 122 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 123 {
 124         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 125         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 126
 127         switch (max_link_bw) {
 128         case DP_LINK_BW_1_62:
 129         case DP_LINK_BW_2_7:
 130                 break;
 131         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 132                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 133                      INTEL_INFO(dev)->gen >= 8) &&
 134                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 135                         max_link_bw = DP_LINK_BW_5_4;
 136                 else
 137                         max_link_bw = DP_LINK_BW_2_7;
 138                 break;
 139         default:
 140                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 141                      max_link_bw);
 142                 max_link_bw = DP_LINK_BW_1_62;
 143                 break;
 144         }
 145         return max_link_bw;
 146 }
 147
 148 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 149 {
 150         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 151         struct drm_device *dev = intel_dig_port->base.base.dev;
 152         u8 source_max, sink_max;
 153
 154         source_max = 4;
 155         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 156             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 157                 source_max = 2;
 158
 159         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 160
 161         return min(source_max, sink_max);
 162 }
 163
 164 /*
 165  * The units on the numbers in the next two are... bizarre.  Examples will
 166  * make it clearer; this one parallels an example in the eDP spec.
 167  *
 168  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 169  *
 170  *     270000 * 1 * 8 / 10 == 216000
 171  *
 172  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 173  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 174  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 175  * 119000.  At 18bpp that's 2142000 kilobits per second.
 176  *
 177  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 178  * get the result in decakilobits instead of kilobits.
 179  */
 180
 181 static int
 182 intel_dp_link_required(int pixel_clock, int bpp)
 183 {
 184         return (pixel_clock * bpp + 9) / 10;
 185 }
 186
 187 static int
 188 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 189 {
 190         return (max_link_clock * max_lanes * 8) / 10;
 191 }
 192
 193 static enum drm_mode_status
 194 intel_dp_mode_valid(struct drm_connector *connector,
 195                     struct drm_display_mode *mode)
 196 {
 197         struct intel_dp *intel_dp = intel_attached_dp(connector);
 198         struct intel_connector *intel_connector = to_intel_connector(connector);
 199         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 200         int target_clock = mode->clock;
 201         int max_rate, mode_rate, max_lanes, max_link_clock;
 202
 203         if (is_edp(intel_dp) && fixed_mode) {
 204                 if (mode->hdisplay > fixed_mode->hdisplay)
 205                         return MODE_PANEL;
 206
 207                 if (mode->vdisplay > fixed_mode->vdisplay)
 208                         return MODE_PANEL;
 209
 210                 target_clock = fixed_mode->clock;
 211         }
 212
 213         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 214         max_lanes = intel_dp_max_lane_count(intel_dp);
 215
 216         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 217         mode_rate = intel_dp_link_required(target_clock, 18);
 218
 219         if (mode_rate > max_rate)
 220                 return MODE_CLOCK_HIGH;
 221
 222         if (mode->clock < 10000)
 223                 return MODE_CLOCK_LOW;
 224
 225         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 226                 return MODE_H_ILLEGAL;
 227
 228         return MODE_OK;
 229 }
 230
 231 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 232 {
 233         int     i;
 234         uint32_t v = 0;
 235
 236         if (src_bytes > 4)
 237                 src_bytes = 4;
 238         for (i = 0; i < src_bytes; i++)
 239                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 240         return v;
 241 }
 242
 243 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 244 {
 245         int i;
 246         if (dst_bytes > 4)
 247                 dst_bytes = 4;
 248         for (i = 0; i < dst_bytes; i++)
 249                 dst[i] = src >> ((3-i) * 8);
 250 }
 251
 252 /* hrawclock is 1/4 the FSB frequency */
 253 static int
 254 intel_hrawclk(struct drm_device *dev)
 255 {
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         uint32_t clkcfg;
 258
 259         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 260         if (IS_VALLEYVIEW(dev))
 261                 return 200;
 262
 263         clkcfg = I915_READ(CLKCFG);
 264         switch (clkcfg & CLKCFG_FSB_MASK) {
 265         case CLKCFG_FSB_400:
 266                 return 100;
 267         case CLKCFG_FSB_533:
 268                 return 133;
 269         case CLKCFG_FSB_667:
 270                 return 166;
 271         case CLKCFG_FSB_800:
 272                 return 200;
 273         case CLKCFG_FSB_1067:
 274                 return 266;
 275         case CLKCFG_FSB_1333:
 276                 return 333;
 277         /* these two are just a guess; one of them might be right */
 278         case CLKCFG_FSB_1600:
 279         case CLKCFG_FSB_1600_ALT:
 280                 return 400;
 281         default:
 282                 return 133;
 283         }
 284 }
 285
 286 static void
 287 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 288                                     struct intel_dp *intel_dp);
 289 static void
 290 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 291                                               struct intel_dp *intel_dp);
 292
 293 static void pps_lock(struct intel_dp *intel_dp)
 294 {
 295         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 296         struct intel_encoder *encoder = &intel_dig_port->base;
 297         struct drm_device *dev = encoder->base.dev;
 298         struct drm_i915_private *dev_priv = dev->dev_private;
 299         enum intel_display_power_domain power_domain;
 300
 301         /*
 302          * See vlv_power_sequencer_reset() why we need
 303          * a power domain reference here.
 304          */
 305         power_domain = intel_display_port_power_domain(encoder);
 306         intel_display_power_get(dev_priv, power_domain);
 307
 308         mutex_lock(&dev_priv->pps_mutex);
 309 }
 310
 311 static void pps_unlock(struct intel_dp *intel_dp)
 312 {
 313         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 314         struct intel_encoder *encoder = &intel_dig_port->base;
 315         struct drm_device *dev = encoder->base.dev;
 316         struct drm_i915_private *dev_priv = dev->dev_private;
 317         enum intel_display_power_domain power_domain;
 318
 319         mutex_unlock(&dev_priv->pps_mutex);
 320
 321         power_domain = intel_display_port_power_domain(encoder);
 322         intel_display_power_put(dev_priv, power_domain);
 323 }
 324
 325 static void
 326 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 327 {
 328         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 329         struct drm_device *dev = intel_dig_port->base.base.dev;
 330         struct drm_i915_private *dev_priv = dev->dev_private;
 331         enum pipe pipe = intel_dp->pps_pipe;
 332         bool pll_enabled;
 333         uint32_t DP;
 334
 335         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 336                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 337                  pipe_name(pipe), port_name(intel_dig_port->port)))
 338                 return;
 339
 340         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 341                       pipe_name(pipe), port_name(intel_dig_port->port));
 342
 343         /* Preserve the BIOS-computed detected bit. This is
 344          * supposed to be read-only.
 345          */
 346         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 347         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 348         DP |= DP_PORT_WIDTH(1);
 349         DP |= DP_LINK_TRAIN_PAT_1;
 350
 351         if (IS_CHERRYVIEW(dev))
 352                 DP |= DP_PIPE_SELECT_CHV(pipe);
 353         else if (pipe == PIPE_B)
 354                 DP |= DP_PIPEB_SELECT;
 355
 356         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 357
 358         /*
 359          * The DPLL for the pipe must be enabled for this to work.
 360          * So enable temporarily it if it's not already enabled.
 361          */
 362         if (!pll_enabled)
 363                 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 364                                  &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
 365
 366         /*
 367          * Similar magic as in intel_dp_enable_port().
 368          * We _must_ do this port enable + disable trick
 369          * to make this power seqeuencer lock onto the port.
 370          * Otherwise even VDD force bit won't work.
 371          */
 372         I915_WRITE(intel_dp->output_reg, DP);
 373         POSTING_READ(intel_dp->output_reg);
 374
 375         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 376         POSTING_READ(intel_dp->output_reg);
 377
 378         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 379         POSTING_READ(intel_dp->output_reg);
 380
 381         if (!pll_enabled)
 382                 vlv_force_pll_off(dev, pipe);
 383 }
 384
 385 static enum pipe
 386 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 387 {
 388         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 389         struct drm_device *dev = intel_dig_port->base.base.dev;
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         struct intel_encoder *encoder;
 392         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 393         enum pipe pipe;
 394
 395         lockdep_assert_held(&dev_priv->pps_mutex);
 396
 397         /* We should never land here with regular DP ports */
 398         WARN_ON(!is_edp(intel_dp));
 399
 400         if (intel_dp->pps_pipe != INVALID_PIPE)
 401                 return intel_dp->pps_pipe;
 402
 403         /*
 404          * We don't have power sequencer currently.
 405          * Pick one that's not used by other ports.
 406          */
 407         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 408                             base.head) {
 409                 struct intel_dp *tmp;
 410
 411                 if (encoder->type != INTEL_OUTPUT_EDP)
 412                         continue;
 413
 414                 tmp = enc_to_intel_dp(&encoder->base);
 415
 416                 if (tmp->pps_pipe != INVALID_PIPE)
 417                         pipes &= ~(1 << tmp->pps_pipe);
 418         }
 419
 420         /*
 421          * Didn't find one. This should not happen since there
 422          * are two power sequencers and up to two eDP ports.
 423          */
 424         if (WARN_ON(pipes == 0))
 425                 pipe = PIPE_A;
 426         else
 427                 pipe = ffs(pipes) - 1;
 428
 429         vlv_steal_power_sequencer(dev, pipe);
 430         intel_dp->pps_pipe = pipe;
 431
 432         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 433                       pipe_name(intel_dp->pps_pipe),
 434                       port_name(intel_dig_port->port));
 435
 436         /* init power sequencer on this pipe and port */
 437         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 438         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 439
 440         /*
 441          * Even vdd force doesn't work until we've made
 442          * the power sequencer lock in on the port.
 443          */
 444         vlv_power_sequencer_kick(intel_dp);
 445
 446         return intel_dp->pps_pipe;
 447 }
 448
 449 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 450                                enum pipe pipe);
 451
 452 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 453                                enum pipe pipe)
 454 {
 455         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 456 }
 457
 458 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 459                                 enum pipe pipe)
 460 {
 461         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 462 }
 463
 464 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 465                          enum pipe pipe)
 466 {
 467         return true;
 468 }
 469
 470 static enum pipe
 471 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 472                      enum port port,
 473                      vlv_pipe_check pipe_check)
 474 {
 475         enum pipe pipe;
 476
 477         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 478                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 479                         PANEL_PORT_SELECT_MASK;
 480
 481                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 482                         continue;
 483
 484                 if (!pipe_check(dev_priv, pipe))
 485                         continue;
 486
 487                 return pipe;
 488         }
 489
 490         return INVALID_PIPE;
 491 }
 492
 493 static void
 494 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 495 {
 496         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 497         struct drm_device *dev = intel_dig_port->base.base.dev;
 498         struct drm_i915_private *dev_priv = dev->dev_private;
 499         enum port port = intel_dig_port->port;
 500
 501         lockdep_assert_held(&dev_priv->pps_mutex);
 502
 503         /* try to find a pipe with this port selected */
 504         /* first pick one where the panel is on */
 505         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 506                                                   vlv_pipe_has_pp_on);
 507         /* didn't find one? pick one where vdd is on */
 508         if (intel_dp->pps_pipe == INVALID_PIPE)
 509                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 510                                                           vlv_pipe_has_vdd_on);
 511         /* didn't find one? pick one with just the correct port */
 512         if (intel_dp->pps_pipe == INVALID_PIPE)
 513                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 514                                                           vlv_pipe_any);
 515
 516         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 517         if (intel_dp->pps_pipe == INVALID_PIPE) {
 518                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 519                               port_name(port));
 520                 return;
 521         }
 522
 523         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 524                       port_name(port), pipe_name(intel_dp->pps_pipe));
 525
 526         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 527         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 528 }
 529
 530 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 531 {
 532         struct drm_device *dev = dev_priv->dev;
 533         struct intel_encoder *encoder;
 534
 535         if (WARN_ON(!IS_VALLEYVIEW(dev)))
 536                 return;
 537
 538         /*
 539          * We can't grab pps_mutex here due to deadlock with power_domain
 540          * mutex when power_domain functions are called while holding pps_mutex.
 541          * That also means that in order to use pps_pipe the code needs to
 542          * hold both a power domain reference and pps_mutex, and the power domain
 543          * reference get/put must be done while _not_ holding pps_mutex.
 544          * pps_{lock,unlock}() do these steps in the correct order, so one
 545          * should use them always.
 546          */
 547
 548         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 549                 struct intel_dp *intel_dp;
 550
 551                 if (encoder->type != INTEL_OUTPUT_EDP)
 552                         continue;
 553
 554                 intel_dp = enc_to_intel_dp(&encoder->base);
 555                 intel_dp->pps_pipe = INVALID_PIPE;
 556         }
 557 }
 558
 559 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 560 {
 561         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 562
 563         if (HAS_PCH_SPLIT(dev))
 564                 return PCH_PP_CONTROL;
 565         else
 566                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 567 }
 568
 569 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 570 {
 571         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 return PCH_PP_STATUS;
 575         else
 576                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 577 }
 578
 579 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 580    This function only applicable when panel PM state is not to be tracked */
 581 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 582                               void *unused)
 583 {
 584         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 585                                                  edp_notifier);
 586         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 587         struct drm_i915_private *dev_priv = dev->dev_private;
 588         u32 pp_div;
 589         u32 pp_ctrl_reg, pp_div_reg;
 590
 591         if (!is_edp(intel_dp) || code != SYS_RESTART)
 592                 return 0;
 593
 594         pps_lock(intel_dp);
 595
 596         if (IS_VALLEYVIEW(dev)) {
 597                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 598
 599                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 600                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 601                 pp_div = I915_READ(pp_div_reg);
 602                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 603
 604                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 605                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 606                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 607                 msleep(intel_dp->panel_power_cycle_delay);
 608         }
 609
 610         pps_unlock(intel_dp);
 611
 612         return 0;
 613 }
 614
 615 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 616 {
 617         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 618         struct drm_i915_private *dev_priv = dev->dev_private;
 619
 620         lockdep_assert_held(&dev_priv->pps_mutex);
 621
 622         if (IS_VALLEYVIEW(dev) &&
 623             intel_dp->pps_pipe == INVALID_PIPE)
 624                 return false;
 625
 626         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 627 }
 628
 629 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 630 {
 631         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 632         struct drm_i915_private *dev_priv = dev->dev_private;
 633
 634         lockdep_assert_held(&dev_priv->pps_mutex);
 635
 636         if (IS_VALLEYVIEW(dev) &&
 637             intel_dp->pps_pipe == INVALID_PIPE)
 638                 return false;
 639
 640         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 641 }
 642
 643 static void
 644 intel_dp_check_edp(struct intel_dp *intel_dp)
 645 {
 646         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 647         struct drm_i915_private *dev_priv = dev->dev_private;
 648
 649         if (!is_edp(intel_dp))
 650                 return;
 651
 652         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 653                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 654                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 655                               I915_READ(_pp_stat_reg(intel_dp)),
 656                               I915_READ(_pp_ctrl_reg(intel_dp)));
 657         }
 658 }
 659
 660 static uint32_t
 661 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 662 {
 663         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 664         struct drm_device *dev = intel_dig_port->base.base.dev;
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 667         uint32_t status;
 668         bool done;
 669
 670 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 671         if (has_aux_irq)
 672                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 673                                           msecs_to_jiffies_timeout(10));
 674         else
 675                 done = wait_for_atomic(C, 10) == 0;
 676         if (!done)
 677                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 678                           has_aux_irq);
 679 #undef C
 680
 681         return status;
 682 }
 683
 684 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 685 {
 686         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 687         struct drm_device *dev = intel_dig_port->base.base.dev;
 688
 689         /*
 690          * The clock divider is based off the hrawclk, and would like to run at
 691          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 692          */
 693         return index ? 0 : intel_hrawclk(dev) / 2;
 694 }
 695
 696 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 697 {
 698         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 699         struct drm_device *dev = intel_dig_port->base.base.dev;
 700
 701         if (index)
 702                 return 0;
 703
 704         if (intel_dig_port->port == PORT_A) {
 705                 if (IS_GEN6(dev) || IS_GEN7(dev))
 706                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 707                 else
 708                         return 225; /* eDP input clock at 450Mhz */
 709         } else {
 710                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 711         }
 712 }
 713
 714 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 715 {
 716         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 717         struct drm_device *dev = intel_dig_port->base.base.dev;
 718         struct drm_i915_private *dev_priv = dev->dev_private;
 719
 720         if (intel_dig_port->port == PORT_A) {
 721                 if (index)
 722                         return 0;
 723                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 724         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 725                 /* Workaround for non-ULT HSW */
 726                 switch (index) {
 727                 case 0: return 63;
 728                 case 1: return 72;
 729                 default: return 0;
 730                 }
 731         } else  {
 732                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 733         }
 734 }
 735
 736 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 737 {
 738         return index ? 0 : 100;
 739 }
 740
 741 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 742 {
 743         /*
 744          * SKL doesn't need us to program the AUX clock divider (Hardware will
 745          * derive the clock from CDCLK automatically). We still implement the
 746          * get_aux_clock_divider vfunc to plug-in into the existing code.
 747          */
 748         return index ? 0 : 1;
 749 }
 750
 751 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 752                                       bool has_aux_irq,
 753                                       int send_bytes,
 754                                       uint32_t aux_clock_divider)
 755 {
 756         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 757         struct drm_device *dev = intel_dig_port->base.base.dev;
 758         uint32_t precharge, timeout;
 759
 760         if (IS_GEN6(dev))
 761                 precharge = 3;
 762         else
 763                 precharge = 5;
 764
 765         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 766                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 767         else
 768                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 769
 770         return DP_AUX_CH_CTL_SEND_BUSY |
 771                DP_AUX_CH_CTL_DONE |
 772                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 773                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 774                timeout |
 775                DP_AUX_CH_CTL_RECEIVE_ERROR |
 776                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 777                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 778                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 779 }
 780
 781 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 782                                       bool has_aux_irq,
 783                                       int send_bytes,
 784                                       uint32_t unused)
 785 {
 786         return DP_AUX_CH_CTL_SEND_BUSY |
 787                DP_AUX_CH_CTL_DONE |
 788                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 789                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 790                DP_AUX_CH_CTL_TIME_OUT_1600us |
 791                DP_AUX_CH_CTL_RECEIVE_ERROR |
 792                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 793                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 794 }
 795
 796 static int
 797 intel_dp_aux_ch(struct intel_dp *intel_dp,
 798                 const uint8_t *send, int send_bytes,
 799                 uint8_t *recv, int recv_size)
 800 {
 801         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 802         struct drm_device *dev = intel_dig_port->base.base.dev;
 803         struct drm_i915_private *dev_priv = dev->dev_private;
 804         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 805         uint32_t ch_data = ch_ctl + 4;
 806         uint32_t aux_clock_divider;
 807         int i, ret, recv_bytes;
 808         uint32_t status;
 809         int try, clock = 0;
 810         bool has_aux_irq = HAS_AUX_IRQ(dev);
 811         bool vdd;
 812
 813         pps_lock(intel_dp);
 814
 815         /*
 816          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 817          * In such cases we want to leave VDD enabled and it's up to upper layers
 818          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 819          * ourselves.
 820          */
 821         vdd = edp_panel_vdd_on(intel_dp);
 822
 823         /* dp aux is extremely sensitive to irq latency, hence request the
 824          * lowest possible wakeup latency and so prevent the cpu from going into
 825          * deep sleep states.
 826          */
 827         pm_qos_update_request(&dev_priv->pm_qos, 0);
 828
 829         intel_dp_check_edp(intel_dp);
 830
 831         intel_aux_display_runtime_get(dev_priv);
 832
 833         /* Try to wait for any previous AUX channel activity */
 834         for (try = 0; try < 3; try++) {
 835                 status = I915_READ_NOTRACE(ch_ctl);
 836                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 837                         break;
 838                 msleep(1);
 839         }
 840
 841         if (try == 3) {
 842                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 843                      I915_READ(ch_ctl));
 844                 ret = -EBUSY;
 845                 goto out;
 846         }
 847
 848         /* Only 5 data registers! */
 849         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 850                 ret = -E2BIG;
 851                 goto out;
 852         }
 853
 854         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 855                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 856                                                           has_aux_irq,
 857                                                           send_bytes,
 858                                                           aux_clock_divider);
 859
 860                 /* Must try at least 3 times according to DP spec */
 861                 for (try = 0; try < 5; try++) {
 862                         /* Load the send data into the aux channel data registers */
 863                         for (i = 0; i < send_bytes; i += 4)
 864                                 I915_WRITE(ch_data + i,
 865                                            intel_dp_pack_aux(send + i,
 866                                                              send_bytes - i));
 867
 868                         /* Send the command and wait for it to complete */
 869                         I915_WRITE(ch_ctl, send_ctl);
 870
 871                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 872
 873                         /* Clear done status and any errors */
 874                         I915_WRITE(ch_ctl,
 875                                    status |
 876                                    DP_AUX_CH_CTL_DONE |
 877                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 878                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 879
 880                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 881                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 882                                 continue;
 883                         if (status & DP_AUX_CH_CTL_DONE)
 884                                 break;
 885                 }
 886                 if (status & DP_AUX_CH_CTL_DONE)
 887                         break;
 888         }
 889
 890         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 891                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 892                 ret = -EBUSY;
 893                 goto out;
 894         }
 895
 896         /* Check for timeout or receive error.
 897          * Timeouts occur when the sink is not connected
 898          */
 899         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 900                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 901                 ret = -EIO;
 902                 goto out;
 903         }
 904
 905         /* Timeouts occur when the device isn't connected, so they're
 906          * "normal" -- don't fill the kernel log with these */
 907         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 908                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 909                 ret = -ETIMEDOUT;
 910                 goto out;
 911         }
 912
 913         /* Unload any bytes sent back from the other side */
 914         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 915                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 916         if (recv_bytes > recv_size)
 917                 recv_bytes = recv_size;
 918
 919         for (i = 0; i < recv_bytes; i += 4)
 920                 intel_dp_unpack_aux(I915_READ(ch_data + i),
 921                                     recv + i, recv_bytes - i);
 922
 923         ret = recv_bytes;
 924 out:
 925         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 926         intel_aux_display_runtime_put(dev_priv);
 927
 928         if (vdd)
 929                 edp_panel_vdd_off(intel_dp, false);
 930
 931         pps_unlock(intel_dp);
 932
 933         return ret;
 934 }
 935
 936 #define BARE_ADDRESS_SIZE       3
 937 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 938 static ssize_t
 939 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 940 {
 941         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 942         uint8_t txbuf[20], rxbuf[20];
 943         size_t txsize, rxsize;
 944         int ret;
 945
 946         txbuf[0] = msg->request << 4;
 947         txbuf[1] = msg->address >> 8;
 948         txbuf[2] = msg->address & 0xff;
 949         txbuf[3] = msg->size - 1;
 950
 951         switch (msg->request & ~DP_AUX_I2C_MOT) {
 952         case DP_AUX_NATIVE_WRITE:
 953         case DP_AUX_I2C_WRITE:
 954                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 955                 rxsize = 1;
 956
 957                 if (WARN_ON(txsize > 20))
 958                         return -E2BIG;
 959
 960                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 961
 962                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 963                 if (ret > 0) {
 964                         msg->reply = rxbuf[0] >> 4;
 965
 966                         /* Return payload size. */
 967                         ret = msg->size;
 968                 }
 969                 break;
 970
 971         case DP_AUX_NATIVE_READ:
 972         case DP_AUX_I2C_READ:
 973                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 974                 rxsize = msg->size + 1;
 975
 976                 if (WARN_ON(rxsize > 20))
 977                         return -E2BIG;
 978
 979                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 980                 if (ret > 0) {
 981                         msg->reply = rxbuf[0] >> 4;
 982                         /*
 983                          * Assume happy day, and copy the data. The caller is
 984                          * expected to check msg->reply before touching it.
 985                          *
 986                          * Return payload size.
 987                          */
 988                         ret--;
 989                         memcpy(msg->buffer, rxbuf + 1, ret);
 990                 }
 991                 break;
 992
 993         default:
 994                 ret = -EINVAL;
 995                 break;
 996         }
 997
 998         return ret;
 999 }
1000
1001 static void
1002 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1003 {
1004         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1005         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1006         enum port port = intel_dig_port->port;
1007         const char *name = NULL;
1008         int ret;
1009
1010         switch (port) {
1011         case PORT_A:
1012                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1013                 name = "DPDDC-A";
1014                 break;
1015         case PORT_B:
1016                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1017                 name = "DPDDC-B";
1018                 break;
1019         case PORT_C:
1020                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1021                 name = "DPDDC-C";
1022                 break;
1023         case PORT_D:
1024                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1025                 name = "DPDDC-D";
1026                 break;
1027         default:
1028                 BUG();
1029         }
1030
1031         /*
1032          * The AUX_CTL register is usually DP_CTL + 0x10.
1033          *
1034          * On Haswell and Broadwell though:
1035          *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1036          *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1037          *
1038          * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1039          */
1040         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1041                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1042
1043         intel_dp->aux.name = name;
1044         intel_dp->aux.dev = dev->dev;
1045         intel_dp->aux.transfer = intel_dp_aux_transfer;
1046
1047         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1048                       connector->base.kdev->kobj.name);
1049
1050         ret = drm_dp_aux_register(&intel_dp->aux);
1051         if (ret < 0) {
1052                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1053                           name, ret);
1054                 return;
1055         }
1056
1057         ret = sysfs_create_link(&connector->base.kdev->kobj,
1058                                 &intel_dp->aux.ddc.dev.kobj,
1059                                 intel_dp->aux.ddc.dev.kobj.name);
1060         if (ret < 0) {
1061                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1062                 drm_dp_aux_unregister(&intel_dp->aux);
1063         }
1064 }
1065
1066 static void
1067 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1068 {
1069         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1070
1071         if (!intel_connector->mst_port)
1072                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1073                                   intel_dp->aux.ddc.dev.kobj.name);
1074         intel_connector_unregister(intel_connector);
1075 }
1076
1077 static void
1078 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
1079 {
1080         u32 ctrl1;
1081
1082         pipe_config->ddi_pll_sel = SKL_DPLL0;
1083         pipe_config->dpll_hw_state.cfgcr1 = 0;
1084         pipe_config->dpll_hw_state.cfgcr2 = 0;
1085
1086         ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1087         switch (link_bw) {
1088         case DP_LINK_BW_1_62:
1089                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1090                                               SKL_DPLL0);
1091                 break;
1092         case DP_LINK_BW_2_7:
1093                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1094                                               SKL_DPLL0);
1095                 break;
1096         case DP_LINK_BW_5_4:
1097                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1098                                               SKL_DPLL0);
1099                 break;
1100         }
1101         pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1102 }
1103
1104 static void
1105 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
1106 {
1107         switch (link_bw) {
1108         case DP_LINK_BW_1_62:
1109                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1110                 break;
1111         case DP_LINK_BW_2_7:
1112                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1113                 break;
1114         case DP_LINK_BW_5_4:
1115                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1116                 break;
1117         }
1118 }
1119
1120 static void
1121 intel_dp_set_clock(struct intel_encoder *encoder,
1122                    struct intel_crtc_state *pipe_config, int link_bw)
1123 {
1124         struct drm_device *dev = encoder->base.dev;
1125         const struct dp_link_dpll *divisor = NULL;
1126         int i, count = 0;
1127
1128         if (IS_G4X(dev)) {
1129                 divisor = gen4_dpll;
1130                 count = ARRAY_SIZE(gen4_dpll);
1131         } else if (HAS_PCH_SPLIT(dev)) {
1132                 divisor = pch_dpll;
1133                 count = ARRAY_SIZE(pch_dpll);
1134         } else if (IS_CHERRYVIEW(dev)) {
1135                 divisor = chv_dpll;
1136                 count = ARRAY_SIZE(chv_dpll);
1137         } else if (IS_VALLEYVIEW(dev)) {
1138                 divisor = vlv_dpll;
1139                 count = ARRAY_SIZE(vlv_dpll);
1140         }
1141
1142         if (divisor && count) {
1143                 for (i = 0; i < count; i++) {
1144                         if (link_bw == divisor[i].link_bw) {
1145                                 pipe_config->dpll = divisor[i].dpll;
1146                                 pipe_config->clock_set = true;
1147                                 break;
1148                         }
1149                 }
1150         }
1151 }
1152
1153 bool
1154 intel_dp_compute_config(struct intel_encoder *encoder,
1155                         struct intel_crtc_state *pipe_config)
1156 {
1157         struct drm_device *dev = encoder->base.dev;
1158         struct drm_i915_private *dev_priv = dev->dev_private;
1159         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1160         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1161         enum port port = dp_to_dig_port(intel_dp)->port;
1162         struct intel_crtc *intel_crtc = encoder->new_crtc;
1163         struct intel_connector *intel_connector = intel_dp->attached_connector;
1164         int lane_count, clock;
1165         int min_lane_count = 1;
1166         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1167         /* Conveniently, the link BW constants become indices with a shift...*/
1168         int min_clock = 0;
1169         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1170         int bpp, mode_rate;
1171         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1172         int link_avail, link_clock;
1173
1174         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1175                 pipe_config->has_pch_encoder = true;
1176
1177         pipe_config->has_dp_encoder = true;
1178         pipe_config->has_drrs = false;
1179         pipe_config->has_audio = intel_dp->has_audio;
1180
1181         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1182                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1183                                        adjusted_mode);
1184                 if (!HAS_PCH_SPLIT(dev))
1185                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1186                                                  intel_connector->panel.fitting_mode);
1187                 else
1188                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1189                                                 intel_connector->panel.fitting_mode);
1190         }
1191
1192         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1193                 return false;
1194
1195         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1196                       "max bw %02x pixel clock %iKHz\n",
1197                       max_lane_count, bws[max_clock],
1198                       adjusted_mode->crtc_clock);
1199
1200         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1201          * bpc in between. */
1202         bpp = pipe_config->pipe_bpp;
1203         if (is_edp(intel_dp)) {
1204                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1205                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1206                                       dev_priv->vbt.edp_bpp);
1207                         bpp = dev_priv->vbt.edp_bpp;
1208                 }
1209
1210                 /*
1211                  * Use the maximum clock and number of lanes the eDP panel
1212                  * advertizes being capable of. The panels are generally
1213                  * designed to support only a single clock and lane
1214                  * configuration, and typically these values correspond to the
1215                  * native resolution of the panel.
1216                  */
1217                 min_lane_count = max_lane_count;
1218                 min_clock = max_clock;
1219         }
1220
1221         for (; bpp >= 6*3; bpp -= 2*3) {
1222                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1223                                                    bpp);
1224
1225                 for (clock = min_clock; clock <= max_clock; clock++) {
1226                         for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1227                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1228                                 link_avail = intel_dp_max_data_rate(link_clock,
1229                                                                     lane_count);
1230
1231                                 if (mode_rate <= link_avail) {
1232                                         goto found;
1233                                 }
1234                         }
1235                 }
1236         }
1237
1238         return false;
1239
1240 found:
1241         if (intel_dp->color_range_auto) {
1242                 /*
1243                  * See:
1244                  * CEA-861-E - 5.1 Default Encoding Parameters
1245                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1246                  */
1247                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1248                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
1249                 else
1250                         intel_dp->color_range = 0;
1251         }
1252
1253         if (intel_dp->color_range)
1254                 pipe_config->limited_color_range = true;
1255
1256         intel_dp->link_bw = bws[clock];
1257         intel_dp->lane_count = lane_count;
1258         pipe_config->pipe_bpp = bpp;
1259         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1260
1261         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1262                       intel_dp->link_bw, intel_dp->lane_count,
1263                       pipe_config->port_clock, bpp);
1264         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1265                       mode_rate, link_avail);
1266
1267         intel_link_compute_m_n(bpp, lane_count,
1268                                adjusted_mode->crtc_clock,
1269                                pipe_config->port_clock,
1270                                &pipe_config->dp_m_n);
1271
1272         if (intel_connector->panel.downclock_mode != NULL &&
1273                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1274                         pipe_config->has_drrs = true;
1275                         intel_link_compute_m_n(bpp, lane_count,
1276                                 intel_connector->panel.downclock_mode->clock,
1277                                 pipe_config->port_clock,
1278                                 &pipe_config->dp_m2_n2);
1279         }
1280
1281         if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1282                 skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
1283         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1284                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1285         else
1286                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1287
1288         return true;
1289 }
1290
1291 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1292 {
1293         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1294         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1295         struct drm_device *dev = crtc->base.dev;
1296         struct drm_i915_private *dev_priv = dev->dev_private;
1297         u32 dpa_ctl;
1298
1299         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1300                       crtc->config->port_clock);
1301         dpa_ctl = I915_READ(DP_A);
1302         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1303
1304         if (crtc->config->port_clock == 162000) {
1305                 /* For a long time we've carried around a ILK-DevA w/a for the
1306                  * 160MHz clock. If we're really unlucky, it's still required.
1307                  */
1308                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1309                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1310                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1311         } else {
1312                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1313                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1314         }
1315
1316         I915_WRITE(DP_A, dpa_ctl);
1317
1318         POSTING_READ(DP_A);
1319         udelay(500);
1320 }
1321
1322 static void intel_dp_prepare(struct intel_encoder *encoder)
1323 {
1324         struct drm_device *dev = encoder->base.dev;
1325         struct drm_i915_private *dev_priv = dev->dev_private;
1326         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1327         enum port port = dp_to_dig_port(intel_dp)->port;
1328         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1329         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1330
1331         /*
1332          * There are four kinds of DP registers:
1333          *
1334          *      IBX PCH
1335          *      SNB CPU
1336          *      IVB CPU
1337          *      CPT PCH
1338          *
1339          * IBX PCH and CPU are the same for almost everything,
1340          * except that the CPU DP PLL is configured in this
1341          * register
1342          *
1343          * CPT PCH is quite different, having many bits moved
1344          * to the TRANS_DP_CTL register instead. That
1345          * configuration happens (oddly) in ironlake_pch_enable
1346          */
1347
1348         /* Preserve the BIOS-computed detected bit. This is
1349          * supposed to be read-only.
1350          */
1351         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1352
1353         /* Handle DP bits in common between all three register formats */
1354         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1355         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1356
1357         if (crtc->config->has_audio)
1358                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1359
1360         /* Split out the IBX/CPU vs CPT settings */
1361
1362         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1363                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1364                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1365                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1366                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1367                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1368
1369                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1370                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1371
1372                 intel_dp->DP |= crtc->pipe << 29;
1373         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1374                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1375                         intel_dp->DP |= intel_dp->color_range;
1376
1377                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1378                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1379                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1380                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1381                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1382
1383                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1384                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1385
1386                 if (!IS_CHERRYVIEW(dev)) {
1387                         if (crtc->pipe == 1)
1388                                 intel_dp->DP |= DP_PIPEB_SELECT;
1389                 } else {
1390                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1391                 }
1392         } else {
1393                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1394         }
1395 }
1396
1397 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1398 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1399
1400 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1401 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1402
1403 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1404 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1405
1406 static void wait_panel_status(struct intel_dp *intel_dp,
1407                                        u32 mask,
1408                                        u32 value)
1409 {
1410         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1411         struct drm_i915_private *dev_priv = dev->dev_private;
1412         u32 pp_stat_reg, pp_ctrl_reg;
1413
1414         lockdep_assert_held(&dev_priv->pps_mutex);
1415
1416         pp_stat_reg = _pp_stat_reg(intel_dp);
1417         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1418
1419         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1420                         mask, value,
1421                         I915_READ(pp_stat_reg),
1422                         I915_READ(pp_ctrl_reg));
1423
1424         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1425                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1426                                 I915_READ(pp_stat_reg),
1427                                 I915_READ(pp_ctrl_reg));
1428         }
1429
1430         DRM_DEBUG_KMS("Wait complete\n");
1431 }
1432
1433 static void wait_panel_on(struct intel_dp *intel_dp)
1434 {
1435         DRM_DEBUG_KMS("Wait for panel power on\n");
1436         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1437 }
1438
1439 static void wait_panel_off(struct intel_dp *intel_dp)
1440 {
1441         DRM_DEBUG_KMS("Wait for panel power off time\n");
1442         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1443 }
1444
1445 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1446 {
1447         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1448
1449         /* When we disable the VDD override bit last we have to do the manual
1450          * wait. */
1451         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1452                                        intel_dp->panel_power_cycle_delay);
1453
1454         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1455 }
1456
1457 static void wait_backlight_on(struct intel_dp *intel_dp)
1458 {
1459         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1460                                        intel_dp->backlight_on_delay);
1461 }
1462
1463 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1464 {
1465         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1466                                        intel_dp->backlight_off_delay);
1467 }
1468
1469 /* Read the current pp_control value, unlocking the register if it
1470  * is locked
1471  */
1472
1473 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1474 {
1475         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1476         struct drm_i915_private *dev_priv = dev->dev_private;
1477         u32 control;
1478
1479         lockdep_assert_held(&dev_priv->pps_mutex);
1480
1481         control = I915_READ(_pp_ctrl_reg(intel_dp));
1482         control &= ~PANEL_UNLOCK_MASK;
1483         control |= PANEL_UNLOCK_REGS;
1484         return control;
1485 }
1486
1487 /*
1488  * Must be paired with edp_panel_vdd_off().
1489  * Must hold pps_mutex around the whole on/off sequence.
1490  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1491  */
1492 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1493 {
1494         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1495         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1496         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1497         struct drm_i915_private *dev_priv = dev->dev_private;
1498         enum intel_display_power_domain power_domain;
1499         u32 pp;
1500         u32 pp_stat_reg, pp_ctrl_reg;
1501         bool need_to_disable = !intel_dp->want_panel_vdd;
1502
1503         lockdep_assert_held(&dev_priv->pps_mutex);
1504
1505         if (!is_edp(intel_dp))
1506                 return false;
1507
1508         cancel_delayed_work(&intel_dp->panel_vdd_work);
1509         intel_dp->want_panel_vdd = true;
1510
1511         if (edp_have_panel_vdd(intel_dp))
1512                 return need_to_disable;
1513
1514         power_domain = intel_display_port_power_domain(intel_encoder);
1515         intel_display_power_get(dev_priv, power_domain);
1516
1517         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1518                       port_name(intel_dig_port->port));
1519
1520         if (!edp_have_panel_power(intel_dp))
1521                 wait_panel_power_cycle(intel_dp);
1522
1523         pp = ironlake_get_pp_control(intel_dp);
1524         pp |= EDP_FORCE_VDD;
1525
1526         pp_stat_reg = _pp_stat_reg(intel_dp);
1527         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1528
1529         I915_WRITE(pp_ctrl_reg, pp);
1530         POSTING_READ(pp_ctrl_reg);
1531         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1532                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1533         /*
1534          * If the panel wasn't on, delay before accessing aux channel
1535          */
1536         if (!edp_have_panel_power(intel_dp)) {
1537                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1538                               port_name(intel_dig_port->port));
1539                 msleep(intel_dp->panel_power_up_delay);
1540         }
1541
1542         return need_to_disable;
1543 }
1544
1545 /*
1546  * Must be paired with intel_edp_panel_vdd_off() or
1547  * intel_edp_panel_off().
1548  * Nested calls to these functions are not allowed since
1549  * we drop the lock. Caller must use some higher level
1550  * locking to prevent nested calls from other threads.
1551  */
1552 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1553 {
1554         bool vdd;
1555
1556         if (!is_edp(intel_dp))
1557                 return;
1558
1559         pps_lock(intel_dp);
1560         vdd = edp_panel_vdd_on(intel_dp);
1561         pps_unlock(intel_dp);
1562
1563         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1564              port_name(dp_to_dig_port(intel_dp)->port));
1565 }
1566
1567 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1568 {
1569         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1570         struct drm_i915_private *dev_priv = dev->dev_private;
1571         struct intel_digital_port *intel_dig_port =
1572                 dp_to_dig_port(intel_dp);
1573         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1574         enum intel_display_power_domain power_domain;
1575         u32 pp;
1576         u32 pp_stat_reg, pp_ctrl_reg;
1577
1578         lockdep_assert_held(&dev_priv->pps_mutex);
1579
1580         WARN_ON(intel_dp->want_panel_vdd);
1581
1582         if (!edp_have_panel_vdd(intel_dp))
1583                 return;
1584
1585         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1586                       port_name(intel_dig_port->port));
1587
1588         pp = ironlake_get_pp_control(intel_dp);
1589         pp &= ~EDP_FORCE_VDD;
1590
1591         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1592         pp_stat_reg = _pp_stat_reg(intel_dp);
1593
1594         I915_WRITE(pp_ctrl_reg, pp);
1595         POSTING_READ(pp_ctrl_reg);
1596
1597         /* Make sure sequencer is idle before allowing subsequent activity */
1598         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1599         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1600
1601         if ((pp & POWER_TARGET_ON) == 0)
1602                 intel_dp->last_power_cycle = jiffies;
1603
1604         power_domain = intel_display_port_power_domain(intel_encoder);
1605         intel_display_power_put(dev_priv, power_domain);
1606 }
1607
1608 static void edp_panel_vdd_work(struct work_struct *__work)
1609 {
1610         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1611                                                  struct intel_dp, panel_vdd_work);
1612
1613         pps_lock(intel_dp);
1614         if (!intel_dp->want_panel_vdd)
1615                 edp_panel_vdd_off_sync(intel_dp);
1616         pps_unlock(intel_dp);
1617 }
1618
1619 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1620 {
1621         unsigned long delay;
1622
1623         /*
1624          * Queue the timer to fire a long time from now (relative to the power
1625          * down delay) to keep the panel power up across a sequence of
1626          * operations.
1627          */
1628         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1629         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1630 }
1631
1632 /*
1633  * Must be paired with edp_panel_vdd_on().
1634  * Must hold pps_mutex around the whole on/off sequence.
1635  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1636  */
1637 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1638 {
1639         struct drm_i915_private *dev_priv =
1640                 intel_dp_to_dev(intel_dp)->dev_private;
1641
1642         lockdep_assert_held(&dev_priv->pps_mutex);
1643
1644         if (!is_edp(intel_dp))
1645                 return;
1646
1647         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1648              port_name(dp_to_dig_port(intel_dp)->port));
1649
1650         intel_dp->want_panel_vdd = false;
1651
1652         if (sync)
1653                 edp_panel_vdd_off_sync(intel_dp);
1654         else
1655                 edp_panel_vdd_schedule_off(intel_dp);
1656 }
1657
1658 static void edp_panel_on(struct intel_dp *intel_dp)
1659 {
1660         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1661         struct drm_i915_private *dev_priv = dev->dev_private;
1662         u32 pp;
1663         u32 pp_ctrl_reg;
1664
1665         lockdep_assert_held(&dev_priv->pps_mutex);
1666
1667         if (!is_edp(intel_dp))
1668                 return;
1669
1670         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1671                       port_name(dp_to_dig_port(intel_dp)->port));
1672
1673         if (WARN(edp_have_panel_power(intel_dp),
1674                  "eDP port %c panel power already on\n",
1675                  port_name(dp_to_dig_port(intel_dp)->port)))
1676                 return;
1677
1678         wait_panel_power_cycle(intel_dp);
1679
1680         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1681         pp = ironlake_get_pp_control(intel_dp);
1682         if (IS_GEN5(dev)) {
1683                 /* ILK workaround: disable reset around power sequence */
1684                 pp &= ~PANEL_POWER_RESET;
1685                 I915_WRITE(pp_ctrl_reg, pp);
1686                 POSTING_READ(pp_ctrl_reg);
1687         }
1688
1689         pp |= POWER_TARGET_ON;
1690         if (!IS_GEN5(dev))
1691                 pp |= PANEL_POWER_RESET;
1692
1693         I915_WRITE(pp_ctrl_reg, pp);
1694         POSTING_READ(pp_ctrl_reg);
1695
1696         wait_panel_on(intel_dp);
1697         intel_dp->last_power_on = jiffies;
1698
1699         if (IS_GEN5(dev)) {
1700                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1701                 I915_WRITE(pp_ctrl_reg, pp);
1702                 POSTING_READ(pp_ctrl_reg);
1703         }
1704 }
1705
1706 void intel_edp_panel_on(struct intel_dp *intel_dp)
1707 {
1708         if (!is_edp(intel_dp))
1709                 return;
1710
1711         pps_lock(intel_dp);
1712         edp_panel_on(intel_dp);
1713         pps_unlock(intel_dp);
1714 }
1715
1716
1717 static void edp_panel_off(struct intel_dp *intel_dp)
1718 {
1719         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1720         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1721         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1722         struct drm_i915_private *dev_priv = dev->dev_private;
1723         enum intel_display_power_domain power_domain;
1724         u32 pp;
1725         u32 pp_ctrl_reg;
1726
1727         lockdep_assert_held(&dev_priv->pps_mutex);
1728
1729         if (!is_edp(intel_dp))
1730                 return;
1731
1732         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1733                       port_name(dp_to_dig_port(intel_dp)->port));
1734
1735         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1736              port_name(dp_to_dig_port(intel_dp)->port));
1737
1738         pp = ironlake_get_pp_control(intel_dp);
1739         /* We need to switch off panel power _and_ force vdd, for otherwise some
1740          * panels get very unhappy and cease to work. */
1741         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1742                 EDP_BLC_ENABLE);
1743
1744         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1745
1746         intel_dp->want_panel_vdd = false;
1747
1748         I915_WRITE(pp_ctrl_reg, pp);
1749         POSTING_READ(pp_ctrl_reg);
1750
1751         intel_dp->last_power_cycle = jiffies;
1752         wait_panel_off(intel_dp);
1753
1754         /* We got a reference when we enabled the VDD. */
1755         power_domain = intel_display_port_power_domain(intel_encoder);
1756         intel_display_power_put(dev_priv, power_domain);
1757 }
1758
1759 void intel_edp_panel_off(struct intel_dp *intel_dp)
1760 {
1761         if (!is_edp(intel_dp))
1762                 return;
1763
1764         pps_lock(intel_dp);
1765         edp_panel_off(intel_dp);
1766         pps_unlock(intel_dp);
1767 }
1768
1769 /* Enable backlight in the panel power control. */
1770 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1771 {
1772         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1773         struct drm_device *dev = intel_dig_port->base.base.dev;
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         u32 pp;
1776         u32 pp_ctrl_reg;
1777
1778         /*
1779          * If we enable the backlight right away following a panel power
1780          * on, we may see slight flicker as the panel syncs with the eDP
1781          * link.  So delay a bit to make sure the image is solid before
1782          * allowing it to appear.
1783          */
1784         wait_backlight_on(intel_dp);
1785
1786         pps_lock(intel_dp);
1787
1788         pp = ironlake_get_pp_control(intel_dp);
1789         pp |= EDP_BLC_ENABLE;
1790
1791         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1792
1793         I915_WRITE(pp_ctrl_reg, pp);
1794         POSTING_READ(pp_ctrl_reg);
1795
1796         pps_unlock(intel_dp);
1797 }
1798
1799 /* Enable backlight PWM and backlight PP control. */
1800 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1801 {
1802         if (!is_edp(intel_dp))
1803                 return;
1804
1805         DRM_DEBUG_KMS("\n");
1806
1807         intel_panel_enable_backlight(intel_dp->attached_connector);
1808         _intel_edp_backlight_on(intel_dp);
1809 }
1810
1811 /* Disable backlight in the panel power control. */
1812 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1813 {
1814         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1815         struct drm_i915_private *dev_priv = dev->dev_private;
1816         u32 pp;
1817         u32 pp_ctrl_reg;
1818
1819         if (!is_edp(intel_dp))
1820                 return;
1821
1822         pps_lock(intel_dp);
1823
1824         pp = ironlake_get_pp_control(intel_dp);
1825         pp &= ~EDP_BLC_ENABLE;
1826
1827         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1828
1829         I915_WRITE(pp_ctrl_reg, pp);
1830         POSTING_READ(pp_ctrl_reg);
1831
1832         pps_unlock(intel_dp);
1833
1834         intel_dp->last_backlight_off = jiffies;
1835         edp_wait_backlight_off(intel_dp);
1836 }
1837
1838 /* Disable backlight PP control and backlight PWM. */
1839 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1840 {
1841         if (!is_edp(intel_dp))
1842                 return;
1843
1844         DRM_DEBUG_KMS("\n");
1845
1846         _intel_edp_backlight_off(intel_dp);
1847         intel_panel_disable_backlight(intel_dp->attached_connector);
1848 }
1849
1850 /*
1851  * Hook for controlling the panel power control backlight through the bl_power
1852  * sysfs attribute. Take care to handle multiple calls.
1853  */
1854 static void intel_edp_backlight_power(struct intel_connector *connector,
1855                                       bool enable)
1856 {
1857         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1858         bool is_enabled;
1859
1860         pps_lock(intel_dp);
1861         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1862         pps_unlock(intel_dp);
1863
1864         if (is_enabled == enable)
1865                 return;
1866
1867         DRM_DEBUG_KMS("panel power control backlight %s\n",
1868                       enable ? "enable" : "disable");
1869
1870         if (enable)
1871                 _intel_edp_backlight_on(intel_dp);
1872         else
1873                 _intel_edp_backlight_off(intel_dp);
1874 }
1875
1876 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1877 {
1878         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1879         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1880         struct drm_device *dev = crtc->dev;
1881         struct drm_i915_private *dev_priv = dev->dev_private;
1882         u32 dpa_ctl;
1883
1884         assert_pipe_disabled(dev_priv,
1885                              to_intel_crtc(crtc)->pipe);
1886
1887         DRM_DEBUG_KMS("\n");
1888         dpa_ctl = I915_READ(DP_A);
1889         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1890         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1891
1892         /* We don't adjust intel_dp->DP while tearing down the link, to
1893          * facilitate link retraining (e.g. after hotplug). Hence clear all
1894          * enable bits here to ensure that we don't enable too much. */
1895         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1896         intel_dp->DP |= DP_PLL_ENABLE;
1897         I915_WRITE(DP_A, intel_dp->DP);
1898         POSTING_READ(DP_A);
1899         udelay(200);
1900 }
1901
1902 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1903 {
1904         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1905         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1906         struct drm_device *dev = crtc->dev;
1907         struct drm_i915_private *dev_priv = dev->dev_private;
1908         u32 dpa_ctl;
1909
1910         assert_pipe_disabled(dev_priv,
1911                              to_intel_crtc(crtc)->pipe);
1912
1913         dpa_ctl = I915_READ(DP_A);
1914         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1915              "dp pll off, should be on\n");
1916         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1917
1918         /* We can't rely on the value tracked for the DP register in
1919          * intel_dp->DP because link_down must not change that (otherwise link
1920          * re-training will fail. */
1921         dpa_ctl &= ~DP_PLL_ENABLE;
1922         I915_WRITE(DP_A, dpa_ctl);
1923         POSTING_READ(DP_A);
1924         udelay(200);
1925 }
1926
1927 /* If the sink supports it, try to set the power state appropriately */
1928 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1929 {
1930         int ret, i;
1931
1932         /* Should have a valid DPCD by this point */
1933         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1934                 return;
1935
1936         if (mode != DRM_MODE_DPMS_ON) {
1937                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1938                                          DP_SET_POWER_D3);
1939         } else {
1940                 /*
1941                  * When turning on, we need to retry for 1ms to give the sink
1942                  * time to wake up.
1943                  */
1944                 for (i = 0; i < 3; i++) {
1945                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1946                                                  DP_SET_POWER_D0);
1947                         if (ret == 1)
1948                                 break;
1949                         msleep(1);
1950                 }
1951         }
1952
1953         if (ret != 1)
1954                 DRM_DEBUG_KMS("failed to %s sink power state\n",
1955                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
1956 }
1957
1958 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1959                                   enum pipe *pipe)
1960 {
1961         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1962         enum port port = dp_to_dig_port(intel_dp)->port;
1963         struct drm_device *dev = encoder->base.dev;
1964         struct drm_i915_private *dev_priv = dev->dev_private;
1965         enum intel_display_power_domain power_domain;
1966         u32 tmp;
1967
1968         power_domain = intel_display_port_power_domain(encoder);
1969         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1970                 return false;
1971
1972         tmp = I915_READ(intel_dp->output_reg);
1973
1974         if (!(tmp & DP_PORT_EN))
1975                 return false;
1976
1977         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1978                 *pipe = PORT_TO_PIPE_CPT(tmp);
1979         } else if (IS_CHERRYVIEW(dev)) {
1980                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1981         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1982                 *pipe = PORT_TO_PIPE(tmp);
1983         } else {
1984                 u32 trans_sel;
1985                 u32 trans_dp;
1986                 int i;
1987
1988                 switch (intel_dp->output_reg) {
1989                 case PCH_DP_B:
1990                         trans_sel = TRANS_DP_PORT_SEL_B;
1991                         break;
1992                 case PCH_DP_C:
1993                         trans_sel = TRANS_DP_PORT_SEL_C;
1994                         break;
1995                 case PCH_DP_D:
1996                         trans_sel = TRANS_DP_PORT_SEL_D;
1997                         break;
1998                 default:
1999                         return true;
2000                 }
2001
2002                 for_each_pipe(dev_priv, i) {
2003                         trans_dp = I915_READ(TRANS_DP_CTL(i));
2004                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2005                                 *pipe = i;
2006                                 return true;
2007                         }
2008                 }
2009
2010                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2011                               intel_dp->output_reg);
2012         }
2013
2014         return true;
2015 }
2016
2017 static void intel_dp_get_config(struct intel_encoder *encoder,
2018                                 struct intel_crtc_state *pipe_config)
2019 {
2020         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2021         u32 tmp, flags = 0;
2022         struct drm_device *dev = encoder->base.dev;
2023         struct drm_i915_private *dev_priv = dev->dev_private;
2024         enum port port = dp_to_dig_port(intel_dp)->port;
2025         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2026         int dotclock;
2027
2028         tmp = I915_READ(intel_dp->output_reg);
2029         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2030                 pipe_config->has_audio = true;
2031
2032         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
2033                 if (tmp & DP_SYNC_HS_HIGH)
2034                         flags |= DRM_MODE_FLAG_PHSYNC;
2035                 else
2036                         flags |= DRM_MODE_FLAG_NHSYNC;
2037
2038                 if (tmp & DP_SYNC_VS_HIGH)
2039                         flags |= DRM_MODE_FLAG_PVSYNC;
2040                 else
2041                         flags |= DRM_MODE_FLAG_NVSYNC;
2042         } else {
2043                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2044                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2045                         flags |= DRM_MODE_FLAG_PHSYNC;
2046                 else
2047                         flags |= DRM_MODE_FLAG_NHSYNC;
2048
2049                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2050                         flags |= DRM_MODE_FLAG_PVSYNC;
2051                 else
2052                         flags |= DRM_MODE_FLAG_NVSYNC;
2053         }
2054
2055         pipe_config->base.adjusted_mode.flags |= flags;
2056
2057         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2058             tmp & DP_COLOR_RANGE_16_235)
2059                 pipe_config->limited_color_range = true;
2060
2061         pipe_config->has_dp_encoder = true;
2062
2063         intel_dp_get_m_n(crtc, pipe_config);
2064
2065         if (port == PORT_A) {
2066                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2067                         pipe_config->port_clock = 162000;
2068                 else
2069                         pipe_config->port_clock = 270000;
2070         }
2071
2072         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2073                                             &pipe_config->dp_m_n);
2074
2075         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2076                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2077
2078         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2079
2080         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2081             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2082                 /*
2083                  * This is a big fat ugly hack.
2084                  *
2085                  * Some machines in UEFI boot mode provide us a VBT that has 18
2086                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2087                  * unknown we fail to light up. Yet the same BIOS boots up with
2088                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2089                  * max, not what it tells us to use.
2090                  *
2091                  * Note: This will still be broken if the eDP panel is not lit
2092                  * up by the BIOS, and thus we can't get the mode at module
2093                  * load.
2094                  */
2095                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2096                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2097                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2098         }
2099 }
2100
2101 static void intel_disable_dp(struct intel_encoder *encoder)
2102 {
2103         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2104         struct drm_device *dev = encoder->base.dev;
2105         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2106
2107         if (crtc->config->has_audio)
2108                 intel_audio_codec_disable(encoder);
2109
2110         if (HAS_PSR(dev) && !HAS_DDI(dev))
2111                 intel_psr_disable(intel_dp);
2112
2113         /* Make sure the panel is off before trying to change the mode. But also
2114          * ensure that we have vdd while we switch off the panel. */
2115         intel_edp_panel_vdd_on(intel_dp);
2116         intel_edp_backlight_off(intel_dp);
2117         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2118         intel_edp_panel_off(intel_dp);
2119
2120         /* disable the port before the pipe on g4x */
2121         if (INTEL_INFO(dev)->gen < 5)
2122                 intel_dp_link_down(intel_dp);
2123 }
2124
2125 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2126 {
2127         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2128         enum port port = dp_to_dig_port(intel_dp)->port;
2129
2130         intel_dp_link_down(intel_dp);
2131         if (port == PORT_A)
2132                 ironlake_edp_pll_off(intel_dp);
2133 }
2134
2135 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2136 {
2137         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2138
2139         intel_dp_link_down(intel_dp);
2140 }
2141
2142 static void chv_post_disable_dp(struct intel_encoder *encoder)
2143 {
2144         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2145         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2146         struct drm_device *dev = encoder->base.dev;
2147         struct drm_i915_private *dev_priv = dev->dev_private;
2148         struct intel_crtc *intel_crtc =
2149                 to_intel_crtc(encoder->base.crtc);
2150         enum dpio_channel ch = vlv_dport_to_channel(dport);
2151         enum pipe pipe = intel_crtc->pipe;
2152         u32 val;
2153
2154         intel_dp_link_down(intel_dp);
2155
2156         mutex_lock(&dev_priv->dpio_lock);
2157
2158         /* Propagate soft reset to data lane reset */
2159         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2160         val |= CHV_PCS_REQ_SOFTRESET_EN;
2161         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2162
2163         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2164         val |= CHV_PCS_REQ_SOFTRESET_EN;
2165         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2166
2167         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2168         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2169         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2170
2171         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2172         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2173         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2174
2175         mutex_unlock(&dev_priv->dpio_lock);
2176 }
2177
2178 static void
2179 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2180                          uint32_t *DP,
2181                          uint8_t dp_train_pat)
2182 {
2183         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2184         struct drm_device *dev = intel_dig_port->base.base.dev;
2185         struct drm_i915_private *dev_priv = dev->dev_private;
2186         enum port port = intel_dig_port->port;
2187
2188         if (HAS_DDI(dev)) {
2189                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2190
2191                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2192                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2193                 else
2194                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2195
2196                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2197                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2198                 case DP_TRAINING_PATTERN_DISABLE:
2199                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2200
2201                         break;
2202                 case DP_TRAINING_PATTERN_1:
2203                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2204                         break;
2205                 case DP_TRAINING_PATTERN_2:
2206                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2207                         break;
2208                 case DP_TRAINING_PATTERN_3:
2209                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2210                         break;
2211                 }
2212                 I915_WRITE(DP_TP_CTL(port), temp);
2213
2214         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2215                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2216
2217                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2218                 case DP_TRAINING_PATTERN_DISABLE:
2219                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2220                         break;
2221                 case DP_TRAINING_PATTERN_1:
2222                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2223                         break;
2224                 case DP_TRAINING_PATTERN_2:
2225                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2226                         break;
2227                 case DP_TRAINING_PATTERN_3:
2228                         DRM_ERROR("DP training pattern 3 not supported\n");
2229                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2230                         break;
2231                 }
2232
2233         } else {
2234                 if (IS_CHERRYVIEW(dev))
2235                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2236                 else
2237                         *DP &= ~DP_LINK_TRAIN_MASK;
2238
2239                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2240                 case DP_TRAINING_PATTERN_DISABLE:
2241                         *DP |= DP_LINK_TRAIN_OFF;
2242                         break;
2243                 case DP_TRAINING_PATTERN_1:
2244                         *DP |= DP_LINK_TRAIN_PAT_1;
2245                         break;
2246                 case DP_TRAINING_PATTERN_2:
2247                         *DP |= DP_LINK_TRAIN_PAT_2;
2248                         break;
2249                 case DP_TRAINING_PATTERN_3:
2250                         if (IS_CHERRYVIEW(dev)) {
2251                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2252                         } else {
2253                                 DRM_ERROR("DP training pattern 3 not supported\n");
2254                                 *DP |= DP_LINK_TRAIN_PAT_2;
2255                         }
2256                         break;
2257                 }
2258         }
2259 }
2260
2261 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2262 {
2263         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2264         struct drm_i915_private *dev_priv = dev->dev_private;
2265
2266         /* enable with pattern 1 (as per spec) */
2267         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2268                                  DP_TRAINING_PATTERN_1);
2269
2270         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2271         POSTING_READ(intel_dp->output_reg);
2272
2273         /*
2274          * Magic for VLV/CHV. We _must_ first set up the register
2275          * without actually enabling the port, and then do another
2276          * write to enable the port. Otherwise link training will
2277          * fail when the power sequencer is freshly used for this port.
2278          */
2279         intel_dp->DP |= DP_PORT_EN;
2280
2281         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2282         POSTING_READ(intel_dp->output_reg);
2283 }
2284
2285 static void intel_enable_dp(struct intel_encoder *encoder)
2286 {
2287         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2288         struct drm_device *dev = encoder->base.dev;
2289         struct drm_i915_private *dev_priv = dev->dev_private;
2290         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2291         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2292
2293         if (WARN_ON(dp_reg & DP_PORT_EN))
2294                 return;
2295
2296         pps_lock(intel_dp);
2297
2298         if (IS_VALLEYVIEW(dev))
2299                 vlv_init_panel_power_sequencer(intel_dp);
2300
2301         intel_dp_enable_port(intel_dp);
2302
2303         edp_panel_vdd_on(intel_dp);
2304         edp_panel_on(intel_dp);
2305         edp_panel_vdd_off(intel_dp, true);
2306
2307         pps_unlock(intel_dp);
2308
2309         if (IS_VALLEYVIEW(dev))
2310                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2311
2312         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2313         intel_dp_start_link_train(intel_dp);
2314         intel_dp_complete_link_train(intel_dp);
2315         intel_dp_stop_link_train(intel_dp);
2316
2317         if (crtc->config->has_audio) {
2318                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2319                                  pipe_name(crtc->pipe));
2320                 intel_audio_codec_enable(encoder);
2321         }
2322 }
2323
2324 static void g4x_enable_dp(struct intel_encoder *encoder)
2325 {
2326         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2327
2328         intel_enable_dp(encoder);
2329         intel_edp_backlight_on(intel_dp);
2330 }
2331
2332 static void vlv_enable_dp(struct intel_encoder *encoder)
2333 {
2334         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2335
2336         intel_edp_backlight_on(intel_dp);
2337         intel_psr_enable(intel_dp);
2338 }
2339
2340 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2341 {
2342         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2343         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2344
2345         intel_dp_prepare(encoder);
2346
2347         /* Only ilk+ has port A */
2348         if (dport->port == PORT_A) {
2349                 ironlake_set_pll_cpu_edp(intel_dp);
2350                 ironlake_edp_pll_on(intel_dp);
2351         }
2352 }
2353
2354 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2355 {
2356         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2357         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2358         enum pipe pipe = intel_dp->pps_pipe;
2359         int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2360
2361         edp_panel_vdd_off_sync(intel_dp);
2362
2363         /*
2364          * VLV seems to get confused when multiple power seqeuencers
2365          * have the same port selected (even if only one has power/vdd
2366          * enabled). The failure manifests as vlv_wait_port_ready() failing
2367          * CHV on the other hand doesn't seem to mind having the same port
2368          * selected in multiple power seqeuencers, but let's clear the
2369          * port select always when logically disconnecting a power sequencer
2370          * from a port.
2371          */
2372         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2373                       pipe_name(pipe), port_name(intel_dig_port->port));
2374         I915_WRITE(pp_on_reg, 0);
2375         POSTING_READ(pp_on_reg);
2376
2377         intel_dp->pps_pipe = INVALID_PIPE;
2378 }
2379
2380 static void vlv_steal_power_sequencer(struct drm_device *dev,
2381                                       enum pipe pipe)
2382 {
2383         struct drm_i915_private *dev_priv = dev->dev_private;
2384         struct intel_encoder *encoder;
2385
2386         lockdep_assert_held(&dev_priv->pps_mutex);
2387
2388         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2389                 return;
2390
2391         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2392                             base.head) {
2393                 struct intel_dp *intel_dp;
2394                 enum port port;
2395
2396                 if (encoder->type != INTEL_OUTPUT_EDP)
2397                         continue;
2398
2399                 intel_dp = enc_to_intel_dp(&encoder->base);
2400                 port = dp_to_dig_port(intel_dp)->port;
2401
2402                 if (intel_dp->pps_pipe != pipe)
2403                         continue;
2404
2405                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2406                               pipe_name(pipe), port_name(port));
2407
2408                 WARN(encoder->connectors_active,
2409                      "stealing pipe %c power sequencer from active eDP port %c\n",
2410                      pipe_name(pipe), port_name(port));
2411
2412                 /* make sure vdd is off before we steal it */
2413                 vlv_detach_power_sequencer(intel_dp);
2414         }
2415 }
2416
2417 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2418 {
2419         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2420         struct intel_encoder *encoder = &intel_dig_port->base;
2421         struct drm_device *dev = encoder->base.dev;
2422         struct drm_i915_private *dev_priv = dev->dev_private;
2423         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2424
2425         lockdep_assert_held(&dev_priv->pps_mutex);
2426
2427         if (!is_edp(intel_dp))
2428                 return;
2429
2430         if (intel_dp->pps_pipe == crtc->pipe)
2431                 return;
2432
2433         /*
2434          * If another power sequencer was being used on this
2435          * port previously make sure to turn off vdd there while
2436          * we still have control of it.
2437          */
2438         if (intel_dp->pps_pipe != INVALID_PIPE)
2439                 vlv_detach_power_sequencer(intel_dp);
2440
2441         /*
2442          * We may be stealing the power
2443          * sequencer from another port.
2444          */
2445         vlv_steal_power_sequencer(dev, crtc->pipe);
2446
2447         /* now it's all ours */
2448         intel_dp->pps_pipe = crtc->pipe;
2449
2450         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2451                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2452
2453         /* init power sequencer on this pipe and port */
2454         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2455         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2456 }
2457
2458 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2459 {
2460         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2461         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2462         struct drm_device *dev = encoder->base.dev;
2463         struct drm_i915_private *dev_priv = dev->dev_private;
2464         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2465         enum dpio_channel port = vlv_dport_to_channel(dport);
2466         int pipe = intel_crtc->pipe;
2467         u32 val;
2468
2469         mutex_lock(&dev_priv->dpio_lock);
2470
2471         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2472         val = 0;
2473         if (pipe)
2474                 val |= (1<<21);
2475         else
2476                 val &= ~(1<<21);
2477         val |= 0x001000c4;
2478         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2479         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2480         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2481
2482         mutex_unlock(&dev_priv->dpio_lock);
2483
2484         intel_enable_dp(encoder);
2485 }
2486
2487 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2488 {
2489         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2490         struct drm_device *dev = encoder->base.dev;
2491         struct drm_i915_private *dev_priv = dev->dev_private;
2492         struct intel_crtc *intel_crtc =
2493                 to_intel_crtc(encoder->base.crtc);
2494         enum dpio_channel port = vlv_dport_to_channel(dport);
2495         int pipe = intel_crtc->pipe;
2496
2497         intel_dp_prepare(encoder);
2498
2499         /* Program Tx lane resets to default */
2500         mutex_lock(&dev_priv->dpio_lock);
2501         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2502                          DPIO_PCS_TX_LANE2_RESET |
2503                          DPIO_PCS_TX_LANE1_RESET);
2504         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2505                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2506                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2507                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2508                                  DPIO_PCS_CLK_SOFT_RESET);
2509
2510         /* Fix up inter-pair skew failure */
2511         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2512         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2513         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2514         mutex_unlock(&dev_priv->dpio_lock);
2515 }
2516
2517 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2518 {
2519         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2520         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2521         struct drm_device *dev = encoder->base.dev;
2522         struct drm_i915_private *dev_priv = dev->dev_private;
2523         struct intel_crtc *intel_crtc =
2524                 to_intel_crtc(encoder->base.crtc);
2525         enum dpio_channel ch = vlv_dport_to_channel(dport);
2526         int pipe = intel_crtc->pipe;
2527         int data, i;
2528         u32 val;
2529
2530         mutex_lock(&dev_priv->dpio_lock);
2531
2532         /* allow hardware to manage TX FIFO reset source */
2533         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2534         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2535         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2536
2537         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2538         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2539         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2540
2541         /* Deassert soft data lane reset*/
2542         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2543         val |= CHV_PCS_REQ_SOFTRESET_EN;
2544         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2545
2546         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2547         val |= CHV_PCS_REQ_SOFTRESET_EN;
2548         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2549
2550         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2551         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2552         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2553
2554         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2555         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2556         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2557
2558         /* Program Tx lane latency optimal setting*/
2559         for (i = 0; i < 4; i++) {
2560                 /* Set the latency optimal bit */
2561                 data = (i == 1) ? 0x0 : 0x6;
2562                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2563                                 data << DPIO_FRC_LATENCY_SHFIT);
2564
2565                 /* Set the upar bit */
2566                 data = (i == 1) ? 0x0 : 0x1;
2567                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2568                                 data << DPIO_UPAR_SHIFT);
2569         }
2570
2571         /* Data lane stagger programming */
2572         /* FIXME: Fix up value only after power analysis */
2573
2574         mutex_unlock(&dev_priv->dpio_lock);
2575
2576         intel_enable_dp(encoder);
2577 }
2578
2579 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2580 {
2581         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2582         struct drm_device *dev = encoder->base.dev;
2583         struct drm_i915_private *dev_priv = dev->dev_private;
2584         struct intel_crtc *intel_crtc =
2585                 to_intel_crtc(encoder->base.crtc);
2586         enum dpio_channel ch = vlv_dport_to_channel(dport);
2587         enum pipe pipe = intel_crtc->pipe;
2588         u32 val;
2589
2590         intel_dp_prepare(encoder);
2591
2592         mutex_lock(&dev_priv->dpio_lock);
2593
2594         /* program left/right clock distribution */
2595         if (pipe != PIPE_B) {
2596                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2597                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2598                 if (ch == DPIO_CH0)
2599                         val |= CHV_BUFLEFTENA1_FORCE;
2600                 if (ch == DPIO_CH1)
2601                         val |= CHV_BUFRIGHTENA1_FORCE;
2602                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2603         } else {
2604                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2605                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2606                 if (ch == DPIO_CH0)
2607                         val |= CHV_BUFLEFTENA2_FORCE;
2608                 if (ch == DPIO_CH1)
2609                         val |= CHV_BUFRIGHTENA2_FORCE;
2610                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2611         }
2612
2613         /* program clock channel usage */
2614         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2615         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2616         if (pipe != PIPE_B)
2617                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2618         else
2619                 val |= CHV_PCS_USEDCLKCHANNEL;
2620         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2621
2622         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2623         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2624         if (pipe != PIPE_B)
2625                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2626         else
2627                 val |= CHV_PCS_USEDCLKCHANNEL;
2628         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2629
2630         /*
2631          * This a a bit weird since generally CL
2632          * matches the pipe, but here we need to
2633          * pick the CL based on the port.
2634          */
2635         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2636         if (pipe != PIPE_B)
2637                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2638         else
2639                 val |= CHV_CMN_USEDCLKCHANNEL;
2640         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2641
2642         mutex_unlock(&dev_priv->dpio_lock);
2643 }
2644
2645 /*
2646  * Native read with retry for link status and receiver capability reads for
2647  * cases where the sink may still be asleep.
2648  *
2649  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2650  * supposed to retry 3 times per the spec.
2651  */
2652 static ssize_t
2653 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2654                         void *buffer, size_t size)
2655 {
2656         ssize_t ret;
2657         int i;
2658
2659         /*
2660          * Sometime we just get the same incorrect byte repeated
2661          * over the entire buffer. Doing just one throw away read
2662          * initially seems to "solve" it.
2663          */
2664         drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2665
2666         for (i = 0; i < 3; i++) {
2667                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2668                 if (ret == size)
2669                         return ret;
2670                 msleep(1);
2671         }
2672
2673         return ret;
2674 }
2675
2676 /*
2677  * Fetch AUX CH registers 0x202 - 0x207 which contain
2678  * link status information
2679  */
2680 static bool
2681 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2682 {
2683         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2684                                        DP_LANE0_1_STATUS,
2685                                        link_status,
2686                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2687 }
2688
2689 /* These are source-specific values. */
2690 static uint8_t
2691 intel_dp_voltage_max(struct intel_dp *intel_dp)
2692 {
2693         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2694         struct drm_i915_private *dev_priv = dev->dev_private;
2695         enum port port = dp_to_dig_port(intel_dp)->port;
2696
2697         if (INTEL_INFO(dev)->gen >= 9) {
2698                 if (dev_priv->vbt.edp_low_vswing && port == PORT_A)
2699                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2700                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2701         } else if (IS_VALLEYVIEW(dev))
2702                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2703         else if (IS_GEN7(dev) && port == PORT_A)
2704                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2705         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2706                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2707         else
2708                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2709 }
2710
2711 static uint8_t
2712 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2713 {
2714         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2715         enum port port = dp_to_dig_port(intel_dp)->port;
2716
2717         if (INTEL_INFO(dev)->gen >= 9) {
2718                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2719                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2720                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2721                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2722                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2723                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2724                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2725                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2726                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2727                 default:
2728                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2729                 }
2730         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2731                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2732                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2733                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2734                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2735                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2736                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2737                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2738                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2739                 default:
2740                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2741                 }
2742         } else if (IS_VALLEYVIEW(dev)) {
2743                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2744                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2745                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2746                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2747                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2748                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2749                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2750                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2751                 default:
2752                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2753                 }
2754         } else if (IS_GEN7(dev) && port == PORT_A) {
2755                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2756                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2757                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2758                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2759                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2760                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2761                 default:
2762                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2763                 }
2764         } else {
2765                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2766                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2767                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2768                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2769                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2770                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2771                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2772                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2773                 default:
2774                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2775                 }
2776         }
2777 }
2778
2779 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2780 {
2781         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2782         struct drm_i915_private *dev_priv = dev->dev_private;
2783         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2784         struct intel_crtc *intel_crtc =
2785                 to_intel_crtc(dport->base.base.crtc);
2786         unsigned long demph_reg_value, preemph_reg_value,
2787                 uniqtranscale_reg_value;
2788         uint8_t train_set = intel_dp->train_set[0];
2789         enum dpio_channel port = vlv_dport_to_channel(dport);
2790         int pipe = intel_crtc->pipe;
2791
2792         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2793         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2794                 preemph_reg_value = 0x0004000;
2795                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2796                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2797                         demph_reg_value = 0x2B405555;
2798                         uniqtranscale_reg_value = 0x552AB83A;
2799                         break;
2800                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2801                         demph_reg_value = 0x2B404040;
2802                         uniqtranscale_reg_value = 0x5548B83A;
2803                         break;
2804                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2805                         demph_reg_value = 0x2B245555;
2806                         uniqtranscale_reg_value = 0x5560B83A;
2807                         break;
2808                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2809                         demph_reg_value = 0x2B405555;
2810                         uniqtranscale_reg_value = 0x5598DA3A;
2811                         break;
2812                 default:
2813                         return 0;
2814                 }
2815                 break;
2816         case DP_TRAIN_PRE_EMPH_LEVEL_1:
2817                 preemph_reg_value = 0x0002000;
2818                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2819                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2820                         demph_reg_value = 0x2B404040;
2821                         uniqtranscale_reg_value = 0x5552B83A;
2822                         break;
2823                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2824                         demph_reg_value = 0x2B404848;
2825                         uniqtranscale_reg_value = 0x5580B83A;
2826                         break;
2827                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2828                         demph_reg_value = 0x2B404040;
2829                         uniqtranscale_reg_value = 0x55ADDA3A;
2830                         break;
2831                 default:
2832                         return 0;
2833                 }
2834                 break;
2835         case DP_TRAIN_PRE_EMPH_LEVEL_2:
2836                 preemph_reg_value = 0x0000000;
2837                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2838                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2839                         demph_reg_value = 0x2B305555;
2840                         uniqtranscale_reg_value = 0x5570B83A;
2841                         break;
2842                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2843                         demph_reg_value = 0x2B2B4040;
2844                         uniqtranscale_reg_value = 0x55ADDA3A;
2845                         break;
2846                 default:
2847                         return 0;
2848                 }
2849                 break;
2850         case DP_TRAIN_PRE_EMPH_LEVEL_3:
2851                 preemph_reg_value = 0x0006000;
2852                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2853                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2854                         demph_reg_value = 0x1B405555;
2855                         uniqtranscale_reg_value = 0x55ADDA3A;
2856                         break;
2857                 default:
2858                         return 0;
2859                 }
2860                 break;
2861         default:
2862                 return 0;
2863         }
2864
2865         mutex_lock(&dev_priv->dpio_lock);
2866         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2867         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2868         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2869                          uniqtranscale_reg_value);
2870         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2871         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2872         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2873         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2874         mutex_unlock(&dev_priv->dpio_lock);
2875
2876         return 0;
2877 }
2878
2879 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2880 {
2881         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2882         struct drm_i915_private *dev_priv = dev->dev_private;
2883         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2884         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2885         u32 deemph_reg_value, margin_reg_value, val;
2886         uint8_t train_set = intel_dp->train_set[0];
2887         enum dpio_channel ch = vlv_dport_to_channel(dport);
2888         enum pipe pipe = intel_crtc->pipe;
2889         int i;
2890
2891         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2892         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2893                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2894                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2895                         deemph_reg_value = 128;
2896                         margin_reg_value = 52;
2897                         break;
2898                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2899                         deemph_reg_value = 128;
2900                         margin_reg_value = 77;
2901                         break;
2902                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2903                         deemph_reg_value = 128;
2904                         margin_reg_value = 102;
2905                         break;
2906                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2907                         deemph_reg_value = 128;
2908                         margin_reg_value = 154;
2909                         /* FIXME extra to set for 1200 */
2910                         break;
2911                 default:
2912                         return 0;
2913                 }
2914                 break;
2915         case DP_TRAIN_PRE_EMPH_LEVEL_1:
2916                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2917                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2918                         deemph_reg_value = 85;
2919                         margin_reg_value = 78;
2920                         break;
2921                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2922                         deemph_reg_value = 85;
2923                         margin_reg_value = 116;
2924                         break;
2925                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2926                         deemph_reg_value = 85;
2927                         margin_reg_value = 154;
2928                         break;
2929                 default:
2930                         return 0;
2931                 }
2932                 break;
2933         case DP_TRAIN_PRE_EMPH_LEVEL_2:
2934                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2935                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2936                         deemph_reg_value = 64;
2937                         margin_reg_value = 104;
2938                         break;
2939                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2940                         deemph_reg_value = 64;
2941                         margin_reg_value = 154;
2942                         break;
2943                 default:
2944                         return 0;
2945                 }
2946                 break;
2947         case DP_TRAIN_PRE_EMPH_LEVEL_3:
2948                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2949                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2950                         deemph_reg_value = 43;
2951                         margin_reg_value = 154;
2952                         break;
2953                 default:
2954                         return 0;
2955                 }
2956                 break;
2957         default:
2958                 return 0;
2959         }
2960
2961         mutex_lock(&dev_priv->dpio_lock);
2962
2963         /* Clear calc init */
2964         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2965         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2966         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2967         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
2968         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2969
2970         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2971         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2972         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2973         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
2974         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2975
2976         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
2977         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2978         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2979         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
2980
2981         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
2982         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2983         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2984         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
2985
2986         /* Program swing deemph */
2987         for (i = 0; i < 4; i++) {
2988                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2989                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2990                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2991                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2992         }
2993
2994         /* Program swing margin */
2995         for (i = 0; i < 4; i++) {
2996                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2997                 val &= ~DPIO_SWING_MARGIN000_MASK;
2998                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
2999                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3000         }
3001
3002         /* Disable unique transition scale */
3003         for (i = 0; i < 4; i++) {
3004                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3005                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3006                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3007         }
3008
3009         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3010                         == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3011                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3012                         == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3013
3014                 /*
3015                  * The document said it needs to set bit 27 for ch0 and bit 26
3016                  * for ch1. Might be a typo in the doc.
3017                  * For now, for this unique transition scale selection, set bit
3018                  * 27 for ch0 and ch1.
3019                  */
3020                 for (i = 0; i < 4; i++) {
3021                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3022                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3023                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3024                 }
3025
3026                 for (i = 0; i < 4; i++) {
3027                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3028                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3029                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3030                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3031                 }
3032         }
3033
3034         /* Start swing calculation */
3035         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3036         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3037         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3038
3039         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3040         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3041         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3042
3043         /* LRC Bypass */
3044         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3045         val |= DPIO_LRC_BYPASS;
3046         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3047
3048         mutex_unlock(&dev_priv->dpio_lock);
3049
3050         return 0;
3051 }
3052
3053 static void
3054 intel_get_adjust_train(struct intel_dp *intel_dp,
3055                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
3056 {
3057         uint8_t v = 0;
3058         uint8_t p = 0;
3059         int lane;
3060         uint8_t voltage_max;
3061         uint8_t preemph_max;
3062
3063         for (lane = 0; lane < intel_dp->lane_count; lane++) {
3064                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3065                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3066
3067                 if (this_v > v)
3068                         v = this_v;
3069                 if (this_p > p)
3070                         p = this_p;
3071         }
3072
3073         voltage_max = intel_dp_voltage_max(intel_dp);
3074         if (v >= voltage_max)
3075                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3076
3077         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3078         if (p >= preemph_max)
3079                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3080
3081         for (lane = 0; lane < 4; lane++)
3082                 intel_dp->train_set[lane] = v | p;
3083 }
3084
3085 static uint32_t
3086 intel_gen4_signal_levels(uint8_t train_set)
3087 {
3088         uint32_t        signal_levels = 0;
3089
3090         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3091         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3092         default:
3093                 signal_levels |= DP_VOLTAGE_0_4;
3094                 break;
3095         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3096                 signal_levels |= DP_VOLTAGE_0_6;
3097                 break;
3098         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3099                 signal_levels |= DP_VOLTAGE_0_8;
3100                 break;
3101         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3102                 signal_levels |= DP_VOLTAGE_1_2;
3103                 break;
3104         }
3105         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3106         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3107         default:
3108                 signal_levels |= DP_PRE_EMPHASIS_0;
3109                 break;
3110         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3111                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3112                 break;
3113         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3114                 signal_levels |= DP_PRE_EMPHASIS_6;
3115                 break;
3116         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3117                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3118                 break;
3119         }
3120         return signal_levels;
3121 }
3122
3123 /* Gen6's DP voltage swing and pre-emphasis control */
3124 static uint32_t
3125 intel_gen6_edp_signal_levels(uint8_t train_set)
3126 {
3127         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3128                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3129         switch (signal_levels) {
3130         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3131         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3132                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3133         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3134                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3135         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3136         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3137                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3138         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3139         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3140                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3141         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3142         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3143                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3144         default:
3145                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3146                               "0x%x\n", signal_levels);
3147                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3148         }
3149 }
3150
3151 /* Gen7's DP voltage swing and pre-emphasis control */
3152 static uint32_t
3153 intel_gen7_edp_signal_levels(uint8_t train_set)
3154 {
3155         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3156                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3157         switch (signal_levels) {
3158         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3159                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3160         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3161                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3162         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3163                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3164
3165         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3166                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3167         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3168                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3169
3170         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3171                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3172         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3173                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3174
3175         default:
3176                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3177                               "0x%x\n", signal_levels);
3178                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3179         }
3180 }
3181
3182 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3183 static uint32_t
3184 intel_hsw_signal_levels(uint8_t train_set)
3185 {
3186         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3187                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3188         switch (signal_levels) {
3189         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3190                 return DDI_BUF_TRANS_SELECT(0);
3191         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3192                 return DDI_BUF_TRANS_SELECT(1);
3193         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3194                 return DDI_BUF_TRANS_SELECT(2);
3195         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3196                 return DDI_BUF_TRANS_SELECT(3);
3197
3198         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3199                 return DDI_BUF_TRANS_SELECT(4);
3200         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3201                 return DDI_BUF_TRANS_SELECT(5);
3202         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3203                 return DDI_BUF_TRANS_SELECT(6);
3204
3205         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3206                 return DDI_BUF_TRANS_SELECT(7);
3207         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3208                 return DDI_BUF_TRANS_SELECT(8);
3209
3210         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3211                 return DDI_BUF_TRANS_SELECT(9);
3212         default:
3213                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3214                               "0x%x\n", signal_levels);
3215                 return DDI_BUF_TRANS_SELECT(0);
3216         }
3217 }
3218
3219 /* Properly updates "DP" with the correct signal levels. */
3220 static void
3221 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3222 {
3223         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3224         enum port port = intel_dig_port->port;
3225         struct drm_device *dev = intel_dig_port->base.base.dev;
3226         uint32_t signal_levels, mask;
3227         uint8_t train_set = intel_dp->train_set[0];
3228
3229         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
3230                 signal_levels = intel_hsw_signal_levels(train_set);
3231                 mask = DDI_BUF_EMP_MASK;
3232         } else if (IS_CHERRYVIEW(dev)) {
3233                 signal_levels = intel_chv_signal_levels(intel_dp);
3234                 mask = 0;
3235         } else if (IS_VALLEYVIEW(dev)) {
3236                 signal_levels = intel_vlv_signal_levels(intel_dp);
3237                 mask = 0;
3238         } else if (IS_GEN7(dev) && port == PORT_A) {
3239                 signal_levels = intel_gen7_edp_signal_levels(train_set);
3240                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3241         } else if (IS_GEN6(dev) && port == PORT_A) {
3242                 signal_levels = intel_gen6_edp_signal_levels(train_set);
3243                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3244         } else {
3245                 signal_levels = intel_gen4_signal_levels(train_set);
3246                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3247         }
3248
3249         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3250
3251         *DP = (*DP & ~mask) | signal_levels;
3252 }
3253
3254 static bool
3255 intel_dp_set_link_train(struct intel_dp *intel_dp,
3256                         uint32_t *DP,
3257                         uint8_t dp_train_pat)
3258 {
3259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3260         struct drm_device *dev = intel_dig_port->base.base.dev;
3261         struct drm_i915_private *dev_priv = dev->dev_private;
3262         uint8_t buf[sizeof(intel_dp->train_set) + 1];
3263         int ret, len;
3264
3265         _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3266
3267         I915_WRITE(intel_dp->output_reg, *DP);
3268         POSTING_READ(intel_dp->output_reg);
3269
3270         buf[0] = dp_train_pat;
3271         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3272             DP_TRAINING_PATTERN_DISABLE) {
3273                 /* don't write DP_TRAINING_LANEx_SET on disable */
3274                 len = 1;
3275         } else {
3276                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3277                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3278                 len = intel_dp->lane_count + 1;
3279         }
3280
3281         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3282                                 buf, len);
3283
3284         return ret == len;
3285 }
3286
3287 static bool
3288 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3289                         uint8_t dp_train_pat)
3290 {
3291         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3292         intel_dp_set_signal_levels(intel_dp, DP);
3293         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3294 }
3295
3296 static bool
3297 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3298                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3299 {
3300         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3301         struct drm_device *dev = intel_dig_port->base.base.dev;
3302         struct drm_i915_private *dev_priv = dev->dev_private;
3303         int ret;
3304
3305         intel_get_adjust_train(intel_dp, link_status);
3306         intel_dp_set_signal_levels(intel_dp, DP);
3307
3308         I915_WRITE(intel_dp->output_reg, *DP);
3309         POSTING_READ(intel_dp->output_reg);
3310
3311         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3312                                 intel_dp->train_set, intel_dp->lane_count);
3313
3314         return ret == intel_dp->lane_count;
3315 }
3316
3317 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3318 {
3319         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3320         struct drm_device *dev = intel_dig_port->base.base.dev;
3321         struct drm_i915_private *dev_priv = dev->dev_private;
3322         enum port port = intel_dig_port->port;
3323         uint32_t val;
3324
3325         if (!HAS_DDI(dev))
3326                 return;
3327
3328         val = I915_READ(DP_TP_CTL(port));
3329         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3330         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3331         I915_WRITE(DP_TP_CTL(port), val);
3332
3333         /*
3334          * On PORT_A we can have only eDP in SST mode. There the only reason
3335          * we need to set idle transmission mode is to work around a HW issue
3336          * where we enable the pipe while not in idle link-training mode.
3337          * In this case there is requirement to wait for a minimum number of
3338          * idle patterns to be sent.
3339          */
3340         if (port == PORT_A)
3341                 return;
3342
3343         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3344                      1))
3345                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3346 }
3347
3348 /* Enable corresponding port and start training pattern 1 */
3349 void
3350 intel_dp_start_link_train(struct intel_dp *intel_dp)
3351 {
3352         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3353         struct drm_device *dev = encoder->dev;
3354         int i;
3355         uint8_t voltage;
3356         int voltage_tries, loop_tries;
3357         uint32_t DP = intel_dp->DP;
3358         uint8_t link_config[2];
3359
3360         if (HAS_DDI(dev))
3361                 intel_ddi_prepare_link_retrain(encoder);
3362
3363         /* Write the link configuration data */
3364         link_config[0] = intel_dp->link_bw;
3365         link_config[1] = intel_dp->lane_count;
3366         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3367                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3368         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3369
3370         link_config[0] = 0;
3371         link_config[1] = DP_SET_ANSI_8B10B;
3372         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3373
3374         DP |= DP_PORT_EN;
3375
3376         /* clock recovery */
3377         if (!intel_dp_reset_link_train(intel_dp, &DP,
3378                                        DP_TRAINING_PATTERN_1 |
3379                                        DP_LINK_SCRAMBLING_DISABLE)) {
3380                 DRM_ERROR("failed to enable link training\n");
3381                 return;
3382         }
3383
3384         voltage = 0xff;
3385         voltage_tries = 0;
3386         loop_tries = 0;
3387         for (;;) {
3388                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3389
3390                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3391                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3392                         DRM_ERROR("failed to get link status\n");
3393                         break;
3394                 }
3395
3396                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3397                         DRM_DEBUG_KMS("clock recovery OK\n");
3398                         break;
3399                 }
3400
3401                 /* Check to see if we've tried the max voltage */
3402                 for (i = 0; i < intel_dp->lane_count; i++)
3403                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3404                                 break;
3405                 if (i == intel_dp->lane_count) {
3406                         ++loop_tries;
3407                         if (loop_tries == 5) {
3408                                 DRM_ERROR("too many full retries, give up\n");
3409                                 break;
3410                         }
3411                         intel_dp_reset_link_train(intel_dp, &DP,
3412                                                   DP_TRAINING_PATTERN_1 |
3413                                                   DP_LINK_SCRAMBLING_DISABLE);
3414                         voltage_tries = 0;
3415                         continue;
3416                 }
3417
3418                 /* Check to see if we've tried the same voltage 5 times */
3419                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3420                         ++voltage_tries;
3421                         if (voltage_tries == 5) {
3422                                 DRM_ERROR("too many voltage retries, give up\n");
3423                                 break;
3424                         }
3425                 } else
3426                         voltage_tries = 0;
3427                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3428
3429                 /* Update training set as requested by target */
3430                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3431                         DRM_ERROR("failed to update link training\n");
3432                         break;
3433                 }
3434         }
3435
3436         intel_dp->DP = DP;
3437 }
3438
3439 void
3440 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3441 {
3442         bool channel_eq = false;
3443         int tries, cr_tries;
3444         uint32_t DP = intel_dp->DP;
3445         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3446
3447         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3448         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3449                 training_pattern = DP_TRAINING_PATTERN_3;
3450
3451         /* channel equalization */
3452         if (!intel_dp_set_link_train(intel_dp, &DP,
3453                                      training_pattern |
3454                                      DP_LINK_SCRAMBLING_DISABLE)) {
3455                 DRM_ERROR("failed to start channel equalization\n");
3456                 return;
3457         }
3458
3459         tries = 0;
3460         cr_tries = 0;
3461         channel_eq = false;
3462         for (;;) {
3463                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3464
3465                 if (cr_tries > 5) {
3466                         DRM_ERROR("failed to train DP, aborting\n");
3467                         break;
3468                 }
3469
3470                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3471                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3472                         DRM_ERROR("failed to get link status\n");
3473                         break;
3474                 }
3475
3476                 /* Make sure clock is still ok */
3477                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3478                         intel_dp_start_link_train(intel_dp);
3479                         intel_dp_set_link_train(intel_dp, &DP,
3480                                                 training_pattern |
3481                                                 DP_LINK_SCRAMBLING_DISABLE);
3482                         cr_tries++;
3483                         continue;
3484                 }
3485
3486                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3487                         channel_eq = true;
3488                         break;
3489                 }
3490
3491                 /* Try 5 times, then try clock recovery if that fails */
3492                 if (tries > 5) {
3493                         intel_dp_start_link_train(intel_dp);
3494                         intel_dp_set_link_train(intel_dp, &DP,
3495                                                 training_pattern |
3496                                                 DP_LINK_SCRAMBLING_DISABLE);
3497                         tries = 0;
3498                         cr_tries++;
3499                         continue;
3500                 }
3501
3502                 /* Update training set as requested by target */
3503                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3504                         DRM_ERROR("failed to update link training\n");
3505                         break;
3506                 }
3507                 ++tries;
3508         }
3509
3510         intel_dp_set_idle_link_train(intel_dp);
3511
3512         intel_dp->DP = DP;
3513
3514         if (channel_eq)
3515                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3516
3517 }
3518
3519 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3520 {
3521         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3522                                 DP_TRAINING_PATTERN_DISABLE);
3523 }
3524
3525 static void
3526 intel_dp_link_down(struct intel_dp *intel_dp)
3527 {
3528         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3529         enum port port = intel_dig_port->port;
3530         struct drm_device *dev = intel_dig_port->base.base.dev;
3531         struct drm_i915_private *dev_priv = dev->dev_private;
3532         uint32_t DP = intel_dp->DP;
3533
3534         if (WARN_ON(HAS_DDI(dev)))
3535                 return;
3536
3537         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3538                 return;
3539
3540         DRM_DEBUG_KMS("\n");
3541
3542         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3543                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3544                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3545         } else {
3546                 if (IS_CHERRYVIEW(dev))
3547                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3548                 else
3549                         DP &= ~DP_LINK_TRAIN_MASK;
3550                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3551         }
3552         POSTING_READ(intel_dp->output_reg);
3553
3554         if (HAS_PCH_IBX(dev) &&
3555             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3556                 /* Hardware workaround: leaving our transcoder select
3557                  * set to transcoder B while it's off will prevent the
3558                  * corresponding HDMI output on transcoder A.
3559                  *
3560                  * Combine this with another hardware workaround:
3561                  * transcoder select bit can only be cleared while the
3562                  * port is enabled.
3563                  */
3564                 DP &= ~DP_PIPEB_SELECT;
3565                 I915_WRITE(intel_dp->output_reg, DP);
3566                 POSTING_READ(intel_dp->output_reg);
3567         }
3568
3569         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3570         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3571         POSTING_READ(intel_dp->output_reg);
3572         msleep(intel_dp->panel_power_down_delay);
3573 }
3574
3575 static bool
3576 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3577 {
3578         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3579         struct drm_device *dev = dig_port->base.base.dev;
3580         struct drm_i915_private *dev_priv = dev->dev_private;
3581
3582         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3583                                     sizeof(intel_dp->dpcd)) < 0)
3584                 return false; /* aux transfer failed */
3585
3586         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3587
3588         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3589                 return false; /* DPCD not present */
3590
3591         /* Check if the panel supports PSR */
3592         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3593         if (is_edp(intel_dp)) {
3594                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3595                                         intel_dp->psr_dpcd,
3596                                         sizeof(intel_dp->psr_dpcd));
3597                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3598                         dev_priv->psr.sink_support = true;
3599                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3600                 }
3601         }
3602
3603         /* Training Pattern 3 support, both source and sink */
3604         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3605             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3606             (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
3607                 intel_dp->use_tps3 = true;
3608                 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3609         } else
3610                 intel_dp->use_tps3 = false;
3611
3612         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3613               DP_DWN_STRM_PORT_PRESENT))
3614                 return true; /* native DP sink */
3615
3616         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3617                 return true; /* no per-port downstream info */
3618
3619         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3620                                     intel_dp->downstream_ports,
3621                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3622                 return false; /* downstream port status fetch failed */
3623
3624         return true;
3625 }
3626
3627 static void
3628 intel_dp_probe_oui(struct intel_dp *intel_dp)
3629 {
3630         u8 buf[3];
3631
3632         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3633                 return;
3634
3635         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3636                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3637                               buf[0], buf[1], buf[2]);
3638
3639         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3640                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3641                               buf[0], buf[1], buf[2]);
3642 }
3643
3644 static bool
3645 intel_dp_probe_mst(struct intel_dp *intel_dp)
3646 {
3647         u8 buf[1];
3648
3649         if (!intel_dp->can_mst)
3650                 return false;
3651
3652         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3653                 return false;
3654
3655         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3656                 if (buf[0] & DP_MST_CAP) {
3657                         DRM_DEBUG_KMS("Sink is MST capable\n");
3658                         intel_dp->is_mst = true;
3659                 } else {
3660                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3661                         intel_dp->is_mst = false;
3662                 }
3663         }
3664
3665         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3666         return intel_dp->is_mst;
3667 }
3668
3669 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3670 {
3671         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3672         struct drm_device *dev = intel_dig_port->base.base.dev;
3673         struct intel_crtc *intel_crtc =
3674                 to_intel_crtc(intel_dig_port->base.base.crtc);
3675         u8 buf;
3676         int test_crc_count;
3677         int attempts = 6;
3678
3679         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3680                 return -EIO;
3681
3682         if (!(buf & DP_TEST_CRC_SUPPORTED))
3683                 return -ENOTTY;
3684
3685         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3686                 return -EIO;
3687
3688         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3689                                 buf | DP_TEST_SINK_START) < 0)
3690                 return -EIO;
3691
3692         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3693                 return -EIO;
3694         test_crc_count = buf & DP_TEST_COUNT_MASK;
3695
3696         do {
3697                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3698                                       DP_TEST_SINK_MISC, &buf) < 0)
3699                         return -EIO;
3700                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3701         } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3702
3703         if (attempts == 0) {
3704                 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3705                 return -ETIMEDOUT;
3706         }
3707
3708         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3709                 return -EIO;
3710
3711         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3712                 return -EIO;
3713         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3714                                buf & ~DP_TEST_SINK_START) < 0)
3715                 return -EIO;
3716
3717         return 0;
3718 }
3719
3720 static bool
3721 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3722 {
3723         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3724                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3725                                        sink_irq_vector, 1) == 1;
3726 }
3727
3728 static bool
3729 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3730 {
3731         int ret;
3732
3733         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3734                                              DP_SINK_COUNT_ESI,
3735                                              sink_irq_vector, 14);
3736         if (ret != 14)
3737                 return false;
3738
3739         return true;
3740 }
3741
3742 static void
3743 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3744 {
3745         /* NAK by default */
3746         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3747 }
3748
3749 static int
3750 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3751 {
3752         bool bret;
3753
3754         if (intel_dp->is_mst) {
3755                 u8 esi[16] = { 0 };
3756                 int ret = 0;
3757                 int retry;
3758                 bool handled;
3759                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3760 go_again:
3761                 if (bret == true) {
3762
3763                         /* check link status - esi[10] = 0x200c */
3764                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3765                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3766                                 intel_dp_start_link_train(intel_dp);
3767                                 intel_dp_complete_link_train(intel_dp);
3768                                 intel_dp_stop_link_train(intel_dp);
3769                         }
3770
3771                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
3772                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3773
3774                         if (handled) {
3775                                 for (retry = 0; retry < 3; retry++) {
3776                                         int wret;
3777                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3778                                                                  DP_SINK_COUNT_ESI+1,
3779                                                                  &esi[1], 3);
3780                                         if (wret == 3) {
3781                                                 break;
3782                                         }
3783                                 }
3784
3785                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3786                                 if (bret == true) {
3787                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3788                                         goto go_again;
3789                                 }
3790                         } else
3791                                 ret = 0;
3792
3793                         return ret;
3794                 } else {
3795                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3796                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3797                         intel_dp->is_mst = false;
3798                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3799                         /* send a hotplug event */
3800                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3801                 }
3802         }
3803         return -EINVAL;
3804 }
3805
3806 /*
3807  * According to DP spec
3808  * 5.1.2:
3809  *  1. Read DPCD
3810  *  2. Configure link according to Receiver Capabilities
3811  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3812  *  4. Check link status on receipt of hot-plug interrupt
3813  */
3814 static void
3815 intel_dp_check_link_status(struct intel_dp *intel_dp)
3816 {
3817         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3818         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3819         u8 sink_irq_vector;
3820         u8 link_status[DP_LINK_STATUS_SIZE];
3821
3822         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3823
3824         if (!intel_encoder->connectors_active)
3825                 return;
3826
3827         if (WARN_ON(!intel_encoder->base.crtc))
3828                 return;
3829
3830         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3831                 return;
3832
3833         /* Try to read receiver status if the link appears to be up */
3834         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3835                 return;
3836         }
3837
3838         /* Now read the DPCD to see if it's actually running */
3839         if (!intel_dp_get_dpcd(intel_dp)) {
3840                 return;
3841         }
3842
3843         /* Try to read the source of the interrupt */
3844         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3845             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3846                 /* Clear interrupt source */
3847                 drm_dp_dpcd_writeb(&intel_dp->aux,
3848                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3849                                    sink_irq_vector);
3850
3851                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3852                         intel_dp_handle_test_request(intel_dp);
3853                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3854                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3855         }
3856
3857         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3858                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3859                               intel_encoder->base.name);
3860                 intel_dp_start_link_train(intel_dp);
3861                 intel_dp_complete_link_train(intel_dp);
3862                 intel_dp_stop_link_train(intel_dp);
3863         }
3864 }
3865
3866 /* XXX this is probably wrong for multiple downstream ports */
3867 static enum drm_connector_status
3868 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3869 {
3870         uint8_t *dpcd = intel_dp->dpcd;
3871         uint8_t type;
3872
3873         if (!intel_dp_get_dpcd(intel_dp))
3874                 return connector_status_disconnected;
3875
3876         /* if there's no downstream port, we're done */
3877         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3878                 return connector_status_connected;
3879
3880         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3881         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3882             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3883                 uint8_t reg;
3884
3885                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3886                                             &reg, 1) < 0)
3887                         return connector_status_unknown;
3888
3889                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3890                                               : connector_status_disconnected;
3891         }
3892
3893         /* If no HPD, poke DDC gently */
3894         if (drm_probe_ddc(&intel_dp->aux.ddc))
3895                 return connector_status_connected;
3896
3897         /* Well we tried, say unknown for unreliable port types */
3898         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3899                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3900                 if (type == DP_DS_PORT_TYPE_VGA ||
3901                     type == DP_DS_PORT_TYPE_NON_EDID)
3902                         return connector_status_unknown;
3903         } else {
3904                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3905                         DP_DWN_STRM_PORT_TYPE_MASK;
3906                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3907                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3908                         return connector_status_unknown;
3909         }
3910
3911         /* Anything else is out of spec, warn and ignore */
3912         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3913         return connector_status_disconnected;
3914 }
3915
3916 static enum drm_connector_status
3917 edp_detect(struct intel_dp *intel_dp)
3918 {
3919         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3920         enum drm_connector_status status;
3921
3922         status = intel_panel_detect(dev);
3923         if (status == connector_status_unknown)
3924                 status = connector_status_connected;
3925
3926         return status;
3927 }
3928
3929 static enum drm_connector_status
3930 ironlake_dp_detect(struct intel_dp *intel_dp)
3931 {
3932         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3933         struct drm_i915_private *dev_priv = dev->dev_private;
3934         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3935
3936         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3937                 return connector_status_disconnected;
3938
3939         return intel_dp_detect_dpcd(intel_dp);
3940 }
3941
3942 static int g4x_digital_port_connected(struct drm_device *dev,
3943                                        struct intel_digital_port *intel_dig_port)
3944 {
3945         struct drm_i915_private *dev_priv = dev->dev_private;
3946         uint32_t bit;
3947
3948         if (IS_VALLEYVIEW(dev)) {
3949                 switch (intel_dig_port->port) {
3950                 case PORT_B:
3951                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3952                         break;
3953                 case PORT_C:
3954                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3955                         break;
3956                 case PORT_D:
3957                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3958                         break;
3959                 default:
3960                         return -EINVAL;
3961                 }
3962         } else {
3963                 switch (intel_dig_port->port) {
3964                 case PORT_B:
3965                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3966                         break;
3967                 case PORT_C:
3968                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3969                         break;
3970                 case PORT_D:
3971                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3972                         break;
3973                 default:
3974                         return -EINVAL;
3975                 }
3976         }
3977
3978         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3979                 return 0;
3980         return 1;
3981 }
3982
3983 static enum drm_connector_status
3984 g4x_dp_detect(struct intel_dp *intel_dp)
3985 {
3986         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3987         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3988         int ret;
3989
3990         /* Can't disconnect eDP, but you can close the lid... */
3991         if (is_edp(intel_dp)) {
3992                 enum drm_connector_status status;
3993
3994                 status = intel_panel_detect(dev);
3995                 if (status == connector_status_unknown)
3996                         status = connector_status_connected;
3997                 return status;
3998         }
3999
4000         ret = g4x_digital_port_connected(dev, intel_dig_port);
4001         if (ret == -EINVAL)
4002                 return connector_status_unknown;
4003         else if (ret == 0)
4004                 return connector_status_disconnected;
4005
4006         return intel_dp_detect_dpcd(intel_dp);
4007 }
4008
4009 static struct edid *
4010 intel_dp_get_edid(struct intel_dp *intel_dp)
4011 {
4012         struct intel_connector *intel_connector = intel_dp->attached_connector;
4013
4014         /* use cached edid if we have one */
4015         if (intel_connector->edid) {
4016                 /* invalid edid */
4017                 if (IS_ERR(intel_connector->edid))
4018                         return NULL;
4019
4020                 return drm_edid_duplicate(intel_connector->edid);
4021         } else
4022                 return drm_get_edid(&intel_connector->base,
4023                                     &intel_dp->aux.ddc);
4024 }
4025
4026 static void
4027 intel_dp_set_edid(struct intel_dp *intel_dp)
4028 {
4029         struct intel_connector *intel_connector = intel_dp->attached_connector;
4030         struct edid *edid;
4031
4032         edid = intel_dp_get_edid(intel_dp);
4033         intel_connector->detect_edid = edid;
4034
4035         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4036                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4037         else
4038                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4039 }
4040
4041 static void
4042 intel_dp_unset_edid(struct intel_dp *intel_dp)
4043 {
4044         struct intel_connector *intel_connector = intel_dp->attached_connector;
4045
4046         kfree(intel_connector->detect_edid);
4047         intel_connector->detect_edid = NULL;
4048
4049         intel_dp->has_audio = false;
4050 }
4051
4052 static enum intel_display_power_domain
4053 intel_dp_power_get(struct intel_dp *dp)
4054 {
4055         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4056         enum intel_display_power_domain power_domain;
4057
4058         power_domain = intel_display_port_power_domain(encoder);
4059         intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4060
4061         return power_domain;
4062 }
4063
4064 static void
4065 intel_dp_power_put(struct intel_dp *dp,
4066                    enum intel_display_power_domain power_domain)
4067 {
4068         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4069         intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4070 }
4071
4072 static enum drm_connector_status
4073 intel_dp_detect(struct drm_connector *connector, bool force)
4074 {
4075         struct intel_dp *intel_dp = intel_attached_dp(connector);
4076         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4077         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4078         struct drm_device *dev = connector->dev;
4079         enum drm_connector_status status;
4080         enum intel_display_power_domain power_domain;
4081         bool ret;
4082
4083         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4084                       connector->base.id, connector->name);
4085         intel_dp_unset_edid(intel_dp);
4086
4087         if (intel_dp->is_mst) {
4088                 /* MST devices are disconnected from a monitor POV */
4089                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4090                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4091                 return connector_status_disconnected;
4092         }
4093
4094         power_domain = intel_dp_power_get(intel_dp);
4095
4096         /* Can't disconnect eDP, but you can close the lid... */
4097         if (is_edp(intel_dp))
4098                 status = edp_detect(intel_dp);
4099         else if (HAS_PCH_SPLIT(dev))
4100                 status = ironlake_dp_detect(intel_dp);
4101         else
4102                 status = g4x_dp_detect(intel_dp);
4103         if (status != connector_status_connected)
4104                 goto out;
4105
4106         intel_dp_probe_oui(intel_dp);
4107
4108         ret = intel_dp_probe_mst(intel_dp);
4109         if (ret) {
4110                 /* if we are in MST mode then this connector
4111                    won't appear connected or have anything with EDID on it */
4112                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4113                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4114                 status = connector_status_disconnected;
4115                 goto out;
4116         }
4117
4118         intel_dp_set_edid(intel_dp);
4119
4120         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4121                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4122         status = connector_status_connected;
4123
4124 out:
4125         intel_dp_power_put(intel_dp, power_domain);
4126         return status;
4127 }
4128
4129 static void
4130 intel_dp_force(struct drm_connector *connector)
4131 {
4132         struct intel_dp *intel_dp = intel_attached_dp(connector);
4133         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4134         enum intel_display_power_domain power_domain;
4135
4136         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4137                       connector->base.id, connector->name);
4138         intel_dp_unset_edid(intel_dp);
4139
4140         if (connector->status != connector_status_connected)
4141                 return;
4142
4143         power_domain = intel_dp_power_get(intel_dp);
4144
4145         intel_dp_set_edid(intel_dp);
4146
4147         intel_dp_power_put(intel_dp, power_domain);
4148
4149         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4150                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4151 }
4152
4153 static int intel_dp_get_modes(struct drm_connector *connector)
4154 {
4155         struct intel_connector *intel_connector = to_intel_connector(connector);
4156         struct edid *edid;
4157
4158         edid = intel_connector->detect_edid;
4159         if (edid) {
4160                 int ret = intel_connector_update_modes(connector, edid);
4161                 if (ret)
4162                         return ret;
4163         }
4164
4165         /* if eDP has no EDID, fall back to fixed mode */
4166         if (is_edp(intel_attached_dp(connector)) &&
4167             intel_connector->panel.fixed_mode) {
4168                 struct drm_display_mode *mode;
4169
4170                 mode = drm_mode_duplicate(connector->dev,
4171                                           intel_connector->panel.fixed_mode);
4172                 if (mode) {
4173                         drm_mode_probed_add(connector, mode);
4174                         return 1;
4175                 }
4176         }
4177
4178         return 0;
4179 }
4180
4181 static bool
4182 intel_dp_detect_audio(struct drm_connector *connector)
4183 {
4184         bool has_audio = false;
4185         struct edid *edid;
4186
4187         edid = to_intel_connector(connector)->detect_edid;
4188         if (edid)
4189                 has_audio = drm_detect_monitor_audio(edid);
4190
4191         return has_audio;
4192 }
4193
4194 static int
4195 intel_dp_set_property(struct drm_connector *connector,
4196                       struct drm_property *property,
4197                       uint64_t val)
4198 {
4199         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4200         struct intel_connector *intel_connector = to_intel_connector(connector);
4201         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4202         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4203         int ret;
4204
4205         ret = drm_object_property_set_value(&connector->base, property, val);
4206         if (ret)
4207                 return ret;
4208
4209         if (property == dev_priv->force_audio_property) {
4210                 int i = val;
4211                 bool has_audio;
4212
4213                 if (i == intel_dp->force_audio)
4214                         return 0;
4215
4216                 intel_dp->force_audio = i;
4217
4218                 if (i == HDMI_AUDIO_AUTO)
4219                         has_audio = intel_dp_detect_audio(connector);
4220                 else
4221                         has_audio = (i == HDMI_AUDIO_ON);
4222
4223                 if (has_audio == intel_dp->has_audio)
4224                         return 0;
4225
4226                 intel_dp->has_audio = has_audio;
4227                 goto done;
4228         }
4229
4230         if (property == dev_priv->broadcast_rgb_property) {
4231                 bool old_auto = intel_dp->color_range_auto;
4232                 uint32_t old_range = intel_dp->color_range;
4233
4234                 switch (val) {
4235                 case INTEL_BROADCAST_RGB_AUTO:
4236                         intel_dp->color_range_auto = true;
4237                         break;
4238                 case INTEL_BROADCAST_RGB_FULL:
4239                         intel_dp->color_range_auto = false;
4240                         intel_dp->color_range = 0;
4241                         break;
4242                 case INTEL_BROADCAST_RGB_LIMITED:
4243                         intel_dp->color_range_auto = false;
4244                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
4245                         break;
4246                 default:
4247                         return -EINVAL;
4248                 }
4249
4250                 if (old_auto == intel_dp->color_range_auto &&
4251                     old_range == intel_dp->color_range)
4252                         return 0;
4253
4254                 goto done;
4255         }
4256
4257         if (is_edp(intel_dp) &&
4258             property == connector->dev->mode_config.scaling_mode_property) {
4259                 if (val == DRM_MODE_SCALE_NONE) {
4260                         DRM_DEBUG_KMS("no scaling not supported\n");
4261                         return -EINVAL;
4262                 }
4263
4264                 if (intel_connector->panel.fitting_mode == val) {
4265                         /* the eDP scaling property is not changed */
4266                         return 0;
4267                 }
4268                 intel_connector->panel.fitting_mode = val;
4269
4270                 goto done;
4271         }
4272
4273         return -EINVAL;
4274
4275 done:
4276         if (intel_encoder->base.crtc)
4277                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4278
4279         return 0;
4280 }
4281
4282 static void
4283 intel_dp_connector_destroy(struct drm_connector *connector)
4284 {
4285         struct intel_connector *intel_connector = to_intel_connector(connector);
4286
4287         kfree(intel_connector->detect_edid);
4288
4289         if (!IS_ERR_OR_NULL(intel_connector->edid))
4290                 kfree(intel_connector->edid);
4291
4292         /* Can't call is_edp() since the encoder may have been destroyed
4293          * already. */
4294         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4295                 intel_panel_fini(&intel_connector->panel);
4296
4297         drm_connector_cleanup(connector);
4298         kfree(connector);
4299 }
4300
4301 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4302 {
4303         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4304         struct intel_dp *intel_dp = &intel_dig_port->dp;
4305
4306         drm_dp_aux_unregister(&intel_dp->aux);
4307         intel_dp_mst_encoder_cleanup(intel_dig_port);
4308         if (is_edp(intel_dp)) {
4309                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4310                 /*
4311                  * vdd might still be enabled do to the delayed vdd off.
4312                  * Make sure vdd is actually turned off here.
4313                  */
4314                 pps_lock(intel_dp);
4315                 edp_panel_vdd_off_sync(intel_dp);
4316                 pps_unlock(intel_dp);
4317
4318                 if (intel_dp->edp_notifier.notifier_call) {
4319                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4320                         intel_dp->edp_notifier.notifier_call = NULL;
4321                 }
4322         }
4323         drm_encoder_cleanup(encoder);
4324         kfree(intel_dig_port);
4325 }
4326
4327 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4328 {
4329         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4330
4331         if (!is_edp(intel_dp))
4332                 return;
4333
4334         /*
4335          * vdd might still be enabled do to the delayed vdd off.
4336          * Make sure vdd is actually turned off here.
4337          */
4338         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4339         pps_lock(intel_dp);
4340         edp_panel_vdd_off_sync(intel_dp);
4341         pps_unlock(intel_dp);
4342 }
4343
4344 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4345 {
4346         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4347         struct drm_device *dev = intel_dig_port->base.base.dev;
4348         struct drm_i915_private *dev_priv = dev->dev_private;
4349         enum intel_display_power_domain power_domain;
4350
4351         lockdep_assert_held(&dev_priv->pps_mutex);
4352
4353         if (!edp_have_panel_vdd(intel_dp))
4354                 return;
4355
4356         /*
4357          * The VDD bit needs a power domain reference, so if the bit is
4358          * already enabled when we boot or resume, grab this reference and
4359          * schedule a vdd off, so we don't hold on to the reference
4360          * indefinitely.
4361          */
4362         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4363         power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4364         intel_display_power_get(dev_priv, power_domain);
4365
4366         edp_panel_vdd_schedule_off(intel_dp);
4367 }
4368
4369 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4370 {
4371         struct intel_dp *intel_dp;
4372
4373         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4374                 return;
4375
4376         intel_dp = enc_to_intel_dp(encoder);
4377
4378         pps_lock(intel_dp);
4379
4380         /*
4381          * Read out the current power sequencer assignment,
4382          * in case the BIOS did something with it.
4383          */
4384         if (IS_VALLEYVIEW(encoder->dev))
4385                 vlv_initial_power_sequencer_setup(intel_dp);
4386
4387         intel_edp_panel_vdd_sanitize(intel_dp);
4388
4389         pps_unlock(intel_dp);
4390 }
4391
4392 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4393         .dpms = intel_connector_dpms,
4394         .detect = intel_dp_detect,
4395         .force = intel_dp_force,
4396         .fill_modes = drm_helper_probe_single_connector_modes,
4397         .set_property = intel_dp_set_property,
4398         .atomic_get_property = intel_connector_atomic_get_property,
4399         .destroy = intel_dp_connector_destroy,
4400         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4401 };
4402
4403 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4404         .get_modes = intel_dp_get_modes,
4405         .mode_valid = intel_dp_mode_valid,
4406         .best_encoder = intel_best_encoder,
4407 };
4408
4409 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4410         .reset = intel_dp_encoder_reset,
4411         .destroy = intel_dp_encoder_destroy,
4412 };
4413
4414 void
4415 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4416 {
4417         return;
4418 }
4419
4420 enum irqreturn
4421 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4422 {
4423         struct intel_dp *intel_dp = &intel_dig_port->dp;
4424         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4425         struct drm_device *dev = intel_dig_port->base.base.dev;
4426         struct drm_i915_private *dev_priv = dev->dev_private;
4427         enum intel_display_power_domain power_domain;
4428         enum irqreturn ret = IRQ_NONE;
4429
4430         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4431                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4432
4433         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4434                 /*
4435                  * vdd off can generate a long pulse on eDP which
4436                  * would require vdd on to handle it, and thus we
4437                  * would end up in an endless cycle of
4438                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4439                  */
4440                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4441                               port_name(intel_dig_port->port));
4442                 return IRQ_HANDLED;
4443         }
4444
4445         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4446                       port_name(intel_dig_port->port),
4447                       long_hpd ? "long" : "short");
4448
4449         power_domain = intel_display_port_power_domain(intel_encoder);
4450         intel_display_power_get(dev_priv, power_domain);
4451
4452         if (long_hpd) {
4453
4454                 if (HAS_PCH_SPLIT(dev)) {
4455                         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4456                                 goto mst_fail;
4457                 } else {
4458                         if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4459                                 goto mst_fail;
4460                 }
4461
4462                 if (!intel_dp_get_dpcd(intel_dp)) {
4463                         goto mst_fail;
4464                 }
4465
4466                 intel_dp_probe_oui(intel_dp);
4467
4468                 if (!intel_dp_probe_mst(intel_dp))
4469                         goto mst_fail;
4470
4471         } else {
4472                 if (intel_dp->is_mst) {
4473                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4474                                 goto mst_fail;
4475                 }
4476
4477                 if (!intel_dp->is_mst) {
4478                         /*
4479                          * we'll check the link status via the normal hot plug path later -
4480                          * but for short hpds we should check it now
4481                          */
4482                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4483                         intel_dp_check_link_status(intel_dp);
4484                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4485                 }
4486         }
4487
4488         ret = IRQ_HANDLED;
4489
4490         goto put_power;
4491 mst_fail:
4492         /* if we were in MST mode, and device is not there get out of MST mode */
4493         if (intel_dp->is_mst) {
4494                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4495                 intel_dp->is_mst = false;
4496                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4497         }
4498 put_power:
4499         intel_display_power_put(dev_priv, power_domain);
4500
4501         return ret;
4502 }
4503
4504 /* Return which DP Port should be selected for Transcoder DP control */
4505 int
4506 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4507 {
4508         struct drm_device *dev = crtc->dev;
4509         struct intel_encoder *intel_encoder;
4510         struct intel_dp *intel_dp;
4511
4512         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4513                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4514
4515                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4516                     intel_encoder->type == INTEL_OUTPUT_EDP)
4517                         return intel_dp->output_reg;
4518         }
4519
4520         return -1;
4521 }
4522
4523 /* check the VBT to see whether the eDP is on DP-D port */
4524 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4525 {
4526         struct drm_i915_private *dev_priv = dev->dev_private;
4527         union child_device_config *p_child;
4528         int i;
4529         static const short port_mapping[] = {
4530                 [PORT_B] = PORT_IDPB,
4531                 [PORT_C] = PORT_IDPC,
4532                 [PORT_D] = PORT_IDPD,
4533         };
4534
4535         if (port == PORT_A)
4536                 return true;
4537
4538         if (!dev_priv->vbt.child_dev_num)
4539                 return false;
4540
4541         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4542                 p_child = dev_priv->vbt.child_dev + i;
4543
4544                 if (p_child->common.dvo_port == port_mapping[port] &&
4545                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4546                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4547                         return true;
4548         }
4549         return false;
4550 }
4551
4552 void
4553 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4554 {
4555         struct intel_connector *intel_connector = to_intel_connector(connector);
4556
4557         intel_attach_force_audio_property(connector);
4558         intel_attach_broadcast_rgb_property(connector);
4559         intel_dp->color_range_auto = true;
4560
4561         if (is_edp(intel_dp)) {
4562                 drm_mode_create_scaling_mode_property(connector->dev);
4563                 drm_object_attach_property(
4564                         &connector->base,
4565                         connector->dev->mode_config.scaling_mode_property,
4566                         DRM_MODE_SCALE_ASPECT);
4567                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4568         }
4569 }
4570
4571 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4572 {
4573         intel_dp->last_power_cycle = jiffies;
4574         intel_dp->last_power_on = jiffies;
4575         intel_dp->last_backlight_off = jiffies;
4576 }
4577
4578 static void
4579 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4580                                     struct intel_dp *intel_dp)
4581 {
4582         struct drm_i915_private *dev_priv = dev->dev_private;
4583         struct edp_power_seq cur, vbt, spec,
4584                 *final = &intel_dp->pps_delays;
4585         u32 pp_on, pp_off, pp_div, pp;
4586         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4587
4588         lockdep_assert_held(&dev_priv->pps_mutex);
4589
4590         /* already initialized? */
4591         if (final->t11_t12 != 0)
4592                 return;
4593
4594         if (HAS_PCH_SPLIT(dev)) {
4595                 pp_ctrl_reg = PCH_PP_CONTROL;
4596                 pp_on_reg = PCH_PP_ON_DELAYS;
4597                 pp_off_reg = PCH_PP_OFF_DELAYS;
4598                 pp_div_reg = PCH_PP_DIVISOR;
4599         } else {
4600                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4601
4602                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4603                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4604                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4605                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4606         }
4607
4608         /* Workaround: Need to write PP_CONTROL with the unlock key as
4609          * the very first thing. */
4610         pp = ironlake_get_pp_control(intel_dp);
4611         I915_WRITE(pp_ctrl_reg, pp);
4612
4613         pp_on = I915_READ(pp_on_reg);
4614         pp_off = I915_READ(pp_off_reg);
4615         pp_div = I915_READ(pp_div_reg);
4616
4617         /* Pull timing values out of registers */
4618         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4619                 PANEL_POWER_UP_DELAY_SHIFT;
4620
4621         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4622                 PANEL_LIGHT_ON_DELAY_SHIFT;
4623
4624         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4625                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4626
4627         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4628                 PANEL_POWER_DOWN_DELAY_SHIFT;
4629
4630         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4631                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4632
4633         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4634                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4635
4636         vbt = dev_priv->vbt.edp_pps;
4637
4638         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4639          * our hw here, which are all in 100usec. */
4640         spec.t1_t3 = 210 * 10;
4641         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4642         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4643         spec.t10 = 500 * 10;
4644         /* This one is special and actually in units of 100ms, but zero
4645          * based in the hw (so we need to add 100 ms). But the sw vbt
4646          * table multiplies it with 1000 to make it in units of 100usec,
4647          * too. */
4648         spec.t11_t12 = (510 + 100) * 10;
4649
4650         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4651                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4652
4653         /* Use the max of the register settings and vbt. If both are
4654          * unset, fall back to the spec limits. */
4655 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
4656                                        spec.field : \
4657                                        max(cur.field, vbt.field))
4658         assign_final(t1_t3);
4659         assign_final(t8);
4660         assign_final(t9);
4661         assign_final(t10);
4662         assign_final(t11_t12);
4663 #undef assign_final
4664
4665 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
4666         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4667         intel_dp->backlight_on_delay = get_delay(t8);
4668         intel_dp->backlight_off_delay = get_delay(t9);
4669         intel_dp->panel_power_down_delay = get_delay(t10);
4670         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4671 #undef get_delay
4672
4673         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4674                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4675                       intel_dp->panel_power_cycle_delay);
4676
4677         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4678                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4679 }
4680
4681 static void
4682 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4683                                               struct intel_dp *intel_dp)
4684 {
4685         struct drm_i915_private *dev_priv = dev->dev_private;
4686         u32 pp_on, pp_off, pp_div, port_sel = 0;
4687         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4688         int pp_on_reg, pp_off_reg, pp_div_reg;
4689         enum port port = dp_to_dig_port(intel_dp)->port;
4690         const struct edp_power_seq *seq = &intel_dp->pps_delays;
4691
4692         lockdep_assert_held(&dev_priv->pps_mutex);
4693
4694         if (HAS_PCH_SPLIT(dev)) {
4695                 pp_on_reg = PCH_PP_ON_DELAYS;
4696                 pp_off_reg = PCH_PP_OFF_DELAYS;
4697                 pp_div_reg = PCH_PP_DIVISOR;
4698         } else {
4699                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4700
4701                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4702                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4703                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4704         }
4705
4706         /*
4707          * And finally store the new values in the power sequencer. The
4708          * backlight delays are set to 1 because we do manual waits on them. For
4709          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4710          * we'll end up waiting for the backlight off delay twice: once when we
4711          * do the manual sleep, and once when we disable the panel and wait for
4712          * the PP_STATUS bit to become zero.
4713          */
4714         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4715                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4716         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4717                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4718         /* Compute the divisor for the pp clock, simply match the Bspec
4719          * formula. */
4720         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4721         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4722                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4723
4724         /* Haswell doesn't have any port selection bits for the panel
4725          * power sequencer any more. */
4726         if (IS_VALLEYVIEW(dev)) {
4727                 port_sel = PANEL_PORT_SELECT_VLV(port);
4728         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4729                 if (port == PORT_A)
4730                         port_sel = PANEL_PORT_SELECT_DPA;
4731                 else
4732                         port_sel = PANEL_PORT_SELECT_DPD;
4733         }
4734
4735         pp_on |= port_sel;
4736
4737         I915_WRITE(pp_on_reg, pp_on);
4738         I915_WRITE(pp_off_reg, pp_off);
4739         I915_WRITE(pp_div_reg, pp_div);
4740
4741         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4742                       I915_READ(pp_on_reg),
4743                       I915_READ(pp_off_reg),
4744                       I915_READ(pp_div_reg));
4745 }
4746
4747 /**
4748  * intel_dp_set_drrs_state - program registers for RR switch to take effect
4749  * @dev: DRM device
4750  * @refresh_rate: RR to be programmed
4751  *
4752  * This function gets called when refresh rate (RR) has to be changed from
4753  * one frequency to another. Switches can be between high and low RR
4754  * supported by the panel or to any other RR based on media playback (in
4755  * this case, RR value needs to be passed from user space).
4756  *
4757  * The caller of this function needs to take a lock on dev_priv->drrs.
4758  */
4759 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4760 {
4761         struct drm_i915_private *dev_priv = dev->dev_private;
4762         struct intel_encoder *encoder;
4763         struct intel_digital_port *dig_port = NULL;
4764         struct intel_dp *intel_dp = dev_priv->drrs.dp;
4765         struct intel_crtc_state *config = NULL;
4766         struct intel_crtc *intel_crtc = NULL;
4767         u32 reg, val;
4768         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4769
4770         if (refresh_rate <= 0) {
4771                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4772                 return;
4773         }
4774
4775         if (intel_dp == NULL) {
4776                 DRM_DEBUG_KMS("DRRS not supported.\n");
4777                 return;
4778         }
4779
4780         /*
4781          * FIXME: This needs proper synchronization with psr state for some
4782          * platforms that cannot have PSR and DRRS enabled at the same time.
4783          */
4784
4785         dig_port = dp_to_dig_port(intel_dp);
4786         encoder = &dig_port->base;
4787         intel_crtc = encoder->new_crtc;
4788
4789         if (!intel_crtc) {
4790                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4791                 return;
4792         }
4793
4794         config = intel_crtc->config;
4795
4796         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4797                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4798                 return;
4799         }
4800
4801         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4802                         refresh_rate)
4803                 index = DRRS_LOW_RR;
4804
4805         if (index == dev_priv->drrs.refresh_rate_type) {
4806                 DRM_DEBUG_KMS(
4807                         "DRRS requested for previously set RR...ignoring\n");
4808                 return;
4809         }
4810
4811         if (!intel_crtc->active) {
4812                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4813                 return;
4814         }
4815
4816         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
4817                 switch (index) {
4818                 case DRRS_HIGH_RR:
4819                         intel_dp_set_m_n(intel_crtc, M1_N1);
4820                         break;
4821                 case DRRS_LOW_RR:
4822                         intel_dp_set_m_n(intel_crtc, M2_N2);
4823                         break;
4824                 case DRRS_MAX_RR:
4825                 default:
4826                         DRM_ERROR("Unsupported refreshrate type\n");
4827                 }
4828         } else if (INTEL_INFO(dev)->gen > 6) {
4829                 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
4830                 val = I915_READ(reg);
4831
4832                 if (index > DRRS_HIGH_RR) {
4833                         if (IS_VALLEYVIEW(dev))
4834                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4835                         else
4836                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4837                 } else {
4838                         if (IS_VALLEYVIEW(dev))
4839                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4840                         else
4841                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4842                 }
4843                 I915_WRITE(reg, val);
4844         }
4845
4846         dev_priv->drrs.refresh_rate_type = index;
4847
4848         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4849 }
4850
4851 /**
4852  * intel_edp_drrs_enable - init drrs struct if supported
4853  * @intel_dp: DP struct
4854  *
4855  * Initializes frontbuffer_bits and drrs.dp
4856  */
4857 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
4858 {
4859         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4860         struct drm_i915_private *dev_priv = dev->dev_private;
4861         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4862         struct drm_crtc *crtc = dig_port->base.base.crtc;
4863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4864
4865         if (!intel_crtc->config->has_drrs) {
4866                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
4867                 return;
4868         }
4869
4870         mutex_lock(&dev_priv->drrs.mutex);
4871         if (WARN_ON(dev_priv->drrs.dp)) {
4872                 DRM_ERROR("DRRS already enabled\n");
4873                 goto unlock;
4874         }
4875
4876         dev_priv->drrs.busy_frontbuffer_bits = 0;
4877
4878         dev_priv->drrs.dp = intel_dp;
4879
4880 unlock:
4881         mutex_unlock(&dev_priv->drrs.mutex);
4882 }
4883
4884 /**
4885  * intel_edp_drrs_disable - Disable DRRS
4886  * @intel_dp: DP struct
4887  *
4888  */
4889 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
4890 {
4891         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4892         struct drm_i915_private *dev_priv = dev->dev_private;
4893         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4894         struct drm_crtc *crtc = dig_port->base.base.crtc;
4895         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4896
4897         if (!intel_crtc->config->has_drrs)
4898                 return;
4899
4900         mutex_lock(&dev_priv->drrs.mutex);
4901         if (!dev_priv->drrs.dp) {
4902                 mutex_unlock(&dev_priv->drrs.mutex);
4903                 return;
4904         }
4905
4906         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
4907                 intel_dp_set_drrs_state(dev_priv->dev,
4908                         intel_dp->attached_connector->panel.
4909                         fixed_mode->vrefresh);
4910
4911         dev_priv->drrs.dp = NULL;
4912         mutex_unlock(&dev_priv->drrs.mutex);
4913
4914         cancel_delayed_work_sync(&dev_priv->drrs.work);
4915 }
4916
4917 static void intel_edp_drrs_downclock_work(struct work_struct *work)
4918 {
4919         struct drm_i915_private *dev_priv =
4920                 container_of(work, typeof(*dev_priv), drrs.work.work);
4921         struct intel_dp *intel_dp;
4922
4923         mutex_lock(&dev_priv->drrs.mutex);
4924
4925         intel_dp = dev_priv->drrs.dp;
4926
4927         if (!intel_dp)
4928                 goto unlock;
4929
4930         /*
4931          * The delayed work can race with an invalidate hence we need to
4932          * recheck.
4933          */
4934
4935         if (dev_priv->drrs.busy_frontbuffer_bits)
4936                 goto unlock;
4937
4938         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
4939                 intel_dp_set_drrs_state(dev_priv->dev,
4940                         intel_dp->attached_connector->panel.
4941                         downclock_mode->vrefresh);
4942
4943 unlock:
4944
4945         mutex_unlock(&dev_priv->drrs.mutex);
4946 }
4947
4948 /**
4949  * intel_edp_drrs_invalidate - Invalidate DRRS
4950  * @dev: DRM device
4951  * @frontbuffer_bits: frontbuffer plane tracking bits
4952  *
4953  * When there is a disturbance on screen (due to cursor movement/time
4954  * update etc), DRRS needs to be invalidated, i.e. need to switch to
4955  * high RR.
4956  *
4957  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
4958  */
4959 void intel_edp_drrs_invalidate(struct drm_device *dev,
4960                 unsigned frontbuffer_bits)
4961 {
4962         struct drm_i915_private *dev_priv = dev->dev_private;
4963         struct drm_crtc *crtc;
4964         enum pipe pipe;
4965
4966         if (!dev_priv->drrs.dp)
4967                 return;
4968
4969         mutex_lock(&dev_priv->drrs.mutex);
4970         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
4971         pipe = to_intel_crtc(crtc)->pipe;
4972
4973         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
4974                 cancel_delayed_work_sync(&dev_priv->drrs.work);
4975                 intel_dp_set_drrs_state(dev_priv->dev,
4976                                 dev_priv->drrs.dp->attached_connector->panel.
4977                                 fixed_mode->vrefresh);
4978         }
4979
4980         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
4981
4982         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
4983         mutex_unlock(&dev_priv->drrs.mutex);
4984 }
4985
4986 /**
4987  * intel_edp_drrs_flush - Flush DRRS
4988  * @dev: DRM device
4989  * @frontbuffer_bits: frontbuffer plane tracking bits
4990  *
4991  * When there is no movement on screen, DRRS work can be scheduled.
4992  * This DRRS work is responsible for setting relevant registers after a
4993  * timeout of 1 second.
4994  *
4995  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
4996  */
4997 void intel_edp_drrs_flush(struct drm_device *dev,
4998                 unsigned frontbuffer_bits)
4999 {
5000         struct drm_i915_private *dev_priv = dev->dev_private;
5001         struct drm_crtc *crtc;
5002         enum pipe pipe;
5003
5004         if (!dev_priv->drrs.dp)
5005                 return;
5006
5007         mutex_lock(&dev_priv->drrs.mutex);
5008         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5009         pipe = to_intel_crtc(crtc)->pipe;
5010         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5011
5012         cancel_delayed_work_sync(&dev_priv->drrs.work);
5013
5014         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
5015                         !dev_priv->drrs.busy_frontbuffer_bits)
5016                 schedule_delayed_work(&dev_priv->drrs.work,
5017                                 msecs_to_jiffies(1000));
5018         mutex_unlock(&dev_priv->drrs.mutex);
5019 }
5020
5021 /**
5022  * DOC: Display Refresh Rate Switching (DRRS)
5023  *
5024  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5025  * which enables swtching between low and high refresh rates,
5026  * dynamically, based on the usage scenario. This feature is applicable
5027  * for internal panels.
5028  *
5029  * Indication that the panel supports DRRS is given by the panel EDID, which
5030  * would list multiple refresh rates for one resolution.
5031  *
5032  * DRRS is of 2 types - static and seamless.
5033  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5034  * (may appear as a blink on screen) and is used in dock-undock scenario.
5035  * Seamless DRRS involves changing RR without any visual effect to the user
5036  * and can be used during normal system usage. This is done by programming
5037  * certain registers.
5038  *
5039  * Support for static/seamless DRRS may be indicated in the VBT based on
5040  * inputs from the panel spec.
5041  *
5042  * DRRS saves power by switching to low RR based on usage scenarios.
5043  *
5044  * eDP DRRS:-
5045  *        The implementation is based on frontbuffer tracking implementation.
5046  * When there is a disturbance on the screen triggered by user activity or a
5047  * periodic system activity, DRRS is disabled (RR is changed to high RR).
5048  * When there is no movement on screen, after a timeout of 1 second, a switch
5049  * to low RR is made.
5050  *        For integration with frontbuffer tracking code,
5051  * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5052  *
5053  * DRRS can be further extended to support other internal panels and also
5054  * the scenario of video playback wherein RR is set based on the rate
5055  * requested by userspace.
5056  */
5057
5058 /**
5059  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5060  * @intel_connector: eDP connector
5061  * @fixed_mode: preferred mode of panel
5062  *
5063  * This function is  called only once at driver load to initialize basic
5064  * DRRS stuff.
5065  *
5066  * Returns:
5067  * Downclock mode if panel supports it, else return NULL.
5068  * DRRS support is determined by the presence of downclock mode (apart
5069  * from VBT setting).
5070  */
5071 static struct drm_display_mode *
5072 intel_dp_drrs_init(struct intel_connector *intel_connector,
5073                 struct drm_display_mode *fixed_mode)
5074 {
5075         struct drm_connector *connector = &intel_connector->base;
5076         struct drm_device *dev = connector->dev;
5077         struct drm_i915_private *dev_priv = dev->dev_private;
5078         struct drm_display_mode *downclock_mode = NULL;
5079
5080         if (INTEL_INFO(dev)->gen <= 6) {
5081                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5082                 return NULL;
5083         }
5084
5085         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5086                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5087                 return NULL;
5088         }
5089
5090         downclock_mode = intel_find_panel_downclock
5091                                         (dev, fixed_mode, connector);
5092
5093         if (!downclock_mode) {
5094                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5095                 return NULL;
5096         }
5097
5098         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5099
5100         mutex_init(&dev_priv->drrs.mutex);
5101
5102         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5103
5104         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5105         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5106         return downclock_mode;
5107 }
5108
5109 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5110                                      struct intel_connector *intel_connector)
5111 {
5112         struct drm_connector *connector = &intel_connector->base;
5113         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5114         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5115         struct drm_device *dev = intel_encoder->base.dev;
5116         struct drm_i915_private *dev_priv = dev->dev_private;
5117         struct drm_display_mode *fixed_mode = NULL;
5118         struct drm_display_mode *downclock_mode = NULL;
5119         bool has_dpcd;
5120         struct drm_display_mode *scan;
5121         struct edid *edid;
5122         enum pipe pipe = INVALID_PIPE;
5123
5124         dev_priv->drrs.type = DRRS_NOT_SUPPORTED;
5125
5126         if (!is_edp(intel_dp))
5127                 return true;
5128
5129         pps_lock(intel_dp);
5130         intel_edp_panel_vdd_sanitize(intel_dp);
5131         pps_unlock(intel_dp);
5132
5133         /* Cache DPCD and EDID for edp. */
5134         has_dpcd = intel_dp_get_dpcd(intel_dp);
5135
5136         if (has_dpcd) {
5137                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5138                         dev_priv->no_aux_handshake =
5139                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5140                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5141         } else {
5142                 /* if this fails, presume the device is a ghost */
5143                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5144                 return false;
5145         }
5146
5147         /* We now know it's not a ghost, init power sequence regs. */
5148         pps_lock(intel_dp);
5149         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5150         pps_unlock(intel_dp);
5151
5152         mutex_lock(&dev->mode_config.mutex);
5153         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5154         if (edid) {
5155                 if (drm_add_edid_modes(connector, edid)) {
5156                         drm_mode_connector_update_edid_property(connector,
5157                                                                 edid);
5158                         drm_edid_to_eld(connector, edid);
5159                 } else {
5160                         kfree(edid);
5161                         edid = ERR_PTR(-EINVAL);
5162                 }
5163         } else {
5164                 edid = ERR_PTR(-ENOENT);
5165         }
5166         intel_connector->edid = edid;
5167
5168         /* prefer fixed mode from EDID if available */
5169         list_for_each_entry(scan, &connector->probed_modes, head) {
5170                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5171                         fixed_mode = drm_mode_duplicate(dev, scan);
5172                         downclock_mode = intel_dp_drrs_init(
5173                                                 intel_connector, fixed_mode);
5174                         break;
5175                 }
5176         }
5177
5178         /* fallback to VBT if available for eDP */
5179         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5180                 fixed_mode = drm_mode_duplicate(dev,
5181                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5182                 if (fixed_mode)
5183                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5184         }
5185         mutex_unlock(&dev->mode_config.mutex);
5186
5187         if (IS_VALLEYVIEW(dev)) {
5188                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5189                 register_reboot_notifier(&intel_dp->edp_notifier);
5190
5191                 /*
5192                  * Figure out the current pipe for the initial backlight setup.
5193                  * If the current pipe isn't valid, try the PPS pipe, and if that
5194                  * fails just assume pipe A.
5195                  */
5196                 if (IS_CHERRYVIEW(dev))
5197                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5198                 else
5199                         pipe = PORT_TO_PIPE(intel_dp->DP);
5200
5201                 if (pipe != PIPE_A && pipe != PIPE_B)
5202                         pipe = intel_dp->pps_pipe;
5203
5204                 if (pipe != PIPE_A && pipe != PIPE_B)
5205                         pipe = PIPE_A;
5206
5207                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5208                               pipe_name(pipe));
5209         }
5210
5211         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5212         intel_connector->panel.backlight_power = intel_edp_backlight_power;
5213         intel_panel_setup_backlight(connector, pipe);
5214
5215         return true;
5216 }
5217
5218 bool
5219 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5220                         struct intel_connector *intel_connector)
5221 {
5222         struct drm_connector *connector = &intel_connector->base;
5223         struct intel_dp *intel_dp = &intel_dig_port->dp;
5224         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5225         struct drm_device *dev = intel_encoder->base.dev;
5226         struct drm_i915_private *dev_priv = dev->dev_private;
5227         enum port port = intel_dig_port->port;
5228         int type;
5229
5230         intel_dp->pps_pipe = INVALID_PIPE;
5231
5232         /* intel_dp vfuncs */
5233         if (INTEL_INFO(dev)->gen >= 9)
5234                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5235         else if (IS_VALLEYVIEW(dev))
5236                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5237         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5238                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5239         else if (HAS_PCH_SPLIT(dev))
5240                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5241         else
5242                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5243
5244         if (INTEL_INFO(dev)->gen >= 9)
5245                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5246         else
5247                 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5248
5249         /* Preserve the current hw state. */
5250         intel_dp->DP = I915_READ(intel_dp->output_reg);
5251         intel_dp->attached_connector = intel_connector;
5252
5253         if (intel_dp_is_edp(dev, port))
5254                 type = DRM_MODE_CONNECTOR_eDP;
5255         else
5256                 type = DRM_MODE_CONNECTOR_DisplayPort;
5257
5258         /*
5259          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5260          * for DP the encoder type can be set by the caller to
5261          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5262          */
5263         if (type == DRM_MODE_CONNECTOR_eDP)
5264                 intel_encoder->type = INTEL_OUTPUT_EDP;
5265
5266         /* eDP only on port B and/or C on vlv/chv */
5267         if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5268                     port != PORT_B && port != PORT_C))
5269                 return false;
5270
5271         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5272                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5273                         port_name(port));
5274
5275         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5276         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5277
5278         connector->interlace_allowed = true;
5279         connector->doublescan_allowed = 0;
5280
5281         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5282                           edp_panel_vdd_work);
5283
5284         intel_connector_attach_encoder(intel_connector, intel_encoder);
5285         drm_connector_register(connector);
5286
5287         if (HAS_DDI(dev))
5288                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5289         else
5290                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5291         intel_connector->unregister = intel_dp_connector_unregister;
5292
5293         /* Set up the hotplug pin. */
5294         switch (port) {
5295         case PORT_A:
5296                 intel_encoder->hpd_pin = HPD_PORT_A;
5297                 break;
5298         case PORT_B:
5299                 intel_encoder->hpd_pin = HPD_PORT_B;
5300                 break;
5301         case PORT_C:
5302                 intel_encoder->hpd_pin = HPD_PORT_C;
5303                 break;
5304         case PORT_D:
5305                 intel_encoder->hpd_pin = HPD_PORT_D;
5306                 break;
5307         default:
5308                 BUG();
5309         }
5310
5311         if (is_edp(intel_dp)) {
5312                 pps_lock(intel_dp);
5313                 intel_dp_init_panel_power_timestamps(intel_dp);
5314                 if (IS_VALLEYVIEW(dev))
5315                         vlv_initial_power_sequencer_setup(intel_dp);
5316                 else
5317                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5318                 pps_unlock(intel_dp);
5319         }
5320
5321         intel_dp_aux_init(intel_dp, intel_connector);
5322
5323         /* init MST on ports that can support it */
5324         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
5325                 if (port == PORT_B || port == PORT_C || port == PORT_D) {
5326                         intel_dp_mst_encoder_init(intel_dig_port,
5327                                                   intel_connector->base.base.id);
5328                 }
5329         }
5330
5331         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5332                 drm_dp_aux_unregister(&intel_dp->aux);
5333                 if (is_edp(intel_dp)) {
5334                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5335                         /*
5336                          * vdd might still be enabled do to the delayed vdd off.
5337                          * Make sure vdd is actually turned off here.
5338                          */
5339                         pps_lock(intel_dp);
5340                         edp_panel_vdd_off_sync(intel_dp);
5341                         pps_unlock(intel_dp);
5342                 }
5343                 drm_connector_unregister(connector);
5344                 drm_connector_cleanup(connector);
5345                 return false;
5346         }
5347
5348         intel_dp_add_properties(intel_dp, connector);
5349
5350         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5351          * 0xd.  Failure to do so will result in spurious interrupts being
5352          * generated on the port when a cable is not attached.
5353          */
5354         if (IS_G4X(dev) && !IS_GM45(dev)) {
5355                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5356                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5357         }
5358
5359         return true;
5360 }
5361
5362 void
5363 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5364 {
5365         struct drm_i915_private *dev_priv = dev->dev_private;
5366         struct intel_digital_port *intel_dig_port;
5367         struct intel_encoder *intel_encoder;
5368         struct drm_encoder *encoder;
5369         struct intel_connector *intel_connector;
5370
5371         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5372         if (!intel_dig_port)
5373                 return;
5374
5375         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
5376         if (!intel_connector) {
5377                 kfree(intel_dig_port);
5378                 return;
5379         }
5380
5381         intel_encoder = &intel_dig_port->base;
5382         encoder = &intel_encoder->base;
5383
5384         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5385                          DRM_MODE_ENCODER_TMDS);
5386
5387         intel_encoder->compute_config = intel_dp_compute_config;
5388         intel_encoder->disable = intel_disable_dp;
5389         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5390         intel_encoder->get_config = intel_dp_get_config;
5391         intel_encoder->suspend = intel_dp_encoder_suspend;
5392         if (IS_CHERRYVIEW(dev)) {
5393                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5394                 intel_encoder->pre_enable = chv_pre_enable_dp;
5395                 intel_encoder->enable = vlv_enable_dp;
5396                 intel_encoder->post_disable = chv_post_disable_dp;
5397         } else if (IS_VALLEYVIEW(dev)) {
5398                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5399                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5400                 intel_encoder->enable = vlv_enable_dp;
5401                 intel_encoder->post_disable = vlv_post_disable_dp;
5402         } else {
5403                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5404                 intel_encoder->enable = g4x_enable_dp;
5405                 if (INTEL_INFO(dev)->gen >= 5)
5406                         intel_encoder->post_disable = ilk_post_disable_dp;
5407         }
5408
5409         intel_dig_port->port = port;
5410         intel_dig_port->dp.output_reg = output_reg;
5411
5412         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5413         if (IS_CHERRYVIEW(dev)) {
5414                 if (port == PORT_D)
5415                         intel_encoder->crtc_mask = 1 << 2;
5416                 else
5417                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5418         } else {
5419                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5420         }
5421         intel_encoder->cloneable = 0;
5422         intel_encoder->hot_plug = intel_dp_hot_plug;
5423
5424         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5425         dev_priv->hpd_irq_port[port] = intel_dig_port;
5426
5427         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5428                 drm_encoder_cleanup(encoder);
5429                 kfree(intel_dig_port);
5430                 kfree(intel_connector);
5431         }
5432 }
5433
5434 void intel_dp_mst_suspend(struct drm_device *dev)
5435 {
5436         struct drm_i915_private *dev_priv = dev->dev_private;
5437         int i;
5438
5439         /* disable MST */
5440         for (i = 0; i < I915_MAX_PORTS; i++) {
5441                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5442                 if (!intel_dig_port)
5443                         continue;
5444
5445                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5446                         if (!intel_dig_port->dp.can_mst)
5447                                 continue;
5448                         if (intel_dig_port->dp.is_mst)
5449                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5450                 }
5451         }
5452 }
5453
5454 void intel_dp_mst_resume(struct drm_device *dev)
5455 {
5456         struct drm_i915_private *dev_priv = dev->dev_private;
5457         int i;
5458
5459         for (i = 0; i < I915_MAX_PORTS; i++) {
5460                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5461                 if (!intel_dig_port)
5462                         continue;
5463                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5464                         int ret;
5465
5466                         if (!intel_dig_port->dp.can_mst)
5467                                 continue;
5468
5469                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5470                         if (ret != 0) {
5471                                 intel_dp_check_mst_status(&intel_dig_port->dp);
5472                         }
5473                 }
5474         }
5475 }