drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         int preferred_bpp;
 127 };
 128
 129 struct intel_encoder {
 130         struct drm_encoder base;
 131
 132         enum intel_output_type type;
 133         unsigned int cloneable;
 134         void (*hot_plug)(struct intel_encoder *);
 135         bool (*compute_config)(struct intel_encoder *,
 136                                struct intel_crtc_state *);
 137         void (*pre_pll_enable)(struct intel_encoder *);
 138         void (*pre_enable)(struct intel_encoder *);
 139         void (*enable)(struct intel_encoder *);
 140         void (*mode_set)(struct intel_encoder *intel_encoder);
 141         void (*disable)(struct intel_encoder *);
 142         void (*post_disable)(struct intel_encoder *);
 143         void (*post_pll_disable)(struct intel_encoder *);
 144         /* Read out the current hw state of this connector, returning true if
 145          * the encoder is active. If the encoder is enabled it also set the pipe
 146          * it is connected to in the pipe parameter. */
 147         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 148         /* Reconstructs the equivalent mode flags for the current hardware
 149          * state. This must be called _after_ display->get_pipe_config has
 150          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 151          * be set correctly before calling this function. */
 152         void (*get_config)(struct intel_encoder *,
 153                            struct intel_crtc_state *pipe_config);
 154         /*
 155          * Called during system suspend after all pending requests for the
 156          * encoder are flushed (for example for DP AUX transactions) and
 157          * device interrupts are disabled.
 158          */
 159         void (*suspend)(struct intel_encoder *);
 160         int crtc_mask;
 161         enum hpd_pin hpd_pin;
 162 };
 163
 164 struct intel_panel {
 165         struct drm_display_mode *fixed_mode;
 166         struct drm_display_mode *downclock_mode;
 167         int fitting_mode;
 168
 169         /* backlight */
 170         struct {
 171                 bool present;
 172                 u32 level;
 173                 u32 min;
 174                 u32 max;
 175                 bool enabled;
 176                 bool combination_mode;  /* gen 2/4 only */
 177                 bool active_low_pwm;
 178
 179                 /* PWM chip */
 180                 bool util_pin_active_low;       /* bxt+ */
 181                 u8 controller;          /* bxt+ only */
 182                 struct pwm_device *pwm;
 183
 184                 struct backlight_device *device;
 185
 186                 /* Connector and platform specific backlight functions */
 187                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 188                 uint32_t (*get)(struct intel_connector *connector);
 189                 void (*set)(struct intel_connector *connector, uint32_t level);
 190                 void (*disable)(struct intel_connector *connector);
 191                 void (*enable)(struct intel_connector *connector);
 192                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 193                                       uint32_t hz);
 194                 void (*power)(struct intel_connector *, bool enable);
 195         } backlight;
 196 };
 197
 198 struct intel_connector {
 199         struct drm_connector base;
 200         /*
 201          * The fixed encoder this connector is connected to.
 202          */
 203         struct intel_encoder *encoder;
 204
 205         /* Reads out the current hw, returning true if the connector is enabled
 206          * and active (i.e. dpms ON state). */
 207         bool (*get_hw_state)(struct intel_connector *);
 208
 209         /*
 210          * Removes all interfaces through which the connector is accessible
 211          * - like sysfs, debugfs entries -, so that no new operations can be
 212          * started on the connector. Also makes sure all currently pending
 213          * operations finish before returing.
 214          */
 215         void (*unregister)(struct intel_connector *);
 216
 217         /* Panel info for eDP and LVDS */
 218         struct intel_panel panel;
 219
 220         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 221         struct edid *edid;
 222         struct edid *detect_edid;
 223
 224         /* since POLL and HPD connectors may use the same HPD line keep the native
 225            state of connector->polled in case hotplug storm detection changes it */
 226         u8 polled;
 227
 228         void *port; /* store this opaque as its illegal to dereference it */
 229
 230         struct intel_dp *mst_port;
 231 };
 232
 233 typedef struct dpll {
 234         /* given values */
 235         int n;
 236         int m1, m2;
 237         int p1, p2;
 238         /* derived values */
 239         int     dot;
 240         int     vco;
 241         int     m;
 242         int     p;
 243 } intel_clock_t;
 244
 245 struct intel_atomic_state {
 246         struct drm_atomic_state base;
 247
 248         unsigned int cdclk;
 249
 250         /*
 251          * Calculated device cdclk, can be different from cdclk
 252          * only when all crtc's are DPMS off.
 253          */
 254         unsigned int dev_cdclk;
 255
 256         bool dpll_set, modeset;
 257
 258         unsigned int active_crtcs;
 259         unsigned int min_pixclk[I915_MAX_PIPES];
 260
 261         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 262         struct intel_wm_config wm_config;
 263 };
 264
 265 struct intel_plane_state {
 266         struct drm_plane_state base;
 267         struct drm_rect src;
 268         struct drm_rect dst;
 269         struct drm_rect clip;
 270         bool visible;
 271
 272         /*
 273          * scaler_id
 274          *    = -1 : not using a scaler
 275          *    >=  0 : using a scalers
 276          *
 277          * plane requiring a scaler:
 278          *   - During check_plane, its bit is set in
 279          *     crtc_state->scaler_state.scaler_users by calling helper function
 280          *     update_scaler_plane.
 281          *   - scaler_id indicates the scaler it got assigned.
 282          *
 283          * plane doesn't require a scaler:
 284          *   - this can happen when scaling is no more required or plane simply
 285          *     got disabled.
 286          *   - During check_plane, corresponding bit is reset in
 287          *     crtc_state->scaler_state.scaler_users by calling helper function
 288          *     update_scaler_plane.
 289          */
 290         int scaler_id;
 291
 292         struct drm_intel_sprite_colorkey ckey;
 293
 294         /* async flip related structures */
 295         struct drm_i915_gem_request *wait_req;
 296 };
 297
 298 struct intel_initial_plane_config {
 299         struct intel_framebuffer *fb;
 300         unsigned int tiling;
 301         int size;
 302         u32 base;
 303 };
 304
 305 #define SKL_MIN_SRC_W 8
 306 #define SKL_MAX_SRC_W 4096
 307 #define SKL_MIN_SRC_H 8
 308 #define SKL_MAX_SRC_H 4096
 309 #define SKL_MIN_DST_W 8
 310 #define SKL_MAX_DST_W 4096
 311 #define SKL_MIN_DST_H 8
 312 #define SKL_MAX_DST_H 4096
 313
 314 struct intel_scaler {
 315         int in_use;
 316         uint32_t mode;
 317 };
 318
 319 struct intel_crtc_scaler_state {
 320 #define SKL_NUM_SCALERS 2
 321         struct intel_scaler scalers[SKL_NUM_SCALERS];
 322
 323         /*
 324          * scaler_users: keeps track of users requesting scalers on this crtc.
 325          *
 326          *     If a bit is set, a user is using a scaler.
 327          *     Here user can be a plane or crtc as defined below:
 328          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 329          *       bit 31    - crtc
 330          *
 331          * Instead of creating a new index to cover planes and crtc, using
 332          * existing drm_plane_index for planes which is well less than 31
 333          * planes and bit 31 for crtc. This should be fine to cover all
 334          * our platforms.
 335          *
 336          * intel_atomic_setup_scalers will setup available scalers to users
 337          * requesting scalers. It will gracefully fail if request exceeds
 338          * avilability.
 339          */
 340 #define SKL_CRTC_INDEX 31
 341         unsigned scaler_users;
 342
 343         /* scaler used by crtc for panel fitting purpose */
 344         int scaler_id;
 345 };
 346
 347 /* drm_mode->private_flags */
 348 #define I915_MODE_FLAG_INHERITED 1
 349
 350 struct intel_pipe_wm {
 351         struct intel_wm_level wm[5];
 352         uint32_t linetime;
 353         bool fbc_wm_enabled;
 354         bool pipe_enabled;
 355         bool sprites_enabled;
 356         bool sprites_scaled;
 357 };
 358
 359 struct skl_pipe_wm {
 360         struct skl_wm_level wm[8];
 361         struct skl_wm_level trans_wm;
 362         uint32_t linetime;
 363 };
 364
 365 struct intel_crtc_state {
 366         struct drm_crtc_state base;
 367
 368         /**
 369          * quirks - bitfield with hw state readout quirks
 370          *
 371          * For various reasons the hw state readout code might not be able to
 372          * completely faithfully read out the current state. These cases are
 373          * tracked with quirk flags so that fastboot and state checker can act
 374          * accordingly.
 375          */
 376 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 377         unsigned long quirks;
 378
 379         bool update_pipe; /* can a fast modeset be performed? */
 380         bool disable_cxsr;
 381         bool wm_changed; /* watermarks are updated */
 382
 383         /* Pipe source size (ie. panel fitter input size)
 384          * All planes will be positioned inside this space,
 385          * and get clipped at the edges. */
 386         int pipe_src_w, pipe_src_h;
 387
 388         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 389          * between pch encoders and cpu encoders. */
 390         bool has_pch_encoder;
 391
 392         /* Are we sending infoframes on the attached port */
 393         bool has_infoframe;
 394
 395         /* CPU Transcoder for the pipe. Currently this can only differ from the
 396          * pipe on Haswell (where we have a special eDP transcoder). */
 397         enum transcoder cpu_transcoder;
 398
 399         /*
 400          * Use reduced/limited/broadcast rbg range, compressing from the full
 401          * range fed into the crtcs.
 402          */
 403         bool limited_color_range;
 404
 405         /* DP has a bunch of special case unfortunately, so mark the pipe
 406          * accordingly. */
 407         bool has_dp_encoder;
 408
 409         /* DSI has special cases */
 410         bool has_dsi_encoder;
 411
 412         /* Whether we should send NULL infoframes. Required for audio. */
 413         bool has_hdmi_sink;
 414
 415         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 416          * has_dp_encoder is set. */
 417         bool has_audio;
 418
 419         /*
 420          * Enable dithering, used when the selected pipe bpp doesn't match the
 421          * plane bpp.
 422          */
 423         bool dither;
 424
 425         /* Controls for the clock computation, to override various stages. */
 426         bool clock_set;
 427
 428         /* SDVO TV has a bunch of special case. To make multifunction encoders
 429          * work correctly, we need to track this at runtime.*/
 430         bool sdvo_tv_clock;
 431
 432         /*
 433          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 434          * required. This is set in the 2nd loop of calling encoder's
 435          * ->compute_config if the first pick doesn't work out.
 436          */
 437         bool bw_constrained;
 438
 439         /* Settings for the intel dpll used on pretty much everything but
 440          * haswell. */
 441         struct dpll dpll;
 442
 443         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 444         enum intel_dpll_id shared_dpll;
 445
 446         /*
 447          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 448          * - enum skl_dpll on SKL
 449          */
 450         uint32_t ddi_pll_sel;
 451
 452         /* Actual register state of the dpll, for shared dpll cross-checking. */
 453         struct intel_dpll_hw_state dpll_hw_state;
 454
 455         int pipe_bpp;
 456         struct intel_link_m_n dp_m_n;
 457
 458         /* m2_n2 for eDP downclock */
 459         struct intel_link_m_n dp_m2_n2;
 460         bool has_drrs;
 461
 462         /*
 463          * Frequence the dpll for the port should run at. Differs from the
 464          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 465          * already multiplied by pixel_multiplier.
 466          */
 467         int port_clock;
 468
 469         /* Used by SDVO (and if we ever fix it, HDMI). */
 470         unsigned pixel_multiplier;
 471
 472         uint8_t lane_count;
 473
 474         /* Panel fitter controls for gen2-gen4 + VLV */
 475         struct {
 476                 u32 control;
 477                 u32 pgm_ratios;
 478                 u32 lvds_border_bits;
 479         } gmch_pfit;
 480
 481         /* Panel fitter placement and size for Ironlake+ */
 482         struct {
 483                 u32 pos;
 484                 u32 size;
 485                 bool enabled;
 486                 bool force_thru;
 487         } pch_pfit;
 488
 489         /* FDI configuration, only valid if has_pch_encoder is set. */
 490         int fdi_lanes;
 491         struct intel_link_m_n fdi_m_n;
 492
 493         bool ips_enabled;
 494
 495         bool enable_fbc;
 496
 497         bool double_wide;
 498
 499         bool dp_encoder_is_mst;
 500         int pbn;
 501
 502         struct intel_crtc_scaler_state scaler_state;
 503
 504         /* w/a for waiting 2 vblanks during crtc enable */
 505         enum pipe hsw_workaround_pipe;
 506
 507         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 508         bool disable_lp_wm;
 509
 510         struct {
 511                 /*
 512                  * optimal watermarks, programmed post-vblank when this state
 513                  * is committed
 514                  */
 515                 union {
 516                         struct intel_pipe_wm ilk;
 517                         struct skl_pipe_wm skl;
 518                 } optimal;
 519         } wm;
 520 };
 521
 522 struct vlv_wm_state {
 523         struct vlv_pipe_wm wm[3];
 524         struct vlv_sr_wm sr[3];
 525         uint8_t num_active_planes;
 526         uint8_t num_levels;
 527         uint8_t level;
 528         bool cxsr;
 529 };
 530
 531 struct intel_mmio_flip {
 532         struct work_struct work;
 533         struct drm_i915_private *i915;
 534         struct drm_i915_gem_request *req;
 535         struct intel_crtc *crtc;
 536         unsigned int rotation;
 537 };
 538
 539 /*
 540  * Tracking of operations that need to be performed at the beginning/end of an
 541  * atomic commit, outside the atomic section where interrupts are disabled.
 542  * These are generally operations that grab mutexes or might otherwise sleep
 543  * and thus can't be run with interrupts disabled.
 544  */
 545 struct intel_crtc_atomic_commit {
 546         /* Sleepable operations to perform before commit */
 547
 548         /* Sleepable operations to perform after commit */
 549         unsigned fb_bits;
 550         bool wait_vblank;
 551         bool post_enable_primary;
 552         unsigned update_sprite_watermarks;
 553
 554         /* Sleepable operations to perform before and after commit */
 555         bool update_fbc;
 556 };
 557
 558 struct intel_crtc {
 559         struct drm_crtc base;
 560         enum pipe pipe;
 561         enum plane plane;
 562         u8 lut_r[256], lut_g[256], lut_b[256];
 563         /*
 564          * Whether the crtc and the connected output pipeline is active. Implies
 565          * that crtc->enabled is set, i.e. the current mode configuration has
 566          * some outputs connected to this crtc.
 567          */
 568         bool active;
 569         unsigned long enabled_power_domains;
 570         bool lowfreq_avail;
 571         struct intel_overlay *overlay;
 572         struct intel_unpin_work *unpin_work;
 573
 574         atomic_t unpin_work_count;
 575
 576         /* Display surface base address adjustement for pageflips. Note that on
 577          * gen4+ this only adjusts up to a tile, offsets within a tile are
 578          * handled in the hw itself (with the TILEOFF register). */
 579         u32 dspaddr_offset;
 580         int adjusted_x;
 581         int adjusted_y;
 582
 583         uint32_t cursor_addr;
 584         uint32_t cursor_cntl;
 585         uint32_t cursor_size;
 586         uint32_t cursor_base;
 587
 588         struct intel_crtc_state *config;
 589
 590         /* reset counter value when the last flip was submitted */
 591         unsigned int reset_counter;
 592
 593         /* Access to these should be protected by dev_priv->irq_lock. */
 594         bool cpu_fifo_underrun_disabled;
 595         bool pch_fifo_underrun_disabled;
 596
 597         /* per-pipe watermark state */
 598         struct {
 599                 /* watermarks currently being used  */
 600                 union {
 601                         struct intel_pipe_wm ilk;
 602                         struct skl_pipe_wm skl;
 603                 } active;
 604                 /* allow CxSR on this pipe */
 605                 bool cxsr_allowed;
 606         } wm;
 607
 608         int scanline_offset;
 609
 610         struct {
 611                 unsigned start_vbl_count;
 612                 ktime_t start_vbl_time;
 613                 int min_vbl, max_vbl;
 614                 int scanline_start;
 615         } debug;
 616
 617         struct intel_crtc_atomic_commit atomic;
 618
 619         /* scalers available on this crtc */
 620         int num_scalers;
 621
 622         struct vlv_wm_state wm_state;
 623 };
 624
 625 struct intel_plane_wm_parameters {
 626         uint32_t horiz_pixels;
 627         uint32_t vert_pixels;
 628         /*
 629          *   For packed pixel formats:
 630          *     bytes_per_pixel - holds bytes per pixel
 631          *   For planar pixel formats:
 632          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 633          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 634          */
 635         uint8_t bytes_per_pixel;
 636         uint8_t y_bytes_per_pixel;
 637         bool enabled;
 638         bool scaled;
 639         u64 tiling;
 640         unsigned int rotation;
 641         uint16_t fifo_size;
 642 };
 643
 644 struct intel_plane {
 645         struct drm_plane base;
 646         int plane;
 647         enum pipe pipe;
 648         bool can_scale;
 649         int max_downscale;
 650         uint32_t frontbuffer_bit;
 651
 652         /* Since we need to change the watermarks before/after
 653          * enabling/disabling the planes, we need to store the parameters here
 654          * as the other pieces of the struct may not reflect the values we want
 655          * for the watermark calculations. Currently only Haswell uses this.
 656          */
 657         struct intel_plane_wm_parameters wm;
 658
 659         /*
 660          * NOTE: Do not place new plane state fields here (e.g., when adding
 661          * new plane properties).  New runtime state should now be placed in
 662          * the intel_plane_state structure and accessed via plane_state.
 663          */
 664
 665         void (*update_plane)(struct drm_plane *plane,
 666                              const struct intel_crtc_state *crtc_state,
 667                              const struct intel_plane_state *plane_state);
 668         void (*disable_plane)(struct drm_plane *plane,
 669                               struct drm_crtc *crtc);
 670         int (*check_plane)(struct drm_plane *plane,
 671                            struct intel_crtc_state *crtc_state,
 672                            struct intel_plane_state *state);
 673 };
 674
 675 struct intel_watermark_params {
 676         unsigned long fifo_size;
 677         unsigned long max_wm;
 678         unsigned long default_wm;
 679         unsigned long guard_size;
 680         unsigned long cacheline_size;
 681 };
 682
 683 struct cxsr_latency {
 684         int is_desktop;
 685         int is_ddr3;
 686         unsigned long fsb_freq;
 687         unsigned long mem_freq;
 688         unsigned long display_sr;
 689         unsigned long display_hpll_disable;
 690         unsigned long cursor_sr;
 691         unsigned long cursor_hpll_disable;
 692 };
 693
 694 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 695 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 696 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 697 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 698 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 699 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 700 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 701 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 702 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 703
 704 struct intel_hdmi {
 705         i915_reg_t hdmi_reg;
 706         int ddc_bus;
 707         bool limited_color_range;
 708         bool color_range_auto;
 709         bool has_hdmi_sink;
 710         bool has_audio;
 711         enum hdmi_force_audio force_audio;
 712         bool rgb_quant_range_selectable;
 713         enum hdmi_picture_aspect aspect_ratio;
 714         struct intel_connector *attached_connector;
 715         void (*write_infoframe)(struct drm_encoder *encoder,
 716                                 enum hdmi_infoframe_type type,
 717                                 const void *frame, ssize_t len);
 718         void (*set_infoframes)(struct drm_encoder *encoder,
 719                                bool enable,
 720                                const struct drm_display_mode *adjusted_mode);
 721         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 722                                   const struct intel_crtc_state *pipe_config);
 723 };
 724
 725 struct intel_dp_mst_encoder;
 726 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 727
 728 /*
 729  * enum link_m_n_set:
 730  *      When platform provides two set of M_N registers for dp, we can
 731  *      program them and switch between them incase of DRRS.
 732  *      But When only one such register is provided, we have to program the
 733  *      required divider value on that registers itself based on the DRRS state.
 734  *
 735  * M1_N1        : Program dp_m_n on M1_N1 registers
 736  *                        dp_m2_n2 on M2_N2 registers (If supported)
 737  *
 738  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 739  *                        M2_N2 registers are not supported
 740  */
 741
 742 enum link_m_n_set {
 743         /* Sets the m1_n1 and m2_n2 */
 744         M1_N1 = 0,
 745         M2_N2
 746 };
 747
 748 struct intel_dp {
 749         i915_reg_t output_reg;
 750         i915_reg_t aux_ch_ctl_reg;
 751         i915_reg_t aux_ch_data_reg[5];
 752         uint32_t DP;
 753         int link_rate;
 754         uint8_t lane_count;
 755         bool has_audio;
 756         enum hdmi_force_audio force_audio;
 757         bool limited_color_range;
 758         bool color_range_auto;
 759         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 760         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 761         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 762         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 763         uint8_t num_sink_rates;
 764         int sink_rates[DP_MAX_SUPPORTED_RATES];
 765         struct drm_dp_aux aux;
 766         uint8_t train_set[4];
 767         int panel_power_up_delay;
 768         int panel_power_down_delay;
 769         int panel_power_cycle_delay;
 770         int backlight_on_delay;
 771         int backlight_off_delay;
 772         struct delayed_work panel_vdd_work;
 773         bool want_panel_vdd;
 774         unsigned long last_power_cycle;
 775         unsigned long last_power_on;
 776         unsigned long last_backlight_off;
 777
 778         struct notifier_block edp_notifier;
 779
 780         /*
 781          * Pipe whose power sequencer is currently locked into
 782          * this port. Only relevant on VLV/CHV.
 783          */
 784         enum pipe pps_pipe;
 785         struct edp_power_seq pps_delays;
 786
 787         bool can_mst; /* this port supports mst */
 788         bool is_mst;
 789         int active_mst_links;
 790         /* connector directly attached - won't be use for modeset in mst world */
 791         struct intel_connector *attached_connector;
 792
 793         /* mst connector list */
 794         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 795         struct drm_dp_mst_topology_mgr mst_mgr;
 796
 797         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 798         /*
 799          * This function returns the value we have to program the AUX_CTL
 800          * register with to kick off an AUX transaction.
 801          */
 802         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 803                                      bool has_aux_irq,
 804                                      int send_bytes,
 805                                      uint32_t aux_clock_divider);
 806
 807         /* This is called before a link training is starterd */
 808         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 809
 810         bool train_set_valid;
 811
 812         /* Displayport compliance testing */
 813         unsigned long compliance_test_type;
 814         unsigned long compliance_test_data;
 815         bool compliance_test_active;
 816 };
 817
 818 struct intel_digital_port {
 819         struct intel_encoder base;
 820         enum port port;
 821         u32 saved_port_bits;
 822         struct intel_dp dp;
 823         struct intel_hdmi hdmi;
 824         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 825         bool release_cl2_override;
 826         uint8_t max_lanes;
 827         /* for communication with audio component; protected by av_mutex */
 828         const struct drm_connector *audio_connector;
 829 };
 830
 831 struct intel_dp_mst_encoder {
 832         struct intel_encoder base;
 833         enum pipe pipe;
 834         struct intel_digital_port *primary;
 835         void *port; /* store this opaque as its illegal to dereference it */
 836 };
 837
 838 static inline enum dpio_channel
 839 vlv_dport_to_channel(struct intel_digital_port *dport)
 840 {
 841         switch (dport->port) {
 842         case PORT_B:
 843         case PORT_D:
 844                 return DPIO_CH0;
 845         case PORT_C:
 846                 return DPIO_CH1;
 847         default:
 848                 BUG();
 849         }
 850 }
 851
 852 static inline enum dpio_phy
 853 vlv_dport_to_phy(struct intel_digital_port *dport)
 854 {
 855         switch (dport->port) {
 856         case PORT_B:
 857         case PORT_C:
 858                 return DPIO_PHY0;
 859         case PORT_D:
 860                 return DPIO_PHY1;
 861         default:
 862                 BUG();
 863         }
 864 }
 865
 866 static inline enum dpio_channel
 867 vlv_pipe_to_channel(enum pipe pipe)
 868 {
 869         switch (pipe) {
 870         case PIPE_A:
 871         case PIPE_C:
 872                 return DPIO_CH0;
 873         case PIPE_B:
 874                 return DPIO_CH1;
 875         default:
 876                 BUG();
 877         }
 878 }
 879
 880 static inline struct drm_crtc *
 881 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 882 {
 883         struct drm_i915_private *dev_priv = dev->dev_private;
 884         return dev_priv->pipe_to_crtc_mapping[pipe];
 885 }
 886
 887 static inline struct drm_crtc *
 888 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 889 {
 890         struct drm_i915_private *dev_priv = dev->dev_private;
 891         return dev_priv->plane_to_crtc_mapping[plane];
 892 }
 893
 894 struct intel_unpin_work {
 895         struct work_struct work;
 896         struct drm_crtc *crtc;
 897         struct drm_framebuffer *old_fb;
 898         struct drm_i915_gem_object *pending_flip_obj;
 899         struct drm_pending_vblank_event *event;
 900         atomic_t pending;
 901 #define INTEL_FLIP_INACTIVE     0
 902 #define INTEL_FLIP_PENDING      1
 903 #define INTEL_FLIP_COMPLETE     2
 904         u32 flip_count;
 905         u32 gtt_offset;
 906         struct drm_i915_gem_request *flip_queued_req;
 907         u32 flip_queued_vblank;
 908         u32 flip_ready_vblank;
 909         bool enable_stall_check;
 910 };
 911
 912 struct intel_load_detect_pipe {
 913         struct drm_framebuffer *release_fb;
 914         bool load_detect_temp;
 915         int dpms_mode;
 916 };
 917
 918 static inline struct intel_encoder *
 919 intel_attached_encoder(struct drm_connector *connector)
 920 {
 921         return to_intel_connector(connector)->encoder;
 922 }
 923
 924 static inline struct intel_digital_port *
 925 enc_to_dig_port(struct drm_encoder *encoder)
 926 {
 927         return container_of(encoder, struct intel_digital_port, base.base);
 928 }
 929
 930 static inline struct intel_dp_mst_encoder *
 931 enc_to_mst(struct drm_encoder *encoder)
 932 {
 933         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 934 }
 935
 936 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 937 {
 938         return &enc_to_dig_port(encoder)->dp;
 939 }
 940
 941 static inline struct intel_digital_port *
 942 dp_to_dig_port(struct intel_dp *intel_dp)
 943 {
 944         return container_of(intel_dp, struct intel_digital_port, dp);
 945 }
 946
 947 static inline struct intel_digital_port *
 948 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 949 {
 950         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 951 }
 952
 953 /*
 954  * Returns the number of planes for this pipe, ie the number of sprites + 1
 955  * (primary plane). This doesn't count the cursor plane then.
 956  */
 957 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 958 {
 959         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 960 }
 961
 962 /* intel_fifo_underrun.c */
 963 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 964                                            enum pipe pipe, bool enable);
 965 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 966                                            enum transcoder pch_transcoder,
 967                                            bool enable);
 968 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 969                                          enum pipe pipe);
 970 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 971                                          enum transcoder pch_transcoder);
 972 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
 973 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
 974
 975 /* i915_irq.c */
 976 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 977 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 978 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 979 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 980 void gen6_reset_rps_interrupts(struct drm_device *dev);
 981 void gen6_enable_rps_interrupts(struct drm_device *dev);
 982 void gen6_disable_rps_interrupts(struct drm_device *dev);
 983 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 984 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 985 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 986 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 987 {
 988         /*
 989          * We only use drm_irq_uninstall() at unload and VT switch, so
 990          * this is the only thing we need to check.
 991          */
 992         return dev_priv->pm.irqs_enabled;
 993 }
 994
 995 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 996 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 997                                      unsigned int pipe_mask);
 998
 999 /* intel_crt.c */
1000 void intel_crt_init(struct drm_device *dev);
1001
1002
1003 /* intel_ddi.c */
1004 void intel_ddi_clk_select(struct intel_encoder *encoder,
1005                           const struct intel_crtc_state *pipe_config);
1006 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1007 void hsw_fdi_link_train(struct drm_crtc *crtc);
1008 void intel_ddi_init(struct drm_device *dev, enum port port);
1009 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1010 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1011 void intel_ddi_pll_init(struct drm_device *dev);
1012 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1013 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1014                                        enum transcoder cpu_transcoder);
1015 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1016 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1017 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1018                           struct intel_crtc_state *crtc_state);
1019 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1020 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1021 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1022 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1023 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1024                                  struct intel_crtc *intel_crtc);
1025 void intel_ddi_get_config(struct intel_encoder *encoder,
1026                           struct intel_crtc_state *pipe_config);
1027 struct intel_encoder *
1028 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1029
1030 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1031 void intel_ddi_clock_get(struct intel_encoder *encoder,
1032                          struct intel_crtc_state *pipe_config);
1033 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1034 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1035
1036 /* intel_frontbuffer.c */
1037 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1038                              enum fb_op_origin origin);
1039 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1040                                     unsigned frontbuffer_bits);
1041 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1042                                      unsigned frontbuffer_bits);
1043 void intel_frontbuffer_flip(struct drm_device *dev,
1044                             unsigned frontbuffer_bits);
1045 unsigned int intel_fb_align_height(struct drm_device *dev,
1046                                    unsigned int height,
1047                                    uint32_t pixel_format,
1048                                    uint64_t fb_format_modifier);
1049 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1050                         enum fb_op_origin origin);
1051 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1052                               uint64_t fb_modifier, uint32_t pixel_format);
1053
1054 /* intel_audio.c */
1055 void intel_init_audio(struct drm_device *dev);
1056 void intel_audio_codec_enable(struct intel_encoder *encoder);
1057 void intel_audio_codec_disable(struct intel_encoder *encoder);
1058 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1059 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1060
1061 /* intel_display.c */
1062 extern const struct drm_plane_funcs intel_plane_funcs;
1063 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1064 int intel_pch_rawclk(struct drm_device *dev);
1065 int intel_hrawclk(struct drm_device *dev);
1066 void intel_mark_busy(struct drm_device *dev);
1067 void intel_mark_idle(struct drm_device *dev);
1068 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1069 int intel_display_suspend(struct drm_device *dev);
1070 void intel_encoder_destroy(struct drm_encoder *encoder);
1071 int intel_connector_init(struct intel_connector *);
1072 struct intel_connector *intel_connector_alloc(void);
1073 bool intel_connector_get_hw_state(struct intel_connector *connector);
1074 void intel_connector_attach_encoder(struct intel_connector *connector,
1075                                     struct intel_encoder *encoder);
1076 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1077 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1078                                              struct drm_crtc *crtc);
1079 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1080 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1081                                 struct drm_file *file_priv);
1082 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1083                                              enum pipe pipe);
1084 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1085 static inline void
1086 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1087 {
1088         drm_wait_one_vblank(dev, pipe);
1089 }
1090 static inline void
1091 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1092 {
1093         const struct intel_crtc *crtc =
1094                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1095
1096         if (crtc->active)
1097                 intel_wait_for_vblank(dev, pipe);
1098 }
1099 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1100 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1101                          struct intel_digital_port *dport,
1102                          unsigned int expected_mask);
1103 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1104                                 struct drm_display_mode *mode,
1105                                 struct intel_load_detect_pipe *old,
1106                                 struct drm_modeset_acquire_ctx *ctx);
1107 void intel_release_load_detect_pipe(struct drm_connector *connector,
1108                                     struct intel_load_detect_pipe *old,
1109                                     struct drm_modeset_acquire_ctx *ctx);
1110 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1111                                struct drm_framebuffer *fb,
1112                                const struct drm_plane_state *plane_state);
1113 struct drm_framebuffer *
1114 __intel_framebuffer_create(struct drm_device *dev,
1115                            struct drm_mode_fb_cmd2 *mode_cmd,
1116                            struct drm_i915_gem_object *obj);
1117 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1118 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1119 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1120 void intel_check_page_flip(struct drm_device *dev, int pipe);
1121 int intel_prepare_plane_fb(struct drm_plane *plane,
1122                            const struct drm_plane_state *new_state);
1123 void intel_cleanup_plane_fb(struct drm_plane *plane,
1124                             const struct drm_plane_state *old_state);
1125 int intel_plane_atomic_get_property(struct drm_plane *plane,
1126                                     const struct drm_plane_state *state,
1127                                     struct drm_property *property,
1128                                     uint64_t *val);
1129 int intel_plane_atomic_set_property(struct drm_plane *plane,
1130                                     struct drm_plane_state *state,
1131                                     struct drm_property *property,
1132                                     uint64_t val);
1133 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1134                                     struct drm_plane_state *plane_state);
1135
1136 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1137                                uint64_t fb_modifier, unsigned int cpp);
1138
1139 static inline bool
1140 intel_rotation_90_or_270(unsigned int rotation)
1141 {
1142         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1143 }
1144
1145 void intel_create_rotation_property(struct drm_device *dev,
1146                                         struct intel_plane *plane);
1147
1148 /* shared dpll functions */
1149 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1150 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1151                         struct intel_shared_dpll *pll,
1152                         bool state);
1153 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1154 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1155 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1156                                                 struct intel_crtc_state *state);
1157
1158 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1159                      const struct dpll *dpll);
1160 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1161
1162 /* modesetting asserts */
1163 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1164                            enum pipe pipe);
1165 void assert_pll(struct drm_i915_private *dev_priv,
1166                 enum pipe pipe, bool state);
1167 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1168 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1169 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1170                        enum pipe pipe, bool state);
1171 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1172 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1173 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1174 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1175 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1176 u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
1177                               int *x, int *y,
1178                               uint64_t fb_modifier,
1179                               unsigned int cpp,
1180                               unsigned int pitch);
1181 void intel_prepare_reset(struct drm_device *dev);
1182 void intel_finish_reset(struct drm_device *dev);
1183 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1184 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1185 void broxton_init_cdclk(struct drm_device *dev);
1186 void broxton_uninit_cdclk(struct drm_device *dev);
1187 void broxton_ddi_phy_init(struct drm_device *dev);
1188 void broxton_ddi_phy_uninit(struct drm_device *dev);
1189 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1190 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1191 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1192 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1193 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1194 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1195 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1196 void intel_dp_get_m_n(struct intel_crtc *crtc,
1197                       struct intel_crtc_state *pipe_config);
1198 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1199 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1200 void
1201 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1202                                 int dotclock);
1203 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1204                         intel_clock_t *best_clock);
1205 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1206
1207 bool intel_crtc_active(struct drm_crtc *crtc);
1208 void hsw_enable_ips(struct intel_crtc *crtc);
1209 void hsw_disable_ips(struct intel_crtc *crtc);
1210 enum intel_display_power_domain
1211 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1212 enum intel_display_power_domain
1213 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1214 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1215                                  struct intel_crtc_state *pipe_config);
1216
1217 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1218 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1219
1220 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1221                            struct drm_i915_gem_object *obj,
1222                            unsigned int plane);
1223
1224 u32 skl_plane_ctl_format(uint32_t pixel_format);
1225 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1226 u32 skl_plane_ctl_rotation(unsigned int rotation);
1227
1228 /* intel_csr.c */
1229 void intel_csr_ucode_init(struct drm_i915_private *);
1230 void intel_csr_load_program(struct drm_i915_private *);
1231 void intel_csr_ucode_fini(struct drm_i915_private *);
1232
1233 /* intel_dp.c */
1234 void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1235 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1236                              struct intel_connector *intel_connector);
1237 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1238                               const struct intel_crtc_state *pipe_config);
1239 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1240 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1241 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1242 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1243 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1244 bool intel_dp_compute_config(struct intel_encoder *encoder,
1245                              struct intel_crtc_state *pipe_config);
1246 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1247 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1248                                   bool long_hpd);
1249 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1250 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1251 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1252 void intel_edp_panel_on(struct intel_dp *intel_dp);
1253 void intel_edp_panel_off(struct intel_dp *intel_dp);
1254 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1255 void intel_dp_mst_suspend(struct drm_device *dev);
1256 void intel_dp_mst_resume(struct drm_device *dev);
1257 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1258 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1259 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1260 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1261 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1262 void intel_plane_destroy(struct drm_plane *plane);
1263 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1264 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1265 void intel_edp_drrs_invalidate(struct drm_device *dev,
1266                 unsigned frontbuffer_bits);
1267 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1268 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1269                                          struct intel_digital_port *port);
1270 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1271
1272 void
1273 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1274                                        uint8_t dp_train_pat);
1275 void
1276 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1277 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1278 uint8_t
1279 intel_dp_voltage_max(struct intel_dp *intel_dp);
1280 uint8_t
1281 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1282 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1283                            uint8_t *link_bw, uint8_t *rate_select);
1284 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1285 bool
1286 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1287
1288 /* intel_dp_mst.c */
1289 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1290 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1291 /* intel_dsi.c */
1292 void intel_dsi_init(struct drm_device *dev);
1293
1294
1295 /* intel_dvo.c */
1296 void intel_dvo_init(struct drm_device *dev);
1297
1298
1299 /* legacy fbdev emulation in intel_fbdev.c */
1300 #ifdef CONFIG_DRM_FBDEV_EMULATION
1301 extern int intel_fbdev_init(struct drm_device *dev);
1302 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1303 extern void intel_fbdev_fini(struct drm_device *dev);
1304 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1305 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1306 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1307 #else
1308 static inline int intel_fbdev_init(struct drm_device *dev)
1309 {
1310         return 0;
1311 }
1312
1313 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1314 {
1315 }
1316
1317 static inline void intel_fbdev_fini(struct drm_device *dev)
1318 {
1319 }
1320
1321 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1322 {
1323 }
1324
1325 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1326 {
1327 }
1328 #endif
1329
1330 /* intel_fbc.c */
1331 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1332                            struct drm_atomic_state *state);
1333 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1334 void intel_fbc_pre_update(struct intel_crtc *crtc);
1335 void intel_fbc_post_update(struct intel_crtc *crtc);
1336 void intel_fbc_init(struct drm_i915_private *dev_priv);
1337 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1338 void intel_fbc_enable(struct intel_crtc *crtc);
1339 void intel_fbc_disable(struct intel_crtc *crtc);
1340 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1341 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1342                           unsigned int frontbuffer_bits,
1343                           enum fb_op_origin origin);
1344 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1345                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1346 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1347
1348 /* intel_hdmi.c */
1349 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1350 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1351                                struct intel_connector *intel_connector);
1352 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1353 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1354                                struct intel_crtc_state *pipe_config);
1355
1356
1357 /* intel_lvds.c */
1358 void intel_lvds_init(struct drm_device *dev);
1359 bool intel_is_dual_link_lvds(struct drm_device *dev);
1360
1361
1362 /* intel_modes.c */
1363 int intel_connector_update_modes(struct drm_connector *connector,
1364                                  struct edid *edid);
1365 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1366 void intel_attach_force_audio_property(struct drm_connector *connector);
1367 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1368 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1369
1370
1371 /* intel_overlay.c */
1372 void intel_setup_overlay(struct drm_device *dev);
1373 void intel_cleanup_overlay(struct drm_device *dev);
1374 int intel_overlay_switch_off(struct intel_overlay *overlay);
1375 int intel_overlay_put_image(struct drm_device *dev, void *data,
1376                             struct drm_file *file_priv);
1377 int intel_overlay_attrs(struct drm_device *dev, void *data,
1378                         struct drm_file *file_priv);
1379 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1380
1381
1382 /* intel_panel.c */
1383 int intel_panel_init(struct intel_panel *panel,
1384                      struct drm_display_mode *fixed_mode,
1385                      struct drm_display_mode *downclock_mode);
1386 void intel_panel_fini(struct intel_panel *panel);
1387 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1388                             struct drm_display_mode *adjusted_mode);
1389 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1390                              struct intel_crtc_state *pipe_config,
1391                              int fitting_mode);
1392 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1393                               struct intel_crtc_state *pipe_config,
1394                               int fitting_mode);
1395 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1396                                     u32 level, u32 max);
1397 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1398 void intel_panel_enable_backlight(struct intel_connector *connector);
1399 void intel_panel_disable_backlight(struct intel_connector *connector);
1400 void intel_panel_destroy_backlight(struct drm_connector *connector);
1401 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1402 extern struct drm_display_mode *intel_find_panel_downclock(
1403                                 struct drm_device *dev,
1404                                 struct drm_display_mode *fixed_mode,
1405                                 struct drm_connector *connector);
1406 void intel_backlight_register(struct drm_device *dev);
1407 void intel_backlight_unregister(struct drm_device *dev);
1408
1409
1410 /* intel_psr.c */
1411 void intel_psr_enable(struct intel_dp *intel_dp);
1412 void intel_psr_disable(struct intel_dp *intel_dp);
1413 void intel_psr_invalidate(struct drm_device *dev,
1414                           unsigned frontbuffer_bits);
1415 void intel_psr_flush(struct drm_device *dev,
1416                      unsigned frontbuffer_bits,
1417                      enum fb_op_origin origin);
1418 void intel_psr_init(struct drm_device *dev);
1419 void intel_psr_single_frame_update(struct drm_device *dev,
1420                                    unsigned frontbuffer_bits);
1421
1422 /* intel_runtime_pm.c */
1423 int intel_power_domains_init(struct drm_i915_private *);
1424 void intel_power_domains_fini(struct drm_i915_private *);
1425 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1426 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1427 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
1428 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
1429 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1430 const char *
1431 intel_display_power_domain_str(enum intel_display_power_domain domain);
1432
1433 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1434                                     enum intel_display_power_domain domain);
1435 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1436                                       enum intel_display_power_domain domain);
1437 void intel_display_power_get(struct drm_i915_private *dev_priv,
1438                              enum intel_display_power_domain domain);
1439 void intel_display_power_put(struct drm_i915_private *dev_priv,
1440                              enum intel_display_power_domain domain);
1441
1442 static inline void
1443 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1444 {
1445         WARN_ONCE(dev_priv->pm.suspended,
1446                   "Device suspended during HW access\n");
1447 }
1448
1449 static inline void
1450 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1451 {
1452         assert_rpm_device_not_suspended(dev_priv);
1453         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1454          * too much noise. */
1455         if (!atomic_read(&dev_priv->pm.wakeref_count))
1456                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1457 }
1458
1459 static inline int
1460 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1461 {
1462         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1463
1464         assert_rpm_wakelock_held(dev_priv);
1465
1466         return seq;
1467 }
1468
1469 static inline void
1470 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1471 {
1472         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1473                   "HW access outside of RPM atomic section\n");
1474 }
1475
1476 /**
1477  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1478  * @dev_priv: i915 device instance
1479  *
1480  * This function disable asserts that check if we hold an RPM wakelock
1481  * reference, while keeping the device-not-suspended checks still enabled.
1482  * It's meant to be used only in special circumstances where our rule about
1483  * the wakelock refcount wrt. the device power state doesn't hold. According
1484  * to this rule at any point where we access the HW or want to keep the HW in
1485  * an active state we must hold an RPM wakelock reference acquired via one of
1486  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1487  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1488  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1489  * users should avoid using this function.
1490  *
1491  * Any calls to this function must have a symmetric call to
1492  * enable_rpm_wakeref_asserts().
1493  */
1494 static inline void
1495 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1496 {
1497         atomic_inc(&dev_priv->pm.wakeref_count);
1498 }
1499
1500 /**
1501  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1502  * @dev_priv: i915 device instance
1503  *
1504  * This function re-enables the RPM assert checks after disabling them with
1505  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1506  * circumstances otherwise its use should be avoided.
1507  *
1508  * Any calls to this function must have a symmetric call to
1509  * disable_rpm_wakeref_asserts().
1510  */
1511 static inline void
1512 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1513 {
1514         atomic_dec(&dev_priv->pm.wakeref_count);
1515 }
1516
1517 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1518 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)   \
1519         disable_rpm_wakeref_asserts(dev_priv)
1520
1521 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)    \
1522         enable_rpm_wakeref_asserts(dev_priv)
1523
1524 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1525 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1526 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1527
1528 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1529
1530 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1531                              bool override, unsigned int mask);
1532 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1533                           enum dpio_channel ch, bool override);
1534
1535
1536 /* intel_pm.c */
1537 void intel_init_clock_gating(struct drm_device *dev);
1538 void intel_suspend_hw(struct drm_device *dev);
1539 int ilk_wm_max_level(const struct drm_device *dev);
1540 void intel_update_watermarks(struct drm_crtc *crtc);
1541 void intel_init_pm(struct drm_device *dev);
1542 void intel_pm_setup(struct drm_device *dev);
1543 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1544 void intel_gpu_ips_teardown(void);
1545 void intel_init_gt_powersave(struct drm_device *dev);
1546 void intel_cleanup_gt_powersave(struct drm_device *dev);
1547 void intel_enable_gt_powersave(struct drm_device *dev);
1548 void intel_disable_gt_powersave(struct drm_device *dev);
1549 void intel_suspend_gt_powersave(struct drm_device *dev);
1550 void intel_reset_gt_powersave(struct drm_device *dev);
1551 void gen6_update_ring_freq(struct drm_device *dev);
1552 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1553 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1554 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1555 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1556                     struct intel_rps_client *rps,
1557                     unsigned long submitted);
1558 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1559                                        struct drm_i915_gem_request *req);
1560 void vlv_wm_get_hw_state(struct drm_device *dev);
1561 void ilk_wm_get_hw_state(struct drm_device *dev);
1562 void skl_wm_get_hw_state(struct drm_device *dev);
1563 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1564                           struct skl_ddb_allocation *ddb /* out */);
1565 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1566 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6);
1567
1568 /* intel_sdvo.c */
1569 bool intel_sdvo_init(struct drm_device *dev,
1570                      i915_reg_t reg, enum port port);
1571
1572
1573 /* intel_sprite.c */
1574 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1575 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1576                               struct drm_file *file_priv);
1577 void intel_pipe_update_start(struct intel_crtc *crtc);
1578 void intel_pipe_update_end(struct intel_crtc *crtc);
1579
1580 /* intel_tv.c */
1581 void intel_tv_init(struct drm_device *dev);
1582
1583 /* intel_atomic.c */
1584 int intel_connector_atomic_get_property(struct drm_connector *connector,
1585                                         const struct drm_connector_state *state,
1586                                         struct drm_property *property,
1587                                         uint64_t *val);
1588 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1589 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1590                                struct drm_crtc_state *state);
1591 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1592 void intel_atomic_state_clear(struct drm_atomic_state *);
1593 struct intel_shared_dpll_config *
1594 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1595
1596 static inline struct intel_crtc_state *
1597 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1598                             struct intel_crtc *crtc)
1599 {
1600         struct drm_crtc_state *crtc_state;
1601         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1602         if (IS_ERR(crtc_state))
1603                 return ERR_CAST(crtc_state);
1604
1605         return to_intel_crtc_state(crtc_state);
1606 }
1607 int intel_atomic_setup_scalers(struct drm_device *dev,
1608         struct intel_crtc *intel_crtc,
1609         struct intel_crtc_state *crtc_state);
1610
1611 /* intel_atomic_plane.c */
1612 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1613 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1614 void intel_plane_destroy_state(struct drm_plane *plane,
1615                                struct drm_plane_state *state);
1616 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1617
1618 #endif /* __INTEL_DRV_H__ */