drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         int preferred_bpp;
 127 };
 128
 129 struct intel_encoder {
 130         struct drm_encoder base;
 131
 132         enum intel_output_type type;
 133         unsigned int cloneable;
 134         void (*hot_plug)(struct intel_encoder *);
 135         bool (*compute_config)(struct intel_encoder *,
 136                                struct intel_crtc_state *);
 137         void (*pre_pll_enable)(struct intel_encoder *);
 138         void (*pre_enable)(struct intel_encoder *);
 139         void (*enable)(struct intel_encoder *);
 140         void (*mode_set)(struct intel_encoder *intel_encoder);
 141         void (*disable)(struct intel_encoder *);
 142         void (*post_disable)(struct intel_encoder *);
 143         void (*post_pll_disable)(struct intel_encoder *);
 144         /* Read out the current hw state of this connector, returning true if
 145          * the encoder is active. If the encoder is enabled it also set the pipe
 146          * it is connected to in the pipe parameter. */
 147         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 148         /* Reconstructs the equivalent mode flags for the current hardware
 149          * state. This must be called _after_ display->get_pipe_config has
 150          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 151          * be set correctly before calling this function. */
 152         void (*get_config)(struct intel_encoder *,
 153                            struct intel_crtc_state *pipe_config);
 154         /*
 155          * Called during system suspend after all pending requests for the
 156          * encoder are flushed (for example for DP AUX transactions) and
 157          * device interrupts are disabled.
 158          */
 159         void (*suspend)(struct intel_encoder *);
 160         int crtc_mask;
 161         enum hpd_pin hpd_pin;
 162 };
 163
 164 struct intel_panel {
 165         struct drm_display_mode *fixed_mode;
 166         struct drm_display_mode *downclock_mode;
 167         int fitting_mode;
 168
 169         /* backlight */
 170         struct {
 171                 bool present;
 172                 u32 level;
 173                 u32 min;
 174                 u32 max;
 175                 bool enabled;
 176                 bool combination_mode;  /* gen 2/4 only */
 177                 bool active_low_pwm;
 178
 179                 /* PWM chip */
 180                 bool util_pin_active_low;       /* bxt+ */
 181                 u8 controller;          /* bxt+ only */
 182                 struct pwm_device *pwm;
 183
 184                 struct backlight_device *device;
 185
 186                 /* Connector and platform specific backlight functions */
 187                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 188                 uint32_t (*get)(struct intel_connector *connector);
 189                 void (*set)(struct intel_connector *connector, uint32_t level);
 190                 void (*disable)(struct intel_connector *connector);
 191                 void (*enable)(struct intel_connector *connector);
 192                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 193                                       uint32_t hz);
 194                 void (*power)(struct intel_connector *, bool enable);
 195         } backlight;
 196 };
 197
 198 struct intel_connector {
 199         struct drm_connector base;
 200         /*
 201          * The fixed encoder this connector is connected to.
 202          */
 203         struct intel_encoder *encoder;
 204
 205         /* Reads out the current hw, returning true if the connector is enabled
 206          * and active (i.e. dpms ON state). */
 207         bool (*get_hw_state)(struct intel_connector *);
 208
 209         /*
 210          * Removes all interfaces through which the connector is accessible
 211          * - like sysfs, debugfs entries -, so that no new operations can be
 212          * started on the connector. Also makes sure all currently pending
 213          * operations finish before returing.
 214          */
 215         void (*unregister)(struct intel_connector *);
 216
 217         /* Panel info for eDP and LVDS */
 218         struct intel_panel panel;
 219
 220         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 221         struct edid *edid;
 222         struct edid *detect_edid;
 223
 224         /* since POLL and HPD connectors may use the same HPD line keep the native
 225            state of connector->polled in case hotplug storm detection changes it */
 226         u8 polled;
 227
 228         void *port; /* store this opaque as its illegal to dereference it */
 229
 230         struct intel_dp *mst_port;
 231 };
 232
 233 typedef struct dpll {
 234         /* given values */
 235         int n;
 236         int m1, m2;
 237         int p1, p2;
 238         /* derived values */
 239         int     dot;
 240         int     vco;
 241         int     m;
 242         int     p;
 243 } intel_clock_t;
 244
 245 struct intel_atomic_state {
 246         struct drm_atomic_state base;
 247
 248         unsigned int cdclk;
 249         bool dpll_set;
 250         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 251         struct intel_wm_config wm_config;
 252 };
 253
 254 struct intel_plane_state {
 255         struct drm_plane_state base;
 256         struct drm_rect src;
 257         struct drm_rect dst;
 258         struct drm_rect clip;
 259         bool visible;
 260
 261         /*
 262          * scaler_id
 263          *    = -1 : not using a scaler
 264          *    >=  0 : using a scalers
 265          *
 266          * plane requiring a scaler:
 267          *   - During check_plane, its bit is set in
 268          *     crtc_state->scaler_state.scaler_users by calling helper function
 269          *     update_scaler_plane.
 270          *   - scaler_id indicates the scaler it got assigned.
 271          *
 272          * plane doesn't require a scaler:
 273          *   - this can happen when scaling is no more required or plane simply
 274          *     got disabled.
 275          *   - During check_plane, corresponding bit is reset in
 276          *     crtc_state->scaler_state.scaler_users by calling helper function
 277          *     update_scaler_plane.
 278          */
 279         int scaler_id;
 280
 281         struct drm_intel_sprite_colorkey ckey;
 282
 283         /* async flip related structures */
 284         struct drm_i915_gem_request *wait_req;
 285 };
 286
 287 struct intel_initial_plane_config {
 288         struct intel_framebuffer *fb;
 289         unsigned int tiling;
 290         int size;
 291         u32 base;
 292 };
 293
 294 #define SKL_MIN_SRC_W 8
 295 #define SKL_MAX_SRC_W 4096
 296 #define SKL_MIN_SRC_H 8
 297 #define SKL_MAX_SRC_H 4096
 298 #define SKL_MIN_DST_W 8
 299 #define SKL_MAX_DST_W 4096
 300 #define SKL_MIN_DST_H 8
 301 #define SKL_MAX_DST_H 4096
 302
 303 struct intel_scaler {
 304         int in_use;
 305         uint32_t mode;
 306 };
 307
 308 struct intel_crtc_scaler_state {
 309 #define SKL_NUM_SCALERS 2
 310         struct intel_scaler scalers[SKL_NUM_SCALERS];
 311
 312         /*
 313          * scaler_users: keeps track of users requesting scalers on this crtc.
 314          *
 315          *     If a bit is set, a user is using a scaler.
 316          *     Here user can be a plane or crtc as defined below:
 317          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 318          *       bit 31    - crtc
 319          *
 320          * Instead of creating a new index to cover planes and crtc, using
 321          * existing drm_plane_index for planes which is well less than 31
 322          * planes and bit 31 for crtc. This should be fine to cover all
 323          * our platforms.
 324          *
 325          * intel_atomic_setup_scalers will setup available scalers to users
 326          * requesting scalers. It will gracefully fail if request exceeds
 327          * avilability.
 328          */
 329 #define SKL_CRTC_INDEX 31
 330         unsigned scaler_users;
 331
 332         /* scaler used by crtc for panel fitting purpose */
 333         int scaler_id;
 334 };
 335
 336 /* drm_mode->private_flags */
 337 #define I915_MODE_FLAG_INHERITED 1
 338
 339 struct intel_pipe_wm {
 340         struct intel_wm_level wm[5];
 341         uint32_t linetime;
 342         bool fbc_wm_enabled;
 343         bool pipe_enabled;
 344         bool sprites_enabled;
 345         bool sprites_scaled;
 346 };
 347
 348 struct skl_pipe_wm {
 349         struct skl_wm_level wm[8];
 350         struct skl_wm_level trans_wm;
 351         uint32_t linetime;
 352 };
 353
 354 struct intel_crtc_state {
 355         struct drm_crtc_state base;
 356
 357         /**
 358          * quirks - bitfield with hw state readout quirks
 359          *
 360          * For various reasons the hw state readout code might not be able to
 361          * completely faithfully read out the current state. These cases are
 362          * tracked with quirk flags so that fastboot and state checker can act
 363          * accordingly.
 364          */
 365 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 366         unsigned long quirks;
 367
 368         bool update_pipe; /* can a fast modeset be performed? */
 369         bool disable_cxsr;
 370         bool wm_changed; /* watermarks are updated */
 371
 372         /* Pipe source size (ie. panel fitter input size)
 373          * All planes will be positioned inside this space,
 374          * and get clipped at the edges. */
 375         int pipe_src_w, pipe_src_h;
 376
 377         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 378          * between pch encoders and cpu encoders. */
 379         bool has_pch_encoder;
 380
 381         /* Are we sending infoframes on the attached port */
 382         bool has_infoframe;
 383
 384         /* CPU Transcoder for the pipe. Currently this can only differ from the
 385          * pipe on Haswell (where we have a special eDP transcoder). */
 386         enum transcoder cpu_transcoder;
 387
 388         /*
 389          * Use reduced/limited/broadcast rbg range, compressing from the full
 390          * range fed into the crtcs.
 391          */
 392         bool limited_color_range;
 393
 394         /* DP has a bunch of special case unfortunately, so mark the pipe
 395          * accordingly. */
 396         bool has_dp_encoder;
 397
 398         /* DSI has special cases */
 399         bool has_dsi_encoder;
 400
 401         /* Whether we should send NULL infoframes. Required for audio. */
 402         bool has_hdmi_sink;
 403
 404         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 405          * has_dp_encoder is set. */
 406         bool has_audio;
 407
 408         /*
 409          * Enable dithering, used when the selected pipe bpp doesn't match the
 410          * plane bpp.
 411          */
 412         bool dither;
 413
 414         /* Controls for the clock computation, to override various stages. */
 415         bool clock_set;
 416
 417         /* SDVO TV has a bunch of special case. To make multifunction encoders
 418          * work correctly, we need to track this at runtime.*/
 419         bool sdvo_tv_clock;
 420
 421         /*
 422          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 423          * required. This is set in the 2nd loop of calling encoder's
 424          * ->compute_config if the first pick doesn't work out.
 425          */
 426         bool bw_constrained;
 427
 428         /* Settings for the intel dpll used on pretty much everything but
 429          * haswell. */
 430         struct dpll dpll;
 431
 432         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 433         enum intel_dpll_id shared_dpll;
 434
 435         /*
 436          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 437          * - enum skl_dpll on SKL
 438          */
 439         uint32_t ddi_pll_sel;
 440
 441         /* Actual register state of the dpll, for shared dpll cross-checking. */
 442         struct intel_dpll_hw_state dpll_hw_state;
 443
 444         int pipe_bpp;
 445         struct intel_link_m_n dp_m_n;
 446
 447         /* m2_n2 for eDP downclock */
 448         struct intel_link_m_n dp_m2_n2;
 449         bool has_drrs;
 450
 451         /*
 452          * Frequence the dpll for the port should run at. Differs from the
 453          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 454          * already multiplied by pixel_multiplier.
 455          */
 456         int port_clock;
 457
 458         /* Used by SDVO (and if we ever fix it, HDMI). */
 459         unsigned pixel_multiplier;
 460
 461         uint8_t lane_count;
 462
 463         /* Panel fitter controls for gen2-gen4 + VLV */
 464         struct {
 465                 u32 control;
 466                 u32 pgm_ratios;
 467                 u32 lvds_border_bits;
 468         } gmch_pfit;
 469
 470         /* Panel fitter placement and size for Ironlake+ */
 471         struct {
 472                 u32 pos;
 473                 u32 size;
 474                 bool enabled;
 475                 bool force_thru;
 476         } pch_pfit;
 477
 478         /* FDI configuration, only valid if has_pch_encoder is set. */
 479         int fdi_lanes;
 480         struct intel_link_m_n fdi_m_n;
 481
 482         bool ips_enabled;
 483
 484         bool double_wide;
 485
 486         bool dp_encoder_is_mst;
 487         int pbn;
 488
 489         struct intel_crtc_scaler_state scaler_state;
 490
 491         /* w/a for waiting 2 vblanks during crtc enable */
 492         enum pipe hsw_workaround_pipe;
 493
 494         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 495         bool disable_lp_wm;
 496
 497         struct {
 498                 /*
 499                  * optimal watermarks, programmed post-vblank when this state
 500                  * is committed
 501                  */
 502                 union {
 503                         struct intel_pipe_wm ilk;
 504                         struct skl_pipe_wm skl;
 505                 } optimal;
 506         } wm;
 507 };
 508
 509 struct vlv_wm_state {
 510         struct vlv_pipe_wm wm[3];
 511         struct vlv_sr_wm sr[3];
 512         uint8_t num_active_planes;
 513         uint8_t num_levels;
 514         uint8_t level;
 515         bool cxsr;
 516 };
 517
 518 struct intel_mmio_flip {
 519         struct work_struct work;
 520         struct drm_i915_private *i915;
 521         struct drm_i915_gem_request *req;
 522         struct intel_crtc *crtc;
 523         unsigned int rotation;
 524 };
 525
 526 /*
 527  * Tracking of operations that need to be performed at the beginning/end of an
 528  * atomic commit, outside the atomic section where interrupts are disabled.
 529  * These are generally operations that grab mutexes or might otherwise sleep
 530  * and thus can't be run with interrupts disabled.
 531  */
 532 struct intel_crtc_atomic_commit {
 533         /* Sleepable operations to perform before commit */
 534         bool disable_fbc;
 535         bool disable_ips;
 536         bool pre_disable_primary;
 537
 538         /* Sleepable operations to perform after commit */
 539         unsigned fb_bits;
 540         bool wait_vblank;
 541         bool update_fbc;
 542         bool post_enable_primary;
 543         unsigned update_sprite_watermarks;
 544 };
 545
 546 struct intel_crtc {
 547         struct drm_crtc base;
 548         enum pipe pipe;
 549         enum plane plane;
 550         u8 lut_r[256], lut_g[256], lut_b[256];
 551         /*
 552          * Whether the crtc and the connected output pipeline is active. Implies
 553          * that crtc->enabled is set, i.e. the current mode configuration has
 554          * some outputs connected to this crtc.
 555          */
 556         bool active;
 557         unsigned long enabled_power_domains;
 558         bool lowfreq_avail;
 559         struct intel_overlay *overlay;
 560         struct intel_unpin_work *unpin_work;
 561
 562         atomic_t unpin_work_count;
 563
 564         /* Display surface base address adjustement for pageflips. Note that on
 565          * gen4+ this only adjusts up to a tile, offsets within a tile are
 566          * handled in the hw itself (with the TILEOFF register). */
 567         unsigned long dspaddr_offset;
 568         int adjusted_x;
 569         int adjusted_y;
 570
 571         uint32_t cursor_addr;
 572         uint32_t cursor_cntl;
 573         uint32_t cursor_size;
 574         uint32_t cursor_base;
 575
 576         struct intel_crtc_state *config;
 577
 578         /* reset counter value when the last flip was submitted */
 579         unsigned int reset_counter;
 580
 581         /* Access to these should be protected by dev_priv->irq_lock. */
 582         bool cpu_fifo_underrun_disabled;
 583         bool pch_fifo_underrun_disabled;
 584
 585         /* per-pipe watermark state */
 586         struct {
 587                 /* watermarks currently being used  */
 588                 union {
 589                         struct intel_pipe_wm ilk;
 590                         struct skl_pipe_wm skl;
 591                 } active;
 592                 /* allow CxSR on this pipe */
 593                 bool cxsr_allowed;
 594         } wm;
 595
 596         int scanline_offset;
 597
 598         struct {
 599                 unsigned start_vbl_count;
 600                 ktime_t start_vbl_time;
 601                 int min_vbl, max_vbl;
 602                 int scanline_start;
 603         } debug;
 604
 605         struct intel_crtc_atomic_commit atomic;
 606
 607         /* scalers available on this crtc */
 608         int num_scalers;
 609
 610         struct vlv_wm_state wm_state;
 611 };
 612
 613 struct intel_plane_wm_parameters {
 614         uint32_t horiz_pixels;
 615         uint32_t vert_pixels;
 616         /*
 617          *   For packed pixel formats:
 618          *     bytes_per_pixel - holds bytes per pixel
 619          *   For planar pixel formats:
 620          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 621          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 622          */
 623         uint8_t bytes_per_pixel;
 624         uint8_t y_bytes_per_pixel;
 625         bool enabled;
 626         bool scaled;
 627         u64 tiling;
 628         unsigned int rotation;
 629         uint16_t fifo_size;
 630 };
 631
 632 struct intel_plane {
 633         struct drm_plane base;
 634         int plane;
 635         enum pipe pipe;
 636         bool can_scale;
 637         int max_downscale;
 638         uint32_t frontbuffer_bit;
 639
 640         /* Since we need to change the watermarks before/after
 641          * enabling/disabling the planes, we need to store the parameters here
 642          * as the other pieces of the struct may not reflect the values we want
 643          * for the watermark calculations. Currently only Haswell uses this.
 644          */
 645         struct intel_plane_wm_parameters wm;
 646
 647         /*
 648          * NOTE: Do not place new plane state fields here (e.g., when adding
 649          * new plane properties).  New runtime state should now be placed in
 650          * the intel_plane_state structure and accessed via drm_plane->state.
 651          */
 652
 653         void (*update_plane)(struct drm_plane *plane,
 654                              struct drm_crtc *crtc,
 655                              struct drm_framebuffer *fb,
 656                              int crtc_x, int crtc_y,
 657                              unsigned int crtc_w, unsigned int crtc_h,
 658                              uint32_t x, uint32_t y,
 659                              uint32_t src_w, uint32_t src_h);
 660         void (*disable_plane)(struct drm_plane *plane,
 661                               struct drm_crtc *crtc);
 662         int (*check_plane)(struct drm_plane *plane,
 663                            struct intel_crtc_state *crtc_state,
 664                            struct intel_plane_state *state);
 665         void (*commit_plane)(struct drm_plane *plane,
 666                              struct intel_plane_state *state);
 667 };
 668
 669 struct intel_watermark_params {
 670         unsigned long fifo_size;
 671         unsigned long max_wm;
 672         unsigned long default_wm;
 673         unsigned long guard_size;
 674         unsigned long cacheline_size;
 675 };
 676
 677 struct cxsr_latency {
 678         int is_desktop;
 679         int is_ddr3;
 680         unsigned long fsb_freq;
 681         unsigned long mem_freq;
 682         unsigned long display_sr;
 683         unsigned long display_hpll_disable;
 684         unsigned long cursor_sr;
 685         unsigned long cursor_hpll_disable;
 686 };
 687
 688 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 689 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 690 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 691 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 692 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 693 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 694 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 695 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 696 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 697
 698 struct intel_hdmi {
 699         i915_reg_t hdmi_reg;
 700         int ddc_bus;
 701         bool limited_color_range;
 702         bool color_range_auto;
 703         bool has_hdmi_sink;
 704         bool has_audio;
 705         enum hdmi_force_audio force_audio;
 706         bool rgb_quant_range_selectable;
 707         enum hdmi_picture_aspect aspect_ratio;
 708         struct intel_connector *attached_connector;
 709         void (*write_infoframe)(struct drm_encoder *encoder,
 710                                 enum hdmi_infoframe_type type,
 711                                 const void *frame, ssize_t len);
 712         void (*set_infoframes)(struct drm_encoder *encoder,
 713                                bool enable,
 714                                const struct drm_display_mode *adjusted_mode);
 715         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 716                                   const struct intel_crtc_state *pipe_config);
 717 };
 718
 719 struct intel_dp_mst_encoder;
 720 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 721
 722 /*
 723  * enum link_m_n_set:
 724  *      When platform provides two set of M_N registers for dp, we can
 725  *      program them and switch between them incase of DRRS.
 726  *      But When only one such register is provided, we have to program the
 727  *      required divider value on that registers itself based on the DRRS state.
 728  *
 729  * M1_N1        : Program dp_m_n on M1_N1 registers
 730  *                        dp_m2_n2 on M2_N2 registers (If supported)
 731  *
 732  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 733  *                        M2_N2 registers are not supported
 734  */
 735
 736 enum link_m_n_set {
 737         /* Sets the m1_n1 and m2_n2 */
 738         M1_N1 = 0,
 739         M2_N2
 740 };
 741
 742 struct intel_dp {
 743         i915_reg_t output_reg;
 744         i915_reg_t aux_ch_ctl_reg;
 745         i915_reg_t aux_ch_data_reg[5];
 746         uint32_t DP;
 747         int link_rate;
 748         uint8_t lane_count;
 749         bool has_audio;
 750         enum hdmi_force_audio force_audio;
 751         bool limited_color_range;
 752         bool color_range_auto;
 753         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 754         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 755         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 756         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 757         uint8_t num_sink_rates;
 758         int sink_rates[DP_MAX_SUPPORTED_RATES];
 759         struct drm_dp_aux aux;
 760         uint8_t train_set[4];
 761         int panel_power_up_delay;
 762         int panel_power_down_delay;
 763         int panel_power_cycle_delay;
 764         int backlight_on_delay;
 765         int backlight_off_delay;
 766         struct delayed_work panel_vdd_work;
 767         bool want_panel_vdd;
 768         unsigned long last_power_cycle;
 769         unsigned long last_power_on;
 770         unsigned long last_backlight_off;
 771
 772         struct notifier_block edp_notifier;
 773
 774         /*
 775          * Pipe whose power sequencer is currently locked into
 776          * this port. Only relevant on VLV/CHV.
 777          */
 778         enum pipe pps_pipe;
 779         struct edp_power_seq pps_delays;
 780
 781         bool can_mst; /* this port supports mst */
 782         bool is_mst;
 783         int active_mst_links;
 784         /* connector directly attached - won't be use for modeset in mst world */
 785         struct intel_connector *attached_connector;
 786
 787         /* mst connector list */
 788         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 789         struct drm_dp_mst_topology_mgr mst_mgr;
 790
 791         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 792         /*
 793          * This function returns the value we have to program the AUX_CTL
 794          * register with to kick off an AUX transaction.
 795          */
 796         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 797                                      bool has_aux_irq,
 798                                      int send_bytes,
 799                                      uint32_t aux_clock_divider);
 800
 801         /* This is called before a link training is starterd */
 802         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 803
 804         bool train_set_valid;
 805
 806         /* Displayport compliance testing */
 807         unsigned long compliance_test_type;
 808         unsigned long compliance_test_data;
 809         bool compliance_test_active;
 810 };
 811
 812 struct intel_digital_port {
 813         struct intel_encoder base;
 814         enum port port;
 815         u32 saved_port_bits;
 816         struct intel_dp dp;
 817         struct intel_hdmi hdmi;
 818         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 819         bool release_cl2_override;
 820         /* for communication with audio component; protected by av_mutex */
 821         const struct drm_connector *audio_connector;
 822 };
 823
 824 struct intel_dp_mst_encoder {
 825         struct intel_encoder base;
 826         enum pipe pipe;
 827         struct intel_digital_port *primary;
 828         void *port; /* store this opaque as its illegal to dereference it */
 829 };
 830
 831 static inline enum dpio_channel
 832 vlv_dport_to_channel(struct intel_digital_port *dport)
 833 {
 834         switch (dport->port) {
 835         case PORT_B:
 836         case PORT_D:
 837                 return DPIO_CH0;
 838         case PORT_C:
 839                 return DPIO_CH1;
 840         default:
 841                 BUG();
 842         }
 843 }
 844
 845 static inline enum dpio_phy
 846 vlv_dport_to_phy(struct intel_digital_port *dport)
 847 {
 848         switch (dport->port) {
 849         case PORT_B:
 850         case PORT_C:
 851                 return DPIO_PHY0;
 852         case PORT_D:
 853                 return DPIO_PHY1;
 854         default:
 855                 BUG();
 856         }
 857 }
 858
 859 static inline enum dpio_channel
 860 vlv_pipe_to_channel(enum pipe pipe)
 861 {
 862         switch (pipe) {
 863         case PIPE_A:
 864         case PIPE_C:
 865                 return DPIO_CH0;
 866         case PIPE_B:
 867                 return DPIO_CH1;
 868         default:
 869                 BUG();
 870         }
 871 }
 872
 873 static inline struct drm_crtc *
 874 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 875 {
 876         struct drm_i915_private *dev_priv = dev->dev_private;
 877         return dev_priv->pipe_to_crtc_mapping[pipe];
 878 }
 879
 880 static inline struct drm_crtc *
 881 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 882 {
 883         struct drm_i915_private *dev_priv = dev->dev_private;
 884         return dev_priv->plane_to_crtc_mapping[plane];
 885 }
 886
 887 struct intel_unpin_work {
 888         struct work_struct work;
 889         struct drm_crtc *crtc;
 890         struct drm_framebuffer *old_fb;
 891         struct drm_i915_gem_object *pending_flip_obj;
 892         struct drm_pending_vblank_event *event;
 893         atomic_t pending;
 894 #define INTEL_FLIP_INACTIVE     0
 895 #define INTEL_FLIP_PENDING      1
 896 #define INTEL_FLIP_COMPLETE     2
 897         u32 flip_count;
 898         u32 gtt_offset;
 899         struct drm_i915_gem_request *flip_queued_req;
 900         u32 flip_queued_vblank;
 901         u32 flip_ready_vblank;
 902         bool enable_stall_check;
 903 };
 904
 905 struct intel_load_detect_pipe {
 906         struct drm_framebuffer *release_fb;
 907         bool load_detect_temp;
 908         int dpms_mode;
 909 };
 910
 911 static inline struct intel_encoder *
 912 intel_attached_encoder(struct drm_connector *connector)
 913 {
 914         return to_intel_connector(connector)->encoder;
 915 }
 916
 917 static inline struct intel_digital_port *
 918 enc_to_dig_port(struct drm_encoder *encoder)
 919 {
 920         return container_of(encoder, struct intel_digital_port, base.base);
 921 }
 922
 923 static inline struct intel_dp_mst_encoder *
 924 enc_to_mst(struct drm_encoder *encoder)
 925 {
 926         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 927 }
 928
 929 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 930 {
 931         return &enc_to_dig_port(encoder)->dp;
 932 }
 933
 934 static inline struct intel_digital_port *
 935 dp_to_dig_port(struct intel_dp *intel_dp)
 936 {
 937         return container_of(intel_dp, struct intel_digital_port, dp);
 938 }
 939
 940 static inline struct intel_digital_port *
 941 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 942 {
 943         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 944 }
 945
 946 /*
 947  * Returns the number of planes for this pipe, ie the number of sprites + 1
 948  * (primary plane). This doesn't count the cursor plane then.
 949  */
 950 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 951 {
 952         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 953 }
 954
 955 /* intel_fifo_underrun.c */
 956 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 957                                            enum pipe pipe, bool enable);
 958 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 959                                            enum transcoder pch_transcoder,
 960                                            bool enable);
 961 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 962                                          enum pipe pipe);
 963 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 964                                          enum transcoder pch_transcoder);
 965 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
 966 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
 967
 968 /* i915_irq.c */
 969 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 970 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 971 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 972 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 973 void gen6_reset_rps_interrupts(struct drm_device *dev);
 974 void gen6_enable_rps_interrupts(struct drm_device *dev);
 975 void gen6_disable_rps_interrupts(struct drm_device *dev);
 976 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 977 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 978 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 979 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 980 {
 981         /*
 982          * We only use drm_irq_uninstall() at unload and VT switch, so
 983          * this is the only thing we need to check.
 984          */
 985         return dev_priv->pm.irqs_enabled;
 986 }
 987
 988 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 989 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 990                                      unsigned int pipe_mask);
 991
 992 /* intel_crt.c */
 993 void intel_crt_init(struct drm_device *dev);
 994
 995
 996 /* intel_ddi.c */
 997 void intel_ddi_clk_select(struct intel_encoder *encoder,
 998                           const struct intel_crtc_state *pipe_config);
 999 void intel_prepare_ddi(struct drm_device *dev);
1000 void hsw_fdi_link_train(struct drm_crtc *crtc);
1001 void intel_ddi_init(struct drm_device *dev, enum port port);
1002 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1003 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1004 void intel_ddi_pll_init(struct drm_device *dev);
1005 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1006 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1007                                        enum transcoder cpu_transcoder);
1008 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1009 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1010 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1011                           struct intel_crtc_state *crtc_state);
1012 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1013 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1014 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1015 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1016 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1017                                  struct intel_crtc *intel_crtc);
1018 void intel_ddi_get_config(struct intel_encoder *encoder,
1019                           struct intel_crtc_state *pipe_config);
1020 struct intel_encoder *
1021 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1022
1023 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1024 void intel_ddi_clock_get(struct intel_encoder *encoder,
1025                          struct intel_crtc_state *pipe_config);
1026 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1027 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1028
1029 /* intel_frontbuffer.c */
1030 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1031                              enum fb_op_origin origin);
1032 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1033                                     unsigned frontbuffer_bits);
1034 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1035                                      unsigned frontbuffer_bits);
1036 void intel_frontbuffer_flip(struct drm_device *dev,
1037                             unsigned frontbuffer_bits);
1038 unsigned int intel_fb_align_height(struct drm_device *dev,
1039                                    unsigned int height,
1040                                    uint32_t pixel_format,
1041                                    uint64_t fb_format_modifier);
1042 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1043                         enum fb_op_origin origin);
1044 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
1045                               uint32_t pixel_format);
1046
1047 /* intel_audio.c */
1048 void intel_init_audio(struct drm_device *dev);
1049 void intel_audio_codec_enable(struct intel_encoder *encoder);
1050 void intel_audio_codec_disable(struct intel_encoder *encoder);
1051 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1052 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1053
1054 /* intel_display.c */
1055 extern const struct drm_plane_funcs intel_plane_funcs;
1056 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1057 int intel_pch_rawclk(struct drm_device *dev);
1058 int intel_hrawclk(struct drm_device *dev);
1059 void intel_mark_busy(struct drm_device *dev);
1060 void intel_mark_idle(struct drm_device *dev);
1061 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1062 int intel_display_suspend(struct drm_device *dev);
1063 void intel_encoder_destroy(struct drm_encoder *encoder);
1064 int intel_connector_init(struct intel_connector *);
1065 struct intel_connector *intel_connector_alloc(void);
1066 bool intel_connector_get_hw_state(struct intel_connector *connector);
1067 void intel_connector_attach_encoder(struct intel_connector *connector,
1068                                     struct intel_encoder *encoder);
1069 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1070 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1071                                              struct drm_crtc *crtc);
1072 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1073 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1074                                 struct drm_file *file_priv);
1075 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1076                                              enum pipe pipe);
1077 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1078 static inline void
1079 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1080 {
1081         drm_wait_one_vblank(dev, pipe);
1082 }
1083 static inline void
1084 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1085 {
1086         const struct intel_crtc *crtc =
1087                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1088
1089         if (crtc->active)
1090                 intel_wait_for_vblank(dev, pipe);
1091 }
1092 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1093 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1094                          struct intel_digital_port *dport,
1095                          unsigned int expected_mask);
1096 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1097                                 struct drm_display_mode *mode,
1098                                 struct intel_load_detect_pipe *old,
1099                                 struct drm_modeset_acquire_ctx *ctx);
1100 void intel_release_load_detect_pipe(struct drm_connector *connector,
1101                                     struct intel_load_detect_pipe *old,
1102                                     struct drm_modeset_acquire_ctx *ctx);
1103 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1104                                struct drm_framebuffer *fb,
1105                                const struct drm_plane_state *plane_state);
1106 struct drm_framebuffer *
1107 __intel_framebuffer_create(struct drm_device *dev,
1108                            struct drm_mode_fb_cmd2 *mode_cmd,
1109                            struct drm_i915_gem_object *obj);
1110 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1111 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1112 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1113 void intel_check_page_flip(struct drm_device *dev, int pipe);
1114 int intel_prepare_plane_fb(struct drm_plane *plane,
1115                            const struct drm_plane_state *new_state);
1116 void intel_cleanup_plane_fb(struct drm_plane *plane,
1117                             const struct drm_plane_state *old_state);
1118 int intel_plane_atomic_get_property(struct drm_plane *plane,
1119                                     const struct drm_plane_state *state,
1120                                     struct drm_property *property,
1121                                     uint64_t *val);
1122 int intel_plane_atomic_set_property(struct drm_plane *plane,
1123                                     struct drm_plane_state *state,
1124                                     struct drm_property *property,
1125                                     uint64_t val);
1126 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1127                                     struct drm_plane_state *plane_state);
1128
1129 unsigned int
1130 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1131                   uint64_t fb_format_modifier, unsigned int plane);
1132
1133 static inline bool
1134 intel_rotation_90_or_270(unsigned int rotation)
1135 {
1136         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1137 }
1138
1139 void intel_create_rotation_property(struct drm_device *dev,
1140                                         struct intel_plane *plane);
1141
1142 /* shared dpll functions */
1143 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1144 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1145                         struct intel_shared_dpll *pll,
1146                         bool state);
1147 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1148 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1149 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1150                                                 struct intel_crtc_state *state);
1151
1152 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1153                       const struct dpll *dpll);
1154 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1155
1156 /* modesetting asserts */
1157 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1158                            enum pipe pipe);
1159 void assert_pll(struct drm_i915_private *dev_priv,
1160                 enum pipe pipe, bool state);
1161 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1162 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1163 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1164                        enum pipe pipe, bool state);
1165 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1166 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1167 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1168 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1169 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1170 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1171                                              int *x, int *y,
1172                                              unsigned int tiling_mode,
1173                                              unsigned int bpp,
1174                                              unsigned int pitch);
1175 void intel_prepare_reset(struct drm_device *dev);
1176 void intel_finish_reset(struct drm_device *dev);
1177 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1178 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1179 void broxton_init_cdclk(struct drm_device *dev);
1180 void broxton_uninit_cdclk(struct drm_device *dev);
1181 void broxton_ddi_phy_init(struct drm_device *dev);
1182 void broxton_ddi_phy_uninit(struct drm_device *dev);
1183 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1184 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1185 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1186 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1187 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1188 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1189 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1190 void intel_dp_get_m_n(struct intel_crtc *crtc,
1191                       struct intel_crtc_state *pipe_config);
1192 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1193 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1194 void
1195 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1196                                 int dotclock);
1197 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1198                         intel_clock_t *best_clock);
1199 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1200
1201 bool intel_crtc_active(struct drm_crtc *crtc);
1202 void hsw_enable_ips(struct intel_crtc *crtc);
1203 void hsw_disable_ips(struct intel_crtc *crtc);
1204 enum intel_display_power_domain
1205 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1206 enum intel_display_power_domain
1207 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1208 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1209                                  struct intel_crtc_state *pipe_config);
1210 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1211
1212 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1213 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1214
1215 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1216                            struct drm_i915_gem_object *obj,
1217                            unsigned int plane);
1218
1219 u32 skl_plane_ctl_format(uint32_t pixel_format);
1220 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1221 u32 skl_plane_ctl_rotation(unsigned int rotation);
1222
1223 /* intel_csr.c */
1224 void intel_csr_ucode_init(struct drm_i915_private *);
1225 void intel_csr_load_program(struct drm_i915_private *);
1226 void intel_csr_ucode_fini(struct drm_i915_private *);
1227
1228 /* intel_dp.c */
1229 void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1230 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1231                              struct intel_connector *intel_connector);
1232 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1233                               const struct intel_crtc_state *pipe_config);
1234 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1235 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1236 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1237 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1238 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1239 bool intel_dp_compute_config(struct intel_encoder *encoder,
1240                              struct intel_crtc_state *pipe_config);
1241 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1242 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1243                                   bool long_hpd);
1244 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1245 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1246 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1247 void intel_edp_panel_on(struct intel_dp *intel_dp);
1248 void intel_edp_panel_off(struct intel_dp *intel_dp);
1249 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1250 void intel_dp_mst_suspend(struct drm_device *dev);
1251 void intel_dp_mst_resume(struct drm_device *dev);
1252 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1253 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1254 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1255 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1256 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1257 void intel_plane_destroy(struct drm_plane *plane);
1258 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1259 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1260 void intel_edp_drrs_invalidate(struct drm_device *dev,
1261                 unsigned frontbuffer_bits);
1262 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1263 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1264                                          struct intel_digital_port *port);
1265 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1266
1267 void
1268 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1269                                        uint8_t dp_train_pat);
1270 void
1271 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1272 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1273 uint8_t
1274 intel_dp_voltage_max(struct intel_dp *intel_dp);
1275 uint8_t
1276 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1277 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1278                            uint8_t *link_bw, uint8_t *rate_select);
1279 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1280 bool
1281 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1282
1283 /* intel_dp_mst.c */
1284 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1285 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1286 /* intel_dsi.c */
1287 void intel_dsi_init(struct drm_device *dev);
1288
1289
1290 /* intel_dvo.c */
1291 void intel_dvo_init(struct drm_device *dev);
1292
1293
1294 /* legacy fbdev emulation in intel_fbdev.c */
1295 #ifdef CONFIG_DRM_FBDEV_EMULATION
1296 extern int intel_fbdev_init(struct drm_device *dev);
1297 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1298 extern void intel_fbdev_fini(struct drm_device *dev);
1299 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1300 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1301 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1302 #else
1303 static inline int intel_fbdev_init(struct drm_device *dev)
1304 {
1305         return 0;
1306 }
1307
1308 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1309 {
1310 }
1311
1312 static inline void intel_fbdev_fini(struct drm_device *dev)
1313 {
1314 }
1315
1316 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1317 {
1318 }
1319
1320 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1321 {
1322 }
1323 #endif
1324
1325 /* intel_fbc.c */
1326 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1327 void intel_fbc_deactivate(struct intel_crtc *crtc);
1328 void intel_fbc_update(struct intel_crtc *crtc);
1329 void intel_fbc_init(struct drm_i915_private *dev_priv);
1330 void intel_fbc_enable(struct intel_crtc *crtc);
1331 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1332 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1333 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1334                           unsigned int frontbuffer_bits,
1335                           enum fb_op_origin origin);
1336 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1337                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1338 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1339
1340 /* intel_hdmi.c */
1341 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1342 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1343                                struct intel_connector *intel_connector);
1344 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1345 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1346                                struct intel_crtc_state *pipe_config);
1347
1348
1349 /* intel_lvds.c */
1350 void intel_lvds_init(struct drm_device *dev);
1351 bool intel_is_dual_link_lvds(struct drm_device *dev);
1352
1353
1354 /* intel_modes.c */
1355 int intel_connector_update_modes(struct drm_connector *connector,
1356                                  struct edid *edid);
1357 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1358 void intel_attach_force_audio_property(struct drm_connector *connector);
1359 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1360 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1361
1362
1363 /* intel_overlay.c */
1364 void intel_setup_overlay(struct drm_device *dev);
1365 void intel_cleanup_overlay(struct drm_device *dev);
1366 int intel_overlay_switch_off(struct intel_overlay *overlay);
1367 int intel_overlay_put_image(struct drm_device *dev, void *data,
1368                             struct drm_file *file_priv);
1369 int intel_overlay_attrs(struct drm_device *dev, void *data,
1370                         struct drm_file *file_priv);
1371 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1372
1373
1374 /* intel_panel.c */
1375 int intel_panel_init(struct intel_panel *panel,
1376                      struct drm_display_mode *fixed_mode,
1377                      struct drm_display_mode *downclock_mode);
1378 void intel_panel_fini(struct intel_panel *panel);
1379 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1380                             struct drm_display_mode *adjusted_mode);
1381 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1382                              struct intel_crtc_state *pipe_config,
1383                              int fitting_mode);
1384 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1385                               struct intel_crtc_state *pipe_config,
1386                               int fitting_mode);
1387 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1388                                     u32 level, u32 max);
1389 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1390 void intel_panel_enable_backlight(struct intel_connector *connector);
1391 void intel_panel_disable_backlight(struct intel_connector *connector);
1392 void intel_panel_destroy_backlight(struct drm_connector *connector);
1393 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1394 extern struct drm_display_mode *intel_find_panel_downclock(
1395                                 struct drm_device *dev,
1396                                 struct drm_display_mode *fixed_mode,
1397                                 struct drm_connector *connector);
1398 void intel_backlight_register(struct drm_device *dev);
1399 void intel_backlight_unregister(struct drm_device *dev);
1400
1401
1402 /* intel_psr.c */
1403 void intel_psr_enable(struct intel_dp *intel_dp);
1404 void intel_psr_disable(struct intel_dp *intel_dp);
1405 void intel_psr_invalidate(struct drm_device *dev,
1406                           unsigned frontbuffer_bits);
1407 void intel_psr_flush(struct drm_device *dev,
1408                      unsigned frontbuffer_bits,
1409                      enum fb_op_origin origin);
1410 void intel_psr_init(struct drm_device *dev);
1411 void intel_psr_single_frame_update(struct drm_device *dev,
1412                                    unsigned frontbuffer_bits);
1413
1414 /* intel_runtime_pm.c */
1415 int intel_power_domains_init(struct drm_i915_private *);
1416 void intel_power_domains_fini(struct drm_i915_private *);
1417 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1418 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1419 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
1420 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
1421 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1422 const char *
1423 intel_display_power_domain_str(enum intel_display_power_domain domain);
1424
1425 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1426                                     enum intel_display_power_domain domain);
1427 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1428                                       enum intel_display_power_domain domain);
1429 void intel_display_power_get(struct drm_i915_private *dev_priv,
1430                              enum intel_display_power_domain domain);
1431 void intel_display_power_put(struct drm_i915_private *dev_priv,
1432                              enum intel_display_power_domain domain);
1433
1434 static inline void
1435 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1436 {
1437         WARN_ONCE(dev_priv->pm.suspended,
1438                   "Device suspended during HW access\n");
1439 }
1440
1441 static inline void
1442 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1443 {
1444         assert_rpm_device_not_suspended(dev_priv);
1445         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1446          * too much noise. */
1447         if (!atomic_read(&dev_priv->pm.wakeref_count))
1448                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1449 }
1450
1451 static inline int
1452 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1453 {
1454         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1455
1456         assert_rpm_wakelock_held(dev_priv);
1457
1458         return seq;
1459 }
1460
1461 static inline void
1462 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1463 {
1464         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1465                   "HW access outside of RPM atomic section\n");
1466 }
1467
1468 /**
1469  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1470  * @dev_priv: i915 device instance
1471  *
1472  * This function disable asserts that check if we hold an RPM wakelock
1473  * reference, while keeping the device-not-suspended checks still enabled.
1474  * It's meant to be used only in special circumstances where our rule about
1475  * the wakelock refcount wrt. the device power state doesn't hold. According
1476  * to this rule at any point where we access the HW or want to keep the HW in
1477  * an active state we must hold an RPM wakelock reference acquired via one of
1478  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1479  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1480  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1481  * users should avoid using this function.
1482  *
1483  * Any calls to this function must have a symmetric call to
1484  * enable_rpm_wakeref_asserts().
1485  */
1486 static inline void
1487 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1488 {
1489         atomic_inc(&dev_priv->pm.wakeref_count);
1490 }
1491
1492 /**
1493  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1494  * @dev_priv: i915 device instance
1495  *
1496  * This function re-enables the RPM assert checks after disabling them with
1497  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1498  * circumstances otherwise its use should be avoided.
1499  *
1500  * Any calls to this function must have a symmetric call to
1501  * disable_rpm_wakeref_asserts().
1502  */
1503 static inline void
1504 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1505 {
1506         atomic_dec(&dev_priv->pm.wakeref_count);
1507 }
1508
1509 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1510 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)   \
1511         disable_rpm_wakeref_asserts(dev_priv)
1512
1513 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)    \
1514         enable_rpm_wakeref_asserts(dev_priv)
1515
1516 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1517 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1518 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1519
1520 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1521
1522 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1523                              bool override, unsigned int mask);
1524 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1525                           enum dpio_channel ch, bool override);
1526
1527
1528 /* intel_pm.c */
1529 void intel_init_clock_gating(struct drm_device *dev);
1530 void intel_suspend_hw(struct drm_device *dev);
1531 int ilk_wm_max_level(const struct drm_device *dev);
1532 void intel_update_watermarks(struct drm_crtc *crtc);
1533 void intel_init_pm(struct drm_device *dev);
1534 void intel_pm_setup(struct drm_device *dev);
1535 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1536 void intel_gpu_ips_teardown(void);
1537 void intel_init_gt_powersave(struct drm_device *dev);
1538 void intel_cleanup_gt_powersave(struct drm_device *dev);
1539 void intel_enable_gt_powersave(struct drm_device *dev);
1540 void intel_disable_gt_powersave(struct drm_device *dev);
1541 void intel_suspend_gt_powersave(struct drm_device *dev);
1542 void intel_reset_gt_powersave(struct drm_device *dev);
1543 void gen6_update_ring_freq(struct drm_device *dev);
1544 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1545 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1546 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1547 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1548                     struct intel_rps_client *rps,
1549                     unsigned long submitted);
1550 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1551                                        struct drm_i915_gem_request *req);
1552 void vlv_wm_get_hw_state(struct drm_device *dev);
1553 void ilk_wm_get_hw_state(struct drm_device *dev);
1554 void skl_wm_get_hw_state(struct drm_device *dev);
1555 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1556                           struct skl_ddb_allocation *ddb /* out */);
1557 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1558
1559 /* intel_sdvo.c */
1560 bool intel_sdvo_init(struct drm_device *dev,
1561                      i915_reg_t reg, enum port port);
1562
1563
1564 /* intel_sprite.c */
1565 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1566 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1567                               struct drm_file *file_priv);
1568 void intel_pipe_update_start(struct intel_crtc *crtc);
1569 void intel_pipe_update_end(struct intel_crtc *crtc);
1570
1571 /* intel_tv.c */
1572 void intel_tv_init(struct drm_device *dev);
1573
1574 /* intel_atomic.c */
1575 int intel_connector_atomic_get_property(struct drm_connector *connector,
1576                                         const struct drm_connector_state *state,
1577                                         struct drm_property *property,
1578                                         uint64_t *val);
1579 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1580 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1581                                struct drm_crtc_state *state);
1582 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1583 void intel_atomic_state_clear(struct drm_atomic_state *);
1584 struct intel_shared_dpll_config *
1585 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1586
1587 static inline struct intel_crtc_state *
1588 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1589                             struct intel_crtc *crtc)
1590 {
1591         struct drm_crtc_state *crtc_state;
1592         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1593         if (IS_ERR(crtc_state))
1594                 return ERR_CAST(crtc_state);
1595
1596         return to_intel_crtc_state(crtc_state);
1597 }
1598 int intel_atomic_setup_scalers(struct drm_device *dev,
1599         struct intel_crtc *intel_crtc,
1600         struct intel_crtc_state *crtc_state);
1601
1602 /* intel_atomic_plane.c */
1603 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1604 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1605 void intel_plane_destroy_state(struct drm_plane *plane,
1606                                struct drm_plane_state *state);
1607 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1608
1609 #endif /* __INTEL_DRV_H__ */