drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <drm/drm_mipi_dsi.h>
  33 #include <linux/slab.h>
  34 #include <linux/gpio/consumer.h>
  35 #include "i915_drv.h"
  36 #include "intel_drv.h"
  37 #include "intel_dsi.h"
  38
  39 static const struct {
  40         u16 panel_id;
  41         struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
  42 } intel_dsi_drivers[] = {
  43         {
  44                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  45                 .init = vbt_panel_init,
  46         },
  47 };
  48
  49 /* return pixels in terms of txbyteclkhs */
  50 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  51                        u16 burst_mode_ratio)
  52 {
  53         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  54                                          8 * 100), lane_count);
  55 }
  56
  57 /* return pixels equvalent to txbyteclkhs */
  58 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  59                         u16 burst_mode_ratio)
  60 {
  61         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  62                                                 (bpp * burst_mode_ratio));
  63 }
  64
  65 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  66 {
  67         /* It just so happens the VBT matches register contents. */
  68         switch (fmt) {
  69         case VID_MODE_FORMAT_RGB888:
  70                 return MIPI_DSI_FMT_RGB888;
  71         case VID_MODE_FORMAT_RGB666:
  72                 return MIPI_DSI_FMT_RGB666;
  73         case VID_MODE_FORMAT_RGB666_PACKED:
  74                 return MIPI_DSI_FMT_RGB666_PACKED;
  75         case VID_MODE_FORMAT_RGB565:
  76                 return MIPI_DSI_FMT_RGB565;
  77         default:
  78                 MISSING_CASE(fmt);
  79                 return MIPI_DSI_FMT_RGB666;
  80         }
  81 }
  82
  83 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  84 {
  85         struct drm_encoder *encoder = &intel_dsi->base.base;
  86         struct drm_device *dev = encoder->dev;
  87         struct drm_i915_private *dev_priv = to_i915(dev);
  88         u32 mask;
  89
  90         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  91                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  92
  93         if (intel_wait_for_register(dev_priv,
  94                                     MIPI_GEN_FIFO_STAT(port), mask, mask,
  95                                     100))
  96                 DRM_ERROR("DPI FIFOs are not empty\n");
  97 }
  98
  99 static void write_data(struct drm_i915_private *dev_priv,
 100                        i915_reg_t reg,
 101                        const u8 *data, u32 len)
 102 {
 103         u32 i, j;
 104
 105         for (i = 0; i < len; i += 4) {
 106                 u32 val = 0;
 107
 108                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 109                         val |= *data++ << 8 * j;
 110
 111                 I915_WRITE(reg, val);
 112         }
 113 }
 114
 115 static void read_data(struct drm_i915_private *dev_priv,
 116                       i915_reg_t reg,
 117                       u8 *data, u32 len)
 118 {
 119         u32 i, j;
 120
 121         for (i = 0; i < len; i += 4) {
 122                 u32 val = I915_READ(reg);
 123
 124                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 125                         *data++ = val >> 8 * j;
 126         }
 127 }
 128
 129 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 130                                        const struct mipi_dsi_msg *msg)
 131 {
 132         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 133         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 134         struct drm_i915_private *dev_priv = to_i915(dev);
 135         enum port port = intel_dsi_host->port;
 136         struct mipi_dsi_packet packet;
 137         ssize_t ret;
 138         const u8 *header, *data;
 139         i915_reg_t data_reg, ctrl_reg;
 140         u32 data_mask, ctrl_mask;
 141
 142         ret = mipi_dsi_create_packet(&packet, msg);
 143         if (ret < 0)
 144                 return ret;
 145
 146         header = packet.header;
 147         data = packet.payload;
 148
 149         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 150                 data_reg = MIPI_LP_GEN_DATA(port);
 151                 data_mask = LP_DATA_FIFO_FULL;
 152                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 153                 ctrl_mask = LP_CTRL_FIFO_FULL;
 154         } else {
 155                 data_reg = MIPI_HS_GEN_DATA(port);
 156                 data_mask = HS_DATA_FIFO_FULL;
 157                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 158                 ctrl_mask = HS_CTRL_FIFO_FULL;
 159         }
 160
 161         /* note: this is never true for reads */
 162         if (packet.payload_length) {
 163                 if (intel_wait_for_register(dev_priv,
 164                                             MIPI_GEN_FIFO_STAT(port),
 165                                             data_mask, 0,
 166                                             50))
 167                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 168
 169                 write_data(dev_priv, data_reg, packet.payload,
 170                            packet.payload_length);
 171         }
 172
 173         if (msg->rx_len) {
 174                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 175         }
 176
 177         if (intel_wait_for_register(dev_priv,
 178                                     MIPI_GEN_FIFO_STAT(port),
 179                                     ctrl_mask, 0,
 180                                     50)) {
 181                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 182         }
 183
 184         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 185
 186         /* ->rx_len is set only for reads */
 187         if (msg->rx_len) {
 188                 data_mask = GEN_READ_DATA_AVAIL;
 189                 if (intel_wait_for_register(dev_priv,
 190                                             MIPI_INTR_STAT(port),
 191                                             data_mask, data_mask,
 192                                             50))
 193                         DRM_ERROR("Timeout waiting for read data.\n");
 194
 195                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 196         }
 197
 198         /* XXX: fix for reads and writes */
 199         return 4 + packet.payload_length;
 200 }
 201
 202 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 203                                  struct mipi_dsi_device *dsi)
 204 {
 205         return 0;
 206 }
 207
 208 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 209                                  struct mipi_dsi_device *dsi)
 210 {
 211         return 0;
 212 }
 213
 214 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 215         .attach = intel_dsi_host_attach,
 216         .detach = intel_dsi_host_detach,
 217         .transfer = intel_dsi_host_transfer,
 218 };
 219
 220 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 221                                                   enum port port)
 222 {
 223         struct intel_dsi_host *host;
 224         struct mipi_dsi_device *device;
 225
 226         host = kzalloc(sizeof(*host), GFP_KERNEL);
 227         if (!host)
 228                 return NULL;
 229
 230         host->base.ops = &intel_dsi_host_ops;
 231         host->intel_dsi = intel_dsi;
 232         host->port = port;
 233
 234         /*
 235          * We should call mipi_dsi_host_register(&host->base) here, but we don't
 236          * have a host->dev, and we don't have OF stuff either. So just use the
 237          * dsi framework as a library and hope for the best. Create the dsi
 238          * devices by ourselves here too. Need to be careful though, because we
 239          * don't initialize any of the driver model devices here.
 240          */
 241         device = kzalloc(sizeof(*device), GFP_KERNEL);
 242         if (!device) {
 243                 kfree(host);
 244                 return NULL;
 245         }
 246
 247         device->host = &host->base;
 248         host->device = device;
 249
 250         return host;
 251 }
 252
 253 /*
 254  * send a video mode command
 255  *
 256  * XXX: commands with data in MIPI_DPI_DATA?
 257  */
 258 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 259                         enum port port)
 260 {
 261         struct drm_encoder *encoder = &intel_dsi->base.base;
 262         struct drm_device *dev = encoder->dev;
 263         struct drm_i915_private *dev_priv = to_i915(dev);
 264         u32 mask;
 265
 266         /* XXX: pipe, hs */
 267         if (hs)
 268                 cmd &= ~DPI_LP_MODE;
 269         else
 270                 cmd |= DPI_LP_MODE;
 271
 272         /* clear bit */
 273         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 274
 275         /* XXX: old code skips write if control unchanged */
 276         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 277                 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 278
 279         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 280
 281         mask = SPL_PKT_SENT_INTERRUPT;
 282         if (intel_wait_for_register(dev_priv,
 283                                     MIPI_INTR_STAT(port), mask, mask,
 284                                     100))
 285                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 286
 287         return 0;
 288 }
 289
 290 static void band_gap_reset(struct drm_i915_private *dev_priv)
 291 {
 292         mutex_lock(&dev_priv->sb_lock);
 293
 294         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 295         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 296         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 297         udelay(150);
 298         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 299         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 300
 301         mutex_unlock(&dev_priv->sb_lock);
 302 }
 303
 304 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
 305 {
 306         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
 307 }
 308
 309 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 310 {
 311         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 312 }
 313
 314 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 315                                      struct intel_crtc_state *pipe_config)
 316 {
 317         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 318         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 319                                                    base);
 320         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 321         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 322         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 323         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 324         int ret;
 325
 326         DRM_DEBUG_KMS("\n");
 327
 328         if (fixed_mode) {
 329                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 330
 331                 if (HAS_GMCH_DISPLAY(dev_priv))
 332                         intel_gmch_panel_fitting(crtc, pipe_config,
 333                                                  intel_connector->panel.fitting_mode);
 334                 else
 335                         intel_pch_panel_fitting(crtc, pipe_config,
 336                                                 intel_connector->panel.fitting_mode);
 337         }
 338
 339         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 340         adjusted_mode->flags = 0;
 341
 342         if (IS_BROXTON(dev_priv)) {
 343                 /* Dual link goes to DSI transcoder A. */
 344                 if (intel_dsi->ports == BIT(PORT_C))
 345                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 346                 else
 347                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 348         }
 349
 350         ret = intel_compute_dsi_pll(encoder, pipe_config);
 351         if (ret)
 352                 return false;
 353
 354         pipe_config->clock_set = true;
 355
 356         return true;
 357 }
 358
 359 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 360 {
 361         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 362         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 363         enum port port;
 364         u32 val;
 365
 366         DRM_DEBUG_KMS("\n");
 367
 368         /* Exit Low power state in 4 steps*/
 369         for_each_dsi_port(port, intel_dsi->ports) {
 370
 371                 /* 1. Enable MIPI PHY transparent latch */
 372                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 373                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 374                 usleep_range(2000, 2500);
 375
 376                 /* 2. Enter ULPS */
 377                 val = I915_READ(MIPI_DEVICE_READY(port));
 378                 val &= ~ULPS_STATE_MASK;
 379                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 380                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 381                 usleep_range(2, 3);
 382
 383                 /* 3. Exit ULPS */
 384                 val = I915_READ(MIPI_DEVICE_READY(port));
 385                 val &= ~ULPS_STATE_MASK;
 386                 val |= (ULPS_STATE_EXIT | DEVICE_READY);
 387                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 388                 usleep_range(1000, 1500);
 389
 390                 /* Clear ULPS and set device ready */
 391                 val = I915_READ(MIPI_DEVICE_READY(port));
 392                 val &= ~ULPS_STATE_MASK;
 393                 val |= DEVICE_READY;
 394                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 395         }
 396 }
 397
 398 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 399 {
 400         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 401         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 402         enum port port;
 403         u32 val;
 404
 405         DRM_DEBUG_KMS("\n");
 406
 407         mutex_lock(&dev_priv->sb_lock);
 408         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 409          * needed everytime after power gate */
 410         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 411         mutex_unlock(&dev_priv->sb_lock);
 412
 413         /* bandgap reset is needed after everytime we do power gate */
 414         band_gap_reset(dev_priv);
 415
 416         for_each_dsi_port(port, intel_dsi->ports) {
 417
 418                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 419                 usleep_range(2500, 3000);
 420
 421                 /* Enable MIPI PHY transparent latch
 422                  * Common bit for both MIPI Port A & MIPI Port C
 423                  * No similar bit in MIPI Port C reg
 424                  */
 425                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 426                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 427                 usleep_range(1000, 1500);
 428
 429                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 430                 usleep_range(2500, 3000);
 431
 432                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 433                 usleep_range(2500, 3000);
 434         }
 435 }
 436
 437 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 438 {
 439         struct drm_device *dev = encoder->base.dev;
 440
 441         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 442                 vlv_dsi_device_ready(encoder);
 443         else if (IS_BROXTON(dev))
 444                 bxt_dsi_device_ready(encoder);
 445 }
 446
 447 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 448 {
 449         struct drm_device *dev = encoder->base.dev;
 450         struct drm_i915_private *dev_priv = to_i915(dev);
 451         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 452         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 453         enum port port;
 454
 455         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 456                 u32 temp;
 457
 458                 temp = I915_READ(VLV_CHICKEN_3);
 459                 temp &= ~PIXEL_OVERLAP_CNT_MASK |
 460                                         intel_dsi->pixel_overlap <<
 461                                         PIXEL_OVERLAP_CNT_SHIFT;
 462                 I915_WRITE(VLV_CHICKEN_3, temp);
 463         }
 464
 465         for_each_dsi_port(port, intel_dsi->ports) {
 466                 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
 467                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 468                 u32 temp;
 469
 470                 temp = I915_READ(port_ctrl);
 471
 472                 temp &= ~LANE_CONFIGURATION_MASK;
 473                 temp &= ~DUAL_LINK_MODE_MASK;
 474
 475                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 476                         temp |= (intel_dsi->dual_link - 1)
 477                                                 << DUAL_LINK_MODE_SHIFT;
 478                         temp |= intel_crtc->pipe ?
 479                                         LANE_CONFIGURATION_DUAL_LINK_B :
 480                                         LANE_CONFIGURATION_DUAL_LINK_A;
 481                 }
 482                 /* assert ip_tg_enable signal */
 483                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 484                 POSTING_READ(port_ctrl);
 485         }
 486 }
 487
 488 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 489 {
 490         struct drm_device *dev = encoder->base.dev;
 491         struct drm_i915_private *dev_priv = to_i915(dev);
 492         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 493         enum port port;
 494
 495         for_each_dsi_port(port, intel_dsi->ports) {
 496                 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
 497                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 498                 u32 temp;
 499
 500                 /* de-assert ip_tg_enable signal */
 501                 temp = I915_READ(port_ctrl);
 502                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 503                 POSTING_READ(port_ctrl);
 504         }
 505 }
 506
 507 static void intel_dsi_enable(struct intel_encoder *encoder)
 508 {
 509         struct drm_device *dev = encoder->base.dev;
 510         struct drm_i915_private *dev_priv = to_i915(dev);
 511         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 512         enum port port;
 513
 514         DRM_DEBUG_KMS("\n");
 515
 516         if (is_cmd_mode(intel_dsi)) {
 517                 for_each_dsi_port(port, intel_dsi->ports)
 518                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 519         } else {
 520                 msleep(20); /* XXX */
 521                 for_each_dsi_port(port, intel_dsi->ports)
 522                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 523                 msleep(100);
 524
 525                 drm_panel_enable(intel_dsi->panel);
 526
 527                 for_each_dsi_port(port, intel_dsi->ports)
 528                         wait_for_dsi_fifo_empty(intel_dsi, port);
 529
 530                 intel_dsi_port_enable(encoder);
 531         }
 532
 533         intel_panel_enable_backlight(intel_dsi->attached_connector);
 534 }
 535
 536 static void intel_dsi_prepare(struct intel_encoder *intel_encoder);
 537
 538 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 539 {
 540         struct drm_device *dev = encoder->base.dev;
 541         struct drm_i915_private *dev_priv = to_i915(dev);
 542         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 543         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 544         enum port port;
 545
 546         DRM_DEBUG_KMS("\n");
 547
 548         /*
 549          * The BIOS may leave the PLL in a wonky state where it doesn't
 550          * lock. It needs to be fully powered down to fix it.
 551          */
 552         intel_disable_dsi_pll(encoder);
 553         intel_enable_dsi_pll(encoder, crtc->config);
 554
 555         intel_dsi_prepare(encoder);
 556
 557         /* Panel Enable over CRC PMIC */
 558         if (intel_dsi->gpio_panel)
 559                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 560
 561         msleep(intel_dsi->panel_on_delay);
 562
 563         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 564                 u32 val;
 565
 566                 /* Disable DPOunit clock gating, can stall pipe */
 567                 val = I915_READ(DSPCLK_GATE_D);
 568                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 569                 I915_WRITE(DSPCLK_GATE_D, val);
 570         }
 571
 572         /* put device in ready state */
 573         intel_dsi_device_ready(encoder);
 574
 575         drm_panel_prepare(intel_dsi->panel);
 576
 577         for_each_dsi_port(port, intel_dsi->ports)
 578                 wait_for_dsi_fifo_empty(intel_dsi, port);
 579
 580         /* Enable port in pre-enable phase itself because as per hw team
 581          * recommendation, port should be enabled befor plane & pipe */
 582         intel_dsi_enable(encoder);
 583 }
 584
 585 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 586 {
 587         DRM_DEBUG_KMS("\n");
 588
 589         /* for DSI port enable has to be done before pipe
 590          * and plane enable, so port enable is done in
 591          * pre_enable phase itself unlike other encoders
 592          */
 593 }
 594
 595 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 596 {
 597         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 598         enum port port;
 599
 600         DRM_DEBUG_KMS("\n");
 601
 602         intel_panel_disable_backlight(intel_dsi->attached_connector);
 603
 604         if (is_vid_mode(intel_dsi)) {
 605                 /* Send Shutdown command to the panel in LP mode */
 606                 for_each_dsi_port(port, intel_dsi->ports)
 607                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 608                 msleep(10);
 609         }
 610 }
 611
 612 static void intel_dsi_disable(struct intel_encoder *encoder)
 613 {
 614         struct drm_device *dev = encoder->base.dev;
 615         struct drm_i915_private *dev_priv = to_i915(dev);
 616         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 617         enum port port;
 618         u32 temp;
 619
 620         DRM_DEBUG_KMS("\n");
 621
 622         if (is_vid_mode(intel_dsi)) {
 623                 for_each_dsi_port(port, intel_dsi->ports)
 624                         wait_for_dsi_fifo_empty(intel_dsi, port);
 625
 626                 intel_dsi_port_disable(encoder);
 627                 msleep(2);
 628         }
 629
 630         for_each_dsi_port(port, intel_dsi->ports) {
 631                 /* Panel commands can be sent when clock is in LP11 */
 632                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 633
 634                 intel_dsi_reset_clocks(encoder, port);
 635                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 636
 637                 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 638                 temp &= ~VID_MODE_FORMAT_MASK;
 639                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 640
 641                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
 642         }
 643         /* if disable packets are sent before sending shutdown packet then in
 644          * some next enable sequence send turn on packet error is observed */
 645         drm_panel_disable(intel_dsi->panel);
 646
 647         for_each_dsi_port(port, intel_dsi->ports)
 648                 wait_for_dsi_fifo_empty(intel_dsi, port);
 649 }
 650
 651 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 652 {
 653         struct drm_device *dev = encoder->base.dev;
 654         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 655         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 656         enum port port;
 657
 658         DRM_DEBUG_KMS("\n");
 659         for_each_dsi_port(port, intel_dsi->ports) {
 660                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 661                 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
 662                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 663                 u32 val;
 664
 665                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 666                                                         ULPS_STATE_ENTER);
 667                 usleep_range(2000, 2500);
 668
 669                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 670                                                         ULPS_STATE_EXIT);
 671                 usleep_range(2000, 2500);
 672
 673                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 674                                                         ULPS_STATE_ENTER);
 675                 usleep_range(2000, 2500);
 676
 677                 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
 678                  * only. MIPI Port C has no similar bit for checking
 679                  */
 680                 if (intel_wait_for_register(dev_priv,
 681                                             port_ctrl, AFE_LATCHOUT, 0,
 682                                             30))
 683                         DRM_ERROR("DSI LP not going Low\n");
 684
 685                 /* Disable MIPI PHY transparent latch */
 686                 val = I915_READ(port_ctrl);
 687                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 688                 usleep_range(1000, 1500);
 689
 690                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 691                 usleep_range(2000, 2500);
 692         }
 693
 694         intel_disable_dsi_pll(encoder);
 695 }
 696
 697 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 698 {
 699         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 700         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 701
 702         DRM_DEBUG_KMS("\n");
 703
 704         intel_dsi_disable(encoder);
 705
 706         intel_dsi_clear_device_ready(encoder);
 707
 708         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 709                 u32 val;
 710
 711                 val = I915_READ(DSPCLK_GATE_D);
 712                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 713                 I915_WRITE(DSPCLK_GATE_D, val);
 714         }
 715
 716         drm_panel_unprepare(intel_dsi->panel);
 717
 718         msleep(intel_dsi->panel_off_delay);
 719
 720         /* Panel Disable over CRC PMIC */
 721         if (intel_dsi->gpio_panel)
 722                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 723
 724         /*
 725          * FIXME As we do with eDP, just make a note of the time here
 726          * and perform the wait before the next panel power on.
 727          */
 728         msleep(intel_dsi->panel_pwr_cycle_delay);
 729 }
 730
 731 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 732                                    enum pipe *pipe)
 733 {
 734         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 735         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 736         struct drm_device *dev = encoder->base.dev;
 737         enum intel_display_power_domain power_domain;
 738         enum port port;
 739         bool active = false;
 740
 741         DRM_DEBUG_KMS("\n");
 742
 743         power_domain = intel_display_port_power_domain(encoder);
 744         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 745                 return false;
 746
 747         /*
 748          * On Broxton the PLL needs to be enabled with a valid divider
 749          * configuration, otherwise accessing DSI registers will hang the
 750          * machine. See BSpec North Display Engine registers/MIPI[BXT].
 751          */
 752         if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
 753                 goto out_put_power;
 754
 755         /* XXX: this only works for one DSI output */
 756         for_each_dsi_port(port, intel_dsi->ports) {
 757                 i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
 758                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 759                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 760
 761                 /*
 762                  * Due to some hardware limitations on VLV/CHV, the DPI enable
 763                  * bit in port C control register does not get set. As a
 764                  * workaround, check pipe B conf instead.
 765                  */
 766                 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && port == PORT_C)
 767                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
 768
 769                 /* Try command mode if video mode not enabled */
 770                 if (!enabled) {
 771                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 772                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
 773                 }
 774
 775                 if (!enabled)
 776                         continue;
 777
 778                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
 779                         continue;
 780
 781                 if (IS_BROXTON(dev_priv)) {
 782                         u32 tmp = I915_READ(MIPI_CTRL(port));
 783                         tmp &= BXT_PIPE_SELECT_MASK;
 784                         tmp >>= BXT_PIPE_SELECT_SHIFT;
 785
 786                         if (WARN_ON(tmp > PIPE_C))
 787                                 continue;
 788
 789                         *pipe = tmp;
 790                 } else {
 791                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
 792                 }
 793
 794                 active = true;
 795                 break;
 796         }
 797
 798 out_put_power:
 799         intel_display_power_put(dev_priv, power_domain);
 800
 801         return active;
 802 }
 803
 804 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
 805                                  struct intel_crtc_state *pipe_config)
 806 {
 807         struct drm_device *dev = encoder->base.dev;
 808         struct drm_i915_private *dev_priv = to_i915(dev);
 809         struct drm_display_mode *adjusted_mode =
 810                                         &pipe_config->base.adjusted_mode;
 811         struct drm_display_mode *adjusted_mode_sw;
 812         struct intel_crtc *intel_crtc;
 813         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 814         unsigned int lane_count = intel_dsi->lane_count;
 815         unsigned int bpp, fmt;
 816         enum port port;
 817         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 818         u16 hfp_sw, hsync_sw, hbp_sw;
 819         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
 820                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
 821
 822         intel_crtc = to_intel_crtc(encoder->base.crtc);
 823         adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode;
 824
 825         /*
 826          * Atleast one port is active as encoder->get_config called only if
 827          * encoder->get_hw_state() returns true.
 828          */
 829         for_each_dsi_port(port, intel_dsi->ports) {
 830                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
 831                         break;
 832         }
 833
 834         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
 835         pipe_config->pipe_bpp =
 836                         mipi_dsi_pixel_format_to_bpp(
 837                                 pixel_format_from_register_bits(fmt));
 838         bpp = pipe_config->pipe_bpp;
 839
 840         /* In terms of pixels */
 841         adjusted_mode->crtc_hdisplay =
 842                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
 843         adjusted_mode->crtc_vdisplay =
 844                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
 845         adjusted_mode->crtc_vtotal =
 846                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
 847
 848         hactive = adjusted_mode->crtc_hdisplay;
 849         hfp = I915_READ(MIPI_HFP_COUNT(port));
 850
 851         /*
 852          * Meaningful for video mode non-burst sync pulse mode only,
 853          * can be zero for non-burst sync events and burst modes
 854          */
 855         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
 856         hbp = I915_READ(MIPI_HBP_COUNT(port));
 857
 858         /* harizontal values are in terms of high speed byte clock */
 859         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
 860                                                 intel_dsi->burst_mode_ratio);
 861         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
 862                                                 intel_dsi->burst_mode_ratio);
 863         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
 864                                                 intel_dsi->burst_mode_ratio);
 865
 866         if (intel_dsi->dual_link) {
 867                 hfp *= 2;
 868                 hsync *= 2;
 869                 hbp *= 2;
 870         }
 871
 872         /* vertical values are in terms of lines */
 873         vfp = I915_READ(MIPI_VFP_COUNT(port));
 874         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
 875         vbp = I915_READ(MIPI_VBP_COUNT(port));
 876
 877         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
 878         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
 879         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
 880         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
 881         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
 882
 883         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
 884         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
 885         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
 886         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
 887
 888         /*
 889          * In BXT DSI there is no regs programmed with few horizontal timings
 890          * in Pixels but txbyteclkhs.. So retrieval process adds some
 891          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
 892          * Actually here for the given adjusted_mode, we are calculating the
 893          * value programmed to the port and then back to the horizontal timing
 894          * param in pixels. This is the expected value, including roundup errors
 895          * And if that is same as retrieved value from port, then
 896          * (HW state) adjusted_mode's horizontal timings are corrected to
 897          * match with SW state to nullify the errors.
 898          */
 899         /* Calculating the value programmed to the Port register */
 900         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
 901                                         adjusted_mode_sw->crtc_hdisplay;
 902         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
 903                                         adjusted_mode_sw->crtc_hsync_start;
 904         hbp_sw = adjusted_mode_sw->crtc_htotal -
 905                                         adjusted_mode_sw->crtc_hsync_end;
 906
 907         if (intel_dsi->dual_link) {
 908                 hfp_sw /= 2;
 909                 hsync_sw /= 2;
 910                 hbp_sw /= 2;
 911         }
 912
 913         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
 914                                                 intel_dsi->burst_mode_ratio);
 915         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
 916                             intel_dsi->burst_mode_ratio);
 917         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
 918                                                 intel_dsi->burst_mode_ratio);
 919
 920         /* Reverse calculating the adjusted mode parameters from port reg vals*/
 921         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
 922                                                 intel_dsi->burst_mode_ratio);
 923         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
 924                                                 intel_dsi->burst_mode_ratio);
 925         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
 926                                                 intel_dsi->burst_mode_ratio);
 927
 928         if (intel_dsi->dual_link) {
 929                 hfp_sw *= 2;
 930                 hsync_sw *= 2;
 931                 hbp_sw *= 2;
 932         }
 933
 934         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
 935                                                         hsync_sw + hbp_sw;
 936         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
 937         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
 938         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
 939         crtc_hblank_end_sw = crtc_htotal_sw;
 940
 941         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
 942                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
 943
 944         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
 945                 adjusted_mode->crtc_hsync_start =
 946                                         adjusted_mode_sw->crtc_hsync_start;
 947
 948         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
 949                 adjusted_mode->crtc_hsync_end =
 950                                         adjusted_mode_sw->crtc_hsync_end;
 951
 952         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
 953                 adjusted_mode->crtc_hblank_start =
 954                                         adjusted_mode_sw->crtc_hblank_start;
 955
 956         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
 957                 adjusted_mode->crtc_hblank_end =
 958                                         adjusted_mode_sw->crtc_hblank_end;
 959 }
 960
 961 static void intel_dsi_get_config(struct intel_encoder *encoder,
 962                                  struct intel_crtc_state *pipe_config)
 963 {
 964         struct drm_device *dev = encoder->base.dev;
 965         u32 pclk;
 966         DRM_DEBUG_KMS("\n");
 967
 968         if (IS_BROXTON(dev))
 969                 bxt_dsi_get_pipe_config(encoder, pipe_config);
 970
 971         pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
 972                                   pipe_config);
 973         if (!pclk)
 974                 return;
 975
 976         pipe_config->base.adjusted_mode.crtc_clock = pclk;
 977         pipe_config->port_clock = pclk;
 978 }
 979
 980 static enum drm_mode_status
 981 intel_dsi_mode_valid(struct drm_connector *connector,
 982                      struct drm_display_mode *mode)
 983 {
 984         struct intel_connector *intel_connector = to_intel_connector(connector);
 985         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 986         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 987
 988         DRM_DEBUG_KMS("\n");
 989
 990         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 991                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 992                 return MODE_NO_DBLESCAN;
 993         }
 994
 995         if (fixed_mode) {
 996                 if (mode->hdisplay > fixed_mode->hdisplay)
 997                         return MODE_PANEL;
 998                 if (mode->vdisplay > fixed_mode->vdisplay)
 999                         return MODE_PANEL;
1000                 if (fixed_mode->clock > max_dotclk)
1001                         return MODE_CLOCK_HIGH;
1002         }
1003
1004         return MODE_OK;
1005 }
1006
1007 /* return txclkesc cycles in terms of divider and duration in us */
1008 static u16 txclkesc(u32 divider, unsigned int us)
1009 {
1010         switch (divider) {
1011         case ESCAPE_CLOCK_DIVIDER_1:
1012         default:
1013                 return 20 * us;
1014         case ESCAPE_CLOCK_DIVIDER_2:
1015                 return 10 * us;
1016         case ESCAPE_CLOCK_DIVIDER_4:
1017                 return 5 * us;
1018         }
1019 }
1020
1021 static void set_dsi_timings(struct drm_encoder *encoder,
1022                             const struct drm_display_mode *adjusted_mode)
1023 {
1024         struct drm_device *dev = encoder->dev;
1025         struct drm_i915_private *dev_priv = to_i915(dev);
1026         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1027         enum port port;
1028         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1029         unsigned int lane_count = intel_dsi->lane_count;
1030
1031         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1032
1033         hactive = adjusted_mode->crtc_hdisplay;
1034         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1035         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1036         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1037
1038         if (intel_dsi->dual_link) {
1039                 hactive /= 2;
1040                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1041                         hactive += intel_dsi->pixel_overlap;
1042                 hfp /= 2;
1043                 hsync /= 2;
1044                 hbp /= 2;
1045         }
1046
1047         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1048         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1049         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1050
1051         /* horizontal values are in terms of high speed byte clock */
1052         hactive = txbyteclkhs(hactive, bpp, lane_count,
1053                               intel_dsi->burst_mode_ratio);
1054         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1055         hsync = txbyteclkhs(hsync, bpp, lane_count,
1056                             intel_dsi->burst_mode_ratio);
1057         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1058
1059         for_each_dsi_port(port, intel_dsi->ports) {
1060                 if (IS_BROXTON(dev)) {
1061                         /*
1062                          * Program hdisplay and vdisplay on MIPI transcoder.
1063                          * This is different from calculated hactive and
1064                          * vactive, as they are calculated per channel basis,
1065                          * whereas these values should be based on resolution.
1066                          */
1067                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1068                                    adjusted_mode->crtc_hdisplay);
1069                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1070                                    adjusted_mode->crtc_vdisplay);
1071                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1072                                    adjusted_mode->crtc_vtotal);
1073                 }
1074
1075                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1076                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1077
1078                 /* meaningful for video mode non-burst sync pulse mode only,
1079                  * can be zero for non-burst sync events and burst modes */
1080                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1081                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1082
1083                 /* vertical values are in terms of lines */
1084                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1085                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1086                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1087         }
1088 }
1089
1090 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1091 {
1092         switch (fmt) {
1093         case MIPI_DSI_FMT_RGB888:
1094                 return VID_MODE_FORMAT_RGB888;
1095         case MIPI_DSI_FMT_RGB666:
1096                 return VID_MODE_FORMAT_RGB666;
1097         case MIPI_DSI_FMT_RGB666_PACKED:
1098                 return VID_MODE_FORMAT_RGB666_PACKED;
1099         case MIPI_DSI_FMT_RGB565:
1100                 return VID_MODE_FORMAT_RGB565;
1101         default:
1102                 MISSING_CASE(fmt);
1103                 return VID_MODE_FORMAT_RGB666;
1104         }
1105 }
1106
1107 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
1108 {
1109         struct drm_encoder *encoder = &intel_encoder->base;
1110         struct drm_device *dev = encoder->dev;
1111         struct drm_i915_private *dev_priv = to_i915(dev);
1112         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
1113         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1114         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1115         enum port port;
1116         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1117         u32 val, tmp;
1118         u16 mode_hdisplay;
1119
1120         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1121
1122         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1123
1124         if (intel_dsi->dual_link) {
1125                 mode_hdisplay /= 2;
1126                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1127                         mode_hdisplay += intel_dsi->pixel_overlap;
1128         }
1129
1130         for_each_dsi_port(port, intel_dsi->ports) {
1131                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1132                         /*
1133                          * escape clock divider, 20MHz, shared for A and C.
1134                          * device ready must be off when doing this! txclkesc?
1135                          */
1136                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1137                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1138                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1139                                         ESCAPE_CLOCK_DIVIDER_1);
1140
1141                         /* read request priority is per pipe */
1142                         tmp = I915_READ(MIPI_CTRL(port));
1143                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1144                         I915_WRITE(MIPI_CTRL(port), tmp |
1145                                         READ_REQUEST_PRIORITY_HIGH);
1146                 } else if (IS_BROXTON(dev)) {
1147                         enum pipe pipe = intel_crtc->pipe;
1148
1149                         tmp = I915_READ(MIPI_CTRL(port));
1150                         tmp &= ~BXT_PIPE_SELECT_MASK;
1151
1152                         tmp |= BXT_PIPE_SELECT(pipe);
1153                         I915_WRITE(MIPI_CTRL(port), tmp);
1154                 }
1155
1156                 /* XXX: why here, why like this? handling in irq handler?! */
1157                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1158                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1159
1160                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1161
1162                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1163                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1164                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1165         }
1166
1167         set_dsi_timings(encoder, adjusted_mode);
1168
1169         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1170         if (is_cmd_mode(intel_dsi)) {
1171                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1172                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1173         } else {
1174                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1175                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1176         }
1177
1178         tmp = 0;
1179         if (intel_dsi->eotp_pkt == 0)
1180                 tmp |= EOT_DISABLE;
1181         if (intel_dsi->clock_stop)
1182                 tmp |= CLOCKSTOP;
1183
1184         if (IS_BROXTON(dev_priv)) {
1185                 tmp |= BXT_DPHY_DEFEATURE_EN;
1186                 if (!is_cmd_mode(intel_dsi))
1187                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1188         }
1189
1190         for_each_dsi_port(port, intel_dsi->ports) {
1191                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1192
1193                 /* timeouts for recovery. one frame IIUC. if counter expires,
1194                  * EOT and stop state. */
1195
1196                 /*
1197                  * In burst mode, value greater than one DPI line Time in byte
1198                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1199                  * said value is recommended.
1200                  *
1201                  * In non-burst mode, Value greater than one DPI frame time in
1202                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1203                  * said value is recommended.
1204                  *
1205                  * In DBI only mode, value greater than one DBI frame time in
1206                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1207                  * said value is recommended.
1208                  */
1209
1210                 if (is_vid_mode(intel_dsi) &&
1211                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1212                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1213                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1214                                             intel_dsi->lane_count,
1215                                             intel_dsi->burst_mode_ratio) + 1);
1216                 } else {
1217                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1218                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1219                                             adjusted_mode->crtc_htotal,
1220                                             bpp, intel_dsi->lane_count,
1221                                             intel_dsi->burst_mode_ratio) + 1);
1222                 }
1223                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1224                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1225                                                 intel_dsi->turn_arnd_val);
1226                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1227                                                 intel_dsi->rst_timer_val);
1228
1229                 /* dphy stuff */
1230
1231                 /* in terms of low power clock */
1232                 I915_WRITE(MIPI_INIT_COUNT(port),
1233                                 txclkesc(intel_dsi->escape_clk_div, 100));
1234
1235                 if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
1236                         /*
1237                          * BXT spec says write MIPI_INIT_COUNT for
1238                          * both the ports, even if only one is
1239                          * getting used. So write the other port
1240                          * if not in dual link mode.
1241                          */
1242                         I915_WRITE(MIPI_INIT_COUNT(port ==
1243                                                 PORT_A ? PORT_C : PORT_A),
1244                                         intel_dsi->init_count);
1245                 }
1246
1247                 /* recovery disables */
1248                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1249
1250                 /* in terms of low power clock */
1251                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1252
1253                 /* in terms of txbyteclkhs. actual high to low switch +
1254                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1255                  *
1256                  * XXX: write MIPI_STOP_STATE_STALL?
1257                  */
1258                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1259                                                 intel_dsi->hs_to_lp_count);
1260
1261                 /* XXX: low power clock equivalence in terms of byte clock.
1262                  * the number of byte clocks occupied in one low power clock.
1263                  * based on txbyteclkhs and txclkesc.
1264                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1265                  * ) / 105.???
1266                  */
1267                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1268
1269                 /* the bw essential for transmitting 16 long packets containing
1270                  * 252 bytes meant for dcs write memory command is programmed in
1271                  * this register in terms of byte clocks. based on dsi transfer
1272                  * rate and the number of lanes configured the time taken to
1273                  * transmit 16 long packets in a dsi stream varies. */
1274                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1275
1276                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1277                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1278                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1279
1280                 if (is_vid_mode(intel_dsi))
1281                         /* Some panels might have resolution which is not a
1282                          * multiple of 64 like 1366 x 768. Enable RANDOM
1283                          * resolution support for such panels by default */
1284                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1285                                 intel_dsi->video_frmt_cfg_bits |
1286                                 intel_dsi->video_mode_format |
1287                                 IP_TG_CONFIG |
1288                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1289         }
1290 }
1291
1292 static enum drm_connector_status
1293 intel_dsi_detect(struct drm_connector *connector, bool force)
1294 {
1295         return connector_status_connected;
1296 }
1297
1298 static int intel_dsi_get_modes(struct drm_connector *connector)
1299 {
1300         struct intel_connector *intel_connector = to_intel_connector(connector);
1301         struct drm_display_mode *mode;
1302
1303         DRM_DEBUG_KMS("\n");
1304
1305         if (!intel_connector->panel.fixed_mode) {
1306                 DRM_DEBUG_KMS("no fixed mode\n");
1307                 return 0;
1308         }
1309
1310         mode = drm_mode_duplicate(connector->dev,
1311                                   intel_connector->panel.fixed_mode);
1312         if (!mode) {
1313                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1314                 return 0;
1315         }
1316
1317         drm_mode_probed_add(connector, mode);
1318         return 1;
1319 }
1320
1321 static int intel_dsi_set_property(struct drm_connector *connector,
1322                                   struct drm_property *property,
1323                                   uint64_t val)
1324 {
1325         struct drm_device *dev = connector->dev;
1326         struct intel_connector *intel_connector = to_intel_connector(connector);
1327         struct drm_crtc *crtc;
1328         int ret;
1329
1330         ret = drm_object_property_set_value(&connector->base, property, val);
1331         if (ret)
1332                 return ret;
1333
1334         if (property == dev->mode_config.scaling_mode_property) {
1335                 if (val == DRM_MODE_SCALE_NONE) {
1336                         DRM_DEBUG_KMS("no scaling not supported\n");
1337                         return -EINVAL;
1338                 }
1339                 if (HAS_GMCH_DISPLAY(dev) &&
1340                     val == DRM_MODE_SCALE_CENTER) {
1341                         DRM_DEBUG_KMS("centering not supported\n");
1342                         return -EINVAL;
1343                 }
1344
1345                 if (intel_connector->panel.fitting_mode == val)
1346                         return 0;
1347
1348                 intel_connector->panel.fitting_mode = val;
1349         }
1350
1351         crtc = intel_attached_encoder(connector)->base.crtc;
1352         if (crtc && crtc->state->enable) {
1353                 /*
1354                  * If the CRTC is enabled, the display will be changed
1355                  * according to the new panel fitting mode.
1356                  */
1357                 intel_crtc_restore_mode(crtc);
1358         }
1359
1360         return 0;
1361 }
1362
1363 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1364 {
1365         struct intel_connector *intel_connector = to_intel_connector(connector);
1366
1367         DRM_DEBUG_KMS("\n");
1368         intel_panel_fini(&intel_connector->panel);
1369         drm_connector_cleanup(connector);
1370         kfree(connector);
1371 }
1372
1373 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1374 {
1375         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1376
1377         if (intel_dsi->panel) {
1378                 drm_panel_detach(intel_dsi->panel);
1379                 /* XXX: Logically this call belongs in the panel driver. */
1380                 drm_panel_remove(intel_dsi->panel);
1381         }
1382
1383         /* dispose of the gpios */
1384         if (intel_dsi->gpio_panel)
1385                 gpiod_put(intel_dsi->gpio_panel);
1386
1387         intel_encoder_destroy(encoder);
1388 }
1389
1390 static const struct drm_encoder_funcs intel_dsi_funcs = {
1391         .destroy = intel_dsi_encoder_destroy,
1392 };
1393
1394 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1395         .get_modes = intel_dsi_get_modes,
1396         .mode_valid = intel_dsi_mode_valid,
1397 };
1398
1399 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1400         .dpms = drm_atomic_helper_connector_dpms,
1401         .detect = intel_dsi_detect,
1402         .late_register = intel_connector_register,
1403         .early_unregister = intel_connector_unregister,
1404         .destroy = intel_dsi_connector_destroy,
1405         .fill_modes = drm_helper_probe_single_connector_modes,
1406         .set_property = intel_dsi_set_property,
1407         .atomic_get_property = intel_connector_atomic_get_property,
1408         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1409         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1410 };
1411
1412 static void intel_dsi_add_properties(struct intel_connector *connector)
1413 {
1414         struct drm_device *dev = connector->base.dev;
1415
1416         if (connector->panel.fixed_mode) {
1417                 drm_mode_create_scaling_mode_property(dev);
1418                 drm_object_attach_property(&connector->base.base,
1419                                            dev->mode_config.scaling_mode_property,
1420                                            DRM_MODE_SCALE_ASPECT);
1421                 connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
1422         }
1423 }
1424
1425 void intel_dsi_init(struct drm_device *dev)
1426 {
1427         struct intel_dsi *intel_dsi;
1428         struct intel_encoder *intel_encoder;
1429         struct drm_encoder *encoder;
1430         struct intel_connector *intel_connector;
1431         struct drm_connector *connector;
1432         struct drm_display_mode *scan, *fixed_mode = NULL;
1433         struct drm_i915_private *dev_priv = to_i915(dev);
1434         enum port port;
1435         unsigned int i;
1436
1437         DRM_DEBUG_KMS("\n");
1438
1439         /* There is no detection method for MIPI so rely on VBT */
1440         if (!intel_bios_is_dsi_present(dev_priv, &port))
1441                 return;
1442
1443         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1444                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1445         } else if (IS_BROXTON(dev)) {
1446                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1447         } else {
1448                 DRM_ERROR("Unsupported Mipi device to reg base");
1449                 return;
1450         }
1451
1452         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1453         if (!intel_dsi)
1454                 return;
1455
1456         intel_connector = intel_connector_alloc();
1457         if (!intel_connector) {
1458                 kfree(intel_dsi);
1459                 return;
1460         }
1461
1462         intel_encoder = &intel_dsi->base;
1463         encoder = &intel_encoder->base;
1464         intel_dsi->attached_connector = intel_connector;
1465
1466         connector = &intel_connector->base;
1467
1468         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1469                          "DSI %c", port_name(port));
1470
1471         intel_encoder->compute_config = intel_dsi_compute_config;
1472         intel_encoder->pre_enable = intel_dsi_pre_enable;
1473         intel_encoder->enable = intel_dsi_enable_nop;
1474         intel_encoder->disable = intel_dsi_pre_disable;
1475         intel_encoder->post_disable = intel_dsi_post_disable;
1476         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1477         intel_encoder->get_config = intel_dsi_get_config;
1478
1479         intel_connector->get_hw_state = intel_connector_get_hw_state;
1480
1481         /*
1482          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1483          * port C. BXT isn't limited like this.
1484          */
1485         if (IS_BROXTON(dev_priv))
1486                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1487         else if (port == PORT_A)
1488                 intel_encoder->crtc_mask = BIT(PIPE_A);
1489         else
1490                 intel_encoder->crtc_mask = BIT(PIPE_B);
1491
1492         if (dev_priv->vbt.dsi.config->dual_link) {
1493                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1494
1495                 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
1496                 case DL_DCS_PORT_A:
1497                         intel_dsi->dcs_backlight_ports = BIT(PORT_A);
1498                         break;
1499                 case DL_DCS_PORT_C:
1500                         intel_dsi->dcs_backlight_ports = BIT(PORT_C);
1501                         break;
1502                 default:
1503                 case DL_DCS_PORT_A_AND_C:
1504                         intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C);
1505                         break;
1506                 }
1507
1508                 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
1509                 case DL_DCS_PORT_A:
1510                         intel_dsi->dcs_cabc_ports = BIT(PORT_A);
1511                         break;
1512                 case DL_DCS_PORT_C:
1513                         intel_dsi->dcs_cabc_ports = BIT(PORT_C);
1514                         break;
1515                 default:
1516                 case DL_DCS_PORT_A_AND_C:
1517                         intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C);
1518                         break;
1519                 }
1520         } else {
1521                 intel_dsi->ports = BIT(port);
1522                 intel_dsi->dcs_backlight_ports = BIT(port);
1523                 intel_dsi->dcs_cabc_ports = BIT(port);
1524         }
1525
1526         if (!dev_priv->vbt.dsi.config->cabc_supported)
1527                 intel_dsi->dcs_cabc_ports = 0;
1528
1529         /* Create a DSI host (and a device) for each port. */
1530         for_each_dsi_port(port, intel_dsi->ports) {
1531                 struct intel_dsi_host *host;
1532
1533                 host = intel_dsi_host_init(intel_dsi, port);
1534                 if (!host)
1535                         goto err;
1536
1537                 intel_dsi->dsi_hosts[port] = host;
1538         }
1539
1540         for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1541                 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1542                                                              intel_dsi_drivers[i].panel_id);
1543                 if (intel_dsi->panel)
1544                         break;
1545         }
1546
1547         if (!intel_dsi->panel) {
1548                 DRM_DEBUG_KMS("no device found\n");
1549                 goto err;
1550         }
1551
1552         /*
1553          * In case of BYT with CRC PMIC, we need to use GPIO for
1554          * Panel control.
1555          */
1556         if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
1557                 intel_dsi->gpio_panel =
1558                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1559
1560                 if (IS_ERR(intel_dsi->gpio_panel)) {
1561                         DRM_ERROR("Failed to own gpio for panel control\n");
1562                         intel_dsi->gpio_panel = NULL;
1563                 }
1564         }
1565
1566         intel_encoder->type = INTEL_OUTPUT_DSI;
1567         intel_encoder->cloneable = 0;
1568         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1569                            DRM_MODE_CONNECTOR_DSI);
1570
1571         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1572
1573         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1574         connector->interlace_allowed = false;
1575         connector->doublescan_allowed = false;
1576
1577         intel_connector_attach_encoder(intel_connector, intel_encoder);
1578
1579         drm_panel_attach(intel_dsi->panel, connector);
1580
1581         mutex_lock(&dev->mode_config.mutex);
1582         drm_panel_get_modes(intel_dsi->panel);
1583         list_for_each_entry(scan, &connector->probed_modes, head) {
1584                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1585                         fixed_mode = drm_mode_duplicate(dev, scan);
1586                         break;
1587                 }
1588         }
1589         mutex_unlock(&dev->mode_config.mutex);
1590
1591         if (!fixed_mode) {
1592                 DRM_DEBUG_KMS("no fixed mode\n");
1593                 goto err;
1594         }
1595
1596         connector->display_info.width_mm = fixed_mode->width_mm;
1597         connector->display_info.height_mm = fixed_mode->height_mm;
1598
1599         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1600         intel_panel_setup_backlight(connector, INVALID_PIPE);
1601
1602         intel_dsi_add_properties(intel_connector);
1603
1604         return;
1605
1606 err:
1607         drm_encoder_cleanup(&intel_encoder->base);
1608         kfree(intel_dsi);
1609         kfree(intel_connector);
1610 }