drivers/gpu/drm/i915/intel_guc_loader.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Vinit Azad <vinit.azad@intel.com>
  25  *    Ben Widawsky <ben@bwidawsk.net>
  26  *    Dave Gordon <david.s.gordon@intel.com>
  27  *    Alex Dai <yu.dai@intel.com>
  28  */
  29 #include <linux/firmware.h>
  30 #include "i915_drv.h"
  31 #include "intel_guc.h"
  32
  33 /**
  34  * DOC: GuC-specific firmware loader
  35  *
  36  * intel_guc:
  37  * Top level structure of guc. It handles firmware loading and manages client
  38  * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
  39  * ExecList submission.
  40  *
  41  * Firmware versioning:
  42  * The firmware build process will generate a version header file with major and
  43  * minor version defined. The versions are built into CSS header of firmware.
  44  * i915 kernel driver set the minimal firmware version required per platform.
  45  * The firmware installation package will install (symbolic link) proper version
  46  * of firmware.
  47  *
  48  * GuC address space:
  49  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  50  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  51  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  52  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
  53  *
  54  * Firmware log:
  55  * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
  56  * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
  57  * i915_guc_load_status will print out firmware loading status and scratch
  58  * registers value.
  59  *
  60  */
  61
  62 #define SKL_FW_MAJOR 6
  63 #define SKL_FW_MINOR 1
  64
  65 #define BXT_FW_MAJOR 8
  66 #define BXT_FW_MINOR 7
  67
  68 #define KBL_FW_MAJOR 9
  69 #define KBL_FW_MINOR 14
  70
  71 #define GUC_FW_PATH(platform, major, minor) \
  72        "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
  73
  74 #define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
  75 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
  76
  77 #define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
  78 MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
  79
  80 #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
  81 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
  82
  83 /* User-friendly representation of an enum */
  84 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
  85 {
  86         switch (status) {
  87         case GUC_FIRMWARE_FAIL:
  88                 return "FAIL";
  89         case GUC_FIRMWARE_NONE:
  90                 return "NONE";
  91         case GUC_FIRMWARE_PENDING:
  92                 return "PENDING";
  93         case GUC_FIRMWARE_SUCCESS:
  94                 return "SUCCESS";
  95         default:
  96                 return "UNKNOWN!";
  97         }
  98 };
  99
 100 static void guc_interrupts_release(struct drm_i915_private *dev_priv)
 101 {
 102         struct intel_engine_cs *engine;
 103         int irqs;
 104
 105         /* tell all command streamers NOT to forward interrupts or vblank to GuC */
 106         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
 107         irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
 108         for_each_engine(engine, dev_priv)
 109                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
 110
 111         /* route all GT interrupts to the host */
 112         I915_WRITE(GUC_BCS_RCS_IER, 0);
 113         I915_WRITE(GUC_VCS2_VCS1_IER, 0);
 114         I915_WRITE(GUC_WD_VECS_IER, 0);
 115 }
 116
 117 static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
 118 {
 119         struct intel_engine_cs *engine;
 120         int irqs;
 121         u32 tmp;
 122
 123         /* tell all command streamers to forward interrupts (but not vblank) to GuC */
 124         irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
 125         for_each_engine(engine, dev_priv)
 126                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
 127
 128         /* route USER_INTERRUPT to Host, all others are sent to GuC. */
 129         irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
 130                GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 131         /* These three registers have the same bit definitions */
 132         I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
 133         I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
 134         I915_WRITE(GUC_WD_VECS_IER, ~irqs);
 135
 136         /*
 137          * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
 138          * (unmasked) PM interrupts to the GuC. All other bits of this
 139          * register *disable* generation of a specific interrupt.
 140          *
 141          * 'pm_intr_keep' indicates bits that are NOT to be set when
 142          * writing to the PM interrupt mask register, i.e. interrupts
 143          * that must not be disabled.
 144          *
 145          * If the GuC is handling these interrupts, then we must not let
 146          * the PM code disable ANY interrupt that the GuC is expecting.
 147          * So for each ENABLED (0) bit in this register, we must SET the
 148          * bit in pm_intr_keep so that it's left enabled for the GuC.
 149          *
 150          * OTOH the REDIRECT_TO_GUC bit is initially SET in pm_intr_keep
 151          * (so interrupts go to the DISPLAY unit at first); but here we
 152          * need to CLEAR that bit, which will result in the register bit
 153          * being left SET!
 154          */
 155         tmp = I915_READ(GEN6_PMINTRMSK);
 156         if (tmp & GEN8_PMINTR_REDIRECT_TO_GUC) {
 157                 dev_priv->rps.pm_intr_keep |= ~tmp;
 158                 dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
 159         }
 160 }
 161
 162 static u32 get_gttype(struct drm_i915_private *dev_priv)
 163 {
 164         /* XXX: GT type based on PCI device ID? field seems unused by fw */
 165         return 0;
 166 }
 167
 168 static u32 get_core_family(struct drm_i915_private *dev_priv)
 169 {
 170         u32 gen = INTEL_GEN(dev_priv);
 171
 172         switch (gen) {
 173         case 9:
 174                 return GFXCORE_FAMILY_GEN9;
 175
 176         default:
 177                 WARN(1, "GEN%d does not support GuC operation!\n", gen);
 178                 return GFXCORE_FAMILY_UNKNOWN;
 179         }
 180 }
 181
 182 /*
 183  * Initialise the GuC parameter block before starting the firmware
 184  * transfer. These parameters are read by the firmware on startup
 185  * and cannot be changed thereafter.
 186  */
 187 static void guc_params_init(struct drm_i915_private *dev_priv)
 188 {
 189         struct intel_guc *guc = &dev_priv->guc;
 190         u32 params[GUC_CTL_MAX_DWORDS];
 191         int i;
 192
 193         memset(&params, 0, sizeof(params));
 194
 195         params[GUC_CTL_DEVICE_INFO] |=
 196                 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
 197                 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
 198
 199         /*
 200          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 201          * second. This ARAR is calculated by:
 202          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 203          */
 204         params[GUC_CTL_ARAT_HIGH] = 0;
 205         params[GUC_CTL_ARAT_LOW] = 100000000;
 206
 207         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 208
 209         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 210                         GUC_CTL_VCS2_ENABLED;
 211
 212         if (i915.guc_log_level >= 0) {
 213                 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 214                 params[GUC_CTL_DEBUG] =
 215                         i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
 216         }
 217
 218         if (guc->ads_vma) {
 219                 u32 ads = i915_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
 220                 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
 221                 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
 222         }
 223
 224         /* If GuC submission is enabled, set up additional parameters here */
 225         if (i915.enable_guc_submission) {
 226                 u32 pgs = i915_ggtt_offset(dev_priv->guc.ctx_pool_vma);
 227                 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
 228
 229                 pgs >>= PAGE_SHIFT;
 230                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 231                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 232
 233                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 234
 235                 /* Unmask this bit to enable the GuC's internal scheduler */
 236                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 237         }
 238
 239         I915_WRITE(SOFT_SCRATCH(0), 0);
 240
 241         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 242                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 243 }
 244
 245 /*
 246  * Read the GuC status register (GUC_STATUS) and store it in the
 247  * specified location; then return a boolean indicating whether
 248  * the value matches either of two values representing completion
 249  * of the GuC boot process.
 250  *
 251  * This is used for polling the GuC status in a wait_for()
 252  * loop below.
 253  */
 254 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
 255                                       u32 *status)
 256 {
 257         u32 val = I915_READ(GUC_STATUS);
 258         u32 uk_val = val & GS_UKERNEL_MASK;
 259         *status = val;
 260         return (uk_val == GS_UKERNEL_READY ||
 261                 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
 262 }
 263
 264 /*
 265  * Transfer the firmware image to RAM for execution by the microcontroller.
 266  *
 267  * Architecturally, the DMA engine is bidirectional, and can potentially even
 268  * transfer between GTT locations. This functionality is left out of the API
 269  * for now as there is no need for it.
 270  *
 271  * Note that GuC needs the CSS header plus uKernel code to be copied by the
 272  * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
 273  */
 274 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 275                               struct i915_vma *vma)
 276 {
 277         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 278         unsigned long offset;
 279         struct sg_table *sg = vma->pages;
 280         u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
 281         int i, ret = 0;
 282
 283         /* where RSA signature starts */
 284         offset = guc_fw->rsa_offset;
 285
 286         /* Copy RSA signature from the fw image to HW for verification */
 287         sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
 288         for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
 289                 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
 290
 291         /* The header plus uCode will be copied to WOPCM via DMA, excluding any
 292          * other components */
 293         I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 294
 295         /* Set the source address for the new blob */
 296         offset = i915_ggtt_offset(vma) + guc_fw->header_offset;
 297         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 298         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 299
 300         /*
 301          * Set the DMA destination. Current uCode expects the code to be
 302          * loaded at 8k; locations below this are used for the stack.
 303          */
 304         I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
 305         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 306
 307         /* Finally start the DMA */
 308         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 309
 310         /*
 311          * Wait for the DMA to complete & the GuC to start up.
 312          * NB: Docs recommend not using the interrupt for completion.
 313          * Measurements indicate this should take no more than 20ms, so a
 314          * timeout here indicates that the GuC has failed and is unusable.
 315          * (Higher levels of the driver will attempt to fall back to
 316          * execlist mode if this happens.)
 317          */
 318         ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
 319
 320         DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
 321                         I915_READ(DMA_CTRL), status);
 322
 323         if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 324                 DRM_ERROR("GuC firmware signature verification failed\n");
 325                 ret = -ENOEXEC;
 326         }
 327
 328         DRM_DEBUG_DRIVER("returning %d\n", ret);
 329
 330         return ret;
 331 }
 332
 333 static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
 334 {
 335         u32 wopcm_size = GUC_WOPCM_TOP;
 336
 337         /* On BXT, the top of WOPCM is reserved for RC6 context */
 338         if (IS_BROXTON(dev_priv))
 339                 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
 340
 341         return wopcm_size;
 342 }
 343
 344 /*
 345  * Load the GuC firmware blob into the MinuteIA.
 346  */
 347 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 348 {
 349         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 350         struct drm_device *dev = &dev_priv->drm;
 351         struct i915_vma *vma;
 352         int ret;
 353
 354         ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
 355         if (ret) {
 356                 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
 357                 return ret;
 358         }
 359
 360         vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
 361         if (IS_ERR(vma)) {
 362                 DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
 363                 return PTR_ERR(vma);
 364         }
 365
 366         /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
 367         I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 368
 369         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 370
 371         /* init WOPCM */
 372         I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
 373         I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 374
 375         /* Enable MIA caching. GuC clock gating is disabled. */
 376         I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 377
 378         /* WaDisableMinuteIaClockGating:skl,bxt */
 379         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 380             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 381                 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
 382                                               ~GUC_ENABLE_MIA_CLOCK_GATING));
 383         }
 384
 385         /* WaC6DisallowByGfxPause*/
 386         if (IS_SKL_REVID(dev, 0, SKL_REVID_C0) ||
 387             IS_BXT_REVID(dev, 0, BXT_REVID_B0))
 388                 I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 389
 390         if (IS_BROXTON(dev))
 391                 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 392         else
 393                 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 394
 395         if (IS_GEN9(dev)) {
 396                 /* DOP Clock Gating Enable for GuC clocks */
 397                 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
 398                                             I915_READ(GEN7_MISCCPCTL)));
 399
 400                 /* allows for 5us (in 10ns units) before GT can go to RC6 */
 401                 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
 402         }
 403
 404         guc_params_init(dev_priv);
 405
 406         ret = guc_ucode_xfer_dma(dev_priv, vma);
 407
 408         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 409
 410         /*
 411          * We keep the object pages for reuse during resume. But we can unpin it
 412          * now that DMA has completed, so it doesn't continue to take up space.
 413          */
 414         i915_vma_unpin(vma);
 415
 416         return ret;
 417 }
 418
 419 static int guc_hw_reset(struct drm_i915_private *dev_priv)
 420 {
 421         int ret;
 422         u32 guc_status;
 423
 424         ret = intel_guc_reset(dev_priv);
 425         if (ret) {
 426                 DRM_ERROR("GuC reset failed, ret = %d\n", ret);
 427                 return ret;
 428         }
 429
 430         guc_status = I915_READ(GUC_STATUS);
 431         WARN(!(guc_status & GS_MIA_IN_RESET),
 432              "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status);
 433
 434         return ret;
 435 }
 436
 437 /**
 438  * intel_guc_setup() - finish preparing the GuC for activity
 439  * @dev:        drm device
 440  *
 441  * Called from gem_init_hw() during driver loading and also after a GPU reset.
 442  *
 443  * The main action required here it to load the GuC uCode into the device.
 444  * The firmware image should have already been fetched into memory by the
 445  * earlier call to intel_guc_init(), so here we need only check that worked,
 446  * and then transfer the image to the h/w.
 447  *
 448  * Return:      non-zero code on error
 449  */
 450 int intel_guc_setup(struct drm_device *dev)
 451 {
 452         struct drm_i915_private *dev_priv = to_i915(dev);
 453         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 454         const char *fw_path = guc_fw->guc_fw_path;
 455         int retries, ret, err;
 456
 457         DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
 458                 fw_path,
 459                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 460                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 461
 462         /* Loading forbidden, or no firmware to load? */
 463         if (!i915.enable_guc_loading) {
 464                 err = 0;
 465                 goto fail;
 466         } else if (fw_path == NULL) {
 467                 /* Device is known to have no uCode (e.g. no GuC) */
 468                 err = -ENXIO;
 469                 goto fail;
 470         } else if (*fw_path == '\0') {
 471                 /* Device has a GuC but we don't know what f/w to load? */
 472                 WARN(1, "No GuC firmware known for this platform!\n");
 473                 err = -ENODEV;
 474                 goto fail;
 475         }
 476
 477         /* Fetch failed, or already fetched but failed to load? */
 478         if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
 479                 err = -EIO;
 480                 goto fail;
 481         } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
 482                 err = -ENOEXEC;
 483                 goto fail;
 484         }
 485
 486         guc_interrupts_release(dev_priv);
 487
 488         guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
 489
 490         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 491                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 492                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 493
 494         err = i915_guc_submission_init(dev_priv);
 495         if (err)
 496                 goto fail;
 497
 498         /*
 499          * WaEnableuKernelHeaderValidFix:skl,bxt
 500          * For BXT, this is only upto B0 but below WA is required for later
 501          * steppings also so this is extended as well.
 502          */
 503         /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
 504         for (retries = 3; ; ) {
 505                 /*
 506                  * Always reset the GuC just before (re)loading, so
 507                  * that the state and timing are fairly predictable
 508                  */
 509                 err = guc_hw_reset(dev_priv);
 510                 if (err)
 511                         goto fail;
 512
 513                 err = guc_ucode_xfer(dev_priv);
 514                 if (!err)
 515                         break;
 516
 517                 if (--retries == 0)
 518                         goto fail;
 519
 520                 DRM_INFO("GuC fw load failed: %d; will reset and "
 521                          "retry %d more time(s)\n", err, retries);
 522         }
 523
 524         guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
 525
 526         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 527                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 528                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 529
 530         if (i915.enable_guc_submission) {
 531                 err = i915_guc_submission_enable(dev_priv);
 532                 if (err)
 533                         goto fail;
 534                 guc_interrupts_capture(dev_priv);
 535         }
 536
 537         return 0;
 538
 539 fail:
 540         if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
 541                 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
 542
 543         guc_interrupts_release(dev_priv);
 544         i915_guc_submission_disable(dev_priv);
 545         i915_guc_submission_fini(dev_priv);
 546
 547         /*
 548          * We've failed to load the firmware :(
 549          *
 550          * Decide whether to disable GuC submission and fall back to
 551          * execlist mode, and whether to hide the error by returning
 552          * zero or to return -EIO, which the caller will treat as a
 553          * nonfatal error (i.e. it doesn't prevent driver load, but
 554          * marks the GPU as wedged until reset).
 555          */
 556         if (i915.enable_guc_loading > 1) {
 557                 ret = -EIO;
 558         } else if (i915.enable_guc_submission > 1) {
 559                 ret = -EIO;
 560         } else {
 561                 ret = 0;
 562         }
 563
 564         if (err == 0 && !HAS_GUC_UCODE(dev))
 565                 ;       /* Don't mention the GuC! */
 566         else if (err == 0)
 567                 DRM_INFO("GuC firmware load skipped\n");
 568         else if (ret != -EIO)
 569                 DRM_NOTE("GuC firmware load failed: %d\n", err);
 570         else
 571                 DRM_WARN("GuC firmware load failed: %d\n", err);
 572
 573         if (i915.enable_guc_submission) {
 574                 if (fw_path == NULL)
 575                         DRM_INFO("GuC submission without firmware not supported\n");
 576                 if (ret == 0)
 577                         DRM_NOTE("Falling back from GuC submission to execlist mode\n");
 578                 else
 579                         DRM_ERROR("GuC init failed: %d\n", ret);
 580         }
 581         i915.enable_guc_submission = 0;
 582
 583         return ret;
 584 }
 585
 586 static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 587 {
 588         struct pci_dev *pdev = dev->pdev;
 589         struct drm_i915_gem_object *obj;
 590         const struct firmware *fw;
 591         struct guc_css_header *css;
 592         size_t size;
 593         int err;
 594
 595         DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
 596                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
 597
 598         err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
 599         if (err)
 600                 goto fail;
 601         if (!fw)
 602                 goto fail;
 603
 604         DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
 605                 guc_fw->guc_fw_path, fw);
 606
 607         /* Check the size of the blob before examining buffer contents */
 608         if (fw->size < sizeof(struct guc_css_header)) {
 609                 DRM_NOTE("Firmware header is missing\n");
 610                 goto fail;
 611         }
 612
 613         css = (struct guc_css_header *)fw->data;
 614
 615         /* Firmware bits always start from header */
 616         guc_fw->header_offset = 0;
 617         guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 618                 css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 619
 620         if (guc_fw->header_size != sizeof(struct guc_css_header)) {
 621                 DRM_NOTE("CSS header definition mismatch\n");
 622                 goto fail;
 623         }
 624
 625         /* then, uCode */
 626         guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
 627         guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 628
 629         /* now RSA */
 630         if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
 631                 DRM_NOTE("RSA key size is bad\n");
 632                 goto fail;
 633         }
 634         guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
 635         guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
 636
 637         /* At least, it should have header, uCode and RSA. Size of all three. */
 638         size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
 639         if (fw->size < size) {
 640                 DRM_NOTE("Missing firmware components\n");
 641                 goto fail;
 642         }
 643
 644         /* Header and uCode will be loaded to WOPCM. Size of the two. */
 645         size = guc_fw->header_size + guc_fw->ucode_size;
 646         if (size > guc_wopcm_size(to_i915(dev))) {
 647                 DRM_NOTE("Firmware is too large to fit in WOPCM\n");
 648                 goto fail;
 649         }
 650
 651         /*
 652          * The GuC firmware image has the version number embedded at a well-known
 653          * offset within the firmware blob; note that major / minor version are
 654          * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 655          * in terms of bytes (u8).
 656          */
 657         guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
 658         guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
 659
 660         if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
 661             guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
 662                 DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
 663                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 664                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 665                 err = -ENOEXEC;
 666                 goto fail;
 667         }
 668
 669         DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
 670                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 671                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 672
 673         mutex_lock(&dev->struct_mutex);
 674         obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
 675         mutex_unlock(&dev->struct_mutex);
 676         if (IS_ERR_OR_NULL(obj)) {
 677                 err = obj ? PTR_ERR(obj) : -ENOMEM;
 678                 goto fail;
 679         }
 680
 681         guc_fw->guc_fw_obj = obj;
 682         guc_fw->guc_fw_size = fw->size;
 683
 684         DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
 685                         guc_fw->guc_fw_obj);
 686
 687         release_firmware(fw);
 688         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
 689         return;
 690
 691 fail:
 692         DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
 693                  guc_fw->guc_fw_path, err);
 694         DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
 695                 err, fw, guc_fw->guc_fw_obj);
 696
 697         mutex_lock(&dev->struct_mutex);
 698         obj = guc_fw->guc_fw_obj;
 699         if (obj)
 700                 i915_gem_object_put(obj);
 701         guc_fw->guc_fw_obj = NULL;
 702         mutex_unlock(&dev->struct_mutex);
 703
 704         release_firmware(fw);           /* OK even if fw is NULL */
 705         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
 706 }
 707
 708 /**
 709  * intel_guc_init() - define parameters and fetch firmware
 710  * @dev:        drm device
 711  *
 712  * Called early during driver load, but after GEM is initialised.
 713  *
 714  * The firmware will be transferred to the GuC's memory later,
 715  * when intel_guc_setup() is called.
 716  */
 717 void intel_guc_init(struct drm_device *dev)
 718 {
 719         struct drm_i915_private *dev_priv = to_i915(dev);
 720         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 721         const char *fw_path;
 722
 723         /* A negative value means "use platform default" */
 724         if (i915.enable_guc_loading < 0)
 725                 i915.enable_guc_loading = HAS_GUC_UCODE(dev);
 726         if (i915.enable_guc_submission < 0)
 727                 i915.enable_guc_submission = HAS_GUC_SCHED(dev);
 728
 729         if (!HAS_GUC_UCODE(dev)) {
 730                 fw_path = NULL;
 731         } else if (IS_SKYLAKE(dev)) {
 732                 fw_path = I915_SKL_GUC_UCODE;
 733                 guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
 734                 guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
 735         } else if (IS_BROXTON(dev)) {
 736                 fw_path = I915_BXT_GUC_UCODE;
 737                 guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
 738                 guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
 739         } else if (IS_KABYLAKE(dev)) {
 740                 fw_path = I915_KBL_GUC_UCODE;
 741                 guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
 742                 guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
 743         } else {
 744                 fw_path = "";   /* unknown device */
 745         }
 746
 747         guc_fw->guc_dev = dev;
 748         guc_fw->guc_fw_path = fw_path;
 749         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 750         guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 751
 752         /* Early (and silent) return if GuC loading is disabled */
 753         if (!i915.enable_guc_loading)
 754                 return;
 755         if (fw_path == NULL)
 756                 return;
 757         if (*fw_path == '\0')
 758                 return;
 759
 760         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 761         DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 762         guc_fw_fetch(dev, guc_fw);
 763         /* status must now be FAIL or SUCCESS */
 764 }
 765
 766 /**
 767  * intel_guc_fini() - clean up all allocated resources
 768  * @dev:        drm device
 769  */
 770 void intel_guc_fini(struct drm_device *dev)
 771 {
 772         struct drm_i915_private *dev_priv = to_i915(dev);
 773         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 774
 775         mutex_lock(&dev->struct_mutex);
 776         guc_interrupts_release(dev_priv);
 777         i915_guc_submission_disable(dev_priv);
 778         i915_guc_submission_fini(dev_priv);
 779
 780         if (guc_fw->guc_fw_obj)
 781                 i915_gem_object_put(guc_fw->guc_fw_obj);
 782         guc_fw->guc_fw_obj = NULL;
 783         mutex_unlock(&dev->struct_mutex);
 784
 785         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 786 }