drivers/gpu/drm/i915/intel_guc_loader.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Vinit Azad <vinit.azad@intel.com>
  25  *    Ben Widawsky <ben@bwidawsk.net>
  26  *    Dave Gordon <david.s.gordon@intel.com>
  27  *    Alex Dai <yu.dai@intel.com>
  28  */
  29 #include <linux/firmware.h>
  30 #include "i915_drv.h"
  31 #include "intel_guc.h"
  32
  33 /**
  34  * DOC: GuC-specific firmware loader
  35  *
  36  * intel_guc:
  37  * Top level structure of guc. It handles firmware loading and manages client
  38  * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
  39  * ExecList submission.
  40  *
  41  * Firmware versioning:
  42  * The firmware build process will generate a version header file with major and
  43  * minor version defined. The versions are built into CSS header of firmware.
  44  * i915 kernel driver set the minimal firmware version required per platform.
  45  * The firmware installation package will install (symbolic link) proper version
  46  * of firmware.
  47  *
  48  * GuC address space:
  49  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  50  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  51  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  52  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
  53  *
  54  * Firmware log:
  55  * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
  56  * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
  57  * i915_guc_load_status will print out firmware loading status and scratch
  58  * registers value.
  59  *
  60  */
  61
  62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver6_1.bin"
  63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
  64
  65 #define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin"
  66 MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
  67
  68 #define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9_14.bin"
  69 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
  70
  71 /* User-friendly representation of an enum */
  72 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
  73 {
  74         switch (status) {
  75         case GUC_FIRMWARE_FAIL:
  76                 return "FAIL";
  77         case GUC_FIRMWARE_NONE:
  78                 return "NONE";
  79         case GUC_FIRMWARE_PENDING:
  80                 return "PENDING";
  81         case GUC_FIRMWARE_SUCCESS:
  82                 return "SUCCESS";
  83         default:
  84                 return "UNKNOWN!";
  85         }
  86 };
  87
  88 static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
  89 {
  90         struct intel_engine_cs *engine;
  91         int irqs;
  92
  93         /* tell all command streamers NOT to forward interrupts or vblank to GuC */
  94         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
  95         irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
  96         for_each_engine(engine, dev_priv)
  97                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
  98
  99         /* route all GT interrupts to the host */
 100         I915_WRITE(GUC_BCS_RCS_IER, 0);
 101         I915_WRITE(GUC_VCS2_VCS1_IER, 0);
 102         I915_WRITE(GUC_WD_VECS_IER, 0);
 103 }
 104
 105 static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 106 {
 107         struct intel_engine_cs *engine;
 108         int irqs;
 109         u32 tmp;
 110
 111         /* tell all command streamers to forward interrupts (but not vblank) to GuC */
 112         irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
 113         for_each_engine(engine, dev_priv)
 114                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
 115
 116         /* route USER_INTERRUPT to Host, all others are sent to GuC. */
 117         irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
 118                GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 119         /* These three registers have the same bit definitions */
 120         I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
 121         I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
 122         I915_WRITE(GUC_WD_VECS_IER, ~irqs);
 123
 124         /*
 125          * If GuC has routed PM interrupts to itself, don't keep it.
 126          * and keep other interrupts those are unmasked by GuC.
 127         */
 128         tmp = I915_READ(GEN6_PMINTRMSK);
 129         if (tmp & GEN8_PMINTR_REDIRECT_TO_NON_DISP) {
 130                 dev_priv->rps.pm_intr_keep |= ~(tmp & ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
 131                 dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 132         }
 133 }
 134
 135 static u32 get_gttype(struct drm_i915_private *dev_priv)
 136 {
 137         /* XXX: GT type based on PCI device ID? field seems unused by fw */
 138         return 0;
 139 }
 140
 141 static u32 get_core_family(struct drm_i915_private *dev_priv)
 142 {
 143         switch (INTEL_INFO(dev_priv)->gen) {
 144         case 9:
 145                 return GFXCORE_FAMILY_GEN9;
 146
 147         default:
 148                 DRM_ERROR("GUC: unsupported core family\n");
 149                 return GFXCORE_FAMILY_UNKNOWN;
 150         }
 151 }
 152
 153 static void set_guc_init_params(struct drm_i915_private *dev_priv)
 154 {
 155         struct intel_guc *guc = &dev_priv->guc;
 156         u32 params[GUC_CTL_MAX_DWORDS];
 157         int i;
 158
 159         memset(&params, 0, sizeof(params));
 160
 161         params[GUC_CTL_DEVICE_INFO] |=
 162                 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
 163                 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
 164
 165         /*
 166          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 167          * second. This ARAR is calculated by:
 168          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 169          */
 170         params[GUC_CTL_ARAT_HIGH] = 0;
 171         params[GUC_CTL_ARAT_LOW] = 100000000;
 172
 173         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 174
 175         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 176                         GUC_CTL_VCS2_ENABLED;
 177
 178         if (i915.guc_log_level >= 0) {
 179                 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 180                 params[GUC_CTL_DEBUG] =
 181                         i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
 182         }
 183
 184         if (guc->ads_obj) {
 185                 u32 ads = (u32)i915_gem_obj_ggtt_offset(guc->ads_obj)
 186                                 >> PAGE_SHIFT;
 187                 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
 188                 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
 189         }
 190
 191         /* If GuC submission is enabled, set up additional parameters here */
 192         if (i915.enable_guc_submission) {
 193                 u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
 194                 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
 195
 196                 pgs >>= PAGE_SHIFT;
 197                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 198                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 199
 200                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 201
 202                 /* Unmask this bit to enable the GuC's internal scheduler */
 203                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 204         }
 205
 206         I915_WRITE(SOFT_SCRATCH(0), 0);
 207
 208         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 209                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 210 }
 211
 212 /*
 213  * Read the GuC status register (GUC_STATUS) and store it in the
 214  * specified location; then return a boolean indicating whether
 215  * the value matches either of two values representing completion
 216  * of the GuC boot process.
 217  *
 218  * This is used for polling the GuC status in a wait_for()
 219  * loop below.
 220  */
 221 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
 222                                       u32 *status)
 223 {
 224         u32 val = I915_READ(GUC_STATUS);
 225         u32 uk_val = val & GS_UKERNEL_MASK;
 226         *status = val;
 227         return (uk_val == GS_UKERNEL_READY ||
 228                 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
 229 }
 230
 231 /*
 232  * Transfer the firmware image to RAM for execution by the microcontroller.
 233  *
 234  * Architecturally, the DMA engine is bidirectional, and can potentially even
 235  * transfer between GTT locations. This functionality is left out of the API
 236  * for now as there is no need for it.
 237  *
 238  * Note that GuC needs the CSS header plus uKernel code to be copied by the
 239  * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
 240  */
 241 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 242 {
 243         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 244         struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
 245         unsigned long offset;
 246         struct sg_table *sg = fw_obj->pages;
 247         u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
 248         int i, ret = 0;
 249
 250         /* where RSA signature starts */
 251         offset = guc_fw->rsa_offset;
 252
 253         /* Copy RSA signature from the fw image to HW for verification */
 254         sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
 255         for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
 256                 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
 257
 258         /* The header plus uCode will be copied to WOPCM via DMA, excluding any
 259          * other components */
 260         I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 261
 262         /* Set the source address for the new blob */
 263         offset = i915_gem_obj_ggtt_offset(fw_obj) + guc_fw->header_offset;
 264         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 265         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 266
 267         /*
 268          * Set the DMA destination. Current uCode expects the code to be
 269          * loaded at 8k; locations below this are used for the stack.
 270          */
 271         I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
 272         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 273
 274         /* Finally start the DMA */
 275         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 276
 277         /*
 278          * Wait for the DMA to complete & the GuC to start up.
 279          * NB: Docs recommend not using the interrupt for completion.
 280          * Measurements indicate this should take no more than 20ms, so a
 281          * timeout here indicates that the GuC has failed and is unusable.
 282          * (Higher levels of the driver will attempt to fall back to
 283          * execlist mode if this happens.)
 284          */
 285         ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
 286
 287         DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
 288                         I915_READ(DMA_CTRL), status);
 289
 290         if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 291                 DRM_ERROR("GuC firmware signature verification failed\n");
 292                 ret = -ENOEXEC;
 293         }
 294
 295         DRM_DEBUG_DRIVER("returning %d\n", ret);
 296
 297         return ret;
 298 }
 299
 300 static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
 301 {
 302         u32 wopcm_size = GUC_WOPCM_TOP;
 303
 304         /* On BXT, the top of WOPCM is reserved for RC6 context */
 305         if (IS_BROXTON(dev_priv))
 306                 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
 307
 308         return wopcm_size;
 309 }
 310
 311 /*
 312  * Load the GuC firmware blob into the MinuteIA.
 313  */
 314 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 315 {
 316         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 317         struct drm_device *dev = &dev_priv->drm;
 318         int ret;
 319
 320         ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
 321         if (ret) {
 322                 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
 323                 return ret;
 324         }
 325
 326         ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
 327         if (ret) {
 328                 DRM_DEBUG_DRIVER("pin failed %d\n", ret);
 329                 return ret;
 330         }
 331
 332         /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
 333         I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 334
 335         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 336
 337         /* init WOPCM */
 338         I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
 339         I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 340
 341         /* Enable MIA caching. GuC clock gating is disabled. */
 342         I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 343
 344         /* WaDisableMinuteIaClockGating:skl,bxt */
 345         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 346             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 347                 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
 348                                               ~GUC_ENABLE_MIA_CLOCK_GATING));
 349         }
 350
 351         /* WaC6DisallowByGfxPause*/
 352         I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 353
 354         if (IS_BROXTON(dev))
 355                 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 356         else
 357                 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 358
 359         if (IS_GEN9(dev)) {
 360                 /* DOP Clock Gating Enable for GuC clocks */
 361                 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
 362                                             I915_READ(GEN7_MISCCPCTL)));
 363
 364                 /* allows for 5us before GT can go to RC6 */
 365                 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
 366         }
 367
 368         set_guc_init_params(dev_priv);
 369
 370         ret = guc_ucode_xfer_dma(dev_priv);
 371
 372         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 373
 374         /*
 375          * We keep the object pages for reuse during resume. But we can unpin it
 376          * now that DMA has completed, so it doesn't continue to take up space.
 377          */
 378         i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
 379
 380         return ret;
 381 }
 382
 383 static int i915_reset_guc(struct drm_i915_private *dev_priv)
 384 {
 385         int ret;
 386         u32 guc_status;
 387
 388         ret = intel_guc_reset(dev_priv);
 389         if (ret) {
 390                 DRM_ERROR("GuC reset failed, ret = %d\n", ret);
 391                 return ret;
 392         }
 393
 394         guc_status = I915_READ(GUC_STATUS);
 395         WARN(!(guc_status & GS_MIA_IN_RESET),
 396              "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status);
 397
 398         return ret;
 399 }
 400
 401 /**
 402  * intel_guc_setup() - finish preparing the GuC for activity
 403  * @dev:        drm device
 404  *
 405  * Called from gem_init_hw() during driver loading and also after a GPU reset.
 406  *
 407  * The main action required here it to load the GuC uCode into the device.
 408  * The firmware image should have already been fetched into memory by the
 409  * earlier call to intel_guc_init(), so here we need only check that worked,
 410  * and then transfer the image to the h/w.
 411  *
 412  * Return:      non-zero code on error
 413  */
 414 int intel_guc_setup(struct drm_device *dev)
 415 {
 416         struct drm_i915_private *dev_priv = to_i915(dev);
 417         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 418         const char *fw_path = guc_fw->guc_fw_path;
 419         int retries, ret, err;
 420
 421         DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
 422                 fw_path,
 423                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 424                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 425
 426         /* Loading forbidden, or no firmware to load? */
 427         if (!i915.enable_guc_loading) {
 428                 err = 0;
 429                 goto fail;
 430         } else if (fw_path == NULL) {
 431                 /* Device is known to have no uCode (e.g. no GuC) */
 432                 err = -ENXIO;
 433                 goto fail;
 434         } else if (*fw_path == '\0') {
 435                 /* Device has a GuC but we don't know what f/w to load? */
 436                 DRM_INFO("No GuC firmware known for this platform\n");
 437                 err = -ENODEV;
 438                 goto fail;
 439         }
 440
 441         /* Fetch failed, or already fetched but failed to load? */
 442         if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
 443                 err = -EIO;
 444                 goto fail;
 445         } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
 446                 err = -ENOEXEC;
 447                 goto fail;
 448         }
 449
 450         direct_interrupts_to_host(dev_priv);
 451
 452         guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
 453
 454         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 455                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 456                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 457
 458         err = i915_guc_submission_init(dev_priv);
 459         if (err)
 460                 goto fail;
 461
 462         /*
 463          * WaEnableuKernelHeaderValidFix:skl,bxt
 464          * For BXT, this is only upto B0 but below WA is required for later
 465          * steppings also so this is extended as well.
 466          */
 467         /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
 468         for (retries = 3; ; ) {
 469                 /*
 470                  * Always reset the GuC just before (re)loading, so
 471                  * that the state and timing are fairly predictable
 472                  */
 473                 err = i915_reset_guc(dev_priv);
 474                 if (err) {
 475                         DRM_ERROR("GuC reset failed: %d\n", err);
 476                         goto fail;
 477                 }
 478
 479                 err = guc_ucode_xfer(dev_priv);
 480                 if (!err)
 481                         break;
 482
 483                 if (--retries == 0)
 484                         goto fail;
 485
 486                 DRM_INFO("GuC fw load failed: %d; will reset and "
 487                          "retry %d more time(s)\n", err, retries);
 488         }
 489
 490         guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
 491
 492         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 493                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 494                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 495
 496         if (i915.enable_guc_submission) {
 497                 err = i915_guc_submission_enable(dev_priv);
 498                 if (err)
 499                         goto fail;
 500                 direct_interrupts_to_guc(dev_priv);
 501         }
 502
 503         return 0;
 504
 505 fail:
 506         if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
 507                 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
 508
 509         direct_interrupts_to_host(dev_priv);
 510         i915_guc_submission_disable(dev_priv);
 511         i915_guc_submission_fini(dev_priv);
 512
 513         /*
 514          * We've failed to load the firmware :(
 515          *
 516          * Decide whether to disable GuC submission and fall back to
 517          * execlist mode, and whether to hide the error by returning
 518          * zero or to return -EIO, which the caller will treat as a
 519          * nonfatal error (i.e. it doesn't prevent driver load, but
 520          * marks the GPU as wedged until reset).
 521          */
 522         if (i915.enable_guc_loading > 1) {
 523                 ret = -EIO;
 524         } else if (i915.enable_guc_submission > 1) {
 525                 ret = -EIO;
 526         } else {
 527                 ret = 0;
 528         }
 529
 530         if (err == 0 && !HAS_GUC_UCODE(dev))
 531                 ;       /* Don't mention the GuC! */
 532         else if (err == 0)
 533                 DRM_INFO("GuC firmware load skipped\n");
 534         else if (ret != -EIO)
 535                 DRM_INFO("GuC firmware load failed: %d\n", err);
 536         else
 537                 DRM_ERROR("GuC firmware load failed: %d\n", err);
 538
 539         if (i915.enable_guc_submission) {
 540                 if (fw_path == NULL)
 541                         DRM_INFO("GuC submission without firmware not supported\n");
 542                 if (ret == 0)
 543                         DRM_INFO("Falling back from GuC submission to execlist mode\n");
 544                 else
 545                         DRM_ERROR("GuC init failed: %d\n", ret);
 546         }
 547         i915.enable_guc_submission = 0;
 548
 549         return ret;
 550 }
 551
 552 static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 553 {
 554         struct drm_i915_gem_object *obj;
 555         const struct firmware *fw;
 556         struct guc_css_header *css;
 557         size_t size;
 558         int err;
 559
 560         DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
 561                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
 562
 563         err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
 564         if (err)
 565                 goto fail;
 566         if (!fw)
 567                 goto fail;
 568
 569         DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
 570                 guc_fw->guc_fw_path, fw);
 571
 572         /* Check the size of the blob before examining buffer contents */
 573         if (fw->size < sizeof(struct guc_css_header)) {
 574                 DRM_ERROR("Firmware header is missing\n");
 575                 goto fail;
 576         }
 577
 578         css = (struct guc_css_header *)fw->data;
 579
 580         /* Firmware bits always start from header */
 581         guc_fw->header_offset = 0;
 582         guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 583                 css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 584
 585         if (guc_fw->header_size != sizeof(struct guc_css_header)) {
 586                 DRM_ERROR("CSS header definition mismatch\n");
 587                 goto fail;
 588         }
 589
 590         /* then, uCode */
 591         guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
 592         guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 593
 594         /* now RSA */
 595         if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
 596                 DRM_ERROR("RSA key size is bad\n");
 597                 goto fail;
 598         }
 599         guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
 600         guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
 601
 602         /* At least, it should have header, uCode and RSA. Size of all three. */
 603         size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
 604         if (fw->size < size) {
 605                 DRM_ERROR("Missing firmware components\n");
 606                 goto fail;
 607         }
 608
 609         /* Header and uCode will be loaded to WOPCM. Size of the two. */
 610         size = guc_fw->header_size + guc_fw->ucode_size;
 611         if (size > guc_wopcm_size(to_i915(dev))) {
 612                 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
 613                 goto fail;
 614         }
 615
 616         /*
 617          * The GuC firmware image has the version number embedded at a well-known
 618          * offset within the firmware blob; note that major / minor version are
 619          * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 620          * in terms of bytes (u8).
 621          */
 622         guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
 623         guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
 624
 625         if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
 626             guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
 627                 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
 628                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 629                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 630                 err = -ENOEXEC;
 631                 goto fail;
 632         }
 633
 634         DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
 635                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 636                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 637
 638         mutex_lock(&dev->struct_mutex);
 639         obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
 640         mutex_unlock(&dev->struct_mutex);
 641         if (IS_ERR_OR_NULL(obj)) {
 642                 err = obj ? PTR_ERR(obj) : -ENOMEM;
 643                 goto fail;
 644         }
 645
 646         guc_fw->guc_fw_obj = obj;
 647         guc_fw->guc_fw_size = fw->size;
 648
 649         DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
 650                         guc_fw->guc_fw_obj);
 651
 652         release_firmware(fw);
 653         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
 654         return;
 655
 656 fail:
 657         DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
 658                 err, fw, guc_fw->guc_fw_obj);
 659         DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
 660                   guc_fw->guc_fw_path, err);
 661
 662         mutex_lock(&dev->struct_mutex);
 663         obj = guc_fw->guc_fw_obj;
 664         if (obj)
 665                 drm_gem_object_unreference(&obj->base);
 666         guc_fw->guc_fw_obj = NULL;
 667         mutex_unlock(&dev->struct_mutex);
 668
 669         release_firmware(fw);           /* OK even if fw is NULL */
 670         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
 671 }
 672
 673 /**
 674  * intel_guc_init() - define parameters and fetch firmware
 675  * @dev:        drm device
 676  *
 677  * Called early during driver load, but after GEM is initialised.
 678  *
 679  * The firmware will be transferred to the GuC's memory later,
 680  * when intel_guc_setup() is called.
 681  */
 682 void intel_guc_init(struct drm_device *dev)
 683 {
 684         struct drm_i915_private *dev_priv = to_i915(dev);
 685         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 686         const char *fw_path;
 687
 688         /* A negative value means "use platform default" */
 689         if (i915.enable_guc_loading < 0)
 690                 i915.enable_guc_loading = HAS_GUC_UCODE(dev);
 691         if (i915.enable_guc_submission < 0)
 692                 i915.enable_guc_submission = HAS_GUC_SCHED(dev);
 693
 694         if (!HAS_GUC_UCODE(dev)) {
 695                 fw_path = NULL;
 696         } else if (IS_SKYLAKE(dev)) {
 697                 fw_path = I915_SKL_GUC_UCODE;
 698                 guc_fw->guc_fw_major_wanted = 6;
 699                 guc_fw->guc_fw_minor_wanted = 1;
 700         } else if (IS_BROXTON(dev)) {
 701                 fw_path = I915_BXT_GUC_UCODE;
 702                 guc_fw->guc_fw_major_wanted = 8;
 703                 guc_fw->guc_fw_minor_wanted = 7;
 704         } else if (IS_KABYLAKE(dev)) {
 705                 fw_path = I915_KBL_GUC_UCODE;
 706                 guc_fw->guc_fw_major_wanted = 9;
 707                 guc_fw->guc_fw_minor_wanted = 14;
 708         } else {
 709                 fw_path = "";   /* unknown device */
 710         }
 711
 712         guc_fw->guc_dev = dev;
 713         guc_fw->guc_fw_path = fw_path;
 714         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 715         guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 716
 717         /* Early (and silent) return if GuC loading is disabled */
 718         if (!i915.enable_guc_loading)
 719                 return;
 720         if (fw_path == NULL)
 721                 return;
 722         if (*fw_path == '\0')
 723                 return;
 724
 725         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 726         DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 727         guc_fw_fetch(dev, guc_fw);
 728         /* status must now be FAIL or SUCCESS */
 729 }
 730
 731 /**
 732  * intel_guc_fini() - clean up all allocated resources
 733  * @dev:        drm device
 734  */
 735 void intel_guc_fini(struct drm_device *dev)
 736 {
 737         struct drm_i915_private *dev_priv = to_i915(dev);
 738         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 739
 740         mutex_lock(&dev->struct_mutex);
 741         direct_interrupts_to_host(dev_priv);
 742         i915_guc_submission_disable(dev_priv);
 743         i915_guc_submission_fini(dev_priv);
 744
 745         if (guc_fw->guc_fw_obj)
 746                 drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
 747         guc_fw->guc_fw_obj = NULL;
 748         mutex_unlock(&dev->struct_mutex);
 749
 750         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 751 }