2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
42 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
49 struct drm_i915_private *dev_priv = dev->dev_private;
50 uint32_t enabled_bits;
52 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
54 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
55 "HDMI port enabled, expecting disabled\n");
58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
60 struct intel_digital_port *intel_dig_port =
61 container_of(encoder, struct intel_digital_port, base.base);
62 return &intel_dig_port->hdmi;
65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
67 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
73 case HDMI_INFOFRAME_TYPE_AVI:
74 return VIDEO_DIP_SELECT_AVI;
75 case HDMI_INFOFRAME_TYPE_SPD:
76 return VIDEO_DIP_SELECT_SPD;
77 case HDMI_INFOFRAME_TYPE_VENDOR:
78 return VIDEO_DIP_SELECT_VENDOR;
80 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
88 case HDMI_INFOFRAME_TYPE_AVI:
89 return VIDEO_DIP_ENABLE_AVI;
90 case HDMI_INFOFRAME_TYPE_SPD:
91 return VIDEO_DIP_ENABLE_SPD;
92 case HDMI_INFOFRAME_TYPE_VENDOR:
93 return VIDEO_DIP_ENABLE_VENDOR;
95 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
103 case HDMI_INFOFRAME_TYPE_AVI:
104 return VIDEO_DIP_ENABLE_AVI_HSW;
105 case HDMI_INFOFRAME_TYPE_SPD:
106 return VIDEO_DIP_ENABLE_SPD_HSW;
107 case HDMI_INFOFRAME_TYPE_VENDOR:
108 return VIDEO_DIP_ENABLE_VS_HSW;
110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
115 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
116 enum transcoder cpu_transcoder,
117 struct drm_i915_private *dev_priv)
120 case HDMI_INFOFRAME_TYPE_AVI:
121 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
122 case HDMI_INFOFRAME_TYPE_SPD:
123 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
124 case HDMI_INFOFRAME_TYPE_VENDOR:
125 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
127 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
132 static void g4x_write_infoframe(struct drm_encoder *encoder,
133 enum hdmi_infoframe_type type,
134 const void *frame, ssize_t len)
136 const uint32_t *data = frame;
137 struct drm_device *dev = encoder->dev;
138 struct drm_i915_private *dev_priv = dev->dev_private;
139 u32 val = I915_READ(VIDEO_DIP_CTL);
142 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
144 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
145 val |= g4x_infoframe_index(type);
147 val &= ~g4x_infoframe_enable(type);
149 I915_WRITE(VIDEO_DIP_CTL, val);
152 for (i = 0; i < len; i += 4) {
153 I915_WRITE(VIDEO_DIP_DATA, *data);
156 /* Write every possible data byte to force correct ECC calculation. */
157 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
158 I915_WRITE(VIDEO_DIP_DATA, 0);
161 val |= g4x_infoframe_enable(type);
162 val &= ~VIDEO_DIP_FREQ_MASK;
163 val |= VIDEO_DIP_FREQ_VSYNC;
165 I915_WRITE(VIDEO_DIP_CTL, val);
166 POSTING_READ(VIDEO_DIP_CTL);
169 static void ibx_write_infoframe(struct drm_encoder *encoder,
170 enum hdmi_infoframe_type type,
171 const void *frame, ssize_t len)
173 const uint32_t *data = frame;
174 struct drm_device *dev = encoder->dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
177 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
178 u32 val = I915_READ(reg);
180 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
182 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
183 val |= g4x_infoframe_index(type);
185 val &= ~g4x_infoframe_enable(type);
187 I915_WRITE(reg, val);
190 for (i = 0; i < len; i += 4) {
191 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
194 /* Write every possible data byte to force correct ECC calculation. */
195 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
196 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
199 val |= g4x_infoframe_enable(type);
200 val &= ~VIDEO_DIP_FREQ_MASK;
201 val |= VIDEO_DIP_FREQ_VSYNC;
203 I915_WRITE(reg, val);
207 static void cpt_write_infoframe(struct drm_encoder *encoder,
208 enum hdmi_infoframe_type type,
209 const void *frame, ssize_t len)
211 const uint32_t *data = frame;
212 struct drm_device *dev = encoder->dev;
213 struct drm_i915_private *dev_priv = dev->dev_private;
214 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
215 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
216 u32 val = I915_READ(reg);
218 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
220 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
221 val |= g4x_infoframe_index(type);
223 /* The DIP control register spec says that we need to update the AVI
224 * infoframe without clearing its enable bit */
225 if (type != HDMI_INFOFRAME_TYPE_AVI)
226 val &= ~g4x_infoframe_enable(type);
228 I915_WRITE(reg, val);
231 for (i = 0; i < len; i += 4) {
232 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
235 /* Write every possible data byte to force correct ECC calculation. */
236 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
237 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
240 val |= g4x_infoframe_enable(type);
241 val &= ~VIDEO_DIP_FREQ_MASK;
242 val |= VIDEO_DIP_FREQ_VSYNC;
244 I915_WRITE(reg, val);
248 static void vlv_write_infoframe(struct drm_encoder *encoder,
249 enum hdmi_infoframe_type type,
250 const void *frame, ssize_t len)
252 const uint32_t *data = frame;
253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
256 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
257 u32 val = I915_READ(reg);
259 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
261 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
262 val |= g4x_infoframe_index(type);
264 val &= ~g4x_infoframe_enable(type);
266 I915_WRITE(reg, val);
269 for (i = 0; i < len; i += 4) {
270 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
273 /* Write every possible data byte to force correct ECC calculation. */
274 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
275 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
278 val |= g4x_infoframe_enable(type);
279 val &= ~VIDEO_DIP_FREQ_MASK;
280 val |= VIDEO_DIP_FREQ_VSYNC;
282 I915_WRITE(reg, val);
286 static void hsw_write_infoframe(struct drm_encoder *encoder,
287 enum hdmi_infoframe_type type,
288 const void *frame, ssize_t len)
290 const uint32_t *data = frame;
291 struct drm_device *dev = encoder->dev;
292 struct drm_i915_private *dev_priv = dev->dev_private;
293 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
294 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
297 u32 val = I915_READ(ctl_reg);
299 data_reg = hsw_infoframe_data_reg(type,
300 intel_crtc->config.cpu_transcoder,
305 val &= ~hsw_infoframe_enable(type);
306 I915_WRITE(ctl_reg, val);
309 for (i = 0; i < len; i += 4) {
310 I915_WRITE(data_reg + i, *data);
313 /* Write every possible data byte to force correct ECC calculation. */
314 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
315 I915_WRITE(data_reg + i, 0);
318 val |= hsw_infoframe_enable(type);
319 I915_WRITE(ctl_reg, val);
320 POSTING_READ(ctl_reg);
324 * The data we write to the DIP data buffer registers is 1 byte bigger than the
325 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
326 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
327 * used for both technologies.
329 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
330 * DW1: DB3 | DB2 | DB1 | DB0
331 * DW2: DB7 | DB6 | DB5 | DB4
334 * (HB is Header Byte, DB is Data Byte)
336 * The hdmi pack() functions don't know about that hardware specific hole so we
337 * trick them by giving an offset into the buffer and moving back the header
340 static void intel_write_infoframe(struct drm_encoder *encoder,
341 union hdmi_infoframe *frame)
343 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
344 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
347 /* see comment above for the reason for this offset */
348 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
352 /* Insert the 'hole' (see big comment above) at position 3 */
353 buffer[0] = buffer[1];
354 buffer[1] = buffer[2];
355 buffer[2] = buffer[3];
359 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
362 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
363 struct drm_display_mode *adjusted_mode)
365 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
366 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
367 union hdmi_infoframe frame;
370 /* Set user selected PAR to incoming mode's member */
371 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
373 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
376 DRM_ERROR("couldn't fill AVI infoframe\n");
380 if (intel_hdmi->rgb_quant_range_selectable) {
381 if (intel_crtc->config.limited_color_range)
382 frame.avi.quantization_range =
383 HDMI_QUANTIZATION_RANGE_LIMITED;
385 frame.avi.quantization_range =
386 HDMI_QUANTIZATION_RANGE_FULL;
389 intel_write_infoframe(encoder, &frame);
392 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
394 union hdmi_infoframe frame;
397 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
399 DRM_ERROR("couldn't fill SPD infoframe\n");
403 frame.spd.sdi = HDMI_SPD_SDI_PC;
405 intel_write_infoframe(encoder, &frame);
409 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
410 struct drm_display_mode *adjusted_mode)
412 union hdmi_infoframe frame;
415 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
420 intel_write_infoframe(encoder, &frame);
423 static void g4x_set_infoframes(struct drm_encoder *encoder,
425 struct drm_display_mode *adjusted_mode)
427 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
428 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
429 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
430 u32 reg = VIDEO_DIP_CTL;
431 u32 val = I915_READ(reg);
432 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
434 assert_hdmi_port_disabled(intel_hdmi);
436 /* If the registers were not initialized yet, they might be zeroes,
437 * which means we're selecting the AVI DIP and we're setting its
438 * frequency to once. This seems to really confuse the HW and make
439 * things stop working (the register spec says the AVI always needs to
440 * be sent every VSync). So here we avoid writing to the register more
441 * than we need and also explicitly select the AVI DIP and explicitly
442 * set its frequency to every VSync. Avoiding to write it twice seems to
443 * be enough to solve the problem, but being defensive shouldn't hurt us
445 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
448 if (!(val & VIDEO_DIP_ENABLE))
450 val &= ~VIDEO_DIP_ENABLE;
451 I915_WRITE(reg, val);
456 if (port != (val & VIDEO_DIP_PORT_MASK)) {
457 if (val & VIDEO_DIP_ENABLE) {
458 val &= ~VIDEO_DIP_ENABLE;
459 I915_WRITE(reg, val);
462 val &= ~VIDEO_DIP_PORT_MASK;
466 val |= VIDEO_DIP_ENABLE;
467 val &= ~VIDEO_DIP_ENABLE_VENDOR;
469 I915_WRITE(reg, val);
472 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
473 intel_hdmi_set_spd_infoframe(encoder);
474 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
477 static void ibx_set_infoframes(struct drm_encoder *encoder,
479 struct drm_display_mode *adjusted_mode)
481 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
482 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
483 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
484 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
485 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
486 u32 val = I915_READ(reg);
487 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
489 assert_hdmi_port_disabled(intel_hdmi);
491 /* See the big comment in g4x_set_infoframes() */
492 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
495 if (!(val & VIDEO_DIP_ENABLE))
497 val &= ~VIDEO_DIP_ENABLE;
498 I915_WRITE(reg, val);
503 if (port != (val & VIDEO_DIP_PORT_MASK)) {
504 if (val & VIDEO_DIP_ENABLE) {
505 val &= ~VIDEO_DIP_ENABLE;
506 I915_WRITE(reg, val);
509 val &= ~VIDEO_DIP_PORT_MASK;
513 val |= VIDEO_DIP_ENABLE;
514 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
515 VIDEO_DIP_ENABLE_GCP);
517 I915_WRITE(reg, val);
520 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
521 intel_hdmi_set_spd_infoframe(encoder);
522 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
525 static void cpt_set_infoframes(struct drm_encoder *encoder,
527 struct drm_display_mode *adjusted_mode)
529 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
530 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
531 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
532 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
533 u32 val = I915_READ(reg);
535 assert_hdmi_port_disabled(intel_hdmi);
537 /* See the big comment in g4x_set_infoframes() */
538 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
541 if (!(val & VIDEO_DIP_ENABLE))
543 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
544 I915_WRITE(reg, val);
549 /* Set both together, unset both together: see the spec. */
550 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
551 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
552 VIDEO_DIP_ENABLE_GCP);
554 I915_WRITE(reg, val);
557 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
558 intel_hdmi_set_spd_infoframe(encoder);
559 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
562 static void vlv_set_infoframes(struct drm_encoder *encoder,
564 struct drm_display_mode *adjusted_mode)
566 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
567 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
568 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
569 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
570 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
571 u32 val = I915_READ(reg);
572 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
574 assert_hdmi_port_disabled(intel_hdmi);
576 /* See the big comment in g4x_set_infoframes() */
577 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
580 if (!(val & VIDEO_DIP_ENABLE))
582 val &= ~VIDEO_DIP_ENABLE;
583 I915_WRITE(reg, val);
588 if (port != (val & VIDEO_DIP_PORT_MASK)) {
589 if (val & VIDEO_DIP_ENABLE) {
590 val &= ~VIDEO_DIP_ENABLE;
591 I915_WRITE(reg, val);
594 val &= ~VIDEO_DIP_PORT_MASK;
598 val |= VIDEO_DIP_ENABLE;
599 val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
600 VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
602 I915_WRITE(reg, val);
605 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
606 intel_hdmi_set_spd_infoframe(encoder);
607 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
610 static void hsw_set_infoframes(struct drm_encoder *encoder,
612 struct drm_display_mode *adjusted_mode)
614 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
615 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
616 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
617 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
618 u32 val = I915_READ(reg);
620 assert_hdmi_port_disabled(intel_hdmi);
628 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
629 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
631 I915_WRITE(reg, val);
634 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
635 intel_hdmi_set_spd_infoframe(encoder);
636 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
639 static void intel_hdmi_prepare(struct intel_encoder *encoder)
641 struct drm_device *dev = encoder->base.dev;
642 struct drm_i915_private *dev_priv = dev->dev_private;
643 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
644 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
645 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
648 hdmi_val = SDVO_ENCODING_HDMI;
649 if (!HAS_PCH_SPLIT(dev))
650 hdmi_val |= intel_hdmi->color_range;
651 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
652 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
653 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
654 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
656 if (crtc->config.pipe_bpp > 24)
657 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
659 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
661 if (crtc->config.has_hdmi_sink)
662 hdmi_val |= HDMI_MODE_SELECT_HDMI;
664 if (crtc->config.has_audio) {
665 WARN_ON(!crtc->config.has_hdmi_sink);
666 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
667 pipe_name(crtc->pipe));
668 hdmi_val |= SDVO_AUDIO_ENABLE;
669 intel_write_eld(&encoder->base, adjusted_mode);
672 if (HAS_PCH_CPT(dev))
673 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
674 else if (IS_CHERRYVIEW(dev))
675 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
677 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
679 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
680 POSTING_READ(intel_hdmi->hdmi_reg);
683 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
686 struct drm_device *dev = encoder->base.dev;
687 struct drm_i915_private *dev_priv = dev->dev_private;
688 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
689 enum intel_display_power_domain power_domain;
692 power_domain = intel_display_port_power_domain(encoder);
693 if (!intel_display_power_enabled(dev_priv, power_domain))
696 tmp = I915_READ(intel_hdmi->hdmi_reg);
698 if (!(tmp & SDVO_ENABLE))
701 if (HAS_PCH_CPT(dev))
702 *pipe = PORT_TO_PIPE_CPT(tmp);
703 else if (IS_CHERRYVIEW(dev))
704 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
706 *pipe = PORT_TO_PIPE(tmp);
711 static void intel_hdmi_get_config(struct intel_encoder *encoder,
712 struct intel_crtc_config *pipe_config)
714 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
715 struct drm_device *dev = encoder->base.dev;
716 struct drm_i915_private *dev_priv = dev->dev_private;
720 tmp = I915_READ(intel_hdmi->hdmi_reg);
722 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
723 flags |= DRM_MODE_FLAG_PHSYNC;
725 flags |= DRM_MODE_FLAG_NHSYNC;
727 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
728 flags |= DRM_MODE_FLAG_PVSYNC;
730 flags |= DRM_MODE_FLAG_NVSYNC;
732 if (tmp & HDMI_MODE_SELECT_HDMI)
733 pipe_config->has_hdmi_sink = true;
735 if (tmp & SDVO_AUDIO_ENABLE)
736 pipe_config->has_audio = true;
738 if (!HAS_PCH_SPLIT(dev) &&
739 tmp & HDMI_COLOR_RANGE_16_235)
740 pipe_config->limited_color_range = true;
742 pipe_config->adjusted_mode.flags |= flags;
744 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
745 dotclock = pipe_config->port_clock * 2 / 3;
747 dotclock = pipe_config->port_clock;
749 if (HAS_PCH_SPLIT(dev_priv->dev))
750 ironlake_check_encoder_dotclock(pipe_config, dotclock);
752 pipe_config->adjusted_mode.crtc_clock = dotclock;
755 static void intel_enable_hdmi(struct intel_encoder *encoder)
757 struct drm_device *dev = encoder->base.dev;
758 struct drm_i915_private *dev_priv = dev->dev_private;
759 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
760 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
762 u32 enable_bits = SDVO_ENABLE;
764 if (intel_crtc->config.has_audio)
765 enable_bits |= SDVO_AUDIO_ENABLE;
767 temp = I915_READ(intel_hdmi->hdmi_reg);
769 /* HW workaround for IBX, we need to move the port to transcoder A
770 * before disabling it, so restore the transcoder select bit here. */
771 if (HAS_PCH_IBX(dev))
772 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
774 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
775 * we do this anyway which shows more stable in testing.
777 if (HAS_PCH_SPLIT(dev)) {
778 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
779 POSTING_READ(intel_hdmi->hdmi_reg);
784 I915_WRITE(intel_hdmi->hdmi_reg, temp);
785 POSTING_READ(intel_hdmi->hdmi_reg);
787 /* HW workaround, need to write this twice for issue that may result
788 * in first write getting masked.
790 if (HAS_PCH_SPLIT(dev)) {
791 I915_WRITE(intel_hdmi->hdmi_reg, temp);
792 POSTING_READ(intel_hdmi->hdmi_reg);
796 static void vlv_enable_hdmi(struct intel_encoder *encoder)
800 static void intel_disable_hdmi(struct intel_encoder *encoder)
802 struct drm_device *dev = encoder->base.dev;
803 struct drm_i915_private *dev_priv = dev->dev_private;
804 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
806 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
808 temp = I915_READ(intel_hdmi->hdmi_reg);
810 /* HW workaround for IBX, we need to move the port to transcoder A
811 * before disabling it. */
812 if (HAS_PCH_IBX(dev)) {
813 struct drm_crtc *crtc = encoder->base.crtc;
814 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
816 if (temp & SDVO_PIPE_B_SELECT) {
817 temp &= ~SDVO_PIPE_B_SELECT;
818 I915_WRITE(intel_hdmi->hdmi_reg, temp);
819 POSTING_READ(intel_hdmi->hdmi_reg);
821 /* Again we need to write this twice. */
822 I915_WRITE(intel_hdmi->hdmi_reg, temp);
823 POSTING_READ(intel_hdmi->hdmi_reg);
825 /* Transcoder selection bits only update
826 * effectively on vblank. */
828 intel_wait_for_vblank(dev, pipe);
834 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
835 * we do this anyway which shows more stable in testing.
837 if (HAS_PCH_SPLIT(dev)) {
838 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
839 POSTING_READ(intel_hdmi->hdmi_reg);
842 temp &= ~enable_bits;
844 I915_WRITE(intel_hdmi->hdmi_reg, temp);
845 POSTING_READ(intel_hdmi->hdmi_reg);
847 /* HW workaround, need to write this twice for issue that may result
848 * in first write getting masked.
850 if (HAS_PCH_SPLIT(dev)) {
851 I915_WRITE(intel_hdmi->hdmi_reg, temp);
852 POSTING_READ(intel_hdmi->hdmi_reg);
856 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
858 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
860 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
862 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
868 static enum drm_mode_status
869 intel_hdmi_mode_valid(struct drm_connector *connector,
870 struct drm_display_mode *mode)
872 int clock = mode->clock;
874 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
877 if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
879 return MODE_CLOCK_HIGH;
881 return MODE_CLOCK_LOW;
883 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
884 return MODE_NO_DBLESCAN;
889 static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
891 struct drm_device *dev = crtc->base.dev;
892 struct intel_encoder *encoder;
893 int count = 0, count_hdmi = 0;
895 if (HAS_GMCH_DISPLAY(dev))
898 for_each_intel_encoder(dev, encoder) {
899 if (encoder->new_crtc != crtc)
902 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
907 * HDMI 12bpc affects the clocks, so it's only possible
908 * when not cloning with other encoder types.
910 return count_hdmi > 0 && count_hdmi == count;
913 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
914 struct intel_crtc_config *pipe_config)
916 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
917 struct drm_device *dev = encoder->base.dev;
918 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
919 int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
920 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
923 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
925 if (intel_hdmi->color_range_auto) {
926 /* See CEA-861-E - 5.1 Default Encoding Parameters */
927 if (pipe_config->has_hdmi_sink &&
928 drm_match_cea_mode(adjusted_mode) > 1)
929 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
931 intel_hdmi->color_range = 0;
934 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
935 pipe_config->pixel_multiplier = 2;
938 if (intel_hdmi->color_range)
939 pipe_config->limited_color_range = true;
941 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
942 pipe_config->has_pch_encoder = true;
944 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
945 pipe_config->has_audio = true;
948 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
949 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
950 * outputs. We also need to check that the higher clock still fits
953 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
954 clock_12bpc <= portclock_limit &&
955 hdmi_12bpc_possible(encoder->new_crtc)) {
956 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
959 /* Need to adjust the port link by 1.5x for 12bpc. */
960 pipe_config->port_clock = clock_12bpc;
962 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
966 if (!pipe_config->bw_constrained) {
967 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
968 pipe_config->pipe_bpp = desired_bpp;
971 if (adjusted_mode->crtc_clock > portclock_limit) {
972 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
980 intel_hdmi_unset_edid(struct drm_connector *connector)
982 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
984 intel_hdmi->has_hdmi_sink = false;
985 intel_hdmi->has_audio = false;
986 intel_hdmi->rgb_quant_range_selectable = false;
988 kfree(to_intel_connector(connector)->detect_edid);
989 to_intel_connector(connector)->detect_edid = NULL;
993 intel_hdmi_set_edid(struct drm_connector *connector)
995 struct drm_i915_private *dev_priv = to_i915(connector->dev);
996 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
997 struct intel_encoder *intel_encoder =
998 &hdmi_to_dig_port(intel_hdmi)->base;
999 enum intel_display_power_domain power_domain;
1001 bool connected = false;
1003 power_domain = intel_display_port_power_domain(intel_encoder);
1004 intel_display_power_get(dev_priv, power_domain);
1006 edid = drm_get_edid(connector,
1007 intel_gmbus_get_adapter(dev_priv,
1008 intel_hdmi->ddc_bus));
1010 intel_display_power_put(dev_priv, power_domain);
1012 to_intel_connector(connector)->detect_edid = edid;
1013 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1014 intel_hdmi->rgb_quant_range_selectable =
1015 drm_rgb_quant_range_selectable(edid);
1017 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1018 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1019 intel_hdmi->has_audio =
1020 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1022 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1023 intel_hdmi->has_hdmi_sink =
1024 drm_detect_hdmi_monitor(edid);
1032 static enum drm_connector_status
1033 intel_hdmi_detect(struct drm_connector *connector, bool force)
1035 enum drm_connector_status status;
1037 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1038 connector->base.id, connector->name);
1040 intel_hdmi_unset_edid(connector);
1042 if (intel_hdmi_set_edid(connector)) {
1043 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1045 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1046 status = connector_status_connected;
1048 status = connector_status_disconnected;
1054 intel_hdmi_force(struct drm_connector *connector)
1056 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1058 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1059 connector->base.id, connector->name);
1061 intel_hdmi_unset_edid(connector);
1063 if (connector->status != connector_status_connected)
1066 intel_hdmi_set_edid(connector);
1067 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1070 static int intel_hdmi_get_modes(struct drm_connector *connector)
1074 edid = to_intel_connector(connector)->detect_edid;
1078 return intel_connector_update_modes(connector, edid);
1082 intel_hdmi_detect_audio(struct drm_connector *connector)
1084 bool has_audio = false;
1087 edid = to_intel_connector(connector)->detect_edid;
1088 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1089 has_audio = drm_detect_monitor_audio(edid);
1095 intel_hdmi_set_property(struct drm_connector *connector,
1096 struct drm_property *property,
1099 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1100 struct intel_digital_port *intel_dig_port =
1101 hdmi_to_dig_port(intel_hdmi);
1102 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1105 ret = drm_object_property_set_value(&connector->base, property, val);
1109 if (property == dev_priv->force_audio_property) {
1110 enum hdmi_force_audio i = val;
1113 if (i == intel_hdmi->force_audio)
1116 intel_hdmi->force_audio = i;
1118 if (i == HDMI_AUDIO_AUTO)
1119 has_audio = intel_hdmi_detect_audio(connector);
1121 has_audio = (i == HDMI_AUDIO_ON);
1123 if (i == HDMI_AUDIO_OFF_DVI)
1124 intel_hdmi->has_hdmi_sink = 0;
1126 intel_hdmi->has_audio = has_audio;
1130 if (property == dev_priv->broadcast_rgb_property) {
1131 bool old_auto = intel_hdmi->color_range_auto;
1132 uint32_t old_range = intel_hdmi->color_range;
1135 case INTEL_BROADCAST_RGB_AUTO:
1136 intel_hdmi->color_range_auto = true;
1138 case INTEL_BROADCAST_RGB_FULL:
1139 intel_hdmi->color_range_auto = false;
1140 intel_hdmi->color_range = 0;
1142 case INTEL_BROADCAST_RGB_LIMITED:
1143 intel_hdmi->color_range_auto = false;
1144 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1150 if (old_auto == intel_hdmi->color_range_auto &&
1151 old_range == intel_hdmi->color_range)
1157 if (property == connector->dev->mode_config.aspect_ratio_property) {
1159 case DRM_MODE_PICTURE_ASPECT_NONE:
1160 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1162 case DRM_MODE_PICTURE_ASPECT_4_3:
1163 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1165 case DRM_MODE_PICTURE_ASPECT_16_9:
1166 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1177 if (intel_dig_port->base.base.crtc)
1178 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1183 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1185 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1186 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1187 struct drm_display_mode *adjusted_mode =
1188 &intel_crtc->config.adjusted_mode;
1190 intel_hdmi_prepare(encoder);
1192 intel_hdmi->set_infoframes(&encoder->base,
1193 intel_crtc->config.has_hdmi_sink,
1197 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1199 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1200 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1201 struct drm_device *dev = encoder->base.dev;
1202 struct drm_i915_private *dev_priv = dev->dev_private;
1203 struct intel_crtc *intel_crtc =
1204 to_intel_crtc(encoder->base.crtc);
1205 struct drm_display_mode *adjusted_mode =
1206 &intel_crtc->config.adjusted_mode;
1207 enum dpio_channel port = vlv_dport_to_channel(dport);
1208 int pipe = intel_crtc->pipe;
1211 /* Enable clock channels for this port */
1212 mutex_lock(&dev_priv->dpio_lock);
1213 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1220 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1223 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1224 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1225 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1226 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1227 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1228 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1229 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1230 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1232 /* Program lane clock */
1233 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1234 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1235 mutex_unlock(&dev_priv->dpio_lock);
1237 intel_hdmi->set_infoframes(&encoder->base,
1238 intel_crtc->config.has_hdmi_sink,
1241 intel_enable_hdmi(encoder);
1243 vlv_wait_port_ready(dev_priv, dport);
1246 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1248 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1249 struct drm_device *dev = encoder->base.dev;
1250 struct drm_i915_private *dev_priv = dev->dev_private;
1251 struct intel_crtc *intel_crtc =
1252 to_intel_crtc(encoder->base.crtc);
1253 enum dpio_channel port = vlv_dport_to_channel(dport);
1254 int pipe = intel_crtc->pipe;
1256 intel_hdmi_prepare(encoder);
1258 /* Program Tx lane resets to default */
1259 mutex_lock(&dev_priv->dpio_lock);
1260 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1261 DPIO_PCS_TX_LANE2_RESET |
1262 DPIO_PCS_TX_LANE1_RESET);
1263 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1264 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1265 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1266 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1267 DPIO_PCS_CLK_SOFT_RESET);
1269 /* Fix up inter-pair skew failure */
1270 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1271 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1272 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1274 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1275 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1276 mutex_unlock(&dev_priv->dpio_lock);
1279 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1281 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1282 struct drm_device *dev = encoder->base.dev;
1283 struct drm_i915_private *dev_priv = dev->dev_private;
1284 struct intel_crtc *intel_crtc =
1285 to_intel_crtc(encoder->base.crtc);
1286 enum dpio_channel ch = vlv_dport_to_channel(dport);
1287 enum pipe pipe = intel_crtc->pipe;
1290 intel_hdmi_prepare(encoder);
1292 mutex_lock(&dev_priv->dpio_lock);
1294 /* program left/right clock distribution */
1295 if (pipe != PIPE_B) {
1296 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1297 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1299 val |= CHV_BUFLEFTENA1_FORCE;
1301 val |= CHV_BUFRIGHTENA1_FORCE;
1302 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1304 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1305 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1307 val |= CHV_BUFLEFTENA2_FORCE;
1309 val |= CHV_BUFRIGHTENA2_FORCE;
1310 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1313 /* program clock channel usage */
1314 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1315 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1317 val &= ~CHV_PCS_USEDCLKCHANNEL;
1319 val |= CHV_PCS_USEDCLKCHANNEL;
1320 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1322 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1323 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1325 val &= ~CHV_PCS_USEDCLKCHANNEL;
1327 val |= CHV_PCS_USEDCLKCHANNEL;
1328 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1331 * This a a bit weird since generally CL
1332 * matches the pipe, but here we need to
1333 * pick the CL based on the port.
1335 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1337 val &= ~CHV_CMN_USEDCLKCHANNEL;
1339 val |= CHV_CMN_USEDCLKCHANNEL;
1340 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1342 mutex_unlock(&dev_priv->dpio_lock);
1345 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1347 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1348 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1349 struct intel_crtc *intel_crtc =
1350 to_intel_crtc(encoder->base.crtc);
1351 enum dpio_channel port = vlv_dport_to_channel(dport);
1352 int pipe = intel_crtc->pipe;
1354 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1355 mutex_lock(&dev_priv->dpio_lock);
1356 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1357 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1358 mutex_unlock(&dev_priv->dpio_lock);
1361 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1363 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1364 struct drm_device *dev = encoder->base.dev;
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366 struct intel_crtc *intel_crtc =
1367 to_intel_crtc(encoder->base.crtc);
1368 enum dpio_channel ch = vlv_dport_to_channel(dport);
1369 enum pipe pipe = intel_crtc->pipe;
1372 mutex_lock(&dev_priv->dpio_lock);
1374 /* Propagate soft reset to data lane reset */
1375 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1376 val |= CHV_PCS_REQ_SOFTRESET_EN;
1377 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1379 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1380 val |= CHV_PCS_REQ_SOFTRESET_EN;
1381 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1383 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1384 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1385 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1387 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1388 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1389 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1391 mutex_unlock(&dev_priv->dpio_lock);
1394 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1396 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1397 struct drm_device *dev = encoder->base.dev;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 struct intel_crtc *intel_crtc =
1400 to_intel_crtc(encoder->base.crtc);
1401 enum dpio_channel ch = vlv_dport_to_channel(dport);
1402 int pipe = intel_crtc->pipe;
1406 mutex_lock(&dev_priv->dpio_lock);
1408 /* Deassert soft data lane reset*/
1409 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1410 val |= CHV_PCS_REQ_SOFTRESET_EN;
1411 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1413 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1414 val |= CHV_PCS_REQ_SOFTRESET_EN;
1415 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1417 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1418 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1419 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1421 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1422 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1423 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1425 /* Program Tx latency optimal setting */
1426 for (i = 0; i < 4; i++) {
1427 /* Set the latency optimal bit */
1428 data = (i == 1) ? 0x0 : 0x6;
1429 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1430 data << DPIO_FRC_LATENCY_SHFIT);
1432 /* Set the upar bit */
1433 data = (i == 1) ? 0x0 : 0x1;
1434 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1435 data << DPIO_UPAR_SHIFT);
1438 /* Data lane stagger programming */
1439 /* FIXME: Fix up value only after power analysis */
1441 /* Clear calc init */
1442 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1443 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1444 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1446 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1447 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1448 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1450 /* FIXME: Program the support xxx V-dB */
1452 for (i = 0; i < 4; i++) {
1453 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1454 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1455 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1456 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1459 for (i = 0; i < 4; i++) {
1460 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1461 val &= ~DPIO_SWING_MARGIN000_MASK;
1462 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1463 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1466 /* Disable unique transition scale */
1467 for (i = 0; i < 4; i++) {
1468 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1469 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1470 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1473 /* Additional steps for 1200mV-0dB */
1475 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1477 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1479 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1480 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1482 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1483 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1484 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1486 /* Start swing calculation */
1487 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1488 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1489 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1491 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1492 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1493 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1496 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1497 val |= DPIO_LRC_BYPASS;
1498 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1500 mutex_unlock(&dev_priv->dpio_lock);
1502 intel_enable_hdmi(encoder);
1504 vlv_wait_port_ready(dev_priv, dport);
1507 static void intel_hdmi_destroy(struct drm_connector *connector)
1509 kfree(to_intel_connector(connector)->detect_edid);
1510 drm_connector_cleanup(connector);
1514 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1515 .dpms = intel_connector_dpms,
1516 .detect = intel_hdmi_detect,
1517 .force = intel_hdmi_force,
1518 .fill_modes = drm_helper_probe_single_connector_modes,
1519 .set_property = intel_hdmi_set_property,
1520 .destroy = intel_hdmi_destroy,
1523 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1524 .get_modes = intel_hdmi_get_modes,
1525 .mode_valid = intel_hdmi_mode_valid,
1526 .best_encoder = intel_best_encoder,
1529 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1530 .destroy = intel_encoder_destroy,
1534 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1536 if (!drm_mode_create_aspect_ratio_property(connector->dev))
1537 drm_object_attach_property(&connector->base,
1538 connector->dev->mode_config.aspect_ratio_property,
1539 DRM_MODE_PICTURE_ASPECT_NONE);
1543 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1545 intel_attach_force_audio_property(connector);
1546 intel_attach_broadcast_rgb_property(connector);
1547 intel_hdmi->color_range_auto = true;
1548 intel_attach_aspect_ratio_property(connector);
1549 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1552 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1553 struct intel_connector *intel_connector)
1555 struct drm_connector *connector = &intel_connector->base;
1556 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1557 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1558 struct drm_device *dev = intel_encoder->base.dev;
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 enum port port = intel_dig_port->port;
1562 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1563 DRM_MODE_CONNECTOR_HDMIA);
1564 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1566 connector->interlace_allowed = 1;
1567 connector->doublescan_allowed = 0;
1568 connector->stereo_allowed = 1;
1572 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1573 intel_encoder->hpd_pin = HPD_PORT_B;
1576 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1577 intel_encoder->hpd_pin = HPD_PORT_C;
1580 if (IS_CHERRYVIEW(dev))
1581 intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
1583 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1584 intel_encoder->hpd_pin = HPD_PORT_D;
1587 intel_encoder->hpd_pin = HPD_PORT_A;
1588 /* Internal port only for eDP. */
1593 if (IS_VALLEYVIEW(dev)) {
1594 intel_hdmi->write_infoframe = vlv_write_infoframe;
1595 intel_hdmi->set_infoframes = vlv_set_infoframes;
1596 } else if (IS_G4X(dev)) {
1597 intel_hdmi->write_infoframe = g4x_write_infoframe;
1598 intel_hdmi->set_infoframes = g4x_set_infoframes;
1599 } else if (HAS_DDI(dev)) {
1600 intel_hdmi->write_infoframe = hsw_write_infoframe;
1601 intel_hdmi->set_infoframes = hsw_set_infoframes;
1602 } else if (HAS_PCH_IBX(dev)) {
1603 intel_hdmi->write_infoframe = ibx_write_infoframe;
1604 intel_hdmi->set_infoframes = ibx_set_infoframes;
1606 intel_hdmi->write_infoframe = cpt_write_infoframe;
1607 intel_hdmi->set_infoframes = cpt_set_infoframes;
1611 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1613 intel_connector->get_hw_state = intel_connector_get_hw_state;
1614 intel_connector->unregister = intel_connector_unregister;
1616 intel_hdmi_add_properties(intel_hdmi, connector);
1618 intel_connector_attach_encoder(intel_connector, intel_encoder);
1619 drm_connector_register(connector);
1621 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1622 * 0xd. Failure to do so will result in spurious interrupts being
1623 * generated on the port when a cable is not attached.
1625 if (IS_G4X(dev) && !IS_GM45(dev)) {
1626 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1627 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1631 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1633 struct intel_digital_port *intel_dig_port;
1634 struct intel_encoder *intel_encoder;
1635 struct intel_connector *intel_connector;
1637 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1638 if (!intel_dig_port)
1641 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1642 if (!intel_connector) {
1643 kfree(intel_dig_port);
1647 intel_encoder = &intel_dig_port->base;
1649 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1650 DRM_MODE_ENCODER_TMDS);
1652 intel_encoder->compute_config = intel_hdmi_compute_config;
1653 intel_encoder->disable = intel_disable_hdmi;
1654 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1655 intel_encoder->get_config = intel_hdmi_get_config;
1656 if (IS_CHERRYVIEW(dev)) {
1657 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1658 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1659 intel_encoder->enable = vlv_enable_hdmi;
1660 intel_encoder->post_disable = chv_hdmi_post_disable;
1661 } else if (IS_VALLEYVIEW(dev)) {
1662 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1663 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1664 intel_encoder->enable = vlv_enable_hdmi;
1665 intel_encoder->post_disable = vlv_hdmi_post_disable;
1667 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1668 intel_encoder->enable = intel_enable_hdmi;
1671 intel_encoder->type = INTEL_OUTPUT_HDMI;
1672 if (IS_CHERRYVIEW(dev)) {
1674 intel_encoder->crtc_mask = 1 << 2;
1676 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1678 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1680 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1682 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1683 * to work on real hardware. And since g4x can send infoframes to
1684 * only one port anyway, nothing is lost by allowing it.
1687 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1689 intel_dig_port->port = port;
1690 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1691 intel_dig_port->dp.output_reg = 0;
1693 intel_hdmi_init_connector(intel_dig_port, intel_connector);