drivers/gpu/drm/i915/intel_lrc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *    Michel Thierry <michel.thierry@intel.com>
  26  *    Thomas Daniel <thomas.daniel@intel.com>
  27  *    Oscar Mateo <oscar.mateo@intel.com>
  28  *
  29  */
  30
  31 /**
  32  * DOC: Logical Rings, Logical Ring Contexts and Execlists
  33  *
  34  * Motivation:
  35  * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
  36  * These expanded contexts enable a number of new abilities, especially
  37  * "Execlists" (also implemented in this file).
  38  *
  39  * One of the main differences with the legacy HW contexts is that logical
  40  * ring contexts incorporate many more things to the context's state, like
  41  * PDPs or ringbuffer control registers:
  42  *
  43  * The reason why PDPs are included in the context is straightforward: as
  44  * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
  45  * contained there mean you don't need to do a ppgtt->switch_mm yourself,
  46  * instead, the GPU will do it for you on the context switch.
  47  *
  48  * But, what about the ringbuffer control registers (head, tail, etc..)?
  49  * shouldn't we just need a set of those per engine command streamer? This is
  50  * where the name "Logical Rings" starts to make sense: by virtualizing the
  51  * rings, the engine cs shifts to a new "ring buffer" with every context
  52  * switch. When you want to submit a workload to the GPU you: A) choose your
  53  * context, B) find its appropriate virtualized ring, C) write commands to it
  54  * and then, finally, D) tell the GPU to switch to that context.
  55  *
  56  * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
  57  * to a contexts is via a context execution list, ergo "Execlists".
  58  *
  59  * LRC implementation:
  60  * Regarding the creation of contexts, we have:
  61  *
  62  * - One global default context.
  63  * - One local default context for each opened fd.
  64  * - One local extra context for each context create ioctl call.
  65  *
  66  * Now that ringbuffers belong per-context (and not per-engine, like before)
  67  * and that contexts are uniquely tied to a given engine (and not reusable,
  68  * like before) we need:
  69  *
  70  * - One ringbuffer per-engine inside each context.
  71  * - One backing object per-engine inside each context.
  72  *
  73  * The global default context starts its life with these new objects fully
  74  * allocated and populated. The local default context for each opened fd is
  75  * more complex, because we don't know at creation time which engine is going
  76  * to use them. To handle this, we have implemented a deferred creation of LR
  77  * contexts:
  78  *
  79  * The local context starts its life as a hollow or blank holder, that only
  80  * gets populated for a given engine once we receive an execbuffer. If later
  81  * on we receive another execbuffer ioctl for the same context but a different
  82  * engine, we allocate/populate a new ringbuffer and context backing object and
  83  * so on.
  84  *
  85  * Finally, regarding local contexts created using the ioctl call: as they are
  86  * only allowed with the render ring, we can allocate & populate them right
  87  * away (no need to defer anything, at least for now).
  88  *
  89  * Execlists implementation:
  90  * Execlists are the new method by which, on gen8+ hardware, workloads are
  91  * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
  92  * This method works as follows:
  93  *
  94  * When a request is committed, its commands (the BB start and any leading or
  95  * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
  96  * for the appropriate context. The tail pointer in the hardware context is not
  97  * updated at this time, but instead, kept by the driver in the ringbuffer
  98  * structure. A structure representing this request is added to a request queue
  99  * for the appropriate engine: this structure contains a copy of the context's
 100  * tail after the request was written to the ring buffer and a pointer to the
 101  * context itself.
 102  *
 103  * If the engine's request queue was empty before the request was added, the
 104  * queue is processed immediately. Otherwise the queue will be processed during
 105  * a context switch interrupt. In any case, elements on the queue will get sent
 106  * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 107  * globally unique 20-bits submission ID.
 108  *
 109  * When execution of a request completes, the GPU updates the context status
 110  * buffer with a context complete event and generates a context switch interrupt.
 111  * During the interrupt handling, the driver examines the events in the buffer:
 112  * for each context complete event, if the announced ID matches that on the head
 113  * of the request queue, then that request is retired and removed from the queue.
 114  *
 115  * After processing, if any requests were retired and the queue is not empty
 116  * then a new execution list can be submitted. The two requests at the front of
 117  * the queue are next to be submitted but since a context may not occur twice in
 118  * an execution list, if subsequent requests have the same ID as the first then
 119  * the two requests must be combined. This is done simply by discarding requests
 120  * at the head of the queue until either only one requests is left (in which case
 121  * we use a NULL second context) or the first two requests have unique IDs.
 122  *
 123  * By always executing the first two requests in the queue the driver ensures
 124  * that the GPU is kept as busy as possible. In the case where a single context
 125  * completes but a second context is still executing, the request for this second
 126  * context will be at the head of the queue when we remove the first one. This
 127  * request will then be resubmitted along with a new request for a different context,
 128  * which will cause the hardware to continue executing the second request and queue
 129  * the new request (the GPU detects the condition of a context getting preempted
 130  * with the same context and optimizes the context switch flow by not doing
 131  * preemption, but just sampling the new tail pointer).
 132  *
 133  */
 134
 135 #include <drm/drmP.h>
 136 #include <drm/i915_drm.h>
 137 #include "i915_drv.h"
 138
 139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
 140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
 141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
 142
 143 #define RING_EXECLIST_QFULL             (1 << 0x2)
 144 #define RING_EXECLIST1_VALID            (1 << 0x3)
 145 #define RING_EXECLIST0_VALID            (1 << 0x4)
 146 #define RING_EXECLIST_ACTIVE_STATUS     (3 << 0xE)
 147 #define RING_EXECLIST1_ACTIVE           (1 << 0x11)
 148 #define RING_EXECLIST0_ACTIVE           (1 << 0x12)
 149
 150 #define GEN8_CTX_STATUS_IDLE_ACTIVE     (1 << 0)
 151 #define GEN8_CTX_STATUS_PREEMPTED       (1 << 1)
 152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH  (1 << 2)
 153 #define GEN8_CTX_STATUS_ACTIVE_IDLE     (1 << 3)
 154 #define GEN8_CTX_STATUS_COMPLETE        (1 << 4)
 155 #define GEN8_CTX_STATUS_LITE_RESTORE    (1 << 15)
 156
 157 #define CTX_LRI_HEADER_0                0x01
 158 #define CTX_CONTEXT_CONTROL             0x02
 159 #define CTX_RING_HEAD                   0x04
 160 #define CTX_RING_TAIL                   0x06
 161 #define CTX_RING_BUFFER_START           0x08
 162 #define CTX_RING_BUFFER_CONTROL         0x0a
 163 #define CTX_BB_HEAD_U                   0x0c
 164 #define CTX_BB_HEAD_L                   0x0e
 165 #define CTX_BB_STATE                    0x10
 166 #define CTX_SECOND_BB_HEAD_U            0x12
 167 #define CTX_SECOND_BB_HEAD_L            0x14
 168 #define CTX_SECOND_BB_STATE             0x16
 169 #define CTX_BB_PER_CTX_PTR              0x18
 170 #define CTX_RCS_INDIRECT_CTX            0x1a
 171 #define CTX_RCS_INDIRECT_CTX_OFFSET     0x1c
 172 #define CTX_LRI_HEADER_1                0x21
 173 #define CTX_CTX_TIMESTAMP               0x22
 174 #define CTX_PDP3_UDW                    0x24
 175 #define CTX_PDP3_LDW                    0x26
 176 #define CTX_PDP2_UDW                    0x28
 177 #define CTX_PDP2_LDW                    0x2a
 178 #define CTX_PDP1_UDW                    0x2c
 179 #define CTX_PDP1_LDW                    0x2e
 180 #define CTX_PDP0_UDW                    0x30
 181 #define CTX_PDP0_LDW                    0x32
 182 #define CTX_LRI_HEADER_2                0x41
 183 #define CTX_R_PWR_CLK_STATE             0x42
 184 #define CTX_GPGPU_CSR_BASE_ADDRESS      0x44
 185
 186 #define GEN8_CTX_VALID (1<<0)
 187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
 188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
 189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
 190 #define GEN8_CTX_PRIVILEGE (1<<8)
 191 enum {
 192         ADVANCED_CONTEXT = 0,
 193         LEGACY_CONTEXT,
 194         ADVANCED_AD_CONTEXT,
 195         LEGACY_64B_CONTEXT
 196 };
 197 #define GEN8_CTX_MODE_SHIFT 3
 198 enum {
 199         FAULT_AND_HANG = 0,
 200         FAULT_AND_HALT, /* Debug only */
 201         FAULT_AND_STREAM,
 202         FAULT_AND_CONTINUE /* Unsupported */
 203 };
 204 #define GEN8_CTX_ID_SHIFT 32
 205
 206 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 207                 struct intel_context *ctx);
 208
 209 /**
 210  * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 211  * @dev: DRM device.
 212  * @enable_execlists: value of i915.enable_execlists module parameter.
 213  *
 214  * Only certain platforms support Execlists (the prerequisites being
 215  * support for Logical Ring Contexts and Aliasing PPGTT or better).
 216  *
 217  * Return: 1 if Execlists is supported and has to be enabled.
 218  */
 219 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
 220 {
 221         WARN_ON(i915.enable_ppgtt == -1);
 222
 223         if (INTEL_INFO(dev)->gen >= 9)
 224                 return 1;
 225
 226         if (enable_execlists == 0)
 227                 return 0;
 228
 229         if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
 230             i915.use_mmio_flip >= 0)
 231                 return 1;
 232
 233         return 0;
 234 }
 235
 236 /**
 237  * intel_execlists_ctx_id() - get the Execlists Context ID
 238  * @ctx_obj: Logical Ring Context backing object.
 239  *
 240  * Do not confuse with ctx->id! Unfortunately we have a name overload
 241  * here: the old context ID we pass to userspace as a handler so that
 242  * they can refer to a context, and the new context ID we pass to the
 243  * ELSP so that the GPU can inform us of the context status via
 244  * interrupts.
 245  *
 246  * Return: 20-bits globally unique context ID.
 247  */
 248 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
 249 {
 250         u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 251
 252         /* LRCA is required to be 4K aligned so the more significant 20 bits
 253          * are globally unique */
 254         return lrca >> 12;
 255 }
 256
 257 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
 258 {
 259         uint64_t desc;
 260         uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 261
 262         WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
 263
 264         desc = GEN8_CTX_VALID;
 265         desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
 266         desc |= GEN8_CTX_L3LLC_COHERENT;
 267         desc |= GEN8_CTX_PRIVILEGE;
 268         desc |= lrca;
 269         desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
 270
 271         /* TODO: WaDisableLiteRestore when we start using semaphore
 272          * signalling between Command Streamers */
 273         /* desc |= GEN8_CTX_FORCE_RESTORE; */
 274
 275         return desc;
 276 }
 277
 278 static void execlists_elsp_write(struct intel_engine_cs *ring,
 279                                  struct drm_i915_gem_object *ctx_obj0,
 280                                  struct drm_i915_gem_object *ctx_obj1)
 281 {
 282         struct drm_device *dev = ring->dev;
 283         struct drm_i915_private *dev_priv = dev->dev_private;
 284         uint64_t temp = 0;
 285         uint32_t desc[4];
 286         unsigned long flags;
 287
 288         /* XXX: You must always write both descriptors in the order below. */
 289         if (ctx_obj1)
 290                 temp = execlists_ctx_descriptor(ctx_obj1);
 291         else
 292                 temp = 0;
 293         desc[1] = (u32)(temp >> 32);
 294         desc[0] = (u32)temp;
 295
 296         temp = execlists_ctx_descriptor(ctx_obj0);
 297         desc[3] = (u32)(temp >> 32);
 298         desc[2] = (u32)temp;
 299
 300         /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes
 301          * are in progress.
 302          *
 303          * The other problem is that we can't just call gen6_gt_force_wake_get()
 304          * because that function calls intel_runtime_pm_get(), which might sleep.
 305          * Instead, we do the runtime_pm_get/put when creating/destroying requests.
 306          */
 307         spin_lock_irqsave(&dev_priv->uncore.lock, flags);
 308         if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
 309                 if (dev_priv->uncore.fw_rendercount++ == 0)
 310                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 311                                                               FORCEWAKE_RENDER);
 312                 if (dev_priv->uncore.fw_mediacount++ == 0)
 313                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 314                                                               FORCEWAKE_MEDIA);
 315                 if (INTEL_INFO(dev)->gen >= 9) {
 316                         if (dev_priv->uncore.fw_blittercount++ == 0)
 317                                 dev_priv->uncore.funcs.force_wake_get(dev_priv,
 318                                                         FORCEWAKE_BLITTER);
 319                 }
 320         } else {
 321                 if (dev_priv->uncore.forcewake_count++ == 0)
 322                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 323                                                               FORCEWAKE_ALL);
 324         }
 325         spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 326
 327         I915_WRITE(RING_ELSP(ring), desc[1]);
 328         I915_WRITE(RING_ELSP(ring), desc[0]);
 329         I915_WRITE(RING_ELSP(ring), desc[3]);
 330         /* The context is automatically loaded after the following */
 331         I915_WRITE(RING_ELSP(ring), desc[2]);
 332
 333         /* ELSP is a wo register, so use another nearby reg for posting instead */
 334         POSTING_READ(RING_EXECLIST_STATUS(ring));
 335
 336         /* Release Force Wakeup (see the big comment above). */
 337         spin_lock_irqsave(&dev_priv->uncore.lock, flags);
 338         if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
 339                 if (--dev_priv->uncore.fw_rendercount == 0)
 340                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 341                                                               FORCEWAKE_RENDER);
 342                 if (--dev_priv->uncore.fw_mediacount == 0)
 343                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 344                                                               FORCEWAKE_MEDIA);
 345                 if (INTEL_INFO(dev)->gen >= 9) {
 346                         if (--dev_priv->uncore.fw_blittercount == 0)
 347                                 dev_priv->uncore.funcs.force_wake_put(dev_priv,
 348                                                         FORCEWAKE_BLITTER);
 349                 }
 350         } else {
 351                 if (--dev_priv->uncore.forcewake_count == 0)
 352                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 353                                                               FORCEWAKE_ALL);
 354         }
 355
 356         spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 357 }
 358
 359 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
 360                                     struct drm_i915_gem_object *ring_obj,
 361                                     u32 tail)
 362 {
 363         struct page *page;
 364         uint32_t *reg_state;
 365
 366         page = i915_gem_object_get_page(ctx_obj, 1);
 367         reg_state = kmap_atomic(page);
 368
 369         reg_state[CTX_RING_TAIL+1] = tail;
 370         reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
 371
 372         kunmap_atomic(reg_state);
 373
 374         return 0;
 375 }
 376
 377 static void execlists_submit_contexts(struct intel_engine_cs *ring,
 378                                       struct intel_context *to0, u32 tail0,
 379                                       struct intel_context *to1, u32 tail1)
 380 {
 381         struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
 382         struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
 383         struct drm_i915_gem_object *ctx_obj1 = NULL;
 384         struct intel_ringbuffer *ringbuf1 = NULL;
 385
 386         BUG_ON(!ctx_obj0);
 387         WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
 388         WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
 389
 390         execlists_update_context(ctx_obj0, ringbuf0->obj, tail0);
 391
 392         if (to1) {
 393                 ringbuf1 = to1->engine[ring->id].ringbuf;
 394                 ctx_obj1 = to1->engine[ring->id].state;
 395                 BUG_ON(!ctx_obj1);
 396                 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
 397                 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
 398
 399                 execlists_update_context(ctx_obj1, ringbuf1->obj, tail1);
 400         }
 401
 402         execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
 403 }
 404
 405 static void execlists_context_unqueue(struct intel_engine_cs *ring)
 406 {
 407         struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL;
 408         struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL;
 409
 410         assert_spin_locked(&ring->execlist_lock);
 411
 412         if (list_empty(&ring->execlist_queue))
 413                 return;
 414
 415         /* Try to read in pairs */
 416         list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
 417                                  execlist_link) {
 418                 if (!req0) {
 419                         req0 = cursor;
 420                 } else if (req0->ctx == cursor->ctx) {
 421                         /* Same ctx: ignore first request, as second request
 422                          * will update tail past first request's workload */
 423                         cursor->elsp_submitted = req0->elsp_submitted;
 424                         list_del(&req0->execlist_link);
 425                         list_add_tail(&req0->execlist_link,
 426                                 &ring->execlist_retired_req_list);
 427                         req0 = cursor;
 428                 } else {
 429                         req1 = cursor;
 430                         break;
 431                 }
 432         }
 433
 434         WARN_ON(req1 && req1->elsp_submitted);
 435
 436         execlists_submit_contexts(ring, req0->ctx, req0->tail,
 437                                   req1 ? req1->ctx : NULL,
 438                                   req1 ? req1->tail : 0);
 439
 440         req0->elsp_submitted++;
 441         if (req1)
 442                 req1->elsp_submitted++;
 443 }
 444
 445 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
 446                                            u32 request_id)
 447 {
 448         struct intel_ctx_submit_request *head_req;
 449
 450         assert_spin_locked(&ring->execlist_lock);
 451
 452         head_req = list_first_entry_or_null(&ring->execlist_queue,
 453                                             struct intel_ctx_submit_request,
 454                                             execlist_link);
 455
 456         if (head_req != NULL) {
 457                 struct drm_i915_gem_object *ctx_obj =
 458                                 head_req->ctx->engine[ring->id].state;
 459                 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
 460                         WARN(head_req->elsp_submitted == 0,
 461                              "Never submitted head request\n");
 462
 463                         if (--head_req->elsp_submitted <= 0) {
 464                                 list_del(&head_req->execlist_link);
 465                                 list_add_tail(&head_req->execlist_link,
 466                                         &ring->execlist_retired_req_list);
 467                                 return true;
 468                         }
 469                 }
 470         }
 471
 472         return false;
 473 }
 474
 475 /**
 476  * intel_lrc_irq_handler() - handle Context Switch interrupts
 477  * @ring: Engine Command Streamer to handle.
 478  *
 479  * Check the unread Context Status Buffers and manage the submission of new
 480  * contexts to the ELSP accordingly.
 481  */
 482 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
 483 {
 484         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 485         u32 status_pointer;
 486         u8 read_pointer;
 487         u8 write_pointer;
 488         u32 status;
 489         u32 status_id;
 490         u32 submit_contexts = 0;
 491
 492         status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
 493
 494         read_pointer = ring->next_context_status_buffer;
 495         write_pointer = status_pointer & 0x07;
 496         if (read_pointer > write_pointer)
 497                 write_pointer += 6;
 498
 499         spin_lock(&ring->execlist_lock);
 500
 501         while (read_pointer < write_pointer) {
 502                 read_pointer++;
 503                 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 504                                 (read_pointer % 6) * 8);
 505                 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 506                                 (read_pointer % 6) * 8 + 4);
 507
 508                 if (status & GEN8_CTX_STATUS_PREEMPTED) {
 509                         if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
 510                                 if (execlists_check_remove_request(ring, status_id))
 511                                         WARN(1, "Lite Restored request removed from queue\n");
 512                         } else
 513                                 WARN(1, "Preemption without Lite Restore\n");
 514                 }
 515
 516                  if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
 517                      (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
 518                         if (execlists_check_remove_request(ring, status_id))
 519                                 submit_contexts++;
 520                 }
 521         }
 522
 523         if (submit_contexts != 0)
 524                 execlists_context_unqueue(ring);
 525
 526         spin_unlock(&ring->execlist_lock);
 527
 528         WARN(submit_contexts > 2, "More than two context complete events?\n");
 529         ring->next_context_status_buffer = write_pointer % 6;
 530
 531         I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
 532                    ((u32)ring->next_context_status_buffer & 0x07) << 8);
 533 }
 534
 535 static int execlists_context_queue(struct intel_engine_cs *ring,
 536                                    struct intel_context *to,
 537                                    u32 tail)
 538 {
 539         struct intel_ctx_submit_request *req = NULL, *cursor;
 540         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 541         unsigned long flags;
 542         int num_elements = 0;
 543
 544         req = kzalloc(sizeof(*req), GFP_KERNEL);
 545         if (req == NULL)
 546                 return -ENOMEM;
 547         req->ctx = to;
 548         i915_gem_context_reference(req->ctx);
 549
 550         if (to != ring->default_context)
 551                 intel_lr_context_pin(ring, to);
 552
 553         req->ring = ring;
 554         req->tail = tail;
 555
 556         intel_runtime_pm_get(dev_priv);
 557
 558         spin_lock_irqsave(&ring->execlist_lock, flags);
 559
 560         list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
 561                 if (++num_elements > 2)
 562                         break;
 563
 564         if (num_elements > 2) {
 565                 struct intel_ctx_submit_request *tail_req;
 566
 567                 tail_req = list_last_entry(&ring->execlist_queue,
 568                                            struct intel_ctx_submit_request,
 569                                            execlist_link);
 570
 571                 if (to == tail_req->ctx) {
 572                         WARN(tail_req->elsp_submitted != 0,
 573                                 "More than 2 already-submitted reqs queued\n");
 574                         list_del(&tail_req->execlist_link);
 575                         list_add_tail(&tail_req->execlist_link,
 576                                 &ring->execlist_retired_req_list);
 577                 }
 578         }
 579
 580         list_add_tail(&req->execlist_link, &ring->execlist_queue);
 581         if (num_elements == 0)
 582                 execlists_context_unqueue(ring);
 583
 584         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 585
 586         return 0;
 587 }
 588
 589 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf)
 590 {
 591         struct intel_engine_cs *ring = ringbuf->ring;
 592         uint32_t flush_domains;
 593         int ret;
 594
 595         flush_domains = 0;
 596         if (ring->gpu_caches_dirty)
 597                 flush_domains = I915_GEM_GPU_DOMAINS;
 598
 599         ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains);
 600         if (ret)
 601                 return ret;
 602
 603         ring->gpu_caches_dirty = false;
 604         return 0;
 605 }
 606
 607 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
 608                                  struct list_head *vmas)
 609 {
 610         struct intel_engine_cs *ring = ringbuf->ring;
 611         struct i915_vma *vma;
 612         uint32_t flush_domains = 0;
 613         bool flush_chipset = false;
 614         int ret;
 615
 616         list_for_each_entry(vma, vmas, exec_list) {
 617                 struct drm_i915_gem_object *obj = vma->obj;
 618
 619                 ret = i915_gem_object_sync(obj, ring);
 620                 if (ret)
 621                         return ret;
 622
 623                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
 624                         flush_chipset |= i915_gem_clflush_object(obj, false);
 625
 626                 flush_domains |= obj->base.write_domain;
 627         }
 628
 629         if (flush_domains & I915_GEM_DOMAIN_GTT)
 630                 wmb();
 631
 632         /* Unconditionally invalidate gpu caches and ensure that we do flush
 633          * any residual writes from the previous batch.
 634          */
 635         return logical_ring_invalidate_all_caches(ringbuf);
 636 }
 637
 638 /**
 639  * execlists_submission() - submit a batchbuffer for execution, Execlists style
 640  * @dev: DRM device.
 641  * @file: DRM file.
 642  * @ring: Engine Command Streamer to submit to.
 643  * @ctx: Context to employ for this submission.
 644  * @args: execbuffer call arguments.
 645  * @vmas: list of vmas.
 646  * @batch_obj: the batchbuffer to submit.
 647  * @exec_start: batchbuffer start virtual address pointer.
 648  * @flags: translated execbuffer call flags.
 649  *
 650  * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 651  * away the submission details of the execbuffer ioctl call.
 652  *
 653  * Return: non-zero if the submission fails.
 654  */
 655 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
 656                                struct intel_engine_cs *ring,
 657                                struct intel_context *ctx,
 658                                struct drm_i915_gem_execbuffer2 *args,
 659                                struct list_head *vmas,
 660                                struct drm_i915_gem_object *batch_obj,
 661                                u64 exec_start, u32 flags)
 662 {
 663         struct drm_i915_private *dev_priv = dev->dev_private;
 664         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 665         int instp_mode;
 666         u32 instp_mask;
 667         int ret;
 668
 669         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
 670         instp_mask = I915_EXEC_CONSTANTS_MASK;
 671         switch (instp_mode) {
 672         case I915_EXEC_CONSTANTS_REL_GENERAL:
 673         case I915_EXEC_CONSTANTS_ABSOLUTE:
 674         case I915_EXEC_CONSTANTS_REL_SURFACE:
 675                 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
 676                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
 677                         return -EINVAL;
 678                 }
 679
 680                 if (instp_mode != dev_priv->relative_constants_mode) {
 681                         if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
 682                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
 683                                 return -EINVAL;
 684                         }
 685
 686                         /* The HW changed the meaning on this bit on gen6 */
 687                         instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
 688                 }
 689                 break;
 690         default:
 691                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
 692                 return -EINVAL;
 693         }
 694
 695         if (args->num_cliprects != 0) {
 696                 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
 697                 return -EINVAL;
 698         } else {
 699                 if (args->DR4 == 0xffffffff) {
 700                         DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
 701                         args->DR4 = 0;
 702                 }
 703
 704                 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
 705                         DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
 706                         return -EINVAL;
 707                 }
 708         }
 709
 710         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
 711                 DRM_DEBUG("sol reset is gen7 only\n");
 712                 return -EINVAL;
 713         }
 714
 715         ret = execlists_move_to_gpu(ringbuf, vmas);
 716         if (ret)
 717                 return ret;
 718
 719         if (ring == &dev_priv->ring[RCS] &&
 720             instp_mode != dev_priv->relative_constants_mode) {
 721                 ret = intel_logical_ring_begin(ringbuf, 4);
 722                 if (ret)
 723                         return ret;
 724
 725                 intel_logical_ring_emit(ringbuf, MI_NOOP);
 726                 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
 727                 intel_logical_ring_emit(ringbuf, INSTPM);
 728                 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
 729                 intel_logical_ring_advance(ringbuf);
 730
 731                 dev_priv->relative_constants_mode = instp_mode;
 732         }
 733
 734         ret = ring->emit_bb_start(ringbuf, exec_start, flags);
 735         if (ret)
 736                 return ret;
 737
 738         i915_gem_execbuffer_move_to_active(vmas, ring);
 739         i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
 740
 741         return 0;
 742 }
 743
 744 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
 745 {
 746         struct intel_ctx_submit_request *req, *tmp;
 747         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 748         unsigned long flags;
 749         struct list_head retired_list;
 750
 751         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 752         if (list_empty(&ring->execlist_retired_req_list))
 753                 return;
 754
 755         INIT_LIST_HEAD(&retired_list);
 756         spin_lock_irqsave(&ring->execlist_lock, flags);
 757         list_replace_init(&ring->execlist_retired_req_list, &retired_list);
 758         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 759
 760         list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
 761                 struct intel_context *ctx = req->ctx;
 762                 struct drm_i915_gem_object *ctx_obj =
 763                                 ctx->engine[ring->id].state;
 764
 765                 if (ctx_obj && (ctx != ring->default_context))
 766                         intel_lr_context_unpin(ring, ctx);
 767                 intel_runtime_pm_put(dev_priv);
 768                 i915_gem_context_unreference(req->ctx);
 769                 list_del(&req->execlist_link);
 770                 kfree(req);
 771         }
 772 }
 773
 774 void intel_logical_ring_stop(struct intel_engine_cs *ring)
 775 {
 776         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 777         int ret;
 778
 779         if (!intel_ring_initialized(ring))
 780                 return;
 781
 782         ret = intel_ring_idle(ring);
 783         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
 784                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 785                           ring->name, ret);
 786
 787         /* TODO: Is this correct with Execlists enabled? */
 788         I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 789         if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 790                 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 791                 return;
 792         }
 793         I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 794 }
 795
 796 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf)
 797 {
 798         struct intel_engine_cs *ring = ringbuf->ring;
 799         int ret;
 800
 801         if (!ring->gpu_caches_dirty)
 802                 return 0;
 803
 804         ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS);
 805         if (ret)
 806                 return ret;
 807
 808         ring->gpu_caches_dirty = false;
 809         return 0;
 810 }
 811
 812 /**
 813  * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
 814  * @ringbuf: Logical Ringbuffer to advance.
 815  *
 816  * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 817  * really happens during submission is that the context and current tail will be placed
 818  * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 819  * point, the tail *inside* the context is updated and the ELSP written to.
 820  */
 821 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf)
 822 {
 823         struct intel_engine_cs *ring = ringbuf->ring;
 824         struct intel_context *ctx = ringbuf->FIXME_lrc_ctx;
 825
 826         intel_logical_ring_advance(ringbuf);
 827
 828         if (intel_ring_stopped(ring))
 829                 return;
 830
 831         execlists_context_queue(ring, ctx, ringbuf->tail);
 832 }
 833
 834 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 835                 struct intel_context *ctx)
 836 {
 837         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 838         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 839         int ret = 0;
 840
 841         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 842         if (ctx->engine[ring->id].unpin_count++ == 0) {
 843                 ret = i915_gem_obj_ggtt_pin(ctx_obj,
 844                                 GEN8_LR_CONTEXT_ALIGN, 0);
 845                 if (ret)
 846                         goto reset_unpin_count;
 847
 848                 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
 849                 if (ret)
 850                         goto unpin_ctx_obj;
 851         }
 852
 853         return ret;
 854
 855 unpin_ctx_obj:
 856         i915_gem_object_ggtt_unpin(ctx_obj);
 857 reset_unpin_count:
 858         ctx->engine[ring->id].unpin_count = 0;
 859
 860         return ret;
 861 }
 862
 863 void intel_lr_context_unpin(struct intel_engine_cs *ring,
 864                 struct intel_context *ctx)
 865 {
 866         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 867         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 868
 869         if (ctx_obj) {
 870                 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 871                 if (--ctx->engine[ring->id].unpin_count == 0) {
 872                         intel_unpin_ringbuffer_obj(ringbuf);
 873                         i915_gem_object_ggtt_unpin(ctx_obj);
 874                 }
 875         }
 876 }
 877
 878 static int logical_ring_alloc_request(struct intel_engine_cs *ring,
 879                                       struct intel_context *ctx)
 880 {
 881         struct drm_i915_gem_request *request;
 882         struct drm_i915_private *dev_private = ring->dev->dev_private;
 883         int ret;
 884
 885         if (ring->outstanding_lazy_request)
 886                 return 0;
 887
 888         request = kzalloc(sizeof(*request), GFP_KERNEL);
 889         if (request == NULL)
 890                 return -ENOMEM;
 891
 892         if (ctx != ring->default_context) {
 893                 ret = intel_lr_context_pin(ring, ctx);
 894                 if (ret) {
 895                         kfree(request);
 896                         return ret;
 897                 }
 898         }
 899
 900         kref_init(&request->ref);
 901         request->ring = ring;
 902         request->uniq = dev_private->request_uniq++;
 903
 904         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
 905         if (ret) {
 906                 intel_lr_context_unpin(ring, ctx);
 907                 kfree(request);
 908                 return ret;
 909         }
 910
 911         /* Hold a reference to the context this request belongs to
 912          * (we will need it when the time comes to emit/retire the
 913          * request).
 914          */
 915         request->ctx = ctx;
 916         i915_gem_context_reference(request->ctx);
 917
 918         ring->outstanding_lazy_request = request;
 919         return 0;
 920 }
 921
 922 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
 923                                      int bytes)
 924 {
 925         struct intel_engine_cs *ring = ringbuf->ring;
 926         struct drm_i915_gem_request *request;
 927         int ret;
 928
 929         if (intel_ring_space(ringbuf) >= bytes)
 930                 return 0;
 931
 932         list_for_each_entry(request, &ring->request_list, list) {
 933                 /*
 934                  * The request queue is per-engine, so can contain requests
 935                  * from multiple ringbuffers. Here, we must ignore any that
 936                  * aren't from the ringbuffer we're considering.
 937                  */
 938                 struct intel_context *ctx = request->ctx;
 939                 if (ctx->engine[ring->id].ringbuf != ringbuf)
 940                         continue;
 941
 942                 /* Would completion of this request free enough space? */
 943                 if (__intel_ring_space(request->tail, ringbuf->tail,
 944                                        ringbuf->size) >= bytes) {
 945                         break;
 946                 }
 947         }
 948
 949         if (&request->list == &ring->request_list)
 950                 return -ENOSPC;
 951
 952         ret = i915_wait_request(request);
 953         if (ret)
 954                 return ret;
 955
 956         i915_gem_retire_requests_ring(ring);
 957
 958         return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC;
 959 }
 960
 961 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
 962                                        int bytes)
 963 {
 964         struct intel_engine_cs *ring = ringbuf->ring;
 965         struct drm_device *dev = ring->dev;
 966         struct drm_i915_private *dev_priv = dev->dev_private;
 967         unsigned long end;
 968         int ret;
 969
 970         ret = logical_ring_wait_request(ringbuf, bytes);
 971         if (ret != -ENOSPC)
 972                 return ret;
 973
 974         /* Force the context submission in case we have been skipping it */
 975         intel_logical_ring_advance_and_submit(ringbuf);
 976
 977         /* With GEM the hangcheck timer should kick us out of the loop,
 978          * leaving it early runs the risk of corrupting GEM state (due
 979          * to running on almost untested codepaths). But on resume
 980          * timers don't work yet, so prevent a complete hang in that
 981          * case by choosing an insanely large timeout. */
 982         end = jiffies + 60 * HZ;
 983
 984         ret = 0;
 985         do {
 986                 if (intel_ring_space(ringbuf) >= bytes)
 987                         break;
 988
 989                 msleep(1);
 990
 991                 if (dev_priv->mm.interruptible && signal_pending(current)) {
 992                         ret = -ERESTARTSYS;
 993                         break;
 994                 }
 995
 996                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
 997                                            dev_priv->mm.interruptible);
 998                 if (ret)
 999                         break;
1000
1001                 if (time_after(jiffies, end)) {
1002                         ret = -EBUSY;
1003                         break;
1004                 }
1005         } while (1);
1006
1007         return ret;
1008 }
1009
1010 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf)
1011 {
1012         uint32_t __iomem *virt;
1013         int rem = ringbuf->size - ringbuf->tail;
1014
1015         if (ringbuf->space < rem) {
1016                 int ret = logical_ring_wait_for_space(ringbuf, rem);
1017
1018                 if (ret)
1019                         return ret;
1020         }
1021
1022         virt = ringbuf->virtual_start + ringbuf->tail;
1023         rem /= 4;
1024         while (rem--)
1025                 iowrite32(MI_NOOP, virt++);
1026
1027         ringbuf->tail = 0;
1028         intel_ring_update_space(ringbuf);
1029
1030         return 0;
1031 }
1032
1033 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes)
1034 {
1035         int ret;
1036
1037         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1038                 ret = logical_ring_wrap_buffer(ringbuf);
1039                 if (unlikely(ret))
1040                         return ret;
1041         }
1042
1043         if (unlikely(ringbuf->space < bytes)) {
1044                 ret = logical_ring_wait_for_space(ringbuf, bytes);
1045                 if (unlikely(ret))
1046                         return ret;
1047         }
1048
1049         return 0;
1050 }
1051
1052 /**
1053  * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1054  *
1055  * @ringbuf: Logical ringbuffer.
1056  * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1057  *
1058  * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1059  * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1060  * and also preallocates a request (every workload submission is still mediated through
1061  * requests, same as it did with legacy ringbuffer submission).
1062  *
1063  * Return: non-zero if the ringbuffer is not ready to be written to.
1064  */
1065 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords)
1066 {
1067         struct intel_engine_cs *ring = ringbuf->ring;
1068         struct drm_device *dev = ring->dev;
1069         struct drm_i915_private *dev_priv = dev->dev_private;
1070         int ret;
1071
1072         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1073                                    dev_priv->mm.interruptible);
1074         if (ret)
1075                 return ret;
1076
1077         ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t));
1078         if (ret)
1079                 return ret;
1080
1081         /* Preallocate the olr before touching the ring */
1082         ret = logical_ring_alloc_request(ring, ringbuf->FIXME_lrc_ctx);
1083         if (ret)
1084                 return ret;
1085
1086         ringbuf->space -= num_dwords * sizeof(uint32_t);
1087         return 0;
1088 }
1089
1090 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1091                                                struct intel_context *ctx)
1092 {
1093         int ret, i;
1094         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1095         struct drm_device *dev = ring->dev;
1096         struct drm_i915_private *dev_priv = dev->dev_private;
1097         struct i915_workarounds *w = &dev_priv->workarounds;
1098
1099         if (WARN_ON_ONCE(w->count == 0))
1100                 return 0;
1101
1102         ring->gpu_caches_dirty = true;
1103         ret = logical_ring_flush_all_caches(ringbuf);
1104         if (ret)
1105                 return ret;
1106
1107         ret = intel_logical_ring_begin(ringbuf, w->count * 2 + 2);
1108         if (ret)
1109                 return ret;
1110
1111         intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1112         for (i = 0; i < w->count; i++) {
1113                 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1114                 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1115         }
1116         intel_logical_ring_emit(ringbuf, MI_NOOP);
1117
1118         intel_logical_ring_advance(ringbuf);
1119
1120         ring->gpu_caches_dirty = true;
1121         ret = logical_ring_flush_all_caches(ringbuf);
1122         if (ret)
1123                 return ret;
1124
1125         return 0;
1126 }
1127
1128 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1129 {
1130         struct drm_device *dev = ring->dev;
1131         struct drm_i915_private *dev_priv = dev->dev_private;
1132
1133         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1134         I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1135
1136         I915_WRITE(RING_MODE_GEN7(ring),
1137                    _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1138                    _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1139         POSTING_READ(RING_MODE_GEN7(ring));
1140         DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1141
1142         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1143
1144         return 0;
1145 }
1146
1147 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1148 {
1149         struct drm_device *dev = ring->dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         int ret;
1152
1153         ret = gen8_init_common_ring(ring);
1154         if (ret)
1155                 return ret;
1156
1157         /* We need to disable the AsyncFlip performance optimisations in order
1158          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1159          * programmed to '1' on all products.
1160          *
1161          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1162          */
1163         I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1164
1165         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1166
1167         return init_workarounds_ring(ring);
1168 }
1169
1170 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1171                               u64 offset, unsigned flags)
1172 {
1173         bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1174         int ret;
1175
1176         ret = intel_logical_ring_begin(ringbuf, 4);
1177         if (ret)
1178                 return ret;
1179
1180         /* FIXME(BDW): Address space and security selectors. */
1181         intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1182         intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1183         intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1184         intel_logical_ring_emit(ringbuf, MI_NOOP);
1185         intel_logical_ring_advance(ringbuf);
1186
1187         return 0;
1188 }
1189
1190 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1191 {
1192         struct drm_device *dev = ring->dev;
1193         struct drm_i915_private *dev_priv = dev->dev_private;
1194         unsigned long flags;
1195
1196         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1197                 return false;
1198
1199         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1200         if (ring->irq_refcount++ == 0) {
1201                 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1202                 POSTING_READ(RING_IMR(ring->mmio_base));
1203         }
1204         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1205
1206         return true;
1207 }
1208
1209 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1210 {
1211         struct drm_device *dev = ring->dev;
1212         struct drm_i915_private *dev_priv = dev->dev_private;
1213         unsigned long flags;
1214
1215         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1216         if (--ring->irq_refcount == 0) {
1217                 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1218                 POSTING_READ(RING_IMR(ring->mmio_base));
1219         }
1220         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1221 }
1222
1223 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1224                            u32 invalidate_domains,
1225                            u32 unused)
1226 {
1227         struct intel_engine_cs *ring = ringbuf->ring;
1228         struct drm_device *dev = ring->dev;
1229         struct drm_i915_private *dev_priv = dev->dev_private;
1230         uint32_t cmd;
1231         int ret;
1232
1233         ret = intel_logical_ring_begin(ringbuf, 4);
1234         if (ret)
1235                 return ret;
1236
1237         cmd = MI_FLUSH_DW + 1;
1238
1239         if (ring == &dev_priv->ring[VCS]) {
1240                 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
1241                         cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1242                                 MI_FLUSH_DW_STORE_INDEX |
1243                                 MI_FLUSH_DW_OP_STOREDW;
1244         } else {
1245                 if (invalidate_domains & I915_GEM_DOMAIN_RENDER)
1246                         cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1247                                 MI_FLUSH_DW_OP_STOREDW;
1248         }
1249
1250         intel_logical_ring_emit(ringbuf, cmd);
1251         intel_logical_ring_emit(ringbuf,
1252                                 I915_GEM_HWS_SCRATCH_ADDR |
1253                                 MI_FLUSH_DW_USE_GTT);
1254         intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1255         intel_logical_ring_emit(ringbuf, 0); /* value */
1256         intel_logical_ring_advance(ringbuf);
1257
1258         return 0;
1259 }
1260
1261 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1262                                   u32 invalidate_domains,
1263                                   u32 flush_domains)
1264 {
1265         struct intel_engine_cs *ring = ringbuf->ring;
1266         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1267         u32 flags = 0;
1268         int ret;
1269
1270         flags |= PIPE_CONTROL_CS_STALL;
1271
1272         if (flush_domains) {
1273                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1274                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1275         }
1276
1277         if (invalidate_domains) {
1278                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1279                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1280                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1281                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1282                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1283                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1284                 flags |= PIPE_CONTROL_QW_WRITE;
1285                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1286         }
1287
1288         ret = intel_logical_ring_begin(ringbuf, 6);
1289         if (ret)
1290                 return ret;
1291
1292         intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1293         intel_logical_ring_emit(ringbuf, flags);
1294         intel_logical_ring_emit(ringbuf, scratch_addr);
1295         intel_logical_ring_emit(ringbuf, 0);
1296         intel_logical_ring_emit(ringbuf, 0);
1297         intel_logical_ring_emit(ringbuf, 0);
1298         intel_logical_ring_advance(ringbuf);
1299
1300         return 0;
1301 }
1302
1303 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1304 {
1305         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1306 }
1307
1308 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1309 {
1310         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1311 }
1312
1313 static int gen8_emit_request(struct intel_ringbuffer *ringbuf)
1314 {
1315         struct intel_engine_cs *ring = ringbuf->ring;
1316         u32 cmd;
1317         int ret;
1318
1319         ret = intel_logical_ring_begin(ringbuf, 6);
1320         if (ret)
1321                 return ret;
1322
1323         cmd = MI_STORE_DWORD_IMM_GEN4;
1324         cmd |= MI_GLOBAL_GTT;
1325
1326         intel_logical_ring_emit(ringbuf, cmd);
1327         intel_logical_ring_emit(ringbuf,
1328                                 (ring->status_page.gfx_addr +
1329                                 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1330         intel_logical_ring_emit(ringbuf, 0);
1331         intel_logical_ring_emit(ringbuf,
1332                 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1333         intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1334         intel_logical_ring_emit(ringbuf, MI_NOOP);
1335         intel_logical_ring_advance_and_submit(ringbuf);
1336
1337         return 0;
1338 }
1339
1340 static int gen8_init_rcs_context(struct intel_engine_cs *ring,
1341                        struct intel_context *ctx)
1342 {
1343         int ret;
1344
1345         ret = intel_logical_ring_workarounds_emit(ring, ctx);
1346         if (ret)
1347                 return ret;
1348
1349         return intel_lr_context_render_state_init(ring, ctx);
1350 }
1351
1352 /**
1353  * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1354  *
1355  * @ring: Engine Command Streamer.
1356  *
1357  */
1358 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1359 {
1360         struct drm_i915_private *dev_priv;
1361
1362         if (!intel_ring_initialized(ring))
1363                 return;
1364
1365         dev_priv = ring->dev->dev_private;
1366
1367         intel_logical_ring_stop(ring);
1368         WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1369         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1370
1371         if (ring->cleanup)
1372                 ring->cleanup(ring);
1373
1374         i915_cmd_parser_fini_ring(ring);
1375
1376         if (ring->status_page.obj) {
1377                 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1378                 ring->status_page.obj = NULL;
1379         }
1380 }
1381
1382 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1383 {
1384         int ret;
1385
1386         /* Intentionally left blank. */
1387         ring->buffer = NULL;
1388
1389         ring->dev = dev;
1390         INIT_LIST_HEAD(&ring->active_list);
1391         INIT_LIST_HEAD(&ring->request_list);
1392         init_waitqueue_head(&ring->irq_queue);
1393
1394         INIT_LIST_HEAD(&ring->execlist_queue);
1395         INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1396         spin_lock_init(&ring->execlist_lock);
1397         ring->next_context_status_buffer = 0;
1398
1399         ret = i915_cmd_parser_init_ring(ring);
1400         if (ret)
1401                 return ret;
1402
1403         ret = intel_lr_context_deferred_create(ring->default_context, ring);
1404
1405         return ret;
1406 }
1407
1408 static int logical_render_ring_init(struct drm_device *dev)
1409 {
1410         struct drm_i915_private *dev_priv = dev->dev_private;
1411         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1412         int ret;
1413
1414         ring->name = "render ring";
1415         ring->id = RCS;
1416         ring->mmio_base = RENDER_RING_BASE;
1417         ring->irq_enable_mask =
1418                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1419         ring->irq_keep_mask =
1420                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1421         if (HAS_L3_DPF(dev))
1422                 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1423
1424         ring->init_hw = gen8_init_render_ring;
1425         ring->init_context = gen8_init_rcs_context;
1426         ring->cleanup = intel_fini_pipe_control;
1427         ring->get_seqno = gen8_get_seqno;
1428         ring->set_seqno = gen8_set_seqno;
1429         ring->emit_request = gen8_emit_request;
1430         ring->emit_flush = gen8_emit_flush_render;
1431         ring->irq_get = gen8_logical_ring_get_irq;
1432         ring->irq_put = gen8_logical_ring_put_irq;
1433         ring->emit_bb_start = gen8_emit_bb_start;
1434
1435         ring->dev = dev;
1436         ret = logical_ring_init(dev, ring);
1437         if (ret)
1438                 return ret;
1439
1440         return intel_init_pipe_control(ring);
1441 }
1442
1443 static int logical_bsd_ring_init(struct drm_device *dev)
1444 {
1445         struct drm_i915_private *dev_priv = dev->dev_private;
1446         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1447
1448         ring->name = "bsd ring";
1449         ring->id = VCS;
1450         ring->mmio_base = GEN6_BSD_RING_BASE;
1451         ring->irq_enable_mask =
1452                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1453         ring->irq_keep_mask =
1454                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1455
1456         ring->init_hw = gen8_init_common_ring;
1457         ring->get_seqno = gen8_get_seqno;
1458         ring->set_seqno = gen8_set_seqno;
1459         ring->emit_request = gen8_emit_request;
1460         ring->emit_flush = gen8_emit_flush;
1461         ring->irq_get = gen8_logical_ring_get_irq;
1462         ring->irq_put = gen8_logical_ring_put_irq;
1463         ring->emit_bb_start = gen8_emit_bb_start;
1464
1465         return logical_ring_init(dev, ring);
1466 }
1467
1468 static int logical_bsd2_ring_init(struct drm_device *dev)
1469 {
1470         struct drm_i915_private *dev_priv = dev->dev_private;
1471         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1472
1473         ring->name = "bds2 ring";
1474         ring->id = VCS2;
1475         ring->mmio_base = GEN8_BSD2_RING_BASE;
1476         ring->irq_enable_mask =
1477                 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1478         ring->irq_keep_mask =
1479                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1480
1481         ring->init_hw = gen8_init_common_ring;
1482         ring->get_seqno = gen8_get_seqno;
1483         ring->set_seqno = gen8_set_seqno;
1484         ring->emit_request = gen8_emit_request;
1485         ring->emit_flush = gen8_emit_flush;
1486         ring->irq_get = gen8_logical_ring_get_irq;
1487         ring->irq_put = gen8_logical_ring_put_irq;
1488         ring->emit_bb_start = gen8_emit_bb_start;
1489
1490         return logical_ring_init(dev, ring);
1491 }
1492
1493 static int logical_blt_ring_init(struct drm_device *dev)
1494 {
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1497
1498         ring->name = "blitter ring";
1499         ring->id = BCS;
1500         ring->mmio_base = BLT_RING_BASE;
1501         ring->irq_enable_mask =
1502                 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1503         ring->irq_keep_mask =
1504                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1505
1506         ring->init_hw = gen8_init_common_ring;
1507         ring->get_seqno = gen8_get_seqno;
1508         ring->set_seqno = gen8_set_seqno;
1509         ring->emit_request = gen8_emit_request;
1510         ring->emit_flush = gen8_emit_flush;
1511         ring->irq_get = gen8_logical_ring_get_irq;
1512         ring->irq_put = gen8_logical_ring_put_irq;
1513         ring->emit_bb_start = gen8_emit_bb_start;
1514
1515         return logical_ring_init(dev, ring);
1516 }
1517
1518 static int logical_vebox_ring_init(struct drm_device *dev)
1519 {
1520         struct drm_i915_private *dev_priv = dev->dev_private;
1521         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1522
1523         ring->name = "video enhancement ring";
1524         ring->id = VECS;
1525         ring->mmio_base = VEBOX_RING_BASE;
1526         ring->irq_enable_mask =
1527                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1528         ring->irq_keep_mask =
1529                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1530
1531         ring->init_hw = gen8_init_common_ring;
1532         ring->get_seqno = gen8_get_seqno;
1533         ring->set_seqno = gen8_set_seqno;
1534         ring->emit_request = gen8_emit_request;
1535         ring->emit_flush = gen8_emit_flush;
1536         ring->irq_get = gen8_logical_ring_get_irq;
1537         ring->irq_put = gen8_logical_ring_put_irq;
1538         ring->emit_bb_start = gen8_emit_bb_start;
1539
1540         return logical_ring_init(dev, ring);
1541 }
1542
1543 /**
1544  * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1545  * @dev: DRM device.
1546  *
1547  * This function inits the engines for an Execlists submission style (the equivalent in the
1548  * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1549  * those engines that are present in the hardware.
1550  *
1551  * Return: non-zero if the initialization failed.
1552  */
1553 int intel_logical_rings_init(struct drm_device *dev)
1554 {
1555         struct drm_i915_private *dev_priv = dev->dev_private;
1556         int ret;
1557
1558         ret = logical_render_ring_init(dev);
1559         if (ret)
1560                 return ret;
1561
1562         if (HAS_BSD(dev)) {
1563                 ret = logical_bsd_ring_init(dev);
1564                 if (ret)
1565                         goto cleanup_render_ring;
1566         }
1567
1568         if (HAS_BLT(dev)) {
1569                 ret = logical_blt_ring_init(dev);
1570                 if (ret)
1571                         goto cleanup_bsd_ring;
1572         }
1573
1574         if (HAS_VEBOX(dev)) {
1575                 ret = logical_vebox_ring_init(dev);
1576                 if (ret)
1577                         goto cleanup_blt_ring;
1578         }
1579
1580         if (HAS_BSD2(dev)) {
1581                 ret = logical_bsd2_ring_init(dev);
1582                 if (ret)
1583                         goto cleanup_vebox_ring;
1584         }
1585
1586         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1587         if (ret)
1588                 goto cleanup_bsd2_ring;
1589
1590         return 0;
1591
1592 cleanup_bsd2_ring:
1593         intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1594 cleanup_vebox_ring:
1595         intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1596 cleanup_blt_ring:
1597         intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1598 cleanup_bsd_ring:
1599         intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1600 cleanup_render_ring:
1601         intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1602
1603         return ret;
1604 }
1605
1606 int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1607                                        struct intel_context *ctx)
1608 {
1609         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1610         struct render_state so;
1611         struct drm_i915_file_private *file_priv = ctx->file_priv;
1612         struct drm_file *file = file_priv ? file_priv->file : NULL;
1613         int ret;
1614
1615         ret = i915_gem_render_state_prepare(ring, &so);
1616         if (ret)
1617                 return ret;
1618
1619         if (so.rodata == NULL)
1620                 return 0;
1621
1622         ret = ring->emit_bb_start(ringbuf,
1623                         so.ggtt_offset,
1624                         I915_DISPATCH_SECURE);
1625         if (ret)
1626                 goto out;
1627
1628         i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1629
1630         ret = __i915_add_request(ring, file, so.obj);
1631         /* intel_logical_ring_add_request moves object to inactive if it
1632          * fails */
1633 out:
1634         i915_gem_render_state_fini(&so);
1635         return ret;
1636 }
1637
1638 static int
1639 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1640                     struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1641 {
1642         struct drm_device *dev = ring->dev;
1643         struct drm_i915_private *dev_priv = dev->dev_private;
1644         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1645         struct page *page;
1646         uint32_t *reg_state;
1647         int ret;
1648
1649         if (!ppgtt)
1650                 ppgtt = dev_priv->mm.aliasing_ppgtt;
1651
1652         ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1653         if (ret) {
1654                 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1655                 return ret;
1656         }
1657
1658         ret = i915_gem_object_get_pages(ctx_obj);
1659         if (ret) {
1660                 DRM_DEBUG_DRIVER("Could not get object pages\n");
1661                 return ret;
1662         }
1663
1664         i915_gem_object_pin_pages(ctx_obj);
1665
1666         /* The second page of the context object contains some fields which must
1667          * be set up prior to the first execution. */
1668         page = i915_gem_object_get_page(ctx_obj, 1);
1669         reg_state = kmap_atomic(page);
1670
1671         /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1672          * commands followed by (reg, value) pairs. The values we are setting here are
1673          * only for the first context restore: on a subsequent save, the GPU will
1674          * recreate this batchbuffer with new values (including all the missing
1675          * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1676         if (ring->id == RCS)
1677                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1678         else
1679                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1680         reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1681         reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1682         reg_state[CTX_CONTEXT_CONTROL+1] =
1683                         _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
1684         reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1685         reg_state[CTX_RING_HEAD+1] = 0;
1686         reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1687         reg_state[CTX_RING_TAIL+1] = 0;
1688         reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1689         /* Ring buffer start address is not known until the buffer is pinned.
1690          * It is written to the context image in execlists_update_context()
1691          */
1692         reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1693         reg_state[CTX_RING_BUFFER_CONTROL+1] =
1694                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1695         reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1696         reg_state[CTX_BB_HEAD_U+1] = 0;
1697         reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1698         reg_state[CTX_BB_HEAD_L+1] = 0;
1699         reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1700         reg_state[CTX_BB_STATE+1] = (1<<5);
1701         reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1702         reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1703         reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1704         reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1705         reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1706         reg_state[CTX_SECOND_BB_STATE+1] = 0;
1707         if (ring->id == RCS) {
1708                 /* TODO: according to BSpec, the register state context
1709                  * for CHV does not have these. OTOH, these registers do
1710                  * exist in CHV. I'm waiting for a clarification */
1711                 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1712                 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1713                 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1714                 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1715                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1716                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1717         }
1718         reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1719         reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1720         reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1721         reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1722         reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1723         reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1724         reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1725         reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1726         reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1727         reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1728         reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1729         reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1730         reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
1731         reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
1732         reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
1733         reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
1734         reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
1735         reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
1736         reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
1737         reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
1738         if (ring->id == RCS) {
1739                 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1740                 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
1741                 reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
1742         }
1743
1744         kunmap_atomic(reg_state);
1745
1746         ctx_obj->dirty = 1;
1747         set_page_dirty(page);
1748         i915_gem_object_unpin_pages(ctx_obj);
1749
1750         return 0;
1751 }
1752
1753 /**
1754  * intel_lr_context_free() - free the LRC specific bits of a context
1755  * @ctx: the LR context to free.
1756  *
1757  * The real context freeing is done in i915_gem_context_free: this only
1758  * takes care of the bits that are LRC related: the per-engine backing
1759  * objects and the logical ringbuffer.
1760  */
1761 void intel_lr_context_free(struct intel_context *ctx)
1762 {
1763         int i;
1764
1765         for (i = 0; i < I915_NUM_RINGS; i++) {
1766                 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1767
1768                 if (ctx_obj) {
1769                         struct intel_ringbuffer *ringbuf =
1770                                         ctx->engine[i].ringbuf;
1771                         struct intel_engine_cs *ring = ringbuf->ring;
1772
1773                         if (ctx == ring->default_context) {
1774                                 intel_unpin_ringbuffer_obj(ringbuf);
1775                                 i915_gem_object_ggtt_unpin(ctx_obj);
1776                         }
1777                         intel_destroy_ringbuffer_obj(ringbuf);
1778                         kfree(ringbuf);
1779                         drm_gem_object_unreference(&ctx_obj->base);
1780                 }
1781         }
1782 }
1783
1784 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1785 {
1786         int ret = 0;
1787
1788         WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1789
1790         switch (ring->id) {
1791         case RCS:
1792                 if (INTEL_INFO(ring->dev)->gen >= 9)
1793                         ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1794                 else
1795                         ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1796                 break;
1797         case VCS:
1798         case BCS:
1799         case VECS:
1800         case VCS2:
1801                 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1802                 break;
1803         }
1804
1805         return ret;
1806 }
1807
1808 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1809                 struct drm_i915_gem_object *default_ctx_obj)
1810 {
1811         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1812
1813         /* The status page is offset 0 from the default context object
1814          * in LRC mode. */
1815         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1816         ring->status_page.page_addr =
1817                         kmap(sg_page(default_ctx_obj->pages->sgl));
1818         ring->status_page.obj = default_ctx_obj;
1819
1820         I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1821                         (u32)ring->status_page.gfx_addr);
1822         POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1823 }
1824
1825 /**
1826  * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1827  * @ctx: LR context to create.
1828  * @ring: engine to be used with the context.
1829  *
1830  * This function can be called more than once, with different engines, if we plan
1831  * to use the context with them. The context backing objects and the ringbuffers
1832  * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1833  * the creation is a deferred call: it's better to make sure first that we need to use
1834  * a given ring with the context.
1835  *
1836  * Return: non-zero on error.
1837  */
1838 int intel_lr_context_deferred_create(struct intel_context *ctx,
1839                                      struct intel_engine_cs *ring)
1840 {
1841         const bool is_global_default_ctx = (ctx == ring->default_context);
1842         struct drm_device *dev = ring->dev;
1843         struct drm_i915_gem_object *ctx_obj;
1844         uint32_t context_size;
1845         struct intel_ringbuffer *ringbuf;
1846         int ret;
1847
1848         WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1849         WARN_ON(ctx->engine[ring->id].state);
1850
1851         context_size = round_up(get_lr_context_size(ring), 4096);
1852
1853         ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1854         if (IS_ERR(ctx_obj)) {
1855                 ret = PTR_ERR(ctx_obj);
1856                 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1857                 return ret;
1858         }
1859
1860         if (is_global_default_ctx) {
1861                 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1862                 if (ret) {
1863                         DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1864                                         ret);
1865                         drm_gem_object_unreference(&ctx_obj->base);
1866                         return ret;
1867                 }
1868         }
1869
1870         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1871         if (!ringbuf) {
1872                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1873                                 ring->name);
1874                 ret = -ENOMEM;
1875                 goto error_unpin_ctx;
1876         }
1877
1878         ringbuf->ring = ring;
1879         ringbuf->FIXME_lrc_ctx = ctx;
1880
1881         ringbuf->size = 32 * PAGE_SIZE;
1882         ringbuf->effective_size = ringbuf->size;
1883         ringbuf->head = 0;
1884         ringbuf->tail = 0;
1885         ringbuf->last_retired_head = -1;
1886         intel_ring_update_space(ringbuf);
1887
1888         if (ringbuf->obj == NULL) {
1889                 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1890                 if (ret) {
1891                         DRM_DEBUG_DRIVER(
1892                                 "Failed to allocate ringbuffer obj %s: %d\n",
1893                                 ring->name, ret);
1894                         goto error_free_rbuf;
1895                 }
1896
1897                 if (is_global_default_ctx) {
1898                         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1899                         if (ret) {
1900                                 DRM_ERROR(
1901                                         "Failed to pin and map ringbuffer %s: %d\n",
1902                                         ring->name, ret);
1903                                 goto error_destroy_rbuf;
1904                         }
1905                 }
1906
1907         }
1908
1909         ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1910         if (ret) {
1911                 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1912                 goto error;
1913         }
1914
1915         ctx->engine[ring->id].ringbuf = ringbuf;
1916         ctx->engine[ring->id].state = ctx_obj;
1917
1918         if (ctx == ring->default_context)
1919                 lrc_setup_hardware_status_page(ring, ctx_obj);
1920         else if (ring->id == RCS && !ctx->rcs_initialized) {
1921                 if (ring->init_context) {
1922                         ret = ring->init_context(ring, ctx);
1923                         if (ret) {
1924                                 DRM_ERROR("ring init context: %d\n", ret);
1925                                 ctx->engine[ring->id].ringbuf = NULL;
1926                                 ctx->engine[ring->id].state = NULL;
1927                                 goto error;
1928                         }
1929                 }
1930
1931                 ctx->rcs_initialized = true;
1932         }
1933
1934         return 0;
1935
1936 error:
1937         if (is_global_default_ctx)
1938                 intel_unpin_ringbuffer_obj(ringbuf);
1939 error_destroy_rbuf:
1940         intel_destroy_ringbuffer_obj(ringbuf);
1941 error_free_rbuf:
1942         kfree(ringbuf);
1943 error_unpin_ctx:
1944         if (is_global_default_ctx)
1945                 i915_gem_object_ggtt_unpin(ctx_obj);
1946         drm_gem_object_unreference(&ctx_obj->base);
1947         return ret;
1948 }