drivers/gpu/drm/i915/intel_lrc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *    Michel Thierry <michel.thierry@intel.com>
  26  *    Thomas Daniel <thomas.daniel@intel.com>
  27  *    Oscar Mateo <oscar.mateo@intel.com>
  28  *
  29  */
  30
  31 /**
  32  * DOC: Logical Rings, Logical Ring Contexts and Execlists
  33  *
  34  * Motivation:
  35  * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
  36  * These expanded contexts enable a number of new abilities, especially
  37  * "Execlists" (also implemented in this file).
  38  *
  39  * One of the main differences with the legacy HW contexts is that logical
  40  * ring contexts incorporate many more things to the context's state, like
  41  * PDPs or ringbuffer control registers:
  42  *
  43  * The reason why PDPs are included in the context is straightforward: as
  44  * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
  45  * contained there mean you don't need to do a ppgtt->switch_mm yourself,
  46  * instead, the GPU will do it for you on the context switch.
  47  *
  48  * But, what about the ringbuffer control registers (head, tail, etc..)?
  49  * shouldn't we just need a set of those per engine command streamer? This is
  50  * where the name "Logical Rings" starts to make sense: by virtualizing the
  51  * rings, the engine cs shifts to a new "ring buffer" with every context
  52  * switch. When you want to submit a workload to the GPU you: A) choose your
  53  * context, B) find its appropriate virtualized ring, C) write commands to it
  54  * and then, finally, D) tell the GPU to switch to that context.
  55  *
  56  * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
  57  * to a contexts is via a context execution list, ergo "Execlists".
  58  *
  59  * LRC implementation:
  60  * Regarding the creation of contexts, we have:
  61  *
  62  * - One global default context.
  63  * - One local default context for each opened fd.
  64  * - One local extra context for each context create ioctl call.
  65  *
  66  * Now that ringbuffers belong per-context (and not per-engine, like before)
  67  * and that contexts are uniquely tied to a given engine (and not reusable,
  68  * like before) we need:
  69  *
  70  * - One ringbuffer per-engine inside each context.
  71  * - One backing object per-engine inside each context.
  72  *
  73  * The global default context starts its life with these new objects fully
  74  * allocated and populated. The local default context for each opened fd is
  75  * more complex, because we don't know at creation time which engine is going
  76  * to use them. To handle this, we have implemented a deferred creation of LR
  77  * contexts:
  78  *
  79  * The local context starts its life as a hollow or blank holder, that only
  80  * gets populated for a given engine once we receive an execbuffer. If later
  81  * on we receive another execbuffer ioctl for the same context but a different
  82  * engine, we allocate/populate a new ringbuffer and context backing object and
  83  * so on.
  84  *
  85  * Finally, regarding local contexts created using the ioctl call: as they are
  86  * only allowed with the render ring, we can allocate & populate them right
  87  * away (no need to defer anything, at least for now).
  88  *
  89  * Execlists implementation:
  90  * Execlists are the new method by which, on gen8+ hardware, workloads are
  91  * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
  92  * This method works as follows:
  93  *
  94  * When a request is committed, its commands (the BB start and any leading or
  95  * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
  96  * for the appropriate context. The tail pointer in the hardware context is not
  97  * updated at this time, but instead, kept by the driver in the ringbuffer
  98  * structure. A structure representing this request is added to a request queue
  99  * for the appropriate engine: this structure contains a copy of the context's
 100  * tail after the request was written to the ring buffer and a pointer to the
 101  * context itself.
 102  *
 103  * If the engine's request queue was empty before the request was added, the
 104  * queue is processed immediately. Otherwise the queue will be processed during
 105  * a context switch interrupt. In any case, elements on the queue will get sent
 106  * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 107  * globally unique 20-bits submission ID.
 108  *
 109  * When execution of a request completes, the GPU updates the context status
 110  * buffer with a context complete event and generates a context switch interrupt.
 111  * During the interrupt handling, the driver examines the events in the buffer:
 112  * for each context complete event, if the announced ID matches that on the head
 113  * of the request queue, then that request is retired and removed from the queue.
 114  *
 115  * After processing, if any requests were retired and the queue is not empty
 116  * then a new execution list can be submitted. The two requests at the front of
 117  * the queue are next to be submitted but since a context may not occur twice in
 118  * an execution list, if subsequent requests have the same ID as the first then
 119  * the two requests must be combined. This is done simply by discarding requests
 120  * at the head of the queue until either only one requests is left (in which case
 121  * we use a NULL second context) or the first two requests have unique IDs.
 122  *
 123  * By always executing the first two requests in the queue the driver ensures
 124  * that the GPU is kept as busy as possible. In the case where a single context
 125  * completes but a second context is still executing, the request for this second
 126  * context will be at the head of the queue when we remove the first one. This
 127  * request will then be resubmitted along with a new request for a different context,
 128  * which will cause the hardware to continue executing the second request and queue
 129  * the new request (the GPU detects the condition of a context getting preempted
 130  * with the same context and optimizes the context switch flow by not doing
 131  * preemption, but just sampling the new tail pointer).
 132  *
 133  */
 134
 135 #include <drm/drmP.h>
 136 #include <drm/i915_drm.h>
 137 #include "i915_drv.h"
 138
 139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
 140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
 141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
 142
 143 #define RING_EXECLIST_QFULL             (1 << 0x2)
 144 #define RING_EXECLIST1_VALID            (1 << 0x3)
 145 #define RING_EXECLIST0_VALID            (1 << 0x4)
 146 #define RING_EXECLIST_ACTIVE_STATUS     (3 << 0xE)
 147 #define RING_EXECLIST1_ACTIVE           (1 << 0x11)
 148 #define RING_EXECLIST0_ACTIVE           (1 << 0x12)
 149
 150 #define GEN8_CTX_STATUS_IDLE_ACTIVE     (1 << 0)
 151 #define GEN8_CTX_STATUS_PREEMPTED       (1 << 1)
 152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH  (1 << 2)
 153 #define GEN8_CTX_STATUS_ACTIVE_IDLE     (1 << 3)
 154 #define GEN8_CTX_STATUS_COMPLETE        (1 << 4)
 155 #define GEN8_CTX_STATUS_LITE_RESTORE    (1 << 15)
 156
 157 #define CTX_LRI_HEADER_0                0x01
 158 #define CTX_CONTEXT_CONTROL             0x02
 159 #define CTX_RING_HEAD                   0x04
 160 #define CTX_RING_TAIL                   0x06
 161 #define CTX_RING_BUFFER_START           0x08
 162 #define CTX_RING_BUFFER_CONTROL         0x0a
 163 #define CTX_BB_HEAD_U                   0x0c
 164 #define CTX_BB_HEAD_L                   0x0e
 165 #define CTX_BB_STATE                    0x10
 166 #define CTX_SECOND_BB_HEAD_U            0x12
 167 #define CTX_SECOND_BB_HEAD_L            0x14
 168 #define CTX_SECOND_BB_STATE             0x16
 169 #define CTX_BB_PER_CTX_PTR              0x18
 170 #define CTX_RCS_INDIRECT_CTX            0x1a
 171 #define CTX_RCS_INDIRECT_CTX_OFFSET     0x1c
 172 #define CTX_LRI_HEADER_1                0x21
 173 #define CTX_CTX_TIMESTAMP               0x22
 174 #define CTX_PDP3_UDW                    0x24
 175 #define CTX_PDP3_LDW                    0x26
 176 #define CTX_PDP2_UDW                    0x28
 177 #define CTX_PDP2_LDW                    0x2a
 178 #define CTX_PDP1_UDW                    0x2c
 179 #define CTX_PDP1_LDW                    0x2e
 180 #define CTX_PDP0_UDW                    0x30
 181 #define CTX_PDP0_LDW                    0x32
 182 #define CTX_LRI_HEADER_2                0x41
 183 #define CTX_R_PWR_CLK_STATE             0x42
 184 #define CTX_GPGPU_CSR_BASE_ADDRESS      0x44
 185
 186 #define GEN8_CTX_VALID (1<<0)
 187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
 188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
 189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
 190 #define GEN8_CTX_PRIVILEGE (1<<8)
 191 enum {
 192         ADVANCED_CONTEXT = 0,
 193         LEGACY_CONTEXT,
 194         ADVANCED_AD_CONTEXT,
 195         LEGACY_64B_CONTEXT
 196 };
 197 #define GEN8_CTX_MODE_SHIFT 3
 198 enum {
 199         FAULT_AND_HANG = 0,
 200         FAULT_AND_HALT, /* Debug only */
 201         FAULT_AND_STREAM,
 202         FAULT_AND_CONTINUE /* Unsupported */
 203 };
 204 #define GEN8_CTX_ID_SHIFT 32
 205
 206 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 207                 struct intel_context *ctx);
 208
 209 /**
 210  * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 211  * @dev: DRM device.
 212  * @enable_execlists: value of i915.enable_execlists module parameter.
 213  *
 214  * Only certain platforms support Execlists (the prerequisites being
 215  * support for Logical Ring Contexts and Aliasing PPGTT or better).
 216  *
 217  * Return: 1 if Execlists is supported and has to be enabled.
 218  */
 219 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
 220 {
 221         WARN_ON(i915.enable_ppgtt == -1);
 222
 223         if (INTEL_INFO(dev)->gen >= 9)
 224                 return 1;
 225
 226         if (enable_execlists == 0)
 227                 return 0;
 228
 229         if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
 230             i915.use_mmio_flip >= 0)
 231                 return 1;
 232
 233         return 0;
 234 }
 235
 236 /**
 237  * intel_execlists_ctx_id() - get the Execlists Context ID
 238  * @ctx_obj: Logical Ring Context backing object.
 239  *
 240  * Do not confuse with ctx->id! Unfortunately we have a name overload
 241  * here: the old context ID we pass to userspace as a handler so that
 242  * they can refer to a context, and the new context ID we pass to the
 243  * ELSP so that the GPU can inform us of the context status via
 244  * interrupts.
 245  *
 246  * Return: 20-bits globally unique context ID.
 247  */
 248 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
 249 {
 250         u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 251
 252         /* LRCA is required to be 4K aligned so the more significant 20 bits
 253          * are globally unique */
 254         return lrca >> 12;
 255 }
 256
 257 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
 258                                          struct drm_i915_gem_object *ctx_obj)
 259 {
 260         struct drm_device *dev = ring->dev;
 261         uint64_t desc;
 262         uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 263
 264         WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
 265
 266         desc = GEN8_CTX_VALID;
 267         desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
 268         desc |= GEN8_CTX_L3LLC_COHERENT;
 269         desc |= GEN8_CTX_PRIVILEGE;
 270         desc |= lrca;
 271         desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
 272
 273         /* TODO: WaDisableLiteRestore when we start using semaphore
 274          * signalling between Command Streamers */
 275         /* desc |= GEN8_CTX_FORCE_RESTORE; */
 276
 277         /* WaEnableForceRestoreInCtxtDescForVCS:skl */
 278         if (IS_GEN9(dev) &&
 279             INTEL_REVID(dev) <= SKL_REVID_B0 &&
 280             (ring->id == BCS || ring->id == VCS ||
 281             ring->id == VECS || ring->id == VCS2))
 282                 desc |= GEN8_CTX_FORCE_RESTORE;
 283
 284         return desc;
 285 }
 286
 287 static void execlists_elsp_write(struct intel_engine_cs *ring,
 288                                  struct drm_i915_gem_object *ctx_obj0,
 289                                  struct drm_i915_gem_object *ctx_obj1)
 290 {
 291         struct drm_device *dev = ring->dev;
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293         uint64_t temp = 0;
 294         uint32_t desc[4];
 295
 296         /* XXX: You must always write both descriptors in the order below. */
 297         if (ctx_obj1)
 298                 temp = execlists_ctx_descriptor(ring, ctx_obj1);
 299         else
 300                 temp = 0;
 301         desc[1] = (u32)(temp >> 32);
 302         desc[0] = (u32)temp;
 303
 304         temp = execlists_ctx_descriptor(ring, ctx_obj0);
 305         desc[3] = (u32)(temp >> 32);
 306         desc[2] = (u32)temp;
 307
 308         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 309         I915_WRITE(RING_ELSP(ring), desc[1]);
 310         I915_WRITE(RING_ELSP(ring), desc[0]);
 311         I915_WRITE(RING_ELSP(ring), desc[3]);
 312
 313         /* The context is automatically loaded after the following */
 314         I915_WRITE(RING_ELSP(ring), desc[2]);
 315
 316         /* ELSP is a wo register, so use another nearby reg for posting instead */
 317         POSTING_READ(RING_EXECLIST_STATUS(ring));
 318         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 319 }
 320
 321 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
 322                                     struct drm_i915_gem_object *ring_obj,
 323                                     u32 tail)
 324 {
 325         struct page *page;
 326         uint32_t *reg_state;
 327
 328         page = i915_gem_object_get_page(ctx_obj, 1);
 329         reg_state = kmap_atomic(page);
 330
 331         reg_state[CTX_RING_TAIL+1] = tail;
 332         reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
 333
 334         kunmap_atomic(reg_state);
 335
 336         return 0;
 337 }
 338
 339 static void execlists_submit_contexts(struct intel_engine_cs *ring,
 340                                       struct intel_context *to0, u32 tail0,
 341                                       struct intel_context *to1, u32 tail1)
 342 {
 343         struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
 344         struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
 345         struct drm_i915_gem_object *ctx_obj1 = NULL;
 346         struct intel_ringbuffer *ringbuf1 = NULL;
 347
 348         BUG_ON(!ctx_obj0);
 349         WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
 350         WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
 351
 352         execlists_update_context(ctx_obj0, ringbuf0->obj, tail0);
 353
 354         if (to1) {
 355                 ringbuf1 = to1->engine[ring->id].ringbuf;
 356                 ctx_obj1 = to1->engine[ring->id].state;
 357                 BUG_ON(!ctx_obj1);
 358                 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
 359                 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
 360
 361                 execlists_update_context(ctx_obj1, ringbuf1->obj, tail1);
 362         }
 363
 364         execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
 365 }
 366
 367 static void execlists_context_unqueue(struct intel_engine_cs *ring)
 368 {
 369         struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
 370         struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
 371
 372         assert_spin_locked(&ring->execlist_lock);
 373
 374         if (list_empty(&ring->execlist_queue))
 375                 return;
 376
 377         /* Try to read in pairs */
 378         list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
 379                                  execlist_link) {
 380                 if (!req0) {
 381                         req0 = cursor;
 382                 } else if (req0->ctx == cursor->ctx) {
 383                         /* Same ctx: ignore first request, as second request
 384                          * will update tail past first request's workload */
 385                         cursor->elsp_submitted = req0->elsp_submitted;
 386                         list_del(&req0->execlist_link);
 387                         list_add_tail(&req0->execlist_link,
 388                                 &ring->execlist_retired_req_list);
 389                         req0 = cursor;
 390                 } else {
 391                         req1 = cursor;
 392                         break;
 393                 }
 394         }
 395
 396         WARN_ON(req1 && req1->elsp_submitted);
 397
 398         execlists_submit_contexts(ring, req0->ctx, req0->tail,
 399                                   req1 ? req1->ctx : NULL,
 400                                   req1 ? req1->tail : 0);
 401
 402         req0->elsp_submitted++;
 403         if (req1)
 404                 req1->elsp_submitted++;
 405 }
 406
 407 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
 408                                            u32 request_id)
 409 {
 410         struct drm_i915_gem_request *head_req;
 411
 412         assert_spin_locked(&ring->execlist_lock);
 413
 414         head_req = list_first_entry_or_null(&ring->execlist_queue,
 415                                             struct drm_i915_gem_request,
 416                                             execlist_link);
 417
 418         if (head_req != NULL) {
 419                 struct drm_i915_gem_object *ctx_obj =
 420                                 head_req->ctx->engine[ring->id].state;
 421                 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
 422                         WARN(head_req->elsp_submitted == 0,
 423                              "Never submitted head request\n");
 424
 425                         if (--head_req->elsp_submitted <= 0) {
 426                                 list_del(&head_req->execlist_link);
 427                                 list_add_tail(&head_req->execlist_link,
 428                                         &ring->execlist_retired_req_list);
 429                                 return true;
 430                         }
 431                 }
 432         }
 433
 434         return false;
 435 }
 436
 437 /**
 438  * intel_lrc_irq_handler() - handle Context Switch interrupts
 439  * @ring: Engine Command Streamer to handle.
 440  *
 441  * Check the unread Context Status Buffers and manage the submission of new
 442  * contexts to the ELSP accordingly.
 443  */
 444 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
 445 {
 446         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 447         u32 status_pointer;
 448         u8 read_pointer;
 449         u8 write_pointer;
 450         u32 status;
 451         u32 status_id;
 452         u32 submit_contexts = 0;
 453
 454         status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
 455
 456         read_pointer = ring->next_context_status_buffer;
 457         write_pointer = status_pointer & 0x07;
 458         if (read_pointer > write_pointer)
 459                 write_pointer += 6;
 460
 461         spin_lock(&ring->execlist_lock);
 462
 463         while (read_pointer < write_pointer) {
 464                 read_pointer++;
 465                 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 466                                 (read_pointer % 6) * 8);
 467                 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 468                                 (read_pointer % 6) * 8 + 4);
 469
 470                 if (status & GEN8_CTX_STATUS_PREEMPTED) {
 471                         if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
 472                                 if (execlists_check_remove_request(ring, status_id))
 473                                         WARN(1, "Lite Restored request removed from queue\n");
 474                         } else
 475                                 WARN(1, "Preemption without Lite Restore\n");
 476                 }
 477
 478                  if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
 479                      (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
 480                         if (execlists_check_remove_request(ring, status_id))
 481                                 submit_contexts++;
 482                 }
 483         }
 484
 485         if (submit_contexts != 0)
 486                 execlists_context_unqueue(ring);
 487
 488         spin_unlock(&ring->execlist_lock);
 489
 490         WARN(submit_contexts > 2, "More than two context complete events?\n");
 491         ring->next_context_status_buffer = write_pointer % 6;
 492
 493         I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
 494                    ((u32)ring->next_context_status_buffer & 0x07) << 8);
 495 }
 496
 497 static int execlists_context_queue(struct intel_engine_cs *ring,
 498                                    struct intel_context *to,
 499                                    u32 tail,
 500                                    struct drm_i915_gem_request *request)
 501 {
 502         struct drm_i915_gem_request *cursor;
 503         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 504         unsigned long flags;
 505         int num_elements = 0;
 506
 507         if (to != ring->default_context)
 508                 intel_lr_context_pin(ring, to);
 509
 510         if (!request) {
 511                 /*
 512                  * If there isn't a request associated with this submission,
 513                  * create one as a temporary holder.
 514                  */
 515                 WARN(1, "execlist context submission without request");
 516                 request = kzalloc(sizeof(*request), GFP_KERNEL);
 517                 if (request == NULL)
 518                         return -ENOMEM;
 519                 request->ring = ring;
 520                 request->ctx = to;
 521         } else {
 522                 WARN_ON(to != request->ctx);
 523         }
 524         request->tail = tail;
 525         i915_gem_request_reference(request);
 526         i915_gem_context_reference(request->ctx);
 527
 528         intel_runtime_pm_get(dev_priv);
 529
 530         spin_lock_irqsave(&ring->execlist_lock, flags);
 531
 532         list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
 533                 if (++num_elements > 2)
 534                         break;
 535
 536         if (num_elements > 2) {
 537                 struct drm_i915_gem_request *tail_req;
 538
 539                 tail_req = list_last_entry(&ring->execlist_queue,
 540                                            struct drm_i915_gem_request,
 541                                            execlist_link);
 542
 543                 if (to == tail_req->ctx) {
 544                         WARN(tail_req->elsp_submitted != 0,
 545                                 "More than 2 already-submitted reqs queued\n");
 546                         list_del(&tail_req->execlist_link);
 547                         list_add_tail(&tail_req->execlist_link,
 548                                 &ring->execlist_retired_req_list);
 549                 }
 550         }
 551
 552         list_add_tail(&request->execlist_link, &ring->execlist_queue);
 553         if (num_elements == 0)
 554                 execlists_context_unqueue(ring);
 555
 556         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 557
 558         return 0;
 559 }
 560
 561 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
 562                                               struct intel_context *ctx)
 563 {
 564         struct intel_engine_cs *ring = ringbuf->ring;
 565         uint32_t flush_domains;
 566         int ret;
 567
 568         flush_domains = 0;
 569         if (ring->gpu_caches_dirty)
 570                 flush_domains = I915_GEM_GPU_DOMAINS;
 571
 572         ret = ring->emit_flush(ringbuf, ctx,
 573                                I915_GEM_GPU_DOMAINS, flush_domains);
 574         if (ret)
 575                 return ret;
 576
 577         ring->gpu_caches_dirty = false;
 578         return 0;
 579 }
 580
 581 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
 582                                  struct intel_context *ctx,
 583                                  struct list_head *vmas)
 584 {
 585         struct intel_engine_cs *ring = ringbuf->ring;
 586         struct i915_vma *vma;
 587         uint32_t flush_domains = 0;
 588         bool flush_chipset = false;
 589         int ret;
 590
 591         list_for_each_entry(vma, vmas, exec_list) {
 592                 struct drm_i915_gem_object *obj = vma->obj;
 593
 594                 ret = i915_gem_object_sync(obj, ring);
 595                 if (ret)
 596                         return ret;
 597
 598                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
 599                         flush_chipset |= i915_gem_clflush_object(obj, false);
 600
 601                 flush_domains |= obj->base.write_domain;
 602         }
 603
 604         if (flush_domains & I915_GEM_DOMAIN_GTT)
 605                 wmb();
 606
 607         /* Unconditionally invalidate gpu caches and ensure that we do flush
 608          * any residual writes from the previous batch.
 609          */
 610         return logical_ring_invalidate_all_caches(ringbuf, ctx);
 611 }
 612
 613 /**
 614  * execlists_submission() - submit a batchbuffer for execution, Execlists style
 615  * @dev: DRM device.
 616  * @file: DRM file.
 617  * @ring: Engine Command Streamer to submit to.
 618  * @ctx: Context to employ for this submission.
 619  * @args: execbuffer call arguments.
 620  * @vmas: list of vmas.
 621  * @batch_obj: the batchbuffer to submit.
 622  * @exec_start: batchbuffer start virtual address pointer.
 623  * @dispatch_flags: translated execbuffer call flags.
 624  *
 625  * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 626  * away the submission details of the execbuffer ioctl call.
 627  *
 628  * Return: non-zero if the submission fails.
 629  */
 630 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
 631                                struct intel_engine_cs *ring,
 632                                struct intel_context *ctx,
 633                                struct drm_i915_gem_execbuffer2 *args,
 634                                struct list_head *vmas,
 635                                struct drm_i915_gem_object *batch_obj,
 636                                u64 exec_start, u32 dispatch_flags)
 637 {
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 640         int instp_mode;
 641         u32 instp_mask;
 642         int ret;
 643
 644         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
 645         instp_mask = I915_EXEC_CONSTANTS_MASK;
 646         switch (instp_mode) {
 647         case I915_EXEC_CONSTANTS_REL_GENERAL:
 648         case I915_EXEC_CONSTANTS_ABSOLUTE:
 649         case I915_EXEC_CONSTANTS_REL_SURFACE:
 650                 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
 651                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
 652                         return -EINVAL;
 653                 }
 654
 655                 if (instp_mode != dev_priv->relative_constants_mode) {
 656                         if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
 657                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
 658                                 return -EINVAL;
 659                         }
 660
 661                         /* The HW changed the meaning on this bit on gen6 */
 662                         instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
 663                 }
 664                 break;
 665         default:
 666                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
 667                 return -EINVAL;
 668         }
 669
 670         if (args->num_cliprects != 0) {
 671                 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
 672                 return -EINVAL;
 673         } else {
 674                 if (args->DR4 == 0xffffffff) {
 675                         DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
 676                         args->DR4 = 0;
 677                 }
 678
 679                 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
 680                         DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
 681                         return -EINVAL;
 682                 }
 683         }
 684
 685         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
 686                 DRM_DEBUG("sol reset is gen7 only\n");
 687                 return -EINVAL;
 688         }
 689
 690         ret = execlists_move_to_gpu(ringbuf, ctx, vmas);
 691         if (ret)
 692                 return ret;
 693
 694         if (ring == &dev_priv->ring[RCS] &&
 695             instp_mode != dev_priv->relative_constants_mode) {
 696                 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
 697                 if (ret)
 698                         return ret;
 699
 700                 intel_logical_ring_emit(ringbuf, MI_NOOP);
 701                 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
 702                 intel_logical_ring_emit(ringbuf, INSTPM);
 703                 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
 704                 intel_logical_ring_advance(ringbuf);
 705
 706                 dev_priv->relative_constants_mode = instp_mode;
 707         }
 708
 709         ret = ring->emit_bb_start(ringbuf, ctx, exec_start, dispatch_flags);
 710         if (ret)
 711                 return ret;
 712
 713         trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags);
 714
 715         i915_gem_execbuffer_move_to_active(vmas, ring);
 716         i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
 717
 718         return 0;
 719 }
 720
 721 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
 722 {
 723         struct drm_i915_gem_request *req, *tmp;
 724         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 725         unsigned long flags;
 726         struct list_head retired_list;
 727
 728         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 729         if (list_empty(&ring->execlist_retired_req_list))
 730                 return;
 731
 732         INIT_LIST_HEAD(&retired_list);
 733         spin_lock_irqsave(&ring->execlist_lock, flags);
 734         list_replace_init(&ring->execlist_retired_req_list, &retired_list);
 735         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 736
 737         list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
 738                 struct intel_context *ctx = req->ctx;
 739                 struct drm_i915_gem_object *ctx_obj =
 740                                 ctx->engine[ring->id].state;
 741
 742                 if (ctx_obj && (ctx != ring->default_context))
 743                         intel_lr_context_unpin(ring, ctx);
 744                 intel_runtime_pm_put(dev_priv);
 745                 i915_gem_context_unreference(ctx);
 746                 list_del(&req->execlist_link);
 747                 i915_gem_request_unreference(req);
 748         }
 749 }
 750
 751 void intel_logical_ring_stop(struct intel_engine_cs *ring)
 752 {
 753         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 754         int ret;
 755
 756         if (!intel_ring_initialized(ring))
 757                 return;
 758
 759         ret = intel_ring_idle(ring);
 760         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
 761                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 762                           ring->name, ret);
 763
 764         /* TODO: Is this correct with Execlists enabled? */
 765         I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 766         if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 767                 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 768                 return;
 769         }
 770         I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 771 }
 772
 773 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
 774                                   struct intel_context *ctx)
 775 {
 776         struct intel_engine_cs *ring = ringbuf->ring;
 777         int ret;
 778
 779         if (!ring->gpu_caches_dirty)
 780                 return 0;
 781
 782         ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS);
 783         if (ret)
 784                 return ret;
 785
 786         ring->gpu_caches_dirty = false;
 787         return 0;
 788 }
 789
 790 /*
 791  * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
 792  * @ringbuf: Logical Ringbuffer to advance.
 793  *
 794  * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 795  * really happens during submission is that the context and current tail will be placed
 796  * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 797  * point, the tail *inside* the context is updated and the ELSP written to.
 798  */
 799 static void
 800 intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
 801                                       struct intel_context *ctx,
 802                                       struct drm_i915_gem_request *request)
 803 {
 804         struct intel_engine_cs *ring = ringbuf->ring;
 805
 806         intel_logical_ring_advance(ringbuf);
 807
 808         if (intel_ring_stopped(ring))
 809                 return;
 810
 811         execlists_context_queue(ring, ctx, ringbuf->tail, request);
 812 }
 813
 814 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 815                 struct intel_context *ctx)
 816 {
 817         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 818         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 819         int ret = 0;
 820
 821         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 822         if (ctx->engine[ring->id].pin_count++ == 0) {
 823                 ret = i915_gem_obj_ggtt_pin(ctx_obj,
 824                                 GEN8_LR_CONTEXT_ALIGN, 0);
 825                 if (ret)
 826                         goto reset_pin_count;
 827
 828                 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
 829                 if (ret)
 830                         goto unpin_ctx_obj;
 831         }
 832
 833         return ret;
 834
 835 unpin_ctx_obj:
 836         i915_gem_object_ggtt_unpin(ctx_obj);
 837 reset_pin_count:
 838         ctx->engine[ring->id].pin_count = 0;
 839
 840         return ret;
 841 }
 842
 843 void intel_lr_context_unpin(struct intel_engine_cs *ring,
 844                 struct intel_context *ctx)
 845 {
 846         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 847         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 848
 849         if (ctx_obj) {
 850                 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 851                 if (--ctx->engine[ring->id].pin_count == 0) {
 852                         intel_unpin_ringbuffer_obj(ringbuf);
 853                         i915_gem_object_ggtt_unpin(ctx_obj);
 854                 }
 855         }
 856 }
 857
 858 static int logical_ring_alloc_request(struct intel_engine_cs *ring,
 859                                       struct intel_context *ctx)
 860 {
 861         struct drm_i915_gem_request *request;
 862         struct drm_i915_private *dev_private = ring->dev->dev_private;
 863         int ret;
 864
 865         if (ring->outstanding_lazy_request)
 866                 return 0;
 867
 868         request = kzalloc(sizeof(*request), GFP_KERNEL);
 869         if (request == NULL)
 870                 return -ENOMEM;
 871
 872         if (ctx != ring->default_context) {
 873                 ret = intel_lr_context_pin(ring, ctx);
 874                 if (ret) {
 875                         kfree(request);
 876                         return ret;
 877                 }
 878         }
 879
 880         kref_init(&request->ref);
 881         request->ring = ring;
 882         request->uniq = dev_private->request_uniq++;
 883
 884         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
 885         if (ret) {
 886                 intel_lr_context_unpin(ring, ctx);
 887                 kfree(request);
 888                 return ret;
 889         }
 890
 891         request->ctx = ctx;
 892         i915_gem_context_reference(request->ctx);
 893         request->ringbuf = ctx->engine[ring->id].ringbuf;
 894
 895         ring->outstanding_lazy_request = request;
 896         return 0;
 897 }
 898
 899 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
 900                                      int bytes)
 901 {
 902         struct intel_engine_cs *ring = ringbuf->ring;
 903         struct drm_i915_gem_request *request;
 904         int ret;
 905
 906         if (intel_ring_space(ringbuf) >= bytes)
 907                 return 0;
 908
 909         list_for_each_entry(request, &ring->request_list, list) {
 910                 /*
 911                  * The request queue is per-engine, so can contain requests
 912                  * from multiple ringbuffers. Here, we must ignore any that
 913                  * aren't from the ringbuffer we're considering.
 914                  */
 915                 struct intel_context *ctx = request->ctx;
 916                 if (ctx->engine[ring->id].ringbuf != ringbuf)
 917                         continue;
 918
 919                 /* Would completion of this request free enough space? */
 920                 if (__intel_ring_space(request->tail, ringbuf->tail,
 921                                        ringbuf->size) >= bytes) {
 922                         break;
 923                 }
 924         }
 925
 926         if (&request->list == &ring->request_list)
 927                 return -ENOSPC;
 928
 929         ret = i915_wait_request(request);
 930         if (ret)
 931                 return ret;
 932
 933         i915_gem_retire_requests_ring(ring);
 934
 935         return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC;
 936 }
 937
 938 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
 939                                        struct intel_context *ctx,
 940                                        int bytes)
 941 {
 942         struct intel_engine_cs *ring = ringbuf->ring;
 943         struct drm_device *dev = ring->dev;
 944         struct drm_i915_private *dev_priv = dev->dev_private;
 945         unsigned long end;
 946         int ret;
 947
 948         ret = logical_ring_wait_request(ringbuf, bytes);
 949         if (ret != -ENOSPC)
 950                 return ret;
 951
 952         /* Force the context submission in case we have been skipping it */
 953         intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL);
 954
 955         /* With GEM the hangcheck timer should kick us out of the loop,
 956          * leaving it early runs the risk of corrupting GEM state (due
 957          * to running on almost untested codepaths). But on resume
 958          * timers don't work yet, so prevent a complete hang in that
 959          * case by choosing an insanely large timeout. */
 960         end = jiffies + 60 * HZ;
 961
 962         ret = 0;
 963         do {
 964                 if (intel_ring_space(ringbuf) >= bytes)
 965                         break;
 966
 967                 msleep(1);
 968
 969                 if (dev_priv->mm.interruptible && signal_pending(current)) {
 970                         ret = -ERESTARTSYS;
 971                         break;
 972                 }
 973
 974                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
 975                                            dev_priv->mm.interruptible);
 976                 if (ret)
 977                         break;
 978
 979                 if (time_after(jiffies, end)) {
 980                         ret = -EBUSY;
 981                         break;
 982                 }
 983         } while (1);
 984
 985         return ret;
 986 }
 987
 988 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
 989                                     struct intel_context *ctx)
 990 {
 991         uint32_t __iomem *virt;
 992         int rem = ringbuf->size - ringbuf->tail;
 993
 994         if (ringbuf->space < rem) {
 995                 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
 996
 997                 if (ret)
 998                         return ret;
 999         }
1000
1001         virt = ringbuf->virtual_start + ringbuf->tail;
1002         rem /= 4;
1003         while (rem--)
1004                 iowrite32(MI_NOOP, virt++);
1005
1006         ringbuf->tail = 0;
1007         intel_ring_update_space(ringbuf);
1008
1009         return 0;
1010 }
1011
1012 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
1013                                 struct intel_context *ctx, int bytes)
1014 {
1015         int ret;
1016
1017         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1018                 ret = logical_ring_wrap_buffer(ringbuf, ctx);
1019                 if (unlikely(ret))
1020                         return ret;
1021         }
1022
1023         if (unlikely(ringbuf->space < bytes)) {
1024                 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
1025                 if (unlikely(ret))
1026                         return ret;
1027         }
1028
1029         return 0;
1030 }
1031
1032 /**
1033  * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1034  *
1035  * @ringbuf: Logical ringbuffer.
1036  * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1037  *
1038  * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1039  * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1040  * and also preallocates a request (every workload submission is still mediated through
1041  * requests, same as it did with legacy ringbuffer submission).
1042  *
1043  * Return: non-zero if the ringbuffer is not ready to be written to.
1044  */
1045 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
1046                              struct intel_context *ctx, int num_dwords)
1047 {
1048         struct intel_engine_cs *ring = ringbuf->ring;
1049         struct drm_device *dev = ring->dev;
1050         struct drm_i915_private *dev_priv = dev->dev_private;
1051         int ret;
1052
1053         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1054                                    dev_priv->mm.interruptible);
1055         if (ret)
1056                 return ret;
1057
1058         ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
1059         if (ret)
1060                 return ret;
1061
1062         /* Preallocate the olr before touching the ring */
1063         ret = logical_ring_alloc_request(ring, ctx);
1064         if (ret)
1065                 return ret;
1066
1067         ringbuf->space -= num_dwords * sizeof(uint32_t);
1068         return 0;
1069 }
1070
1071 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1072                                                struct intel_context *ctx)
1073 {
1074         int ret, i;
1075         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1076         struct drm_device *dev = ring->dev;
1077         struct drm_i915_private *dev_priv = dev->dev_private;
1078         struct i915_workarounds *w = &dev_priv->workarounds;
1079
1080         if (WARN_ON_ONCE(w->count == 0))
1081                 return 0;
1082
1083         ring->gpu_caches_dirty = true;
1084         ret = logical_ring_flush_all_caches(ringbuf, ctx);
1085         if (ret)
1086                 return ret;
1087
1088         ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2);
1089         if (ret)
1090                 return ret;
1091
1092         intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1093         for (i = 0; i < w->count; i++) {
1094                 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1095                 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1096         }
1097         intel_logical_ring_emit(ringbuf, MI_NOOP);
1098
1099         intel_logical_ring_advance(ringbuf);
1100
1101         ring->gpu_caches_dirty = true;
1102         ret = logical_ring_flush_all_caches(ringbuf, ctx);
1103         if (ret)
1104                 return ret;
1105
1106         return 0;
1107 }
1108
1109 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1110 {
1111         struct drm_device *dev = ring->dev;
1112         struct drm_i915_private *dev_priv = dev->dev_private;
1113
1114         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1115         I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1116
1117         I915_WRITE(RING_MODE_GEN7(ring),
1118                    _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1119                    _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1120         POSTING_READ(RING_MODE_GEN7(ring));
1121         ring->next_context_status_buffer = 0;
1122         DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1123
1124         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1125
1126         return 0;
1127 }
1128
1129 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1130 {
1131         struct drm_device *dev = ring->dev;
1132         struct drm_i915_private *dev_priv = dev->dev_private;
1133         int ret;
1134
1135         ret = gen8_init_common_ring(ring);
1136         if (ret)
1137                 return ret;
1138
1139         /* We need to disable the AsyncFlip performance optimisations in order
1140          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1141          * programmed to '1' on all products.
1142          *
1143          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1144          */
1145         I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1146
1147         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1148
1149         return init_workarounds_ring(ring);
1150 }
1151
1152 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1153 {
1154         int ret;
1155
1156         ret = gen8_init_common_ring(ring);
1157         if (ret)
1158                 return ret;
1159
1160         return init_workarounds_ring(ring);
1161 }
1162
1163 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1164                               struct intel_context *ctx,
1165                               u64 offset, unsigned dispatch_flags)
1166 {
1167         bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1168         int ret;
1169
1170         ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1171         if (ret)
1172                 return ret;
1173
1174         /* FIXME(BDW): Address space and security selectors. */
1175         intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1176         intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1177         intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1178         intel_logical_ring_emit(ringbuf, MI_NOOP);
1179         intel_logical_ring_advance(ringbuf);
1180
1181         return 0;
1182 }
1183
1184 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1185 {
1186         struct drm_device *dev = ring->dev;
1187         struct drm_i915_private *dev_priv = dev->dev_private;
1188         unsigned long flags;
1189
1190         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1191                 return false;
1192
1193         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1194         if (ring->irq_refcount++ == 0) {
1195                 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1196                 POSTING_READ(RING_IMR(ring->mmio_base));
1197         }
1198         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1199
1200         return true;
1201 }
1202
1203 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1204 {
1205         struct drm_device *dev = ring->dev;
1206         struct drm_i915_private *dev_priv = dev->dev_private;
1207         unsigned long flags;
1208
1209         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1210         if (--ring->irq_refcount == 0) {
1211                 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1212                 POSTING_READ(RING_IMR(ring->mmio_base));
1213         }
1214         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1215 }
1216
1217 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1218                            struct intel_context *ctx,
1219                            u32 invalidate_domains,
1220                            u32 unused)
1221 {
1222         struct intel_engine_cs *ring = ringbuf->ring;
1223         struct drm_device *dev = ring->dev;
1224         struct drm_i915_private *dev_priv = dev->dev_private;
1225         uint32_t cmd;
1226         int ret;
1227
1228         ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1229         if (ret)
1230                 return ret;
1231
1232         cmd = MI_FLUSH_DW + 1;
1233
1234         /* We always require a command barrier so that subsequent
1235          * commands, such as breadcrumb interrupts, are strictly ordered
1236          * wrt the contents of the write cache being flushed to memory
1237          * (and thus being coherent from the CPU).
1238          */
1239         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1240
1241         if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1242                 cmd |= MI_INVALIDATE_TLB;
1243                 if (ring == &dev_priv->ring[VCS])
1244                         cmd |= MI_INVALIDATE_BSD;
1245         }
1246
1247         intel_logical_ring_emit(ringbuf, cmd);
1248         intel_logical_ring_emit(ringbuf,
1249                                 I915_GEM_HWS_SCRATCH_ADDR |
1250                                 MI_FLUSH_DW_USE_GTT);
1251         intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1252         intel_logical_ring_emit(ringbuf, 0); /* value */
1253         intel_logical_ring_advance(ringbuf);
1254
1255         return 0;
1256 }
1257
1258 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1259                                   struct intel_context *ctx,
1260                                   u32 invalidate_domains,
1261                                   u32 flush_domains)
1262 {
1263         struct intel_engine_cs *ring = ringbuf->ring;
1264         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1265         u32 flags = 0;
1266         int ret;
1267
1268         flags |= PIPE_CONTROL_CS_STALL;
1269
1270         if (flush_domains) {
1271                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1272                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1273         }
1274
1275         if (invalidate_domains) {
1276                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1277                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1278                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1279                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1280                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1281                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1282                 flags |= PIPE_CONTROL_QW_WRITE;
1283                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1284         }
1285
1286         ret = intel_logical_ring_begin(ringbuf, ctx, 6);
1287         if (ret)
1288                 return ret;
1289
1290         intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1291         intel_logical_ring_emit(ringbuf, flags);
1292         intel_logical_ring_emit(ringbuf, scratch_addr);
1293         intel_logical_ring_emit(ringbuf, 0);
1294         intel_logical_ring_emit(ringbuf, 0);
1295         intel_logical_ring_emit(ringbuf, 0);
1296         intel_logical_ring_advance(ringbuf);
1297
1298         return 0;
1299 }
1300
1301 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1302 {
1303         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1304 }
1305
1306 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1307 {
1308         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1309 }
1310
1311 static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1312                              struct drm_i915_gem_request *request)
1313 {
1314         struct intel_engine_cs *ring = ringbuf->ring;
1315         u32 cmd;
1316         int ret;
1317
1318         ret = intel_logical_ring_begin(ringbuf, request->ctx, 6);
1319         if (ret)
1320                 return ret;
1321
1322         cmd = MI_STORE_DWORD_IMM_GEN4;
1323         cmd |= MI_GLOBAL_GTT;
1324
1325         intel_logical_ring_emit(ringbuf, cmd);
1326         intel_logical_ring_emit(ringbuf,
1327                                 (ring->status_page.gfx_addr +
1328                                 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1329         intel_logical_ring_emit(ringbuf, 0);
1330         intel_logical_ring_emit(ringbuf,
1331                 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1332         intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1333         intel_logical_ring_emit(ringbuf, MI_NOOP);
1334         intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
1335
1336         return 0;
1337 }
1338
1339 static int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1340                                               struct intel_context *ctx)
1341 {
1342         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1343         struct render_state so;
1344         struct drm_i915_file_private *file_priv = ctx->file_priv;
1345         struct drm_file *file = file_priv ? file_priv->file : NULL;
1346         int ret;
1347
1348         ret = i915_gem_render_state_prepare(ring, &so);
1349         if (ret)
1350                 return ret;
1351
1352         if (so.rodata == NULL)
1353                 return 0;
1354
1355         ret = ring->emit_bb_start(ringbuf,
1356                         ctx,
1357                         so.ggtt_offset,
1358                         I915_DISPATCH_SECURE);
1359         if (ret)
1360                 goto out;
1361
1362         i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1363
1364         ret = __i915_add_request(ring, file, so.obj);
1365         /* intel_logical_ring_add_request moves object to inactive if it
1366          * fails */
1367 out:
1368         i915_gem_render_state_fini(&so);
1369         return ret;
1370 }
1371
1372 static int gen8_init_rcs_context(struct intel_engine_cs *ring,
1373                        struct intel_context *ctx)
1374 {
1375         int ret;
1376
1377         ret = intel_logical_ring_workarounds_emit(ring, ctx);
1378         if (ret)
1379                 return ret;
1380
1381         return intel_lr_context_render_state_init(ring, ctx);
1382 }
1383
1384 /**
1385  * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1386  *
1387  * @ring: Engine Command Streamer.
1388  *
1389  */
1390 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1391 {
1392         struct drm_i915_private *dev_priv;
1393
1394         if (!intel_ring_initialized(ring))
1395                 return;
1396
1397         dev_priv = ring->dev->dev_private;
1398
1399         intel_logical_ring_stop(ring);
1400         WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1401         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1402
1403         if (ring->cleanup)
1404                 ring->cleanup(ring);
1405
1406         i915_cmd_parser_fini_ring(ring);
1407
1408         if (ring->status_page.obj) {
1409                 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1410                 ring->status_page.obj = NULL;
1411         }
1412 }
1413
1414 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1415 {
1416         int ret;
1417
1418         /* Intentionally left blank. */
1419         ring->buffer = NULL;
1420
1421         ring->dev = dev;
1422         INIT_LIST_HEAD(&ring->active_list);
1423         INIT_LIST_HEAD(&ring->request_list);
1424         init_waitqueue_head(&ring->irq_queue);
1425
1426         INIT_LIST_HEAD(&ring->execlist_queue);
1427         INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1428         spin_lock_init(&ring->execlist_lock);
1429
1430         ret = i915_cmd_parser_init_ring(ring);
1431         if (ret)
1432                 return ret;
1433
1434         ret = intel_lr_context_deferred_create(ring->default_context, ring);
1435
1436         return ret;
1437 }
1438
1439 static int logical_render_ring_init(struct drm_device *dev)
1440 {
1441         struct drm_i915_private *dev_priv = dev->dev_private;
1442         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1443         int ret;
1444
1445         ring->name = "render ring";
1446         ring->id = RCS;
1447         ring->mmio_base = RENDER_RING_BASE;
1448         ring->irq_enable_mask =
1449                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1450         ring->irq_keep_mask =
1451                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1452         if (HAS_L3_DPF(dev))
1453                 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1454
1455         if (INTEL_INFO(dev)->gen >= 9)
1456                 ring->init_hw = gen9_init_render_ring;
1457         else
1458                 ring->init_hw = gen8_init_render_ring;
1459         ring->init_context = gen8_init_rcs_context;
1460         ring->cleanup = intel_fini_pipe_control;
1461         ring->get_seqno = gen8_get_seqno;
1462         ring->set_seqno = gen8_set_seqno;
1463         ring->emit_request = gen8_emit_request;
1464         ring->emit_flush = gen8_emit_flush_render;
1465         ring->irq_get = gen8_logical_ring_get_irq;
1466         ring->irq_put = gen8_logical_ring_put_irq;
1467         ring->emit_bb_start = gen8_emit_bb_start;
1468
1469         ring->dev = dev;
1470         ret = logical_ring_init(dev, ring);
1471         if (ret)
1472                 return ret;
1473
1474         return intel_init_pipe_control(ring);
1475 }
1476
1477 static int logical_bsd_ring_init(struct drm_device *dev)
1478 {
1479         struct drm_i915_private *dev_priv = dev->dev_private;
1480         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1481
1482         ring->name = "bsd ring";
1483         ring->id = VCS;
1484         ring->mmio_base = GEN6_BSD_RING_BASE;
1485         ring->irq_enable_mask =
1486                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1487         ring->irq_keep_mask =
1488                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1489
1490         ring->init_hw = gen8_init_common_ring;
1491         ring->get_seqno = gen8_get_seqno;
1492         ring->set_seqno = gen8_set_seqno;
1493         ring->emit_request = gen8_emit_request;
1494         ring->emit_flush = gen8_emit_flush;
1495         ring->irq_get = gen8_logical_ring_get_irq;
1496         ring->irq_put = gen8_logical_ring_put_irq;
1497         ring->emit_bb_start = gen8_emit_bb_start;
1498
1499         return logical_ring_init(dev, ring);
1500 }
1501
1502 static int logical_bsd2_ring_init(struct drm_device *dev)
1503 {
1504         struct drm_i915_private *dev_priv = dev->dev_private;
1505         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1506
1507         ring->name = "bds2 ring";
1508         ring->id = VCS2;
1509         ring->mmio_base = GEN8_BSD2_RING_BASE;
1510         ring->irq_enable_mask =
1511                 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1512         ring->irq_keep_mask =
1513                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1514
1515         ring->init_hw = gen8_init_common_ring;
1516         ring->get_seqno = gen8_get_seqno;
1517         ring->set_seqno = gen8_set_seqno;
1518         ring->emit_request = gen8_emit_request;
1519         ring->emit_flush = gen8_emit_flush;
1520         ring->irq_get = gen8_logical_ring_get_irq;
1521         ring->irq_put = gen8_logical_ring_put_irq;
1522         ring->emit_bb_start = gen8_emit_bb_start;
1523
1524         return logical_ring_init(dev, ring);
1525 }
1526
1527 static int logical_blt_ring_init(struct drm_device *dev)
1528 {
1529         struct drm_i915_private *dev_priv = dev->dev_private;
1530         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1531
1532         ring->name = "blitter ring";
1533         ring->id = BCS;
1534         ring->mmio_base = BLT_RING_BASE;
1535         ring->irq_enable_mask =
1536                 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1537         ring->irq_keep_mask =
1538                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1539
1540         ring->init_hw = gen8_init_common_ring;
1541         ring->get_seqno = gen8_get_seqno;
1542         ring->set_seqno = gen8_set_seqno;
1543         ring->emit_request = gen8_emit_request;
1544         ring->emit_flush = gen8_emit_flush;
1545         ring->irq_get = gen8_logical_ring_get_irq;
1546         ring->irq_put = gen8_logical_ring_put_irq;
1547         ring->emit_bb_start = gen8_emit_bb_start;
1548
1549         return logical_ring_init(dev, ring);
1550 }
1551
1552 static int logical_vebox_ring_init(struct drm_device *dev)
1553 {
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1556
1557         ring->name = "video enhancement ring";
1558         ring->id = VECS;
1559         ring->mmio_base = VEBOX_RING_BASE;
1560         ring->irq_enable_mask =
1561                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1562         ring->irq_keep_mask =
1563                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1564
1565         ring->init_hw = gen8_init_common_ring;
1566         ring->get_seqno = gen8_get_seqno;
1567         ring->set_seqno = gen8_set_seqno;
1568         ring->emit_request = gen8_emit_request;
1569         ring->emit_flush = gen8_emit_flush;
1570         ring->irq_get = gen8_logical_ring_get_irq;
1571         ring->irq_put = gen8_logical_ring_put_irq;
1572         ring->emit_bb_start = gen8_emit_bb_start;
1573
1574         return logical_ring_init(dev, ring);
1575 }
1576
1577 /**
1578  * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1579  * @dev: DRM device.
1580  *
1581  * This function inits the engines for an Execlists submission style (the equivalent in the
1582  * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1583  * those engines that are present in the hardware.
1584  *
1585  * Return: non-zero if the initialization failed.
1586  */
1587 int intel_logical_rings_init(struct drm_device *dev)
1588 {
1589         struct drm_i915_private *dev_priv = dev->dev_private;
1590         int ret;
1591
1592         ret = logical_render_ring_init(dev);
1593         if (ret)
1594                 return ret;
1595
1596         if (HAS_BSD(dev)) {
1597                 ret = logical_bsd_ring_init(dev);
1598                 if (ret)
1599                         goto cleanup_render_ring;
1600         }
1601
1602         if (HAS_BLT(dev)) {
1603                 ret = logical_blt_ring_init(dev);
1604                 if (ret)
1605                         goto cleanup_bsd_ring;
1606         }
1607
1608         if (HAS_VEBOX(dev)) {
1609                 ret = logical_vebox_ring_init(dev);
1610                 if (ret)
1611                         goto cleanup_blt_ring;
1612         }
1613
1614         if (HAS_BSD2(dev)) {
1615                 ret = logical_bsd2_ring_init(dev);
1616                 if (ret)
1617                         goto cleanup_vebox_ring;
1618         }
1619
1620         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1621         if (ret)
1622                 goto cleanup_bsd2_ring;
1623
1624         return 0;
1625
1626 cleanup_bsd2_ring:
1627         intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1628 cleanup_vebox_ring:
1629         intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1630 cleanup_blt_ring:
1631         intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1632 cleanup_bsd_ring:
1633         intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1634 cleanup_render_ring:
1635         intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1636
1637         return ret;
1638 }
1639
1640 static u32
1641 make_rpcs(struct drm_device *dev)
1642 {
1643         u32 rpcs = 0;
1644
1645         /*
1646          * No explicit RPCS request is needed to ensure full
1647          * slice/subslice/EU enablement prior to Gen9.
1648         */
1649         if (INTEL_INFO(dev)->gen < 9)
1650                 return 0;
1651
1652         /*
1653          * Starting in Gen9, render power gating can leave
1654          * slice/subslice/EU in a partially enabled state. We
1655          * must make an explicit request through RPCS for full
1656          * enablement.
1657         */
1658         if (INTEL_INFO(dev)->has_slice_pg) {
1659                 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1660                 rpcs |= INTEL_INFO(dev)->slice_total <<
1661                         GEN8_RPCS_S_CNT_SHIFT;
1662                 rpcs |= GEN8_RPCS_ENABLE;
1663         }
1664
1665         if (INTEL_INFO(dev)->has_subslice_pg) {
1666                 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1667                 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
1668                         GEN8_RPCS_SS_CNT_SHIFT;
1669                 rpcs |= GEN8_RPCS_ENABLE;
1670         }
1671
1672         if (INTEL_INFO(dev)->has_eu_pg) {
1673                 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1674                         GEN8_RPCS_EU_MIN_SHIFT;
1675                 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1676                         GEN8_RPCS_EU_MAX_SHIFT;
1677                 rpcs |= GEN8_RPCS_ENABLE;
1678         }
1679
1680         return rpcs;
1681 }
1682
1683 static int
1684 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1685                     struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1686 {
1687         struct drm_device *dev = ring->dev;
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1690         struct page *page;
1691         uint32_t *reg_state;
1692         int ret;
1693
1694         if (!ppgtt)
1695                 ppgtt = dev_priv->mm.aliasing_ppgtt;
1696
1697         ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1698         if (ret) {
1699                 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1700                 return ret;
1701         }
1702
1703         ret = i915_gem_object_get_pages(ctx_obj);
1704         if (ret) {
1705                 DRM_DEBUG_DRIVER("Could not get object pages\n");
1706                 return ret;
1707         }
1708
1709         i915_gem_object_pin_pages(ctx_obj);
1710
1711         /* The second page of the context object contains some fields which must
1712          * be set up prior to the first execution. */
1713         page = i915_gem_object_get_page(ctx_obj, 1);
1714         reg_state = kmap_atomic(page);
1715
1716         /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1717          * commands followed by (reg, value) pairs. The values we are setting here are
1718          * only for the first context restore: on a subsequent save, the GPU will
1719          * recreate this batchbuffer with new values (including all the missing
1720          * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1721         if (ring->id == RCS)
1722                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1723         else
1724                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1725         reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1726         reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1727         reg_state[CTX_CONTEXT_CONTROL+1] =
1728                 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1729                                 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
1730         reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1731         reg_state[CTX_RING_HEAD+1] = 0;
1732         reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1733         reg_state[CTX_RING_TAIL+1] = 0;
1734         reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1735         /* Ring buffer start address is not known until the buffer is pinned.
1736          * It is written to the context image in execlists_update_context()
1737          */
1738         reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1739         reg_state[CTX_RING_BUFFER_CONTROL+1] =
1740                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1741         reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1742         reg_state[CTX_BB_HEAD_U+1] = 0;
1743         reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1744         reg_state[CTX_BB_HEAD_L+1] = 0;
1745         reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1746         reg_state[CTX_BB_STATE+1] = (1<<5);
1747         reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1748         reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1749         reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1750         reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1751         reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1752         reg_state[CTX_SECOND_BB_STATE+1] = 0;
1753         if (ring->id == RCS) {
1754                 /* TODO: according to BSpec, the register state context
1755                  * for CHV does not have these. OTOH, these registers do
1756                  * exist in CHV. I'm waiting for a clarification */
1757                 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1758                 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1759                 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1760                 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1761                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1762                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1763         }
1764         reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1765         reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1766         reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1767         reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1768         reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1769         reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1770         reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1771         reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1772         reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1773         reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1774         reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1775         reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1776         reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[3]->daddr);
1777         reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[3]->daddr);
1778         reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[2]->daddr);
1779         reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[2]->daddr);
1780         reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[1]->daddr);
1781         reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[1]->daddr);
1782         reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[0]->daddr);
1783         reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[0]->daddr);
1784         if (ring->id == RCS) {
1785                 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1786                 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
1787                 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
1788         }
1789
1790         kunmap_atomic(reg_state);
1791
1792         ctx_obj->dirty = 1;
1793         set_page_dirty(page);
1794         i915_gem_object_unpin_pages(ctx_obj);
1795
1796         return 0;
1797 }
1798
1799 /**
1800  * intel_lr_context_free() - free the LRC specific bits of a context
1801  * @ctx: the LR context to free.
1802  *
1803  * The real context freeing is done in i915_gem_context_free: this only
1804  * takes care of the bits that are LRC related: the per-engine backing
1805  * objects and the logical ringbuffer.
1806  */
1807 void intel_lr_context_free(struct intel_context *ctx)
1808 {
1809         int i;
1810
1811         for (i = 0; i < I915_NUM_RINGS; i++) {
1812                 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1813
1814                 if (ctx_obj) {
1815                         struct intel_ringbuffer *ringbuf =
1816                                         ctx->engine[i].ringbuf;
1817                         struct intel_engine_cs *ring = ringbuf->ring;
1818
1819                         if (ctx == ring->default_context) {
1820                                 intel_unpin_ringbuffer_obj(ringbuf);
1821                                 i915_gem_object_ggtt_unpin(ctx_obj);
1822                         }
1823                         WARN_ON(ctx->engine[ring->id].pin_count);
1824                         intel_destroy_ringbuffer_obj(ringbuf);
1825                         kfree(ringbuf);
1826                         drm_gem_object_unreference(&ctx_obj->base);
1827                 }
1828         }
1829 }
1830
1831 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1832 {
1833         int ret = 0;
1834
1835         WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1836
1837         switch (ring->id) {
1838         case RCS:
1839                 if (INTEL_INFO(ring->dev)->gen >= 9)
1840                         ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1841                 else
1842                         ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1843                 break;
1844         case VCS:
1845         case BCS:
1846         case VECS:
1847         case VCS2:
1848                 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1849                 break;
1850         }
1851
1852         return ret;
1853 }
1854
1855 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1856                 struct drm_i915_gem_object *default_ctx_obj)
1857 {
1858         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1859
1860         /* The status page is offset 0 from the default context object
1861          * in LRC mode. */
1862         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1863         ring->status_page.page_addr =
1864                         kmap(sg_page(default_ctx_obj->pages->sgl));
1865         ring->status_page.obj = default_ctx_obj;
1866
1867         I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1868                         (u32)ring->status_page.gfx_addr);
1869         POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1870 }
1871
1872 /**
1873  * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1874  * @ctx: LR context to create.
1875  * @ring: engine to be used with the context.
1876  *
1877  * This function can be called more than once, with different engines, if we plan
1878  * to use the context with them. The context backing objects and the ringbuffers
1879  * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1880  * the creation is a deferred call: it's better to make sure first that we need to use
1881  * a given ring with the context.
1882  *
1883  * Return: non-zero on error.
1884  */
1885 int intel_lr_context_deferred_create(struct intel_context *ctx,
1886                                      struct intel_engine_cs *ring)
1887 {
1888         const bool is_global_default_ctx = (ctx == ring->default_context);
1889         struct drm_device *dev = ring->dev;
1890         struct drm_i915_gem_object *ctx_obj;
1891         uint32_t context_size;
1892         struct intel_ringbuffer *ringbuf;
1893         int ret;
1894
1895         WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1896         WARN_ON(ctx->engine[ring->id].state);
1897
1898         context_size = round_up(get_lr_context_size(ring), 4096);
1899
1900         ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1901         if (IS_ERR(ctx_obj)) {
1902                 ret = PTR_ERR(ctx_obj);
1903                 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1904                 return ret;
1905         }
1906
1907         if (is_global_default_ctx) {
1908                 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1909                 if (ret) {
1910                         DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1911                                         ret);
1912                         drm_gem_object_unreference(&ctx_obj->base);
1913                         return ret;
1914                 }
1915         }
1916
1917         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1918         if (!ringbuf) {
1919                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1920                                 ring->name);
1921                 ret = -ENOMEM;
1922                 goto error_unpin_ctx;
1923         }
1924
1925         ringbuf->ring = ring;
1926
1927         ringbuf->size = 32 * PAGE_SIZE;
1928         ringbuf->effective_size = ringbuf->size;
1929         ringbuf->head = 0;
1930         ringbuf->tail = 0;
1931         ringbuf->last_retired_head = -1;
1932         intel_ring_update_space(ringbuf);
1933
1934         if (ringbuf->obj == NULL) {
1935                 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1936                 if (ret) {
1937                         DRM_DEBUG_DRIVER(
1938                                 "Failed to allocate ringbuffer obj %s: %d\n",
1939                                 ring->name, ret);
1940                         goto error_free_rbuf;
1941                 }
1942
1943                 if (is_global_default_ctx) {
1944                         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1945                         if (ret) {
1946                                 DRM_ERROR(
1947                                         "Failed to pin and map ringbuffer %s: %d\n",
1948                                         ring->name, ret);
1949                                 goto error_destroy_rbuf;
1950                         }
1951                 }
1952
1953         }
1954
1955         ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1956         if (ret) {
1957                 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1958                 goto error;
1959         }
1960
1961         ctx->engine[ring->id].ringbuf = ringbuf;
1962         ctx->engine[ring->id].state = ctx_obj;
1963
1964         if (ctx == ring->default_context)
1965                 lrc_setup_hardware_status_page(ring, ctx_obj);
1966         else if (ring->id == RCS && !ctx->rcs_initialized) {
1967                 if (ring->init_context) {
1968                         ret = ring->init_context(ring, ctx);
1969                         if (ret) {
1970                                 DRM_ERROR("ring init context: %d\n", ret);
1971                                 ctx->engine[ring->id].ringbuf = NULL;
1972                                 ctx->engine[ring->id].state = NULL;
1973                                 goto error;
1974                         }
1975                 }
1976
1977                 ctx->rcs_initialized = true;
1978         }
1979
1980         return 0;
1981
1982 error:
1983         if (is_global_default_ctx)
1984                 intel_unpin_ringbuffer_obj(ringbuf);
1985 error_destroy_rbuf:
1986         intel_destroy_ringbuffer_obj(ringbuf);
1987 error_free_rbuf:
1988         kfree(ringbuf);
1989 error_unpin_ctx:
1990         if (is_global_default_ctx)
1991                 i915_gem_object_ggtt_unpin(ctx_obj);
1992         drm_gem_object_unreference(&ctx_obj->base);
1993         return ret;
1994 }
1995
1996 void intel_lr_context_reset(struct drm_device *dev,
1997                         struct intel_context *ctx)
1998 {
1999         struct drm_i915_private *dev_priv = dev->dev_private;
2000         struct intel_engine_cs *ring;
2001         int i;
2002
2003         for_each_ring(ring, dev_priv, i) {
2004                 struct drm_i915_gem_object *ctx_obj =
2005                                 ctx->engine[ring->id].state;
2006                 struct intel_ringbuffer *ringbuf =
2007                                 ctx->engine[ring->id].ringbuf;
2008                 uint32_t *reg_state;
2009                 struct page *page;
2010
2011                 if (!ctx_obj)
2012                         continue;
2013
2014                 if (i915_gem_object_get_pages(ctx_obj)) {
2015                         WARN(1, "Failed get_pages for context obj\n");
2016                         continue;
2017                 }
2018                 page = i915_gem_object_get_page(ctx_obj, 1);
2019                 reg_state = kmap_atomic(page);
2020
2021                 reg_state[CTX_RING_HEAD+1] = 0;
2022                 reg_state[CTX_RING_TAIL+1] = 0;
2023
2024                 kunmap_atomic(reg_state);
2025
2026                 ringbuf->head = 0;
2027                 ringbuf->tail = 0;
2028         }
2029 }