drivers/gpu/drm/i915/intel_lrc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *    Michel Thierry <michel.thierry@intel.com>
  26  *    Thomas Daniel <thomas.daniel@intel.com>
  27  *    Oscar Mateo <oscar.mateo@intel.com>
  28  *
  29  */
  30
  31 /**
  32  * DOC: Logical Rings, Logical Ring Contexts and Execlists
  33  *
  34  * Motivation:
  35  * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
  36  * These expanded contexts enable a number of new abilities, especially
  37  * "Execlists" (also implemented in this file).
  38  *
  39  * One of the main differences with the legacy HW contexts is that logical
  40  * ring contexts incorporate many more things to the context's state, like
  41  * PDPs or ringbuffer control registers:
  42  *
  43  * The reason why PDPs are included in the context is straightforward: as
  44  * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
  45  * contained there mean you don't need to do a ppgtt->switch_mm yourself,
  46  * instead, the GPU will do it for you on the context switch.
  47  *
  48  * But, what about the ringbuffer control registers (head, tail, etc..)?
  49  * shouldn't we just need a set of those per engine command streamer? This is
  50  * where the name "Logical Rings" starts to make sense: by virtualizing the
  51  * rings, the engine cs shifts to a new "ring buffer" with every context
  52  * switch. When you want to submit a workload to the GPU you: A) choose your
  53  * context, B) find its appropriate virtualized ring, C) write commands to it
  54  * and then, finally, D) tell the GPU to switch to that context.
  55  *
  56  * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
  57  * to a contexts is via a context execution list, ergo "Execlists".
  58  *
  59  * LRC implementation:
  60  * Regarding the creation of contexts, we have:
  61  *
  62  * - One global default context.
  63  * - One local default context for each opened fd.
  64  * - One local extra context for each context create ioctl call.
  65  *
  66  * Now that ringbuffers belong per-context (and not per-engine, like before)
  67  * and that contexts are uniquely tied to a given engine (and not reusable,
  68  * like before) we need:
  69  *
  70  * - One ringbuffer per-engine inside each context.
  71  * - One backing object per-engine inside each context.
  72  *
  73  * The global default context starts its life with these new objects fully
  74  * allocated and populated. The local default context for each opened fd is
  75  * more complex, because we don't know at creation time which engine is going
  76  * to use them. To handle this, we have implemented a deferred creation of LR
  77  * contexts:
  78  *
  79  * The local context starts its life as a hollow or blank holder, that only
  80  * gets populated for a given engine once we receive an execbuffer. If later
  81  * on we receive another execbuffer ioctl for the same context but a different
  82  * engine, we allocate/populate a new ringbuffer and context backing object and
  83  * so on.
  84  *
  85  * Finally, regarding local contexts created using the ioctl call: as they are
  86  * only allowed with the render ring, we can allocate & populate them right
  87  * away (no need to defer anything, at least for now).
  88  *
  89  * Execlists implementation:
  90  * Execlists are the new method by which, on gen8+ hardware, workloads are
  91  * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
  92  * This method works as follows:
  93  *
  94  * When a request is committed, its commands (the BB start and any leading or
  95  * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
  96  * for the appropriate context. The tail pointer in the hardware context is not
  97  * updated at this time, but instead, kept by the driver in the ringbuffer
  98  * structure. A structure representing this request is added to a request queue
  99  * for the appropriate engine: this structure contains a copy of the context's
 100  * tail after the request was written to the ring buffer and a pointer to the
 101  * context itself.
 102  *
 103  * If the engine's request queue was empty before the request was added, the
 104  * queue is processed immediately. Otherwise the queue will be processed during
 105  * a context switch interrupt. In any case, elements on the queue will get sent
 106  * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 107  * globally unique 20-bits submission ID.
 108  *
 109  * When execution of a request completes, the GPU updates the context status
 110  * buffer with a context complete event and generates a context switch interrupt.
 111  * During the interrupt handling, the driver examines the events in the buffer:
 112  * for each context complete event, if the announced ID matches that on the head
 113  * of the request queue, then that request is retired and removed from the queue.
 114  *
 115  * After processing, if any requests were retired and the queue is not empty
 116  * then a new execution list can be submitted. The two requests at the front of
 117  * the queue are next to be submitted but since a context may not occur twice in
 118  * an execution list, if subsequent requests have the same ID as the first then
 119  * the two requests must be combined. This is done simply by discarding requests
 120  * at the head of the queue until either only one requests is left (in which case
 121  * we use a NULL second context) or the first two requests have unique IDs.
 122  *
 123  * By always executing the first two requests in the queue the driver ensures
 124  * that the GPU is kept as busy as possible. In the case where a single context
 125  * completes but a second context is still executing, the request for this second
 126  * context will be at the head of the queue when we remove the first one. This
 127  * request will then be resubmitted along with a new request for a different context,
 128  * which will cause the hardware to continue executing the second request and queue
 129  * the new request (the GPU detects the condition of a context getting preempted
 130  * with the same context and optimizes the context switch flow by not doing
 131  * preemption, but just sampling the new tail pointer).
 132  *
 133  */
 134
 135 #include <drm/drmP.h>
 136 #include <drm/i915_drm.h>
 137 #include "i915_drv.h"
 138
 139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
 140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
 141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
 142
 143 #define RING_EXECLIST_QFULL             (1 << 0x2)
 144 #define RING_EXECLIST1_VALID            (1 << 0x3)
 145 #define RING_EXECLIST0_VALID            (1 << 0x4)
 146 #define RING_EXECLIST_ACTIVE_STATUS     (3 << 0xE)
 147 #define RING_EXECLIST1_ACTIVE           (1 << 0x11)
 148 #define RING_EXECLIST0_ACTIVE           (1 << 0x12)
 149
 150 #define GEN8_CTX_STATUS_IDLE_ACTIVE     (1 << 0)
 151 #define GEN8_CTX_STATUS_PREEMPTED       (1 << 1)
 152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH  (1 << 2)
 153 #define GEN8_CTX_STATUS_ACTIVE_IDLE     (1 << 3)
 154 #define GEN8_CTX_STATUS_COMPLETE        (1 << 4)
 155 #define GEN8_CTX_STATUS_LITE_RESTORE    (1 << 15)
 156
 157 #define CTX_LRI_HEADER_0                0x01
 158 #define CTX_CONTEXT_CONTROL             0x02
 159 #define CTX_RING_HEAD                   0x04
 160 #define CTX_RING_TAIL                   0x06
 161 #define CTX_RING_BUFFER_START           0x08
 162 #define CTX_RING_BUFFER_CONTROL         0x0a
 163 #define CTX_BB_HEAD_U                   0x0c
 164 #define CTX_BB_HEAD_L                   0x0e
 165 #define CTX_BB_STATE                    0x10
 166 #define CTX_SECOND_BB_HEAD_U            0x12
 167 #define CTX_SECOND_BB_HEAD_L            0x14
 168 #define CTX_SECOND_BB_STATE             0x16
 169 #define CTX_BB_PER_CTX_PTR              0x18
 170 #define CTX_RCS_INDIRECT_CTX            0x1a
 171 #define CTX_RCS_INDIRECT_CTX_OFFSET     0x1c
 172 #define CTX_LRI_HEADER_1                0x21
 173 #define CTX_CTX_TIMESTAMP               0x22
 174 #define CTX_PDP3_UDW                    0x24
 175 #define CTX_PDP3_LDW                    0x26
 176 #define CTX_PDP2_UDW                    0x28
 177 #define CTX_PDP2_LDW                    0x2a
 178 #define CTX_PDP1_UDW                    0x2c
 179 #define CTX_PDP1_LDW                    0x2e
 180 #define CTX_PDP0_UDW                    0x30
 181 #define CTX_PDP0_LDW                    0x32
 182 #define CTX_LRI_HEADER_2                0x41
 183 #define CTX_R_PWR_CLK_STATE             0x42
 184 #define CTX_GPGPU_CSR_BASE_ADDRESS      0x44
 185
 186 #define GEN8_CTX_VALID (1<<0)
 187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
 188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
 189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
 190 #define GEN8_CTX_PRIVILEGE (1<<8)
 191 enum {
 192         ADVANCED_CONTEXT = 0,
 193         LEGACY_CONTEXT,
 194         ADVANCED_AD_CONTEXT,
 195         LEGACY_64B_CONTEXT
 196 };
 197 #define GEN8_CTX_MODE_SHIFT 3
 198 enum {
 199         FAULT_AND_HANG = 0,
 200         FAULT_AND_HALT, /* Debug only */
 201         FAULT_AND_STREAM,
 202         FAULT_AND_CONTINUE /* Unsupported */
 203 };
 204 #define GEN8_CTX_ID_SHIFT 32
 205
 206 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 207                 struct intel_context *ctx);
 208
 209 /**
 210  * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 211  * @dev: DRM device.
 212  * @enable_execlists: value of i915.enable_execlists module parameter.
 213  *
 214  * Only certain platforms support Execlists (the prerequisites being
 215  * support for Logical Ring Contexts and Aliasing PPGTT or better).
 216  *
 217  * Return: 1 if Execlists is supported and has to be enabled.
 218  */
 219 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
 220 {
 221         WARN_ON(i915.enable_ppgtt == -1);
 222
 223         if (INTEL_INFO(dev)->gen >= 9)
 224                 return 1;
 225
 226         if (enable_execlists == 0)
 227                 return 0;
 228
 229         if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
 230             i915.use_mmio_flip >= 0)
 231                 return 1;
 232
 233         return 0;
 234 }
 235
 236 /**
 237  * intel_execlists_ctx_id() - get the Execlists Context ID
 238  * @ctx_obj: Logical Ring Context backing object.
 239  *
 240  * Do not confuse with ctx->id! Unfortunately we have a name overload
 241  * here: the old context ID we pass to userspace as a handler so that
 242  * they can refer to a context, and the new context ID we pass to the
 243  * ELSP so that the GPU can inform us of the context status via
 244  * interrupts.
 245  *
 246  * Return: 20-bits globally unique context ID.
 247  */
 248 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
 249 {
 250         u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 251
 252         /* LRCA is required to be 4K aligned so the more significant 20 bits
 253          * are globally unique */
 254         return lrca >> 12;
 255 }
 256
 257 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
 258 {
 259         uint64_t desc;
 260         uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 261
 262         WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
 263
 264         desc = GEN8_CTX_VALID;
 265         desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
 266         desc |= GEN8_CTX_L3LLC_COHERENT;
 267         desc |= GEN8_CTX_PRIVILEGE;
 268         desc |= lrca;
 269         desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
 270
 271         /* TODO: WaDisableLiteRestore when we start using semaphore
 272          * signalling between Command Streamers */
 273         /* desc |= GEN8_CTX_FORCE_RESTORE; */
 274
 275         return desc;
 276 }
 277
 278 static void execlists_elsp_write(struct intel_engine_cs *ring,
 279                                  struct drm_i915_gem_object *ctx_obj0,
 280                                  struct drm_i915_gem_object *ctx_obj1)
 281 {
 282         struct drm_device *dev = ring->dev;
 283         struct drm_i915_private *dev_priv = dev->dev_private;
 284         uint64_t temp = 0;
 285         uint32_t desc[4];
 286
 287         /* XXX: You must always write both descriptors in the order below. */
 288         if (ctx_obj1)
 289                 temp = execlists_ctx_descriptor(ctx_obj1);
 290         else
 291                 temp = 0;
 292         desc[1] = (u32)(temp >> 32);
 293         desc[0] = (u32)temp;
 294
 295         temp = execlists_ctx_descriptor(ctx_obj0);
 296         desc[3] = (u32)(temp >> 32);
 297         desc[2] = (u32)temp;
 298
 299         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 300         I915_WRITE(RING_ELSP(ring), desc[1]);
 301         I915_WRITE(RING_ELSP(ring), desc[0]);
 302         I915_WRITE(RING_ELSP(ring), desc[3]);
 303
 304         /* The context is automatically loaded after the following */
 305         I915_WRITE(RING_ELSP(ring), desc[2]);
 306
 307         /* ELSP is a wo register, so use another nearby reg for posting instead */
 308         POSTING_READ(RING_EXECLIST_STATUS(ring));
 309         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 310 }
 311
 312 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
 313                                     struct drm_i915_gem_object *ring_obj,
 314                                     u32 tail)
 315 {
 316         struct page *page;
 317         uint32_t *reg_state;
 318
 319         page = i915_gem_object_get_page(ctx_obj, 1);
 320         reg_state = kmap_atomic(page);
 321
 322         reg_state[CTX_RING_TAIL+1] = tail;
 323         reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
 324
 325         kunmap_atomic(reg_state);
 326
 327         return 0;
 328 }
 329
 330 static void execlists_submit_contexts(struct intel_engine_cs *ring,
 331                                       struct intel_context *to0, u32 tail0,
 332                                       struct intel_context *to1, u32 tail1)
 333 {
 334         struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
 335         struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
 336         struct drm_i915_gem_object *ctx_obj1 = NULL;
 337         struct intel_ringbuffer *ringbuf1 = NULL;
 338
 339         BUG_ON(!ctx_obj0);
 340         WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
 341         WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
 342
 343         execlists_update_context(ctx_obj0, ringbuf0->obj, tail0);
 344
 345         if (to1) {
 346                 ringbuf1 = to1->engine[ring->id].ringbuf;
 347                 ctx_obj1 = to1->engine[ring->id].state;
 348                 BUG_ON(!ctx_obj1);
 349                 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
 350                 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
 351
 352                 execlists_update_context(ctx_obj1, ringbuf1->obj, tail1);
 353         }
 354
 355         execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
 356 }
 357
 358 static void execlists_context_unqueue(struct intel_engine_cs *ring)
 359 {
 360         struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
 361         struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
 362
 363         assert_spin_locked(&ring->execlist_lock);
 364
 365         if (list_empty(&ring->execlist_queue))
 366                 return;
 367
 368         /* Try to read in pairs */
 369         list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
 370                                  execlist_link) {
 371                 if (!req0) {
 372                         req0 = cursor;
 373                 } else if (req0->ctx == cursor->ctx) {
 374                         /* Same ctx: ignore first request, as second request
 375                          * will update tail past first request's workload */
 376                         cursor->elsp_submitted = req0->elsp_submitted;
 377                         list_del(&req0->execlist_link);
 378                         list_add_tail(&req0->execlist_link,
 379                                 &ring->execlist_retired_req_list);
 380                         req0 = cursor;
 381                 } else {
 382                         req1 = cursor;
 383                         break;
 384                 }
 385         }
 386
 387         WARN_ON(req1 && req1->elsp_submitted);
 388
 389         execlists_submit_contexts(ring, req0->ctx, req0->tail,
 390                                   req1 ? req1->ctx : NULL,
 391                                   req1 ? req1->tail : 0);
 392
 393         req0->elsp_submitted++;
 394         if (req1)
 395                 req1->elsp_submitted++;
 396 }
 397
 398 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
 399                                            u32 request_id)
 400 {
 401         struct drm_i915_gem_request *head_req;
 402
 403         assert_spin_locked(&ring->execlist_lock);
 404
 405         head_req = list_first_entry_or_null(&ring->execlist_queue,
 406                                             struct drm_i915_gem_request,
 407                                             execlist_link);
 408
 409         if (head_req != NULL) {
 410                 struct drm_i915_gem_object *ctx_obj =
 411                                 head_req->ctx->engine[ring->id].state;
 412                 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
 413                         WARN(head_req->elsp_submitted == 0,
 414                              "Never submitted head request\n");
 415
 416                         if (--head_req->elsp_submitted <= 0) {
 417                                 list_del(&head_req->execlist_link);
 418                                 list_add_tail(&head_req->execlist_link,
 419                                         &ring->execlist_retired_req_list);
 420                                 return true;
 421                         }
 422                 }
 423         }
 424
 425         return false;
 426 }
 427
 428 /**
 429  * intel_lrc_irq_handler() - handle Context Switch interrupts
 430  * @ring: Engine Command Streamer to handle.
 431  *
 432  * Check the unread Context Status Buffers and manage the submission of new
 433  * contexts to the ELSP accordingly.
 434  */
 435 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
 436 {
 437         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 438         u32 status_pointer;
 439         u8 read_pointer;
 440         u8 write_pointer;
 441         u32 status;
 442         u32 status_id;
 443         u32 submit_contexts = 0;
 444
 445         status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
 446
 447         read_pointer = ring->next_context_status_buffer;
 448         write_pointer = status_pointer & 0x07;
 449         if (read_pointer > write_pointer)
 450                 write_pointer += 6;
 451
 452         spin_lock(&ring->execlist_lock);
 453
 454         while (read_pointer < write_pointer) {
 455                 read_pointer++;
 456                 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 457                                 (read_pointer % 6) * 8);
 458                 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 459                                 (read_pointer % 6) * 8 + 4);
 460
 461                 if (status & GEN8_CTX_STATUS_PREEMPTED) {
 462                         if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
 463                                 if (execlists_check_remove_request(ring, status_id))
 464                                         WARN(1, "Lite Restored request removed from queue\n");
 465                         } else
 466                                 WARN(1, "Preemption without Lite Restore\n");
 467                 }
 468
 469                  if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
 470                      (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
 471                         if (execlists_check_remove_request(ring, status_id))
 472                                 submit_contexts++;
 473                 }
 474         }
 475
 476         if (submit_contexts != 0)
 477                 execlists_context_unqueue(ring);
 478
 479         spin_unlock(&ring->execlist_lock);
 480
 481         WARN(submit_contexts > 2, "More than two context complete events?\n");
 482         ring->next_context_status_buffer = write_pointer % 6;
 483
 484         I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
 485                    ((u32)ring->next_context_status_buffer & 0x07) << 8);
 486 }
 487
 488 static int execlists_context_queue(struct intel_engine_cs *ring,
 489                                    struct intel_context *to,
 490                                    u32 tail,
 491                                    struct drm_i915_gem_request *request)
 492 {
 493         struct drm_i915_gem_request *cursor;
 494         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 495         unsigned long flags;
 496         int num_elements = 0;
 497
 498         if (to != ring->default_context)
 499                 intel_lr_context_pin(ring, to);
 500
 501         if (!request) {
 502                 /*
 503                  * If there isn't a request associated with this submission,
 504                  * create one as a temporary holder.
 505                  */
 506                 WARN(1, "execlist context submission without request");
 507                 request = kzalloc(sizeof(*request), GFP_KERNEL);
 508                 if (request == NULL)
 509                         return -ENOMEM;
 510                 request->ring = ring;
 511                 request->ctx = to;
 512         } else {
 513                 WARN_ON(to != request->ctx);
 514         }
 515         request->tail = tail;
 516         i915_gem_request_reference(request);
 517         i915_gem_context_reference(request->ctx);
 518
 519         intel_runtime_pm_get(dev_priv);
 520
 521         spin_lock_irqsave(&ring->execlist_lock, flags);
 522
 523         list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
 524                 if (++num_elements > 2)
 525                         break;
 526
 527         if (num_elements > 2) {
 528                 struct drm_i915_gem_request *tail_req;
 529
 530                 tail_req = list_last_entry(&ring->execlist_queue,
 531                                            struct drm_i915_gem_request,
 532                                            execlist_link);
 533
 534                 if (to == tail_req->ctx) {
 535                         WARN(tail_req->elsp_submitted != 0,
 536                                 "More than 2 already-submitted reqs queued\n");
 537                         list_del(&tail_req->execlist_link);
 538                         list_add_tail(&tail_req->execlist_link,
 539                                 &ring->execlist_retired_req_list);
 540                 }
 541         }
 542
 543         list_add_tail(&request->execlist_link, &ring->execlist_queue);
 544         if (num_elements == 0)
 545                 execlists_context_unqueue(ring);
 546
 547         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 548
 549         return 0;
 550 }
 551
 552 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
 553                                               struct intel_context *ctx)
 554 {
 555         struct intel_engine_cs *ring = ringbuf->ring;
 556         uint32_t flush_domains;
 557         int ret;
 558
 559         flush_domains = 0;
 560         if (ring->gpu_caches_dirty)
 561                 flush_domains = I915_GEM_GPU_DOMAINS;
 562
 563         ret = ring->emit_flush(ringbuf, ctx,
 564                                I915_GEM_GPU_DOMAINS, flush_domains);
 565         if (ret)
 566                 return ret;
 567
 568         ring->gpu_caches_dirty = false;
 569         return 0;
 570 }
 571
 572 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
 573                                  struct intel_context *ctx,
 574                                  struct list_head *vmas)
 575 {
 576         struct intel_engine_cs *ring = ringbuf->ring;
 577         struct i915_vma *vma;
 578         uint32_t flush_domains = 0;
 579         bool flush_chipset = false;
 580         int ret;
 581
 582         list_for_each_entry(vma, vmas, exec_list) {
 583                 struct drm_i915_gem_object *obj = vma->obj;
 584
 585                 ret = i915_gem_object_sync(obj, ring);
 586                 if (ret)
 587                         return ret;
 588
 589                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
 590                         flush_chipset |= i915_gem_clflush_object(obj, false);
 591
 592                 flush_domains |= obj->base.write_domain;
 593         }
 594
 595         if (flush_domains & I915_GEM_DOMAIN_GTT)
 596                 wmb();
 597
 598         /* Unconditionally invalidate gpu caches and ensure that we do flush
 599          * any residual writes from the previous batch.
 600          */
 601         return logical_ring_invalidate_all_caches(ringbuf, ctx);
 602 }
 603
 604 /**
 605  * execlists_submission() - submit a batchbuffer for execution, Execlists style
 606  * @dev: DRM device.
 607  * @file: DRM file.
 608  * @ring: Engine Command Streamer to submit to.
 609  * @ctx: Context to employ for this submission.
 610  * @args: execbuffer call arguments.
 611  * @vmas: list of vmas.
 612  * @batch_obj: the batchbuffer to submit.
 613  * @exec_start: batchbuffer start virtual address pointer.
 614  * @flags: translated execbuffer call flags.
 615  *
 616  * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 617  * away the submission details of the execbuffer ioctl call.
 618  *
 619  * Return: non-zero if the submission fails.
 620  */
 621 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
 622                                struct intel_engine_cs *ring,
 623                                struct intel_context *ctx,
 624                                struct drm_i915_gem_execbuffer2 *args,
 625                                struct list_head *vmas,
 626                                struct drm_i915_gem_object *batch_obj,
 627                                u64 exec_start, u32 flags)
 628 {
 629         struct drm_i915_private *dev_priv = dev->dev_private;
 630         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 631         int instp_mode;
 632         u32 instp_mask;
 633         int ret;
 634
 635         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
 636         instp_mask = I915_EXEC_CONSTANTS_MASK;
 637         switch (instp_mode) {
 638         case I915_EXEC_CONSTANTS_REL_GENERAL:
 639         case I915_EXEC_CONSTANTS_ABSOLUTE:
 640         case I915_EXEC_CONSTANTS_REL_SURFACE:
 641                 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
 642                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
 643                         return -EINVAL;
 644                 }
 645
 646                 if (instp_mode != dev_priv->relative_constants_mode) {
 647                         if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
 648                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
 649                                 return -EINVAL;
 650                         }
 651
 652                         /* The HW changed the meaning on this bit on gen6 */
 653                         instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
 654                 }
 655                 break;
 656         default:
 657                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
 658                 return -EINVAL;
 659         }
 660
 661         if (args->num_cliprects != 0) {
 662                 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
 663                 return -EINVAL;
 664         } else {
 665                 if (args->DR4 == 0xffffffff) {
 666                         DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
 667                         args->DR4 = 0;
 668                 }
 669
 670                 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
 671                         DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
 672                         return -EINVAL;
 673                 }
 674         }
 675
 676         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
 677                 DRM_DEBUG("sol reset is gen7 only\n");
 678                 return -EINVAL;
 679         }
 680
 681         ret = execlists_move_to_gpu(ringbuf, ctx, vmas);
 682         if (ret)
 683                 return ret;
 684
 685         if (ring == &dev_priv->ring[RCS] &&
 686             instp_mode != dev_priv->relative_constants_mode) {
 687                 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
 688                 if (ret)
 689                         return ret;
 690
 691                 intel_logical_ring_emit(ringbuf, MI_NOOP);
 692                 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
 693                 intel_logical_ring_emit(ringbuf, INSTPM);
 694                 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
 695                 intel_logical_ring_advance(ringbuf);
 696
 697                 dev_priv->relative_constants_mode = instp_mode;
 698         }
 699
 700         ret = ring->emit_bb_start(ringbuf, ctx, exec_start, flags);
 701         if (ret)
 702                 return ret;
 703
 704         i915_gem_execbuffer_move_to_active(vmas, ring);
 705         i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
 706
 707         return 0;
 708 }
 709
 710 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
 711 {
 712         struct drm_i915_gem_request *req, *tmp;
 713         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 714         unsigned long flags;
 715         struct list_head retired_list;
 716
 717         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 718         if (list_empty(&ring->execlist_retired_req_list))
 719                 return;
 720
 721         INIT_LIST_HEAD(&retired_list);
 722         spin_lock_irqsave(&ring->execlist_lock, flags);
 723         list_replace_init(&ring->execlist_retired_req_list, &retired_list);
 724         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 725
 726         list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
 727                 struct intel_context *ctx = req->ctx;
 728                 struct drm_i915_gem_object *ctx_obj =
 729                                 ctx->engine[ring->id].state;
 730
 731                 if (ctx_obj && (ctx != ring->default_context))
 732                         intel_lr_context_unpin(ring, ctx);
 733                 intel_runtime_pm_put(dev_priv);
 734                 i915_gem_context_unreference(ctx);
 735                 list_del(&req->execlist_link);
 736                 i915_gem_request_unreference(req);
 737         }
 738 }
 739
 740 void intel_logical_ring_stop(struct intel_engine_cs *ring)
 741 {
 742         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 743         int ret;
 744
 745         if (!intel_ring_initialized(ring))
 746                 return;
 747
 748         ret = intel_ring_idle(ring);
 749         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
 750                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 751                           ring->name, ret);
 752
 753         /* TODO: Is this correct with Execlists enabled? */
 754         I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 755         if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 756                 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 757                 return;
 758         }
 759         I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 760 }
 761
 762 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
 763                                   struct intel_context *ctx)
 764 {
 765         struct intel_engine_cs *ring = ringbuf->ring;
 766         int ret;
 767
 768         if (!ring->gpu_caches_dirty)
 769                 return 0;
 770
 771         ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS);
 772         if (ret)
 773                 return ret;
 774
 775         ring->gpu_caches_dirty = false;
 776         return 0;
 777 }
 778
 779 /**
 780  * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
 781  * @ringbuf: Logical Ringbuffer to advance.
 782  *
 783  * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 784  * really happens during submission is that the context and current tail will be placed
 785  * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 786  * point, the tail *inside* the context is updated and the ELSP written to.
 787  */
 788 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
 789                                            struct intel_context *ctx,
 790                                            struct drm_i915_gem_request *request)
 791 {
 792         struct intel_engine_cs *ring = ringbuf->ring;
 793
 794         intel_logical_ring_advance(ringbuf);
 795
 796         if (intel_ring_stopped(ring))
 797                 return;
 798
 799         execlists_context_queue(ring, ctx, ringbuf->tail, request);
 800 }
 801
 802 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 803                 struct intel_context *ctx)
 804 {
 805         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 806         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 807         int ret = 0;
 808
 809         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 810         if (ctx->engine[ring->id].pin_count++ == 0) {
 811                 ret = i915_gem_obj_ggtt_pin(ctx_obj,
 812                                 GEN8_LR_CONTEXT_ALIGN, 0);
 813                 if (ret)
 814                         goto reset_pin_count;
 815
 816                 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
 817                 if (ret)
 818                         goto unpin_ctx_obj;
 819         }
 820
 821         return ret;
 822
 823 unpin_ctx_obj:
 824         i915_gem_object_ggtt_unpin(ctx_obj);
 825 reset_pin_count:
 826         ctx->engine[ring->id].pin_count = 0;
 827
 828         return ret;
 829 }
 830
 831 void intel_lr_context_unpin(struct intel_engine_cs *ring,
 832                 struct intel_context *ctx)
 833 {
 834         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 835         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 836
 837         if (ctx_obj) {
 838                 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 839                 if (--ctx->engine[ring->id].pin_count == 0) {
 840                         intel_unpin_ringbuffer_obj(ringbuf);
 841                         i915_gem_object_ggtt_unpin(ctx_obj);
 842                 }
 843         }
 844 }
 845
 846 static int logical_ring_alloc_request(struct intel_engine_cs *ring,
 847                                       struct intel_context *ctx)
 848 {
 849         struct drm_i915_gem_request *request;
 850         struct drm_i915_private *dev_private = ring->dev->dev_private;
 851         int ret;
 852
 853         if (ring->outstanding_lazy_request)
 854                 return 0;
 855
 856         request = kzalloc(sizeof(*request), GFP_KERNEL);
 857         if (request == NULL)
 858                 return -ENOMEM;
 859
 860         if (ctx != ring->default_context) {
 861                 ret = intel_lr_context_pin(ring, ctx);
 862                 if (ret) {
 863                         kfree(request);
 864                         return ret;
 865                 }
 866         }
 867
 868         kref_init(&request->ref);
 869         request->ring = ring;
 870         request->uniq = dev_private->request_uniq++;
 871
 872         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
 873         if (ret) {
 874                 intel_lr_context_unpin(ring, ctx);
 875                 kfree(request);
 876                 return ret;
 877         }
 878
 879         /* Hold a reference to the context this request belongs to
 880          * (we will need it when the time comes to emit/retire the
 881          * request).
 882          */
 883         request->ctx = ctx;
 884         i915_gem_context_reference(request->ctx);
 885
 886         ring->outstanding_lazy_request = request;
 887         return 0;
 888 }
 889
 890 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
 891                                      int bytes)
 892 {
 893         struct intel_engine_cs *ring = ringbuf->ring;
 894         struct drm_i915_gem_request *request;
 895         int ret;
 896
 897         if (intel_ring_space(ringbuf) >= bytes)
 898                 return 0;
 899
 900         list_for_each_entry(request, &ring->request_list, list) {
 901                 /*
 902                  * The request queue is per-engine, so can contain requests
 903                  * from multiple ringbuffers. Here, we must ignore any that
 904                  * aren't from the ringbuffer we're considering.
 905                  */
 906                 struct intel_context *ctx = request->ctx;
 907                 if (ctx->engine[ring->id].ringbuf != ringbuf)
 908                         continue;
 909
 910                 /* Would completion of this request free enough space? */
 911                 if (__intel_ring_space(request->tail, ringbuf->tail,
 912                                        ringbuf->size) >= bytes) {
 913                         break;
 914                 }
 915         }
 916
 917         if (&request->list == &ring->request_list)
 918                 return -ENOSPC;
 919
 920         ret = i915_wait_request(request);
 921         if (ret)
 922                 return ret;
 923
 924         i915_gem_retire_requests_ring(ring);
 925
 926         return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC;
 927 }
 928
 929 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
 930                                        struct intel_context *ctx,
 931                                        int bytes)
 932 {
 933         struct intel_engine_cs *ring = ringbuf->ring;
 934         struct drm_device *dev = ring->dev;
 935         struct drm_i915_private *dev_priv = dev->dev_private;
 936         unsigned long end;
 937         int ret;
 938
 939         ret = logical_ring_wait_request(ringbuf, bytes);
 940         if (ret != -ENOSPC)
 941                 return ret;
 942
 943         /* Force the context submission in case we have been skipping it */
 944         intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL);
 945
 946         /* With GEM the hangcheck timer should kick us out of the loop,
 947          * leaving it early runs the risk of corrupting GEM state (due
 948          * to running on almost untested codepaths). But on resume
 949          * timers don't work yet, so prevent a complete hang in that
 950          * case by choosing an insanely large timeout. */
 951         end = jiffies + 60 * HZ;
 952
 953         ret = 0;
 954         do {
 955                 if (intel_ring_space(ringbuf) >= bytes)
 956                         break;
 957
 958                 msleep(1);
 959
 960                 if (dev_priv->mm.interruptible && signal_pending(current)) {
 961                         ret = -ERESTARTSYS;
 962                         break;
 963                 }
 964
 965                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
 966                                            dev_priv->mm.interruptible);
 967                 if (ret)
 968                         break;
 969
 970                 if (time_after(jiffies, end)) {
 971                         ret = -EBUSY;
 972                         break;
 973                 }
 974         } while (1);
 975
 976         return ret;
 977 }
 978
 979 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
 980                                     struct intel_context *ctx)
 981 {
 982         uint32_t __iomem *virt;
 983         int rem = ringbuf->size - ringbuf->tail;
 984
 985         if (ringbuf->space < rem) {
 986                 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
 987
 988                 if (ret)
 989                         return ret;
 990         }
 991
 992         virt = ringbuf->virtual_start + ringbuf->tail;
 993         rem /= 4;
 994         while (rem--)
 995                 iowrite32(MI_NOOP, virt++);
 996
 997         ringbuf->tail = 0;
 998         intel_ring_update_space(ringbuf);
 999
1000         return 0;
1001 }
1002
1003 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
1004                                 struct intel_context *ctx, int bytes)
1005 {
1006         int ret;
1007
1008         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1009                 ret = logical_ring_wrap_buffer(ringbuf, ctx);
1010                 if (unlikely(ret))
1011                         return ret;
1012         }
1013
1014         if (unlikely(ringbuf->space < bytes)) {
1015                 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
1016                 if (unlikely(ret))
1017                         return ret;
1018         }
1019
1020         return 0;
1021 }
1022
1023 /**
1024  * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1025  *
1026  * @ringbuf: Logical ringbuffer.
1027  * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1028  *
1029  * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1030  * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1031  * and also preallocates a request (every workload submission is still mediated through
1032  * requests, same as it did with legacy ringbuffer submission).
1033  *
1034  * Return: non-zero if the ringbuffer is not ready to be written to.
1035  */
1036 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
1037                              struct intel_context *ctx, int num_dwords)
1038 {
1039         struct intel_engine_cs *ring = ringbuf->ring;
1040         struct drm_device *dev = ring->dev;
1041         struct drm_i915_private *dev_priv = dev->dev_private;
1042         int ret;
1043
1044         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1045                                    dev_priv->mm.interruptible);
1046         if (ret)
1047                 return ret;
1048
1049         ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
1050         if (ret)
1051                 return ret;
1052
1053         /* Preallocate the olr before touching the ring */
1054         ret = logical_ring_alloc_request(ring, ctx);
1055         if (ret)
1056                 return ret;
1057
1058         ringbuf->space -= num_dwords * sizeof(uint32_t);
1059         return 0;
1060 }
1061
1062 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1063                                                struct intel_context *ctx)
1064 {
1065         int ret, i;
1066         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1067         struct drm_device *dev = ring->dev;
1068         struct drm_i915_private *dev_priv = dev->dev_private;
1069         struct i915_workarounds *w = &dev_priv->workarounds;
1070
1071         if (WARN_ON_ONCE(w->count == 0))
1072                 return 0;
1073
1074         ring->gpu_caches_dirty = true;
1075         ret = logical_ring_flush_all_caches(ringbuf, ctx);
1076         if (ret)
1077                 return ret;
1078
1079         ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2);
1080         if (ret)
1081                 return ret;
1082
1083         intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1084         for (i = 0; i < w->count; i++) {
1085                 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1086                 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1087         }
1088         intel_logical_ring_emit(ringbuf, MI_NOOP);
1089
1090         intel_logical_ring_advance(ringbuf);
1091
1092         ring->gpu_caches_dirty = true;
1093         ret = logical_ring_flush_all_caches(ringbuf, ctx);
1094         if (ret)
1095                 return ret;
1096
1097         return 0;
1098 }
1099
1100 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1101 {
1102         struct drm_device *dev = ring->dev;
1103         struct drm_i915_private *dev_priv = dev->dev_private;
1104
1105         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1106         I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1107
1108         I915_WRITE(RING_MODE_GEN7(ring),
1109                    _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1110                    _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1111         POSTING_READ(RING_MODE_GEN7(ring));
1112         ring->next_context_status_buffer = 0;
1113         DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1114
1115         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1116
1117         return 0;
1118 }
1119
1120 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1121 {
1122         struct drm_device *dev = ring->dev;
1123         struct drm_i915_private *dev_priv = dev->dev_private;
1124         int ret;
1125
1126         ret = gen8_init_common_ring(ring);
1127         if (ret)
1128                 return ret;
1129
1130         /* We need to disable the AsyncFlip performance optimisations in order
1131          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1132          * programmed to '1' on all products.
1133          *
1134          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1135          */
1136         I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1137
1138         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1139
1140         return init_workarounds_ring(ring);
1141 }
1142
1143 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1144                               struct intel_context *ctx,
1145                               u64 offset, unsigned flags)
1146 {
1147         bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1148         int ret;
1149
1150         ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1151         if (ret)
1152                 return ret;
1153
1154         /* FIXME(BDW): Address space and security selectors. */
1155         intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1156         intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1157         intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1158         intel_logical_ring_emit(ringbuf, MI_NOOP);
1159         intel_logical_ring_advance(ringbuf);
1160
1161         return 0;
1162 }
1163
1164 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1165 {
1166         struct drm_device *dev = ring->dev;
1167         struct drm_i915_private *dev_priv = dev->dev_private;
1168         unsigned long flags;
1169
1170         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1171                 return false;
1172
1173         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1174         if (ring->irq_refcount++ == 0) {
1175                 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1176                 POSTING_READ(RING_IMR(ring->mmio_base));
1177         }
1178         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1179
1180         return true;
1181 }
1182
1183 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1184 {
1185         struct drm_device *dev = ring->dev;
1186         struct drm_i915_private *dev_priv = dev->dev_private;
1187         unsigned long flags;
1188
1189         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1190         if (--ring->irq_refcount == 0) {
1191                 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1192                 POSTING_READ(RING_IMR(ring->mmio_base));
1193         }
1194         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1195 }
1196
1197 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1198                            struct intel_context *ctx,
1199                            u32 invalidate_domains,
1200                            u32 unused)
1201 {
1202         struct intel_engine_cs *ring = ringbuf->ring;
1203         struct drm_device *dev = ring->dev;
1204         struct drm_i915_private *dev_priv = dev->dev_private;
1205         uint32_t cmd;
1206         int ret;
1207
1208         ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1209         if (ret)
1210                 return ret;
1211
1212         cmd = MI_FLUSH_DW + 1;
1213
1214         /* We always require a command barrier so that subsequent
1215          * commands, such as breadcrumb interrupts, are strictly ordered
1216          * wrt the contents of the write cache being flushed to memory
1217          * (and thus being coherent from the CPU).
1218          */
1219         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1220
1221         if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1222                 cmd |= MI_INVALIDATE_TLB;
1223                 if (ring == &dev_priv->ring[VCS])
1224                         cmd |= MI_INVALIDATE_BSD;
1225         }
1226
1227         intel_logical_ring_emit(ringbuf, cmd);
1228         intel_logical_ring_emit(ringbuf,
1229                                 I915_GEM_HWS_SCRATCH_ADDR |
1230                                 MI_FLUSH_DW_USE_GTT);
1231         intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1232         intel_logical_ring_emit(ringbuf, 0); /* value */
1233         intel_logical_ring_advance(ringbuf);
1234
1235         return 0;
1236 }
1237
1238 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1239                                   struct intel_context *ctx,
1240                                   u32 invalidate_domains,
1241                                   u32 flush_domains)
1242 {
1243         struct intel_engine_cs *ring = ringbuf->ring;
1244         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1245         u32 flags = 0;
1246         int ret;
1247
1248         flags |= PIPE_CONTROL_CS_STALL;
1249
1250         if (flush_domains) {
1251                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1252                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1253         }
1254
1255         if (invalidate_domains) {
1256                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1257                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1258                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1259                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1260                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1261                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1262                 flags |= PIPE_CONTROL_QW_WRITE;
1263                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1264         }
1265
1266         ret = intel_logical_ring_begin(ringbuf, ctx, 6);
1267         if (ret)
1268                 return ret;
1269
1270         intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1271         intel_logical_ring_emit(ringbuf, flags);
1272         intel_logical_ring_emit(ringbuf, scratch_addr);
1273         intel_logical_ring_emit(ringbuf, 0);
1274         intel_logical_ring_emit(ringbuf, 0);
1275         intel_logical_ring_emit(ringbuf, 0);
1276         intel_logical_ring_advance(ringbuf);
1277
1278         return 0;
1279 }
1280
1281 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1282 {
1283         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1284 }
1285
1286 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1287 {
1288         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1289 }
1290
1291 static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1292                              struct drm_i915_gem_request *request)
1293 {
1294         struct intel_engine_cs *ring = ringbuf->ring;
1295         u32 cmd;
1296         int ret;
1297
1298         ret = intel_logical_ring_begin(ringbuf, request->ctx, 6);
1299         if (ret)
1300                 return ret;
1301
1302         cmd = MI_STORE_DWORD_IMM_GEN4;
1303         cmd |= MI_GLOBAL_GTT;
1304
1305         intel_logical_ring_emit(ringbuf, cmd);
1306         intel_logical_ring_emit(ringbuf,
1307                                 (ring->status_page.gfx_addr +
1308                                 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1309         intel_logical_ring_emit(ringbuf, 0);
1310         intel_logical_ring_emit(ringbuf,
1311                 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1312         intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1313         intel_logical_ring_emit(ringbuf, MI_NOOP);
1314         intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
1315
1316         return 0;
1317 }
1318
1319 static int gen8_init_rcs_context(struct intel_engine_cs *ring,
1320                        struct intel_context *ctx)
1321 {
1322         int ret;
1323
1324         ret = intel_logical_ring_workarounds_emit(ring, ctx);
1325         if (ret)
1326                 return ret;
1327
1328         return intel_lr_context_render_state_init(ring, ctx);
1329 }
1330
1331 /**
1332  * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1333  *
1334  * @ring: Engine Command Streamer.
1335  *
1336  */
1337 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1338 {
1339         struct drm_i915_private *dev_priv;
1340
1341         if (!intel_ring_initialized(ring))
1342                 return;
1343
1344         dev_priv = ring->dev->dev_private;
1345
1346         intel_logical_ring_stop(ring);
1347         WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1348         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1349
1350         if (ring->cleanup)
1351                 ring->cleanup(ring);
1352
1353         i915_cmd_parser_fini_ring(ring);
1354
1355         if (ring->status_page.obj) {
1356                 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1357                 ring->status_page.obj = NULL;
1358         }
1359 }
1360
1361 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1362 {
1363         int ret;
1364
1365         /* Intentionally left blank. */
1366         ring->buffer = NULL;
1367
1368         ring->dev = dev;
1369         INIT_LIST_HEAD(&ring->active_list);
1370         INIT_LIST_HEAD(&ring->request_list);
1371         init_waitqueue_head(&ring->irq_queue);
1372
1373         INIT_LIST_HEAD(&ring->execlist_queue);
1374         INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1375         spin_lock_init(&ring->execlist_lock);
1376
1377         ret = i915_cmd_parser_init_ring(ring);
1378         if (ret)
1379                 return ret;
1380
1381         ret = intel_lr_context_deferred_create(ring->default_context, ring);
1382
1383         return ret;
1384 }
1385
1386 static int logical_render_ring_init(struct drm_device *dev)
1387 {
1388         struct drm_i915_private *dev_priv = dev->dev_private;
1389         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1390         int ret;
1391
1392         ring->name = "render ring";
1393         ring->id = RCS;
1394         ring->mmio_base = RENDER_RING_BASE;
1395         ring->irq_enable_mask =
1396                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1397         ring->irq_keep_mask =
1398                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1399         if (HAS_L3_DPF(dev))
1400                 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1401
1402         ring->init_hw = gen8_init_render_ring;
1403         ring->init_context = gen8_init_rcs_context;
1404         ring->cleanup = intel_fini_pipe_control;
1405         ring->get_seqno = gen8_get_seqno;
1406         ring->set_seqno = gen8_set_seqno;
1407         ring->emit_request = gen8_emit_request;
1408         ring->emit_flush = gen8_emit_flush_render;
1409         ring->irq_get = gen8_logical_ring_get_irq;
1410         ring->irq_put = gen8_logical_ring_put_irq;
1411         ring->emit_bb_start = gen8_emit_bb_start;
1412
1413         ring->dev = dev;
1414         ret = logical_ring_init(dev, ring);
1415         if (ret)
1416                 return ret;
1417
1418         return intel_init_pipe_control(ring);
1419 }
1420
1421 static int logical_bsd_ring_init(struct drm_device *dev)
1422 {
1423         struct drm_i915_private *dev_priv = dev->dev_private;
1424         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1425
1426         ring->name = "bsd ring";
1427         ring->id = VCS;
1428         ring->mmio_base = GEN6_BSD_RING_BASE;
1429         ring->irq_enable_mask =
1430                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1431         ring->irq_keep_mask =
1432                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1433
1434         ring->init_hw = gen8_init_common_ring;
1435         ring->get_seqno = gen8_get_seqno;
1436         ring->set_seqno = gen8_set_seqno;
1437         ring->emit_request = gen8_emit_request;
1438         ring->emit_flush = gen8_emit_flush;
1439         ring->irq_get = gen8_logical_ring_get_irq;
1440         ring->irq_put = gen8_logical_ring_put_irq;
1441         ring->emit_bb_start = gen8_emit_bb_start;
1442
1443         return logical_ring_init(dev, ring);
1444 }
1445
1446 static int logical_bsd2_ring_init(struct drm_device *dev)
1447 {
1448         struct drm_i915_private *dev_priv = dev->dev_private;
1449         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1450
1451         ring->name = "bds2 ring";
1452         ring->id = VCS2;
1453         ring->mmio_base = GEN8_BSD2_RING_BASE;
1454         ring->irq_enable_mask =
1455                 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1456         ring->irq_keep_mask =
1457                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1458
1459         ring->init_hw = gen8_init_common_ring;
1460         ring->get_seqno = gen8_get_seqno;
1461         ring->set_seqno = gen8_set_seqno;
1462         ring->emit_request = gen8_emit_request;
1463         ring->emit_flush = gen8_emit_flush;
1464         ring->irq_get = gen8_logical_ring_get_irq;
1465         ring->irq_put = gen8_logical_ring_put_irq;
1466         ring->emit_bb_start = gen8_emit_bb_start;
1467
1468         return logical_ring_init(dev, ring);
1469 }
1470
1471 static int logical_blt_ring_init(struct drm_device *dev)
1472 {
1473         struct drm_i915_private *dev_priv = dev->dev_private;
1474         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1475
1476         ring->name = "blitter ring";
1477         ring->id = BCS;
1478         ring->mmio_base = BLT_RING_BASE;
1479         ring->irq_enable_mask =
1480                 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1481         ring->irq_keep_mask =
1482                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1483
1484         ring->init_hw = gen8_init_common_ring;
1485         ring->get_seqno = gen8_get_seqno;
1486         ring->set_seqno = gen8_set_seqno;
1487         ring->emit_request = gen8_emit_request;
1488         ring->emit_flush = gen8_emit_flush;
1489         ring->irq_get = gen8_logical_ring_get_irq;
1490         ring->irq_put = gen8_logical_ring_put_irq;
1491         ring->emit_bb_start = gen8_emit_bb_start;
1492
1493         return logical_ring_init(dev, ring);
1494 }
1495
1496 static int logical_vebox_ring_init(struct drm_device *dev)
1497 {
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1500
1501         ring->name = "video enhancement ring";
1502         ring->id = VECS;
1503         ring->mmio_base = VEBOX_RING_BASE;
1504         ring->irq_enable_mask =
1505                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1506         ring->irq_keep_mask =
1507                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1508
1509         ring->init_hw = gen8_init_common_ring;
1510         ring->get_seqno = gen8_get_seqno;
1511         ring->set_seqno = gen8_set_seqno;
1512         ring->emit_request = gen8_emit_request;
1513         ring->emit_flush = gen8_emit_flush;
1514         ring->irq_get = gen8_logical_ring_get_irq;
1515         ring->irq_put = gen8_logical_ring_put_irq;
1516         ring->emit_bb_start = gen8_emit_bb_start;
1517
1518         return logical_ring_init(dev, ring);
1519 }
1520
1521 /**
1522  * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1523  * @dev: DRM device.
1524  *
1525  * This function inits the engines for an Execlists submission style (the equivalent in the
1526  * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1527  * those engines that are present in the hardware.
1528  *
1529  * Return: non-zero if the initialization failed.
1530  */
1531 int intel_logical_rings_init(struct drm_device *dev)
1532 {
1533         struct drm_i915_private *dev_priv = dev->dev_private;
1534         int ret;
1535
1536         ret = logical_render_ring_init(dev);
1537         if (ret)
1538                 return ret;
1539
1540         if (HAS_BSD(dev)) {
1541                 ret = logical_bsd_ring_init(dev);
1542                 if (ret)
1543                         goto cleanup_render_ring;
1544         }
1545
1546         if (HAS_BLT(dev)) {
1547                 ret = logical_blt_ring_init(dev);
1548                 if (ret)
1549                         goto cleanup_bsd_ring;
1550         }
1551
1552         if (HAS_VEBOX(dev)) {
1553                 ret = logical_vebox_ring_init(dev);
1554                 if (ret)
1555                         goto cleanup_blt_ring;
1556         }
1557
1558         if (HAS_BSD2(dev)) {
1559                 ret = logical_bsd2_ring_init(dev);
1560                 if (ret)
1561                         goto cleanup_vebox_ring;
1562         }
1563
1564         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1565         if (ret)
1566                 goto cleanup_bsd2_ring;
1567
1568         return 0;
1569
1570 cleanup_bsd2_ring:
1571         intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1572 cleanup_vebox_ring:
1573         intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1574 cleanup_blt_ring:
1575         intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1576 cleanup_bsd_ring:
1577         intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1578 cleanup_render_ring:
1579         intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1580
1581         return ret;
1582 }
1583
1584 int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1585                                        struct intel_context *ctx)
1586 {
1587         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1588         struct render_state so;
1589         struct drm_i915_file_private *file_priv = ctx->file_priv;
1590         struct drm_file *file = file_priv ? file_priv->file : NULL;
1591         int ret;
1592
1593         ret = i915_gem_render_state_prepare(ring, &so);
1594         if (ret)
1595                 return ret;
1596
1597         if (so.rodata == NULL)
1598                 return 0;
1599
1600         ret = ring->emit_bb_start(ringbuf,
1601                         ctx,
1602                         so.ggtt_offset,
1603                         I915_DISPATCH_SECURE);
1604         if (ret)
1605                 goto out;
1606
1607         i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1608
1609         ret = __i915_add_request(ring, file, so.obj);
1610         /* intel_logical_ring_add_request moves object to inactive if it
1611          * fails */
1612 out:
1613         i915_gem_render_state_fini(&so);
1614         return ret;
1615 }
1616
1617 static int
1618 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1619                     struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1620 {
1621         struct drm_device *dev = ring->dev;
1622         struct drm_i915_private *dev_priv = dev->dev_private;
1623         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1624         struct page *page;
1625         uint32_t *reg_state;
1626         int ret;
1627
1628         if (!ppgtt)
1629                 ppgtt = dev_priv->mm.aliasing_ppgtt;
1630
1631         ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1632         if (ret) {
1633                 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1634                 return ret;
1635         }
1636
1637         ret = i915_gem_object_get_pages(ctx_obj);
1638         if (ret) {
1639                 DRM_DEBUG_DRIVER("Could not get object pages\n");
1640                 return ret;
1641         }
1642
1643         i915_gem_object_pin_pages(ctx_obj);
1644
1645         /* The second page of the context object contains some fields which must
1646          * be set up prior to the first execution. */
1647         page = i915_gem_object_get_page(ctx_obj, 1);
1648         reg_state = kmap_atomic(page);
1649
1650         /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1651          * commands followed by (reg, value) pairs. The values we are setting here are
1652          * only for the first context restore: on a subsequent save, the GPU will
1653          * recreate this batchbuffer with new values (including all the missing
1654          * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1655         if (ring->id == RCS)
1656                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1657         else
1658                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1659         reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1660         reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1661         reg_state[CTX_CONTEXT_CONTROL+1] =
1662                         _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
1663         reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1664         reg_state[CTX_RING_HEAD+1] = 0;
1665         reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1666         reg_state[CTX_RING_TAIL+1] = 0;
1667         reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1668         /* Ring buffer start address is not known until the buffer is pinned.
1669          * It is written to the context image in execlists_update_context()
1670          */
1671         reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1672         reg_state[CTX_RING_BUFFER_CONTROL+1] =
1673                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1674         reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1675         reg_state[CTX_BB_HEAD_U+1] = 0;
1676         reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1677         reg_state[CTX_BB_HEAD_L+1] = 0;
1678         reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1679         reg_state[CTX_BB_STATE+1] = (1<<5);
1680         reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1681         reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1682         reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1683         reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1684         reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1685         reg_state[CTX_SECOND_BB_STATE+1] = 0;
1686         if (ring->id == RCS) {
1687                 /* TODO: according to BSpec, the register state context
1688                  * for CHV does not have these. OTOH, these registers do
1689                  * exist in CHV. I'm waiting for a clarification */
1690                 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1691                 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1692                 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1693                 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1694                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1695                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1696         }
1697         reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1698         reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1699         reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1700         reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1701         reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1702         reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1703         reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1704         reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1705         reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1706         reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1707         reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1708         reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1709         reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
1710         reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
1711         reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
1712         reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
1713         reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
1714         reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
1715         reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
1716         reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
1717         if (ring->id == RCS) {
1718                 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1719                 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
1720                 reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
1721         }
1722
1723         kunmap_atomic(reg_state);
1724
1725         ctx_obj->dirty = 1;
1726         set_page_dirty(page);
1727         i915_gem_object_unpin_pages(ctx_obj);
1728
1729         return 0;
1730 }
1731
1732 /**
1733  * intel_lr_context_free() - free the LRC specific bits of a context
1734  * @ctx: the LR context to free.
1735  *
1736  * The real context freeing is done in i915_gem_context_free: this only
1737  * takes care of the bits that are LRC related: the per-engine backing
1738  * objects and the logical ringbuffer.
1739  */
1740 void intel_lr_context_free(struct intel_context *ctx)
1741 {
1742         int i;
1743
1744         for (i = 0; i < I915_NUM_RINGS; i++) {
1745                 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1746
1747                 if (ctx_obj) {
1748                         struct intel_ringbuffer *ringbuf =
1749                                         ctx->engine[i].ringbuf;
1750                         struct intel_engine_cs *ring = ringbuf->ring;
1751
1752                         if (ctx == ring->default_context) {
1753                                 intel_unpin_ringbuffer_obj(ringbuf);
1754                                 i915_gem_object_ggtt_unpin(ctx_obj);
1755                         }
1756                         WARN_ON(ctx->engine[ring->id].pin_count);
1757                         intel_destroy_ringbuffer_obj(ringbuf);
1758                         kfree(ringbuf);
1759                         drm_gem_object_unreference(&ctx_obj->base);
1760                 }
1761         }
1762 }
1763
1764 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1765 {
1766         int ret = 0;
1767
1768         WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1769
1770         switch (ring->id) {
1771         case RCS:
1772                 if (INTEL_INFO(ring->dev)->gen >= 9)
1773                         ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1774                 else
1775                         ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1776                 break;
1777         case VCS:
1778         case BCS:
1779         case VECS:
1780         case VCS2:
1781                 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1782                 break;
1783         }
1784
1785         return ret;
1786 }
1787
1788 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1789                 struct drm_i915_gem_object *default_ctx_obj)
1790 {
1791         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1792
1793         /* The status page is offset 0 from the default context object
1794          * in LRC mode. */
1795         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1796         ring->status_page.page_addr =
1797                         kmap(sg_page(default_ctx_obj->pages->sgl));
1798         ring->status_page.obj = default_ctx_obj;
1799
1800         I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1801                         (u32)ring->status_page.gfx_addr);
1802         POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1803 }
1804
1805 /**
1806  * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1807  * @ctx: LR context to create.
1808  * @ring: engine to be used with the context.
1809  *
1810  * This function can be called more than once, with different engines, if we plan
1811  * to use the context with them. The context backing objects and the ringbuffers
1812  * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1813  * the creation is a deferred call: it's better to make sure first that we need to use
1814  * a given ring with the context.
1815  *
1816  * Return: non-zero on error.
1817  */
1818 int intel_lr_context_deferred_create(struct intel_context *ctx,
1819                                      struct intel_engine_cs *ring)
1820 {
1821         const bool is_global_default_ctx = (ctx == ring->default_context);
1822         struct drm_device *dev = ring->dev;
1823         struct drm_i915_gem_object *ctx_obj;
1824         uint32_t context_size;
1825         struct intel_ringbuffer *ringbuf;
1826         int ret;
1827
1828         WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1829         WARN_ON(ctx->engine[ring->id].state);
1830
1831         context_size = round_up(get_lr_context_size(ring), 4096);
1832
1833         ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1834         if (IS_ERR(ctx_obj)) {
1835                 ret = PTR_ERR(ctx_obj);
1836                 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1837                 return ret;
1838         }
1839
1840         if (is_global_default_ctx) {
1841                 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1842                 if (ret) {
1843                         DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1844                                         ret);
1845                         drm_gem_object_unreference(&ctx_obj->base);
1846                         return ret;
1847                 }
1848         }
1849
1850         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1851         if (!ringbuf) {
1852                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1853                                 ring->name);
1854                 ret = -ENOMEM;
1855                 goto error_unpin_ctx;
1856         }
1857
1858         ringbuf->ring = ring;
1859
1860         ringbuf->size = 32 * PAGE_SIZE;
1861         ringbuf->effective_size = ringbuf->size;
1862         ringbuf->head = 0;
1863         ringbuf->tail = 0;
1864         ringbuf->last_retired_head = -1;
1865         intel_ring_update_space(ringbuf);
1866
1867         if (ringbuf->obj == NULL) {
1868                 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1869                 if (ret) {
1870                         DRM_DEBUG_DRIVER(
1871                                 "Failed to allocate ringbuffer obj %s: %d\n",
1872                                 ring->name, ret);
1873                         goto error_free_rbuf;
1874                 }
1875
1876                 if (is_global_default_ctx) {
1877                         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1878                         if (ret) {
1879                                 DRM_ERROR(
1880                                         "Failed to pin and map ringbuffer %s: %d\n",
1881                                         ring->name, ret);
1882                                 goto error_destroy_rbuf;
1883                         }
1884                 }
1885
1886         }
1887
1888         ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1889         if (ret) {
1890                 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1891                 goto error;
1892         }
1893
1894         ctx->engine[ring->id].ringbuf = ringbuf;
1895         ctx->engine[ring->id].state = ctx_obj;
1896
1897         if (ctx == ring->default_context)
1898                 lrc_setup_hardware_status_page(ring, ctx_obj);
1899         else if (ring->id == RCS && !ctx->rcs_initialized) {
1900                 if (ring->init_context) {
1901                         ret = ring->init_context(ring, ctx);
1902                         if (ret) {
1903                                 DRM_ERROR("ring init context: %d\n", ret);
1904                                 ctx->engine[ring->id].ringbuf = NULL;
1905                                 ctx->engine[ring->id].state = NULL;
1906                                 goto error;
1907                         }
1908                 }
1909
1910                 ctx->rcs_initialized = true;
1911         }
1912
1913         return 0;
1914
1915 error:
1916         if (is_global_default_ctx)
1917                 intel_unpin_ringbuffer_obj(ringbuf);
1918 error_destroy_rbuf:
1919         intel_destroy_ringbuffer_obj(ringbuf);
1920 error_free_rbuf:
1921         kfree(ringbuf);
1922 error_unpin_ctx:
1923         if (is_global_default_ctx)
1924                 i915_gem_object_ggtt_unpin(ctx_obj);
1925         drm_gem_object_unreference(&ctx_obj->base);
1926         return ret;
1927 }