drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * RC6 is a special power stage which allows the GPU to enter an very
  36  * low-voltage mode when idle, using down to 0V while at this stage.  This
  37  * stage is entered automatically when the GPU is idle when RC6 support is
  38  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  39  *
  40  * There are different RC6 modes available in Intel GPU, which differentiate
  41  * among each other with the latency required to enter and leave RC6 and
  42  * voltage consumed by the GPU in different states.
  43  *
  44  * The combination of the following flags define which states GPU is allowed
  45  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  46  * RC6pp is deepest RC6. Their support by hardware varies according to the
  47  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  48  * which brings the most power savings; deeper states save more power, but
  49  * require higher latency to switch to and wake up.
  50  */
  51 #define INTEL_RC6_ENABLE                        (1<<0)
  52 #define INTEL_RC6p_ENABLE                       (1<<1)
  53 #define INTEL_RC6pp_ENABLE                      (1<<2)
  54
  55 static void gen9_init_clock_gating(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58
  59         /*
  60          * WaDisableSDEUnitClockGating:skl
  61          * This seems to be a pre-production w/a.
  62          */
  63         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  64                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  65
  66         /*
  67          * WaDisableDgMirrorFixInHalfSliceChicken5:skl
  68          * This is a pre-production w/a.
  69          */
  70         I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
  71                    I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
  72                    ~GEN9_DG_MIRROR_FIX_ENABLE);
  73
  74         /* Wa4x4STCOptimizationDisable:skl */
  75         I915_WRITE(CACHE_MODE_1,
  76                    _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
  77 }
  78
  79
  80 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  81 {
  82         struct drm_i915_private *dev_priv = dev->dev_private;
  83         u32 tmp;
  84
  85         tmp = I915_READ(CLKCFG);
  86
  87         switch (tmp & CLKCFG_FSB_MASK) {
  88         case CLKCFG_FSB_533:
  89                 dev_priv->fsb_freq = 533; /* 133*4 */
  90                 break;
  91         case CLKCFG_FSB_800:
  92                 dev_priv->fsb_freq = 800; /* 200*4 */
  93                 break;
  94         case CLKCFG_FSB_667:
  95                 dev_priv->fsb_freq =  667; /* 167*4 */
  96                 break;
  97         case CLKCFG_FSB_400:
  98                 dev_priv->fsb_freq = 400; /* 100*4 */
  99                 break;
 100         }
 101
 102         switch (tmp & CLKCFG_MEM_MASK) {
 103         case CLKCFG_MEM_533:
 104                 dev_priv->mem_freq = 533;
 105                 break;
 106         case CLKCFG_MEM_667:
 107                 dev_priv->mem_freq = 667;
 108                 break;
 109         case CLKCFG_MEM_800:
 110                 dev_priv->mem_freq = 800;
 111                 break;
 112         }
 113
 114         /* detect pineview DDR3 setting */
 115         tmp = I915_READ(CSHRDDR3CTL);
 116         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 117 }
 118
 119 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 120 {
 121         struct drm_i915_private *dev_priv = dev->dev_private;
 122         u16 ddrpll, csipll;
 123
 124         ddrpll = I915_READ16(DDRMPLL1);
 125         csipll = I915_READ16(CSIPLL0);
 126
 127         switch (ddrpll & 0xff) {
 128         case 0xc:
 129                 dev_priv->mem_freq = 800;
 130                 break;
 131         case 0x10:
 132                 dev_priv->mem_freq = 1066;
 133                 break;
 134         case 0x14:
 135                 dev_priv->mem_freq = 1333;
 136                 break;
 137         case 0x18:
 138                 dev_priv->mem_freq = 1600;
 139                 break;
 140         default:
 141                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 142                                  ddrpll & 0xff);
 143                 dev_priv->mem_freq = 0;
 144                 break;
 145         }
 146
 147         dev_priv->ips.r_t = dev_priv->mem_freq;
 148
 149         switch (csipll & 0x3ff) {
 150         case 0x00c:
 151                 dev_priv->fsb_freq = 3200;
 152                 break;
 153         case 0x00e:
 154                 dev_priv->fsb_freq = 3733;
 155                 break;
 156         case 0x010:
 157                 dev_priv->fsb_freq = 4266;
 158                 break;
 159         case 0x012:
 160                 dev_priv->fsb_freq = 4800;
 161                 break;
 162         case 0x014:
 163                 dev_priv->fsb_freq = 5333;
 164                 break;
 165         case 0x016:
 166                 dev_priv->fsb_freq = 5866;
 167                 break;
 168         case 0x018:
 169                 dev_priv->fsb_freq = 6400;
 170                 break;
 171         default:
 172                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 173                                  csipll & 0x3ff);
 174                 dev_priv->fsb_freq = 0;
 175                 break;
 176         }
 177
 178         if (dev_priv->fsb_freq == 3200) {
 179                 dev_priv->ips.c_m = 0;
 180         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 181                 dev_priv->ips.c_m = 1;
 182         } else {
 183                 dev_priv->ips.c_m = 2;
 184         }
 185 }
 186
 187 static const struct cxsr_latency cxsr_latency_table[] = {
 188         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 189         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 190         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 191         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 192         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 193
 194         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 195         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 196         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 197         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 198         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 199
 200         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 201         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 202         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 203         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 204         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 205
 206         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 207         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 208         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 209         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 210         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 211
 212         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 213         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 214         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 215         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 216         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 217
 218         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 219         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 220         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 221         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 222         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 223 };
 224
 225 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 226                                                          int is_ddr3,
 227                                                          int fsb,
 228                                                          int mem)
 229 {
 230         const struct cxsr_latency *latency;
 231         int i;
 232
 233         if (fsb == 0 || mem == 0)
 234                 return NULL;
 235
 236         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 237                 latency = &cxsr_latency_table[i];
 238                 if (is_desktop == latency->is_desktop &&
 239                     is_ddr3 == latency->is_ddr3 &&
 240                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 241                         return latency;
 242         }
 243
 244         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 245
 246         return NULL;
 247 }
 248
 249 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 250 {
 251         struct drm_device *dev = dev_priv->dev;
 252         u32 val;
 253
 254         if (IS_VALLEYVIEW(dev)) {
 255                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 256         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 257                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 258         } else if (IS_PINEVIEW(dev)) {
 259                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 260                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 261                 I915_WRITE(DSPFW3, val);
 262         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 263                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 264                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 265                 I915_WRITE(FW_BLC_SELF, val);
 266         } else if (IS_I915GM(dev)) {
 267                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 268                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 269                 I915_WRITE(INSTPM, val);
 270         } else {
 271                 return;
 272         }
 273
 274         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 275                       enable ? "enabled" : "disabled");
 276 }
 277
 278 /*
 279  * Latency for FIFO fetches is dependent on several factors:
 280  *   - memory configuration (speed, channels)
 281  *   - chipset
 282  *   - current MCH state
 283  * It can be fairly high in some situations, so here we assume a fairly
 284  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 285  * set this value too high, the FIFO will fetch frequently to stay full)
 286  * and power consumption (set it too low to save power and we might see
 287  * FIFO underruns and display "flicker").
 288  *
 289  * A value of 5us seems to be a good balance; safe for very low end
 290  * platforms but not overly aggressive on lower latency configs.
 291  */
 292 static const int pessimal_latency_ns = 5000;
 293
 294 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 295 {
 296         struct drm_i915_private *dev_priv = dev->dev_private;
 297         uint32_t dsparb = I915_READ(DSPARB);
 298         int size;
 299
 300         size = dsparb & 0x7f;
 301         if (plane)
 302                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 303
 304         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 305                       plane ? "B" : "A", size);
 306
 307         return size;
 308 }
 309
 310 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 311 {
 312         struct drm_i915_private *dev_priv = dev->dev_private;
 313         uint32_t dsparb = I915_READ(DSPARB);
 314         int size;
 315
 316         size = dsparb & 0x1ff;
 317         if (plane)
 318                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 319         size >>= 1; /* Convert to cachelines */
 320
 321         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 322                       plane ? "B" : "A", size);
 323
 324         return size;
 325 }
 326
 327 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 328 {
 329         struct drm_i915_private *dev_priv = dev->dev_private;
 330         uint32_t dsparb = I915_READ(DSPARB);
 331         int size;
 332
 333         size = dsparb & 0x7f;
 334         size >>= 2; /* Convert to cachelines */
 335
 336         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 337                       plane ? "B" : "A",
 338                       size);
 339
 340         return size;
 341 }
 342
 343 /* Pineview has different values for various configs */
 344 static const struct intel_watermark_params pineview_display_wm = {
 345         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 346         .max_wm = PINEVIEW_MAX_WM,
 347         .default_wm = PINEVIEW_DFT_WM,
 348         .guard_size = PINEVIEW_GUARD_WM,
 349         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 350 };
 351 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 352         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 353         .max_wm = PINEVIEW_MAX_WM,
 354         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 355         .guard_size = PINEVIEW_GUARD_WM,
 356         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 357 };
 358 static const struct intel_watermark_params pineview_cursor_wm = {
 359         .fifo_size = PINEVIEW_CURSOR_FIFO,
 360         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 361         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 362         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 363         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 364 };
 365 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 366         .fifo_size = PINEVIEW_CURSOR_FIFO,
 367         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 368         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 369         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 370         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 371 };
 372 static const struct intel_watermark_params g4x_wm_info = {
 373         .fifo_size = G4X_FIFO_SIZE,
 374         .max_wm = G4X_MAX_WM,
 375         .default_wm = G4X_MAX_WM,
 376         .guard_size = 2,
 377         .cacheline_size = G4X_FIFO_LINE_SIZE,
 378 };
 379 static const struct intel_watermark_params g4x_cursor_wm_info = {
 380         .fifo_size = I965_CURSOR_FIFO,
 381         .max_wm = I965_CURSOR_MAX_WM,
 382         .default_wm = I965_CURSOR_DFT_WM,
 383         .guard_size = 2,
 384         .cacheline_size = G4X_FIFO_LINE_SIZE,
 385 };
 386 static const struct intel_watermark_params valleyview_wm_info = {
 387         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 388         .max_wm = VALLEYVIEW_MAX_WM,
 389         .default_wm = VALLEYVIEW_MAX_WM,
 390         .guard_size = 2,
 391         .cacheline_size = G4X_FIFO_LINE_SIZE,
 392 };
 393 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 394         .fifo_size = I965_CURSOR_FIFO,
 395         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 396         .default_wm = I965_CURSOR_DFT_WM,
 397         .guard_size = 2,
 398         .cacheline_size = G4X_FIFO_LINE_SIZE,
 399 };
 400 static const struct intel_watermark_params i965_cursor_wm_info = {
 401         .fifo_size = I965_CURSOR_FIFO,
 402         .max_wm = I965_CURSOR_MAX_WM,
 403         .default_wm = I965_CURSOR_DFT_WM,
 404         .guard_size = 2,
 405         .cacheline_size = I915_FIFO_LINE_SIZE,
 406 };
 407 static const struct intel_watermark_params i945_wm_info = {
 408         .fifo_size = I945_FIFO_SIZE,
 409         .max_wm = I915_MAX_WM,
 410         .default_wm = 1,
 411         .guard_size = 2,
 412         .cacheline_size = I915_FIFO_LINE_SIZE,
 413 };
 414 static const struct intel_watermark_params i915_wm_info = {
 415         .fifo_size = I915_FIFO_SIZE,
 416         .max_wm = I915_MAX_WM,
 417         .default_wm = 1,
 418         .guard_size = 2,
 419         .cacheline_size = I915_FIFO_LINE_SIZE,
 420 };
 421 static const struct intel_watermark_params i830_a_wm_info = {
 422         .fifo_size = I855GM_FIFO_SIZE,
 423         .max_wm = I915_MAX_WM,
 424         .default_wm = 1,
 425         .guard_size = 2,
 426         .cacheline_size = I830_FIFO_LINE_SIZE,
 427 };
 428 static const struct intel_watermark_params i830_bc_wm_info = {
 429         .fifo_size = I855GM_FIFO_SIZE,
 430         .max_wm = I915_MAX_WM/2,
 431         .default_wm = 1,
 432         .guard_size = 2,
 433         .cacheline_size = I830_FIFO_LINE_SIZE,
 434 };
 435 static const struct intel_watermark_params i845_wm_info = {
 436         .fifo_size = I830_FIFO_SIZE,
 437         .max_wm = I915_MAX_WM,
 438         .default_wm = 1,
 439         .guard_size = 2,
 440         .cacheline_size = I830_FIFO_LINE_SIZE,
 441 };
 442
 443 /**
 444  * intel_calculate_wm - calculate watermark level
 445  * @clock_in_khz: pixel clock
 446  * @wm: chip FIFO params
 447  * @pixel_size: display pixel size
 448  * @latency_ns: memory latency for the platform
 449  *
 450  * Calculate the watermark level (the level at which the display plane will
 451  * start fetching from memory again).  Each chip has a different display
 452  * FIFO size and allocation, so the caller needs to figure that out and pass
 453  * in the correct intel_watermark_params structure.
 454  *
 455  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 456  * on the pixel size.  When it reaches the watermark level, it'll start
 457  * fetching FIFO line sized based chunks from memory until the FIFO fills
 458  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 459  * will occur, and a display engine hang could result.
 460  */
 461 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 462                                         const struct intel_watermark_params *wm,
 463                                         int fifo_size,
 464                                         int pixel_size,
 465                                         unsigned long latency_ns)
 466 {
 467         long entries_required, wm_size;
 468
 469         /*
 470          * Note: we need to make sure we don't overflow for various clock &
 471          * latency values.
 472          * clocks go from a few thousand to several hundred thousand.
 473          * latency is usually a few thousand
 474          */
 475         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 476                 1000;
 477         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 478
 479         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 480
 481         wm_size = fifo_size - (entries_required + wm->guard_size);
 482
 483         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 484
 485         /* Don't promote wm_size to unsigned... */
 486         if (wm_size > (long)wm->max_wm)
 487                 wm_size = wm->max_wm;
 488         if (wm_size <= 0)
 489                 wm_size = wm->default_wm;
 490
 491         /*
 492          * Bspec seems to indicate that the value shouldn't be lower than
 493          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 494          * Lets go for 8 which is the burst size since certain platforms
 495          * already use a hardcoded 8 (which is what the spec says should be
 496          * done).
 497          */
 498         if (wm_size <= 8)
 499                 wm_size = 8;
 500
 501         return wm_size;
 502 }
 503
 504 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 505 {
 506         struct drm_crtc *crtc, *enabled = NULL;
 507
 508         for_each_crtc(dev, crtc) {
 509                 if (intel_crtc_active(crtc)) {
 510                         if (enabled)
 511                                 return NULL;
 512                         enabled = crtc;
 513                 }
 514         }
 515
 516         return enabled;
 517 }
 518
 519 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 520 {
 521         struct drm_device *dev = unused_crtc->dev;
 522         struct drm_i915_private *dev_priv = dev->dev_private;
 523         struct drm_crtc *crtc;
 524         const struct cxsr_latency *latency;
 525         u32 reg;
 526         unsigned long wm;
 527
 528         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 529                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 530         if (!latency) {
 531                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 532                 intel_set_memory_cxsr(dev_priv, false);
 533                 return;
 534         }
 535
 536         crtc = single_enabled_crtc(dev);
 537         if (crtc) {
 538                 const struct drm_display_mode *adjusted_mode;
 539                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
 540                 int clock;
 541
 542                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
 543                 clock = adjusted_mode->crtc_clock;
 544
 545                 /* Display SR */
 546                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 547                                         pineview_display_wm.fifo_size,
 548                                         pixel_size, latency->display_sr);
 549                 reg = I915_READ(DSPFW1);
 550                 reg &= ~DSPFW_SR_MASK;
 551                 reg |= wm << DSPFW_SR_SHIFT;
 552                 I915_WRITE(DSPFW1, reg);
 553                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 554
 555                 /* cursor SR */
 556                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 557                                         pineview_display_wm.fifo_size,
 558                                         pixel_size, latency->cursor_sr);
 559                 reg = I915_READ(DSPFW3);
 560                 reg &= ~DSPFW_CURSOR_SR_MASK;
 561                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
 562                 I915_WRITE(DSPFW3, reg);
 563
 564                 /* Display HPLL off SR */
 565                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 566                                         pineview_display_hplloff_wm.fifo_size,
 567                                         pixel_size, latency->display_hpll_disable);
 568                 reg = I915_READ(DSPFW3);
 569                 reg &= ~DSPFW_HPLL_SR_MASK;
 570                 reg |= wm & DSPFW_HPLL_SR_MASK;
 571                 I915_WRITE(DSPFW3, reg);
 572
 573                 /* cursor HPLL off SR */
 574                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 575                                         pineview_display_hplloff_wm.fifo_size,
 576                                         pixel_size, latency->cursor_hpll_disable);
 577                 reg = I915_READ(DSPFW3);
 578                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 579                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
 580                 I915_WRITE(DSPFW3, reg);
 581                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 582
 583                 intel_set_memory_cxsr(dev_priv, true);
 584         } else {
 585                 intel_set_memory_cxsr(dev_priv, false);
 586         }
 587 }
 588
 589 static bool g4x_compute_wm0(struct drm_device *dev,
 590                             int plane,
 591                             const struct intel_watermark_params *display,
 592                             int display_latency_ns,
 593                             const struct intel_watermark_params *cursor,
 594                             int cursor_latency_ns,
 595                             int *plane_wm,
 596                             int *cursor_wm)
 597 {
 598         struct drm_crtc *crtc;
 599         const struct drm_display_mode *adjusted_mode;
 600         int htotal, hdisplay, clock, pixel_size;
 601         int line_time_us, line_count;
 602         int entries, tlb_miss;
 603
 604         crtc = intel_get_crtc_for_plane(dev, plane);
 605         if (!intel_crtc_active(crtc)) {
 606                 *cursor_wm = cursor->guard_size;
 607                 *plane_wm = display->guard_size;
 608                 return false;
 609         }
 610
 611         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
 612         clock = adjusted_mode->crtc_clock;
 613         htotal = adjusted_mode->crtc_htotal;
 614         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
 615         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
 616
 617         /* Use the small buffer method to calculate plane watermark */
 618         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 619         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 620         if (tlb_miss > 0)
 621                 entries += tlb_miss;
 622         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 623         *plane_wm = entries + display->guard_size;
 624         if (*plane_wm > (int)display->max_wm)
 625                 *plane_wm = display->max_wm;
 626
 627         /* Use the large buffer method to calculate cursor watermark */
 628         line_time_us = max(htotal * 1000 / clock, 1);
 629         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 630         entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
 631         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 632         if (tlb_miss > 0)
 633                 entries += tlb_miss;
 634         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 635         *cursor_wm = entries + cursor->guard_size;
 636         if (*cursor_wm > (int)cursor->max_wm)
 637                 *cursor_wm = (int)cursor->max_wm;
 638
 639         return true;
 640 }
 641
 642 /*
 643  * Check the wm result.
 644  *
 645  * If any calculated watermark values is larger than the maximum value that
 646  * can be programmed into the associated watermark register, that watermark
 647  * must be disabled.
 648  */
 649 static bool g4x_check_srwm(struct drm_device *dev,
 650                            int display_wm, int cursor_wm,
 651                            const struct intel_watermark_params *display,
 652                            const struct intel_watermark_params *cursor)
 653 {
 654         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 655                       display_wm, cursor_wm);
 656
 657         if (display_wm > display->max_wm) {
 658                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 659                               display_wm, display->max_wm);
 660                 return false;
 661         }
 662
 663         if (cursor_wm > cursor->max_wm) {
 664                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 665                               cursor_wm, cursor->max_wm);
 666                 return false;
 667         }
 668
 669         if (!(display_wm || cursor_wm)) {
 670                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 671                 return false;
 672         }
 673
 674         return true;
 675 }
 676
 677 static bool g4x_compute_srwm(struct drm_device *dev,
 678                              int plane,
 679                              int latency_ns,
 680                              const struct intel_watermark_params *display,
 681                              const struct intel_watermark_params *cursor,
 682                              int *display_wm, int *cursor_wm)
 683 {
 684         struct drm_crtc *crtc;
 685         const struct drm_display_mode *adjusted_mode;
 686         int hdisplay, htotal, pixel_size, clock;
 687         unsigned long line_time_us;
 688         int line_count, line_size;
 689         int small, large;
 690         int entries;
 691
 692         if (!latency_ns) {
 693                 *display_wm = *cursor_wm = 0;
 694                 return false;
 695         }
 696
 697         crtc = intel_get_crtc_for_plane(dev, plane);
 698         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
 699         clock = adjusted_mode->crtc_clock;
 700         htotal = adjusted_mode->crtc_htotal;
 701         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
 702         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
 703
 704         line_time_us = max(htotal * 1000 / clock, 1);
 705         line_count = (latency_ns / line_time_us + 1000) / 1000;
 706         line_size = hdisplay * pixel_size;
 707
 708         /* Use the minimum of the small and large buffer method for primary */
 709         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 710         large = line_count * line_size;
 711
 712         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 713         *display_wm = entries + display->guard_size;
 714
 715         /* calculate the self-refresh watermark for display cursor */
 716         entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
 717         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 718         *cursor_wm = entries + cursor->guard_size;
 719
 720         return g4x_check_srwm(dev,
 721                               *display_wm, *cursor_wm,
 722                               display, cursor);
 723 }
 724
 725 static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
 726                                       int pixel_size,
 727                                       int *prec_mult,
 728                                       int *drain_latency)
 729 {
 730         struct drm_device *dev = crtc->dev;
 731         int entries;
 732         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
 733
 734         if (WARN(clock == 0, "Pixel clock is zero!\n"))
 735                 return false;
 736
 737         if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
 738                 return false;
 739
 740         entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
 741         if (IS_CHERRYVIEW(dev))
 742                 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 :
 743                                                DRAIN_LATENCY_PRECISION_16;
 744         else
 745                 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
 746                                                DRAIN_LATENCY_PRECISION_32;
 747         *drain_latency = (64 * (*prec_mult) * 4) / entries;
 748
 749         if (*drain_latency > DRAIN_LATENCY_MASK)
 750                 *drain_latency = DRAIN_LATENCY_MASK;
 751
 752         return true;
 753 }
 754
 755 /*
 756  * Update drain latency registers of memory arbiter
 757  *
 758  * Valleyview SoC has a new memory arbiter and needs drain latency registers
 759  * to be programmed. Each plane has a drain latency multiplier and a drain
 760  * latency value.
 761  */
 762
 763 static void vlv_update_drain_latency(struct drm_crtc *crtc)
 764 {
 765         struct drm_device *dev = crtc->dev;
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 768         int pixel_size;
 769         int drain_latency;
 770         enum pipe pipe = intel_crtc->pipe;
 771         int plane_prec, prec_mult, plane_dl;
 772         const int high_precision = IS_CHERRYVIEW(dev) ?
 773                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
 774
 775         plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
 776                    DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
 777                    (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
 778
 779         if (!intel_crtc_active(crtc)) {
 780                 I915_WRITE(VLV_DDL(pipe), plane_dl);
 781                 return;
 782         }
 783
 784         /* Primary plane Drain Latency */
 785         pixel_size = crtc->primary->fb->bits_per_pixel / 8;     /* BPP */
 786         if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
 787                 plane_prec = (prec_mult == high_precision) ?
 788                                            DDL_PLANE_PRECISION_HIGH :
 789                                            DDL_PLANE_PRECISION_LOW;
 790                 plane_dl |= plane_prec | drain_latency;
 791         }
 792
 793         /* Cursor Drain Latency
 794          * BPP is always 4 for cursor
 795          */
 796         pixel_size = 4;
 797
 798         /* Program cursor DL only if it is enabled */
 799         if (intel_crtc->cursor_base &&
 800             vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
 801                 plane_prec = (prec_mult == high_precision) ?
 802                                            DDL_CURSOR_PRECISION_HIGH :
 803                                            DDL_CURSOR_PRECISION_LOW;
 804                 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
 805         }
 806
 807         I915_WRITE(VLV_DDL(pipe), plane_dl);
 808 }
 809
 810 #define single_plane_enabled(mask) is_power_of_2(mask)
 811
 812 static void valleyview_update_wm(struct drm_crtc *crtc)
 813 {
 814         struct drm_device *dev = crtc->dev;
 815         static const int sr_latency_ns = 12000;
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
 818         int plane_sr, cursor_sr;
 819         int ignore_plane_sr, ignore_cursor_sr;
 820         unsigned int enabled = 0;
 821         bool cxsr_enabled;
 822
 823         vlv_update_drain_latency(crtc);
 824
 825         if (g4x_compute_wm0(dev, PIPE_A,
 826                             &valleyview_wm_info, pessimal_latency_ns,
 827                             &valleyview_cursor_wm_info, pessimal_latency_ns,
 828                             &planea_wm, &cursora_wm))
 829                 enabled |= 1 << PIPE_A;
 830
 831         if (g4x_compute_wm0(dev, PIPE_B,
 832                             &valleyview_wm_info, pessimal_latency_ns,
 833                             &valleyview_cursor_wm_info, pessimal_latency_ns,
 834                             &planeb_wm, &cursorb_wm))
 835                 enabled |= 1 << PIPE_B;
 836
 837         if (single_plane_enabled(enabled) &&
 838             g4x_compute_srwm(dev, ffs(enabled) - 1,
 839                              sr_latency_ns,
 840                              &valleyview_wm_info,
 841                              &valleyview_cursor_wm_info,
 842                              &plane_sr, &ignore_cursor_sr) &&
 843             g4x_compute_srwm(dev, ffs(enabled) - 1,
 844                              2*sr_latency_ns,
 845                              &valleyview_wm_info,
 846                              &valleyview_cursor_wm_info,
 847                              &ignore_plane_sr, &cursor_sr)) {
 848                 cxsr_enabled = true;
 849         } else {
 850                 cxsr_enabled = false;
 851                 intel_set_memory_cxsr(dev_priv, false);
 852                 plane_sr = cursor_sr = 0;
 853         }
 854
 855         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
 856                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
 857                       planea_wm, cursora_wm,
 858                       planeb_wm, cursorb_wm,
 859                       plane_sr, cursor_sr);
 860
 861         I915_WRITE(DSPFW1,
 862                    (plane_sr << DSPFW_SR_SHIFT) |
 863                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
 864                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
 865                    (planea_wm << DSPFW_PLANEA_SHIFT));
 866         I915_WRITE(DSPFW2,
 867                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
 868                    (cursora_wm << DSPFW_CURSORA_SHIFT));
 869         I915_WRITE(DSPFW3,
 870                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
 871                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 872
 873         if (cxsr_enabled)
 874                 intel_set_memory_cxsr(dev_priv, true);
 875 }
 876
 877 static void cherryview_update_wm(struct drm_crtc *crtc)
 878 {
 879         struct drm_device *dev = crtc->dev;
 880         static const int sr_latency_ns = 12000;
 881         struct drm_i915_private *dev_priv = dev->dev_private;
 882         int planea_wm, planeb_wm, planec_wm;
 883         int cursora_wm, cursorb_wm, cursorc_wm;
 884         int plane_sr, cursor_sr;
 885         int ignore_plane_sr, ignore_cursor_sr;
 886         unsigned int enabled = 0;
 887         bool cxsr_enabled;
 888
 889         vlv_update_drain_latency(crtc);
 890
 891         if (g4x_compute_wm0(dev, PIPE_A,
 892                             &valleyview_wm_info, pessimal_latency_ns,
 893                             &valleyview_cursor_wm_info, pessimal_latency_ns,
 894                             &planea_wm, &cursora_wm))
 895                 enabled |= 1 << PIPE_A;
 896
 897         if (g4x_compute_wm0(dev, PIPE_B,
 898                             &valleyview_wm_info, pessimal_latency_ns,
 899                             &valleyview_cursor_wm_info, pessimal_latency_ns,
 900                             &planeb_wm, &cursorb_wm))
 901                 enabled |= 1 << PIPE_B;
 902
 903         if (g4x_compute_wm0(dev, PIPE_C,
 904                             &valleyview_wm_info, pessimal_latency_ns,
 905                             &valleyview_cursor_wm_info, pessimal_latency_ns,
 906                             &planec_wm, &cursorc_wm))
 907                 enabled |= 1 << PIPE_C;
 908
 909         if (single_plane_enabled(enabled) &&
 910             g4x_compute_srwm(dev, ffs(enabled) - 1,
 911                              sr_latency_ns,
 912                              &valleyview_wm_info,
 913                              &valleyview_cursor_wm_info,
 914                              &plane_sr, &ignore_cursor_sr) &&
 915             g4x_compute_srwm(dev, ffs(enabled) - 1,
 916                              2*sr_latency_ns,
 917                              &valleyview_wm_info,
 918                              &valleyview_cursor_wm_info,
 919                              &ignore_plane_sr, &cursor_sr)) {
 920                 cxsr_enabled = true;
 921         } else {
 922                 cxsr_enabled = false;
 923                 intel_set_memory_cxsr(dev_priv, false);
 924                 plane_sr = cursor_sr = 0;
 925         }
 926
 927         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
 928                       "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
 929                       "SR: plane=%d, cursor=%d\n",
 930                       planea_wm, cursora_wm,
 931                       planeb_wm, cursorb_wm,
 932                       planec_wm, cursorc_wm,
 933                       plane_sr, cursor_sr);
 934
 935         I915_WRITE(DSPFW1,
 936                    (plane_sr << DSPFW_SR_SHIFT) |
 937                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
 938                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
 939                    (planea_wm << DSPFW_PLANEA_SHIFT));
 940         I915_WRITE(DSPFW2,
 941                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
 942                    (cursora_wm << DSPFW_CURSORA_SHIFT));
 943         I915_WRITE(DSPFW3,
 944                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
 945                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 946         I915_WRITE(DSPFW9_CHV,
 947                    (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
 948                                               DSPFW_CURSORC_MASK)) |
 949                    (planec_wm << DSPFW_PLANEC_SHIFT) |
 950                    (cursorc_wm << DSPFW_CURSORC_SHIFT));
 951
 952         if (cxsr_enabled)
 953                 intel_set_memory_cxsr(dev_priv, true);
 954 }
 955
 956 static void valleyview_update_sprite_wm(struct drm_plane *plane,
 957                                         struct drm_crtc *crtc,
 958                                         uint32_t sprite_width,
 959                                         uint32_t sprite_height,
 960                                         int pixel_size,
 961                                         bool enabled, bool scaled)
 962 {
 963         struct drm_device *dev = crtc->dev;
 964         struct drm_i915_private *dev_priv = dev->dev_private;
 965         int pipe = to_intel_plane(plane)->pipe;
 966         int sprite = to_intel_plane(plane)->plane;
 967         int drain_latency;
 968         int plane_prec;
 969         int sprite_dl;
 970         int prec_mult;
 971         const int high_precision = IS_CHERRYVIEW(dev) ?
 972                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
 973
 974         sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) |
 975                     (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
 976
 977         if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
 978                                                  &drain_latency)) {
 979                 plane_prec = (prec_mult == high_precision) ?
 980                                            DDL_SPRITE_PRECISION_HIGH(sprite) :
 981                                            DDL_SPRITE_PRECISION_LOW(sprite);
 982                 sprite_dl |= plane_prec |
 983                              (drain_latency << DDL_SPRITE_SHIFT(sprite));
 984         }
 985
 986         I915_WRITE(VLV_DDL(pipe), sprite_dl);
 987 }
 988
 989 static void g4x_update_wm(struct drm_crtc *crtc)
 990 {
 991         struct drm_device *dev = crtc->dev;
 992         static const int sr_latency_ns = 12000;
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
 995         int plane_sr, cursor_sr;
 996         unsigned int enabled = 0;
 997         bool cxsr_enabled;
 998
 999         if (g4x_compute_wm0(dev, PIPE_A,
1000                             &g4x_wm_info, pessimal_latency_ns,
1001                             &g4x_cursor_wm_info, pessimal_latency_ns,
1002                             &planea_wm, &cursora_wm))
1003                 enabled |= 1 << PIPE_A;
1004
1005         if (g4x_compute_wm0(dev, PIPE_B,
1006                             &g4x_wm_info, pessimal_latency_ns,
1007                             &g4x_cursor_wm_info, pessimal_latency_ns,
1008                             &planeb_wm, &cursorb_wm))
1009                 enabled |= 1 << PIPE_B;
1010
1011         if (single_plane_enabled(enabled) &&
1012             g4x_compute_srwm(dev, ffs(enabled) - 1,
1013                              sr_latency_ns,
1014                              &g4x_wm_info,
1015                              &g4x_cursor_wm_info,
1016                              &plane_sr, &cursor_sr)) {
1017                 cxsr_enabled = true;
1018         } else {
1019                 cxsr_enabled = false;
1020                 intel_set_memory_cxsr(dev_priv, false);
1021                 plane_sr = cursor_sr = 0;
1022         }
1023
1024         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1025                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1026                       planea_wm, cursora_wm,
1027                       planeb_wm, cursorb_wm,
1028                       plane_sr, cursor_sr);
1029
1030         I915_WRITE(DSPFW1,
1031                    (plane_sr << DSPFW_SR_SHIFT) |
1032                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1033                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1034                    (planea_wm << DSPFW_PLANEA_SHIFT));
1035         I915_WRITE(DSPFW2,
1036                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1037                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1038         /* HPLL off in SR has some issues on G4x... disable it */
1039         I915_WRITE(DSPFW3,
1040                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1041                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1042
1043         if (cxsr_enabled)
1044                 intel_set_memory_cxsr(dev_priv, true);
1045 }
1046
1047 static void i965_update_wm(struct drm_crtc *unused_crtc)
1048 {
1049         struct drm_device *dev = unused_crtc->dev;
1050         struct drm_i915_private *dev_priv = dev->dev_private;
1051         struct drm_crtc *crtc;
1052         int srwm = 1;
1053         int cursor_sr = 16;
1054         bool cxsr_enabled;
1055
1056         /* Calc sr entries for one plane configs */
1057         crtc = single_enabled_crtc(dev);
1058         if (crtc) {
1059                 /* self-refresh has much higher latency */
1060                 static const int sr_latency_ns = 12000;
1061                 const struct drm_display_mode *adjusted_mode =
1062                         &to_intel_crtc(crtc)->config.adjusted_mode;
1063                 int clock = adjusted_mode->crtc_clock;
1064                 int htotal = adjusted_mode->crtc_htotal;
1065                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1066                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1067                 unsigned long line_time_us;
1068                 int entries;
1069
1070                 line_time_us = max(htotal * 1000 / clock, 1);
1071
1072                 /* Use ns/us then divide to preserve precision */
1073                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1074                         pixel_size * hdisplay;
1075                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1076                 srwm = I965_FIFO_SIZE - entries;
1077                 if (srwm < 0)
1078                         srwm = 1;
1079                 srwm &= 0x1ff;
1080                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1081                               entries, srwm);
1082
1083                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1084                         pixel_size * to_intel_crtc(crtc)->cursor_width;
1085                 entries = DIV_ROUND_UP(entries,
1086                                           i965_cursor_wm_info.cacheline_size);
1087                 cursor_sr = i965_cursor_wm_info.fifo_size -
1088                         (entries + i965_cursor_wm_info.guard_size);
1089
1090                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1091                         cursor_sr = i965_cursor_wm_info.max_wm;
1092
1093                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1094                               "cursor %d\n", srwm, cursor_sr);
1095
1096                 cxsr_enabled = true;
1097         } else {
1098                 cxsr_enabled = false;
1099                 /* Turn off self refresh if both pipes are enabled */
1100                 intel_set_memory_cxsr(dev_priv, false);
1101         }
1102
1103         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1104                       srwm);
1105
1106         /* 965 has limitations... */
1107         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1108                    (8 << DSPFW_CURSORB_SHIFT) |
1109                    (8 << DSPFW_PLANEB_SHIFT) |
1110                    (8 << DSPFW_PLANEA_SHIFT));
1111         I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1112                    (8 << DSPFW_PLANEC_SHIFT_OLD));
1113         /* update cursor SR watermark */
1114         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1115
1116         if (cxsr_enabled)
1117                 intel_set_memory_cxsr(dev_priv, true);
1118 }
1119
1120 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1121 {
1122         struct drm_device *dev = unused_crtc->dev;
1123         struct drm_i915_private *dev_priv = dev->dev_private;
1124         const struct intel_watermark_params *wm_info;
1125         uint32_t fwater_lo;
1126         uint32_t fwater_hi;
1127         int cwm, srwm = 1;
1128         int fifo_size;
1129         int planea_wm, planeb_wm;
1130         struct drm_crtc *crtc, *enabled = NULL;
1131
1132         if (IS_I945GM(dev))
1133                 wm_info = &i945_wm_info;
1134         else if (!IS_GEN2(dev))
1135                 wm_info = &i915_wm_info;
1136         else
1137                 wm_info = &i830_a_wm_info;
1138
1139         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1140         crtc = intel_get_crtc_for_plane(dev, 0);
1141         if (intel_crtc_active(crtc)) {
1142                 const struct drm_display_mode *adjusted_mode;
1143                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1144                 if (IS_GEN2(dev))
1145                         cpp = 4;
1146
1147                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1148                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1149                                                wm_info, fifo_size, cpp,
1150                                                pessimal_latency_ns);
1151                 enabled = crtc;
1152         } else {
1153                 planea_wm = fifo_size - wm_info->guard_size;
1154                 if (planea_wm > (long)wm_info->max_wm)
1155                         planea_wm = wm_info->max_wm;
1156         }
1157
1158         if (IS_GEN2(dev))
1159                 wm_info = &i830_bc_wm_info;
1160
1161         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1162         crtc = intel_get_crtc_for_plane(dev, 1);
1163         if (intel_crtc_active(crtc)) {
1164                 const struct drm_display_mode *adjusted_mode;
1165                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1166                 if (IS_GEN2(dev))
1167                         cpp = 4;
1168
1169                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1170                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1171                                                wm_info, fifo_size, cpp,
1172                                                pessimal_latency_ns);
1173                 if (enabled == NULL)
1174                         enabled = crtc;
1175                 else
1176                         enabled = NULL;
1177         } else {
1178                 planeb_wm = fifo_size - wm_info->guard_size;
1179                 if (planeb_wm > (long)wm_info->max_wm)
1180                         planeb_wm = wm_info->max_wm;
1181         }
1182
1183         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1184
1185         if (IS_I915GM(dev) && enabled) {
1186                 struct drm_i915_gem_object *obj;
1187
1188                 obj = intel_fb_obj(enabled->primary->fb);
1189
1190                 /* self-refresh seems busted with untiled */
1191                 if (obj->tiling_mode == I915_TILING_NONE)
1192                         enabled = NULL;
1193         }
1194
1195         /*
1196          * Overlay gets an aggressive default since video jitter is bad.
1197          */
1198         cwm = 2;
1199
1200         /* Play safe and disable self-refresh before adjusting watermarks. */
1201         intel_set_memory_cxsr(dev_priv, false);
1202
1203         /* Calc sr entries for one plane configs */
1204         if (HAS_FW_BLC(dev) && enabled) {
1205                 /* self-refresh has much higher latency */
1206                 static const int sr_latency_ns = 6000;
1207                 const struct drm_display_mode *adjusted_mode =
1208                         &to_intel_crtc(enabled)->config.adjusted_mode;
1209                 int clock = adjusted_mode->crtc_clock;
1210                 int htotal = adjusted_mode->crtc_htotal;
1211                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1212                 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1213                 unsigned long line_time_us;
1214                 int entries;
1215
1216                 line_time_us = max(htotal * 1000 / clock, 1);
1217
1218                 /* Use ns/us then divide to preserve precision */
1219                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1220                         pixel_size * hdisplay;
1221                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1222                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1223                 srwm = wm_info->fifo_size - entries;
1224                 if (srwm < 0)
1225                         srwm = 1;
1226
1227                 if (IS_I945G(dev) || IS_I945GM(dev))
1228                         I915_WRITE(FW_BLC_SELF,
1229                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1230                 else if (IS_I915GM(dev))
1231                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1232         }
1233
1234         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1235                       planea_wm, planeb_wm, cwm, srwm);
1236
1237         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1238         fwater_hi = (cwm & 0x1f);
1239
1240         /* Set request length to 8 cachelines per fetch */
1241         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1242         fwater_hi = fwater_hi | (1 << 8);
1243
1244         I915_WRITE(FW_BLC, fwater_lo);
1245         I915_WRITE(FW_BLC2, fwater_hi);
1246
1247         if (enabled)
1248                 intel_set_memory_cxsr(dev_priv, true);
1249 }
1250
1251 static void i845_update_wm(struct drm_crtc *unused_crtc)
1252 {
1253         struct drm_device *dev = unused_crtc->dev;
1254         struct drm_i915_private *dev_priv = dev->dev_private;
1255         struct drm_crtc *crtc;
1256         const struct drm_display_mode *adjusted_mode;
1257         uint32_t fwater_lo;
1258         int planea_wm;
1259
1260         crtc = single_enabled_crtc(dev);
1261         if (crtc == NULL)
1262                 return;
1263
1264         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1265         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1266                                        &i845_wm_info,
1267                                        dev_priv->display.get_fifo_size(dev, 0),
1268                                        4, pessimal_latency_ns);
1269         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1270         fwater_lo |= (3<<8) | planea_wm;
1271
1272         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1273
1274         I915_WRITE(FW_BLC, fwater_lo);
1275 }
1276
1277 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1278                                     struct drm_crtc *crtc)
1279 {
1280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1281         uint32_t pixel_rate;
1282
1283         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1284
1285         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1286          * adjust the pixel_rate here. */
1287
1288         if (intel_crtc->config.pch_pfit.enabled) {
1289                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1290                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1291
1292                 pipe_w = intel_crtc->config.pipe_src_w;
1293                 pipe_h = intel_crtc->config.pipe_src_h;
1294                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1295                 pfit_h = pfit_size & 0xFFFF;
1296                 if (pipe_w < pfit_w)
1297                         pipe_w = pfit_w;
1298                 if (pipe_h < pfit_h)
1299                         pipe_h = pfit_h;
1300
1301                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1302                                      pfit_w * pfit_h);
1303         }
1304
1305         return pixel_rate;
1306 }
1307
1308 /* latency must be in 0.1us units. */
1309 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1310                                uint32_t latency)
1311 {
1312         uint64_t ret;
1313
1314         if (WARN(latency == 0, "Latency value missing\n"))
1315                 return UINT_MAX;
1316
1317         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1318         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1319
1320         return ret;
1321 }
1322
1323 /* latency must be in 0.1us units. */
1324 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1325                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1326                                uint32_t latency)
1327 {
1328         uint32_t ret;
1329
1330         if (WARN(latency == 0, "Latency value missing\n"))
1331                 return UINT_MAX;
1332
1333         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1334         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1335         ret = DIV_ROUND_UP(ret, 64) + 2;
1336         return ret;
1337 }
1338
1339 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1340                            uint8_t bytes_per_pixel)
1341 {
1342         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1343 }
1344
1345 struct skl_pipe_wm_parameters {
1346         bool active;
1347         uint32_t pipe_htotal;
1348         uint32_t pixel_rate; /* in KHz */
1349         struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1350         struct intel_plane_wm_parameters cursor;
1351 };
1352
1353 struct ilk_pipe_wm_parameters {
1354         bool active;
1355         uint32_t pipe_htotal;
1356         uint32_t pixel_rate;
1357         struct intel_plane_wm_parameters pri;
1358         struct intel_plane_wm_parameters spr;
1359         struct intel_plane_wm_parameters cur;
1360 };
1361
1362 struct ilk_wm_maximums {
1363         uint16_t pri;
1364         uint16_t spr;
1365         uint16_t cur;
1366         uint16_t fbc;
1367 };
1368
1369 /* used in computing the new watermarks state */
1370 struct intel_wm_config {
1371         unsigned int num_pipes_active;
1372         bool sprites_enabled;
1373         bool sprites_scaled;
1374 };
1375
1376 /*
1377  * For both WM_PIPE and WM_LP.
1378  * mem_value must be in 0.1us units.
1379  */
1380 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1381                                    uint32_t mem_value,
1382                                    bool is_lp)
1383 {
1384         uint32_t method1, method2;
1385
1386         if (!params->active || !params->pri.enabled)
1387                 return 0;
1388
1389         method1 = ilk_wm_method1(params->pixel_rate,
1390                                  params->pri.bytes_per_pixel,
1391                                  mem_value);
1392
1393         if (!is_lp)
1394                 return method1;
1395
1396         method2 = ilk_wm_method2(params->pixel_rate,
1397                                  params->pipe_htotal,
1398                                  params->pri.horiz_pixels,
1399                                  params->pri.bytes_per_pixel,
1400                                  mem_value);
1401
1402         return min(method1, method2);
1403 }
1404
1405 /*
1406  * For both WM_PIPE and WM_LP.
1407  * mem_value must be in 0.1us units.
1408  */
1409 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1410                                    uint32_t mem_value)
1411 {
1412         uint32_t method1, method2;
1413
1414         if (!params->active || !params->spr.enabled)
1415                 return 0;
1416
1417         method1 = ilk_wm_method1(params->pixel_rate,
1418                                  params->spr.bytes_per_pixel,
1419                                  mem_value);
1420         method2 = ilk_wm_method2(params->pixel_rate,
1421                                  params->pipe_htotal,
1422                                  params->spr.horiz_pixels,
1423                                  params->spr.bytes_per_pixel,
1424                                  mem_value);
1425         return min(method1, method2);
1426 }
1427
1428 /*
1429  * For both WM_PIPE and WM_LP.
1430  * mem_value must be in 0.1us units.
1431  */
1432 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1433                                    uint32_t mem_value)
1434 {
1435         if (!params->active || !params->cur.enabled)
1436                 return 0;
1437
1438         return ilk_wm_method2(params->pixel_rate,
1439                               params->pipe_htotal,
1440                               params->cur.horiz_pixels,
1441                               params->cur.bytes_per_pixel,
1442                               mem_value);
1443 }
1444
1445 /* Only for WM_LP. */
1446 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1447                                    uint32_t pri_val)
1448 {
1449         if (!params->active || !params->pri.enabled)
1450                 return 0;
1451
1452         return ilk_wm_fbc(pri_val,
1453                           params->pri.horiz_pixels,
1454                           params->pri.bytes_per_pixel);
1455 }
1456
1457 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1458 {
1459         if (INTEL_INFO(dev)->gen >= 8)
1460                 return 3072;
1461         else if (INTEL_INFO(dev)->gen >= 7)
1462                 return 768;
1463         else
1464                 return 512;
1465 }
1466
1467 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1468                                          int level, bool is_sprite)
1469 {
1470         if (INTEL_INFO(dev)->gen >= 8)
1471                 /* BDW primary/sprite plane watermarks */
1472                 return level == 0 ? 255 : 2047;
1473         else if (INTEL_INFO(dev)->gen >= 7)
1474                 /* IVB/HSW primary/sprite plane watermarks */
1475                 return level == 0 ? 127 : 1023;
1476         else if (!is_sprite)
1477                 /* ILK/SNB primary plane watermarks */
1478                 return level == 0 ? 127 : 511;
1479         else
1480                 /* ILK/SNB sprite plane watermarks */
1481                 return level == 0 ? 63 : 255;
1482 }
1483
1484 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1485                                           int level)
1486 {
1487         if (INTEL_INFO(dev)->gen >= 7)
1488                 return level == 0 ? 63 : 255;
1489         else
1490                 return level == 0 ? 31 : 63;
1491 }
1492
1493 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1494 {
1495         if (INTEL_INFO(dev)->gen >= 8)
1496                 return 31;
1497         else
1498                 return 15;
1499 }
1500
1501 /* Calculate the maximum primary/sprite plane watermark */
1502 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1503                                      int level,
1504                                      const struct intel_wm_config *config,
1505                                      enum intel_ddb_partitioning ddb_partitioning,
1506                                      bool is_sprite)
1507 {
1508         unsigned int fifo_size = ilk_display_fifo_size(dev);
1509
1510         /* if sprites aren't enabled, sprites get nothing */
1511         if (is_sprite && !config->sprites_enabled)
1512                 return 0;
1513
1514         /* HSW allows LP1+ watermarks even with multiple pipes */
1515         if (level == 0 || config->num_pipes_active > 1) {
1516                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1517
1518                 /*
1519                  * For some reason the non self refresh
1520                  * FIFO size is only half of the self
1521                  * refresh FIFO size on ILK/SNB.
1522                  */
1523                 if (INTEL_INFO(dev)->gen <= 6)
1524                         fifo_size /= 2;
1525         }
1526
1527         if (config->sprites_enabled) {
1528                 /* level 0 is always calculated with 1:1 split */
1529                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1530                         if (is_sprite)
1531                                 fifo_size *= 5;
1532                         fifo_size /= 6;
1533                 } else {
1534                         fifo_size /= 2;
1535                 }
1536         }
1537
1538         /* clamp to max that the registers can hold */
1539         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1540 }
1541
1542 /* Calculate the maximum cursor plane watermark */
1543 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1544                                       int level,
1545                                       const struct intel_wm_config *config)
1546 {
1547         /* HSW LP1+ watermarks w/ multiple pipes */
1548         if (level > 0 && config->num_pipes_active > 1)
1549                 return 64;
1550
1551         /* otherwise just report max that registers can hold */
1552         return ilk_cursor_wm_reg_max(dev, level);
1553 }
1554
1555 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1556                                     int level,
1557                                     const struct intel_wm_config *config,
1558                                     enum intel_ddb_partitioning ddb_partitioning,
1559                                     struct ilk_wm_maximums *max)
1560 {
1561         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1562         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1563         max->cur = ilk_cursor_wm_max(dev, level, config);
1564         max->fbc = ilk_fbc_wm_reg_max(dev);
1565 }
1566
1567 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1568                                         int level,
1569                                         struct ilk_wm_maximums *max)
1570 {
1571         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1572         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1573         max->cur = ilk_cursor_wm_reg_max(dev, level);
1574         max->fbc = ilk_fbc_wm_reg_max(dev);
1575 }
1576
1577 static bool ilk_validate_wm_level(int level,
1578                                   const struct ilk_wm_maximums *max,
1579                                   struct intel_wm_level *result)
1580 {
1581         bool ret;
1582
1583         /* already determined to be invalid? */
1584         if (!result->enable)
1585                 return false;
1586
1587         result->enable = result->pri_val <= max->pri &&
1588                          result->spr_val <= max->spr &&
1589                          result->cur_val <= max->cur;
1590
1591         ret = result->enable;
1592
1593         /*
1594          * HACK until we can pre-compute everything,
1595          * and thus fail gracefully if LP0 watermarks
1596          * are exceeded...
1597          */
1598         if (level == 0 && !result->enable) {
1599                 if (result->pri_val > max->pri)
1600                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1601                                       level, result->pri_val, max->pri);
1602                 if (result->spr_val > max->spr)
1603                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1604                                       level, result->spr_val, max->spr);
1605                 if (result->cur_val > max->cur)
1606                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1607                                       level, result->cur_val, max->cur);
1608
1609                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1610                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1611                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1612                 result->enable = true;
1613         }
1614
1615         return ret;
1616 }
1617
1618 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1619                                  int level,
1620                                  const struct ilk_pipe_wm_parameters *p,
1621                                  struct intel_wm_level *result)
1622 {
1623         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1624         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1625         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1626
1627         /* WM1+ latency values stored in 0.5us units */
1628         if (level > 0) {
1629                 pri_latency *= 5;
1630                 spr_latency *= 5;
1631                 cur_latency *= 5;
1632         }
1633
1634         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1635         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1636         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1637         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1638         result->enable = true;
1639 }
1640
1641 static uint32_t
1642 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1643 {
1644         struct drm_i915_private *dev_priv = dev->dev_private;
1645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1646         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
1647         u32 linetime, ips_linetime;
1648
1649         if (!intel_crtc_active(crtc))
1650                 return 0;
1651
1652         /* The WM are computed with base on how long it takes to fill a single
1653          * row at the given clock rate, multiplied by 8.
1654          * */
1655         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1656                                      mode->crtc_clock);
1657         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1658                                          intel_ddi_get_cdclk_freq(dev_priv));
1659
1660         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1661                PIPE_WM_LINETIME_TIME(linetime);
1662 }
1663
1664 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
1665 {
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667
1668         if (IS_GEN9(dev)) {
1669                 uint32_t val;
1670                 int ret, i;
1671                 int level, max_level = ilk_wm_max_level(dev);
1672
1673                 /* read the first set of memory latencies[0:3] */
1674                 val = 0; /* data0 to be programmed to 0 for first set */
1675                 mutex_lock(&dev_priv->rps.hw_lock);
1676                 ret = sandybridge_pcode_read(dev_priv,
1677                                              GEN9_PCODE_READ_MEM_LATENCY,
1678                                              &val);
1679                 mutex_unlock(&dev_priv->rps.hw_lock);
1680
1681                 if (ret) {
1682                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1683                         return;
1684                 }
1685
1686                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1687                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1688                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1689                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1690                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1691                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1692                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1693
1694                 /* read the second set of memory latencies[4:7] */
1695                 val = 1; /* data0 to be programmed to 1 for second set */
1696                 mutex_lock(&dev_priv->rps.hw_lock);
1697                 ret = sandybridge_pcode_read(dev_priv,
1698                                              GEN9_PCODE_READ_MEM_LATENCY,
1699                                              &val);
1700                 mutex_unlock(&dev_priv->rps.hw_lock);
1701                 if (ret) {
1702                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1703                         return;
1704                 }
1705
1706                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1707                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1708                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1709                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1710                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1711                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1712                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1713
1714                 /*
1715                  * punit doesn't take into account the read latency so we need
1716                  * to add 2us to the various latency levels we retrieve from
1717                  * the punit.
1718                  *   - W0 is a bit special in that it's the only level that
1719                  *   can't be disabled if we want to have display working, so
1720                  *   we always add 2us there.
1721                  *   - For levels >=1, punit returns 0us latency when they are
1722                  *   disabled, so we respect that and don't add 2us then
1723                  *
1724                  * Additionally, if a level n (n > 1) has a 0us latency, all
1725                  * levels m (m >= n) need to be disabled. We make sure to
1726                  * sanitize the values out of the punit to satisfy this
1727                  * requirement.
1728                  */
1729                 wm[0] += 2;
1730                 for (level = 1; level <= max_level; level++)
1731                         if (wm[level] != 0)
1732                                 wm[level] += 2;
1733                         else {
1734                                 for (i = level + 1; i <= max_level; i++)
1735                                         wm[i] = 0;
1736
1737                                 break;
1738                         }
1739         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1740                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1741
1742                 wm[0] = (sskpd >> 56) & 0xFF;
1743                 if (wm[0] == 0)
1744                         wm[0] = sskpd & 0xF;
1745                 wm[1] = (sskpd >> 4) & 0xFF;
1746                 wm[2] = (sskpd >> 12) & 0xFF;
1747                 wm[3] = (sskpd >> 20) & 0x1FF;
1748                 wm[4] = (sskpd >> 32) & 0x1FF;
1749         } else if (INTEL_INFO(dev)->gen >= 6) {
1750                 uint32_t sskpd = I915_READ(MCH_SSKPD);
1751
1752                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1753                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1754                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1755                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
1756         } else if (INTEL_INFO(dev)->gen >= 5) {
1757                 uint32_t mltr = I915_READ(MLTR_ILK);
1758
1759                 /* ILK primary LP0 latency is 700 ns */
1760                 wm[0] = 7;
1761                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1762                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
1763         }
1764 }
1765
1766 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1767 {
1768         /* ILK sprite LP0 latency is 1300 ns */
1769         if (INTEL_INFO(dev)->gen == 5)
1770                 wm[0] = 13;
1771 }
1772
1773 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1774 {
1775         /* ILK cursor LP0 latency is 1300 ns */
1776         if (INTEL_INFO(dev)->gen == 5)
1777                 wm[0] = 13;
1778
1779         /* WaDoubleCursorLP3Latency:ivb */
1780         if (IS_IVYBRIDGE(dev))
1781                 wm[3] *= 2;
1782 }
1783
1784 int ilk_wm_max_level(const struct drm_device *dev)
1785 {
1786         /* how many WM levels are we expecting */
1787         if (IS_GEN9(dev))
1788                 return 7;
1789         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1790                 return 4;
1791         else if (INTEL_INFO(dev)->gen >= 6)
1792                 return 3;
1793         else
1794                 return 2;
1795 }
1796
1797 static void intel_print_wm_latency(struct drm_device *dev,
1798                                    const char *name,
1799                                    const uint16_t wm[8])
1800 {
1801         int level, max_level = ilk_wm_max_level(dev);
1802
1803         for (level = 0; level <= max_level; level++) {
1804                 unsigned int latency = wm[level];
1805
1806                 if (latency == 0) {
1807                         DRM_ERROR("%s WM%d latency not provided\n",
1808                                   name, level);
1809                         continue;
1810                 }
1811
1812                 /*
1813                  * - latencies are in us on gen9.
1814                  * - before then, WM1+ latency values are in 0.5us units
1815                  */
1816                 if (IS_GEN9(dev))
1817                         latency *= 10;
1818                 else if (level > 0)
1819                         latency *= 5;
1820
1821                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1822                               name, level, wm[level],
1823                               latency / 10, latency % 10);
1824         }
1825 }
1826
1827 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1828                                     uint16_t wm[5], uint16_t min)
1829 {
1830         int level, max_level = ilk_wm_max_level(dev_priv->dev);
1831
1832         if (wm[0] >= min)
1833                 return false;
1834
1835         wm[0] = max(wm[0], min);
1836         for (level = 1; level <= max_level; level++)
1837                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1838
1839         return true;
1840 }
1841
1842 static void snb_wm_latency_quirk(struct drm_device *dev)
1843 {
1844         struct drm_i915_private *dev_priv = dev->dev_private;
1845         bool changed;
1846
1847         /*
1848          * The BIOS provided WM memory latency values are often
1849          * inadequate for high resolution displays. Adjust them.
1850          */
1851         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
1852                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
1853                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
1854
1855         if (!changed)
1856                 return;
1857
1858         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
1859         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
1860         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
1861         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
1862 }
1863
1864 static void ilk_setup_wm_latency(struct drm_device *dev)
1865 {
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867
1868         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
1869
1870         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
1871                sizeof(dev_priv->wm.pri_latency));
1872         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
1873                sizeof(dev_priv->wm.pri_latency));
1874
1875         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
1876         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
1877
1878         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
1879         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
1880         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
1881
1882         if (IS_GEN6(dev))
1883                 snb_wm_latency_quirk(dev);
1884 }
1885
1886 static void skl_setup_wm_latency(struct drm_device *dev)
1887 {
1888         struct drm_i915_private *dev_priv = dev->dev_private;
1889
1890         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
1891         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
1892 }
1893
1894 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
1895                                       struct ilk_pipe_wm_parameters *p)
1896 {
1897         struct drm_device *dev = crtc->dev;
1898         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1899         enum pipe pipe = intel_crtc->pipe;
1900         struct drm_plane *plane;
1901
1902         if (!intel_crtc_active(crtc))
1903                 return;
1904
1905         p->active = true;
1906         p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
1907         p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
1908         p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
1909         p->cur.bytes_per_pixel = 4;
1910         p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
1911         p->cur.horiz_pixels = intel_crtc->cursor_width;
1912         /* TODO: for now, assume primary and cursor planes are always enabled. */
1913         p->pri.enabled = true;
1914         p->cur.enabled = true;
1915
1916         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
1917                 struct intel_plane *intel_plane = to_intel_plane(plane);
1918
1919                 if (intel_plane->pipe == pipe) {
1920                         p->spr = intel_plane->wm;
1921                         break;
1922                 }
1923         }
1924 }
1925
1926 static void ilk_compute_wm_config(struct drm_device *dev,
1927                                   struct intel_wm_config *config)
1928 {
1929         struct intel_crtc *intel_crtc;
1930
1931         /* Compute the currently _active_ config */
1932         for_each_intel_crtc(dev, intel_crtc) {
1933                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
1934
1935                 if (!wm->pipe_enabled)
1936                         continue;
1937
1938                 config->sprites_enabled |= wm->sprites_enabled;
1939                 config->sprites_scaled |= wm->sprites_scaled;
1940                 config->num_pipes_active++;
1941         }
1942 }
1943
1944 /* Compute new watermarks for the pipe */
1945 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
1946                                   const struct ilk_pipe_wm_parameters *params,
1947                                   struct intel_pipe_wm *pipe_wm)
1948 {
1949         struct drm_device *dev = crtc->dev;
1950         const struct drm_i915_private *dev_priv = dev->dev_private;
1951         int level, max_level = ilk_wm_max_level(dev);
1952         /* LP0 watermark maximums depend on this pipe alone */
1953         struct intel_wm_config config = {
1954                 .num_pipes_active = 1,
1955                 .sprites_enabled = params->spr.enabled,
1956                 .sprites_scaled = params->spr.scaled,
1957         };
1958         struct ilk_wm_maximums max;
1959
1960         pipe_wm->pipe_enabled = params->active;
1961         pipe_wm->sprites_enabled = params->spr.enabled;
1962         pipe_wm->sprites_scaled = params->spr.scaled;
1963
1964         /* ILK/SNB: LP2+ watermarks only w/o sprites */
1965         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
1966                 max_level = 1;
1967
1968         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
1969         if (params->spr.scaled)
1970                 max_level = 0;
1971
1972         ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
1973
1974         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1975                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
1976
1977         /* LP0 watermarks always use 1/2 DDB partitioning */
1978         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
1979
1980         /* At least LP0 must be valid */
1981         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
1982                 return false;
1983
1984         ilk_compute_wm_reg_maximums(dev, 1, &max);
1985
1986         for (level = 1; level <= max_level; level++) {
1987                 struct intel_wm_level wm = {};
1988
1989                 ilk_compute_wm_level(dev_priv, level, params, &wm);
1990
1991                 /*
1992                  * Disable any watermark level that exceeds the
1993                  * register maximums since such watermarks are
1994                  * always invalid.
1995                  */
1996                 if (!ilk_validate_wm_level(level, &max, &wm))
1997                         break;
1998
1999                 pipe_wm->wm[level] = wm;
2000         }
2001
2002         return true;
2003 }
2004
2005 /*
2006  * Merge the watermarks from all active pipes for a specific level.
2007  */
2008 static void ilk_merge_wm_level(struct drm_device *dev,
2009                                int level,
2010                                struct intel_wm_level *ret_wm)
2011 {
2012         const struct intel_crtc *intel_crtc;
2013
2014         ret_wm->enable = true;
2015
2016         for_each_intel_crtc(dev, intel_crtc) {
2017                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2018                 const struct intel_wm_level *wm = &active->wm[level];
2019
2020                 if (!active->pipe_enabled)
2021                         continue;
2022
2023                 /*
2024                  * The watermark values may have been used in the past,
2025                  * so we must maintain them in the registers for some
2026                  * time even if the level is now disabled.
2027                  */
2028                 if (!wm->enable)
2029                         ret_wm->enable = false;
2030
2031                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2032                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2033                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2034                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2035         }
2036 }
2037
2038 /*
2039  * Merge all low power watermarks for all active pipes.
2040  */
2041 static void ilk_wm_merge(struct drm_device *dev,
2042                          const struct intel_wm_config *config,
2043                          const struct ilk_wm_maximums *max,
2044                          struct intel_pipe_wm *merged)
2045 {
2046         int level, max_level = ilk_wm_max_level(dev);
2047         int last_enabled_level = max_level;
2048
2049         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2050         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2051             config->num_pipes_active > 1)
2052                 return;
2053
2054         /* ILK: FBC WM must be disabled always */
2055         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2056
2057         /* merge each WM1+ level */
2058         for (level = 1; level <= max_level; level++) {
2059                 struct intel_wm_level *wm = &merged->wm[level];
2060
2061                 ilk_merge_wm_level(dev, level, wm);
2062
2063                 if (level > last_enabled_level)
2064                         wm->enable = false;
2065                 else if (!ilk_validate_wm_level(level, max, wm))
2066                         /* make sure all following levels get disabled */
2067                         last_enabled_level = level - 1;
2068
2069                 /*
2070                  * The spec says it is preferred to disable
2071                  * FBC WMs instead of disabling a WM level.
2072                  */
2073                 if (wm->fbc_val > max->fbc) {
2074                         if (wm->enable)
2075                                 merged->fbc_wm_enabled = false;
2076                         wm->fbc_val = 0;
2077                 }
2078         }
2079
2080         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2081         /*
2082          * FIXME this is racy. FBC might get enabled later.
2083          * What we should check here is whether FBC can be
2084          * enabled sometime later.
2085          */
2086         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2087                 for (level = 2; level <= max_level; level++) {
2088                         struct intel_wm_level *wm = &merged->wm[level];
2089
2090                         wm->enable = false;
2091                 }
2092         }
2093 }
2094
2095 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2096 {
2097         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2098         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2099 }
2100
2101 /* The value we need to program into the WM_LPx latency field */
2102 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2103 {
2104         struct drm_i915_private *dev_priv = dev->dev_private;
2105
2106         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2107                 return 2 * level;
2108         else
2109                 return dev_priv->wm.pri_latency[level];
2110 }
2111
2112 static void ilk_compute_wm_results(struct drm_device *dev,
2113                                    const struct intel_pipe_wm *merged,
2114                                    enum intel_ddb_partitioning partitioning,
2115                                    struct ilk_wm_values *results)
2116 {
2117         struct intel_crtc *intel_crtc;
2118         int level, wm_lp;
2119
2120         results->enable_fbc_wm = merged->fbc_wm_enabled;
2121         results->partitioning = partitioning;
2122
2123         /* LP1+ register values */
2124         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2125                 const struct intel_wm_level *r;
2126
2127                 level = ilk_wm_lp_to_level(wm_lp, merged);
2128
2129                 r = &merged->wm[level];
2130
2131                 /*
2132                  * Maintain the watermark values even if the level is
2133                  * disabled. Doing otherwise could cause underruns.
2134                  */
2135                 results->wm_lp[wm_lp - 1] =
2136                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2137                         (r->pri_val << WM1_LP_SR_SHIFT) |
2138                         r->cur_val;
2139
2140                 if (r->enable)
2141                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2142
2143                 if (INTEL_INFO(dev)->gen >= 8)
2144                         results->wm_lp[wm_lp - 1] |=
2145                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2146                 else
2147                         results->wm_lp[wm_lp - 1] |=
2148                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2149
2150                 /*
2151                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2152                  * level is disabled. Doing otherwise could cause underruns.
2153                  */
2154                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2155                         WARN_ON(wm_lp != 1);
2156                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2157                 } else
2158                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2159         }
2160
2161         /* LP0 register values */
2162         for_each_intel_crtc(dev, intel_crtc) {
2163                 enum pipe pipe = intel_crtc->pipe;
2164                 const struct intel_wm_level *r =
2165                         &intel_crtc->wm.active.wm[0];
2166
2167                 if (WARN_ON(!r->enable))
2168                         continue;
2169
2170                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2171
2172                 results->wm_pipe[pipe] =
2173                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2174                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2175                         r->cur_val;
2176         }
2177 }
2178
2179 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2180  * case both are at the same level. Prefer r1 in case they're the same. */
2181 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2182                                                   struct intel_pipe_wm *r1,
2183                                                   struct intel_pipe_wm *r2)
2184 {
2185         int level, max_level = ilk_wm_max_level(dev);
2186         int level1 = 0, level2 = 0;
2187
2188         for (level = 1; level <= max_level; level++) {
2189                 if (r1->wm[level].enable)
2190                         level1 = level;
2191                 if (r2->wm[level].enable)
2192                         level2 = level;
2193         }
2194
2195         if (level1 == level2) {
2196                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2197                         return r2;
2198                 else
2199                         return r1;
2200         } else if (level1 > level2) {
2201                 return r1;
2202         } else {
2203                 return r2;
2204         }
2205 }
2206
2207 /* dirty bits used to track which watermarks need changes */
2208 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2209 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2210 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2211 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2212 #define WM_DIRTY_FBC (1 << 24)
2213 #define WM_DIRTY_DDB (1 << 25)
2214
2215 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2216                                          const struct ilk_wm_values *old,
2217                                          const struct ilk_wm_values *new)
2218 {
2219         unsigned int dirty = 0;
2220         enum pipe pipe;
2221         int wm_lp;
2222
2223         for_each_pipe(dev_priv, pipe) {
2224                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2225                         dirty |= WM_DIRTY_LINETIME(pipe);
2226                         /* Must disable LP1+ watermarks too */
2227                         dirty |= WM_DIRTY_LP_ALL;
2228                 }
2229
2230                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2231                         dirty |= WM_DIRTY_PIPE(pipe);
2232                         /* Must disable LP1+ watermarks too */
2233                         dirty |= WM_DIRTY_LP_ALL;
2234                 }
2235         }
2236
2237         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2238                 dirty |= WM_DIRTY_FBC;
2239                 /* Must disable LP1+ watermarks too */
2240                 dirty |= WM_DIRTY_LP_ALL;
2241         }
2242
2243         if (old->partitioning != new->partitioning) {
2244                 dirty |= WM_DIRTY_DDB;
2245                 /* Must disable LP1+ watermarks too */
2246                 dirty |= WM_DIRTY_LP_ALL;
2247         }
2248
2249         /* LP1+ watermarks already deemed dirty, no need to continue */
2250         if (dirty & WM_DIRTY_LP_ALL)
2251                 return dirty;
2252
2253         /* Find the lowest numbered LP1+ watermark in need of an update... */
2254         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2255                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2256                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2257                         break;
2258         }
2259
2260         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2261         for (; wm_lp <= 3; wm_lp++)
2262                 dirty |= WM_DIRTY_LP(wm_lp);
2263
2264         return dirty;
2265 }
2266
2267 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2268                                unsigned int dirty)
2269 {
2270         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2271         bool changed = false;
2272
2273         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2274                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2275                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2276                 changed = true;
2277         }
2278         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2279                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2280                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2281                 changed = true;
2282         }
2283         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2284                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2285                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2286                 changed = true;
2287         }
2288
2289         /*
2290          * Don't touch WM1S_LP_EN here.
2291          * Doing so could cause underruns.
2292          */
2293
2294         return changed;
2295 }
2296
2297 /*
2298  * The spec says we shouldn't write when we don't need, because every write
2299  * causes WMs to be re-evaluated, expending some power.
2300  */
2301 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2302                                 struct ilk_wm_values *results)
2303 {
2304         struct drm_device *dev = dev_priv->dev;
2305         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2306         unsigned int dirty;
2307         uint32_t val;
2308
2309         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2310         if (!dirty)
2311                 return;
2312
2313         _ilk_disable_lp_wm(dev_priv, dirty);
2314
2315         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2316                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2317         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2318                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2319         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2320                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2321
2322         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2323                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2324         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2325                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2326         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2327                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2328
2329         if (dirty & WM_DIRTY_DDB) {
2330                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2331                         val = I915_READ(WM_MISC);
2332                         if (results->partitioning == INTEL_DDB_PART_1_2)
2333                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2334                         else
2335                                 val |= WM_MISC_DATA_PARTITION_5_6;
2336                         I915_WRITE(WM_MISC, val);
2337                 } else {
2338                         val = I915_READ(DISP_ARB_CTL2);
2339                         if (results->partitioning == INTEL_DDB_PART_1_2)
2340                                 val &= ~DISP_DATA_PARTITION_5_6;
2341                         else
2342                                 val |= DISP_DATA_PARTITION_5_6;
2343                         I915_WRITE(DISP_ARB_CTL2, val);
2344                 }
2345         }
2346
2347         if (dirty & WM_DIRTY_FBC) {
2348                 val = I915_READ(DISP_ARB_CTL);
2349                 if (results->enable_fbc_wm)
2350                         val &= ~DISP_FBC_WM_DIS;
2351                 else
2352                         val |= DISP_FBC_WM_DIS;
2353                 I915_WRITE(DISP_ARB_CTL, val);
2354         }
2355
2356         if (dirty & WM_DIRTY_LP(1) &&
2357             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2358                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2359
2360         if (INTEL_INFO(dev)->gen >= 7) {
2361                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2362                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2363                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2364                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2365         }
2366
2367         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2368                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2369         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2370                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2371         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2372                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2373
2374         dev_priv->wm.hw = *results;
2375 }
2376
2377 static bool ilk_disable_lp_wm(struct drm_device *dev)
2378 {
2379         struct drm_i915_private *dev_priv = dev->dev_private;
2380
2381         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2382 }
2383
2384 /*
2385  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2386  * different active planes.
2387  */
2388
2389 #define SKL_DDB_SIZE            896     /* in blocks */
2390
2391 static void
2392 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2393                                    struct drm_crtc *for_crtc,
2394                                    const struct intel_wm_config *config,
2395                                    const struct skl_pipe_wm_parameters *params,
2396                                    struct skl_ddb_entry *alloc /* out */)
2397 {
2398         struct drm_crtc *crtc;
2399         unsigned int pipe_size, ddb_size;
2400         int nth_active_pipe;
2401
2402         if (!params->active) {
2403                 alloc->start = 0;
2404                 alloc->end = 0;
2405                 return;
2406         }
2407
2408         ddb_size = SKL_DDB_SIZE;
2409
2410         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2411
2412         nth_active_pipe = 0;
2413         for_each_crtc(dev, crtc) {
2414                 if (!intel_crtc_active(crtc))
2415                         continue;
2416
2417                 if (crtc == for_crtc)
2418                         break;
2419
2420                 nth_active_pipe++;
2421         }
2422
2423         pipe_size = ddb_size / config->num_pipes_active;
2424         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2425         alloc->end = alloc->start + pipe_size;
2426 }
2427
2428 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2429 {
2430         if (config->num_pipes_active == 1)
2431                 return 32;
2432
2433         return 8;
2434 }
2435
2436 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2437 {
2438         entry->start = reg & 0x3ff;
2439         entry->end = (reg >> 16) & 0x3ff;
2440         if (entry->end)
2441                 entry->end += 1;
2442 }
2443
2444 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2445                           struct skl_ddb_allocation *ddb /* out */)
2446 {
2447         struct drm_device *dev = dev_priv->dev;
2448         enum pipe pipe;
2449         int plane;
2450         u32 val;
2451
2452         for_each_pipe(dev_priv, pipe) {
2453                 for_each_plane(pipe, plane) {
2454                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2455                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2456                                                    val);
2457                 }
2458
2459                 val = I915_READ(CUR_BUF_CFG(pipe));
2460                 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2461         }
2462 }
2463
2464 static unsigned int
2465 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
2466 {
2467         return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2468 }
2469
2470 /*
2471  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2472  * a 8192x4096@32bpp framebuffer:
2473  *   3 * 4096 * 8192  * 4 < 2^32
2474  */
2475 static unsigned int
2476 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2477                                  const struct skl_pipe_wm_parameters *params)
2478 {
2479         unsigned int total_data_rate = 0;
2480         int plane;
2481
2482         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2483                 const struct intel_plane_wm_parameters *p;
2484
2485                 p = &params->plane[plane];
2486                 if (!p->enabled)
2487                         continue;
2488
2489                 total_data_rate += skl_plane_relative_data_rate(p);
2490         }
2491
2492         return total_data_rate;
2493 }
2494
2495 static void
2496 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2497                       const struct intel_wm_config *config,
2498                       const struct skl_pipe_wm_parameters *params,
2499                       struct skl_ddb_allocation *ddb /* out */)
2500 {
2501         struct drm_device *dev = crtc->dev;
2502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503         enum pipe pipe = intel_crtc->pipe;
2504         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2505         uint16_t alloc_size, start, cursor_blocks;
2506         unsigned int total_data_rate;
2507         int plane;
2508
2509         skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2510         alloc_size = skl_ddb_entry_size(alloc);
2511         if (alloc_size == 0) {
2512                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2513                 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2514                 return;
2515         }
2516
2517         cursor_blocks = skl_cursor_allocation(config);
2518         ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2519         ddb->cursor[pipe].end = alloc->end;
2520
2521         alloc_size -= cursor_blocks;
2522         alloc->end -= cursor_blocks;
2523
2524         /*
2525          * Each active plane get a portion of the remaining space, in
2526          * proportion to the amount of data they need to fetch from memory.
2527          *
2528          * FIXME: we may not allocate every single block here.
2529          */
2530         total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2531
2532         start = alloc->start;
2533         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2534                 const struct intel_plane_wm_parameters *p;
2535                 unsigned int data_rate;
2536                 uint16_t plane_blocks;
2537
2538                 p = &params->plane[plane];
2539                 if (!p->enabled)
2540                         continue;
2541
2542                 data_rate = skl_plane_relative_data_rate(p);
2543
2544                 /*
2545                  * promote the expression to 64 bits to avoid overflowing, the
2546                  * result is < available as data_rate / total_data_rate < 1
2547                  */
2548                 plane_blocks = div_u64((uint64_t)alloc_size * data_rate,
2549                                        total_data_rate);
2550
2551                 ddb->plane[pipe][plane].start = start;
2552                 ddb->plane[pipe][plane].end = start + plane_blocks;
2553
2554                 start += plane_blocks;
2555         }
2556
2557 }
2558
2559 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_config *config)
2560 {
2561         /* TODO: Take into account the scalers once we support them */
2562         return config->adjusted_mode.crtc_clock;
2563 }
2564
2565 /*
2566  * The max latency should be 257 (max the punit can code is 255 and we add 2us
2567  * for the read latency) and bytes_per_pixel should always be <= 8, so that
2568  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2569  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2570 */
2571 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2572                                uint32_t latency)
2573 {
2574         uint32_t wm_intermediate_val, ret;
2575
2576         if (latency == 0)
2577                 return UINT_MAX;
2578
2579         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel;
2580         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2581
2582         return ret;
2583 }
2584
2585 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2586                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2587                                uint32_t latency)
2588 {
2589         uint32_t ret, plane_bytes_per_line, wm_intermediate_val;
2590
2591         if (latency == 0)
2592                 return UINT_MAX;
2593
2594         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
2595         wm_intermediate_val = latency * pixel_rate;
2596         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
2597                                 plane_bytes_per_line;
2598
2599         return ret;
2600 }
2601
2602 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2603                                        const struct intel_crtc *intel_crtc)
2604 {
2605         struct drm_device *dev = intel_crtc->base.dev;
2606         struct drm_i915_private *dev_priv = dev->dev_private;
2607         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2608         enum pipe pipe = intel_crtc->pipe;
2609
2610         if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2611                    sizeof(new_ddb->plane[pipe])))
2612                 return true;
2613
2614         if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2615                     sizeof(new_ddb->cursor[pipe])))
2616                 return true;
2617
2618         return false;
2619 }
2620
2621 static void skl_compute_wm_global_parameters(struct drm_device *dev,
2622                                              struct intel_wm_config *config)
2623 {
2624         struct drm_crtc *crtc;
2625         struct drm_plane *plane;
2626
2627         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2628                 config->num_pipes_active += intel_crtc_active(crtc);
2629
2630         /* FIXME: I don't think we need those two global parameters on SKL */
2631         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2632                 struct intel_plane *intel_plane = to_intel_plane(plane);
2633
2634                 config->sprites_enabled |= intel_plane->wm.enabled;
2635                 config->sprites_scaled |= intel_plane->wm.scaled;
2636         }
2637 }
2638
2639 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2640                                            struct skl_pipe_wm_parameters *p)
2641 {
2642         struct drm_device *dev = crtc->dev;
2643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2644         enum pipe pipe = intel_crtc->pipe;
2645         struct drm_plane *plane;
2646         int i = 1; /* Index for sprite planes start */
2647
2648         p->active = intel_crtc_active(crtc);
2649         if (p->active) {
2650                 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2651                 p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config);
2652
2653                 /*
2654                  * For now, assume primary and cursor planes are always enabled.
2655                  */
2656                 p->plane[0].enabled = true;
2657                 p->plane[0].bytes_per_pixel =
2658                         crtc->primary->fb->bits_per_pixel / 8;
2659                 p->plane[0].horiz_pixels = intel_crtc->config.pipe_src_w;
2660                 p->plane[0].vert_pixels = intel_crtc->config.pipe_src_h;
2661
2662                 p->cursor.enabled = true;
2663                 p->cursor.bytes_per_pixel = 4;
2664                 p->cursor.horiz_pixels = intel_crtc->cursor_width ?
2665                                          intel_crtc->cursor_width : 64;
2666         }
2667
2668         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2669                 struct intel_plane *intel_plane = to_intel_plane(plane);
2670
2671                 if (intel_plane->pipe == pipe &&
2672                         plane->type == DRM_PLANE_TYPE_OVERLAY)
2673                         p->plane[i++] = intel_plane->wm;
2674         }
2675 }
2676
2677 static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p,
2678                                  struct intel_plane_wm_parameters *p_params,
2679                                  uint16_t ddb_allocation,
2680                                  uint32_t mem_value,
2681                                  uint16_t *out_blocks, /* out */
2682                                  uint8_t *out_lines /* out */)
2683 {
2684         uint32_t method1, method2, plane_bytes_per_line, res_blocks, res_lines;
2685         uint32_t result_bytes;
2686
2687         if (mem_value == 0 || !p->active || !p_params->enabled)
2688                 return false;
2689
2690         method1 = skl_wm_method1(p->pixel_rate,
2691                                  p_params->bytes_per_pixel,
2692                                  mem_value);
2693         method2 = skl_wm_method2(p->pixel_rate,
2694                                  p->pipe_htotal,
2695                                  p_params->horiz_pixels,
2696                                  p_params->bytes_per_pixel,
2697                                  mem_value);
2698
2699         plane_bytes_per_line = p_params->horiz_pixels *
2700                                         p_params->bytes_per_pixel;
2701
2702         /* For now xtile and linear */
2703         if (((ddb_allocation * 512) / plane_bytes_per_line) >= 1)
2704                 result_bytes = min(method1, method2);
2705         else
2706                 result_bytes = method1;
2707
2708         res_blocks = DIV_ROUND_UP(result_bytes, 512) + 1;
2709         res_lines = DIV_ROUND_UP(result_bytes, plane_bytes_per_line);
2710
2711         if (res_blocks > ddb_allocation || res_lines > 31)
2712                 return false;
2713
2714         *out_blocks = res_blocks;
2715         *out_lines = res_lines;
2716
2717         return true;
2718 }
2719
2720 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
2721                                  struct skl_ddb_allocation *ddb,
2722                                  struct skl_pipe_wm_parameters *p,
2723                                  enum pipe pipe,
2724                                  int level,
2725                                  int num_planes,
2726                                  struct skl_wm_level *result)
2727 {
2728         uint16_t latency = dev_priv->wm.skl_latency[level];
2729         uint16_t ddb_blocks;
2730         int i;
2731
2732         for (i = 0; i < num_planes; i++) {
2733                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2734
2735                 result->plane_en[i] = skl_compute_plane_wm(p, &p->plane[i],
2736                                                 ddb_blocks,
2737                                                 latency,
2738                                                 &result->plane_res_b[i],
2739                                                 &result->plane_res_l[i]);
2740         }
2741
2742         ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
2743         result->cursor_en = skl_compute_plane_wm(p, &p->cursor, ddb_blocks,
2744                                                  latency, &result->cursor_res_b,
2745                                                  &result->cursor_res_l);
2746 }
2747
2748 static uint32_t
2749 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
2750 {
2751         if (!intel_crtc_active(crtc))
2752                 return 0;
2753
2754         return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
2755
2756 }
2757
2758 static void skl_compute_transition_wm(struct drm_crtc *crtc,
2759                                       struct skl_pipe_wm_parameters *params,
2760                                       struct skl_wm_level *trans_wm /* out */)
2761 {
2762         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2763         int i;
2764
2765         if (!params->active)
2766                 return;
2767
2768         /* Until we know more, just disable transition WMs */
2769         for (i = 0; i < intel_num_planes(intel_crtc); i++)
2770                 trans_wm->plane_en[i] = false;
2771         trans_wm->cursor_en = false;
2772 }
2773
2774 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
2775                                 struct skl_ddb_allocation *ddb,
2776                                 struct skl_pipe_wm_parameters *params,
2777                                 struct skl_pipe_wm *pipe_wm)
2778 {
2779         struct drm_device *dev = crtc->dev;
2780         const struct drm_i915_private *dev_priv = dev->dev_private;
2781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782         int level, max_level = ilk_wm_max_level(dev);
2783
2784         for (level = 0; level <= max_level; level++) {
2785                 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
2786                                      level, intel_num_planes(intel_crtc),
2787                                      &pipe_wm->wm[level]);
2788         }
2789         pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
2790
2791         skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2792 }
2793
2794 static void skl_compute_wm_results(struct drm_device *dev,
2795                                    struct skl_pipe_wm_parameters *p,
2796                                    struct skl_pipe_wm *p_wm,
2797                                    struct skl_wm_values *r,
2798                                    struct intel_crtc *intel_crtc)
2799 {
2800         int level, max_level = ilk_wm_max_level(dev);
2801         enum pipe pipe = intel_crtc->pipe;
2802         uint32_t temp;
2803         int i;
2804
2805         for (level = 0; level <= max_level; level++) {
2806                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
2807                         temp = 0;
2808
2809                         temp |= p_wm->wm[level].plane_res_l[i] <<
2810                                         PLANE_WM_LINES_SHIFT;
2811                         temp |= p_wm->wm[level].plane_res_b[i];
2812                         if (p_wm->wm[level].plane_en[i])
2813                                 temp |= PLANE_WM_EN;
2814
2815                         r->plane[pipe][i][level] = temp;
2816                 }
2817
2818                 temp = 0;
2819
2820                 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
2821                 temp |= p_wm->wm[level].cursor_res_b;
2822
2823                 if (p_wm->wm[level].cursor_en)
2824                         temp |= PLANE_WM_EN;
2825
2826                 r->cursor[pipe][level] = temp;
2827
2828         }
2829
2830         /* transition WMs */
2831         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
2832                 temp = 0;
2833                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
2834                 temp |= p_wm->trans_wm.plane_res_b[i];
2835                 if (p_wm->trans_wm.plane_en[i])
2836                         temp |= PLANE_WM_EN;
2837
2838                 r->plane_trans[pipe][i] = temp;
2839         }
2840
2841         temp = 0;
2842         temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
2843         temp |= p_wm->trans_wm.cursor_res_b;
2844         if (p_wm->trans_wm.cursor_en)
2845                 temp |= PLANE_WM_EN;
2846
2847         r->cursor_trans[pipe] = temp;
2848
2849         r->wm_linetime[pipe] = p_wm->linetime;
2850 }
2851
2852 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
2853                                 const struct skl_ddb_entry *entry)
2854 {
2855         if (entry->end)
2856                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
2857         else
2858                 I915_WRITE(reg, 0);
2859 }
2860
2861 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
2862                                 const struct skl_wm_values *new)
2863 {
2864         struct drm_device *dev = dev_priv->dev;
2865         struct intel_crtc *crtc;
2866
2867         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2868                 int i, level, max_level = ilk_wm_max_level(dev);
2869                 enum pipe pipe = crtc->pipe;
2870
2871                 if (!new->dirty[pipe])
2872                         continue;
2873
2874                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
2875
2876                 for (level = 0; level <= max_level; level++) {
2877                         for (i = 0; i < intel_num_planes(crtc); i++)
2878                                 I915_WRITE(PLANE_WM(pipe, i, level),
2879                                            new->plane[pipe][i][level]);
2880                         I915_WRITE(CUR_WM(pipe, level),
2881                                    new->cursor[pipe][level]);
2882                 }
2883                 for (i = 0; i < intel_num_planes(crtc); i++)
2884                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
2885                                    new->plane_trans[pipe][i]);
2886                 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
2887
2888                 for (i = 0; i < intel_num_planes(crtc); i++)
2889                         skl_ddb_entry_write(dev_priv,
2890                                             PLANE_BUF_CFG(pipe, i),
2891                                             &new->ddb.plane[pipe][i]);
2892
2893                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
2894                                     &new->ddb.cursor[pipe]);
2895         }
2896 }
2897
2898 /*
2899  * When setting up a new DDB allocation arrangement, we need to correctly
2900  * sequence the times at which the new allocations for the pipes are taken into
2901  * account or we'll have pipes fetching from space previously allocated to
2902  * another pipe.
2903  *
2904  * Roughly the sequence looks like:
2905  *  1. re-allocate the pipe(s) with the allocation being reduced and not
2906  *     overlapping with a previous light-up pipe (another way to put it is:
2907  *     pipes with their new allocation strickly included into their old ones).
2908  *  2. re-allocate the other pipes that get their allocation reduced
2909  *  3. allocate the pipes having their allocation increased
2910  *
2911  * Steps 1. and 2. are here to take care of the following case:
2912  * - Initially DDB looks like this:
2913  *     |   B    |   C    |
2914  * - enable pipe A.
2915  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
2916  *   allocation
2917  *     |  A  |  B  |  C  |
2918  *
2919  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
2920  */
2921
2922 static void
2923 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
2924 {
2925         struct drm_device *dev = dev_priv->dev;
2926         int plane;
2927
2928         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
2929
2930         for_each_plane(pipe, plane) {
2931                 I915_WRITE(PLANE_SURF(pipe, plane),
2932                            I915_READ(PLANE_SURF(pipe, plane)));
2933         }
2934         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
2935 }
2936
2937 static bool
2938 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
2939                             const struct skl_ddb_allocation *new,
2940                             enum pipe pipe)
2941 {
2942         uint16_t old_size, new_size;
2943
2944         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
2945         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
2946
2947         return old_size != new_size &&
2948                new->pipe[pipe].start >= old->pipe[pipe].start &&
2949                new->pipe[pipe].end <= old->pipe[pipe].end;
2950 }
2951
2952 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
2953                                 struct skl_wm_values *new_values)
2954 {
2955         struct drm_device *dev = dev_priv->dev;
2956         struct skl_ddb_allocation *cur_ddb, *new_ddb;
2957         bool reallocated[I915_MAX_PIPES] = {false, false, false};
2958         struct intel_crtc *crtc;
2959         enum pipe pipe;
2960
2961         new_ddb = &new_values->ddb;
2962         cur_ddb = &dev_priv->wm.skl_hw.ddb;
2963
2964         /*
2965          * First pass: flush the pipes with the new allocation contained into
2966          * the old space.
2967          *
2968          * We'll wait for the vblank on those pipes to ensure we can safely
2969          * re-allocate the freed space without this pipe fetching from it.
2970          */
2971         for_each_intel_crtc(dev, crtc) {
2972                 if (!crtc->active)
2973                         continue;
2974
2975                 pipe = crtc->pipe;
2976
2977                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
2978                         continue;
2979
2980                 skl_wm_flush_pipe(dev_priv, pipe, 1);
2981                 intel_wait_for_vblank(dev, pipe);
2982
2983                 reallocated[pipe] = true;
2984         }
2985
2986
2987         /*
2988          * Second pass: flush the pipes that are having their allocation
2989          * reduced, but overlapping with a previous allocation.
2990          *
2991          * Here as well we need to wait for the vblank to make sure the freed
2992          * space is not used anymore.
2993          */
2994         for_each_intel_crtc(dev, crtc) {
2995                 if (!crtc->active)
2996                         continue;
2997
2998                 pipe = crtc->pipe;
2999
3000                 if (reallocated[pipe])
3001                         continue;
3002
3003                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3004                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3005                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3006                         intel_wait_for_vblank(dev, pipe);
3007                         reallocated[pipe] = true;
3008                 }
3009         }
3010
3011         /*
3012          * Third pass: flush the pipes that got more space allocated.
3013          *
3014          * We don't need to actively wait for the update here, next vblank
3015          * will just get more DDB space with the correct WM values.
3016          */
3017         for_each_intel_crtc(dev, crtc) {
3018                 if (!crtc->active)
3019                         continue;
3020
3021                 pipe = crtc->pipe;
3022
3023                 /*
3024                  * At this point, only the pipes more space than before are
3025                  * left to re-allocate.
3026                  */
3027                 if (reallocated[pipe])
3028                         continue;
3029
3030                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3031         }
3032 }
3033
3034 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3035                                struct skl_pipe_wm_parameters *params,
3036                                struct intel_wm_config *config,
3037                                struct skl_ddb_allocation *ddb, /* out */
3038                                struct skl_pipe_wm *pipe_wm /* out */)
3039 {
3040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3041
3042         skl_compute_wm_pipe_parameters(crtc, params);
3043         skl_allocate_pipe_ddb(crtc, config, params, ddb);
3044         skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3045
3046         if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3047                 return false;
3048
3049         intel_crtc->wm.skl_active = *pipe_wm;
3050         return true;
3051 }
3052
3053 static void skl_update_other_pipe_wm(struct drm_device *dev,
3054                                      struct drm_crtc *crtc,
3055                                      struct intel_wm_config *config,
3056                                      struct skl_wm_values *r)
3057 {
3058         struct intel_crtc *intel_crtc;
3059         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3060
3061         /*
3062          * If the WM update hasn't changed the allocation for this_crtc (the
3063          * crtc we are currently computing the new WM values for), other
3064          * enabled crtcs will keep the same allocation and we don't need to
3065          * recompute anything for them.
3066          */
3067         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3068                 return;
3069
3070         /*
3071          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3072          * other active pipes need new DDB allocation and WM values.
3073          */
3074         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3075                                 base.head) {
3076                 struct skl_pipe_wm_parameters params = {};
3077                 struct skl_pipe_wm pipe_wm = {};
3078                 bool wm_changed;
3079
3080                 if (this_crtc->pipe == intel_crtc->pipe)
3081                         continue;
3082
3083                 if (!intel_crtc->active)
3084                         continue;
3085
3086                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3087                                                 &params, config,
3088                                                 &r->ddb, &pipe_wm);
3089
3090                 /*
3091                  * If we end up re-computing the other pipe WM values, it's
3092                  * because it was really needed, so we expect the WM values to
3093                  * be different.
3094                  */
3095                 WARN_ON(!wm_changed);
3096
3097                 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3098                 r->dirty[intel_crtc->pipe] = true;
3099         }
3100 }
3101
3102 static void skl_update_wm(struct drm_crtc *crtc)
3103 {
3104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3105         struct drm_device *dev = crtc->dev;
3106         struct drm_i915_private *dev_priv = dev->dev_private;
3107         struct skl_pipe_wm_parameters params = {};
3108         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3109         struct skl_pipe_wm pipe_wm = {};
3110         struct intel_wm_config config = {};
3111
3112         memset(results, 0, sizeof(*results));
3113
3114         skl_compute_wm_global_parameters(dev, &config);
3115
3116         if (!skl_update_pipe_wm(crtc, &params, &config,
3117                                 &results->ddb, &pipe_wm))
3118                 return;
3119
3120         skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3121         results->dirty[intel_crtc->pipe] = true;
3122
3123         skl_update_other_pipe_wm(dev, crtc, &config, results);
3124         skl_write_wm_values(dev_priv, results);
3125         skl_flush_wm_values(dev_priv, results);
3126
3127         /* store the new configuration */
3128         dev_priv->wm.skl_hw = *results;
3129 }
3130
3131 static void
3132 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3133                      uint32_t sprite_width, uint32_t sprite_height,
3134                      int pixel_size, bool enabled, bool scaled)
3135 {
3136         struct intel_plane *intel_plane = to_intel_plane(plane);
3137
3138         intel_plane->wm.enabled = enabled;
3139         intel_plane->wm.scaled = scaled;
3140         intel_plane->wm.horiz_pixels = sprite_width;
3141         intel_plane->wm.vert_pixels = sprite_height;
3142         intel_plane->wm.bytes_per_pixel = pixel_size;
3143
3144         skl_update_wm(crtc);
3145 }
3146
3147 static void ilk_update_wm(struct drm_crtc *crtc)
3148 {
3149         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3150         struct drm_device *dev = crtc->dev;
3151         struct drm_i915_private *dev_priv = dev->dev_private;
3152         struct ilk_wm_maximums max;
3153         struct ilk_pipe_wm_parameters params = {};
3154         struct ilk_wm_values results = {};
3155         enum intel_ddb_partitioning partitioning;
3156         struct intel_pipe_wm pipe_wm = {};
3157         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3158         struct intel_wm_config config = {};
3159
3160         ilk_compute_wm_parameters(crtc, &params);
3161
3162         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3163
3164         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3165                 return;
3166
3167         intel_crtc->wm.active = pipe_wm;
3168
3169         ilk_compute_wm_config(dev, &config);
3170
3171         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3172         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3173
3174         /* 5/6 split only in single pipe config on IVB+ */
3175         if (INTEL_INFO(dev)->gen >= 7 &&
3176             config.num_pipes_active == 1 && config.sprites_enabled) {
3177                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3178                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3179
3180                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3181         } else {
3182                 best_lp_wm = &lp_wm_1_2;
3183         }
3184
3185         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3186                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3187
3188         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3189
3190         ilk_write_wm_values(dev_priv, &results);
3191 }
3192
3193 static void
3194 ilk_update_sprite_wm(struct drm_plane *plane,
3195                      struct drm_crtc *crtc,
3196                      uint32_t sprite_width, uint32_t sprite_height,
3197                      int pixel_size, bool enabled, bool scaled)
3198 {
3199         struct drm_device *dev = plane->dev;
3200         struct intel_plane *intel_plane = to_intel_plane(plane);
3201
3202         intel_plane->wm.enabled = enabled;
3203         intel_plane->wm.scaled = scaled;
3204         intel_plane->wm.horiz_pixels = sprite_width;
3205         intel_plane->wm.vert_pixels = sprite_width;
3206         intel_plane->wm.bytes_per_pixel = pixel_size;
3207
3208         /*
3209          * IVB workaround: must disable low power watermarks for at least
3210          * one frame before enabling scaling.  LP watermarks can be re-enabled
3211          * when scaling is disabled.
3212          *
3213          * WaCxSRDisabledForSpriteScaling:ivb
3214          */
3215         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3216                 intel_wait_for_vblank(dev, intel_plane->pipe);
3217
3218         ilk_update_wm(crtc);
3219 }
3220
3221 static void skl_pipe_wm_active_state(uint32_t val,
3222                                      struct skl_pipe_wm *active,
3223                                      bool is_transwm,
3224                                      bool is_cursor,
3225                                      int i,
3226                                      int level)
3227 {
3228         bool is_enabled = (val & PLANE_WM_EN) != 0;
3229
3230         if (!is_transwm) {
3231                 if (!is_cursor) {
3232                         active->wm[level].plane_en[i] = is_enabled;
3233                         active->wm[level].plane_res_b[i] =
3234                                         val & PLANE_WM_BLOCKS_MASK;
3235                         active->wm[level].plane_res_l[i] =
3236                                         (val >> PLANE_WM_LINES_SHIFT) &
3237                                                 PLANE_WM_LINES_MASK;
3238                 } else {
3239                         active->wm[level].cursor_en = is_enabled;
3240                         active->wm[level].cursor_res_b =
3241                                         val & PLANE_WM_BLOCKS_MASK;
3242                         active->wm[level].cursor_res_l =
3243                                         (val >> PLANE_WM_LINES_SHIFT) &
3244                                                 PLANE_WM_LINES_MASK;
3245                 }
3246         } else {
3247                 if (!is_cursor) {
3248                         active->trans_wm.plane_en[i] = is_enabled;
3249                         active->trans_wm.plane_res_b[i] =
3250                                         val & PLANE_WM_BLOCKS_MASK;
3251                         active->trans_wm.plane_res_l[i] =
3252                                         (val >> PLANE_WM_LINES_SHIFT) &
3253                                                 PLANE_WM_LINES_MASK;
3254                 } else {
3255                         active->trans_wm.cursor_en = is_enabled;
3256                         active->trans_wm.cursor_res_b =
3257                                         val & PLANE_WM_BLOCKS_MASK;
3258                         active->trans_wm.cursor_res_l =
3259                                         (val >> PLANE_WM_LINES_SHIFT) &
3260                                                 PLANE_WM_LINES_MASK;
3261                 }
3262         }
3263 }
3264
3265 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3266 {
3267         struct drm_device *dev = crtc->dev;
3268         struct drm_i915_private *dev_priv = dev->dev_private;
3269         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271         struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3272         enum pipe pipe = intel_crtc->pipe;
3273         int level, i, max_level;
3274         uint32_t temp;
3275
3276         max_level = ilk_wm_max_level(dev);
3277
3278         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3279
3280         for (level = 0; level <= max_level; level++) {
3281                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3282                         hw->plane[pipe][i][level] =
3283                                         I915_READ(PLANE_WM(pipe, i, level));
3284                 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3285         }
3286
3287         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3288                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3289         hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3290
3291         if (!intel_crtc_active(crtc))
3292                 return;
3293
3294         hw->dirty[pipe] = true;
3295
3296         active->linetime = hw->wm_linetime[pipe];
3297
3298         for (level = 0; level <= max_level; level++) {
3299                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3300                         temp = hw->plane[pipe][i][level];
3301                         skl_pipe_wm_active_state(temp, active, false,
3302                                                 false, i, level);
3303                 }
3304                 temp = hw->cursor[pipe][level];
3305                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3306         }
3307
3308         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3309                 temp = hw->plane_trans[pipe][i];
3310                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3311         }
3312
3313         temp = hw->cursor_trans[pipe];
3314         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3315 }
3316
3317 void skl_wm_get_hw_state(struct drm_device *dev)
3318 {
3319         struct drm_i915_private *dev_priv = dev->dev_private;
3320         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3321         struct drm_crtc *crtc;
3322
3323         skl_ddb_get_hw_state(dev_priv, ddb);
3324         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3325                 skl_pipe_wm_get_hw_state(crtc);
3326 }
3327
3328 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3329 {
3330         struct drm_device *dev = crtc->dev;
3331         struct drm_i915_private *dev_priv = dev->dev_private;
3332         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3334         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3335         enum pipe pipe = intel_crtc->pipe;
3336         static const unsigned int wm0_pipe_reg[] = {
3337                 [PIPE_A] = WM0_PIPEA_ILK,
3338                 [PIPE_B] = WM0_PIPEB_ILK,
3339                 [PIPE_C] = WM0_PIPEC_IVB,
3340         };
3341
3342         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3343         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3344                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3345
3346         active->pipe_enabled = intel_crtc_active(crtc);
3347
3348         if (active->pipe_enabled) {
3349                 u32 tmp = hw->wm_pipe[pipe];
3350
3351                 /*
3352                  * For active pipes LP0 watermark is marked as
3353                  * enabled, and LP1+ watermaks as disabled since
3354                  * we can't really reverse compute them in case
3355                  * multiple pipes are active.
3356                  */
3357                 active->wm[0].enable = true;
3358                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3359                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3360                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3361                 active->linetime = hw->wm_linetime[pipe];
3362         } else {
3363                 int level, max_level = ilk_wm_max_level(dev);
3364
3365                 /*
3366                  * For inactive pipes, all watermark levels
3367                  * should be marked as enabled but zeroed,
3368                  * which is what we'd compute them to.
3369                  */
3370                 for (level = 0; level <= max_level; level++)
3371                         active->wm[level].enable = true;
3372         }
3373 }
3374
3375 void ilk_wm_get_hw_state(struct drm_device *dev)
3376 {
3377         struct drm_i915_private *dev_priv = dev->dev_private;
3378         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3379         struct drm_crtc *crtc;
3380
3381         for_each_crtc(dev, crtc)
3382                 ilk_pipe_wm_get_hw_state(crtc);
3383
3384         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3385         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3386         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3387
3388         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3389         if (INTEL_INFO(dev)->gen >= 7) {
3390                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3391                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3392         }
3393
3394         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3395                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3396                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3397         else if (IS_IVYBRIDGE(dev))
3398                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3399                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3400
3401         hw->enable_fbc_wm =
3402                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3403 }
3404
3405 /**
3406  * intel_update_watermarks - update FIFO watermark values based on current modes
3407  *
3408  * Calculate watermark values for the various WM regs based on current mode
3409  * and plane configuration.
3410  *
3411  * There are several cases to deal with here:
3412  *   - normal (i.e. non-self-refresh)
3413  *   - self-refresh (SR) mode
3414  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3415  *   - lines are small relative to FIFO size (buffer can hold more than 2
3416  *     lines), so need to account for TLB latency
3417  *
3418  *   The normal calculation is:
3419  *     watermark = dotclock * bytes per pixel * latency
3420  *   where latency is platform & configuration dependent (we assume pessimal
3421  *   values here).
3422  *
3423  *   The SR calculation is:
3424  *     watermark = (trunc(latency/line time)+1) * surface width *
3425  *       bytes per pixel
3426  *   where
3427  *     line time = htotal / dotclock
3428  *     surface width = hdisplay for normal plane and 64 for cursor
3429  *   and latency is assumed to be high, as above.
3430  *
3431  * The final value programmed to the register should always be rounded up,
3432  * and include an extra 2 entries to account for clock crossings.
3433  *
3434  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3435  * to set the non-SR watermarks to 8.
3436  */
3437 void intel_update_watermarks(struct drm_crtc *crtc)
3438 {
3439         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3440
3441         if (dev_priv->display.update_wm)
3442                 dev_priv->display.update_wm(crtc);
3443 }
3444
3445 void intel_update_sprite_watermarks(struct drm_plane *plane,
3446                                     struct drm_crtc *crtc,
3447                                     uint32_t sprite_width,
3448                                     uint32_t sprite_height,
3449                                     int pixel_size,
3450                                     bool enabled, bool scaled)
3451 {
3452         struct drm_i915_private *dev_priv = plane->dev->dev_private;
3453
3454         if (dev_priv->display.update_sprite_wm)
3455                 dev_priv->display.update_sprite_wm(plane, crtc,
3456                                                    sprite_width, sprite_height,
3457                                                    pixel_size, enabled, scaled);
3458 }
3459
3460 static struct drm_i915_gem_object *
3461 intel_alloc_context_page(struct drm_device *dev)
3462 {
3463         struct drm_i915_gem_object *ctx;
3464         int ret;
3465
3466         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3467
3468         ctx = i915_gem_alloc_object(dev, 4096);
3469         if (!ctx) {
3470                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3471                 return NULL;
3472         }
3473
3474         ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
3475         if (ret) {
3476                 DRM_ERROR("failed to pin power context: %d\n", ret);
3477                 goto err_unref;
3478         }
3479
3480         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3481         if (ret) {
3482                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3483                 goto err_unpin;
3484         }
3485
3486         return ctx;
3487
3488 err_unpin:
3489         i915_gem_object_ggtt_unpin(ctx);
3490 err_unref:
3491         drm_gem_object_unreference(&ctx->base);
3492         return NULL;
3493 }
3494
3495 /**
3496  * Lock protecting IPS related data structures
3497  */
3498 DEFINE_SPINLOCK(mchdev_lock);
3499
3500 /* Global for IPS driver to get at the current i915 device. Protected by
3501  * mchdev_lock. */
3502 static struct drm_i915_private *i915_mch_dev;
3503
3504 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3505 {
3506         struct drm_i915_private *dev_priv = dev->dev_private;
3507         u16 rgvswctl;
3508
3509         assert_spin_locked(&mchdev_lock);
3510
3511         rgvswctl = I915_READ16(MEMSWCTL);
3512         if (rgvswctl & MEMCTL_CMD_STS) {
3513                 DRM_DEBUG("gpu busy, RCS change rejected\n");
3514                 return false; /* still busy with another command */
3515         }
3516
3517         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3518                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3519         I915_WRITE16(MEMSWCTL, rgvswctl);
3520         POSTING_READ16(MEMSWCTL);
3521
3522         rgvswctl |= MEMCTL_CMD_STS;
3523         I915_WRITE16(MEMSWCTL, rgvswctl);
3524
3525         return true;
3526 }
3527
3528 static void ironlake_enable_drps(struct drm_device *dev)
3529 {
3530         struct drm_i915_private *dev_priv = dev->dev_private;
3531         u32 rgvmodectl = I915_READ(MEMMODECTL);
3532         u8 fmax, fmin, fstart, vstart;
3533
3534         spin_lock_irq(&mchdev_lock);
3535
3536         /* Enable temp reporting */
3537         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3538         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3539
3540         /* 100ms RC evaluation intervals */
3541         I915_WRITE(RCUPEI, 100000);
3542         I915_WRITE(RCDNEI, 100000);
3543
3544         /* Set max/min thresholds to 90ms and 80ms respectively */
3545         I915_WRITE(RCBMAXAVG, 90000);
3546         I915_WRITE(RCBMINAVG, 80000);
3547
3548         I915_WRITE(MEMIHYST, 1);
3549
3550         /* Set up min, max, and cur for interrupt handling */
3551         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3552         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3553         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3554                 MEMMODE_FSTART_SHIFT;
3555
3556         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3557                 PXVFREQ_PX_SHIFT;
3558
3559         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3560         dev_priv->ips.fstart = fstart;
3561
3562         dev_priv->ips.max_delay = fstart;
3563         dev_priv->ips.min_delay = fmin;
3564         dev_priv->ips.cur_delay = fstart;
3565
3566         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3567                          fmax, fmin, fstart);
3568
3569         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3570
3571         /*
3572          * Interrupts will be enabled in ironlake_irq_postinstall
3573          */
3574
3575         I915_WRITE(VIDSTART, vstart);
3576         POSTING_READ(VIDSTART);
3577
3578         rgvmodectl |= MEMMODE_SWMODE_EN;
3579         I915_WRITE(MEMMODECTL, rgvmodectl);
3580
3581         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3582                 DRM_ERROR("stuck trying to change perf mode\n");
3583         mdelay(1);
3584
3585         ironlake_set_drps(dev, fstart);
3586
3587         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3588                 I915_READ(0x112e0);
3589         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3590         dev_priv->ips.last_count2 = I915_READ(0x112f4);
3591         dev_priv->ips.last_time2 = ktime_get_raw_ns();
3592
3593         spin_unlock_irq(&mchdev_lock);
3594 }
3595
3596 static void ironlake_disable_drps(struct drm_device *dev)
3597 {
3598         struct drm_i915_private *dev_priv = dev->dev_private;
3599         u16 rgvswctl;
3600
3601         spin_lock_irq(&mchdev_lock);
3602
3603         rgvswctl = I915_READ16(MEMSWCTL);
3604
3605         /* Ack interrupts, disable EFC interrupt */
3606         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3607         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3608         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3609         I915_WRITE(DEIIR, DE_PCU_EVENT);
3610         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3611
3612         /* Go back to the starting frequency */
3613         ironlake_set_drps(dev, dev_priv->ips.fstart);
3614         mdelay(1);
3615         rgvswctl |= MEMCTL_CMD_STS;
3616         I915_WRITE(MEMSWCTL, rgvswctl);
3617         mdelay(1);
3618
3619         spin_unlock_irq(&mchdev_lock);
3620 }
3621
3622 /* There's a funny hw issue where the hw returns all 0 when reading from
3623  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3624  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3625  * all limits and the gpu stuck at whatever frequency it is at atm).
3626  */
3627 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3628 {
3629         u32 limits;
3630
3631         /* Only set the down limit when we've reached the lowest level to avoid
3632          * getting more interrupts, otherwise leave this clear. This prevents a
3633          * race in the hw when coming out of rc6: There's a tiny window where
3634          * the hw runs at the minimal clock before selecting the desired
3635          * frequency, if the down threshold expires in that window we will not
3636          * receive a down interrupt. */
3637         limits = dev_priv->rps.max_freq_softlimit << 24;
3638         if (val <= dev_priv->rps.min_freq_softlimit)
3639                 limits |= dev_priv->rps.min_freq_softlimit << 16;
3640
3641         return limits;
3642 }
3643
3644 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3645 {
3646         int new_power;
3647
3648         new_power = dev_priv->rps.power;
3649         switch (dev_priv->rps.power) {
3650         case LOW_POWER:
3651                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3652                         new_power = BETWEEN;
3653                 break;
3654
3655         case BETWEEN:
3656                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3657                         new_power = LOW_POWER;
3658                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3659                         new_power = HIGH_POWER;
3660                 break;
3661
3662         case HIGH_POWER:
3663                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3664                         new_power = BETWEEN;
3665                 break;
3666         }
3667         /* Max/min bins are special */
3668         if (val == dev_priv->rps.min_freq_softlimit)
3669                 new_power = LOW_POWER;
3670         if (val == dev_priv->rps.max_freq_softlimit)
3671                 new_power = HIGH_POWER;
3672         if (new_power == dev_priv->rps.power)
3673                 return;
3674
3675         /* Note the units here are not exactly 1us, but 1280ns. */
3676         switch (new_power) {
3677         case LOW_POWER:
3678                 /* Upclock if more than 95% busy over 16ms */
3679                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3680                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3681
3682                 /* Downclock if less than 85% busy over 32ms */
3683                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3684                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3685
3686                 I915_WRITE(GEN6_RP_CONTROL,
3687                            GEN6_RP_MEDIA_TURBO |
3688                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3689                            GEN6_RP_MEDIA_IS_GFX |
3690                            GEN6_RP_ENABLE |
3691                            GEN6_RP_UP_BUSY_AVG |
3692                            GEN6_RP_DOWN_IDLE_AVG);
3693                 break;
3694
3695         case BETWEEN:
3696                 /* Upclock if more than 90% busy over 13ms */
3697                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3698                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3699
3700                 /* Downclock if less than 75% busy over 32ms */
3701                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3702                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3703
3704                 I915_WRITE(GEN6_RP_CONTROL,
3705                            GEN6_RP_MEDIA_TURBO |
3706                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3707                            GEN6_RP_MEDIA_IS_GFX |
3708                            GEN6_RP_ENABLE |
3709                            GEN6_RP_UP_BUSY_AVG |
3710                            GEN6_RP_DOWN_IDLE_AVG);
3711                 break;
3712
3713         case HIGH_POWER:
3714                 /* Upclock if more than 85% busy over 10ms */
3715                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3716                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3717
3718                 /* Downclock if less than 60% busy over 32ms */
3719                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3720                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3721
3722                 I915_WRITE(GEN6_RP_CONTROL,
3723                            GEN6_RP_MEDIA_TURBO |
3724                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3725                            GEN6_RP_MEDIA_IS_GFX |
3726                            GEN6_RP_ENABLE |
3727                            GEN6_RP_UP_BUSY_AVG |
3728                            GEN6_RP_DOWN_IDLE_AVG);
3729                 break;
3730         }
3731
3732         dev_priv->rps.power = new_power;
3733         dev_priv->rps.last_adj = 0;
3734 }
3735
3736 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3737 {
3738         u32 mask = 0;
3739
3740         if (val > dev_priv->rps.min_freq_softlimit)
3741                 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3742         if (val < dev_priv->rps.max_freq_softlimit)
3743                 mask |= GEN6_PM_RP_UP_THRESHOLD;
3744
3745         mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3746         mask &= dev_priv->pm_rps_events;
3747
3748         /* IVB and SNB hard hangs on looping batchbuffer
3749          * if GEN6_PM_UP_EI_EXPIRED is masked.
3750          */
3751         if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3752                 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3753
3754         if (IS_GEN8(dev_priv->dev))
3755                 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3756
3757         return ~mask;
3758 }
3759
3760 /* gen6_set_rps is called to update the frequency request, but should also be
3761  * called when the range (min_delay and max_delay) is modified so that we can
3762  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3763 void gen6_set_rps(struct drm_device *dev, u8 val)
3764 {
3765         struct drm_i915_private *dev_priv = dev->dev_private;
3766
3767         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3768         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3769         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3770
3771         /* min/max delay may still have been modified so be sure to
3772          * write the limits value.
3773          */
3774         if (val != dev_priv->rps.cur_freq) {
3775                 gen6_set_rps_thresholds(dev_priv, val);
3776
3777                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3778                         I915_WRITE(GEN6_RPNSWREQ,
3779                                    HSW_FREQUENCY(val));
3780                 else
3781                         I915_WRITE(GEN6_RPNSWREQ,
3782                                    GEN6_FREQUENCY(val) |
3783                                    GEN6_OFFSET(0) |
3784                                    GEN6_AGGRESSIVE_TURBO);
3785         }
3786
3787         /* Make sure we continue to get interrupts
3788          * until we hit the minimum or maximum frequencies.
3789          */
3790         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3791         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3792
3793         POSTING_READ(GEN6_RPNSWREQ);
3794
3795         dev_priv->rps.cur_freq = val;
3796         trace_intel_gpu_freq_change(val * 50);
3797 }
3798
3799 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3800  *
3801  * * If Gfx is Idle, then
3802  * 1. Mask Turbo interrupts
3803  * 2. Bring up Gfx clock
3804  * 3. Change the freq to Rpn and wait till P-Unit updates freq
3805  * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3806  * 5. Unmask Turbo interrupts
3807 */
3808 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3809 {
3810         struct drm_device *dev = dev_priv->dev;
3811
3812         /* Latest VLV doesn't need to force the gfx clock */
3813         if (dev->pdev->revision >= 0xd) {
3814                 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3815                 return;
3816         }
3817
3818         /*
3819          * When we are idle.  Drop to min voltage state.
3820          */
3821
3822         if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3823                 return;
3824
3825         /* Mask turbo interrupt so that they will not come in between */
3826         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3827
3828         vlv_force_gfx_clock(dev_priv, true);
3829
3830         dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3831
3832         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3833                                         dev_priv->rps.min_freq_softlimit);
3834
3835         if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3836                                 & GENFREQSTATUS) == 0, 100))
3837                 DRM_ERROR("timed out waiting for Punit\n");
3838
3839         vlv_force_gfx_clock(dev_priv, false);
3840
3841         I915_WRITE(GEN6_PMINTRMSK,
3842                    gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3843 }
3844
3845 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3846 {
3847         struct drm_device *dev = dev_priv->dev;
3848
3849         mutex_lock(&dev_priv->rps.hw_lock);
3850         if (dev_priv->rps.enabled) {
3851                 if (IS_CHERRYVIEW(dev))
3852                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3853                 else if (IS_VALLEYVIEW(dev))
3854                         vlv_set_rps_idle(dev_priv);
3855                 else
3856                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3857                 dev_priv->rps.last_adj = 0;
3858         }
3859         mutex_unlock(&dev_priv->rps.hw_lock);
3860 }
3861
3862 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3863 {
3864         struct drm_device *dev = dev_priv->dev;
3865
3866         mutex_lock(&dev_priv->rps.hw_lock);
3867         if (dev_priv->rps.enabled) {
3868                 if (IS_VALLEYVIEW(dev))
3869                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3870                 else
3871                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3872                 dev_priv->rps.last_adj = 0;
3873         }
3874         mutex_unlock(&dev_priv->rps.hw_lock);
3875 }
3876
3877 void valleyview_set_rps(struct drm_device *dev, u8 val)
3878 {
3879         struct drm_i915_private *dev_priv = dev->dev_private;
3880
3881         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3882         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3883         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3884
3885         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3886                       "Odd GPU freq value\n"))
3887                 val &= ~1;
3888
3889         if (val != dev_priv->rps.cur_freq)
3890                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3891
3892         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3893
3894         dev_priv->rps.cur_freq = val;
3895         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3896 }
3897
3898 static void gen9_disable_rps(struct drm_device *dev)
3899 {
3900         struct drm_i915_private *dev_priv = dev->dev_private;
3901
3902         I915_WRITE(GEN6_RC_CONTROL, 0);
3903 }
3904
3905 static void gen6_disable_rps(struct drm_device *dev)
3906 {
3907         struct drm_i915_private *dev_priv = dev->dev_private;
3908
3909         I915_WRITE(GEN6_RC_CONTROL, 0);
3910         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3911 }
3912
3913 static void cherryview_disable_rps(struct drm_device *dev)
3914 {
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916
3917         I915_WRITE(GEN6_RC_CONTROL, 0);
3918 }
3919
3920 static void valleyview_disable_rps(struct drm_device *dev)
3921 {
3922         struct drm_i915_private *dev_priv = dev->dev_private;
3923
3924         /* we're doing forcewake before Disabling RC6,
3925          * This what the BIOS expects when going into suspend */
3926         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3927
3928         I915_WRITE(GEN6_RC_CONTROL, 0);
3929
3930         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3931 }
3932
3933 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3934 {
3935         if (IS_VALLEYVIEW(dev)) {
3936                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3937                         mode = GEN6_RC_CTL_RC6_ENABLE;
3938                 else
3939                         mode = 0;
3940         }
3941         if (HAS_RC6p(dev))
3942                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
3943                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3944                               (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3945                               (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3946
3947         else
3948                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
3949                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3950 }
3951
3952 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3953 {
3954         /* No RC6 before Ironlake */
3955         if (INTEL_INFO(dev)->gen < 5)
3956                 return 0;
3957
3958         /* RC6 is only on Ironlake mobile not on desktop */
3959         if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3960                 return 0;
3961
3962         /* Respect the kernel parameter if it is set */
3963         if (enable_rc6 >= 0) {
3964                 int mask;
3965
3966                 if (HAS_RC6p(dev))
3967                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3968                                INTEL_RC6pp_ENABLE;
3969                 else
3970                         mask = INTEL_RC6_ENABLE;
3971
3972                 if ((enable_rc6 & mask) != enable_rc6)
3973                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3974                                       enable_rc6 & mask, enable_rc6, mask);
3975
3976                 return enable_rc6 & mask;
3977         }
3978
3979         /* Disable RC6 on Ironlake */
3980         if (INTEL_INFO(dev)->gen == 5)
3981                 return 0;
3982
3983         if (IS_IVYBRIDGE(dev))
3984                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3985
3986         return INTEL_RC6_ENABLE;
3987 }
3988
3989 int intel_enable_rc6(const struct drm_device *dev)
3990 {
3991         return i915.enable_rc6;
3992 }
3993
3994 static void gen6_init_rps_frequencies(struct drm_device *dev)
3995 {
3996         struct drm_i915_private *dev_priv = dev->dev_private;
3997         uint32_t rp_state_cap;
3998         u32 ddcc_status = 0;
3999         int ret;
4000
4001         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4002         /* All of these values are in units of 50MHz */
4003         dev_priv->rps.cur_freq          = 0;
4004         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4005         dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
4006         dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
4007         dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
4008         /* hw_max = RP0 until we check for overclocking */
4009         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4010
4011         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4012         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4013                 ret = sandybridge_pcode_read(dev_priv,
4014                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4015                                         &ddcc_status);
4016                 if (0 == ret)
4017                         dev_priv->rps.efficient_freq =
4018                                 (ddcc_status >> 8) & 0xff;
4019         }
4020
4021         /* Preserve min/max settings in case of re-init */
4022         if (dev_priv->rps.max_freq_softlimit == 0)
4023                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4024
4025         if (dev_priv->rps.min_freq_softlimit == 0) {
4026                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4027                         dev_priv->rps.min_freq_softlimit =
4028                                 /* max(RPe, 450 MHz) */
4029                                 max(dev_priv->rps.efficient_freq, (u8) 9);
4030                 else
4031                         dev_priv->rps.min_freq_softlimit =
4032                                 dev_priv->rps.min_freq;
4033         }
4034 }
4035
4036 static void gen9_enable_rps(struct drm_device *dev)
4037 {
4038         struct drm_i915_private *dev_priv = dev->dev_private;
4039         struct intel_engine_cs *ring;
4040         uint32_t rc6_mask = 0;
4041         int unused;
4042
4043         /* 1a: Software RC state - RC0 */
4044         I915_WRITE(GEN6_RC_STATE, 0);
4045
4046         /* 1b: Get forcewake during program sequence. Although the driver
4047          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4048         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4049
4050         /* 2a: Disable RC states. */
4051         I915_WRITE(GEN6_RC_CONTROL, 0);
4052
4053         /* 2b: Program RC6 thresholds.*/
4054         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4055         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4056         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4057         for_each_ring(ring, dev_priv, unused)
4058                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4059         I915_WRITE(GEN6_RC_SLEEP, 0);
4060         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4061
4062         /* 3a: Enable RC6 */
4063         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4064                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4065         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4066                         "on" : "off");
4067         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4068                                    GEN6_RC_CTL_EI_MODE(1) |
4069                                    rc6_mask);
4070
4071         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4072
4073 }
4074
4075 static void gen8_enable_rps(struct drm_device *dev)
4076 {
4077         struct drm_i915_private *dev_priv = dev->dev_private;
4078         struct intel_engine_cs *ring;
4079         uint32_t rc6_mask = 0;
4080         int unused;
4081
4082         /* 1a: Software RC state - RC0 */
4083         I915_WRITE(GEN6_RC_STATE, 0);
4084
4085         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4086          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4087         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4088
4089         /* 2a: Disable RC states. */
4090         I915_WRITE(GEN6_RC_CONTROL, 0);
4091
4092         /* Initialize rps frequencies */
4093         gen6_init_rps_frequencies(dev);
4094
4095         /* 2b: Program RC6 thresholds.*/
4096         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4097         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4098         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4099         for_each_ring(ring, dev_priv, unused)
4100                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4101         I915_WRITE(GEN6_RC_SLEEP, 0);
4102         if (IS_BROADWELL(dev))
4103                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4104         else
4105                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4106
4107         /* 3: Enable RC6 */
4108         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4109                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4110         intel_print_rc6_info(dev, rc6_mask);
4111         if (IS_BROADWELL(dev))
4112                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4113                                 GEN7_RC_CTL_TO_MODE |
4114                                 rc6_mask);
4115         else
4116                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4117                                 GEN6_RC_CTL_EI_MODE(1) |
4118                                 rc6_mask);
4119
4120         /* 4 Program defaults and thresholds for RPS*/
4121         I915_WRITE(GEN6_RPNSWREQ,
4122                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4123         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4124                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4125         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4126         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4127
4128         /* Docs recommend 900MHz, and 300 MHz respectively */
4129         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4130                    dev_priv->rps.max_freq_softlimit << 24 |
4131                    dev_priv->rps.min_freq_softlimit << 16);
4132
4133         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4134         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4135         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4136         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4137
4138         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4139
4140         /* 5: Enable RPS */
4141         I915_WRITE(GEN6_RP_CONTROL,
4142                    GEN6_RP_MEDIA_TURBO |
4143                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4144                    GEN6_RP_MEDIA_IS_GFX |
4145                    GEN6_RP_ENABLE |
4146                    GEN6_RP_UP_BUSY_AVG |
4147                    GEN6_RP_DOWN_IDLE_AVG);
4148
4149         /* 6: Ring frequency + overclocking (our driver does this later */
4150
4151         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4152         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4153
4154         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4155 }
4156
4157 static void gen6_enable_rps(struct drm_device *dev)
4158 {
4159         struct drm_i915_private *dev_priv = dev->dev_private;
4160         struct intel_engine_cs *ring;
4161         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4162         u32 gtfifodbg;
4163         int rc6_mode;
4164         int i, ret;
4165
4166         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4167
4168         /* Here begins a magic sequence of register writes to enable
4169          * auto-downclocking.
4170          *
4171          * Perhaps there might be some value in exposing these to
4172          * userspace...
4173          */
4174         I915_WRITE(GEN6_RC_STATE, 0);
4175
4176         /* Clear the DBG now so we don't confuse earlier errors */
4177         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4178                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4179                 I915_WRITE(GTFIFODBG, gtfifodbg);
4180         }
4181
4182         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4183
4184         /* Initialize rps frequencies */
4185         gen6_init_rps_frequencies(dev);
4186
4187         /* disable the counters and set deterministic thresholds */
4188         I915_WRITE(GEN6_RC_CONTROL, 0);
4189
4190         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4191         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4192         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4193         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4194         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4195
4196         for_each_ring(ring, dev_priv, i)
4197                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4198
4199         I915_WRITE(GEN6_RC_SLEEP, 0);
4200         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4201         if (IS_IVYBRIDGE(dev))
4202                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4203         else
4204                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4205         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4206         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4207
4208         /* Check if we are enabling RC6 */
4209         rc6_mode = intel_enable_rc6(dev_priv->dev);
4210         if (rc6_mode & INTEL_RC6_ENABLE)
4211                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4212
4213         /* We don't use those on Haswell */
4214         if (!IS_HASWELL(dev)) {
4215                 if (rc6_mode & INTEL_RC6p_ENABLE)
4216                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4217
4218                 if (rc6_mode & INTEL_RC6pp_ENABLE)
4219                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4220         }
4221
4222         intel_print_rc6_info(dev, rc6_mask);
4223
4224         I915_WRITE(GEN6_RC_CONTROL,
4225                    rc6_mask |
4226                    GEN6_RC_CTL_EI_MODE(1) |
4227                    GEN6_RC_CTL_HW_ENABLE);
4228
4229         /* Power down if completely idle for over 50ms */
4230         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4231         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4232
4233         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4234         if (ret)
4235                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4236
4237         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4238         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4239                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4240                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4241                                  (pcu_mbox & 0xff) * 50);
4242                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4243         }
4244
4245         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4246         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4247
4248         rc6vids = 0;
4249         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4250         if (IS_GEN6(dev) && ret) {
4251                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4252         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4253                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4254                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4255                 rc6vids &= 0xffff00;
4256                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4257                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4258                 if (ret)
4259                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4260         }
4261
4262         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4263 }
4264
4265 static void __gen6_update_ring_freq(struct drm_device *dev)
4266 {
4267         struct drm_i915_private *dev_priv = dev->dev_private;
4268         int min_freq = 15;
4269         unsigned int gpu_freq;
4270         unsigned int max_ia_freq, min_ring_freq;
4271         int scaling_factor = 180;
4272         struct cpufreq_policy *policy;
4273
4274         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4275
4276         policy = cpufreq_cpu_get(0);
4277         if (policy) {
4278                 max_ia_freq = policy->cpuinfo.max_freq;
4279                 cpufreq_cpu_put(policy);
4280         } else {
4281                 /*
4282                  * Default to measured freq if none found, PCU will ensure we
4283                  * don't go over
4284                  */
4285                 max_ia_freq = tsc_khz;
4286         }
4287
4288         /* Convert from kHz to MHz */
4289         max_ia_freq /= 1000;
4290
4291         min_ring_freq = I915_READ(DCLK) & 0xf;
4292         /* convert DDR frequency from units of 266.6MHz to bandwidth */
4293         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4294
4295         /*
4296          * For each potential GPU frequency, load a ring frequency we'd like
4297          * to use for memory access.  We do this by specifying the IA frequency
4298          * the PCU should use as a reference to determine the ring frequency.
4299          */
4300         for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
4301              gpu_freq--) {
4302                 int diff = dev_priv->rps.max_freq - gpu_freq;
4303                 unsigned int ia_freq = 0, ring_freq = 0;
4304
4305                 if (INTEL_INFO(dev)->gen >= 8) {
4306                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
4307                         ring_freq = max(min_ring_freq, gpu_freq);
4308                 } else if (IS_HASWELL(dev)) {
4309                         ring_freq = mult_frac(gpu_freq, 5, 4);
4310                         ring_freq = max(min_ring_freq, ring_freq);
4311                         /* leave ia_freq as the default, chosen by cpufreq */
4312                 } else {
4313                         /* On older processors, there is no separate ring
4314                          * clock domain, so in order to boost the bandwidth
4315                          * of the ring, we need to upclock the CPU (ia_freq).
4316                          *
4317                          * For GPU frequencies less than 750MHz,
4318                          * just use the lowest ring freq.
4319                          */
4320                         if (gpu_freq < min_freq)
4321                                 ia_freq = 800;
4322                         else
4323                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4324                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4325                 }
4326
4327                 sandybridge_pcode_write(dev_priv,
4328                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4329                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4330                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4331                                         gpu_freq);
4332         }
4333 }
4334
4335 void gen6_update_ring_freq(struct drm_device *dev)
4336 {
4337         struct drm_i915_private *dev_priv = dev->dev_private;
4338
4339         if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4340                 return;
4341
4342         mutex_lock(&dev_priv->rps.hw_lock);
4343         __gen6_update_ring_freq(dev);
4344         mutex_unlock(&dev_priv->rps.hw_lock);
4345 }
4346
4347 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4348 {
4349         u32 val, rp0;
4350
4351         val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4352         rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4353
4354         return rp0;
4355 }
4356
4357 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4358 {
4359         u32 val, rpe;
4360
4361         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4362         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4363
4364         return rpe;
4365 }
4366
4367 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4368 {
4369         u32 val, rp1;
4370
4371         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4372         rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4373
4374         return rp1;
4375 }
4376
4377 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
4378 {
4379         u32 val, rpn;
4380
4381         val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4382         rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
4383         return rpn;
4384 }
4385
4386 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4387 {
4388         u32 val, rp1;
4389
4390         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4391
4392         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4393
4394         return rp1;
4395 }
4396
4397 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4398 {
4399         u32 val, rp0;
4400
4401         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4402
4403         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4404         /* Clamp to max */
4405         rp0 = min_t(u32, rp0, 0xea);
4406
4407         return rp0;
4408 }
4409
4410 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4411 {
4412         u32 val, rpe;
4413
4414         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4415         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4416         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4417         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4418
4419         return rpe;
4420 }
4421
4422 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4423 {
4424         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4425 }
4426
4427 /* Check that the pctx buffer wasn't move under us. */
4428 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4429 {
4430         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4431
4432         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4433                              dev_priv->vlv_pctx->stolen->start);
4434 }
4435
4436
4437 /* Check that the pcbr address is not empty. */
4438 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4439 {
4440         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4441
4442         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4443 }
4444
4445 static void cherryview_setup_pctx(struct drm_device *dev)
4446 {
4447         struct drm_i915_private *dev_priv = dev->dev_private;
4448         unsigned long pctx_paddr, paddr;
4449         struct i915_gtt *gtt = &dev_priv->gtt;
4450         u32 pcbr;
4451         int pctx_size = 32*1024;
4452
4453         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4454
4455         pcbr = I915_READ(VLV_PCBR);
4456         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4457                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4458                 paddr = (dev_priv->mm.stolen_base +
4459                          (gtt->stolen_size - pctx_size));
4460
4461                 pctx_paddr = (paddr & (~4095));
4462                 I915_WRITE(VLV_PCBR, pctx_paddr);
4463         }
4464
4465         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
4466 }
4467
4468 static void valleyview_setup_pctx(struct drm_device *dev)
4469 {
4470         struct drm_i915_private *dev_priv = dev->dev_private;
4471         struct drm_i915_gem_object *pctx;
4472         unsigned long pctx_paddr;
4473         u32 pcbr;
4474         int pctx_size = 24*1024;
4475
4476         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4477
4478         pcbr = I915_READ(VLV_PCBR);
4479         if (pcbr) {
4480                 /* BIOS set it up already, grab the pre-alloc'd space */
4481                 int pcbr_offset;
4482
4483                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4484                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4485                                                                       pcbr_offset,
4486                                                                       I915_GTT_OFFSET_NONE,
4487                                                                       pctx_size);
4488                 goto out;
4489         }
4490
4491         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4492
4493         /*
4494          * From the Gunit register HAS:
4495          * The Gfx driver is expected to program this register and ensure
4496          * proper allocation within Gfx stolen memory.  For example, this
4497          * register should be programmed such than the PCBR range does not
4498          * overlap with other ranges, such as the frame buffer, protected
4499          * memory, or any other relevant ranges.
4500          */
4501         pctx = i915_gem_object_create_stolen(dev, pctx_size);
4502         if (!pctx) {
4503                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4504                 return;
4505         }
4506
4507         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4508         I915_WRITE(VLV_PCBR, pctx_paddr);
4509
4510 out:
4511         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
4512         dev_priv->vlv_pctx = pctx;
4513 }
4514
4515 static void valleyview_cleanup_pctx(struct drm_device *dev)
4516 {
4517         struct drm_i915_private *dev_priv = dev->dev_private;
4518
4519         if (WARN_ON(!dev_priv->vlv_pctx))
4520                 return;
4521
4522         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4523         dev_priv->vlv_pctx = NULL;
4524 }
4525
4526 static void valleyview_init_gt_powersave(struct drm_device *dev)
4527 {
4528         struct drm_i915_private *dev_priv = dev->dev_private;
4529         u32 val;
4530
4531         valleyview_setup_pctx(dev);
4532
4533         mutex_lock(&dev_priv->rps.hw_lock);
4534
4535         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4536         switch ((val >> 6) & 3) {
4537         case 0:
4538         case 1:
4539                 dev_priv->mem_freq = 800;
4540                 break;
4541         case 2:
4542                 dev_priv->mem_freq = 1066;
4543                 break;
4544         case 3:
4545                 dev_priv->mem_freq = 1333;
4546                 break;
4547         }
4548         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
4549
4550         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4551         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4552         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4553                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4554                          dev_priv->rps.max_freq);
4555
4556         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4557         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4558                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4559                          dev_priv->rps.efficient_freq);
4560
4561         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4562         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4563                          vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4564                          dev_priv->rps.rp1_freq);
4565
4566         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4567         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4568                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4569                          dev_priv->rps.min_freq);
4570
4571         /* Preserve min/max settings in case of re-init */
4572         if (dev_priv->rps.max_freq_softlimit == 0)
4573                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4574
4575         if (dev_priv->rps.min_freq_softlimit == 0)
4576                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4577
4578         mutex_unlock(&dev_priv->rps.hw_lock);
4579 }
4580
4581 static void cherryview_init_gt_powersave(struct drm_device *dev)
4582 {
4583         struct drm_i915_private *dev_priv = dev->dev_private;
4584         u32 val;
4585
4586         cherryview_setup_pctx(dev);
4587
4588         mutex_lock(&dev_priv->rps.hw_lock);
4589
4590         mutex_lock(&dev_priv->dpio_lock);
4591         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4592         mutex_unlock(&dev_priv->dpio_lock);
4593
4594         switch ((val >> 2) & 0x7) {
4595         case 0:
4596         case 1:
4597                 dev_priv->rps.cz_freq = 200;
4598                 dev_priv->mem_freq = 1600;
4599                 break;
4600         case 2:
4601                 dev_priv->rps.cz_freq = 267;
4602                 dev_priv->mem_freq = 1600;
4603                 break;
4604         case 3:
4605                 dev_priv->rps.cz_freq = 333;
4606                 dev_priv->mem_freq = 2000;
4607                 break;
4608         case 4:
4609                 dev_priv->rps.cz_freq = 320;
4610                 dev_priv->mem_freq = 1600;
4611                 break;
4612         case 5:
4613                 dev_priv->rps.cz_freq = 400;
4614                 dev_priv->mem_freq = 1600;
4615                 break;
4616         }
4617         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
4618
4619         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4620         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4621         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4622                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4623                          dev_priv->rps.max_freq);
4624
4625         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4626         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4627                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4628                          dev_priv->rps.efficient_freq);
4629
4630         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4631         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4632                          vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4633                          dev_priv->rps.rp1_freq);
4634
4635         dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4636         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4637                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4638                          dev_priv->rps.min_freq);
4639
4640         WARN_ONCE((dev_priv->rps.max_freq |
4641                    dev_priv->rps.efficient_freq |
4642                    dev_priv->rps.rp1_freq |
4643                    dev_priv->rps.min_freq) & 1,
4644                   "Odd GPU freq values\n");
4645
4646         /* Preserve min/max settings in case of re-init */
4647         if (dev_priv->rps.max_freq_softlimit == 0)
4648                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4649
4650         if (dev_priv->rps.min_freq_softlimit == 0)
4651                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4652
4653         mutex_unlock(&dev_priv->rps.hw_lock);
4654 }
4655
4656 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4657 {
4658         valleyview_cleanup_pctx(dev);
4659 }
4660
4661 static void cherryview_enable_rps(struct drm_device *dev)
4662 {
4663         struct drm_i915_private *dev_priv = dev->dev_private;
4664         struct intel_engine_cs *ring;
4665         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4666         int i;
4667
4668         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4669
4670         gtfifodbg = I915_READ(GTFIFODBG);
4671         if (gtfifodbg) {
4672                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4673                                  gtfifodbg);
4674                 I915_WRITE(GTFIFODBG, gtfifodbg);
4675         }
4676
4677         cherryview_check_pctx(dev_priv);
4678
4679         /* 1a & 1b: Get forcewake during program sequence. Although the driver
4680          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4681         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4682
4683         /* 2a: Program RC6 thresholds.*/
4684         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4685         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4686         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4687
4688         for_each_ring(ring, dev_priv, i)
4689                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4690         I915_WRITE(GEN6_RC_SLEEP, 0);
4691
4692         /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
4693         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4694
4695         /* allows RC6 residency counter to work */
4696         I915_WRITE(VLV_COUNTER_CONTROL,
4697                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4698                                       VLV_MEDIA_RC6_COUNT_EN |
4699                                       VLV_RENDER_RC6_COUNT_EN));
4700
4701         /* For now we assume BIOS is allocating and populating the PCBR  */
4702         pcbr = I915_READ(VLV_PCBR);
4703
4704         /* 3: Enable RC6 */
4705         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4706                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4707                 rc6_mode = GEN7_RC_CTL_TO_MODE;
4708
4709         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4710
4711         /* 4 Program defaults and thresholds for RPS*/
4712         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4713         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4714         I915_WRITE(GEN6_RP_UP_EI, 66000);
4715         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4716
4717         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4718
4719         /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4720         I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4721         I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4722
4723         /* 5: Enable RPS */
4724         I915_WRITE(GEN6_RP_CONTROL,
4725                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4726                    GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4727                    GEN6_RP_ENABLE |
4728                    GEN6_RP_UP_BUSY_AVG |
4729                    GEN6_RP_DOWN_IDLE_AVG);
4730
4731         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4732
4733         /* RPS code assumes GPLL is used */
4734         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
4735
4736         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
4737         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4738
4739         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4740         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4741                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4742                          dev_priv->rps.cur_freq);
4743
4744         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4745                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4746                          dev_priv->rps.efficient_freq);
4747
4748         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4749
4750         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4751 }
4752
4753 static void valleyview_enable_rps(struct drm_device *dev)
4754 {
4755         struct drm_i915_private *dev_priv = dev->dev_private;
4756         struct intel_engine_cs *ring;
4757         u32 gtfifodbg, val, rc6_mode = 0;
4758         int i;
4759
4760         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4761
4762         valleyview_check_pctx(dev_priv);
4763
4764         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4765                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4766                                  gtfifodbg);
4767                 I915_WRITE(GTFIFODBG, gtfifodbg);
4768         }
4769
4770         /* If VLV, Forcewake all wells, else re-direct to regular path */
4771         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4772
4773         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4774         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4775         I915_WRITE(GEN6_RP_UP_EI, 66000);
4776         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4777
4778         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4779         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4780
4781         I915_WRITE(GEN6_RP_CONTROL,
4782                    GEN6_RP_MEDIA_TURBO |
4783                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4784                    GEN6_RP_MEDIA_IS_GFX |
4785                    GEN6_RP_ENABLE |
4786                    GEN6_RP_UP_BUSY_AVG |
4787                    GEN6_RP_DOWN_IDLE_CONT);
4788
4789         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4790         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4791         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4792
4793         for_each_ring(ring, dev_priv, i)
4794                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4795
4796         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4797
4798         /* allows RC6 residency counter to work */
4799         I915_WRITE(VLV_COUNTER_CONTROL,
4800                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4801                                       VLV_RENDER_RC0_COUNT_EN |
4802                                       VLV_MEDIA_RC6_COUNT_EN |
4803                                       VLV_RENDER_RC6_COUNT_EN));
4804
4805         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4806                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4807
4808         intel_print_rc6_info(dev, rc6_mode);
4809
4810         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4811
4812         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4813
4814         /* RPS code assumes GPLL is used */
4815         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
4816
4817         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
4818         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4819
4820         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4821         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4822                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4823                          dev_priv->rps.cur_freq);
4824
4825         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4826                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4827                          dev_priv->rps.efficient_freq);
4828
4829         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4830
4831         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4832 }
4833
4834 void ironlake_teardown_rc6(struct drm_device *dev)
4835 {
4836         struct drm_i915_private *dev_priv = dev->dev_private;
4837
4838         if (dev_priv->ips.renderctx) {
4839                 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4840                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4841                 dev_priv->ips.renderctx = NULL;
4842         }
4843
4844         if (dev_priv->ips.pwrctx) {
4845                 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4846                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4847                 dev_priv->ips.pwrctx = NULL;
4848         }
4849 }
4850
4851 static void ironlake_disable_rc6(struct drm_device *dev)
4852 {
4853         struct drm_i915_private *dev_priv = dev->dev_private;
4854
4855         if (I915_READ(PWRCTXA)) {
4856                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4857                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4858                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4859                          50);
4860
4861                 I915_WRITE(PWRCTXA, 0);
4862                 POSTING_READ(PWRCTXA);
4863
4864                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4865                 POSTING_READ(RSTDBYCTL);
4866         }
4867 }
4868
4869 static int ironlake_setup_rc6(struct drm_device *dev)
4870 {
4871         struct drm_i915_private *dev_priv = dev->dev_private;
4872
4873         if (dev_priv->ips.renderctx == NULL)
4874                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4875         if (!dev_priv->ips.renderctx)
4876                 return -ENOMEM;
4877
4878         if (dev_priv->ips.pwrctx == NULL)
4879                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4880         if (!dev_priv->ips.pwrctx) {
4881                 ironlake_teardown_rc6(dev);
4882                 return -ENOMEM;
4883         }
4884
4885         return 0;
4886 }
4887
4888 static void ironlake_enable_rc6(struct drm_device *dev)
4889 {
4890         struct drm_i915_private *dev_priv = dev->dev_private;
4891         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4892         bool was_interruptible;
4893         int ret;
4894
4895         /* rc6 disabled by default due to repeated reports of hanging during
4896          * boot and resume.
4897          */
4898         if (!intel_enable_rc6(dev))
4899                 return;
4900
4901         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4902
4903         ret = ironlake_setup_rc6(dev);
4904         if (ret)
4905                 return;
4906
4907         was_interruptible = dev_priv->mm.interruptible;
4908         dev_priv->mm.interruptible = false;
4909
4910         /*
4911          * GPU can automatically power down the render unit if given a page
4912          * to save state.
4913          */
4914         ret = intel_ring_begin(ring, 6);
4915         if (ret) {
4916                 ironlake_teardown_rc6(dev);
4917                 dev_priv->mm.interruptible = was_interruptible;
4918                 return;
4919         }
4920
4921         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4922         intel_ring_emit(ring, MI_SET_CONTEXT);
4923         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4924                         MI_MM_SPACE_GTT |
4925                         MI_SAVE_EXT_STATE_EN |
4926                         MI_RESTORE_EXT_STATE_EN |
4927                         MI_RESTORE_INHIBIT);
4928         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4929         intel_ring_emit(ring, MI_NOOP);
4930         intel_ring_emit(ring, MI_FLUSH);
4931         intel_ring_advance(ring);
4932
4933         /*
4934          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4935          * does an implicit flush, combined with MI_FLUSH above, it should be
4936          * safe to assume that renderctx is valid
4937          */
4938         ret = intel_ring_idle(ring);
4939         dev_priv->mm.interruptible = was_interruptible;
4940         if (ret) {
4941                 DRM_ERROR("failed to enable ironlake power savings\n");
4942                 ironlake_teardown_rc6(dev);
4943                 return;
4944         }
4945
4946         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4947         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4948
4949         intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4950 }
4951
4952 static unsigned long intel_pxfreq(u32 vidfreq)
4953 {
4954         unsigned long freq;
4955         int div = (vidfreq & 0x3f0000) >> 16;
4956         int post = (vidfreq & 0x3000) >> 12;
4957         int pre = (vidfreq & 0x7);
4958
4959         if (!pre)
4960                 return 0;
4961
4962         freq = ((div * 133333) / ((1<<post) * pre));
4963
4964         return freq;
4965 }
4966
4967 static const struct cparams {
4968         u16 i;
4969         u16 t;
4970         u16 m;
4971         u16 c;
4972 } cparams[] = {
4973         { 1, 1333, 301, 28664 },
4974         { 1, 1066, 294, 24460 },
4975         { 1, 800, 294, 25192 },
4976         { 0, 1333, 276, 27605 },
4977         { 0, 1066, 276, 27605 },
4978         { 0, 800, 231, 23784 },
4979 };
4980
4981 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4982 {
4983         u64 total_count, diff, ret;
4984         u32 count1, count2, count3, m = 0, c = 0;
4985         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4986         int i;
4987
4988         assert_spin_locked(&mchdev_lock);
4989
4990         diff1 = now - dev_priv->ips.last_time1;
4991
4992         /* Prevent division-by-zero if we are asking too fast.
4993          * Also, we don't get interesting results if we are polling
4994          * faster than once in 10ms, so just return the saved value
4995          * in such cases.
4996          */
4997         if (diff1 <= 10)
4998                 return dev_priv->ips.chipset_power;
4999
5000         count1 = I915_READ(DMIEC);
5001         count2 = I915_READ(DDREC);
5002         count3 = I915_READ(CSIEC);
5003
5004         total_count = count1 + count2 + count3;
5005
5006         /* FIXME: handle per-counter overflow */
5007         if (total_count < dev_priv->ips.last_count1) {
5008                 diff = ~0UL - dev_priv->ips.last_count1;
5009                 diff += total_count;
5010         } else {
5011                 diff = total_count - dev_priv->ips.last_count1;
5012         }
5013
5014         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5015                 if (cparams[i].i == dev_priv->ips.c_m &&
5016                     cparams[i].t == dev_priv->ips.r_t) {
5017                         m = cparams[i].m;
5018                         c = cparams[i].c;
5019                         break;
5020                 }
5021         }
5022
5023         diff = div_u64(diff, diff1);
5024         ret = ((m * diff) + c);
5025         ret = div_u64(ret, 10);
5026
5027         dev_priv->ips.last_count1 = total_count;
5028         dev_priv->ips.last_time1 = now;
5029
5030         dev_priv->ips.chipset_power = ret;
5031
5032         return ret;
5033 }
5034
5035 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5036 {
5037         struct drm_device *dev = dev_priv->dev;
5038         unsigned long val;
5039
5040         if (INTEL_INFO(dev)->gen != 5)
5041                 return 0;
5042
5043         spin_lock_irq(&mchdev_lock);
5044
5045         val = __i915_chipset_val(dev_priv);
5046
5047         spin_unlock_irq(&mchdev_lock);
5048
5049         return val;
5050 }
5051
5052 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5053 {
5054         unsigned long m, x, b;
5055         u32 tsfs;
5056
5057         tsfs = I915_READ(TSFS);
5058
5059         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5060         x = I915_READ8(TR1);
5061
5062         b = tsfs & TSFS_INTR_MASK;
5063
5064         return ((m * x) / 127) - b;
5065 }
5066
5067 static int _pxvid_to_vd(u8 pxvid)
5068 {
5069         if (pxvid == 0)
5070                 return 0;
5071
5072         if (pxvid >= 8 && pxvid < 31)
5073                 pxvid = 31;
5074
5075         return (pxvid + 2) * 125;
5076 }
5077
5078 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5079 {
5080         struct drm_device *dev = dev_priv->dev;
5081         const int vd = _pxvid_to_vd(pxvid);
5082         const int vm = vd - 1125;
5083
5084         if (INTEL_INFO(dev)->is_mobile)
5085                 return vm > 0 ? vm : 0;
5086
5087         return vd;
5088 }
5089
5090 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5091 {
5092         u64 now, diff, diffms;
5093         u32 count;
5094
5095         assert_spin_locked(&mchdev_lock);
5096
5097         now = ktime_get_raw_ns();
5098         diffms = now - dev_priv->ips.last_time2;
5099         do_div(diffms, NSEC_PER_MSEC);
5100
5101         /* Don't divide by 0 */
5102         if (!diffms)
5103                 return;
5104
5105         count = I915_READ(GFXEC);
5106
5107         if (count < dev_priv->ips.last_count2) {
5108                 diff = ~0UL - dev_priv->ips.last_count2;
5109                 diff += count;
5110         } else {
5111                 diff = count - dev_priv->ips.last_count2;
5112         }
5113
5114         dev_priv->ips.last_count2 = count;
5115         dev_priv->ips.last_time2 = now;
5116
5117         /* More magic constants... */
5118         diff = diff * 1181;
5119         diff = div_u64(diff, diffms * 10);
5120         dev_priv->ips.gfx_power = diff;
5121 }
5122
5123 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5124 {
5125         struct drm_device *dev = dev_priv->dev;
5126
5127         if (INTEL_INFO(dev)->gen != 5)
5128                 return;
5129
5130         spin_lock_irq(&mchdev_lock);
5131
5132         __i915_update_gfx_val(dev_priv);
5133
5134         spin_unlock_irq(&mchdev_lock);
5135 }
5136
5137 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5138 {
5139         unsigned long t, corr, state1, corr2, state2;
5140         u32 pxvid, ext_v;
5141
5142         assert_spin_locked(&mchdev_lock);
5143
5144         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5145         pxvid = (pxvid >> 24) & 0x7f;
5146         ext_v = pvid_to_extvid(dev_priv, pxvid);
5147
5148         state1 = ext_v;
5149
5150         t = i915_mch_val(dev_priv);
5151
5152         /* Revel in the empirically derived constants */
5153
5154         /* Correction factor in 1/100000 units */
5155         if (t > 80)
5156                 corr = ((t * 2349) + 135940);
5157         else if (t >= 50)
5158                 corr = ((t * 964) + 29317);
5159         else /* < 50 */
5160                 corr = ((t * 301) + 1004);
5161
5162         corr = corr * ((150142 * state1) / 10000 - 78642);
5163         corr /= 100000;
5164         corr2 = (corr * dev_priv->ips.corr);
5165
5166         state2 = (corr2 * state1) / 10000;
5167         state2 /= 100; /* convert to mW */
5168
5169         __i915_update_gfx_val(dev_priv);
5170
5171         return dev_priv->ips.gfx_power + state2;
5172 }
5173
5174 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5175 {
5176         struct drm_device *dev = dev_priv->dev;
5177         unsigned long val;
5178
5179         if (INTEL_INFO(dev)->gen != 5)
5180                 return 0;
5181
5182         spin_lock_irq(&mchdev_lock);
5183
5184         val = __i915_gfx_val(dev_priv);
5185
5186         spin_unlock_irq(&mchdev_lock);
5187
5188         return val;
5189 }
5190
5191 /**
5192  * i915_read_mch_val - return value for IPS use
5193  *
5194  * Calculate and return a value for the IPS driver to use when deciding whether
5195  * we have thermal and power headroom to increase CPU or GPU power budget.
5196  */
5197 unsigned long i915_read_mch_val(void)
5198 {
5199         struct drm_i915_private *dev_priv;
5200         unsigned long chipset_val, graphics_val, ret = 0;
5201
5202         spin_lock_irq(&mchdev_lock);
5203         if (!i915_mch_dev)
5204                 goto out_unlock;
5205         dev_priv = i915_mch_dev;
5206
5207         chipset_val = __i915_chipset_val(dev_priv);
5208         graphics_val = __i915_gfx_val(dev_priv);
5209
5210         ret = chipset_val + graphics_val;
5211
5212 out_unlock:
5213         spin_unlock_irq(&mchdev_lock);
5214
5215         return ret;
5216 }
5217 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5218
5219 /**
5220  * i915_gpu_raise - raise GPU frequency limit
5221  *
5222  * Raise the limit; IPS indicates we have thermal headroom.
5223  */
5224 bool i915_gpu_raise(void)
5225 {
5226         struct drm_i915_private *dev_priv;
5227         bool ret = true;
5228
5229         spin_lock_irq(&mchdev_lock);
5230         if (!i915_mch_dev) {
5231                 ret = false;
5232                 goto out_unlock;
5233         }
5234         dev_priv = i915_mch_dev;
5235
5236         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5237                 dev_priv->ips.max_delay--;
5238
5239 out_unlock:
5240         spin_unlock_irq(&mchdev_lock);
5241
5242         return ret;
5243 }
5244 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5245
5246 /**
5247  * i915_gpu_lower - lower GPU frequency limit
5248  *
5249  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5250  * frequency maximum.
5251  */
5252 bool i915_gpu_lower(void)
5253 {
5254         struct drm_i915_private *dev_priv;
5255         bool ret = true;
5256
5257         spin_lock_irq(&mchdev_lock);
5258         if (!i915_mch_dev) {
5259                 ret = false;
5260                 goto out_unlock;
5261         }
5262         dev_priv = i915_mch_dev;
5263
5264         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5265                 dev_priv->ips.max_delay++;
5266
5267 out_unlock:
5268         spin_unlock_irq(&mchdev_lock);
5269
5270         return ret;
5271 }
5272 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5273
5274 /**
5275  * i915_gpu_busy - indicate GPU business to IPS
5276  *
5277  * Tell the IPS driver whether or not the GPU is busy.
5278  */
5279 bool i915_gpu_busy(void)
5280 {
5281         struct drm_i915_private *dev_priv;
5282         struct intel_engine_cs *ring;
5283         bool ret = false;
5284         int i;
5285
5286         spin_lock_irq(&mchdev_lock);
5287         if (!i915_mch_dev)
5288                 goto out_unlock;
5289         dev_priv = i915_mch_dev;
5290
5291         for_each_ring(ring, dev_priv, i)
5292                 ret |= !list_empty(&ring->request_list);
5293
5294 out_unlock:
5295         spin_unlock_irq(&mchdev_lock);
5296
5297         return ret;
5298 }
5299 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5300
5301 /**
5302  * i915_gpu_turbo_disable - disable graphics turbo
5303  *
5304  * Disable graphics turbo by resetting the max frequency and setting the
5305  * current frequency to the default.
5306  */
5307 bool i915_gpu_turbo_disable(void)
5308 {
5309         struct drm_i915_private *dev_priv;
5310         bool ret = true;
5311
5312         spin_lock_irq(&mchdev_lock);
5313         if (!i915_mch_dev) {
5314                 ret = false;
5315                 goto out_unlock;
5316         }
5317         dev_priv = i915_mch_dev;
5318
5319         dev_priv->ips.max_delay = dev_priv->ips.fstart;
5320
5321         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5322                 ret = false;
5323
5324 out_unlock:
5325         spin_unlock_irq(&mchdev_lock);
5326
5327         return ret;
5328 }
5329 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5330
5331 /**
5332  * Tells the intel_ips driver that the i915 driver is now loaded, if
5333  * IPS got loaded first.
5334  *
5335  * This awkward dance is so that neither module has to depend on the
5336  * other in order for IPS to do the appropriate communication of
5337  * GPU turbo limits to i915.
5338  */
5339 static void
5340 ips_ping_for_i915_load(void)
5341 {
5342         void (*link)(void);
5343
5344         link = symbol_get(ips_link_to_i915_driver);
5345         if (link) {
5346                 link();
5347                 symbol_put(ips_link_to_i915_driver);
5348         }
5349 }
5350
5351 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5352 {
5353         /* We only register the i915 ips part with intel-ips once everything is
5354          * set up, to avoid intel-ips sneaking in and reading bogus values. */
5355         spin_lock_irq(&mchdev_lock);
5356         i915_mch_dev = dev_priv;
5357         spin_unlock_irq(&mchdev_lock);
5358
5359         ips_ping_for_i915_load();
5360 }
5361
5362 void intel_gpu_ips_teardown(void)
5363 {
5364         spin_lock_irq(&mchdev_lock);
5365         i915_mch_dev = NULL;
5366         spin_unlock_irq(&mchdev_lock);
5367 }
5368
5369 static void intel_init_emon(struct drm_device *dev)
5370 {
5371         struct drm_i915_private *dev_priv = dev->dev_private;
5372         u32 lcfuse;
5373         u8 pxw[16];
5374         int i;
5375
5376         /* Disable to program */
5377         I915_WRITE(ECR, 0);
5378         POSTING_READ(ECR);
5379
5380         /* Program energy weights for various events */
5381         I915_WRITE(SDEW, 0x15040d00);
5382         I915_WRITE(CSIEW0, 0x007f0000);
5383         I915_WRITE(CSIEW1, 0x1e220004);
5384         I915_WRITE(CSIEW2, 0x04000004);
5385
5386         for (i = 0; i < 5; i++)
5387                 I915_WRITE(PEW + (i * 4), 0);
5388         for (i = 0; i < 3; i++)
5389                 I915_WRITE(DEW + (i * 4), 0);
5390
5391         /* Program P-state weights to account for frequency power adjustment */
5392         for (i = 0; i < 16; i++) {
5393                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5394                 unsigned long freq = intel_pxfreq(pxvidfreq);
5395                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5396                         PXVFREQ_PX_SHIFT;
5397                 unsigned long val;
5398
5399                 val = vid * vid;
5400                 val *= (freq / 1000);
5401                 val *= 255;
5402                 val /= (127*127*900);
5403                 if (val > 0xff)
5404                         DRM_ERROR("bad pxval: %ld\n", val);
5405                 pxw[i] = val;
5406         }
5407         /* Render standby states get 0 weight */
5408         pxw[14] = 0;
5409         pxw[15] = 0;
5410
5411         for (i = 0; i < 4; i++) {
5412                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5413                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5414                 I915_WRITE(PXW + (i * 4), val);
5415         }
5416
5417         /* Adjust magic regs to magic values (more experimental results) */
5418         I915_WRITE(OGW0, 0);
5419         I915_WRITE(OGW1, 0);
5420         I915_WRITE(EG0, 0x00007f00);
5421         I915_WRITE(EG1, 0x0000000e);
5422         I915_WRITE(EG2, 0x000e0000);
5423         I915_WRITE(EG3, 0x68000300);
5424         I915_WRITE(EG4, 0x42000000);
5425         I915_WRITE(EG5, 0x00140031);
5426         I915_WRITE(EG6, 0);
5427         I915_WRITE(EG7, 0);
5428
5429         for (i = 0; i < 8; i++)
5430                 I915_WRITE(PXWL + (i * 4), 0);
5431
5432         /* Enable PMON + select events */
5433         I915_WRITE(ECR, 0x80000019);
5434
5435         lcfuse = I915_READ(LCFUSE02);
5436
5437         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5438 }
5439
5440 void intel_init_gt_powersave(struct drm_device *dev)
5441 {
5442         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5443
5444         if (IS_CHERRYVIEW(dev))
5445                 cherryview_init_gt_powersave(dev);
5446         else if (IS_VALLEYVIEW(dev))
5447                 valleyview_init_gt_powersave(dev);
5448 }
5449
5450 void intel_cleanup_gt_powersave(struct drm_device *dev)
5451 {
5452         if (IS_CHERRYVIEW(dev))
5453                 return;
5454         else if (IS_VALLEYVIEW(dev))
5455                 valleyview_cleanup_gt_powersave(dev);
5456 }
5457
5458 /**
5459  * intel_suspend_gt_powersave - suspend PM work and helper threads
5460  * @dev: drm device
5461  *
5462  * We don't want to disable RC6 or other features here, we just want
5463  * to make sure any work we've queued has finished and won't bother
5464  * us while we're suspended.
5465  */
5466 void intel_suspend_gt_powersave(struct drm_device *dev)
5467 {
5468         struct drm_i915_private *dev_priv = dev->dev_private;
5469
5470         if (INTEL_INFO(dev)->gen < 6)
5471                 return;
5472
5473         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5474
5475         /*
5476          * TODO: disable RPS interrupts on GEN9+ too once RPS support
5477          * is added for it.
5478          */
5479         if (INTEL_INFO(dev)->gen < 9)
5480                 gen6_disable_rps_interrupts(dev);
5481
5482         /* Force GPU to min freq during suspend */
5483         gen6_rps_idle(dev_priv);
5484 }
5485
5486 void intel_disable_gt_powersave(struct drm_device *dev)
5487 {
5488         struct drm_i915_private *dev_priv = dev->dev_private;
5489
5490         if (IS_IRONLAKE_M(dev)) {
5491                 ironlake_disable_drps(dev);
5492                 ironlake_disable_rc6(dev);
5493         } else if (INTEL_INFO(dev)->gen >= 6) {
5494                 intel_suspend_gt_powersave(dev);
5495
5496                 mutex_lock(&dev_priv->rps.hw_lock);
5497                 if (INTEL_INFO(dev)->gen >= 9)
5498                         gen9_disable_rps(dev);
5499                 else if (IS_CHERRYVIEW(dev))
5500                         cherryview_disable_rps(dev);
5501                 else if (IS_VALLEYVIEW(dev))
5502                         valleyview_disable_rps(dev);
5503                 else
5504                         gen6_disable_rps(dev);
5505
5506                 dev_priv->rps.enabled = false;
5507                 mutex_unlock(&dev_priv->rps.hw_lock);
5508         }
5509 }
5510
5511 static void intel_gen6_powersave_work(struct work_struct *work)
5512 {
5513         struct drm_i915_private *dev_priv =
5514                 container_of(work, struct drm_i915_private,
5515                              rps.delayed_resume_work.work);
5516         struct drm_device *dev = dev_priv->dev;
5517
5518         mutex_lock(&dev_priv->rps.hw_lock);
5519
5520         /*
5521          * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is
5522          * added for it.
5523          */
5524         if (INTEL_INFO(dev)->gen < 9)
5525                 gen6_reset_rps_interrupts(dev);
5526
5527         if (IS_CHERRYVIEW(dev)) {
5528                 cherryview_enable_rps(dev);
5529         } else if (IS_VALLEYVIEW(dev)) {
5530                 valleyview_enable_rps(dev);
5531         } else if (INTEL_INFO(dev)->gen >= 9) {
5532                 gen9_enable_rps(dev);
5533         } else if (IS_BROADWELL(dev)) {
5534                 gen8_enable_rps(dev);
5535                 __gen6_update_ring_freq(dev);
5536         } else {
5537                 gen6_enable_rps(dev);
5538                 __gen6_update_ring_freq(dev);
5539         }
5540         dev_priv->rps.enabled = true;
5541
5542         if (INTEL_INFO(dev)->gen < 9)
5543                 gen6_enable_rps_interrupts(dev);
5544
5545         mutex_unlock(&dev_priv->rps.hw_lock);
5546
5547         intel_runtime_pm_put(dev_priv);
5548 }
5549
5550 void intel_enable_gt_powersave(struct drm_device *dev)
5551 {
5552         struct drm_i915_private *dev_priv = dev->dev_private;
5553
5554         if (IS_IRONLAKE_M(dev)) {
5555                 mutex_lock(&dev->struct_mutex);
5556                 ironlake_enable_drps(dev);
5557                 ironlake_enable_rc6(dev);
5558                 intel_init_emon(dev);
5559                 mutex_unlock(&dev->struct_mutex);
5560         } else if (INTEL_INFO(dev)->gen >= 6) {
5561                 /*
5562                  * PCU communication is slow and this doesn't need to be
5563                  * done at any specific time, so do this out of our fast path
5564                  * to make resume and init faster.
5565                  *
5566                  * We depend on the HW RC6 power context save/restore
5567                  * mechanism when entering D3 through runtime PM suspend. So
5568                  * disable RPM until RPS/RC6 is properly setup. We can only
5569                  * get here via the driver load/system resume/runtime resume
5570                  * paths, so the _noresume version is enough (and in case of
5571                  * runtime resume it's necessary).
5572                  */
5573                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5574                                            round_jiffies_up_relative(HZ)))
5575                         intel_runtime_pm_get_noresume(dev_priv);
5576         }
5577 }
5578
5579 void intel_reset_gt_powersave(struct drm_device *dev)
5580 {
5581         struct drm_i915_private *dev_priv = dev->dev_private;
5582
5583         dev_priv->rps.enabled = false;
5584         intel_enable_gt_powersave(dev);
5585 }
5586
5587 static void ibx_init_clock_gating(struct drm_device *dev)
5588 {
5589         struct drm_i915_private *dev_priv = dev->dev_private;
5590
5591         /*
5592          * On Ibex Peak and Cougar Point, we need to disable clock
5593          * gating for the panel power sequencer or it will fail to
5594          * start up when no ports are active.
5595          */
5596         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5597 }
5598
5599 static void g4x_disable_trickle_feed(struct drm_device *dev)
5600 {
5601         struct drm_i915_private *dev_priv = dev->dev_private;
5602         int pipe;
5603
5604         for_each_pipe(dev_priv, pipe) {
5605                 I915_WRITE(DSPCNTR(pipe),
5606                            I915_READ(DSPCNTR(pipe)) |
5607                            DISPPLANE_TRICKLE_FEED_DISABLE);
5608                 intel_flush_primary_plane(dev_priv, pipe);
5609         }
5610 }
5611
5612 static void ilk_init_lp_watermarks(struct drm_device *dev)
5613 {
5614         struct drm_i915_private *dev_priv = dev->dev_private;
5615
5616         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5617         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5618         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5619
5620         /*
5621          * Don't touch WM1S_LP_EN here.
5622          * Doing so could cause underruns.
5623          */
5624 }
5625
5626 static void ironlake_init_clock_gating(struct drm_device *dev)
5627 {
5628         struct drm_i915_private *dev_priv = dev->dev_private;
5629         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5630
5631         /*
5632          * Required for FBC
5633          * WaFbcDisableDpfcClockGating:ilk
5634          */
5635         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5636                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5637                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5638
5639         I915_WRITE(PCH_3DCGDIS0,
5640                    MARIUNIT_CLOCK_GATE_DISABLE |
5641                    SVSMUNIT_CLOCK_GATE_DISABLE);
5642         I915_WRITE(PCH_3DCGDIS1,
5643                    VFMUNIT_CLOCK_GATE_DISABLE);
5644
5645         /*
5646          * According to the spec the following bits should be set in
5647          * order to enable memory self-refresh
5648          * The bit 22/21 of 0x42004
5649          * The bit 5 of 0x42020
5650          * The bit 15 of 0x45000
5651          */
5652         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5653                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
5654                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5655         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5656         I915_WRITE(DISP_ARB_CTL,
5657                    (I915_READ(DISP_ARB_CTL) |
5658                     DISP_FBC_WM_DIS));
5659
5660         ilk_init_lp_watermarks(dev);
5661
5662         /*
5663          * Based on the document from hardware guys the following bits
5664          * should be set unconditionally in order to enable FBC.
5665          * The bit 22 of 0x42000
5666          * The bit 22 of 0x42004
5667          * The bit 7,8,9 of 0x42020.
5668          */
5669         if (IS_IRONLAKE_M(dev)) {
5670                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5671                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5672                            I915_READ(ILK_DISPLAY_CHICKEN1) |
5673                            ILK_FBCQ_DIS);
5674                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5675                            I915_READ(ILK_DISPLAY_CHICKEN2) |
5676                            ILK_DPARB_GATE);
5677         }
5678
5679         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5680
5681         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5682                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5683                    ILK_ELPIN_409_SELECT);
5684         I915_WRITE(_3D_CHICKEN2,
5685                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5686                    _3D_CHICKEN2_WM_READ_PIPELINED);
5687
5688         /* WaDisableRenderCachePipelinedFlush:ilk */
5689         I915_WRITE(CACHE_MODE_0,
5690                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5691
5692         /* WaDisable_RenderCache_OperationalFlush:ilk */
5693         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5694
5695         g4x_disable_trickle_feed(dev);
5696
5697         ibx_init_clock_gating(dev);
5698 }
5699
5700 static void cpt_init_clock_gating(struct drm_device *dev)
5701 {
5702         struct drm_i915_private *dev_priv = dev->dev_private;
5703         int pipe;
5704         uint32_t val;
5705
5706         /*
5707          * On Ibex Peak and Cougar Point, we need to disable clock
5708          * gating for the panel power sequencer or it will fail to
5709          * start up when no ports are active.
5710          */
5711         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5712                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5713                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
5714         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5715                    DPLS_EDP_PPS_FIX_DIS);
5716         /* The below fixes the weird display corruption, a few pixels shifted
5717          * downward, on (only) LVDS of some HP laptops with IVY.
5718          */
5719         for_each_pipe(dev_priv, pipe) {
5720                 val = I915_READ(TRANS_CHICKEN2(pipe));
5721                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5722                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5723                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5724                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5725                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5726                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5727                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5728                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5729         }
5730         /* WADP0ClockGatingDisable */
5731         for_each_pipe(dev_priv, pipe) {
5732                 I915_WRITE(TRANS_CHICKEN1(pipe),
5733                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5734         }
5735 }
5736
5737 static void gen6_check_mch_setup(struct drm_device *dev)
5738 {
5739         struct drm_i915_private *dev_priv = dev->dev_private;
5740         uint32_t tmp;
5741
5742         tmp = I915_READ(MCH_SSKPD);
5743         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5744                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5745                               tmp);
5746 }
5747
5748 static void gen6_init_clock_gating(struct drm_device *dev)
5749 {
5750         struct drm_i915_private *dev_priv = dev->dev_private;
5751         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5752
5753         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5754
5755         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5756                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5757                    ILK_ELPIN_409_SELECT);
5758
5759         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5760         I915_WRITE(_3D_CHICKEN,
5761                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5762
5763         /* WaDisable_RenderCache_OperationalFlush:snb */
5764         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5765
5766         /*
5767          * BSpec recoomends 8x4 when MSAA is used,
5768          * however in practice 16x4 seems fastest.
5769          *
5770          * Note that PS/WM thread counts depend on the WIZ hashing
5771          * disable bit, which we don't touch here, but it's good
5772          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5773          */
5774         I915_WRITE(GEN6_GT_MODE,
5775                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5776
5777         ilk_init_lp_watermarks(dev);
5778
5779         I915_WRITE(CACHE_MODE_0,
5780                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5781
5782         I915_WRITE(GEN6_UCGCTL1,
5783                    I915_READ(GEN6_UCGCTL1) |
5784                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5785                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5786
5787         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5788          * gating disable must be set.  Failure to set it results in
5789          * flickering pixels due to Z write ordering failures after
5790          * some amount of runtime in the Mesa "fire" demo, and Unigine
5791          * Sanctuary and Tropics, and apparently anything else with
5792          * alpha test or pixel discard.
5793          *
5794          * According to the spec, bit 11 (RCCUNIT) must also be set,
5795          * but we didn't debug actual testcases to find it out.
5796          *
5797          * WaDisableRCCUnitClockGating:snb
5798          * WaDisableRCPBUnitClockGating:snb
5799          */
5800         I915_WRITE(GEN6_UCGCTL2,
5801                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5802                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5803
5804         /* WaStripsFansDisableFastClipPerformanceFix:snb */
5805         I915_WRITE(_3D_CHICKEN3,
5806                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5807
5808         /*
5809          * Bspec says:
5810          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5811          * 3DSTATE_SF number of SF output attributes is more than 16."
5812          */
5813         I915_WRITE(_3D_CHICKEN3,
5814                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5815
5816         /*
5817          * According to the spec the following bits should be
5818          * set in order to enable memory self-refresh and fbc:
5819          * The bit21 and bit22 of 0x42000
5820          * The bit21 and bit22 of 0x42004
5821          * The bit5 and bit7 of 0x42020
5822          * The bit14 of 0x70180
5823          * The bit14 of 0x71180
5824          *
5825          * WaFbcAsynchFlipDisableFbcQueue:snb
5826          */
5827         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5828                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5829                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5830         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5831                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5832                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5833         I915_WRITE(ILK_DSPCLK_GATE_D,
5834                    I915_READ(ILK_DSPCLK_GATE_D) |
5835                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
5836                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5837
5838         g4x_disable_trickle_feed(dev);
5839
5840         cpt_init_clock_gating(dev);
5841
5842         gen6_check_mch_setup(dev);
5843 }
5844
5845 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5846 {
5847         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5848
5849         /*
5850          * WaVSThreadDispatchOverride:ivb,vlv
5851          *
5852          * This actually overrides the dispatch
5853          * mode for all thread types.
5854          */
5855         reg &= ~GEN7_FF_SCHED_MASK;
5856         reg |= GEN7_FF_TS_SCHED_HW;
5857         reg |= GEN7_FF_VS_SCHED_HW;
5858         reg |= GEN7_FF_DS_SCHED_HW;
5859
5860         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5861 }
5862
5863 static void lpt_init_clock_gating(struct drm_device *dev)
5864 {
5865         struct drm_i915_private *dev_priv = dev->dev_private;
5866
5867         /*
5868          * TODO: this bit should only be enabled when really needed, then
5869          * disabled when not needed anymore in order to save power.
5870          */
5871         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5872                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5873                            I915_READ(SOUTH_DSPCLK_GATE_D) |
5874                            PCH_LP_PARTITION_LEVEL_DISABLE);
5875
5876         /* WADPOClockGatingDisable:hsw */
5877         I915_WRITE(_TRANSA_CHICKEN1,
5878                    I915_READ(_TRANSA_CHICKEN1) |
5879                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5880 }
5881
5882 static void lpt_suspend_hw(struct drm_device *dev)
5883 {
5884         struct drm_i915_private *dev_priv = dev->dev_private;
5885
5886         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5887                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5888
5889                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5890                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5891         }
5892 }
5893
5894 static void broadwell_init_clock_gating(struct drm_device *dev)
5895 {
5896         struct drm_i915_private *dev_priv = dev->dev_private;
5897         enum pipe pipe;
5898
5899         I915_WRITE(WM3_LP_ILK, 0);
5900         I915_WRITE(WM2_LP_ILK, 0);
5901         I915_WRITE(WM1_LP_ILK, 0);
5902
5903         /* WaSwitchSolVfFArbitrationPriority:bdw */
5904         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5905
5906         /* WaPsrDPAMaskVBlankInSRD:bdw */
5907         I915_WRITE(CHICKEN_PAR1_1,
5908                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5909
5910         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5911         for_each_pipe(dev_priv, pipe) {
5912                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5913                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
5914                            BDW_DPRS_MASK_VBLANK_SRD);
5915         }
5916
5917         /* WaVSRefCountFullforceMissDisable:bdw */
5918         /* WaDSRefCountFullforceMissDisable:bdw */
5919         I915_WRITE(GEN7_FF_THREAD_MODE,
5920                    I915_READ(GEN7_FF_THREAD_MODE) &
5921                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5922
5923         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5924                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5925
5926         /* WaDisableSDEUnitClockGating:bdw */
5927         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5928                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5929
5930         lpt_init_clock_gating(dev);
5931 }
5932
5933 static void haswell_init_clock_gating(struct drm_device *dev)
5934 {
5935         struct drm_i915_private *dev_priv = dev->dev_private;
5936
5937         ilk_init_lp_watermarks(dev);
5938
5939         /* L3 caching of data atomics doesn't work -- disable it. */
5940         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5941         I915_WRITE(HSW_ROW_CHICKEN3,
5942                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5943
5944         /* This is required by WaCatErrorRejectionIssue:hsw */
5945         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5946                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5947                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5948
5949         /* WaVSRefCountFullforceMissDisable:hsw */
5950         I915_WRITE(GEN7_FF_THREAD_MODE,
5951                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5952
5953         /* WaDisable_RenderCache_OperationalFlush:hsw */
5954         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5955
5956         /* enable HiZ Raw Stall Optimization */
5957         I915_WRITE(CACHE_MODE_0_GEN7,
5958                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5959
5960         /* WaDisable4x2SubspanOptimization:hsw */
5961         I915_WRITE(CACHE_MODE_1,
5962                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5963
5964         /*
5965          * BSpec recommends 8x4 when MSAA is used,
5966          * however in practice 16x4 seems fastest.
5967          *
5968          * Note that PS/WM thread counts depend on the WIZ hashing
5969          * disable bit, which we don't touch here, but it's good
5970          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5971          */
5972         I915_WRITE(GEN7_GT_MODE,
5973                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5974
5975         /* WaSwitchSolVfFArbitrationPriority:hsw */
5976         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5977
5978         /* WaRsPkgCStateDisplayPMReq:hsw */
5979         I915_WRITE(CHICKEN_PAR1_1,
5980                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5981
5982         lpt_init_clock_gating(dev);
5983 }
5984
5985 static void ivybridge_init_clock_gating(struct drm_device *dev)
5986 {
5987         struct drm_i915_private *dev_priv = dev->dev_private;
5988         uint32_t snpcr;
5989
5990         ilk_init_lp_watermarks(dev);
5991
5992         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5993
5994         /* WaDisableEarlyCull:ivb */
5995         I915_WRITE(_3D_CHICKEN3,
5996                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5997
5998         /* WaDisableBackToBackFlipFix:ivb */
5999         I915_WRITE(IVB_CHICKEN3,
6000                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6001                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6002
6003         /* WaDisablePSDDualDispatchEnable:ivb */
6004         if (IS_IVB_GT1(dev))
6005                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6006                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6007
6008         /* WaDisable_RenderCache_OperationalFlush:ivb */
6009         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6010
6011         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6012         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6013                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6014
6015         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6016         I915_WRITE(GEN7_L3CNTLREG1,
6017                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6018         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6019                    GEN7_WA_L3_CHICKEN_MODE);
6020         if (IS_IVB_GT1(dev))
6021                 I915_WRITE(GEN7_ROW_CHICKEN2,
6022                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6023         else {
6024                 /* must write both registers */
6025                 I915_WRITE(GEN7_ROW_CHICKEN2,
6026                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6027                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6028                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6029         }
6030
6031         /* WaForceL3Serialization:ivb */
6032         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6033                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6034
6035         /*
6036          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6037          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6038          */
6039         I915_WRITE(GEN6_UCGCTL2,
6040                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6041
6042         /* This is required by WaCatErrorRejectionIssue:ivb */
6043         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6044                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6045                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6046
6047         g4x_disable_trickle_feed(dev);
6048
6049         gen7_setup_fixed_func_scheduler(dev_priv);
6050
6051         if (0) { /* causes HiZ corruption on ivb:gt1 */
6052                 /* enable HiZ Raw Stall Optimization */
6053                 I915_WRITE(CACHE_MODE_0_GEN7,
6054                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6055         }
6056
6057         /* WaDisable4x2SubspanOptimization:ivb */
6058         I915_WRITE(CACHE_MODE_1,
6059                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6060
6061         /*
6062          * BSpec recommends 8x4 when MSAA is used,
6063          * however in practice 16x4 seems fastest.
6064          *
6065          * Note that PS/WM thread counts depend on the WIZ hashing
6066          * disable bit, which we don't touch here, but it's good
6067          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6068          */
6069         I915_WRITE(GEN7_GT_MODE,
6070                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
6071
6072         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6073         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6074         snpcr |= GEN6_MBC_SNPCR_MED;
6075         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6076
6077         if (!HAS_PCH_NOP(dev))
6078                 cpt_init_clock_gating(dev);
6079
6080         gen6_check_mch_setup(dev);
6081 }
6082
6083 static void valleyview_init_clock_gating(struct drm_device *dev)
6084 {
6085         struct drm_i915_private *dev_priv = dev->dev_private;
6086
6087         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6088
6089         /* WaDisableEarlyCull:vlv */
6090         I915_WRITE(_3D_CHICKEN3,
6091                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6092
6093         /* WaDisableBackToBackFlipFix:vlv */
6094         I915_WRITE(IVB_CHICKEN3,
6095                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6096                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6097
6098         /* WaPsdDispatchEnable:vlv */
6099         /* WaDisablePSDDualDispatchEnable:vlv */
6100         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6101                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6102                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6103
6104         /* WaDisable_RenderCache_OperationalFlush:vlv */
6105         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6106
6107         /* WaForceL3Serialization:vlv */
6108         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6109                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6110
6111         /* WaDisableDopClockGating:vlv */
6112         I915_WRITE(GEN7_ROW_CHICKEN2,
6113                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6114
6115         /* This is required by WaCatErrorRejectionIssue:vlv */
6116         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6117                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6118                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6119
6120         gen7_setup_fixed_func_scheduler(dev_priv);
6121
6122         /*
6123          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6124          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6125          */
6126         I915_WRITE(GEN6_UCGCTL2,
6127                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6128
6129         /* WaDisableL3Bank2xClockGate:vlv
6130          * Disabling L3 clock gating- MMIO 940c[25] = 1
6131          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6132         I915_WRITE(GEN7_UCGCTL4,
6133                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6134
6135         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6136
6137         /*
6138          * BSpec says this must be set, even though
6139          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6140          */
6141         I915_WRITE(CACHE_MODE_1,
6142                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6143
6144         /*
6145          * WaIncreaseL3CreditsForVLVB0:vlv
6146          * This is the hardware default actually.
6147          */
6148         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6149
6150         /*
6151          * WaDisableVLVClockGating_VBIIssue:vlv
6152          * Disable clock gating on th GCFG unit to prevent a delay
6153          * in the reporting of vblank events.
6154          */
6155         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6156 }
6157
6158 static void cherryview_init_clock_gating(struct drm_device *dev)
6159 {
6160         struct drm_i915_private *dev_priv = dev->dev_private;
6161
6162         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6163
6164         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6165
6166         /* WaVSRefCountFullforceMissDisable:chv */
6167         /* WaDSRefCountFullforceMissDisable:chv */
6168         I915_WRITE(GEN7_FF_THREAD_MODE,
6169                    I915_READ(GEN7_FF_THREAD_MODE) &
6170                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6171
6172         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6173         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6174                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6175
6176         /* WaDisableCSUnitClockGating:chv */
6177         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6178                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6179
6180         /* WaDisableSDEUnitClockGating:chv */
6181         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6182                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6183 }
6184
6185 static void g4x_init_clock_gating(struct drm_device *dev)
6186 {
6187         struct drm_i915_private *dev_priv = dev->dev_private;
6188         uint32_t dspclk_gate;
6189
6190         I915_WRITE(RENCLK_GATE_D1, 0);
6191         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6192                    GS_UNIT_CLOCK_GATE_DISABLE |
6193                    CL_UNIT_CLOCK_GATE_DISABLE);
6194         I915_WRITE(RAMCLK_GATE_D, 0);
6195         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6196                 OVRUNIT_CLOCK_GATE_DISABLE |
6197                 OVCUNIT_CLOCK_GATE_DISABLE;
6198         if (IS_GM45(dev))
6199                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6200         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6201
6202         /* WaDisableRenderCachePipelinedFlush */
6203         I915_WRITE(CACHE_MODE_0,
6204                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6205
6206         /* WaDisable_RenderCache_OperationalFlush:g4x */
6207         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6208
6209         g4x_disable_trickle_feed(dev);
6210 }
6211
6212 static void crestline_init_clock_gating(struct drm_device *dev)
6213 {
6214         struct drm_i915_private *dev_priv = dev->dev_private;
6215
6216         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6217         I915_WRITE(RENCLK_GATE_D2, 0);
6218         I915_WRITE(DSPCLK_GATE_D, 0);
6219         I915_WRITE(RAMCLK_GATE_D, 0);
6220         I915_WRITE16(DEUC, 0);
6221         I915_WRITE(MI_ARB_STATE,
6222                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6223
6224         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6225         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6226 }
6227
6228 static void broadwater_init_clock_gating(struct drm_device *dev)
6229 {
6230         struct drm_i915_private *dev_priv = dev->dev_private;
6231
6232         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6233                    I965_RCC_CLOCK_GATE_DISABLE |
6234                    I965_RCPB_CLOCK_GATE_DISABLE |
6235                    I965_ISC_CLOCK_GATE_DISABLE |
6236                    I965_FBC_CLOCK_GATE_DISABLE);
6237         I915_WRITE(RENCLK_GATE_D2, 0);
6238         I915_WRITE(MI_ARB_STATE,
6239                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6240
6241         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6242         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6243 }
6244
6245 static void gen3_init_clock_gating(struct drm_device *dev)
6246 {
6247         struct drm_i915_private *dev_priv = dev->dev_private;
6248         u32 dstate = I915_READ(D_STATE);
6249
6250         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6251                 DSTATE_DOT_CLOCK_GATING;
6252         I915_WRITE(D_STATE, dstate);
6253
6254         if (IS_PINEVIEW(dev))
6255                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6256
6257         /* IIR "flip pending" means done if this bit is set */
6258         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6259
6260         /* interrupts should cause a wake up from C3 */
6261         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6262
6263         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6264         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6265
6266         I915_WRITE(MI_ARB_STATE,
6267                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6268 }
6269
6270 static void i85x_init_clock_gating(struct drm_device *dev)
6271 {
6272         struct drm_i915_private *dev_priv = dev->dev_private;
6273
6274         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6275
6276         /* interrupts should cause a wake up from C3 */
6277         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6278                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6279
6280         I915_WRITE(MEM_MODE,
6281                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6282 }
6283
6284 static void i830_init_clock_gating(struct drm_device *dev)
6285 {
6286         struct drm_i915_private *dev_priv = dev->dev_private;
6287
6288         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6289
6290         I915_WRITE(MEM_MODE,
6291                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6292                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6293 }
6294
6295 void intel_init_clock_gating(struct drm_device *dev)
6296 {
6297         struct drm_i915_private *dev_priv = dev->dev_private;
6298
6299         dev_priv->display.init_clock_gating(dev);
6300 }
6301
6302 void intel_suspend_hw(struct drm_device *dev)
6303 {
6304         if (HAS_PCH_LPT(dev))
6305                 lpt_suspend_hw(dev);
6306 }
6307
6308 /* Set up chip specific power management-related functions */
6309 void intel_init_pm(struct drm_device *dev)
6310 {
6311         struct drm_i915_private *dev_priv = dev->dev_private;
6312
6313         intel_fbc_init(dev_priv);
6314
6315         /* For cxsr */
6316         if (IS_PINEVIEW(dev))
6317                 i915_pineview_get_mem_freq(dev);
6318         else if (IS_GEN5(dev))
6319                 i915_ironlake_get_mem_freq(dev);
6320
6321         /* For FIFO watermark updates */
6322         if (INTEL_INFO(dev)->gen >= 9) {
6323                 skl_setup_wm_latency(dev);
6324
6325                 dev_priv->display.init_clock_gating = gen9_init_clock_gating;
6326                 dev_priv->display.update_wm = skl_update_wm;
6327                 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
6328         } else if (HAS_PCH_SPLIT(dev)) {
6329                 ilk_setup_wm_latency(dev);
6330
6331                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6332                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6333                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6334                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6335                         dev_priv->display.update_wm = ilk_update_wm;
6336                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6337                 } else {
6338                         DRM_DEBUG_KMS("Failed to read display plane latency. "
6339                                       "Disable CxSR\n");
6340                 }
6341
6342                 if (IS_GEN5(dev))
6343                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6344                 else if (IS_GEN6(dev))
6345                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6346                 else if (IS_IVYBRIDGE(dev))
6347                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6348                 else if (IS_HASWELL(dev))
6349                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6350                 else if (INTEL_INFO(dev)->gen == 8)
6351                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
6352         } else if (IS_CHERRYVIEW(dev)) {
6353                 dev_priv->display.update_wm = cherryview_update_wm;
6354                 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6355                 dev_priv->display.init_clock_gating =
6356                         cherryview_init_clock_gating;
6357         } else if (IS_VALLEYVIEW(dev)) {
6358                 dev_priv->display.update_wm = valleyview_update_wm;
6359                 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6360                 dev_priv->display.init_clock_gating =
6361                         valleyview_init_clock_gating;
6362         } else if (IS_PINEVIEW(dev)) {
6363                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6364                                             dev_priv->is_ddr3,
6365                                             dev_priv->fsb_freq,
6366                                             dev_priv->mem_freq)) {
6367                         DRM_INFO("failed to find known CxSR latency "
6368                                  "(found ddr%s fsb freq %d, mem freq %d), "
6369                                  "disabling CxSR\n",
6370                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6371                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6372                         /* Disable CxSR and never update its watermark again */
6373                         intel_set_memory_cxsr(dev_priv, false);
6374                         dev_priv->display.update_wm = NULL;
6375                 } else
6376                         dev_priv->display.update_wm = pineview_update_wm;
6377                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6378         } else if (IS_G4X(dev)) {
6379                 dev_priv->display.update_wm = g4x_update_wm;
6380                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6381         } else if (IS_GEN4(dev)) {
6382                 dev_priv->display.update_wm = i965_update_wm;
6383                 if (IS_CRESTLINE(dev))
6384                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6385                 else if (IS_BROADWATER(dev))
6386                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6387         } else if (IS_GEN3(dev)) {
6388                 dev_priv->display.update_wm = i9xx_update_wm;
6389                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6390                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6391         } else if (IS_GEN2(dev)) {
6392                 if (INTEL_INFO(dev)->num_pipes == 1) {
6393                         dev_priv->display.update_wm = i845_update_wm;
6394                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6395                 } else {
6396                         dev_priv->display.update_wm = i9xx_update_wm;
6397                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6398                 }
6399
6400                 if (IS_I85X(dev) || IS_I865G(dev))
6401                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6402                 else
6403                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
6404         } else {
6405                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6406         }
6407 }
6408
6409 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
6410 {
6411         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6412
6413         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6414                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6415                 return -EAGAIN;
6416         }
6417
6418         I915_WRITE(GEN6_PCODE_DATA, *val);
6419         I915_WRITE(GEN6_PCODE_DATA1, 0);
6420         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6421
6422         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6423                      500)) {
6424                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6425                 return -ETIMEDOUT;
6426         }
6427
6428         *val = I915_READ(GEN6_PCODE_DATA);
6429         I915_WRITE(GEN6_PCODE_DATA, 0);
6430
6431         return 0;
6432 }
6433
6434 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
6435 {
6436         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6437
6438         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6439                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6440                 return -EAGAIN;
6441         }
6442
6443         I915_WRITE(GEN6_PCODE_DATA, val);
6444         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6445
6446         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6447                      500)) {
6448                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6449                 return -ETIMEDOUT;
6450         }
6451
6452         I915_WRITE(GEN6_PCODE_DATA, 0);
6453
6454         return 0;
6455 }
6456
6457 static int vlv_gpu_freq_div(unsigned int czclk_freq)
6458 {
6459         switch (czclk_freq) {
6460         case 200:
6461                 return 10;
6462         case 267:
6463                 return 12;
6464         case 320:
6465         case 333:
6466                 return 16;
6467         case 400:
6468                 return 20;
6469         default:
6470                 return -1;
6471         }
6472 }
6473
6474 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6475 {
6476         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6477
6478         div = vlv_gpu_freq_div(czclk_freq);
6479         if (div < 0)
6480                 return div;
6481
6482         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
6483 }
6484
6485 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
6486 {
6487         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6488
6489         mul = vlv_gpu_freq_div(czclk_freq);
6490         if (mul < 0)
6491                 return mul;
6492
6493         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
6494 }
6495
6496 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6497 {
6498         int div, czclk_freq = dev_priv->rps.cz_freq;
6499
6500         div = vlv_gpu_freq_div(czclk_freq) / 2;
6501         if (div < 0)
6502                 return div;
6503
6504         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
6505 }
6506
6507 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6508 {
6509         int mul, czclk_freq = dev_priv->rps.cz_freq;
6510
6511         mul = vlv_gpu_freq_div(czclk_freq) / 2;
6512         if (mul < 0)
6513                 return mul;
6514
6515         /* CHV needs even values */
6516         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
6517 }
6518
6519 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6520 {
6521         int ret = -1;
6522
6523         if (IS_CHERRYVIEW(dev_priv->dev))
6524                 ret = chv_gpu_freq(dev_priv, val);
6525         else if (IS_VALLEYVIEW(dev_priv->dev))
6526                 ret = byt_gpu_freq(dev_priv, val);
6527
6528         return ret;
6529 }
6530
6531 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6532 {
6533         int ret = -1;
6534
6535         if (IS_CHERRYVIEW(dev_priv->dev))
6536                 ret = chv_freq_opcode(dev_priv, val);
6537         else if (IS_VALLEYVIEW(dev_priv->dev))
6538                 ret = byt_freq_opcode(dev_priv, val);
6539
6540         return ret;
6541 }
6542
6543 void intel_pm_setup(struct drm_device *dev)
6544 {
6545         struct drm_i915_private *dev_priv = dev->dev_private;
6546
6547         mutex_init(&dev_priv->rps.hw_lock);
6548
6549         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6550                           intel_gen6_powersave_work);
6551
6552         dev_priv->pm.suspended = false;
6553 }