drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * DOC: RC6
  36  *
  37  * RC6 is a special power stage which allows the GPU to enter an very
  38  * low-voltage mode when idle, using down to 0V while at this stage.  This
  39  * stage is entered automatically when the GPU is idle when RC6 support is
  40  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  41  *
  42  * There are different RC6 modes available in Intel GPU, which differentiate
  43  * among each other with the latency required to enter and leave RC6 and
  44  * voltage consumed by the GPU in different states.
  45  *
  46  * The combination of the following flags define which states GPU is allowed
  47  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  48  * RC6pp is deepest RC6. Their support by hardware varies according to the
  49  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  50  * which brings the most power savings; deeper states save more power, but
  51  * require higher latency to switch to and wake up.
  52  */
  53 #define INTEL_RC6_ENABLE                        (1<<0)
  54 #define INTEL_RC6p_ENABLE                       (1<<1)
  55 #define INTEL_RC6pp_ENABLE                      (1<<2)
  56
  57 static void bxt_init_clock_gating(struct drm_device *dev)
  58 {
  59         struct drm_i915_private *dev_priv = dev->dev_private;
  60
  61         /* WaDisableSDEUnitClockGating:bxt */
  62         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  63                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  64
  65         /*
  66          * FIXME:
  67          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  68          */
  69         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  70                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  71
  72         /*
  73          * Wa: Backlight PWM may stop in the asserted state, causing backlight
  74          * to stay fully on.
  75          */
  76         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
  77                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
  78                            PWM1_GATING_DIS | PWM2_GATING_DIS);
  79 }
  80
  81 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84         u32 tmp;
  85
  86         tmp = I915_READ(CLKCFG);
  87
  88         switch (tmp & CLKCFG_FSB_MASK) {
  89         case CLKCFG_FSB_533:
  90                 dev_priv->fsb_freq = 533; /* 133*4 */
  91                 break;
  92         case CLKCFG_FSB_800:
  93                 dev_priv->fsb_freq = 800; /* 200*4 */
  94                 break;
  95         case CLKCFG_FSB_667:
  96                 dev_priv->fsb_freq =  667; /* 167*4 */
  97                 break;
  98         case CLKCFG_FSB_400:
  99                 dev_priv->fsb_freq = 400; /* 100*4 */
 100                 break;
 101         }
 102
 103         switch (tmp & CLKCFG_MEM_MASK) {
 104         case CLKCFG_MEM_533:
 105                 dev_priv->mem_freq = 533;
 106                 break;
 107         case CLKCFG_MEM_667:
 108                 dev_priv->mem_freq = 667;
 109                 break;
 110         case CLKCFG_MEM_800:
 111                 dev_priv->mem_freq = 800;
 112                 break;
 113         }
 114
 115         /* detect pineview DDR3 setting */
 116         tmp = I915_READ(CSHRDDR3CTL);
 117         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 118 }
 119
 120 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         u16 ddrpll, csipll;
 124
 125         ddrpll = I915_READ16(DDRMPLL1);
 126         csipll = I915_READ16(CSIPLL0);
 127
 128         switch (ddrpll & 0xff) {
 129         case 0xc:
 130                 dev_priv->mem_freq = 800;
 131                 break;
 132         case 0x10:
 133                 dev_priv->mem_freq = 1066;
 134                 break;
 135         case 0x14:
 136                 dev_priv->mem_freq = 1333;
 137                 break;
 138         case 0x18:
 139                 dev_priv->mem_freq = 1600;
 140                 break;
 141         default:
 142                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 143                                  ddrpll & 0xff);
 144                 dev_priv->mem_freq = 0;
 145                 break;
 146         }
 147
 148         dev_priv->ips.r_t = dev_priv->mem_freq;
 149
 150         switch (csipll & 0x3ff) {
 151         case 0x00c:
 152                 dev_priv->fsb_freq = 3200;
 153                 break;
 154         case 0x00e:
 155                 dev_priv->fsb_freq = 3733;
 156                 break;
 157         case 0x010:
 158                 dev_priv->fsb_freq = 4266;
 159                 break;
 160         case 0x012:
 161                 dev_priv->fsb_freq = 4800;
 162                 break;
 163         case 0x014:
 164                 dev_priv->fsb_freq = 5333;
 165                 break;
 166         case 0x016:
 167                 dev_priv->fsb_freq = 5866;
 168                 break;
 169         case 0x018:
 170                 dev_priv->fsb_freq = 6400;
 171                 break;
 172         default:
 173                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 174                                  csipll & 0x3ff);
 175                 dev_priv->fsb_freq = 0;
 176                 break;
 177         }
 178
 179         if (dev_priv->fsb_freq == 3200) {
 180                 dev_priv->ips.c_m = 0;
 181         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 182                 dev_priv->ips.c_m = 1;
 183         } else {
 184                 dev_priv->ips.c_m = 2;
 185         }
 186 }
 187
 188 static const struct cxsr_latency cxsr_latency_table[] = {
 189         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 190         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 191         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 192         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 193         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 194
 195         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 196         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 197         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 198         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 199         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 200
 201         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 202         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 203         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 204         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 205         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 206
 207         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 208         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 209         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 210         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 211         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 212
 213         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 214         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 215         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 216         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 217         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 218
 219         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 220         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 221         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 222         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 223         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 224 };
 225
 226 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 227                                                          int is_ddr3,
 228                                                          int fsb,
 229                                                          int mem)
 230 {
 231         const struct cxsr_latency *latency;
 232         int i;
 233
 234         if (fsb == 0 || mem == 0)
 235                 return NULL;
 236
 237         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 238                 latency = &cxsr_latency_table[i];
 239                 if (is_desktop == latency->is_desktop &&
 240                     is_ddr3 == latency->is_ddr3 &&
 241                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 242                         return latency;
 243         }
 244
 245         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 246
 247         return NULL;
 248 }
 249
 250 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 251 {
 252         u32 val;
 253
 254         mutex_lock(&dev_priv->rps.hw_lock);
 255
 256         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 257         if (enable)
 258                 val &= ~FORCE_DDR_HIGH_FREQ;
 259         else
 260                 val |= FORCE_DDR_HIGH_FREQ;
 261         val &= ~FORCE_DDR_LOW_FREQ;
 262         val |= FORCE_DDR_FREQ_REQ_ACK;
 263         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 264
 265         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 266                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 267                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 268
 269         mutex_unlock(&dev_priv->rps.hw_lock);
 270 }
 271
 272 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 273 {
 274         u32 val;
 275
 276         mutex_lock(&dev_priv->rps.hw_lock);
 277
 278         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 279         if (enable)
 280                 val |= DSP_MAXFIFO_PM5_ENABLE;
 281         else
 282                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 283         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 284
 285         mutex_unlock(&dev_priv->rps.hw_lock);
 286 }
 287
 288 #define FW_WM(value, plane) \
 289         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 290
 291 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 292 {
 293         struct drm_device *dev = dev_priv->dev;
 294         u32 val;
 295
 296         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 297                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 298                 POSTING_READ(FW_BLC_SELF_VLV);
 299                 dev_priv->wm.vlv.cxsr = enable;
 300         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 301                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 302                 POSTING_READ(FW_BLC_SELF);
 303         } else if (IS_PINEVIEW(dev)) {
 304                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 305                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 306                 I915_WRITE(DSPFW3, val);
 307                 POSTING_READ(DSPFW3);
 308         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 309                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 310                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 311                 I915_WRITE(FW_BLC_SELF, val);
 312                 POSTING_READ(FW_BLC_SELF);
 313         } else if (IS_I915GM(dev)) {
 314                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 315                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 316                 I915_WRITE(INSTPM, val);
 317                 POSTING_READ(INSTPM);
 318         } else {
 319                 return;
 320         }
 321
 322         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 323                       enable ? "enabled" : "disabled");
 324 }
 325
 326
 327 /*
 328  * Latency for FIFO fetches is dependent on several factors:
 329  *   - memory configuration (speed, channels)
 330  *   - chipset
 331  *   - current MCH state
 332  * It can be fairly high in some situations, so here we assume a fairly
 333  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 334  * set this value too high, the FIFO will fetch frequently to stay full)
 335  * and power consumption (set it too low to save power and we might see
 336  * FIFO underruns and display "flicker").
 337  *
 338  * A value of 5us seems to be a good balance; safe for very low end
 339  * platforms but not overly aggressive on lower latency configs.
 340  */
 341 static const int pessimal_latency_ns = 5000;
 342
 343 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 344         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 345
 346 static int vlv_get_fifo_size(struct drm_device *dev,
 347                               enum pipe pipe, int plane)
 348 {
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350         int sprite0_start, sprite1_start, size;
 351
 352         switch (pipe) {
 353                 uint32_t dsparb, dsparb2, dsparb3;
 354         case PIPE_A:
 355                 dsparb = I915_READ(DSPARB);
 356                 dsparb2 = I915_READ(DSPARB2);
 357                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 358                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 359                 break;
 360         case PIPE_B:
 361                 dsparb = I915_READ(DSPARB);
 362                 dsparb2 = I915_READ(DSPARB2);
 363                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 364                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 365                 break;
 366         case PIPE_C:
 367                 dsparb2 = I915_READ(DSPARB2);
 368                 dsparb3 = I915_READ(DSPARB3);
 369                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 370                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 371                 break;
 372         default:
 373                 return 0;
 374         }
 375
 376         switch (plane) {
 377         case 0:
 378                 size = sprite0_start;
 379                 break;
 380         case 1:
 381                 size = sprite1_start - sprite0_start;
 382                 break;
 383         case 2:
 384                 size = 512 - 1 - sprite1_start;
 385                 break;
 386         default:
 387                 return 0;
 388         }
 389
 390         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 391                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 392                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 393                       size);
 394
 395         return size;
 396 }
 397
 398 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 399 {
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         uint32_t dsparb = I915_READ(DSPARB);
 402         int size;
 403
 404         size = dsparb & 0x7f;
 405         if (plane)
 406                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 407
 408         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 409                       plane ? "B" : "A", size);
 410
 411         return size;
 412 }
 413
 414 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417         uint32_t dsparb = I915_READ(DSPARB);
 418         int size;
 419
 420         size = dsparb & 0x1ff;
 421         if (plane)
 422                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 423         size >>= 1; /* Convert to cachelines */
 424
 425         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 426                       plane ? "B" : "A", size);
 427
 428         return size;
 429 }
 430
 431 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 432 {
 433         struct drm_i915_private *dev_priv = dev->dev_private;
 434         uint32_t dsparb = I915_READ(DSPARB);
 435         int size;
 436
 437         size = dsparb & 0x7f;
 438         size >>= 2; /* Convert to cachelines */
 439
 440         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 441                       plane ? "B" : "A",
 442                       size);
 443
 444         return size;
 445 }
 446
 447 /* Pineview has different values for various configs */
 448 static const struct intel_watermark_params pineview_display_wm = {
 449         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 450         .max_wm = PINEVIEW_MAX_WM,
 451         .default_wm = PINEVIEW_DFT_WM,
 452         .guard_size = PINEVIEW_GUARD_WM,
 453         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 454 };
 455 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 456         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 457         .max_wm = PINEVIEW_MAX_WM,
 458         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 459         .guard_size = PINEVIEW_GUARD_WM,
 460         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 461 };
 462 static const struct intel_watermark_params pineview_cursor_wm = {
 463         .fifo_size = PINEVIEW_CURSOR_FIFO,
 464         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 465         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 466         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 467         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 468 };
 469 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 470         .fifo_size = PINEVIEW_CURSOR_FIFO,
 471         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 472         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 473         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 474         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 475 };
 476 static const struct intel_watermark_params g4x_wm_info = {
 477         .fifo_size = G4X_FIFO_SIZE,
 478         .max_wm = G4X_MAX_WM,
 479         .default_wm = G4X_MAX_WM,
 480         .guard_size = 2,
 481         .cacheline_size = G4X_FIFO_LINE_SIZE,
 482 };
 483 static const struct intel_watermark_params g4x_cursor_wm_info = {
 484         .fifo_size = I965_CURSOR_FIFO,
 485         .max_wm = I965_CURSOR_MAX_WM,
 486         .default_wm = I965_CURSOR_DFT_WM,
 487         .guard_size = 2,
 488         .cacheline_size = G4X_FIFO_LINE_SIZE,
 489 };
 490 static const struct intel_watermark_params i965_cursor_wm_info = {
 491         .fifo_size = I965_CURSOR_FIFO,
 492         .max_wm = I965_CURSOR_MAX_WM,
 493         .default_wm = I965_CURSOR_DFT_WM,
 494         .guard_size = 2,
 495         .cacheline_size = I915_FIFO_LINE_SIZE,
 496 };
 497 static const struct intel_watermark_params i945_wm_info = {
 498         .fifo_size = I945_FIFO_SIZE,
 499         .max_wm = I915_MAX_WM,
 500         .default_wm = 1,
 501         .guard_size = 2,
 502         .cacheline_size = I915_FIFO_LINE_SIZE,
 503 };
 504 static const struct intel_watermark_params i915_wm_info = {
 505         .fifo_size = I915_FIFO_SIZE,
 506         .max_wm = I915_MAX_WM,
 507         .default_wm = 1,
 508         .guard_size = 2,
 509         .cacheline_size = I915_FIFO_LINE_SIZE,
 510 };
 511 static const struct intel_watermark_params i830_a_wm_info = {
 512         .fifo_size = I855GM_FIFO_SIZE,
 513         .max_wm = I915_MAX_WM,
 514         .default_wm = 1,
 515         .guard_size = 2,
 516         .cacheline_size = I830_FIFO_LINE_SIZE,
 517 };
 518 static const struct intel_watermark_params i830_bc_wm_info = {
 519         .fifo_size = I855GM_FIFO_SIZE,
 520         .max_wm = I915_MAX_WM/2,
 521         .default_wm = 1,
 522         .guard_size = 2,
 523         .cacheline_size = I830_FIFO_LINE_SIZE,
 524 };
 525 static const struct intel_watermark_params i845_wm_info = {
 526         .fifo_size = I830_FIFO_SIZE,
 527         .max_wm = I915_MAX_WM,
 528         .default_wm = 1,
 529         .guard_size = 2,
 530         .cacheline_size = I830_FIFO_LINE_SIZE,
 531 };
 532
 533 /**
 534  * intel_calculate_wm - calculate watermark level
 535  * @clock_in_khz: pixel clock
 536  * @wm: chip FIFO params
 537  * @cpp: bytes per pixel
 538  * @latency_ns: memory latency for the platform
 539  *
 540  * Calculate the watermark level (the level at which the display plane will
 541  * start fetching from memory again).  Each chip has a different display
 542  * FIFO size and allocation, so the caller needs to figure that out and pass
 543  * in the correct intel_watermark_params structure.
 544  *
 545  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 546  * on the pixel size.  When it reaches the watermark level, it'll start
 547  * fetching FIFO line sized based chunks from memory until the FIFO fills
 548  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 549  * will occur, and a display engine hang could result.
 550  */
 551 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 552                                         const struct intel_watermark_params *wm,
 553                                         int fifo_size, int cpp,
 554                                         unsigned long latency_ns)
 555 {
 556         long entries_required, wm_size;
 557
 558         /*
 559          * Note: we need to make sure we don't overflow for various clock &
 560          * latency values.
 561          * clocks go from a few thousand to several hundred thousand.
 562          * latency is usually a few thousand
 563          */
 564         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 565                 1000;
 566         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 567
 568         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 569
 570         wm_size = fifo_size - (entries_required + wm->guard_size);
 571
 572         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 573
 574         /* Don't promote wm_size to unsigned... */
 575         if (wm_size > (long)wm->max_wm)
 576                 wm_size = wm->max_wm;
 577         if (wm_size <= 0)
 578                 wm_size = wm->default_wm;
 579
 580         /*
 581          * Bspec seems to indicate that the value shouldn't be lower than
 582          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 583          * Lets go for 8 which is the burst size since certain platforms
 584          * already use a hardcoded 8 (which is what the spec says should be
 585          * done).
 586          */
 587         if (wm_size <= 8)
 588                 wm_size = 8;
 589
 590         return wm_size;
 591 }
 592
 593 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 594 {
 595         struct drm_crtc *crtc, *enabled = NULL;
 596
 597         for_each_crtc(dev, crtc) {
 598                 if (intel_crtc_active(crtc)) {
 599                         if (enabled)
 600                                 return NULL;
 601                         enabled = crtc;
 602                 }
 603         }
 604
 605         return enabled;
 606 }
 607
 608 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 609 {
 610         struct drm_device *dev = unused_crtc->dev;
 611         struct drm_i915_private *dev_priv = dev->dev_private;
 612         struct drm_crtc *crtc;
 613         const struct cxsr_latency *latency;
 614         u32 reg;
 615         unsigned long wm;
 616
 617         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 618                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 619         if (!latency) {
 620                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 621                 intel_set_memory_cxsr(dev_priv, false);
 622                 return;
 623         }
 624
 625         crtc = single_enabled_crtc(dev);
 626         if (crtc) {
 627                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 628                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 629                 int clock = adjusted_mode->crtc_clock;
 630
 631                 /* Display SR */
 632                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 633                                         pineview_display_wm.fifo_size,
 634                                         cpp, latency->display_sr);
 635                 reg = I915_READ(DSPFW1);
 636                 reg &= ~DSPFW_SR_MASK;
 637                 reg |= FW_WM(wm, SR);
 638                 I915_WRITE(DSPFW1, reg);
 639                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 640
 641                 /* cursor SR */
 642                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 643                                         pineview_display_wm.fifo_size,
 644                                         cpp, latency->cursor_sr);
 645                 reg = I915_READ(DSPFW3);
 646                 reg &= ~DSPFW_CURSOR_SR_MASK;
 647                 reg |= FW_WM(wm, CURSOR_SR);
 648                 I915_WRITE(DSPFW3, reg);
 649
 650                 /* Display HPLL off SR */
 651                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 652                                         pineview_display_hplloff_wm.fifo_size,
 653                                         cpp, latency->display_hpll_disable);
 654                 reg = I915_READ(DSPFW3);
 655                 reg &= ~DSPFW_HPLL_SR_MASK;
 656                 reg |= FW_WM(wm, HPLL_SR);
 657                 I915_WRITE(DSPFW3, reg);
 658
 659                 /* cursor HPLL off SR */
 660                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 661                                         pineview_display_hplloff_wm.fifo_size,
 662                                         cpp, latency->cursor_hpll_disable);
 663                 reg = I915_READ(DSPFW3);
 664                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 665                 reg |= FW_WM(wm, HPLL_CURSOR);
 666                 I915_WRITE(DSPFW3, reg);
 667                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 668
 669                 intel_set_memory_cxsr(dev_priv, true);
 670         } else {
 671                 intel_set_memory_cxsr(dev_priv, false);
 672         }
 673 }
 674
 675 static bool g4x_compute_wm0(struct drm_device *dev,
 676                             int plane,
 677                             const struct intel_watermark_params *display,
 678                             int display_latency_ns,
 679                             const struct intel_watermark_params *cursor,
 680                             int cursor_latency_ns,
 681                             int *plane_wm,
 682                             int *cursor_wm)
 683 {
 684         struct drm_crtc *crtc;
 685         const struct drm_display_mode *adjusted_mode;
 686         int htotal, hdisplay, clock, cpp;
 687         int line_time_us, line_count;
 688         int entries, tlb_miss;
 689
 690         crtc = intel_get_crtc_for_plane(dev, plane);
 691         if (!intel_crtc_active(crtc)) {
 692                 *cursor_wm = cursor->guard_size;
 693                 *plane_wm = display->guard_size;
 694                 return false;
 695         }
 696
 697         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 698         clock = adjusted_mode->crtc_clock;
 699         htotal = adjusted_mode->crtc_htotal;
 700         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 701         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 702
 703         /* Use the small buffer method to calculate plane watermark */
 704         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 705         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 706         if (tlb_miss > 0)
 707                 entries += tlb_miss;
 708         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 709         *plane_wm = entries + display->guard_size;
 710         if (*plane_wm > (int)display->max_wm)
 711                 *plane_wm = display->max_wm;
 712
 713         /* Use the large buffer method to calculate cursor watermark */
 714         line_time_us = max(htotal * 1000 / clock, 1);
 715         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 716         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 717         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 718         if (tlb_miss > 0)
 719                 entries += tlb_miss;
 720         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 721         *cursor_wm = entries + cursor->guard_size;
 722         if (*cursor_wm > (int)cursor->max_wm)
 723                 *cursor_wm = (int)cursor->max_wm;
 724
 725         return true;
 726 }
 727
 728 /*
 729  * Check the wm result.
 730  *
 731  * If any calculated watermark values is larger than the maximum value that
 732  * can be programmed into the associated watermark register, that watermark
 733  * must be disabled.
 734  */
 735 static bool g4x_check_srwm(struct drm_device *dev,
 736                            int display_wm, int cursor_wm,
 737                            const struct intel_watermark_params *display,
 738                            const struct intel_watermark_params *cursor)
 739 {
 740         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 741                       display_wm, cursor_wm);
 742
 743         if (display_wm > display->max_wm) {
 744                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 745                               display_wm, display->max_wm);
 746                 return false;
 747         }
 748
 749         if (cursor_wm > cursor->max_wm) {
 750                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 751                               cursor_wm, cursor->max_wm);
 752                 return false;
 753         }
 754
 755         if (!(display_wm || cursor_wm)) {
 756                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 757                 return false;
 758         }
 759
 760         return true;
 761 }
 762
 763 static bool g4x_compute_srwm(struct drm_device *dev,
 764                              int plane,
 765                              int latency_ns,
 766                              const struct intel_watermark_params *display,
 767                              const struct intel_watermark_params *cursor,
 768                              int *display_wm, int *cursor_wm)
 769 {
 770         struct drm_crtc *crtc;
 771         const struct drm_display_mode *adjusted_mode;
 772         int hdisplay, htotal, cpp, clock;
 773         unsigned long line_time_us;
 774         int line_count, line_size;
 775         int small, large;
 776         int entries;
 777
 778         if (!latency_ns) {
 779                 *display_wm = *cursor_wm = 0;
 780                 return false;
 781         }
 782
 783         crtc = intel_get_crtc_for_plane(dev, plane);
 784         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 785         clock = adjusted_mode->crtc_clock;
 786         htotal = adjusted_mode->crtc_htotal;
 787         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 788         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 789
 790         line_time_us = max(htotal * 1000 / clock, 1);
 791         line_count = (latency_ns / line_time_us + 1000) / 1000;
 792         line_size = hdisplay * cpp;
 793
 794         /* Use the minimum of the small and large buffer method for primary */
 795         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 796         large = line_count * line_size;
 797
 798         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 799         *display_wm = entries + display->guard_size;
 800
 801         /* calculate the self-refresh watermark for display cursor */
 802         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 803         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 804         *cursor_wm = entries + cursor->guard_size;
 805
 806         return g4x_check_srwm(dev,
 807                               *display_wm, *cursor_wm,
 808                               display, cursor);
 809 }
 810
 811 #define FW_WM_VLV(value, plane) \
 812         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 813
 814 static void vlv_write_wm_values(struct intel_crtc *crtc,
 815                                 const struct vlv_wm_values *wm)
 816 {
 817         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 818         enum pipe pipe = crtc->pipe;
 819
 820         I915_WRITE(VLV_DDL(pipe),
 821                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 822                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 823                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 824                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 825
 826         I915_WRITE(DSPFW1,
 827                    FW_WM(wm->sr.plane, SR) |
 828                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 829                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 830                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 831         I915_WRITE(DSPFW2,
 832                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 833                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 834                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 835         I915_WRITE(DSPFW3,
 836                    FW_WM(wm->sr.cursor, CURSOR_SR));
 837
 838         if (IS_CHERRYVIEW(dev_priv)) {
 839                 I915_WRITE(DSPFW7_CHV,
 840                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 841                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 842                 I915_WRITE(DSPFW8_CHV,
 843                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 844                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 845                 I915_WRITE(DSPFW9_CHV,
 846                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 847                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 848                 I915_WRITE(DSPHOWM,
 849                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 850                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 851                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 852                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 853                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 854                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 855                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 856                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 857                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 858                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 859         } else {
 860                 I915_WRITE(DSPFW7,
 861                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 862                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 863                 I915_WRITE(DSPHOWM,
 864                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 865                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 866                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 867                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 868                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 869                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 870                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 871         }
 872
 873         /* zero (unused) WM1 watermarks */
 874         I915_WRITE(DSPFW4, 0);
 875         I915_WRITE(DSPFW5, 0);
 876         I915_WRITE(DSPFW6, 0);
 877         I915_WRITE(DSPHOWM1, 0);
 878
 879         POSTING_READ(DSPFW1);
 880 }
 881
 882 #undef FW_WM_VLV
 883
 884 enum vlv_wm_level {
 885         VLV_WM_LEVEL_PM2,
 886         VLV_WM_LEVEL_PM5,
 887         VLV_WM_LEVEL_DDR_DVFS,
 888 };
 889
 890 /* latency must be in 0.1us units. */
 891 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 892                                    unsigned int pipe_htotal,
 893                                    unsigned int horiz_pixels,
 894                                    unsigned int cpp,
 895                                    unsigned int latency)
 896 {
 897         unsigned int ret;
 898
 899         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 900         ret = (ret + 1) * horiz_pixels * cpp;
 901         ret = DIV_ROUND_UP(ret, 64);
 902
 903         return ret;
 904 }
 905
 906 static void vlv_setup_wm_latency(struct drm_device *dev)
 907 {
 908         struct drm_i915_private *dev_priv = dev->dev_private;
 909
 910         /* all latencies in usec */
 911         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 912
 913         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 914
 915         if (IS_CHERRYVIEW(dev_priv)) {
 916                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 917                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 918
 919                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 920         }
 921 }
 922
 923 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 924                                      struct intel_crtc *crtc,
 925                                      const struct intel_plane_state *state,
 926                                      int level)
 927 {
 928         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 929         int clock, htotal, cpp, width, wm;
 930
 931         if (dev_priv->wm.pri_latency[level] == 0)
 932                 return USHRT_MAX;
 933
 934         if (!state->visible)
 935                 return 0;
 936
 937         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 938         clock = crtc->config->base.adjusted_mode.crtc_clock;
 939         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 940         width = crtc->config->pipe_src_w;
 941         if (WARN_ON(htotal == 0))
 942                 htotal = 1;
 943
 944         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 945                 /*
 946                  * FIXME the formula gives values that are
 947                  * too big for the cursor FIFO, and hence we
 948                  * would never be able to use cursors. For
 949                  * now just hardcode the watermark.
 950                  */
 951                 wm = 63;
 952         } else {
 953                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 954                                     dev_priv->wm.pri_latency[level] * 10);
 955         }
 956
 957         return min_t(int, wm, USHRT_MAX);
 958 }
 959
 960 static void vlv_compute_fifo(struct intel_crtc *crtc)
 961 {
 962         struct drm_device *dev = crtc->base.dev;
 963         struct vlv_wm_state *wm_state = &crtc->wm_state;
 964         struct intel_plane *plane;
 965         unsigned int total_rate = 0;
 966         const int fifo_size = 512 - 1;
 967         int fifo_extra, fifo_left = fifo_size;
 968
 969         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 970                 struct intel_plane_state *state =
 971                         to_intel_plane_state(plane->base.state);
 972
 973                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 974                         continue;
 975
 976                 if (state->visible) {
 977                         wm_state->num_active_planes++;
 978                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 979                 }
 980         }
 981
 982         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 983                 struct intel_plane_state *state =
 984                         to_intel_plane_state(plane->base.state);
 985                 unsigned int rate;
 986
 987                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 988                         plane->wm.fifo_size = 63;
 989                         continue;
 990                 }
 991
 992                 if (!state->visible) {
 993                         plane->wm.fifo_size = 0;
 994                         continue;
 995                 }
 996
 997                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 998                 plane->wm.fifo_size = fifo_size * rate / total_rate;
 999                 fifo_left -= plane->wm.fifo_size;
1000         }
1001
1002         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1003
1004         /* spread the remainder evenly */
1005         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006                 int plane_extra;
1007
1008                 if (fifo_left == 0)
1009                         break;
1010
1011                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1012                         continue;
1013
1014                 /* give it all to the first plane if none are active */
1015                 if (plane->wm.fifo_size == 0 &&
1016                     wm_state->num_active_planes)
1017                         continue;
1018
1019                 plane_extra = min(fifo_extra, fifo_left);
1020                 plane->wm.fifo_size += plane_extra;
1021                 fifo_left -= plane_extra;
1022         }
1023
1024         WARN_ON(fifo_left != 0);
1025 }
1026
1027 static void vlv_invert_wms(struct intel_crtc *crtc)
1028 {
1029         struct vlv_wm_state *wm_state = &crtc->wm_state;
1030         int level;
1031
1032         for (level = 0; level < wm_state->num_levels; level++) {
1033                 struct drm_device *dev = crtc->base.dev;
1034                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1035                 struct intel_plane *plane;
1036
1037                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1038                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1039
1040                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1041                         switch (plane->base.type) {
1042                                 int sprite;
1043                         case DRM_PLANE_TYPE_CURSOR:
1044                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1045                                         wm_state->wm[level].cursor;
1046                                 break;
1047                         case DRM_PLANE_TYPE_PRIMARY:
1048                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1049                                         wm_state->wm[level].primary;
1050                                 break;
1051                         case DRM_PLANE_TYPE_OVERLAY:
1052                                 sprite = plane->plane;
1053                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1054                                         wm_state->wm[level].sprite[sprite];
1055                                 break;
1056                         }
1057                 }
1058         }
1059 }
1060
1061 static void vlv_compute_wm(struct intel_crtc *crtc)
1062 {
1063         struct drm_device *dev = crtc->base.dev;
1064         struct vlv_wm_state *wm_state = &crtc->wm_state;
1065         struct intel_plane *plane;
1066         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1067         int level;
1068
1069         memset(wm_state, 0, sizeof(*wm_state));
1070
1071         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1072         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1073
1074         wm_state->num_active_planes = 0;
1075
1076         vlv_compute_fifo(crtc);
1077
1078         if (wm_state->num_active_planes != 1)
1079                 wm_state->cxsr = false;
1080
1081         if (wm_state->cxsr) {
1082                 for (level = 0; level < wm_state->num_levels; level++) {
1083                         wm_state->sr[level].plane = sr_fifo_size;
1084                         wm_state->sr[level].cursor = 63;
1085                 }
1086         }
1087
1088         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1089                 struct intel_plane_state *state =
1090                         to_intel_plane_state(plane->base.state);
1091
1092                 if (!state->visible)
1093                         continue;
1094
1095                 /* normal watermarks */
1096                 for (level = 0; level < wm_state->num_levels; level++) {
1097                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1098                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1099
1100                         /* hack */
1101                         if (WARN_ON(level == 0 && wm > max_wm))
1102                                 wm = max_wm;
1103
1104                         if (wm > plane->wm.fifo_size)
1105                                 break;
1106
1107                         switch (plane->base.type) {
1108                                 int sprite;
1109                         case DRM_PLANE_TYPE_CURSOR:
1110                                 wm_state->wm[level].cursor = wm;
1111                                 break;
1112                         case DRM_PLANE_TYPE_PRIMARY:
1113                                 wm_state->wm[level].primary = wm;
1114                                 break;
1115                         case DRM_PLANE_TYPE_OVERLAY:
1116                                 sprite = plane->plane;
1117                                 wm_state->wm[level].sprite[sprite] = wm;
1118                                 break;
1119                         }
1120                 }
1121
1122                 wm_state->num_levels = level;
1123
1124                 if (!wm_state->cxsr)
1125                         continue;
1126
1127                 /* maxfifo watermarks */
1128                 switch (plane->base.type) {
1129                         int sprite, level;
1130                 case DRM_PLANE_TYPE_CURSOR:
1131                         for (level = 0; level < wm_state->num_levels; level++)
1132                                 wm_state->sr[level].cursor =
1133                                         wm_state->wm[level].cursor;
1134                         break;
1135                 case DRM_PLANE_TYPE_PRIMARY:
1136                         for (level = 0; level < wm_state->num_levels; level++)
1137                                 wm_state->sr[level].plane =
1138                                         min(wm_state->sr[level].plane,
1139                                             wm_state->wm[level].primary);
1140                         break;
1141                 case DRM_PLANE_TYPE_OVERLAY:
1142                         sprite = plane->plane;
1143                         for (level = 0; level < wm_state->num_levels; level++)
1144                                 wm_state->sr[level].plane =
1145                                         min(wm_state->sr[level].plane,
1146                                             wm_state->wm[level].sprite[sprite]);
1147                         break;
1148                 }
1149         }
1150
1151         /* clear any (partially) filled invalid levels */
1152         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1153                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1154                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1155         }
1156
1157         vlv_invert_wms(crtc);
1158 }
1159
1160 #define VLV_FIFO(plane, value) \
1161         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1162
1163 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1164 {
1165         struct drm_device *dev = crtc->base.dev;
1166         struct drm_i915_private *dev_priv = to_i915(dev);
1167         struct intel_plane *plane;
1168         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1169
1170         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1172                         WARN_ON(plane->wm.fifo_size != 63);
1173                         continue;
1174                 }
1175
1176                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1177                         sprite0_start = plane->wm.fifo_size;
1178                 else if (plane->plane == 0)
1179                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1180                 else
1181                         fifo_size = sprite1_start + plane->wm.fifo_size;
1182         }
1183
1184         WARN_ON(fifo_size != 512 - 1);
1185
1186         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187                       pipe_name(crtc->pipe), sprite0_start,
1188                       sprite1_start, fifo_size);
1189
1190         switch (crtc->pipe) {
1191                 uint32_t dsparb, dsparb2, dsparb3;
1192         case PIPE_A:
1193                 dsparb = I915_READ(DSPARB);
1194                 dsparb2 = I915_READ(DSPARB2);
1195
1196                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1197                             VLV_FIFO(SPRITEB, 0xff));
1198                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1199                            VLV_FIFO(SPRITEB, sprite1_start));
1200
1201                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1202                              VLV_FIFO(SPRITEB_HI, 0x1));
1203                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1204                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1205
1206                 I915_WRITE(DSPARB, dsparb);
1207                 I915_WRITE(DSPARB2, dsparb2);
1208                 break;
1209         case PIPE_B:
1210                 dsparb = I915_READ(DSPARB);
1211                 dsparb2 = I915_READ(DSPARB2);
1212
1213                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1214                             VLV_FIFO(SPRITED, 0xff));
1215                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1216                            VLV_FIFO(SPRITED, sprite1_start));
1217
1218                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1219                              VLV_FIFO(SPRITED_HI, 0xff));
1220                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1221                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1222
1223                 I915_WRITE(DSPARB, dsparb);
1224                 I915_WRITE(DSPARB2, dsparb2);
1225                 break;
1226         case PIPE_C:
1227                 dsparb3 = I915_READ(DSPARB3);
1228                 dsparb2 = I915_READ(DSPARB2);
1229
1230                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1231                              VLV_FIFO(SPRITEF, 0xff));
1232                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1233                             VLV_FIFO(SPRITEF, sprite1_start));
1234
1235                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1236                              VLV_FIFO(SPRITEF_HI, 0xff));
1237                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1238                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1239
1240                 I915_WRITE(DSPARB3, dsparb3);
1241                 I915_WRITE(DSPARB2, dsparb2);
1242                 break;
1243         default:
1244                 break;
1245         }
1246 }
1247
1248 #undef VLV_FIFO
1249
1250 static void vlv_merge_wm(struct drm_device *dev,
1251                          struct vlv_wm_values *wm)
1252 {
1253         struct intel_crtc *crtc;
1254         int num_active_crtcs = 0;
1255
1256         wm->level = to_i915(dev)->wm.max_level;
1257         wm->cxsr = true;
1258
1259         for_each_intel_crtc(dev, crtc) {
1260                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1261
1262                 if (!crtc->active)
1263                         continue;
1264
1265                 if (!wm_state->cxsr)
1266                         wm->cxsr = false;
1267
1268                 num_active_crtcs++;
1269                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1270         }
1271
1272         if (num_active_crtcs != 1)
1273                 wm->cxsr = false;
1274
1275         if (num_active_crtcs > 1)
1276                 wm->level = VLV_WM_LEVEL_PM2;
1277
1278         for_each_intel_crtc(dev, crtc) {
1279                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1280                 enum pipe pipe = crtc->pipe;
1281
1282                 if (!crtc->active)
1283                         continue;
1284
1285                 wm->pipe[pipe] = wm_state->wm[wm->level];
1286                 if (wm->cxsr)
1287                         wm->sr = wm_state->sr[wm->level];
1288
1289                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1290                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1291                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1292                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1293         }
1294 }
1295
1296 static void vlv_update_wm(struct drm_crtc *crtc)
1297 {
1298         struct drm_device *dev = crtc->dev;
1299         struct drm_i915_private *dev_priv = dev->dev_private;
1300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301         enum pipe pipe = intel_crtc->pipe;
1302         struct vlv_wm_values wm = {};
1303
1304         vlv_compute_wm(intel_crtc);
1305         vlv_merge_wm(dev, &wm);
1306
1307         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1308                 /* FIXME should be part of crtc atomic commit */
1309                 vlv_pipe_set_fifo_size(intel_crtc);
1310                 return;
1311         }
1312
1313         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1314             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1315                 chv_set_memory_dvfs(dev_priv, false);
1316
1317         if (wm.level < VLV_WM_LEVEL_PM5 &&
1318             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1319                 chv_set_memory_pm5(dev_priv, false);
1320
1321         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1322                 intel_set_memory_cxsr(dev_priv, false);
1323
1324         /* FIXME should be part of crtc atomic commit */
1325         vlv_pipe_set_fifo_size(intel_crtc);
1326
1327         vlv_write_wm_values(intel_crtc, &wm);
1328
1329         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1332                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1333                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1334
1335         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1336                 intel_set_memory_cxsr(dev_priv, true);
1337
1338         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1339             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1340                 chv_set_memory_pm5(dev_priv, true);
1341
1342         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1343             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1344                 chv_set_memory_dvfs(dev_priv, true);
1345
1346         dev_priv->wm.vlv = wm;
1347 }
1348
1349 #define single_plane_enabled(mask) is_power_of_2(mask)
1350
1351 static void g4x_update_wm(struct drm_crtc *crtc)
1352 {
1353         struct drm_device *dev = crtc->dev;
1354         static const int sr_latency_ns = 12000;
1355         struct drm_i915_private *dev_priv = dev->dev_private;
1356         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357         int plane_sr, cursor_sr;
1358         unsigned int enabled = 0;
1359         bool cxsr_enabled;
1360
1361         if (g4x_compute_wm0(dev, PIPE_A,
1362                             &g4x_wm_info, pessimal_latency_ns,
1363                             &g4x_cursor_wm_info, pessimal_latency_ns,
1364                             &planea_wm, &cursora_wm))
1365                 enabled |= 1 << PIPE_A;
1366
1367         if (g4x_compute_wm0(dev, PIPE_B,
1368                             &g4x_wm_info, pessimal_latency_ns,
1369                             &g4x_cursor_wm_info, pessimal_latency_ns,
1370                             &planeb_wm, &cursorb_wm))
1371                 enabled |= 1 << PIPE_B;
1372
1373         if (single_plane_enabled(enabled) &&
1374             g4x_compute_srwm(dev, ffs(enabled) - 1,
1375                              sr_latency_ns,
1376                              &g4x_wm_info,
1377                              &g4x_cursor_wm_info,
1378                              &plane_sr, &cursor_sr)) {
1379                 cxsr_enabled = true;
1380         } else {
1381                 cxsr_enabled = false;
1382                 intel_set_memory_cxsr(dev_priv, false);
1383                 plane_sr = cursor_sr = 0;
1384         }
1385
1386         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1388                       planea_wm, cursora_wm,
1389                       planeb_wm, cursorb_wm,
1390                       plane_sr, cursor_sr);
1391
1392         I915_WRITE(DSPFW1,
1393                    FW_WM(plane_sr, SR) |
1394                    FW_WM(cursorb_wm, CURSORB) |
1395                    FW_WM(planeb_wm, PLANEB) |
1396                    FW_WM(planea_wm, PLANEA));
1397         I915_WRITE(DSPFW2,
1398                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1399                    FW_WM(cursora_wm, CURSORA));
1400         /* HPLL off in SR has some issues on G4x... disable it */
1401         I915_WRITE(DSPFW3,
1402                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1403                    FW_WM(cursor_sr, CURSOR_SR));
1404
1405         if (cxsr_enabled)
1406                 intel_set_memory_cxsr(dev_priv, true);
1407 }
1408
1409 static void i965_update_wm(struct drm_crtc *unused_crtc)
1410 {
1411         struct drm_device *dev = unused_crtc->dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         struct drm_crtc *crtc;
1414         int srwm = 1;
1415         int cursor_sr = 16;
1416         bool cxsr_enabled;
1417
1418         /* Calc sr entries for one plane configs */
1419         crtc = single_enabled_crtc(dev);
1420         if (crtc) {
1421                 /* self-refresh has much higher latency */
1422                 static const int sr_latency_ns = 12000;
1423                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1424                 int clock = adjusted_mode->crtc_clock;
1425                 int htotal = adjusted_mode->crtc_htotal;
1426                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1427                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1428                 unsigned long line_time_us;
1429                 int entries;
1430
1431                 line_time_us = max(htotal * 1000 / clock, 1);
1432
1433                 /* Use ns/us then divide to preserve precision */
1434                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1435                         cpp * hdisplay;
1436                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1437                 srwm = I965_FIFO_SIZE - entries;
1438                 if (srwm < 0)
1439                         srwm = 1;
1440                 srwm &= 0x1ff;
1441                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1442                               entries, srwm);
1443
1444                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1445                         cpp * crtc->cursor->state->crtc_w;
1446                 entries = DIV_ROUND_UP(entries,
1447                                           i965_cursor_wm_info.cacheline_size);
1448                 cursor_sr = i965_cursor_wm_info.fifo_size -
1449                         (entries + i965_cursor_wm_info.guard_size);
1450
1451                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1452                         cursor_sr = i965_cursor_wm_info.max_wm;
1453
1454                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455                               "cursor %d\n", srwm, cursor_sr);
1456
1457                 cxsr_enabled = true;
1458         } else {
1459                 cxsr_enabled = false;
1460                 /* Turn off self refresh if both pipes are enabled */
1461                 intel_set_memory_cxsr(dev_priv, false);
1462         }
1463
1464         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1465                       srwm);
1466
1467         /* 965 has limitations... */
1468         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1469                    FW_WM(8, CURSORB) |
1470                    FW_WM(8, PLANEB) |
1471                    FW_WM(8, PLANEA));
1472         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1473                    FW_WM(8, PLANEC_OLD));
1474         /* update cursor SR watermark */
1475         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1476
1477         if (cxsr_enabled)
1478                 intel_set_memory_cxsr(dev_priv, true);
1479 }
1480
1481 #undef FW_WM
1482
1483 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1484 {
1485         struct drm_device *dev = unused_crtc->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         const struct intel_watermark_params *wm_info;
1488         uint32_t fwater_lo;
1489         uint32_t fwater_hi;
1490         int cwm, srwm = 1;
1491         int fifo_size;
1492         int planea_wm, planeb_wm;
1493         struct drm_crtc *crtc, *enabled = NULL;
1494
1495         if (IS_I945GM(dev))
1496                 wm_info = &i945_wm_info;
1497         else if (!IS_GEN2(dev))
1498                 wm_info = &i915_wm_info;
1499         else
1500                 wm_info = &i830_a_wm_info;
1501
1502         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1503         crtc = intel_get_crtc_for_plane(dev, 0);
1504         if (intel_crtc_active(crtc)) {
1505                 const struct drm_display_mode *adjusted_mode;
1506                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1507                 if (IS_GEN2(dev))
1508                         cpp = 4;
1509
1510                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1511                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1512                                                wm_info, fifo_size, cpp,
1513                                                pessimal_latency_ns);
1514                 enabled = crtc;
1515         } else {
1516                 planea_wm = fifo_size - wm_info->guard_size;
1517                 if (planea_wm > (long)wm_info->max_wm)
1518                         planea_wm = wm_info->max_wm;
1519         }
1520
1521         if (IS_GEN2(dev))
1522                 wm_info = &i830_bc_wm_info;
1523
1524         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525         crtc = intel_get_crtc_for_plane(dev, 1);
1526         if (intel_crtc_active(crtc)) {
1527                 const struct drm_display_mode *adjusted_mode;
1528                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1529                 if (IS_GEN2(dev))
1530                         cpp = 4;
1531
1532                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1533                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1534                                                wm_info, fifo_size, cpp,
1535                                                pessimal_latency_ns);
1536                 if (enabled == NULL)
1537                         enabled = crtc;
1538                 else
1539                         enabled = NULL;
1540         } else {
1541                 planeb_wm = fifo_size - wm_info->guard_size;
1542                 if (planeb_wm > (long)wm_info->max_wm)
1543                         planeb_wm = wm_info->max_wm;
1544         }
1545
1546         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
1548         if (IS_I915GM(dev) && enabled) {
1549                 struct drm_i915_gem_object *obj;
1550
1551                 obj = intel_fb_obj(enabled->primary->state->fb);
1552
1553                 /* self-refresh seems busted with untiled */
1554                 if (obj->tiling_mode == I915_TILING_NONE)
1555                         enabled = NULL;
1556         }
1557
1558         /*
1559          * Overlay gets an aggressive default since video jitter is bad.
1560          */
1561         cwm = 2;
1562
1563         /* Play safe and disable self-refresh before adjusting watermarks. */
1564         intel_set_memory_cxsr(dev_priv, false);
1565
1566         /* Calc sr entries for one plane configs */
1567         if (HAS_FW_BLC(dev) && enabled) {
1568                 /* self-refresh has much higher latency */
1569                 static const int sr_latency_ns = 6000;
1570                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1571                 int clock = adjusted_mode->crtc_clock;
1572                 int htotal = adjusted_mode->crtc_htotal;
1573                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1574                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1575                 unsigned long line_time_us;
1576                 int entries;
1577
1578                 line_time_us = max(htotal * 1000 / clock, 1);
1579
1580                 /* Use ns/us then divide to preserve precision */
1581                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1582                         cpp * hdisplay;
1583                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1584                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1585                 srwm = wm_info->fifo_size - entries;
1586                 if (srwm < 0)
1587                         srwm = 1;
1588
1589                 if (IS_I945G(dev) || IS_I945GM(dev))
1590                         I915_WRITE(FW_BLC_SELF,
1591                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1592                 else if (IS_I915GM(dev))
1593                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1594         }
1595
1596         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597                       planea_wm, planeb_wm, cwm, srwm);
1598
1599         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1600         fwater_hi = (cwm & 0x1f);
1601
1602         /* Set request length to 8 cachelines per fetch */
1603         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1604         fwater_hi = fwater_hi | (1 << 8);
1605
1606         I915_WRITE(FW_BLC, fwater_lo);
1607         I915_WRITE(FW_BLC2, fwater_hi);
1608
1609         if (enabled)
1610                 intel_set_memory_cxsr(dev_priv, true);
1611 }
1612
1613 static void i845_update_wm(struct drm_crtc *unused_crtc)
1614 {
1615         struct drm_device *dev = unused_crtc->dev;
1616         struct drm_i915_private *dev_priv = dev->dev_private;
1617         struct drm_crtc *crtc;
1618         const struct drm_display_mode *adjusted_mode;
1619         uint32_t fwater_lo;
1620         int planea_wm;
1621
1622         crtc = single_enabled_crtc(dev);
1623         if (crtc == NULL)
1624                 return;
1625
1626         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1627         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1628                                        &i845_wm_info,
1629                                        dev_priv->display.get_fifo_size(dev, 0),
1630                                        4, pessimal_latency_ns);
1631         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632         fwater_lo |= (3<<8) | planea_wm;
1633
1634         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636         I915_WRITE(FW_BLC, fwater_lo);
1637 }
1638
1639 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1640 {
1641         uint32_t pixel_rate;
1642
1643         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1644
1645         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646          * adjust the pixel_rate here. */
1647
1648         if (pipe_config->pch_pfit.enabled) {
1649                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1650                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1651
1652                 pipe_w = pipe_config->pipe_src_w;
1653                 pipe_h = pipe_config->pipe_src_h;
1654
1655                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1656                 pfit_h = pfit_size & 0xFFFF;
1657                 if (pipe_w < pfit_w)
1658                         pipe_w = pfit_w;
1659                 if (pipe_h < pfit_h)
1660                         pipe_h = pfit_h;
1661
1662                 if (WARN_ON(!pfit_w || !pfit_h))
1663                         return pixel_rate;
1664
1665                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1666                                      pfit_w * pfit_h);
1667         }
1668
1669         return pixel_rate;
1670 }
1671
1672 /* latency must be in 0.1us units. */
1673 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1674 {
1675         uint64_t ret;
1676
1677         if (WARN(latency == 0, "Latency value missing\n"))
1678                 return UINT_MAX;
1679
1680         ret = (uint64_t) pixel_rate * cpp * latency;
1681         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1682
1683         return ret;
1684 }
1685
1686 /* latency must be in 0.1us units. */
1687 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1688                                uint32_t horiz_pixels, uint8_t cpp,
1689                                uint32_t latency)
1690 {
1691         uint32_t ret;
1692
1693         if (WARN(latency == 0, "Latency value missing\n"))
1694                 return UINT_MAX;
1695         if (WARN_ON(!pipe_htotal))
1696                 return UINT_MAX;
1697
1698         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1699         ret = (ret + 1) * horiz_pixels * cpp;
1700         ret = DIV_ROUND_UP(ret, 64) + 2;
1701         return ret;
1702 }
1703
1704 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1705                            uint8_t cpp)
1706 {
1707         /*
1708          * Neither of these should be possible since this function shouldn't be
1709          * called if the CRTC is off or the plane is invisible.  But let's be
1710          * extra paranoid to avoid a potential divide-by-zero if we screw up
1711          * elsewhere in the driver.
1712          */
1713         if (WARN_ON(!cpp))
1714                 return 0;
1715         if (WARN_ON(!horiz_pixels))
1716                 return 0;
1717
1718         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1719 }
1720
1721 struct ilk_wm_maximums {
1722         uint16_t pri;
1723         uint16_t spr;
1724         uint16_t cur;
1725         uint16_t fbc;
1726 };
1727
1728 /*
1729  * For both WM_PIPE and WM_LP.
1730  * mem_value must be in 0.1us units.
1731  */
1732 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1733                                    const struct intel_plane_state *pstate,
1734                                    uint32_t mem_value,
1735                                    bool is_lp)
1736 {
1737         int cpp = pstate->base.fb ?
1738                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1739         uint32_t method1, method2;
1740
1741         if (!cstate->base.active || !pstate->visible)
1742                 return 0;
1743
1744         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1745
1746         if (!is_lp)
1747                 return method1;
1748
1749         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1750                                  cstate->base.adjusted_mode.crtc_htotal,
1751                                  drm_rect_width(&pstate->dst),
1752                                  cpp, mem_value);
1753
1754         return min(method1, method2);
1755 }
1756
1757 /*
1758  * For both WM_PIPE and WM_LP.
1759  * mem_value must be in 0.1us units.
1760  */
1761 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1762                                    const struct intel_plane_state *pstate,
1763                                    uint32_t mem_value)
1764 {
1765         int cpp = pstate->base.fb ?
1766                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1767         uint32_t method1, method2;
1768
1769         if (!cstate->base.active || !pstate->visible)
1770                 return 0;
1771
1772         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1773         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774                                  cstate->base.adjusted_mode.crtc_htotal,
1775                                  drm_rect_width(&pstate->dst),
1776                                  cpp, mem_value);
1777         return min(method1, method2);
1778 }
1779
1780 /*
1781  * For both WM_PIPE and WM_LP.
1782  * mem_value must be in 0.1us units.
1783  */
1784 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1785                                    const struct intel_plane_state *pstate,
1786                                    uint32_t mem_value)
1787 {
1788         /*
1789          * We treat the cursor plane as always-on for the purposes of watermark
1790          * calculation.  Until we have two-stage watermark programming merged,
1791          * this is necessary to avoid flickering.
1792          */
1793         int cpp = 4;
1794         int width = pstate->visible ? pstate->base.crtc_w : 64;
1795
1796         if (!cstate->base.active)
1797                 return 0;
1798
1799         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1800                               cstate->base.adjusted_mode.crtc_htotal,
1801                               width, cpp, mem_value);
1802 }
1803
1804 /* Only for WM_LP. */
1805 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1806                                    const struct intel_plane_state *pstate,
1807                                    uint32_t pri_val)
1808 {
1809         int cpp = pstate->base.fb ?
1810                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1811
1812         if (!cstate->base.active || !pstate->visible)
1813                 return 0;
1814
1815         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1816 }
1817
1818 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819 {
1820         if (INTEL_INFO(dev)->gen >= 8)
1821                 return 3072;
1822         else if (INTEL_INFO(dev)->gen >= 7)
1823                 return 768;
1824         else
1825                 return 512;
1826 }
1827
1828 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1829                                          int level, bool is_sprite)
1830 {
1831         if (INTEL_INFO(dev)->gen >= 8)
1832                 /* BDW primary/sprite plane watermarks */
1833                 return level == 0 ? 255 : 2047;
1834         else if (INTEL_INFO(dev)->gen >= 7)
1835                 /* IVB/HSW primary/sprite plane watermarks */
1836                 return level == 0 ? 127 : 1023;
1837         else if (!is_sprite)
1838                 /* ILK/SNB primary plane watermarks */
1839                 return level == 0 ? 127 : 511;
1840         else
1841                 /* ILK/SNB sprite plane watermarks */
1842                 return level == 0 ? 63 : 255;
1843 }
1844
1845 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1846                                           int level)
1847 {
1848         if (INTEL_INFO(dev)->gen >= 7)
1849                 return level == 0 ? 63 : 255;
1850         else
1851                 return level == 0 ? 31 : 63;
1852 }
1853
1854 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855 {
1856         if (INTEL_INFO(dev)->gen >= 8)
1857                 return 31;
1858         else
1859                 return 15;
1860 }
1861
1862 /* Calculate the maximum primary/sprite plane watermark */
1863 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864                                      int level,
1865                                      const struct intel_wm_config *config,
1866                                      enum intel_ddb_partitioning ddb_partitioning,
1867                                      bool is_sprite)
1868 {
1869         unsigned int fifo_size = ilk_display_fifo_size(dev);
1870
1871         /* if sprites aren't enabled, sprites get nothing */
1872         if (is_sprite && !config->sprites_enabled)
1873                 return 0;
1874
1875         /* HSW allows LP1+ watermarks even with multiple pipes */
1876         if (level == 0 || config->num_pipes_active > 1) {
1877                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1878
1879                 /*
1880                  * For some reason the non self refresh
1881                  * FIFO size is only half of the self
1882                  * refresh FIFO size on ILK/SNB.
1883                  */
1884                 if (INTEL_INFO(dev)->gen <= 6)
1885                         fifo_size /= 2;
1886         }
1887
1888         if (config->sprites_enabled) {
1889                 /* level 0 is always calculated with 1:1 split */
1890                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1891                         if (is_sprite)
1892                                 fifo_size *= 5;
1893                         fifo_size /= 6;
1894                 } else {
1895                         fifo_size /= 2;
1896                 }
1897         }
1898
1899         /* clamp to max that the registers can hold */
1900         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1901 }
1902
1903 /* Calculate the maximum cursor plane watermark */
1904 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1905                                       int level,
1906                                       const struct intel_wm_config *config)
1907 {
1908         /* HSW LP1+ watermarks w/ multiple pipes */
1909         if (level > 0 && config->num_pipes_active > 1)
1910                 return 64;
1911
1912         /* otherwise just report max that registers can hold */
1913         return ilk_cursor_wm_reg_max(dev, level);
1914 }
1915
1916 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1917                                     int level,
1918                                     const struct intel_wm_config *config,
1919                                     enum intel_ddb_partitioning ddb_partitioning,
1920                                     struct ilk_wm_maximums *max)
1921 {
1922         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1923         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1924         max->cur = ilk_cursor_wm_max(dev, level, config);
1925         max->fbc = ilk_fbc_wm_reg_max(dev);
1926 }
1927
1928 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929                                         int level,
1930                                         struct ilk_wm_maximums *max)
1931 {
1932         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1933         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1934         max->cur = ilk_cursor_wm_reg_max(dev, level);
1935         max->fbc = ilk_fbc_wm_reg_max(dev);
1936 }
1937
1938 static bool ilk_validate_wm_level(int level,
1939                                   const struct ilk_wm_maximums *max,
1940                                   struct intel_wm_level *result)
1941 {
1942         bool ret;
1943
1944         /* already determined to be invalid? */
1945         if (!result->enable)
1946                 return false;
1947
1948         result->enable = result->pri_val <= max->pri &&
1949                          result->spr_val <= max->spr &&
1950                          result->cur_val <= max->cur;
1951
1952         ret = result->enable;
1953
1954         /*
1955          * HACK until we can pre-compute everything,
1956          * and thus fail gracefully if LP0 watermarks
1957          * are exceeded...
1958          */
1959         if (level == 0 && !result->enable) {
1960                 if (result->pri_val > max->pri)
1961                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962                                       level, result->pri_val, max->pri);
1963                 if (result->spr_val > max->spr)
1964                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965                                       level, result->spr_val, max->spr);
1966                 if (result->cur_val > max->cur)
1967                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968                                       level, result->cur_val, max->cur);
1969
1970                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1971                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1972                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1973                 result->enable = true;
1974         }
1975
1976         return ret;
1977 }
1978
1979 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1980                                  const struct intel_crtc *intel_crtc,
1981                                  int level,
1982                                  struct intel_crtc_state *cstate,
1983                                  struct intel_plane_state *pristate,
1984                                  struct intel_plane_state *sprstate,
1985                                  struct intel_plane_state *curstate,
1986                                  struct intel_wm_level *result)
1987 {
1988         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992         /* WM1+ latency values stored in 0.5us units */
1993         if (level > 0) {
1994                 pri_latency *= 5;
1995                 spr_latency *= 5;
1996                 cur_latency *= 5;
1997         }
1998
1999         if (pristate) {
2000                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2001                                                      pri_latency, level);
2002                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2003         }
2004
2005         if (sprstate)
2006                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2007
2008         if (curstate)
2009                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2010
2011         result->enable = true;
2012 }
2013
2014 static uint32_t
2015 hsw_compute_linetime_wm(struct drm_device *dev,
2016                         struct intel_crtc_state *cstate)
2017 {
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         const struct drm_display_mode *adjusted_mode =
2020                 &cstate->base.adjusted_mode;
2021         u32 linetime, ips_linetime;
2022
2023         if (!cstate->base.active)
2024                 return 0;
2025         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2026                 return 0;
2027         if (WARN_ON(dev_priv->cdclk_freq == 0))
2028                 return 0;
2029
2030         /* The WM are computed with base on how long it takes to fill a single
2031          * row at the given clock rate, multiplied by 8.
2032          * */
2033         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2034                                      adjusted_mode->crtc_clock);
2035         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2036                                          dev_priv->cdclk_freq);
2037
2038         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2039                PIPE_WM_LINETIME_TIME(linetime);
2040 }
2041
2042 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2043 {
2044         struct drm_i915_private *dev_priv = dev->dev_private;
2045
2046         if (IS_GEN9(dev)) {
2047                 uint32_t val;
2048                 int ret, i;
2049                 int level, max_level = ilk_wm_max_level(dev);
2050
2051                 /* read the first set of memory latencies[0:3] */
2052                 val = 0; /* data0 to be programmed to 0 for first set */
2053                 mutex_lock(&dev_priv->rps.hw_lock);
2054                 ret = sandybridge_pcode_read(dev_priv,
2055                                              GEN9_PCODE_READ_MEM_LATENCY,
2056                                              &val);
2057                 mutex_unlock(&dev_priv->rps.hw_lock);
2058
2059                 if (ret) {
2060                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2061                         return;
2062                 }
2063
2064                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2065                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2066                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2067                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2068                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2069                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2070                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2071
2072                 /* read the second set of memory latencies[4:7] */
2073                 val = 1; /* data0 to be programmed to 1 for second set */
2074                 mutex_lock(&dev_priv->rps.hw_lock);
2075                 ret = sandybridge_pcode_read(dev_priv,
2076                                              GEN9_PCODE_READ_MEM_LATENCY,
2077                                              &val);
2078                 mutex_unlock(&dev_priv->rps.hw_lock);
2079                 if (ret) {
2080                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2081                         return;
2082                 }
2083
2084                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2085                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2086                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2087                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2088                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2089                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2090                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2091
2092                 /*
2093                  * WaWmMemoryReadLatency:skl
2094                  *
2095                  * punit doesn't take into account the read latency so we need
2096                  * to add 2us to the various latency levels we retrieve from
2097                  * the punit.
2098                  *   - W0 is a bit special in that it's the only level that
2099                  *   can't be disabled if we want to have display working, so
2100                  *   we always add 2us there.
2101                  *   - For levels >=1, punit returns 0us latency when they are
2102                  *   disabled, so we respect that and don't add 2us then
2103                  *
2104                  * Additionally, if a level n (n > 1) has a 0us latency, all
2105                  * levels m (m >= n) need to be disabled. We make sure to
2106                  * sanitize the values out of the punit to satisfy this
2107                  * requirement.
2108                  */
2109                 wm[0] += 2;
2110                 for (level = 1; level <= max_level; level++)
2111                         if (wm[level] != 0)
2112                                 wm[level] += 2;
2113                         else {
2114                                 for (i = level + 1; i <= max_level; i++)
2115                                         wm[i] = 0;
2116
2117                                 break;
2118                         }
2119         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2120                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2121
2122                 wm[0] = (sskpd >> 56) & 0xFF;
2123                 if (wm[0] == 0)
2124                         wm[0] = sskpd & 0xF;
2125                 wm[1] = (sskpd >> 4) & 0xFF;
2126                 wm[2] = (sskpd >> 12) & 0xFF;
2127                 wm[3] = (sskpd >> 20) & 0x1FF;
2128                 wm[4] = (sskpd >> 32) & 0x1FF;
2129         } else if (INTEL_INFO(dev)->gen >= 6) {
2130                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2131
2132                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2133                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2134                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2135                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2136         } else if (INTEL_INFO(dev)->gen >= 5) {
2137                 uint32_t mltr = I915_READ(MLTR_ILK);
2138
2139                 /* ILK primary LP0 latency is 700 ns */
2140                 wm[0] = 7;
2141                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2142                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2143         }
2144 }
2145
2146 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2147 {
2148         /* ILK sprite LP0 latency is 1300 ns */
2149         if (INTEL_INFO(dev)->gen == 5)
2150                 wm[0] = 13;
2151 }
2152
2153 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154 {
2155         /* ILK cursor LP0 latency is 1300 ns */
2156         if (INTEL_INFO(dev)->gen == 5)
2157                 wm[0] = 13;
2158
2159         /* WaDoubleCursorLP3Latency:ivb */
2160         if (IS_IVYBRIDGE(dev))
2161                 wm[3] *= 2;
2162 }
2163
2164 int ilk_wm_max_level(const struct drm_device *dev)
2165 {
2166         /* how many WM levels are we expecting */
2167         if (INTEL_INFO(dev)->gen >= 9)
2168                 return 7;
2169         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2170                 return 4;
2171         else if (INTEL_INFO(dev)->gen >= 6)
2172                 return 3;
2173         else
2174                 return 2;
2175 }
2176
2177 static void intel_print_wm_latency(struct drm_device *dev,
2178                                    const char *name,
2179                                    const uint16_t wm[8])
2180 {
2181         int level, max_level = ilk_wm_max_level(dev);
2182
2183         for (level = 0; level <= max_level; level++) {
2184                 unsigned int latency = wm[level];
2185
2186                 if (latency == 0) {
2187                         DRM_ERROR("%s WM%d latency not provided\n",
2188                                   name, level);
2189                         continue;
2190                 }
2191
2192                 /*
2193                  * - latencies are in us on gen9.
2194                  * - before then, WM1+ latency values are in 0.5us units
2195                  */
2196                 if (IS_GEN9(dev))
2197                         latency *= 10;
2198                 else if (level > 0)
2199                         latency *= 5;
2200
2201                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2202                               name, level, wm[level],
2203                               latency / 10, latency % 10);
2204         }
2205 }
2206
2207 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2208                                     uint16_t wm[5], uint16_t min)
2209 {
2210         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2211
2212         if (wm[0] >= min)
2213                 return false;
2214
2215         wm[0] = max(wm[0], min);
2216         for (level = 1; level <= max_level; level++)
2217                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2218
2219         return true;
2220 }
2221
2222 static void snb_wm_latency_quirk(struct drm_device *dev)
2223 {
2224         struct drm_i915_private *dev_priv = dev->dev_private;
2225         bool changed;
2226
2227         /*
2228          * The BIOS provided WM memory latency values are often
2229          * inadequate for high resolution displays. Adjust them.
2230          */
2231         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2232                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2233                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2234
2235         if (!changed)
2236                 return;
2237
2238         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2239         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2240         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2241         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2242 }
2243
2244 static void ilk_setup_wm_latency(struct drm_device *dev)
2245 {
2246         struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2249
2250         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2251                sizeof(dev_priv->wm.pri_latency));
2252         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2253                sizeof(dev_priv->wm.pri_latency));
2254
2255         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2256         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2257
2258         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2259         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2260         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2261
2262         if (IS_GEN6(dev))
2263                 snb_wm_latency_quirk(dev);
2264 }
2265
2266 static void skl_setup_wm_latency(struct drm_device *dev)
2267 {
2268         struct drm_i915_private *dev_priv = dev->dev_private;
2269
2270         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2271         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2272 }
2273
2274 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2275                                  struct intel_pipe_wm *pipe_wm)
2276 {
2277         /* LP0 watermark maximums depend on this pipe alone */
2278         const struct intel_wm_config config = {
2279                 .num_pipes_active = 1,
2280                 .sprites_enabled = pipe_wm->sprites_enabled,
2281                 .sprites_scaled = pipe_wm->sprites_scaled,
2282         };
2283         struct ilk_wm_maximums max;
2284
2285         /* LP0 watermarks always use 1/2 DDB partitioning */
2286         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2287
2288         /* At least LP0 must be valid */
2289         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2290                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2291                 return false;
2292         }
2293
2294         return true;
2295 }
2296
2297 /* Compute new watermarks for the pipe */
2298 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2299 {
2300         struct drm_atomic_state *state = cstate->base.state;
2301         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2302         struct intel_pipe_wm *pipe_wm;
2303         struct drm_device *dev = state->dev;
2304         const struct drm_i915_private *dev_priv = dev->dev_private;
2305         struct intel_plane *intel_plane;
2306         struct intel_plane_state *pristate = NULL;
2307         struct intel_plane_state *sprstate = NULL;
2308         struct intel_plane_state *curstate = NULL;
2309         int level, max_level = ilk_wm_max_level(dev), usable_level;
2310         struct ilk_wm_maximums max;
2311
2312         pipe_wm = &cstate->wm.optimal.ilk;
2313
2314         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2315                 struct intel_plane_state *ps;
2316
2317                 ps = intel_atomic_get_existing_plane_state(state,
2318                                                            intel_plane);
2319                 if (!ps)
2320                         continue;
2321
2322                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2323                         pristate = ps;
2324                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2325                         sprstate = ps;
2326                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2327                         curstate = ps;
2328         }
2329
2330         pipe_wm->pipe_enabled = cstate->base.active;
2331         if (sprstate) {
2332                 pipe_wm->sprites_enabled = sprstate->visible;
2333                 pipe_wm->sprites_scaled = sprstate->visible &&
2334                         (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2335                          drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2336         }
2337
2338         usable_level = max_level;
2339
2340         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2341         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2342                 usable_level = 1;
2343
2344         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2345         if (pipe_wm->sprites_scaled)
2346                 usable_level = 0;
2347
2348         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2349                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2350
2351         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2352         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2353
2354         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2355                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
2356
2357         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2358                 return -EINVAL;
2359
2360         ilk_compute_wm_reg_maximums(dev, 1, &max);
2361
2362         for (level = 1; level <= max_level; level++) {
2363                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2364
2365                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2366                                      pristate, sprstate, curstate, wm);
2367
2368                 /*
2369                  * Disable any watermark level that exceeds the
2370                  * register maximums since such watermarks are
2371                  * always invalid.
2372                  */
2373                 if (level > usable_level)
2374                         continue;
2375
2376                 if (ilk_validate_wm_level(level, &max, wm))
2377                         pipe_wm->wm[level] = *wm;
2378                 else
2379                         usable_level = level;
2380         }
2381
2382         return 0;
2383 }
2384
2385 /*
2386  * Build a set of 'intermediate' watermark values that satisfy both the old
2387  * state and the new state.  These can be programmed to the hardware
2388  * immediately.
2389  */
2390 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2391                                        struct intel_crtc *intel_crtc,
2392                                        struct intel_crtc_state *newstate)
2393 {
2394         struct intel_pipe_wm *a = &newstate->wm.intermediate;
2395         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2396         int level, max_level = ilk_wm_max_level(dev);
2397
2398         /*
2399          * Start with the final, target watermarks, then combine with the
2400          * currently active watermarks to get values that are safe both before
2401          * and after the vblank.
2402          */
2403         *a = newstate->wm.optimal.ilk;
2404         a->pipe_enabled |= b->pipe_enabled;
2405         a->sprites_enabled |= b->sprites_enabled;
2406         a->sprites_scaled |= b->sprites_scaled;
2407
2408         for (level = 0; level <= max_level; level++) {
2409                 struct intel_wm_level *a_wm = &a->wm[level];
2410                 const struct intel_wm_level *b_wm = &b->wm[level];
2411
2412                 a_wm->enable &= b_wm->enable;
2413                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2414                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2415                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2416                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2417         }
2418
2419         /*
2420          * We need to make sure that these merged watermark values are
2421          * actually a valid configuration themselves.  If they're not,
2422          * there's no safe way to transition from the old state to
2423          * the new state, so we need to fail the atomic transaction.
2424          */
2425         if (!ilk_validate_pipe_wm(dev, a))
2426                 return -EINVAL;
2427
2428         /*
2429          * If our intermediate WM are identical to the final WM, then we can
2430          * omit the post-vblank programming; only update if it's different.
2431          */
2432         if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
2433                 newstate->wm.need_postvbl_update = false;
2434
2435         return 0;
2436 }
2437
2438 /*
2439  * Merge the watermarks from all active pipes for a specific level.
2440  */
2441 static void ilk_merge_wm_level(struct drm_device *dev,
2442                                int level,
2443                                struct intel_wm_level *ret_wm)
2444 {
2445         const struct intel_crtc *intel_crtc;
2446
2447         ret_wm->enable = true;
2448
2449         for_each_intel_crtc(dev, intel_crtc) {
2450                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2451                 const struct intel_wm_level *wm = &active->wm[level];
2452
2453                 if (!active->pipe_enabled)
2454                         continue;
2455
2456                 /*
2457                  * The watermark values may have been used in the past,
2458                  * so we must maintain them in the registers for some
2459                  * time even if the level is now disabled.
2460                  */
2461                 if (!wm->enable)
2462                         ret_wm->enable = false;
2463
2464                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2465                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2466                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2467                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2468         }
2469 }
2470
2471 /*
2472  * Merge all low power watermarks for all active pipes.
2473  */
2474 static void ilk_wm_merge(struct drm_device *dev,
2475                          const struct intel_wm_config *config,
2476                          const struct ilk_wm_maximums *max,
2477                          struct intel_pipe_wm *merged)
2478 {
2479         struct drm_i915_private *dev_priv = dev->dev_private;
2480         int level, max_level = ilk_wm_max_level(dev);
2481         int last_enabled_level = max_level;
2482
2483         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2484         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2485             config->num_pipes_active > 1)
2486                 last_enabled_level = 0;
2487
2488         /* ILK: FBC WM must be disabled always */
2489         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2490
2491         /* merge each WM1+ level */
2492         for (level = 1; level <= max_level; level++) {
2493                 struct intel_wm_level *wm = &merged->wm[level];
2494
2495                 ilk_merge_wm_level(dev, level, wm);
2496
2497                 if (level > last_enabled_level)
2498                         wm->enable = false;
2499                 else if (!ilk_validate_wm_level(level, max, wm))
2500                         /* make sure all following levels get disabled */
2501                         last_enabled_level = level - 1;
2502
2503                 /*
2504                  * The spec says it is preferred to disable
2505                  * FBC WMs instead of disabling a WM level.
2506                  */
2507                 if (wm->fbc_val > max->fbc) {
2508                         if (wm->enable)
2509                                 merged->fbc_wm_enabled = false;
2510                         wm->fbc_val = 0;
2511                 }
2512         }
2513
2514         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2515         /*
2516          * FIXME this is racy. FBC might get enabled later.
2517          * What we should check here is whether FBC can be
2518          * enabled sometime later.
2519          */
2520         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2521             intel_fbc_is_active(dev_priv)) {
2522                 for (level = 2; level <= max_level; level++) {
2523                         struct intel_wm_level *wm = &merged->wm[level];
2524
2525                         wm->enable = false;
2526                 }
2527         }
2528 }
2529
2530 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2531 {
2532         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2533         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2534 }
2535
2536 /* The value we need to program into the WM_LPx latency field */
2537 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2538 {
2539         struct drm_i915_private *dev_priv = dev->dev_private;
2540
2541         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2542                 return 2 * level;
2543         else
2544                 return dev_priv->wm.pri_latency[level];
2545 }
2546
2547 static void ilk_compute_wm_results(struct drm_device *dev,
2548                                    const struct intel_pipe_wm *merged,
2549                                    enum intel_ddb_partitioning partitioning,
2550                                    struct ilk_wm_values *results)
2551 {
2552         struct intel_crtc *intel_crtc;
2553         int level, wm_lp;
2554
2555         results->enable_fbc_wm = merged->fbc_wm_enabled;
2556         results->partitioning = partitioning;
2557
2558         /* LP1+ register values */
2559         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2560                 const struct intel_wm_level *r;
2561
2562                 level = ilk_wm_lp_to_level(wm_lp, merged);
2563
2564                 r = &merged->wm[level];
2565
2566                 /*
2567                  * Maintain the watermark values even if the level is
2568                  * disabled. Doing otherwise could cause underruns.
2569                  */
2570                 results->wm_lp[wm_lp - 1] =
2571                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2572                         (r->pri_val << WM1_LP_SR_SHIFT) |
2573                         r->cur_val;
2574
2575                 if (r->enable)
2576                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2577
2578                 if (INTEL_INFO(dev)->gen >= 8)
2579                         results->wm_lp[wm_lp - 1] |=
2580                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2581                 else
2582                         results->wm_lp[wm_lp - 1] |=
2583                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2584
2585                 /*
2586                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2587                  * level is disabled. Doing otherwise could cause underruns.
2588                  */
2589                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2590                         WARN_ON(wm_lp != 1);
2591                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2592                 } else
2593                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2594         }
2595
2596         /* LP0 register values */
2597         for_each_intel_crtc(dev, intel_crtc) {
2598                 enum pipe pipe = intel_crtc->pipe;
2599                 const struct intel_wm_level *r =
2600                         &intel_crtc->wm.active.ilk.wm[0];
2601
2602                 if (WARN_ON(!r->enable))
2603                         continue;
2604
2605                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2606
2607                 results->wm_pipe[pipe] =
2608                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2609                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2610                         r->cur_val;
2611         }
2612 }
2613
2614 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2615  * case both are at the same level. Prefer r1 in case they're the same. */
2616 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2617                                                   struct intel_pipe_wm *r1,
2618                                                   struct intel_pipe_wm *r2)
2619 {
2620         int level, max_level = ilk_wm_max_level(dev);
2621         int level1 = 0, level2 = 0;
2622
2623         for (level = 1; level <= max_level; level++) {
2624                 if (r1->wm[level].enable)
2625                         level1 = level;
2626                 if (r2->wm[level].enable)
2627                         level2 = level;
2628         }
2629
2630         if (level1 == level2) {
2631                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2632                         return r2;
2633                 else
2634                         return r1;
2635         } else if (level1 > level2) {
2636                 return r1;
2637         } else {
2638                 return r2;
2639         }
2640 }
2641
2642 /* dirty bits used to track which watermarks need changes */
2643 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2644 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2645 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2646 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2647 #define WM_DIRTY_FBC (1 << 24)
2648 #define WM_DIRTY_DDB (1 << 25)
2649
2650 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2651                                          const struct ilk_wm_values *old,
2652                                          const struct ilk_wm_values *new)
2653 {
2654         unsigned int dirty = 0;
2655         enum pipe pipe;
2656         int wm_lp;
2657
2658         for_each_pipe(dev_priv, pipe) {
2659                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2660                         dirty |= WM_DIRTY_LINETIME(pipe);
2661                         /* Must disable LP1+ watermarks too */
2662                         dirty |= WM_DIRTY_LP_ALL;
2663                 }
2664
2665                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2666                         dirty |= WM_DIRTY_PIPE(pipe);
2667                         /* Must disable LP1+ watermarks too */
2668                         dirty |= WM_DIRTY_LP_ALL;
2669                 }
2670         }
2671
2672         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2673                 dirty |= WM_DIRTY_FBC;
2674                 /* Must disable LP1+ watermarks too */
2675                 dirty |= WM_DIRTY_LP_ALL;
2676         }
2677
2678         if (old->partitioning != new->partitioning) {
2679                 dirty |= WM_DIRTY_DDB;
2680                 /* Must disable LP1+ watermarks too */
2681                 dirty |= WM_DIRTY_LP_ALL;
2682         }
2683
2684         /* LP1+ watermarks already deemed dirty, no need to continue */
2685         if (dirty & WM_DIRTY_LP_ALL)
2686                 return dirty;
2687
2688         /* Find the lowest numbered LP1+ watermark in need of an update... */
2689         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2690                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2691                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2692                         break;
2693         }
2694
2695         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2696         for (; wm_lp <= 3; wm_lp++)
2697                 dirty |= WM_DIRTY_LP(wm_lp);
2698
2699         return dirty;
2700 }
2701
2702 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2703                                unsigned int dirty)
2704 {
2705         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2706         bool changed = false;
2707
2708         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2709                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2710                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2711                 changed = true;
2712         }
2713         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2714                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2715                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2716                 changed = true;
2717         }
2718         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2719                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2720                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2721                 changed = true;
2722         }
2723
2724         /*
2725          * Don't touch WM1S_LP_EN here.
2726          * Doing so could cause underruns.
2727          */
2728
2729         return changed;
2730 }
2731
2732 /*
2733  * The spec says we shouldn't write when we don't need, because every write
2734  * causes WMs to be re-evaluated, expending some power.
2735  */
2736 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2737                                 struct ilk_wm_values *results)
2738 {
2739         struct drm_device *dev = dev_priv->dev;
2740         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2741         unsigned int dirty;
2742         uint32_t val;
2743
2744         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2745         if (!dirty)
2746                 return;
2747
2748         _ilk_disable_lp_wm(dev_priv, dirty);
2749
2750         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2751                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2752         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2753                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2754         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2755                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2756
2757         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2758                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2759         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2760                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2761         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2762                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2763
2764         if (dirty & WM_DIRTY_DDB) {
2765                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2766                         val = I915_READ(WM_MISC);
2767                         if (results->partitioning == INTEL_DDB_PART_1_2)
2768                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2769                         else
2770                                 val |= WM_MISC_DATA_PARTITION_5_6;
2771                         I915_WRITE(WM_MISC, val);
2772                 } else {
2773                         val = I915_READ(DISP_ARB_CTL2);
2774                         if (results->partitioning == INTEL_DDB_PART_1_2)
2775                                 val &= ~DISP_DATA_PARTITION_5_6;
2776                         else
2777                                 val |= DISP_DATA_PARTITION_5_6;
2778                         I915_WRITE(DISP_ARB_CTL2, val);
2779                 }
2780         }
2781
2782         if (dirty & WM_DIRTY_FBC) {
2783                 val = I915_READ(DISP_ARB_CTL);
2784                 if (results->enable_fbc_wm)
2785                         val &= ~DISP_FBC_WM_DIS;
2786                 else
2787                         val |= DISP_FBC_WM_DIS;
2788                 I915_WRITE(DISP_ARB_CTL, val);
2789         }
2790
2791         if (dirty & WM_DIRTY_LP(1) &&
2792             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2793                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2794
2795         if (INTEL_INFO(dev)->gen >= 7) {
2796                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2797                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2798                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2799                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2800         }
2801
2802         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2803                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2804         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2805                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2806         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2807                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2808
2809         dev_priv->wm.hw = *results;
2810 }
2811
2812 bool ilk_disable_lp_wm(struct drm_device *dev)
2813 {
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815
2816         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2817 }
2818
2819 /*
2820  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2821  * different active planes.
2822  */
2823
2824 #define SKL_DDB_SIZE            896     /* in blocks */
2825 #define BXT_DDB_SIZE            512
2826
2827 /*
2828  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2829  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2830  * other universal planes are in indices 1..n.  Note that this may leave unused
2831  * indices between the top "sprite" plane and the cursor.
2832  */
2833 static int
2834 skl_wm_plane_id(const struct intel_plane *plane)
2835 {
2836         switch (plane->base.type) {
2837         case DRM_PLANE_TYPE_PRIMARY:
2838                 return 0;
2839         case DRM_PLANE_TYPE_CURSOR:
2840                 return PLANE_CURSOR;
2841         case DRM_PLANE_TYPE_OVERLAY:
2842                 return plane->plane + 1;
2843         default:
2844                 MISSING_CASE(plane->base.type);
2845                 return plane->plane;
2846         }
2847 }
2848
2849 static void
2850 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2851                                    const struct intel_crtc_state *cstate,
2852                                    const struct intel_wm_config *config,
2853                                    struct skl_ddb_entry *alloc /* out */)
2854 {
2855         struct drm_crtc *for_crtc = cstate->base.crtc;
2856         struct drm_crtc *crtc;
2857         unsigned int pipe_size, ddb_size;
2858         int nth_active_pipe;
2859
2860         if (!cstate->base.active) {
2861                 alloc->start = 0;
2862                 alloc->end = 0;
2863                 return;
2864         }
2865
2866         if (IS_BROXTON(dev))
2867                 ddb_size = BXT_DDB_SIZE;
2868         else
2869                 ddb_size = SKL_DDB_SIZE;
2870
2871         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2872
2873         nth_active_pipe = 0;
2874         for_each_crtc(dev, crtc) {
2875                 if (!to_intel_crtc(crtc)->active)
2876                         continue;
2877
2878                 if (crtc == for_crtc)
2879                         break;
2880
2881                 nth_active_pipe++;
2882         }
2883
2884         pipe_size = ddb_size / config->num_pipes_active;
2885         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2886         alloc->end = alloc->start + pipe_size;
2887 }
2888
2889 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2890 {
2891         if (config->num_pipes_active == 1)
2892                 return 32;
2893
2894         return 8;
2895 }
2896
2897 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2898 {
2899         entry->start = reg & 0x3ff;
2900         entry->end = (reg >> 16) & 0x3ff;
2901         if (entry->end)
2902                 entry->end += 1;
2903 }
2904
2905 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2906                           struct skl_ddb_allocation *ddb /* out */)
2907 {
2908         enum pipe pipe;
2909         int plane;
2910         u32 val;
2911
2912         memset(ddb, 0, sizeof(*ddb));
2913
2914         for_each_pipe(dev_priv, pipe) {
2915                 enum intel_display_power_domain power_domain;
2916
2917                 power_domain = POWER_DOMAIN_PIPE(pipe);
2918                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2919                         continue;
2920
2921                 for_each_plane(dev_priv, pipe, plane) {
2922                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2923                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2924                                                    val);
2925                 }
2926
2927                 val = I915_READ(CUR_BUF_CFG(pipe));
2928                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2929                                            val);
2930
2931                 intel_display_power_put(dev_priv, power_domain);
2932         }
2933 }
2934
2935 static unsigned int
2936 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2937                              const struct drm_plane_state *pstate,
2938                              int y)
2939 {
2940         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
2941         struct drm_framebuffer *fb = pstate->fb;
2942         uint32_t width = 0, height = 0;
2943
2944         width = drm_rect_width(&intel_pstate->src) >> 16;
2945         height = drm_rect_height(&intel_pstate->src) >> 16;
2946
2947         if (intel_rotation_90_or_270(pstate->rotation))
2948                 swap(width, height);
2949
2950         /* for planar format */
2951         if (fb->pixel_format == DRM_FORMAT_NV12) {
2952                 if (y)  /* y-plane data rate */
2953                         return width * height *
2954                                 drm_format_plane_cpp(fb->pixel_format, 0);
2955                 else    /* uv-plane data rate */
2956                         return (width / 2) * (height / 2) *
2957                                 drm_format_plane_cpp(fb->pixel_format, 1);
2958         }
2959
2960         /* for packed formats */
2961         return width * height * drm_format_plane_cpp(fb->pixel_format, 0);
2962 }
2963
2964 /*
2965  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2966  * a 8192x4096@32bpp framebuffer:
2967  *   3 * 4096 * 8192  * 4 < 2^32
2968  */
2969 static unsigned int
2970 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2971 {
2972         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2973         struct drm_device *dev = intel_crtc->base.dev;
2974         const struct intel_plane *intel_plane;
2975         unsigned int total_data_rate = 0;
2976
2977         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2978                 const struct drm_plane_state *pstate = intel_plane->base.state;
2979
2980                 if (pstate->fb == NULL)
2981                         continue;
2982
2983                 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2984                         continue;
2985
2986                 /* packed/uv */
2987                 total_data_rate += skl_plane_relative_data_rate(cstate,
2988                                                                 pstate,
2989                                                                 0);
2990
2991                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2992                         /* y-plane */
2993                         total_data_rate += skl_plane_relative_data_rate(cstate,
2994                                                                         pstate,
2995                                                                         1);
2996         }
2997
2998         return total_data_rate;
2999 }
3000
3001 static void
3002 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3003                       struct skl_ddb_allocation *ddb /* out */)
3004 {
3005         struct drm_crtc *crtc = cstate->base.crtc;
3006         struct drm_device *dev = crtc->dev;
3007         struct drm_i915_private *dev_priv = to_i915(dev);
3008         struct intel_wm_config *config = &dev_priv->wm.config;
3009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3010         struct intel_plane *intel_plane;
3011         enum pipe pipe = intel_crtc->pipe;
3012         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3013         uint16_t alloc_size, start, cursor_blocks;
3014         uint16_t minimum[I915_MAX_PLANES];
3015         uint16_t y_minimum[I915_MAX_PLANES];
3016         unsigned int total_data_rate;
3017
3018         skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
3019         alloc_size = skl_ddb_entry_size(alloc);
3020         if (alloc_size == 0) {
3021                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3022                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3023                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
3024                 return;
3025         }
3026
3027         cursor_blocks = skl_cursor_allocation(config);
3028         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3029         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3030
3031         alloc_size -= cursor_blocks;
3032         alloc->end -= cursor_blocks;
3033
3034         /* 1. Allocate the mininum required blocks for each active plane */
3035         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3036                 struct drm_plane *plane = &intel_plane->base;
3037                 struct drm_framebuffer *fb = plane->state->fb;
3038                 int id = skl_wm_plane_id(intel_plane);
3039
3040                 if (!to_intel_plane_state(plane->state)->visible)
3041                         continue;
3042
3043                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3044                         continue;
3045
3046                 minimum[id] = 8;
3047                 alloc_size -= minimum[id];
3048                 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3049                 alloc_size -= y_minimum[id];
3050         }
3051
3052         /*
3053          * 2. Distribute the remaining space in proportion to the amount of
3054          * data each plane needs to fetch from memory.
3055          *
3056          * FIXME: we may not allocate every single block here.
3057          */
3058         total_data_rate = skl_get_total_relative_data_rate(cstate);
3059
3060         start = alloc->start;
3061         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3062                 struct drm_plane *plane = &intel_plane->base;
3063                 struct drm_plane_state *pstate = intel_plane->base.state;
3064                 unsigned int data_rate, y_data_rate;
3065                 uint16_t plane_blocks, y_plane_blocks = 0;
3066                 int id = skl_wm_plane_id(intel_plane);
3067
3068                 if (!to_intel_plane_state(pstate)->visible)
3069                         continue;
3070                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3071                         continue;
3072
3073                 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3074
3075                 /*
3076                  * allocation for (packed formats) or (uv-plane part of planar format):
3077                  * promote the expression to 64 bits to avoid overflowing, the
3078                  * result is < available as data_rate / total_data_rate < 1
3079                  */
3080                 plane_blocks = minimum[id];
3081                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3082                                         total_data_rate);
3083
3084                 ddb->plane[pipe][id].start = start;
3085                 ddb->plane[pipe][id].end = start + plane_blocks;
3086
3087                 start += plane_blocks;
3088
3089                 /*
3090                  * allocation for y_plane part of planar format:
3091                  */
3092                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3093                         y_data_rate = skl_plane_relative_data_rate(cstate,
3094                                                                    pstate,
3095                                                                    1);
3096                         y_plane_blocks = y_minimum[id];
3097                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3098                                                 total_data_rate);
3099
3100                         ddb->y_plane[pipe][id].start = start;
3101                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3102
3103                         start += y_plane_blocks;
3104                 }
3105
3106         }
3107
3108 }
3109
3110 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3111 {
3112         /* TODO: Take into account the scalers once we support them */
3113         return config->base.adjusted_mode.crtc_clock;
3114 }
3115
3116 /*
3117  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3118  * for the read latency) and cpp should always be <= 8, so that
3119  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3120  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3121 */
3122 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3123 {
3124         uint32_t wm_intermediate_val, ret;
3125
3126         if (latency == 0)
3127                 return UINT_MAX;
3128
3129         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3130         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3131
3132         return ret;
3133 }
3134
3135 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3136                                uint32_t horiz_pixels, uint8_t cpp,
3137                                uint64_t tiling, uint32_t latency)
3138 {
3139         uint32_t ret;
3140         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3141         uint32_t wm_intermediate_val;
3142
3143         if (latency == 0)
3144                 return UINT_MAX;
3145
3146         plane_bytes_per_line = horiz_pixels * cpp;
3147
3148         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3149             tiling == I915_FORMAT_MOD_Yf_TILED) {
3150                 plane_bytes_per_line *= 4;
3151                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3152                 plane_blocks_per_line /= 4;
3153         } else {
3154                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3155         }
3156
3157         wm_intermediate_val = latency * pixel_rate;
3158         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3159                                 plane_blocks_per_line;
3160
3161         return ret;
3162 }
3163
3164 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3165                                        const struct intel_crtc *intel_crtc)
3166 {
3167         struct drm_device *dev = intel_crtc->base.dev;
3168         struct drm_i915_private *dev_priv = dev->dev_private;
3169         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3170
3171         /*
3172          * If ddb allocation of pipes changed, it may require recalculation of
3173          * watermarks
3174          */
3175         if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3176                 return true;
3177
3178         return false;
3179 }
3180
3181 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3182                                  struct intel_crtc_state *cstate,
3183                                  struct intel_plane *intel_plane,
3184                                  uint16_t ddb_allocation,
3185                                  int level,
3186                                  uint16_t *out_blocks, /* out */
3187                                  uint8_t *out_lines /* out */)
3188 {
3189         struct drm_plane *plane = &intel_plane->base;
3190         struct drm_framebuffer *fb = plane->state->fb;
3191         struct intel_plane_state *intel_pstate =
3192                                         to_intel_plane_state(plane->state);
3193         uint32_t latency = dev_priv->wm.skl_latency[level];
3194         uint32_t method1, method2;
3195         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3196         uint32_t res_blocks, res_lines;
3197         uint32_t selected_result;
3198         uint8_t cpp;
3199         uint32_t width = 0, height = 0;
3200
3201         if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
3202                 return false;
3203
3204         width = drm_rect_width(&intel_pstate->src) >> 16;
3205         height = drm_rect_height(&intel_pstate->src) >> 16;
3206
3207         if (intel_rotation_90_or_270(plane->state->rotation))
3208                 swap(width, height);
3209
3210         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3211         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3212                                  cpp, latency);
3213         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3214                                  cstate->base.adjusted_mode.crtc_htotal,
3215                                  width,
3216                                  cpp,
3217                                  fb->modifier[0],
3218                                  latency);
3219
3220         plane_bytes_per_line = width * cpp;
3221         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3222
3223         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3224             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3225                 uint32_t min_scanlines = 4;
3226                 uint32_t y_tile_minimum;
3227                 if (intel_rotation_90_or_270(plane->state->rotation)) {
3228                         int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3229                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3230                                 drm_format_plane_cpp(fb->pixel_format, 0);
3231
3232                         switch (cpp) {
3233                         case 1:
3234                                 min_scanlines = 16;
3235                                 break;
3236                         case 2:
3237                                 min_scanlines = 8;
3238                                 break;
3239                         case 8:
3240                                 WARN(1, "Unsupported pixel depth for rotation");
3241                         }
3242                 }
3243                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3244                 selected_result = max(method2, y_tile_minimum);
3245         } else {
3246                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3247                         selected_result = min(method1, method2);
3248                 else
3249                         selected_result = method1;
3250         }
3251
3252         res_blocks = selected_result + 1;
3253         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3254
3255         if (level >= 1 && level <= 7) {
3256                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3257                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3258                         res_lines += 4;
3259                 else
3260                         res_blocks++;
3261         }
3262
3263         if (res_blocks >= ddb_allocation || res_lines > 31)
3264                 return false;
3265
3266         *out_blocks = res_blocks;
3267         *out_lines = res_lines;
3268
3269         return true;
3270 }
3271
3272 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3273                                  struct skl_ddb_allocation *ddb,
3274                                  struct intel_crtc_state *cstate,
3275                                  int level,
3276                                  struct skl_wm_level *result)
3277 {
3278         struct drm_device *dev = dev_priv->dev;
3279         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3280         struct intel_plane *intel_plane;
3281         uint16_t ddb_blocks;
3282         enum pipe pipe = intel_crtc->pipe;
3283
3284         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3285                 int i = skl_wm_plane_id(intel_plane);
3286
3287                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3288
3289                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3290                                                 cstate,
3291                                                 intel_plane,
3292                                                 ddb_blocks,
3293                                                 level,
3294                                                 &result->plane_res_b[i],
3295                                                 &result->plane_res_l[i]);
3296         }
3297 }
3298
3299 static uint32_t
3300 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3301 {
3302         if (!cstate->base.active)
3303                 return 0;
3304
3305         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3306                 return 0;
3307
3308         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3309                             skl_pipe_pixel_rate(cstate));
3310 }
3311
3312 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3313                                       struct skl_wm_level *trans_wm /* out */)
3314 {
3315         struct drm_crtc *crtc = cstate->base.crtc;
3316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3317         struct intel_plane *intel_plane;
3318
3319         if (!cstate->base.active)
3320                 return;
3321
3322         /* Until we know more, just disable transition WMs */
3323         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3324                 int i = skl_wm_plane_id(intel_plane);
3325
3326                 trans_wm->plane_en[i] = false;
3327         }
3328 }
3329
3330 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3331                                 struct skl_ddb_allocation *ddb,
3332                                 struct skl_pipe_wm *pipe_wm)
3333 {
3334         struct drm_device *dev = cstate->base.crtc->dev;
3335         const struct drm_i915_private *dev_priv = dev->dev_private;
3336         int level, max_level = ilk_wm_max_level(dev);
3337
3338         for (level = 0; level <= max_level; level++) {
3339                 skl_compute_wm_level(dev_priv, ddb, cstate,
3340                                      level, &pipe_wm->wm[level]);
3341         }
3342         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3343
3344         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3345 }
3346
3347 static void skl_compute_wm_results(struct drm_device *dev,
3348                                    struct skl_pipe_wm *p_wm,
3349                                    struct skl_wm_values *r,
3350                                    struct intel_crtc *intel_crtc)
3351 {
3352         int level, max_level = ilk_wm_max_level(dev);
3353         enum pipe pipe = intel_crtc->pipe;
3354         uint32_t temp;
3355         int i;
3356
3357         for (level = 0; level <= max_level; level++) {
3358                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3359                         temp = 0;
3360
3361                         temp |= p_wm->wm[level].plane_res_l[i] <<
3362                                         PLANE_WM_LINES_SHIFT;
3363                         temp |= p_wm->wm[level].plane_res_b[i];
3364                         if (p_wm->wm[level].plane_en[i])
3365                                 temp |= PLANE_WM_EN;
3366
3367                         r->plane[pipe][i][level] = temp;
3368                 }
3369
3370                 temp = 0;
3371
3372                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3373                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3374
3375                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3376                         temp |= PLANE_WM_EN;
3377
3378                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3379
3380         }
3381
3382         /* transition WMs */
3383         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3384                 temp = 0;
3385                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3386                 temp |= p_wm->trans_wm.plane_res_b[i];
3387                 if (p_wm->trans_wm.plane_en[i])
3388                         temp |= PLANE_WM_EN;
3389
3390                 r->plane_trans[pipe][i] = temp;
3391         }
3392
3393         temp = 0;
3394         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3395         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3396         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3397                 temp |= PLANE_WM_EN;
3398
3399         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3400
3401         r->wm_linetime[pipe] = p_wm->linetime;
3402 }
3403
3404 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3405                                 i915_reg_t reg,
3406                                 const struct skl_ddb_entry *entry)
3407 {
3408         if (entry->end)
3409                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3410         else
3411                 I915_WRITE(reg, 0);
3412 }
3413
3414 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3415                                 const struct skl_wm_values *new)
3416 {
3417         struct drm_device *dev = dev_priv->dev;
3418         struct intel_crtc *crtc;
3419
3420         for_each_intel_crtc(dev, crtc) {
3421                 int i, level, max_level = ilk_wm_max_level(dev);
3422                 enum pipe pipe = crtc->pipe;
3423
3424                 if (!new->dirty[pipe])
3425                         continue;
3426
3427                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3428
3429                 for (level = 0; level <= max_level; level++) {
3430                         for (i = 0; i < intel_num_planes(crtc); i++)
3431                                 I915_WRITE(PLANE_WM(pipe, i, level),
3432                                            new->plane[pipe][i][level]);
3433                         I915_WRITE(CUR_WM(pipe, level),
3434                                    new->plane[pipe][PLANE_CURSOR][level]);
3435                 }
3436                 for (i = 0; i < intel_num_planes(crtc); i++)
3437                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3438                                    new->plane_trans[pipe][i]);
3439                 I915_WRITE(CUR_WM_TRANS(pipe),
3440                            new->plane_trans[pipe][PLANE_CURSOR]);
3441
3442                 for (i = 0; i < intel_num_planes(crtc); i++) {
3443                         skl_ddb_entry_write(dev_priv,
3444                                             PLANE_BUF_CFG(pipe, i),
3445                                             &new->ddb.plane[pipe][i]);
3446                         skl_ddb_entry_write(dev_priv,
3447                                             PLANE_NV12_BUF_CFG(pipe, i),
3448                                             &new->ddb.y_plane[pipe][i]);
3449                 }
3450
3451                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3452                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3453         }
3454 }
3455
3456 /*
3457  * When setting up a new DDB allocation arrangement, we need to correctly
3458  * sequence the times at which the new allocations for the pipes are taken into
3459  * account or we'll have pipes fetching from space previously allocated to
3460  * another pipe.
3461  *
3462  * Roughly the sequence looks like:
3463  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3464  *     overlapping with a previous light-up pipe (another way to put it is:
3465  *     pipes with their new allocation strickly included into their old ones).
3466  *  2. re-allocate the other pipes that get their allocation reduced
3467  *  3. allocate the pipes having their allocation increased
3468  *
3469  * Steps 1. and 2. are here to take care of the following case:
3470  * - Initially DDB looks like this:
3471  *     |   B    |   C    |
3472  * - enable pipe A.
3473  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3474  *   allocation
3475  *     |  A  |  B  |  C  |
3476  *
3477  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3478  */
3479
3480 static void
3481 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3482 {
3483         int plane;
3484
3485         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3486
3487         for_each_plane(dev_priv, pipe, plane) {
3488                 I915_WRITE(PLANE_SURF(pipe, plane),
3489                            I915_READ(PLANE_SURF(pipe, plane)));
3490         }
3491         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3492 }
3493
3494 static bool
3495 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3496                             const struct skl_ddb_allocation *new,
3497                             enum pipe pipe)
3498 {
3499         uint16_t old_size, new_size;
3500
3501         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3502         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3503
3504         return old_size != new_size &&
3505                new->pipe[pipe].start >= old->pipe[pipe].start &&
3506                new->pipe[pipe].end <= old->pipe[pipe].end;
3507 }
3508
3509 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3510                                 struct skl_wm_values *new_values)
3511 {
3512         struct drm_device *dev = dev_priv->dev;
3513         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3514         bool reallocated[I915_MAX_PIPES] = {};
3515         struct intel_crtc *crtc;
3516         enum pipe pipe;
3517
3518         new_ddb = &new_values->ddb;
3519         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3520
3521         /*
3522          * First pass: flush the pipes with the new allocation contained into
3523          * the old space.
3524          *
3525          * We'll wait for the vblank on those pipes to ensure we can safely
3526          * re-allocate the freed space without this pipe fetching from it.
3527          */
3528         for_each_intel_crtc(dev, crtc) {
3529                 if (!crtc->active)
3530                         continue;
3531
3532                 pipe = crtc->pipe;
3533
3534                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3535                         continue;
3536
3537                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3538                 intel_wait_for_vblank(dev, pipe);
3539
3540                 reallocated[pipe] = true;
3541         }
3542
3543
3544         /*
3545          * Second pass: flush the pipes that are having their allocation
3546          * reduced, but overlapping with a previous allocation.
3547          *
3548          * Here as well we need to wait for the vblank to make sure the freed
3549          * space is not used anymore.
3550          */
3551         for_each_intel_crtc(dev, crtc) {
3552                 if (!crtc->active)
3553                         continue;
3554
3555                 pipe = crtc->pipe;
3556
3557                 if (reallocated[pipe])
3558                         continue;
3559
3560                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3561                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3562                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3563                         intel_wait_for_vblank(dev, pipe);
3564                         reallocated[pipe] = true;
3565                 }
3566         }
3567
3568         /*
3569          * Third pass: flush the pipes that got more space allocated.
3570          *
3571          * We don't need to actively wait for the update here, next vblank
3572          * will just get more DDB space with the correct WM values.
3573          */
3574         for_each_intel_crtc(dev, crtc) {
3575                 if (!crtc->active)
3576                         continue;
3577
3578                 pipe = crtc->pipe;
3579
3580                 /*
3581                  * At this point, only the pipes more space than before are
3582                  * left to re-allocate.
3583                  */
3584                 if (reallocated[pipe])
3585                         continue;
3586
3587                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3588         }
3589 }
3590
3591 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3592                                struct skl_ddb_allocation *ddb, /* out */
3593                                struct skl_pipe_wm *pipe_wm /* out */)
3594 {
3595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3596         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3597
3598         skl_allocate_pipe_ddb(cstate, ddb);
3599         skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3600
3601         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3602                 return false;
3603
3604         intel_crtc->wm.active.skl = *pipe_wm;
3605
3606         return true;
3607 }
3608
3609 static void skl_update_other_pipe_wm(struct drm_device *dev,
3610                                      struct drm_crtc *crtc,
3611                                      struct skl_wm_values *r)
3612 {
3613         struct intel_crtc *intel_crtc;
3614         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3615
3616         /*
3617          * If the WM update hasn't changed the allocation for this_crtc (the
3618          * crtc we are currently computing the new WM values for), other
3619          * enabled crtcs will keep the same allocation and we don't need to
3620          * recompute anything for them.
3621          */
3622         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3623                 return;
3624
3625         /*
3626          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3627          * other active pipes need new DDB allocation and WM values.
3628          */
3629         for_each_intel_crtc(dev, intel_crtc) {
3630                 struct skl_pipe_wm pipe_wm = {};
3631                 bool wm_changed;
3632
3633                 if (this_crtc->pipe == intel_crtc->pipe)
3634                         continue;
3635
3636                 if (!intel_crtc->active)
3637                         continue;
3638
3639                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3640                                                 &r->ddb, &pipe_wm);
3641
3642                 /*
3643                  * If we end up re-computing the other pipe WM values, it's
3644                  * because it was really needed, so we expect the WM values to
3645                  * be different.
3646                  */
3647                 WARN_ON(!wm_changed);
3648
3649                 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3650                 r->dirty[intel_crtc->pipe] = true;
3651         }
3652 }
3653
3654 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3655 {
3656         watermarks->wm_linetime[pipe] = 0;
3657         memset(watermarks->plane[pipe], 0,
3658                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3659         memset(watermarks->plane_trans[pipe],
3660                0, sizeof(uint32_t) * I915_MAX_PLANES);
3661         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3662
3663         /* Clear ddb entries for pipe */
3664         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3665         memset(&watermarks->ddb.plane[pipe], 0,
3666                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3667         memset(&watermarks->ddb.y_plane[pipe], 0,
3668                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3669         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3670                sizeof(struct skl_ddb_entry));
3671
3672 }
3673
3674 static void skl_update_wm(struct drm_crtc *crtc)
3675 {
3676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677         struct drm_device *dev = crtc->dev;
3678         struct drm_i915_private *dev_priv = dev->dev_private;
3679         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3680         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3681         struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3682
3683
3684         /* Clear all dirty flags */
3685         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3686
3687         skl_clear_wm(results, intel_crtc->pipe);
3688
3689         if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3690                 return;
3691
3692         skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3693         results->dirty[intel_crtc->pipe] = true;
3694
3695         skl_update_other_pipe_wm(dev, crtc, results);
3696         skl_write_wm_values(dev_priv, results);
3697         skl_flush_wm_values(dev_priv, results);
3698
3699         /* store the new configuration */
3700         dev_priv->wm.skl_hw = *results;
3701 }
3702
3703 static void ilk_compute_wm_config(struct drm_device *dev,
3704                                   struct intel_wm_config *config)
3705 {
3706         struct intel_crtc *crtc;
3707
3708         /* Compute the currently _active_ config */
3709         for_each_intel_crtc(dev, crtc) {
3710                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3711
3712                 if (!wm->pipe_enabled)
3713                         continue;
3714
3715                 config->sprites_enabled |= wm->sprites_enabled;
3716                 config->sprites_scaled |= wm->sprites_scaled;
3717                 config->num_pipes_active++;
3718         }
3719 }
3720
3721 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3722 {
3723         struct drm_device *dev = dev_priv->dev;
3724         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3725         struct ilk_wm_maximums max;
3726         struct intel_wm_config config = {};
3727         struct ilk_wm_values results = {};
3728         enum intel_ddb_partitioning partitioning;
3729
3730         ilk_compute_wm_config(dev, &config);
3731
3732         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3733         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3734
3735         /* 5/6 split only in single pipe config on IVB+ */
3736         if (INTEL_INFO(dev)->gen >= 7 &&
3737             config.num_pipes_active == 1 && config.sprites_enabled) {
3738                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3739                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3740
3741                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3742         } else {
3743                 best_lp_wm = &lp_wm_1_2;
3744         }
3745
3746         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3747                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3748
3749         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3750
3751         ilk_write_wm_values(dev_priv, &results);
3752 }
3753
3754 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
3755 {
3756         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3757         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3758
3759         mutex_lock(&dev_priv->wm.wm_mutex);
3760         intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3761         ilk_program_watermarks(dev_priv);
3762         mutex_unlock(&dev_priv->wm.wm_mutex);
3763 }
3764
3765 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3766 {
3767         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3768         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3769
3770         mutex_lock(&dev_priv->wm.wm_mutex);
3771         if (cstate->wm.need_postvbl_update) {
3772                 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3773                 ilk_program_watermarks(dev_priv);
3774         }
3775         mutex_unlock(&dev_priv->wm.wm_mutex);
3776 }
3777
3778 static void skl_pipe_wm_active_state(uint32_t val,
3779                                      struct skl_pipe_wm *active,
3780                                      bool is_transwm,
3781                                      bool is_cursor,
3782                                      int i,
3783                                      int level)
3784 {
3785         bool is_enabled = (val & PLANE_WM_EN) != 0;
3786
3787         if (!is_transwm) {
3788                 if (!is_cursor) {
3789                         active->wm[level].plane_en[i] = is_enabled;
3790                         active->wm[level].plane_res_b[i] =
3791                                         val & PLANE_WM_BLOCKS_MASK;
3792                         active->wm[level].plane_res_l[i] =
3793                                         (val >> PLANE_WM_LINES_SHIFT) &
3794                                                 PLANE_WM_LINES_MASK;
3795                 } else {
3796                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3797                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3798                                         val & PLANE_WM_BLOCKS_MASK;
3799                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3800                                         (val >> PLANE_WM_LINES_SHIFT) &
3801                                                 PLANE_WM_LINES_MASK;
3802                 }
3803         } else {
3804                 if (!is_cursor) {
3805                         active->trans_wm.plane_en[i] = is_enabled;
3806                         active->trans_wm.plane_res_b[i] =
3807                                         val & PLANE_WM_BLOCKS_MASK;
3808                         active->trans_wm.plane_res_l[i] =
3809                                         (val >> PLANE_WM_LINES_SHIFT) &
3810                                                 PLANE_WM_LINES_MASK;
3811                 } else {
3812                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3813                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3814                                         val & PLANE_WM_BLOCKS_MASK;
3815                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3816                                         (val >> PLANE_WM_LINES_SHIFT) &
3817                                                 PLANE_WM_LINES_MASK;
3818                 }
3819         }
3820 }
3821
3822 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3823 {
3824         struct drm_device *dev = crtc->dev;
3825         struct drm_i915_private *dev_priv = dev->dev_private;
3826         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3828         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3829         struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3830         enum pipe pipe = intel_crtc->pipe;
3831         int level, i, max_level;
3832         uint32_t temp;
3833
3834         max_level = ilk_wm_max_level(dev);
3835
3836         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3837
3838         for (level = 0; level <= max_level; level++) {
3839                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3840                         hw->plane[pipe][i][level] =
3841                                         I915_READ(PLANE_WM(pipe, i, level));
3842                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3843         }
3844
3845         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3846                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3847         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3848
3849         if (!intel_crtc->active)
3850                 return;
3851
3852         hw->dirty[pipe] = true;
3853
3854         active->linetime = hw->wm_linetime[pipe];
3855
3856         for (level = 0; level <= max_level; level++) {
3857                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3858                         temp = hw->plane[pipe][i][level];
3859                         skl_pipe_wm_active_state(temp, active, false,
3860                                                 false, i, level);
3861                 }
3862                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3863                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3864         }
3865
3866         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3867                 temp = hw->plane_trans[pipe][i];
3868                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3869         }
3870
3871         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3872         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3873
3874         intel_crtc->wm.active.skl = *active;
3875 }
3876
3877 void skl_wm_get_hw_state(struct drm_device *dev)
3878 {
3879         struct drm_i915_private *dev_priv = dev->dev_private;
3880         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3881         struct drm_crtc *crtc;
3882
3883         skl_ddb_get_hw_state(dev_priv, ddb);
3884         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3885                 skl_pipe_wm_get_hw_state(crtc);
3886 }
3887
3888 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3889 {
3890         struct drm_device *dev = crtc->dev;
3891         struct drm_i915_private *dev_priv = dev->dev_private;
3892         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3894         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3895         struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3896         enum pipe pipe = intel_crtc->pipe;
3897         static const i915_reg_t wm0_pipe_reg[] = {
3898                 [PIPE_A] = WM0_PIPEA_ILK,
3899                 [PIPE_B] = WM0_PIPEB_ILK,
3900                 [PIPE_C] = WM0_PIPEC_IVB,
3901         };
3902
3903         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3904         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3905                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3906
3907         memset(active, 0, sizeof(*active));
3908
3909         active->pipe_enabled = intel_crtc->active;
3910
3911         if (active->pipe_enabled) {
3912                 u32 tmp = hw->wm_pipe[pipe];
3913
3914                 /*
3915                  * For active pipes LP0 watermark is marked as
3916                  * enabled, and LP1+ watermaks as disabled since
3917                  * we can't really reverse compute them in case
3918                  * multiple pipes are active.
3919                  */
3920                 active->wm[0].enable = true;
3921                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3922                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3923                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3924                 active->linetime = hw->wm_linetime[pipe];
3925         } else {
3926                 int level, max_level = ilk_wm_max_level(dev);
3927
3928                 /*
3929                  * For inactive pipes, all watermark levels
3930                  * should be marked as enabled but zeroed,
3931                  * which is what we'd compute them to.
3932                  */
3933                 for (level = 0; level <= max_level; level++)
3934                         active->wm[level].enable = true;
3935         }
3936
3937         intel_crtc->wm.active.ilk = *active;
3938 }
3939
3940 #define _FW_WM(value, plane) \
3941         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3942 #define _FW_WM_VLV(value, plane) \
3943         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3944
3945 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3946                                struct vlv_wm_values *wm)
3947 {
3948         enum pipe pipe;
3949         uint32_t tmp;
3950
3951         for_each_pipe(dev_priv, pipe) {
3952                 tmp = I915_READ(VLV_DDL(pipe));
3953
3954                 wm->ddl[pipe].primary =
3955                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3956                 wm->ddl[pipe].cursor =
3957                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3958                 wm->ddl[pipe].sprite[0] =
3959                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3960                 wm->ddl[pipe].sprite[1] =
3961                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3962         }
3963
3964         tmp = I915_READ(DSPFW1);
3965         wm->sr.plane = _FW_WM(tmp, SR);
3966         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3967         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3968         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3969
3970         tmp = I915_READ(DSPFW2);
3971         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3972         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3973         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3974
3975         tmp = I915_READ(DSPFW3);
3976         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3977
3978         if (IS_CHERRYVIEW(dev_priv)) {
3979                 tmp = I915_READ(DSPFW7_CHV);
3980                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3981                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3982
3983                 tmp = I915_READ(DSPFW8_CHV);
3984                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3985                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3986
3987                 tmp = I915_READ(DSPFW9_CHV);
3988                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3989                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3990
3991                 tmp = I915_READ(DSPHOWM);
3992                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3993                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3994                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3995                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3996                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3997                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3998                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3999                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4000                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4001                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4002         } else {
4003                 tmp = I915_READ(DSPFW7);
4004                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4005                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4006
4007                 tmp = I915_READ(DSPHOWM);
4008                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4009                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4010                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4011                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4012                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4013                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4014                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4015         }
4016 }
4017
4018 #undef _FW_WM
4019 #undef _FW_WM_VLV
4020
4021 void vlv_wm_get_hw_state(struct drm_device *dev)
4022 {
4023         struct drm_i915_private *dev_priv = to_i915(dev);
4024         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4025         struct intel_plane *plane;
4026         enum pipe pipe;
4027         u32 val;
4028
4029         vlv_read_wm_values(dev_priv, wm);
4030
4031         for_each_intel_plane(dev, plane) {
4032                 switch (plane->base.type) {
4033                         int sprite;
4034                 case DRM_PLANE_TYPE_CURSOR:
4035                         plane->wm.fifo_size = 63;
4036                         break;
4037                 case DRM_PLANE_TYPE_PRIMARY:
4038                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4039                         break;
4040                 case DRM_PLANE_TYPE_OVERLAY:
4041                         sprite = plane->plane;
4042                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4043                         break;
4044                 }
4045         }
4046
4047         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4048         wm->level = VLV_WM_LEVEL_PM2;
4049
4050         if (IS_CHERRYVIEW(dev_priv)) {
4051                 mutex_lock(&dev_priv->rps.hw_lock);
4052
4053                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4054                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4055                         wm->level = VLV_WM_LEVEL_PM5;
4056
4057                 /*
4058                  * If DDR DVFS is disabled in the BIOS, Punit
4059                  * will never ack the request. So if that happens
4060                  * assume we don't have to enable/disable DDR DVFS
4061                  * dynamically. To test that just set the REQ_ACK
4062                  * bit to poke the Punit, but don't change the
4063                  * HIGH/LOW bits so that we don't actually change
4064                  * the current state.
4065                  */
4066                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4067                 val |= FORCE_DDR_FREQ_REQ_ACK;
4068                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4069
4070                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4071                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4072                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4073                                       "assuming DDR DVFS is disabled\n");
4074                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4075                 } else {
4076                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4077                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4078                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4079                 }
4080
4081                 mutex_unlock(&dev_priv->rps.hw_lock);
4082         }
4083
4084         for_each_pipe(dev_priv, pipe)
4085                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4086                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4087                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4088
4089         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4090                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4091 }
4092
4093 void ilk_wm_get_hw_state(struct drm_device *dev)
4094 {
4095         struct drm_i915_private *dev_priv = dev->dev_private;
4096         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4097         struct drm_crtc *crtc;
4098
4099         for_each_crtc(dev, crtc)
4100                 ilk_pipe_wm_get_hw_state(crtc);
4101
4102         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4103         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4104         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4105
4106         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4107         if (INTEL_INFO(dev)->gen >= 7) {
4108                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4109                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4110         }
4111
4112         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4113                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4114                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4115         else if (IS_IVYBRIDGE(dev))
4116                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4117                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4118
4119         hw->enable_fbc_wm =
4120                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4121 }
4122
4123 /**
4124  * intel_update_watermarks - update FIFO watermark values based on current modes
4125  *
4126  * Calculate watermark values for the various WM regs based on current mode
4127  * and plane configuration.
4128  *
4129  * There are several cases to deal with here:
4130  *   - normal (i.e. non-self-refresh)
4131  *   - self-refresh (SR) mode
4132  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4133  *   - lines are small relative to FIFO size (buffer can hold more than 2
4134  *     lines), so need to account for TLB latency
4135  *
4136  *   The normal calculation is:
4137  *     watermark = dotclock * bytes per pixel * latency
4138  *   where latency is platform & configuration dependent (we assume pessimal
4139  *   values here).
4140  *
4141  *   The SR calculation is:
4142  *     watermark = (trunc(latency/line time)+1) * surface width *
4143  *       bytes per pixel
4144  *   where
4145  *     line time = htotal / dotclock
4146  *     surface width = hdisplay for normal plane and 64 for cursor
4147  *   and latency is assumed to be high, as above.
4148  *
4149  * The final value programmed to the register should always be rounded up,
4150  * and include an extra 2 entries to account for clock crossings.
4151  *
4152  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4153  * to set the non-SR watermarks to 8.
4154  */
4155 void intel_update_watermarks(struct drm_crtc *crtc)
4156 {
4157         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4158
4159         if (dev_priv->display.update_wm)
4160                 dev_priv->display.update_wm(crtc);
4161 }
4162
4163 /*
4164  * Lock protecting IPS related data structures
4165  */
4166 DEFINE_SPINLOCK(mchdev_lock);
4167
4168 /* Global for IPS driver to get at the current i915 device. Protected by
4169  * mchdev_lock. */
4170 static struct drm_i915_private *i915_mch_dev;
4171
4172 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4173 {
4174         struct drm_i915_private *dev_priv = dev->dev_private;
4175         u16 rgvswctl;
4176
4177         assert_spin_locked(&mchdev_lock);
4178
4179         rgvswctl = I915_READ16(MEMSWCTL);
4180         if (rgvswctl & MEMCTL_CMD_STS) {
4181                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4182                 return false; /* still busy with another command */
4183         }
4184
4185         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4186                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4187         I915_WRITE16(MEMSWCTL, rgvswctl);
4188         POSTING_READ16(MEMSWCTL);
4189
4190         rgvswctl |= MEMCTL_CMD_STS;
4191         I915_WRITE16(MEMSWCTL, rgvswctl);
4192
4193         return true;
4194 }
4195
4196 static void ironlake_enable_drps(struct drm_device *dev)
4197 {
4198         struct drm_i915_private *dev_priv = dev->dev_private;
4199         u32 rgvmodectl;
4200         u8 fmax, fmin, fstart, vstart;
4201
4202         spin_lock_irq(&mchdev_lock);
4203
4204         rgvmodectl = I915_READ(MEMMODECTL);
4205
4206         /* Enable temp reporting */
4207         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4208         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4209
4210         /* 100ms RC evaluation intervals */
4211         I915_WRITE(RCUPEI, 100000);
4212         I915_WRITE(RCDNEI, 100000);
4213
4214         /* Set max/min thresholds to 90ms and 80ms respectively */
4215         I915_WRITE(RCBMAXAVG, 90000);
4216         I915_WRITE(RCBMINAVG, 80000);
4217
4218         I915_WRITE(MEMIHYST, 1);
4219
4220         /* Set up min, max, and cur for interrupt handling */
4221         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4222         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4223         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4224                 MEMMODE_FSTART_SHIFT;
4225
4226         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4227                 PXVFREQ_PX_SHIFT;
4228
4229         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4230         dev_priv->ips.fstart = fstart;
4231
4232         dev_priv->ips.max_delay = fstart;
4233         dev_priv->ips.min_delay = fmin;
4234         dev_priv->ips.cur_delay = fstart;
4235
4236         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4237                          fmax, fmin, fstart);
4238
4239         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4240
4241         /*
4242          * Interrupts will be enabled in ironlake_irq_postinstall
4243          */
4244
4245         I915_WRITE(VIDSTART, vstart);
4246         POSTING_READ(VIDSTART);
4247
4248         rgvmodectl |= MEMMODE_SWMODE_EN;
4249         I915_WRITE(MEMMODECTL, rgvmodectl);
4250
4251         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4252                 DRM_ERROR("stuck trying to change perf mode\n");
4253         mdelay(1);
4254
4255         ironlake_set_drps(dev, fstart);
4256
4257         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4258                 I915_READ(DDREC) + I915_READ(CSIEC);
4259         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4260         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4261         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4262
4263         spin_unlock_irq(&mchdev_lock);
4264 }
4265
4266 static void ironlake_disable_drps(struct drm_device *dev)
4267 {
4268         struct drm_i915_private *dev_priv = dev->dev_private;
4269         u16 rgvswctl;
4270
4271         spin_lock_irq(&mchdev_lock);
4272
4273         rgvswctl = I915_READ16(MEMSWCTL);
4274
4275         /* Ack interrupts, disable EFC interrupt */
4276         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4277         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4278         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4279         I915_WRITE(DEIIR, DE_PCU_EVENT);
4280         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4281
4282         /* Go back to the starting frequency */
4283         ironlake_set_drps(dev, dev_priv->ips.fstart);
4284         mdelay(1);
4285         rgvswctl |= MEMCTL_CMD_STS;
4286         I915_WRITE(MEMSWCTL, rgvswctl);
4287         mdelay(1);
4288
4289         spin_unlock_irq(&mchdev_lock);
4290 }
4291
4292 /* There's a funny hw issue where the hw returns all 0 when reading from
4293  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4294  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4295  * all limits and the gpu stuck at whatever frequency it is at atm).
4296  */
4297 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4298 {
4299         u32 limits;
4300
4301         /* Only set the down limit when we've reached the lowest level to avoid
4302          * getting more interrupts, otherwise leave this clear. This prevents a
4303          * race in the hw when coming out of rc6: There's a tiny window where
4304          * the hw runs at the minimal clock before selecting the desired
4305          * frequency, if the down threshold expires in that window we will not
4306          * receive a down interrupt. */
4307         if (IS_GEN9(dev_priv)) {
4308                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4309                 if (val <= dev_priv->rps.min_freq_softlimit)
4310                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4311         } else {
4312                 limits = dev_priv->rps.max_freq_softlimit << 24;
4313                 if (val <= dev_priv->rps.min_freq_softlimit)
4314                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4315         }
4316
4317         return limits;
4318 }
4319
4320 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4321 {
4322         int new_power;
4323         u32 threshold_up = 0, threshold_down = 0; /* in % */
4324         u32 ei_up = 0, ei_down = 0;
4325
4326         new_power = dev_priv->rps.power;
4327         switch (dev_priv->rps.power) {
4328         case LOW_POWER:
4329                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4330                         new_power = BETWEEN;
4331                 break;
4332
4333         case BETWEEN:
4334                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4335                         new_power = LOW_POWER;
4336                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4337                         new_power = HIGH_POWER;
4338                 break;
4339
4340         case HIGH_POWER:
4341                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4342                         new_power = BETWEEN;
4343                 break;
4344         }
4345         /* Max/min bins are special */
4346         if (val <= dev_priv->rps.min_freq_softlimit)
4347                 new_power = LOW_POWER;
4348         if (val >= dev_priv->rps.max_freq_softlimit)
4349                 new_power = HIGH_POWER;
4350         if (new_power == dev_priv->rps.power)
4351                 return;
4352
4353         /* Note the units here are not exactly 1us, but 1280ns. */
4354         switch (new_power) {
4355         case LOW_POWER:
4356                 /* Upclock if more than 95% busy over 16ms */
4357                 ei_up = 16000;
4358                 threshold_up = 95;
4359
4360                 /* Downclock if less than 85% busy over 32ms */
4361                 ei_down = 32000;
4362                 threshold_down = 85;
4363                 break;
4364
4365         case BETWEEN:
4366                 /* Upclock if more than 90% busy over 13ms */
4367                 ei_up = 13000;
4368                 threshold_up = 90;
4369
4370                 /* Downclock if less than 75% busy over 32ms */
4371                 ei_down = 32000;
4372                 threshold_down = 75;
4373                 break;
4374
4375         case HIGH_POWER:
4376                 /* Upclock if more than 85% busy over 10ms */
4377                 ei_up = 10000;
4378                 threshold_up = 85;
4379
4380                 /* Downclock if less than 60% busy over 32ms */
4381                 ei_down = 32000;
4382                 threshold_down = 60;
4383                 break;
4384         }
4385
4386         I915_WRITE(GEN6_RP_UP_EI,
4387                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4388         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4389                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4390
4391         I915_WRITE(GEN6_RP_DOWN_EI,
4392                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4393         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4394                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4395
4396          I915_WRITE(GEN6_RP_CONTROL,
4397                     GEN6_RP_MEDIA_TURBO |
4398                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4399                     GEN6_RP_MEDIA_IS_GFX |
4400                     GEN6_RP_ENABLE |
4401                     GEN6_RP_UP_BUSY_AVG |
4402                     GEN6_RP_DOWN_IDLE_AVG);
4403
4404         dev_priv->rps.power = new_power;
4405         dev_priv->rps.up_threshold = threshold_up;
4406         dev_priv->rps.down_threshold = threshold_down;
4407         dev_priv->rps.last_adj = 0;
4408 }
4409
4410 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4411 {
4412         u32 mask = 0;
4413
4414         if (val > dev_priv->rps.min_freq_softlimit)
4415                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4416         if (val < dev_priv->rps.max_freq_softlimit)
4417                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4418
4419         mask &= dev_priv->pm_rps_events;
4420
4421         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4422 }
4423
4424 /* gen6_set_rps is called to update the frequency request, but should also be
4425  * called when the range (min_delay and max_delay) is modified so that we can
4426  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4427 static void gen6_set_rps(struct drm_device *dev, u8 val)
4428 {
4429         struct drm_i915_private *dev_priv = dev->dev_private;
4430
4431         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4432         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4433                 return;
4434
4435         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4436         WARN_ON(val > dev_priv->rps.max_freq);
4437         WARN_ON(val < dev_priv->rps.min_freq);
4438
4439         /* min/max delay may still have been modified so be sure to
4440          * write the limits value.
4441          */
4442         if (val != dev_priv->rps.cur_freq) {
4443                 gen6_set_rps_thresholds(dev_priv, val);
4444
4445                 if (IS_GEN9(dev))
4446                         I915_WRITE(GEN6_RPNSWREQ,
4447                                    GEN9_FREQUENCY(val));
4448                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4449                         I915_WRITE(GEN6_RPNSWREQ,
4450                                    HSW_FREQUENCY(val));
4451                 else
4452                         I915_WRITE(GEN6_RPNSWREQ,
4453                                    GEN6_FREQUENCY(val) |
4454                                    GEN6_OFFSET(0) |
4455                                    GEN6_AGGRESSIVE_TURBO);
4456         }
4457
4458         /* Make sure we continue to get interrupts
4459          * until we hit the minimum or maximum frequencies.
4460          */
4461         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4462         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4463
4464         POSTING_READ(GEN6_RPNSWREQ);
4465
4466         dev_priv->rps.cur_freq = val;
4467         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4468 }
4469
4470 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4471 {
4472         struct drm_i915_private *dev_priv = dev->dev_private;
4473
4474         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4475         WARN_ON(val > dev_priv->rps.max_freq);
4476         WARN_ON(val < dev_priv->rps.min_freq);
4477
4478         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4479                       "Odd GPU freq value\n"))
4480                 val &= ~1;
4481
4482         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4483
4484         if (val != dev_priv->rps.cur_freq) {
4485                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4486                 if (!IS_CHERRYVIEW(dev_priv))
4487                         gen6_set_rps_thresholds(dev_priv, val);
4488         }
4489
4490         dev_priv->rps.cur_freq = val;
4491         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4492 }
4493
4494 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4495  *
4496  * * If Gfx is Idle, then
4497  * 1. Forcewake Media well.
4498  * 2. Request idle freq.
4499  * 3. Release Forcewake of Media well.
4500 */
4501 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4502 {
4503         u32 val = dev_priv->rps.idle_freq;
4504
4505         if (dev_priv->rps.cur_freq <= val)
4506                 return;
4507
4508         /* Wake up the media well, as that takes a lot less
4509          * power than the Render well. */
4510         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4511         valleyview_set_rps(dev_priv->dev, val);
4512         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4513 }
4514
4515 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4516 {
4517         mutex_lock(&dev_priv->rps.hw_lock);
4518         if (dev_priv->rps.enabled) {
4519                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4520                         gen6_rps_reset_ei(dev_priv);
4521                 I915_WRITE(GEN6_PMINTRMSK,
4522                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4523         }
4524         mutex_unlock(&dev_priv->rps.hw_lock);
4525 }
4526
4527 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4528 {
4529         struct drm_device *dev = dev_priv->dev;
4530
4531         mutex_lock(&dev_priv->rps.hw_lock);
4532         if (dev_priv->rps.enabled) {
4533                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4534                         vlv_set_rps_idle(dev_priv);
4535                 else
4536                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4537                 dev_priv->rps.last_adj = 0;
4538                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4539         }
4540         mutex_unlock(&dev_priv->rps.hw_lock);
4541
4542         spin_lock(&dev_priv->rps.client_lock);
4543         while (!list_empty(&dev_priv->rps.clients))
4544                 list_del_init(dev_priv->rps.clients.next);
4545         spin_unlock(&dev_priv->rps.client_lock);
4546 }
4547
4548 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4549                     struct intel_rps_client *rps,
4550                     unsigned long submitted)
4551 {
4552         /* This is intentionally racy! We peek at the state here, then
4553          * validate inside the RPS worker.
4554          */
4555         if (!(dev_priv->mm.busy &&
4556               dev_priv->rps.enabled &&
4557               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4558                 return;
4559
4560         /* Force a RPS boost (and don't count it against the client) if
4561          * the GPU is severely congested.
4562          */
4563         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4564                 rps = NULL;
4565
4566         spin_lock(&dev_priv->rps.client_lock);
4567         if (rps == NULL || list_empty(&rps->link)) {
4568                 spin_lock_irq(&dev_priv->irq_lock);
4569                 if (dev_priv->rps.interrupts_enabled) {
4570                         dev_priv->rps.client_boost = true;
4571                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4572                 }
4573                 spin_unlock_irq(&dev_priv->irq_lock);
4574
4575                 if (rps != NULL) {
4576                         list_add(&rps->link, &dev_priv->rps.clients);
4577                         rps->boosts++;
4578                 } else
4579                         dev_priv->rps.boosts++;
4580         }
4581         spin_unlock(&dev_priv->rps.client_lock);
4582 }
4583
4584 void intel_set_rps(struct drm_device *dev, u8 val)
4585 {
4586         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4587                 valleyview_set_rps(dev, val);
4588         else
4589                 gen6_set_rps(dev, val);
4590 }
4591
4592 static void gen9_disable_rc6(struct drm_device *dev)
4593 {
4594         struct drm_i915_private *dev_priv = dev->dev_private;
4595
4596         I915_WRITE(GEN6_RC_CONTROL, 0);
4597         I915_WRITE(GEN9_PG_ENABLE, 0);
4598 }
4599
4600 static void gen9_disable_rps(struct drm_device *dev)
4601 {
4602         struct drm_i915_private *dev_priv = dev->dev_private;
4603
4604         I915_WRITE(GEN6_RP_CONTROL, 0);
4605 }
4606
4607 static void gen6_disable_rps(struct drm_device *dev)
4608 {
4609         struct drm_i915_private *dev_priv = dev->dev_private;
4610
4611         I915_WRITE(GEN6_RC_CONTROL, 0);
4612         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4613         I915_WRITE(GEN6_RP_CONTROL, 0);
4614 }
4615
4616 static void cherryview_disable_rps(struct drm_device *dev)
4617 {
4618         struct drm_i915_private *dev_priv = dev->dev_private;
4619
4620         I915_WRITE(GEN6_RC_CONTROL, 0);
4621 }
4622
4623 static void valleyview_disable_rps(struct drm_device *dev)
4624 {
4625         struct drm_i915_private *dev_priv = dev->dev_private;
4626
4627         /* we're doing forcewake before Disabling RC6,
4628          * This what the BIOS expects when going into suspend */
4629         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4630
4631         I915_WRITE(GEN6_RC_CONTROL, 0);
4632
4633         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4634 }
4635
4636 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4637 {
4638         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4639                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4640                         mode = GEN6_RC_CTL_RC6_ENABLE;
4641                 else
4642                         mode = 0;
4643         }
4644         if (HAS_RC6p(dev))
4645                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4646                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4647                               onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4648                               onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4649
4650         else
4651                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4652                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4653 }
4654
4655 static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4656 {
4657         struct drm_i915_private *dev_priv = to_i915(dev);
4658         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4659         bool enable_rc6 = true;
4660         unsigned long rc6_ctx_base;
4661
4662         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4663                 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4664                 enable_rc6 = false;
4665         }
4666
4667         /*
4668          * The exact context size is not known for BXT, so assume a page size
4669          * for this check.
4670          */
4671         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4672         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4673               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4674                                         ggtt->stolen_reserved_size))) {
4675                 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4676                 enable_rc6 = false;
4677         }
4678
4679         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4680               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4681               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4682               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4683                 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4684                 enable_rc6 = false;
4685         }
4686
4687         if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4688                                             GEN6_RC_CTL_HW_ENABLE)) &&
4689             ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4690              !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4691                 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4692                 enable_rc6 = false;
4693         }
4694
4695         return enable_rc6;
4696 }
4697
4698 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4699 {
4700         /* No RC6 before Ironlake and code is gone for ilk. */
4701         if (INTEL_INFO(dev)->gen < 6)
4702                 return 0;
4703
4704         if (!enable_rc6)
4705                 return 0;
4706
4707         if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4708                 DRM_INFO("RC6 disabled by BIOS\n");
4709                 return 0;
4710         }
4711
4712         /* Respect the kernel parameter if it is set */
4713         if (enable_rc6 >= 0) {
4714                 int mask;
4715
4716                 if (HAS_RC6p(dev))
4717                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4718                                INTEL_RC6pp_ENABLE;
4719                 else
4720                         mask = INTEL_RC6_ENABLE;
4721
4722                 if ((enable_rc6 & mask) != enable_rc6)
4723                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4724                                       enable_rc6 & mask, enable_rc6, mask);
4725
4726                 return enable_rc6 & mask;
4727         }
4728
4729         if (IS_IVYBRIDGE(dev))
4730                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4731
4732         return INTEL_RC6_ENABLE;
4733 }
4734
4735 int intel_enable_rc6(const struct drm_device *dev)
4736 {
4737         return i915.enable_rc6;
4738 }
4739
4740 static void gen6_init_rps_frequencies(struct drm_device *dev)
4741 {
4742         struct drm_i915_private *dev_priv = dev->dev_private;
4743         uint32_t rp_state_cap;
4744         u32 ddcc_status = 0;
4745         int ret;
4746
4747         /* All of these values are in units of 50MHz */
4748         dev_priv->rps.cur_freq          = 0;
4749         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4750         if (IS_BROXTON(dev)) {
4751                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4752                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4753                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4754                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4755         } else {
4756                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4757                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4758                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4759                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4760         }
4761
4762         /* hw_max = RP0 until we check for overclocking */
4763         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4764
4765         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4766         if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4767             IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4768                 ret = sandybridge_pcode_read(dev_priv,
4769                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4770                                         &ddcc_status);
4771                 if (0 == ret)
4772                         dev_priv->rps.efficient_freq =
4773                                 clamp_t(u8,
4774                                         ((ddcc_status >> 8) & 0xff),
4775                                         dev_priv->rps.min_freq,
4776                                         dev_priv->rps.max_freq);
4777         }
4778
4779         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4780                 /* Store the frequency values in 16.66 MHZ units, which is
4781                    the natural hardware unit for SKL */
4782                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4783                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4784                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4785                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4786                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4787         }
4788
4789         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4790
4791         /* Preserve min/max settings in case of re-init */
4792         if (dev_priv->rps.max_freq_softlimit == 0)
4793                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4794
4795         if (dev_priv->rps.min_freq_softlimit == 0) {
4796                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4797                         dev_priv->rps.min_freq_softlimit =
4798                                 max_t(int, dev_priv->rps.efficient_freq,
4799                                       intel_freq_opcode(dev_priv, 450));
4800                 else
4801                         dev_priv->rps.min_freq_softlimit =
4802                                 dev_priv->rps.min_freq;
4803         }
4804 }
4805
4806 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4807 static void gen9_enable_rps(struct drm_device *dev)
4808 {
4809         struct drm_i915_private *dev_priv = dev->dev_private;
4810
4811         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4812
4813         gen6_init_rps_frequencies(dev);
4814
4815         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4816         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4817                 /*
4818                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
4819                  * clear out the Control register just to avoid inconsitency
4820                  * with debugfs interface, which will show  Turbo as enabled
4821                  * only and that is not expected by the User after adding the
4822                  * WaGsvDisableTurbo. Apart from this there is no problem even
4823                  * if the Turbo is left enabled in the Control register, as the
4824                  * Up/Down interrupts would remain masked.
4825                  */
4826                 gen9_disable_rps(dev);
4827                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4828                 return;
4829         }
4830
4831         /* Program defaults and thresholds for RPS*/
4832         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4833                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4834
4835         /* 1 second timeout*/
4836         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4837                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4838
4839         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4840
4841         /* Leaning on the below call to gen6_set_rps to program/setup the
4842          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4843          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4844         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4845         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4846
4847         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4848 }
4849
4850 static void gen9_enable_rc6(struct drm_device *dev)
4851 {
4852         struct drm_i915_private *dev_priv = dev->dev_private;
4853         struct intel_engine_cs *engine;
4854         uint32_t rc6_mask = 0;
4855
4856         /* 1a: Software RC state - RC0 */
4857         I915_WRITE(GEN6_RC_STATE, 0);
4858
4859         /* 1b: Get forcewake during program sequence. Although the driver
4860          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4861         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4862
4863         /* 2a: Disable RC states. */
4864         I915_WRITE(GEN6_RC_CONTROL, 0);
4865
4866         /* 2b: Program RC6 thresholds.*/
4867
4868         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4869         if (IS_SKYLAKE(dev))
4870                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4871         else
4872                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4873         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4874         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4875         for_each_engine(engine, dev_priv)
4876                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
4877
4878         if (HAS_GUC_UCODE(dev))
4879                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4880
4881         I915_WRITE(GEN6_RC_SLEEP, 0);
4882
4883         /* 2c: Program Coarse Power Gating Policies. */
4884         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4885         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4886
4887         /* 3a: Enable RC6 */
4888         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4889                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4890         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4891         /* WaRsUseTimeoutMode */
4892         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4893             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4894                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4895                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4896                            GEN7_RC_CTL_TO_MODE |
4897                            rc6_mask);
4898         } else {
4899                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4900                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4901                            GEN6_RC_CTL_EI_MODE(1) |
4902                            rc6_mask);
4903         }
4904
4905         /*
4906          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4907          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4908          */
4909         if (NEEDS_WaRsDisableCoarsePowerGating(dev))
4910                 I915_WRITE(GEN9_PG_ENABLE, 0);
4911         else
4912                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4913                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4914
4915         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4916
4917 }
4918
4919 static void gen8_enable_rps(struct drm_device *dev)
4920 {
4921         struct drm_i915_private *dev_priv = dev->dev_private;
4922         struct intel_engine_cs *engine;
4923         uint32_t rc6_mask = 0;
4924
4925         /* 1a: Software RC state - RC0 */
4926         I915_WRITE(GEN6_RC_STATE, 0);
4927
4928         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4929          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4930         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4931
4932         /* 2a: Disable RC states. */
4933         I915_WRITE(GEN6_RC_CONTROL, 0);
4934
4935         /* Initialize rps frequencies */
4936         gen6_init_rps_frequencies(dev);
4937
4938         /* 2b: Program RC6 thresholds.*/
4939         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4940         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4941         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4942         for_each_engine(engine, dev_priv)
4943                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
4944         I915_WRITE(GEN6_RC_SLEEP, 0);
4945         if (IS_BROADWELL(dev))
4946                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4947         else
4948                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4949
4950         /* 3: Enable RC6 */
4951         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4952                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4953         intel_print_rc6_info(dev, rc6_mask);
4954         if (IS_BROADWELL(dev))
4955                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4956                                 GEN7_RC_CTL_TO_MODE |
4957                                 rc6_mask);
4958         else
4959                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4960                                 GEN6_RC_CTL_EI_MODE(1) |
4961                                 rc6_mask);
4962
4963         /* 4 Program defaults and thresholds for RPS*/
4964         I915_WRITE(GEN6_RPNSWREQ,
4965                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4966         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4967                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4968         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4969         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4970
4971         /* Docs recommend 900MHz, and 300 MHz respectively */
4972         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4973                    dev_priv->rps.max_freq_softlimit << 24 |
4974                    dev_priv->rps.min_freq_softlimit << 16);
4975
4976         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4977         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4978         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4979         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4980
4981         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4982
4983         /* 5: Enable RPS */
4984         I915_WRITE(GEN6_RP_CONTROL,
4985                    GEN6_RP_MEDIA_TURBO |
4986                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4987                    GEN6_RP_MEDIA_IS_GFX |
4988                    GEN6_RP_ENABLE |
4989                    GEN6_RP_UP_BUSY_AVG |
4990                    GEN6_RP_DOWN_IDLE_AVG);
4991
4992         /* 6: Ring frequency + overclocking (our driver does this later */
4993
4994         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4995         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4996
4997         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4998 }
4999
5000 static void gen6_enable_rps(struct drm_device *dev)
5001 {
5002         struct drm_i915_private *dev_priv = dev->dev_private;
5003         struct intel_engine_cs *engine;
5004         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
5005         u32 gtfifodbg;
5006         int rc6_mode;
5007         int ret;
5008
5009         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5010
5011         /* Here begins a magic sequence of register writes to enable
5012          * auto-downclocking.
5013          *
5014          * Perhaps there might be some value in exposing these to
5015          * userspace...
5016          */
5017         I915_WRITE(GEN6_RC_STATE, 0);
5018
5019         /* Clear the DBG now so we don't confuse earlier errors */
5020         gtfifodbg = I915_READ(GTFIFODBG);
5021         if (gtfifodbg) {
5022                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5023                 I915_WRITE(GTFIFODBG, gtfifodbg);
5024         }
5025
5026         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5027
5028         /* Initialize rps frequencies */
5029         gen6_init_rps_frequencies(dev);
5030
5031         /* disable the counters and set deterministic thresholds */
5032         I915_WRITE(GEN6_RC_CONTROL, 0);
5033
5034         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5035         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5036         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5037         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5038         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5039
5040         for_each_engine(engine, dev_priv)
5041                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5042
5043         I915_WRITE(GEN6_RC_SLEEP, 0);
5044         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5045         if (IS_IVYBRIDGE(dev))
5046                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5047         else
5048                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5049         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5050         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5051
5052         /* Check if we are enabling RC6 */
5053         rc6_mode = intel_enable_rc6(dev_priv->dev);
5054         if (rc6_mode & INTEL_RC6_ENABLE)
5055                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5056
5057         /* We don't use those on Haswell */
5058         if (!IS_HASWELL(dev)) {
5059                 if (rc6_mode & INTEL_RC6p_ENABLE)
5060                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5061
5062                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5063                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5064         }
5065
5066         intel_print_rc6_info(dev, rc6_mask);
5067
5068         I915_WRITE(GEN6_RC_CONTROL,
5069                    rc6_mask |
5070                    GEN6_RC_CTL_EI_MODE(1) |
5071                    GEN6_RC_CTL_HW_ENABLE);
5072
5073         /* Power down if completely idle for over 50ms */
5074         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5075         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5076
5077         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5078         if (ret)
5079                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5080
5081         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5082         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5083                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5084                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5085                                  (pcu_mbox & 0xff) * 50);
5086                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5087         }
5088
5089         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5090         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5091
5092         rc6vids = 0;
5093         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5094         if (IS_GEN6(dev) && ret) {
5095                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5096         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5097                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5098                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5099                 rc6vids &= 0xffff00;
5100                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5101                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5102                 if (ret)
5103                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5104         }
5105
5106         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5107 }
5108
5109 static void __gen6_update_ring_freq(struct drm_device *dev)
5110 {
5111         struct drm_i915_private *dev_priv = dev->dev_private;
5112         int min_freq = 15;
5113         unsigned int gpu_freq;
5114         unsigned int max_ia_freq, min_ring_freq;
5115         unsigned int max_gpu_freq, min_gpu_freq;
5116         int scaling_factor = 180;
5117         struct cpufreq_policy *policy;
5118
5119         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5120
5121         policy = cpufreq_cpu_get(0);
5122         if (policy) {
5123                 max_ia_freq = policy->cpuinfo.max_freq;
5124                 cpufreq_cpu_put(policy);
5125         } else {
5126                 /*
5127                  * Default to measured freq if none found, PCU will ensure we
5128                  * don't go over
5129                  */
5130                 max_ia_freq = tsc_khz;
5131         }
5132
5133         /* Convert from kHz to MHz */
5134         max_ia_freq /= 1000;
5135
5136         min_ring_freq = I915_READ(DCLK) & 0xf;
5137         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5138         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5139
5140         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5141                 /* Convert GT frequency to 50 HZ units */
5142                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5143                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5144         } else {
5145                 min_gpu_freq = dev_priv->rps.min_freq;
5146                 max_gpu_freq = dev_priv->rps.max_freq;
5147         }
5148
5149         /*
5150          * For each potential GPU frequency, load a ring frequency we'd like
5151          * to use for memory access.  We do this by specifying the IA frequency
5152          * the PCU should use as a reference to determine the ring frequency.
5153          */
5154         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5155                 int diff = max_gpu_freq - gpu_freq;
5156                 unsigned int ia_freq = 0, ring_freq = 0;
5157
5158                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5159                         /*
5160                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5161                          * No floor required for ring frequency on SKL.
5162                          */
5163                         ring_freq = gpu_freq;
5164                 } else if (INTEL_INFO(dev)->gen >= 8) {
5165                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5166                         ring_freq = max(min_ring_freq, gpu_freq);
5167                 } else if (IS_HASWELL(dev)) {
5168                         ring_freq = mult_frac(gpu_freq, 5, 4);
5169                         ring_freq = max(min_ring_freq, ring_freq);
5170                         /* leave ia_freq as the default, chosen by cpufreq */
5171                 } else {
5172                         /* On older processors, there is no separate ring
5173                          * clock domain, so in order to boost the bandwidth
5174                          * of the ring, we need to upclock the CPU (ia_freq).
5175                          *
5176                          * For GPU frequencies less than 750MHz,
5177                          * just use the lowest ring freq.
5178                          */
5179                         if (gpu_freq < min_freq)
5180                                 ia_freq = 800;
5181                         else
5182                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5183                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5184                 }
5185
5186                 sandybridge_pcode_write(dev_priv,
5187                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5188                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5189                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5190                                         gpu_freq);
5191         }
5192 }
5193
5194 void gen6_update_ring_freq(struct drm_device *dev)
5195 {
5196         struct drm_i915_private *dev_priv = dev->dev_private;
5197
5198         if (!HAS_CORE_RING_FREQ(dev))
5199                 return;
5200
5201         mutex_lock(&dev_priv->rps.hw_lock);
5202         __gen6_update_ring_freq(dev);
5203         mutex_unlock(&dev_priv->rps.hw_lock);
5204 }
5205
5206 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5207 {
5208         struct drm_device *dev = dev_priv->dev;
5209         u32 val, rp0;
5210
5211         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5212
5213         switch (INTEL_INFO(dev)->eu_total) {
5214         case 8:
5215                 /* (2 * 4) config */
5216                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5217                 break;
5218         case 12:
5219                 /* (2 * 6) config */
5220                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5221                 break;
5222         case 16:
5223                 /* (2 * 8) config */
5224         default:
5225                 /* Setting (2 * 8) Min RP0 for any other combination */
5226                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5227                 break;
5228         }
5229
5230         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5231
5232         return rp0;
5233 }
5234
5235 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5236 {
5237         u32 val, rpe;
5238
5239         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5240         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5241
5242         return rpe;
5243 }
5244
5245 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5246 {
5247         u32 val, rp1;
5248
5249         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5250         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5251
5252         return rp1;
5253 }
5254
5255 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5256 {
5257         u32 val, rp1;
5258
5259         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5260
5261         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5262
5263         return rp1;
5264 }
5265
5266 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5267 {
5268         u32 val, rp0;
5269
5270         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5271
5272         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5273         /* Clamp to max */
5274         rp0 = min_t(u32, rp0, 0xea);
5275
5276         return rp0;
5277 }
5278
5279 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5280 {
5281         u32 val, rpe;
5282
5283         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5284         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5285         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5286         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5287
5288         return rpe;
5289 }
5290
5291 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5292 {
5293         u32 val;
5294
5295         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5296         /*
5297          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5298          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5299          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5300          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5301          * to make sure it matches what Punit accepts.
5302          */
5303         return max_t(u32, val, 0xc0);
5304 }
5305
5306 /* Check that the pctx buffer wasn't move under us. */
5307 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5308 {
5309         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5310
5311         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5312                              dev_priv->vlv_pctx->stolen->start);
5313 }
5314
5315
5316 /* Check that the pcbr address is not empty. */
5317 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5318 {
5319         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5320
5321         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5322 }
5323
5324 static void cherryview_setup_pctx(struct drm_device *dev)
5325 {
5326         struct drm_i915_private *dev_priv = to_i915(dev);
5327         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5328         unsigned long pctx_paddr, paddr;
5329         u32 pcbr;
5330         int pctx_size = 32*1024;
5331
5332         pcbr = I915_READ(VLV_PCBR);
5333         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5334                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5335                 paddr = (dev_priv->mm.stolen_base +
5336                          (ggtt->stolen_size - pctx_size));
5337
5338                 pctx_paddr = (paddr & (~4095));
5339                 I915_WRITE(VLV_PCBR, pctx_paddr);
5340         }
5341
5342         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5343 }
5344
5345 static void valleyview_setup_pctx(struct drm_device *dev)
5346 {
5347         struct drm_i915_private *dev_priv = dev->dev_private;
5348         struct drm_i915_gem_object *pctx;
5349         unsigned long pctx_paddr;
5350         u32 pcbr;
5351         int pctx_size = 24*1024;
5352
5353         mutex_lock(&dev->struct_mutex);
5354
5355         pcbr = I915_READ(VLV_PCBR);
5356         if (pcbr) {
5357                 /* BIOS set it up already, grab the pre-alloc'd space */
5358                 int pcbr_offset;
5359
5360                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5361                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5362                                                                       pcbr_offset,
5363                                                                       I915_GTT_OFFSET_NONE,
5364                                                                       pctx_size);
5365                 goto out;
5366         }
5367
5368         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5369
5370         /*
5371          * From the Gunit register HAS:
5372          * The Gfx driver is expected to program this register and ensure
5373          * proper allocation within Gfx stolen memory.  For example, this
5374          * register should be programmed such than the PCBR range does not
5375          * overlap with other ranges, such as the frame buffer, protected
5376          * memory, or any other relevant ranges.
5377          */
5378         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5379         if (!pctx) {
5380                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5381                 goto out;
5382         }
5383
5384         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5385         I915_WRITE(VLV_PCBR, pctx_paddr);
5386
5387 out:
5388         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5389         dev_priv->vlv_pctx = pctx;
5390         mutex_unlock(&dev->struct_mutex);
5391 }
5392
5393 static void valleyview_cleanup_pctx(struct drm_device *dev)
5394 {
5395         struct drm_i915_private *dev_priv = dev->dev_private;
5396
5397         if (WARN_ON(!dev_priv->vlv_pctx))
5398                 return;
5399
5400         drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5401         dev_priv->vlv_pctx = NULL;
5402 }
5403
5404 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5405 {
5406         dev_priv->rps.gpll_ref_freq =
5407                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5408                                   CCK_GPLL_CLOCK_CONTROL,
5409                                   dev_priv->czclk_freq);
5410
5411         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5412                          dev_priv->rps.gpll_ref_freq);
5413 }
5414
5415 static void valleyview_init_gt_powersave(struct drm_device *dev)
5416 {
5417         struct drm_i915_private *dev_priv = dev->dev_private;
5418         u32 val;
5419
5420         valleyview_setup_pctx(dev);
5421
5422         vlv_init_gpll_ref_freq(dev_priv);
5423
5424         mutex_lock(&dev_priv->rps.hw_lock);
5425
5426         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5427         switch ((val >> 6) & 3) {
5428         case 0:
5429         case 1:
5430                 dev_priv->mem_freq = 800;
5431                 break;
5432         case 2:
5433                 dev_priv->mem_freq = 1066;
5434                 break;
5435         case 3:
5436                 dev_priv->mem_freq = 1333;
5437                 break;
5438         }
5439         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5440
5441         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5442         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5443         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5444                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5445                          dev_priv->rps.max_freq);
5446
5447         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5448         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5449                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5450                          dev_priv->rps.efficient_freq);
5451
5452         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5453         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5454                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5455                          dev_priv->rps.rp1_freq);
5456
5457         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5458         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5459                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5460                          dev_priv->rps.min_freq);
5461
5462         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5463
5464         /* Preserve min/max settings in case of re-init */
5465         if (dev_priv->rps.max_freq_softlimit == 0)
5466                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5467
5468         if (dev_priv->rps.min_freq_softlimit == 0)
5469                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5470
5471         mutex_unlock(&dev_priv->rps.hw_lock);
5472 }
5473
5474 static void cherryview_init_gt_powersave(struct drm_device *dev)
5475 {
5476         struct drm_i915_private *dev_priv = dev->dev_private;
5477         u32 val;
5478
5479         cherryview_setup_pctx(dev);
5480
5481         vlv_init_gpll_ref_freq(dev_priv);
5482
5483         mutex_lock(&dev_priv->rps.hw_lock);
5484
5485         mutex_lock(&dev_priv->sb_lock);
5486         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5487         mutex_unlock(&dev_priv->sb_lock);
5488
5489         switch ((val >> 2) & 0x7) {
5490         case 3:
5491                 dev_priv->mem_freq = 2000;
5492                 break;
5493         default:
5494                 dev_priv->mem_freq = 1600;
5495                 break;
5496         }
5497         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5498
5499         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5500         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5501         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5502                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5503                          dev_priv->rps.max_freq);
5504
5505         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5506         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5507                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5508                          dev_priv->rps.efficient_freq);
5509
5510         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5511         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5512                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5513                          dev_priv->rps.rp1_freq);
5514
5515         /* PUnit validated range is only [RPe, RP0] */
5516         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5517         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5518                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5519                          dev_priv->rps.min_freq);
5520
5521         WARN_ONCE((dev_priv->rps.max_freq |
5522                    dev_priv->rps.efficient_freq |
5523                    dev_priv->rps.rp1_freq |
5524                    dev_priv->rps.min_freq) & 1,
5525                   "Odd GPU freq values\n");
5526
5527         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5528
5529         /* Preserve min/max settings in case of re-init */
5530         if (dev_priv->rps.max_freq_softlimit == 0)
5531                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5532
5533         if (dev_priv->rps.min_freq_softlimit == 0)
5534                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5535
5536         mutex_unlock(&dev_priv->rps.hw_lock);
5537 }
5538
5539 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5540 {
5541         valleyview_cleanup_pctx(dev);
5542 }
5543
5544 static void cherryview_enable_rps(struct drm_device *dev)
5545 {
5546         struct drm_i915_private *dev_priv = dev->dev_private;
5547         struct intel_engine_cs *engine;
5548         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5549
5550         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5551
5552         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5553                                              GT_FIFO_FREE_ENTRIES_CHV);
5554         if (gtfifodbg) {
5555                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5556                                  gtfifodbg);
5557                 I915_WRITE(GTFIFODBG, gtfifodbg);
5558         }
5559
5560         cherryview_check_pctx(dev_priv);
5561
5562         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5563          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5564         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5565
5566         /*  Disable RC states. */
5567         I915_WRITE(GEN6_RC_CONTROL, 0);
5568
5569         /* 2a: Program RC6 thresholds.*/
5570         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5571         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5572         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5573
5574         for_each_engine(engine, dev_priv)
5575                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5576         I915_WRITE(GEN6_RC_SLEEP, 0);
5577
5578         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5579         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5580
5581         /* allows RC6 residency counter to work */
5582         I915_WRITE(VLV_COUNTER_CONTROL,
5583                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5584                                       VLV_MEDIA_RC6_COUNT_EN |
5585                                       VLV_RENDER_RC6_COUNT_EN));
5586
5587         /* For now we assume BIOS is allocating and populating the PCBR  */
5588         pcbr = I915_READ(VLV_PCBR);
5589
5590         /* 3: Enable RC6 */
5591         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5592                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5593                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5594
5595         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5596
5597         /* 4 Program defaults and thresholds for RPS*/
5598         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5599         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5600         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5601         I915_WRITE(GEN6_RP_UP_EI, 66000);
5602         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5603
5604         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5605
5606         /* 5: Enable RPS */
5607         I915_WRITE(GEN6_RP_CONTROL,
5608                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5609                    GEN6_RP_MEDIA_IS_GFX |
5610                    GEN6_RP_ENABLE |
5611                    GEN6_RP_UP_BUSY_AVG |
5612                    GEN6_RP_DOWN_IDLE_AVG);
5613
5614         /* Setting Fixed Bias */
5615         val = VLV_OVERRIDE_EN |
5616                   VLV_SOC_TDP_EN |
5617                   CHV_BIAS_CPU_50_SOC_50;
5618         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5619
5620         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5621
5622         /* RPS code assumes GPLL is used */
5623         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5624
5625         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5626         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5627
5628         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5629         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5630                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5631                          dev_priv->rps.cur_freq);
5632
5633         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5634                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5635                          dev_priv->rps.idle_freq);
5636
5637         valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5638
5639         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5640 }
5641
5642 static void valleyview_enable_rps(struct drm_device *dev)
5643 {
5644         struct drm_i915_private *dev_priv = dev->dev_private;
5645         struct intel_engine_cs *engine;
5646         u32 gtfifodbg, val, rc6_mode = 0;
5647
5648         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5649
5650         valleyview_check_pctx(dev_priv);
5651
5652         gtfifodbg = I915_READ(GTFIFODBG);
5653         if (gtfifodbg) {
5654                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5655                                  gtfifodbg);
5656                 I915_WRITE(GTFIFODBG, gtfifodbg);
5657         }
5658
5659         /* If VLV, Forcewake all wells, else re-direct to regular path */
5660         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5661
5662         /*  Disable RC states. */
5663         I915_WRITE(GEN6_RC_CONTROL, 0);
5664
5665         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5666         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5667         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5668         I915_WRITE(GEN6_RP_UP_EI, 66000);
5669         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5670
5671         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5672
5673         I915_WRITE(GEN6_RP_CONTROL,
5674                    GEN6_RP_MEDIA_TURBO |
5675                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5676                    GEN6_RP_MEDIA_IS_GFX |
5677                    GEN6_RP_ENABLE |
5678                    GEN6_RP_UP_BUSY_AVG |
5679                    GEN6_RP_DOWN_IDLE_CONT);
5680
5681         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5682         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5683         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5684
5685         for_each_engine(engine, dev_priv)
5686                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5687
5688         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5689
5690         /* allows RC6 residency counter to work */
5691         I915_WRITE(VLV_COUNTER_CONTROL,
5692                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5693                                       VLV_RENDER_RC0_COUNT_EN |
5694                                       VLV_MEDIA_RC6_COUNT_EN |
5695                                       VLV_RENDER_RC6_COUNT_EN));
5696
5697         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5698                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5699
5700         intel_print_rc6_info(dev, rc6_mode);
5701
5702         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5703
5704         /* Setting Fixed Bias */
5705         val = VLV_OVERRIDE_EN |
5706                   VLV_SOC_TDP_EN |
5707                   VLV_BIAS_CPU_125_SOC_875;
5708         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5709
5710         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5711
5712         /* RPS code assumes GPLL is used */
5713         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5714
5715         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5716         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5717
5718         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5719         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5720                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5721                          dev_priv->rps.cur_freq);
5722
5723         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5724                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5725                          dev_priv->rps.idle_freq);
5726
5727         valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5728
5729         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5730 }
5731
5732 static unsigned long intel_pxfreq(u32 vidfreq)
5733 {
5734         unsigned long freq;
5735         int div = (vidfreq & 0x3f0000) >> 16;
5736         int post = (vidfreq & 0x3000) >> 12;
5737         int pre = (vidfreq & 0x7);
5738
5739         if (!pre)
5740                 return 0;
5741
5742         freq = ((div * 133333) / ((1<<post) * pre));
5743
5744         return freq;
5745 }
5746
5747 static const struct cparams {
5748         u16 i;
5749         u16 t;
5750         u16 m;
5751         u16 c;
5752 } cparams[] = {
5753         { 1, 1333, 301, 28664 },
5754         { 1, 1066, 294, 24460 },
5755         { 1, 800, 294, 25192 },
5756         { 0, 1333, 276, 27605 },
5757         { 0, 1066, 276, 27605 },
5758         { 0, 800, 231, 23784 },
5759 };
5760
5761 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5762 {
5763         u64 total_count, diff, ret;
5764         u32 count1, count2, count3, m = 0, c = 0;
5765         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5766         int i;
5767
5768         assert_spin_locked(&mchdev_lock);
5769
5770         diff1 = now - dev_priv->ips.last_time1;
5771
5772         /* Prevent division-by-zero if we are asking too fast.
5773          * Also, we don't get interesting results if we are polling
5774          * faster than once in 10ms, so just return the saved value
5775          * in such cases.
5776          */
5777         if (diff1 <= 10)
5778                 return dev_priv->ips.chipset_power;
5779
5780         count1 = I915_READ(DMIEC);
5781         count2 = I915_READ(DDREC);
5782         count3 = I915_READ(CSIEC);
5783
5784         total_count = count1 + count2 + count3;
5785
5786         /* FIXME: handle per-counter overflow */
5787         if (total_count < dev_priv->ips.last_count1) {
5788                 diff = ~0UL - dev_priv->ips.last_count1;
5789                 diff += total_count;
5790         } else {
5791                 diff = total_count - dev_priv->ips.last_count1;
5792         }
5793
5794         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5795                 if (cparams[i].i == dev_priv->ips.c_m &&
5796                     cparams[i].t == dev_priv->ips.r_t) {
5797                         m = cparams[i].m;
5798                         c = cparams[i].c;
5799                         break;
5800                 }
5801         }
5802
5803         diff = div_u64(diff, diff1);
5804         ret = ((m * diff) + c);
5805         ret = div_u64(ret, 10);
5806
5807         dev_priv->ips.last_count1 = total_count;
5808         dev_priv->ips.last_time1 = now;
5809
5810         dev_priv->ips.chipset_power = ret;
5811
5812         return ret;
5813 }
5814
5815 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5816 {
5817         struct drm_device *dev = dev_priv->dev;
5818         unsigned long val;
5819
5820         if (INTEL_INFO(dev)->gen != 5)
5821                 return 0;
5822
5823         spin_lock_irq(&mchdev_lock);
5824
5825         val = __i915_chipset_val(dev_priv);
5826
5827         spin_unlock_irq(&mchdev_lock);
5828
5829         return val;
5830 }
5831
5832 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5833 {
5834         unsigned long m, x, b;
5835         u32 tsfs;
5836
5837         tsfs = I915_READ(TSFS);
5838
5839         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5840         x = I915_READ8(TR1);
5841
5842         b = tsfs & TSFS_INTR_MASK;
5843
5844         return ((m * x) / 127) - b;
5845 }
5846
5847 static int _pxvid_to_vd(u8 pxvid)
5848 {
5849         if (pxvid == 0)
5850                 return 0;
5851
5852         if (pxvid >= 8 && pxvid < 31)
5853                 pxvid = 31;
5854
5855         return (pxvid + 2) * 125;
5856 }
5857
5858 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5859 {
5860         struct drm_device *dev = dev_priv->dev;
5861         const int vd = _pxvid_to_vd(pxvid);
5862         const int vm = vd - 1125;
5863
5864         if (INTEL_INFO(dev)->is_mobile)
5865                 return vm > 0 ? vm : 0;
5866
5867         return vd;
5868 }
5869
5870 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5871 {
5872         u64 now, diff, diffms;
5873         u32 count;
5874
5875         assert_spin_locked(&mchdev_lock);
5876
5877         now = ktime_get_raw_ns();
5878         diffms = now - dev_priv->ips.last_time2;
5879         do_div(diffms, NSEC_PER_MSEC);
5880
5881         /* Don't divide by 0 */
5882         if (!diffms)
5883                 return;
5884
5885         count = I915_READ(GFXEC);
5886
5887         if (count < dev_priv->ips.last_count2) {
5888                 diff = ~0UL - dev_priv->ips.last_count2;
5889                 diff += count;
5890         } else {
5891                 diff = count - dev_priv->ips.last_count2;
5892         }
5893
5894         dev_priv->ips.last_count2 = count;
5895         dev_priv->ips.last_time2 = now;
5896
5897         /* More magic constants... */
5898         diff = diff * 1181;
5899         diff = div_u64(diff, diffms * 10);
5900         dev_priv->ips.gfx_power = diff;
5901 }
5902
5903 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5904 {
5905         struct drm_device *dev = dev_priv->dev;
5906
5907         if (INTEL_INFO(dev)->gen != 5)
5908                 return;
5909
5910         spin_lock_irq(&mchdev_lock);
5911
5912         __i915_update_gfx_val(dev_priv);
5913
5914         spin_unlock_irq(&mchdev_lock);
5915 }
5916
5917 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5918 {
5919         unsigned long t, corr, state1, corr2, state2;
5920         u32 pxvid, ext_v;
5921
5922         assert_spin_locked(&mchdev_lock);
5923
5924         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5925         pxvid = (pxvid >> 24) & 0x7f;
5926         ext_v = pvid_to_extvid(dev_priv, pxvid);
5927
5928         state1 = ext_v;
5929
5930         t = i915_mch_val(dev_priv);
5931
5932         /* Revel in the empirically derived constants */
5933
5934         /* Correction factor in 1/100000 units */
5935         if (t > 80)
5936                 corr = ((t * 2349) + 135940);
5937         else if (t >= 50)
5938                 corr = ((t * 964) + 29317);
5939         else /* < 50 */
5940                 corr = ((t * 301) + 1004);
5941
5942         corr = corr * ((150142 * state1) / 10000 - 78642);
5943         corr /= 100000;
5944         corr2 = (corr * dev_priv->ips.corr);
5945
5946         state2 = (corr2 * state1) / 10000;
5947         state2 /= 100; /* convert to mW */
5948
5949         __i915_update_gfx_val(dev_priv);
5950
5951         return dev_priv->ips.gfx_power + state2;
5952 }
5953
5954 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5955 {
5956         struct drm_device *dev = dev_priv->dev;
5957         unsigned long val;
5958
5959         if (INTEL_INFO(dev)->gen != 5)
5960                 return 0;
5961
5962         spin_lock_irq(&mchdev_lock);
5963
5964         val = __i915_gfx_val(dev_priv);
5965
5966         spin_unlock_irq(&mchdev_lock);
5967
5968         return val;
5969 }
5970
5971 /**
5972  * i915_read_mch_val - return value for IPS use
5973  *
5974  * Calculate and return a value for the IPS driver to use when deciding whether
5975  * we have thermal and power headroom to increase CPU or GPU power budget.
5976  */
5977 unsigned long i915_read_mch_val(void)
5978 {
5979         struct drm_i915_private *dev_priv;
5980         unsigned long chipset_val, graphics_val, ret = 0;
5981
5982         spin_lock_irq(&mchdev_lock);
5983         if (!i915_mch_dev)
5984                 goto out_unlock;
5985         dev_priv = i915_mch_dev;
5986
5987         chipset_val = __i915_chipset_val(dev_priv);
5988         graphics_val = __i915_gfx_val(dev_priv);
5989
5990         ret = chipset_val + graphics_val;
5991
5992 out_unlock:
5993         spin_unlock_irq(&mchdev_lock);
5994
5995         return ret;
5996 }
5997 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5998
5999 /**
6000  * i915_gpu_raise - raise GPU frequency limit
6001  *
6002  * Raise the limit; IPS indicates we have thermal headroom.
6003  */
6004 bool i915_gpu_raise(void)
6005 {
6006         struct drm_i915_private *dev_priv;
6007         bool ret = true;
6008
6009         spin_lock_irq(&mchdev_lock);
6010         if (!i915_mch_dev) {
6011                 ret = false;
6012                 goto out_unlock;
6013         }
6014         dev_priv = i915_mch_dev;
6015
6016         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6017                 dev_priv->ips.max_delay--;
6018
6019 out_unlock:
6020         spin_unlock_irq(&mchdev_lock);
6021
6022         return ret;
6023 }
6024 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6025
6026 /**
6027  * i915_gpu_lower - lower GPU frequency limit
6028  *
6029  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6030  * frequency maximum.
6031  */
6032 bool i915_gpu_lower(void)
6033 {
6034         struct drm_i915_private *dev_priv;
6035         bool ret = true;
6036
6037         spin_lock_irq(&mchdev_lock);
6038         if (!i915_mch_dev) {
6039                 ret = false;
6040                 goto out_unlock;
6041         }
6042         dev_priv = i915_mch_dev;
6043
6044         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6045                 dev_priv->ips.max_delay++;
6046
6047 out_unlock:
6048         spin_unlock_irq(&mchdev_lock);
6049
6050         return ret;
6051 }
6052 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6053
6054 /**
6055  * i915_gpu_busy - indicate GPU business to IPS
6056  *
6057  * Tell the IPS driver whether or not the GPU is busy.
6058  */
6059 bool i915_gpu_busy(void)
6060 {
6061         struct drm_i915_private *dev_priv;
6062         struct intel_engine_cs *engine;
6063         bool ret = false;
6064
6065         spin_lock_irq(&mchdev_lock);
6066         if (!i915_mch_dev)
6067                 goto out_unlock;
6068         dev_priv = i915_mch_dev;
6069
6070         for_each_engine(engine, dev_priv)
6071                 ret |= !list_empty(&engine->request_list);
6072
6073 out_unlock:
6074         spin_unlock_irq(&mchdev_lock);
6075
6076         return ret;
6077 }
6078 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6079
6080 /**
6081  * i915_gpu_turbo_disable - disable graphics turbo
6082  *
6083  * Disable graphics turbo by resetting the max frequency and setting the
6084  * current frequency to the default.
6085  */
6086 bool i915_gpu_turbo_disable(void)
6087 {
6088         struct drm_i915_private *dev_priv;
6089         bool ret = true;
6090
6091         spin_lock_irq(&mchdev_lock);
6092         if (!i915_mch_dev) {
6093                 ret = false;
6094                 goto out_unlock;
6095         }
6096         dev_priv = i915_mch_dev;
6097
6098         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6099
6100         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6101                 ret = false;
6102
6103 out_unlock:
6104         spin_unlock_irq(&mchdev_lock);
6105
6106         return ret;
6107 }
6108 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6109
6110 /**
6111  * Tells the intel_ips driver that the i915 driver is now loaded, if
6112  * IPS got loaded first.
6113  *
6114  * This awkward dance is so that neither module has to depend on the
6115  * other in order for IPS to do the appropriate communication of
6116  * GPU turbo limits to i915.
6117  */
6118 static void
6119 ips_ping_for_i915_load(void)
6120 {
6121         void (*link)(void);
6122
6123         link = symbol_get(ips_link_to_i915_driver);
6124         if (link) {
6125                 link();
6126                 symbol_put(ips_link_to_i915_driver);
6127         }
6128 }
6129
6130 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6131 {
6132         /* We only register the i915 ips part with intel-ips once everything is
6133          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6134         spin_lock_irq(&mchdev_lock);
6135         i915_mch_dev = dev_priv;
6136         spin_unlock_irq(&mchdev_lock);
6137
6138         ips_ping_for_i915_load();
6139 }
6140
6141 void intel_gpu_ips_teardown(void)
6142 {
6143         spin_lock_irq(&mchdev_lock);
6144         i915_mch_dev = NULL;
6145         spin_unlock_irq(&mchdev_lock);
6146 }
6147
6148 static void intel_init_emon(struct drm_device *dev)
6149 {
6150         struct drm_i915_private *dev_priv = dev->dev_private;
6151         u32 lcfuse;
6152         u8 pxw[16];
6153         int i;
6154
6155         /* Disable to program */
6156         I915_WRITE(ECR, 0);
6157         POSTING_READ(ECR);
6158
6159         /* Program energy weights for various events */
6160         I915_WRITE(SDEW, 0x15040d00);
6161         I915_WRITE(CSIEW0, 0x007f0000);
6162         I915_WRITE(CSIEW1, 0x1e220004);
6163         I915_WRITE(CSIEW2, 0x04000004);
6164
6165         for (i = 0; i < 5; i++)
6166                 I915_WRITE(PEW(i), 0);
6167         for (i = 0; i < 3; i++)
6168                 I915_WRITE(DEW(i), 0);
6169
6170         /* Program P-state weights to account for frequency power adjustment */
6171         for (i = 0; i < 16; i++) {
6172                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6173                 unsigned long freq = intel_pxfreq(pxvidfreq);
6174                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6175                         PXVFREQ_PX_SHIFT;
6176                 unsigned long val;
6177
6178                 val = vid * vid;
6179                 val *= (freq / 1000);
6180                 val *= 255;
6181                 val /= (127*127*900);
6182                 if (val > 0xff)
6183                         DRM_ERROR("bad pxval: %ld\n", val);
6184                 pxw[i] = val;
6185         }
6186         /* Render standby states get 0 weight */
6187         pxw[14] = 0;
6188         pxw[15] = 0;
6189
6190         for (i = 0; i < 4; i++) {
6191                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6192                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6193                 I915_WRITE(PXW(i), val);
6194         }
6195
6196         /* Adjust magic regs to magic values (more experimental results) */
6197         I915_WRITE(OGW0, 0);
6198         I915_WRITE(OGW1, 0);
6199         I915_WRITE(EG0, 0x00007f00);
6200         I915_WRITE(EG1, 0x0000000e);
6201         I915_WRITE(EG2, 0x000e0000);
6202         I915_WRITE(EG3, 0x68000300);
6203         I915_WRITE(EG4, 0x42000000);
6204         I915_WRITE(EG5, 0x00140031);
6205         I915_WRITE(EG6, 0);
6206         I915_WRITE(EG7, 0);
6207
6208         for (i = 0; i < 8; i++)
6209                 I915_WRITE(PXWL(i), 0);
6210
6211         /* Enable PMON + select events */
6212         I915_WRITE(ECR, 0x80000019);
6213
6214         lcfuse = I915_READ(LCFUSE02);
6215
6216         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6217 }
6218
6219 void intel_init_gt_powersave(struct drm_device *dev)
6220 {
6221         struct drm_i915_private *dev_priv = dev->dev_private;
6222
6223         /*
6224          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6225          * requirement.
6226          */
6227         if (!i915.enable_rc6) {
6228                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6229                 intel_runtime_pm_get(dev_priv);
6230         }
6231
6232         if (IS_CHERRYVIEW(dev))
6233                 cherryview_init_gt_powersave(dev);
6234         else if (IS_VALLEYVIEW(dev))
6235                 valleyview_init_gt_powersave(dev);
6236 }
6237
6238 void intel_cleanup_gt_powersave(struct drm_device *dev)
6239 {
6240         struct drm_i915_private *dev_priv = dev->dev_private;
6241
6242         if (IS_CHERRYVIEW(dev))
6243                 return;
6244         else if (IS_VALLEYVIEW(dev))
6245                 valleyview_cleanup_gt_powersave(dev);
6246
6247         if (!i915.enable_rc6)
6248                 intel_runtime_pm_put(dev_priv);
6249 }
6250
6251 static void gen6_suspend_rps(struct drm_device *dev)
6252 {
6253         struct drm_i915_private *dev_priv = dev->dev_private;
6254
6255         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6256
6257         gen6_disable_rps_interrupts(dev);
6258 }
6259
6260 /**
6261  * intel_suspend_gt_powersave - suspend PM work and helper threads
6262  * @dev: drm device
6263  *
6264  * We don't want to disable RC6 or other features here, we just want
6265  * to make sure any work we've queued has finished and won't bother
6266  * us while we're suspended.
6267  */
6268 void intel_suspend_gt_powersave(struct drm_device *dev)
6269 {
6270         struct drm_i915_private *dev_priv = dev->dev_private;
6271
6272         if (INTEL_INFO(dev)->gen < 6)
6273                 return;
6274
6275         gen6_suspend_rps(dev);
6276
6277         /* Force GPU to min freq during suspend */
6278         gen6_rps_idle(dev_priv);
6279 }
6280
6281 void intel_disable_gt_powersave(struct drm_device *dev)
6282 {
6283         struct drm_i915_private *dev_priv = dev->dev_private;
6284
6285         if (IS_IRONLAKE_M(dev)) {
6286                 ironlake_disable_drps(dev);
6287         } else if (INTEL_INFO(dev)->gen >= 6) {
6288                 intel_suspend_gt_powersave(dev);
6289
6290                 mutex_lock(&dev_priv->rps.hw_lock);
6291                 if (INTEL_INFO(dev)->gen >= 9) {
6292                         gen9_disable_rc6(dev);
6293                         gen9_disable_rps(dev);
6294                 } else if (IS_CHERRYVIEW(dev))
6295                         cherryview_disable_rps(dev);
6296                 else if (IS_VALLEYVIEW(dev))
6297                         valleyview_disable_rps(dev);
6298                 else
6299                         gen6_disable_rps(dev);
6300
6301                 dev_priv->rps.enabled = false;
6302                 mutex_unlock(&dev_priv->rps.hw_lock);
6303         }
6304 }
6305
6306 static void intel_gen6_powersave_work(struct work_struct *work)
6307 {
6308         struct drm_i915_private *dev_priv =
6309                 container_of(work, struct drm_i915_private,
6310                              rps.delayed_resume_work.work);
6311         struct drm_device *dev = dev_priv->dev;
6312
6313         mutex_lock(&dev_priv->rps.hw_lock);
6314
6315         gen6_reset_rps_interrupts(dev);
6316
6317         if (IS_CHERRYVIEW(dev)) {
6318                 cherryview_enable_rps(dev);
6319         } else if (IS_VALLEYVIEW(dev)) {
6320                 valleyview_enable_rps(dev);
6321         } else if (INTEL_INFO(dev)->gen >= 9) {
6322                 gen9_enable_rc6(dev);
6323                 gen9_enable_rps(dev);
6324                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6325                         __gen6_update_ring_freq(dev);
6326         } else if (IS_BROADWELL(dev)) {
6327                 gen8_enable_rps(dev);
6328                 __gen6_update_ring_freq(dev);
6329         } else {
6330                 gen6_enable_rps(dev);
6331                 __gen6_update_ring_freq(dev);
6332         }
6333
6334         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6335         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6336
6337         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6338         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6339
6340         dev_priv->rps.enabled = true;
6341
6342         gen6_enable_rps_interrupts(dev);
6343
6344         mutex_unlock(&dev_priv->rps.hw_lock);
6345
6346         intel_runtime_pm_put(dev_priv);
6347 }
6348
6349 void intel_enable_gt_powersave(struct drm_device *dev)
6350 {
6351         struct drm_i915_private *dev_priv = dev->dev_private;
6352
6353         /* Powersaving is controlled by the host when inside a VM */
6354         if (intel_vgpu_active(dev))
6355                 return;
6356
6357         if (IS_IRONLAKE_M(dev)) {
6358                 ironlake_enable_drps(dev);
6359                 mutex_lock(&dev->struct_mutex);
6360                 intel_init_emon(dev);
6361                 mutex_unlock(&dev->struct_mutex);
6362         } else if (INTEL_INFO(dev)->gen >= 6) {
6363                 /*
6364                  * PCU communication is slow and this doesn't need to be
6365                  * done at any specific time, so do this out of our fast path
6366                  * to make resume and init faster.
6367                  *
6368                  * We depend on the HW RC6 power context save/restore
6369                  * mechanism when entering D3 through runtime PM suspend. So
6370                  * disable RPM until RPS/RC6 is properly setup. We can only
6371                  * get here via the driver load/system resume/runtime resume
6372                  * paths, so the _noresume version is enough (and in case of
6373                  * runtime resume it's necessary).
6374                  */
6375                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6376                                            round_jiffies_up_relative(HZ)))
6377                         intel_runtime_pm_get_noresume(dev_priv);
6378         }
6379 }
6380
6381 void intel_reset_gt_powersave(struct drm_device *dev)
6382 {
6383         struct drm_i915_private *dev_priv = dev->dev_private;
6384
6385         if (INTEL_INFO(dev)->gen < 6)
6386                 return;
6387
6388         gen6_suspend_rps(dev);
6389         dev_priv->rps.enabled = false;
6390 }
6391
6392 static void ibx_init_clock_gating(struct drm_device *dev)
6393 {
6394         struct drm_i915_private *dev_priv = dev->dev_private;
6395
6396         /*
6397          * On Ibex Peak and Cougar Point, we need to disable clock
6398          * gating for the panel power sequencer or it will fail to
6399          * start up when no ports are active.
6400          */
6401         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6402 }
6403
6404 static void g4x_disable_trickle_feed(struct drm_device *dev)
6405 {
6406         struct drm_i915_private *dev_priv = dev->dev_private;
6407         enum pipe pipe;
6408
6409         for_each_pipe(dev_priv, pipe) {
6410                 I915_WRITE(DSPCNTR(pipe),
6411                            I915_READ(DSPCNTR(pipe)) |
6412                            DISPPLANE_TRICKLE_FEED_DISABLE);
6413
6414                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6415                 POSTING_READ(DSPSURF(pipe));
6416         }
6417 }
6418
6419 static void ilk_init_lp_watermarks(struct drm_device *dev)
6420 {
6421         struct drm_i915_private *dev_priv = dev->dev_private;
6422
6423         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6424         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6425         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6426
6427         /*
6428          * Don't touch WM1S_LP_EN here.
6429          * Doing so could cause underruns.
6430          */
6431 }
6432
6433 static void ironlake_init_clock_gating(struct drm_device *dev)
6434 {
6435         struct drm_i915_private *dev_priv = dev->dev_private;
6436         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6437
6438         /*
6439          * Required for FBC
6440          * WaFbcDisableDpfcClockGating:ilk
6441          */
6442         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6443                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6444                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6445
6446         I915_WRITE(PCH_3DCGDIS0,
6447                    MARIUNIT_CLOCK_GATE_DISABLE |
6448                    SVSMUNIT_CLOCK_GATE_DISABLE);
6449         I915_WRITE(PCH_3DCGDIS1,
6450                    VFMUNIT_CLOCK_GATE_DISABLE);
6451
6452         /*
6453          * According to the spec the following bits should be set in
6454          * order to enable memory self-refresh
6455          * The bit 22/21 of 0x42004
6456          * The bit 5 of 0x42020
6457          * The bit 15 of 0x45000
6458          */
6459         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6460                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6461                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6462         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6463         I915_WRITE(DISP_ARB_CTL,
6464                    (I915_READ(DISP_ARB_CTL) |
6465                     DISP_FBC_WM_DIS));
6466
6467         ilk_init_lp_watermarks(dev);
6468
6469         /*
6470          * Based on the document from hardware guys the following bits
6471          * should be set unconditionally in order to enable FBC.
6472          * The bit 22 of 0x42000
6473          * The bit 22 of 0x42004
6474          * The bit 7,8,9 of 0x42020.
6475          */
6476         if (IS_IRONLAKE_M(dev)) {
6477                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6478                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6479                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6480                            ILK_FBCQ_DIS);
6481                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6482                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6483                            ILK_DPARB_GATE);
6484         }
6485
6486         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6487
6488         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6489                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6490                    ILK_ELPIN_409_SELECT);
6491         I915_WRITE(_3D_CHICKEN2,
6492                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6493                    _3D_CHICKEN2_WM_READ_PIPELINED);
6494
6495         /* WaDisableRenderCachePipelinedFlush:ilk */
6496         I915_WRITE(CACHE_MODE_0,
6497                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6498
6499         /* WaDisable_RenderCache_OperationalFlush:ilk */
6500         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6501
6502         g4x_disable_trickle_feed(dev);
6503
6504         ibx_init_clock_gating(dev);
6505 }
6506
6507 static void cpt_init_clock_gating(struct drm_device *dev)
6508 {
6509         struct drm_i915_private *dev_priv = dev->dev_private;
6510         int pipe;
6511         uint32_t val;
6512
6513         /*
6514          * On Ibex Peak and Cougar Point, we need to disable clock
6515          * gating for the panel power sequencer or it will fail to
6516          * start up when no ports are active.
6517          */
6518         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6519                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6520                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6521         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6522                    DPLS_EDP_PPS_FIX_DIS);
6523         /* The below fixes the weird display corruption, a few pixels shifted
6524          * downward, on (only) LVDS of some HP laptops with IVY.
6525          */
6526         for_each_pipe(dev_priv, pipe) {
6527                 val = I915_READ(TRANS_CHICKEN2(pipe));
6528                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6529                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6530                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6531                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6532                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6533                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6534                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6535                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6536         }
6537         /* WADP0ClockGatingDisable */
6538         for_each_pipe(dev_priv, pipe) {
6539                 I915_WRITE(TRANS_CHICKEN1(pipe),
6540                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6541         }
6542 }
6543
6544 static void gen6_check_mch_setup(struct drm_device *dev)
6545 {
6546         struct drm_i915_private *dev_priv = dev->dev_private;
6547         uint32_t tmp;
6548
6549         tmp = I915_READ(MCH_SSKPD);
6550         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6551                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6552                               tmp);
6553 }
6554
6555 static void gen6_init_clock_gating(struct drm_device *dev)
6556 {
6557         struct drm_i915_private *dev_priv = dev->dev_private;
6558         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6559
6560         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6561
6562         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6563                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6564                    ILK_ELPIN_409_SELECT);
6565
6566         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6567         I915_WRITE(_3D_CHICKEN,
6568                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6569
6570         /* WaDisable_RenderCache_OperationalFlush:snb */
6571         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6572
6573         /*
6574          * BSpec recoomends 8x4 when MSAA is used,
6575          * however in practice 16x4 seems fastest.
6576          *
6577          * Note that PS/WM thread counts depend on the WIZ hashing
6578          * disable bit, which we don't touch here, but it's good
6579          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6580          */
6581         I915_WRITE(GEN6_GT_MODE,
6582                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6583
6584         ilk_init_lp_watermarks(dev);
6585
6586         I915_WRITE(CACHE_MODE_0,
6587                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6588
6589         I915_WRITE(GEN6_UCGCTL1,
6590                    I915_READ(GEN6_UCGCTL1) |
6591                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6592                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6593
6594         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6595          * gating disable must be set.  Failure to set it results in
6596          * flickering pixels due to Z write ordering failures after
6597          * some amount of runtime in the Mesa "fire" demo, and Unigine
6598          * Sanctuary and Tropics, and apparently anything else with
6599          * alpha test or pixel discard.
6600          *
6601          * According to the spec, bit 11 (RCCUNIT) must also be set,
6602          * but we didn't debug actual testcases to find it out.
6603          *
6604          * WaDisableRCCUnitClockGating:snb
6605          * WaDisableRCPBUnitClockGating:snb
6606          */
6607         I915_WRITE(GEN6_UCGCTL2,
6608                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6609                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6610
6611         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6612         I915_WRITE(_3D_CHICKEN3,
6613                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6614
6615         /*
6616          * Bspec says:
6617          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6618          * 3DSTATE_SF number of SF output attributes is more than 16."
6619          */
6620         I915_WRITE(_3D_CHICKEN3,
6621                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6622
6623         /*
6624          * According to the spec the following bits should be
6625          * set in order to enable memory self-refresh and fbc:
6626          * The bit21 and bit22 of 0x42000
6627          * The bit21 and bit22 of 0x42004
6628          * The bit5 and bit7 of 0x42020
6629          * The bit14 of 0x70180
6630          * The bit14 of 0x71180
6631          *
6632          * WaFbcAsynchFlipDisableFbcQueue:snb
6633          */
6634         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6635                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6636                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6637         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6638                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6639                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6640         I915_WRITE(ILK_DSPCLK_GATE_D,
6641                    I915_READ(ILK_DSPCLK_GATE_D) |
6642                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6643                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6644
6645         g4x_disable_trickle_feed(dev);
6646
6647         cpt_init_clock_gating(dev);
6648
6649         gen6_check_mch_setup(dev);
6650 }
6651
6652 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6653 {
6654         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6655
6656         /*
6657          * WaVSThreadDispatchOverride:ivb,vlv
6658          *
6659          * This actually overrides the dispatch
6660          * mode for all thread types.
6661          */
6662         reg &= ~GEN7_FF_SCHED_MASK;
6663         reg |= GEN7_FF_TS_SCHED_HW;
6664         reg |= GEN7_FF_VS_SCHED_HW;
6665         reg |= GEN7_FF_DS_SCHED_HW;
6666
6667         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6668 }
6669
6670 static void lpt_init_clock_gating(struct drm_device *dev)
6671 {
6672         struct drm_i915_private *dev_priv = dev->dev_private;
6673
6674         /*
6675          * TODO: this bit should only be enabled when really needed, then
6676          * disabled when not needed anymore in order to save power.
6677          */
6678         if (HAS_PCH_LPT_LP(dev))
6679                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6680                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6681                            PCH_LP_PARTITION_LEVEL_DISABLE);
6682
6683         /* WADPOClockGatingDisable:hsw */
6684         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6685                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6686                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6687 }
6688
6689 static void lpt_suspend_hw(struct drm_device *dev)
6690 {
6691         struct drm_i915_private *dev_priv = dev->dev_private;
6692
6693         if (HAS_PCH_LPT_LP(dev)) {
6694                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6695
6696                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6697                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6698         }
6699 }
6700
6701 static void broadwell_init_clock_gating(struct drm_device *dev)
6702 {
6703         struct drm_i915_private *dev_priv = dev->dev_private;
6704         enum pipe pipe;
6705         uint32_t misccpctl;
6706
6707         ilk_init_lp_watermarks(dev);
6708
6709         /* WaSwitchSolVfFArbitrationPriority:bdw */
6710         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6711
6712         /* WaPsrDPAMaskVBlankInSRD:bdw */
6713         I915_WRITE(CHICKEN_PAR1_1,
6714                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6715
6716         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6717         for_each_pipe(dev_priv, pipe) {
6718                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6719                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6720                            BDW_DPRS_MASK_VBLANK_SRD);
6721         }
6722
6723         /* WaVSRefCountFullforceMissDisable:bdw */
6724         /* WaDSRefCountFullforceMissDisable:bdw */
6725         I915_WRITE(GEN7_FF_THREAD_MODE,
6726                    I915_READ(GEN7_FF_THREAD_MODE) &
6727                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6728
6729         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6730                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6731
6732         /* WaDisableSDEUnitClockGating:bdw */
6733         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6734                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6735
6736         /*
6737          * WaProgramL3SqcReg1Default:bdw
6738          * WaTempDisableDOPClkGating:bdw
6739          */
6740         misccpctl = I915_READ(GEN7_MISCCPCTL);
6741         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6742         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6743         /*
6744          * Wait at least 100 clocks before re-enabling clock gating. See
6745          * the definition of L3SQCREG1 in BSpec.
6746          */
6747         POSTING_READ(GEN8_L3SQCREG1);
6748         udelay(1);
6749         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6750
6751         /*
6752          * WaGttCachingOffByDefault:bdw
6753          * GTT cache may not work with big pages, so if those
6754          * are ever enabled GTT cache may need to be disabled.
6755          */
6756         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6757
6758         lpt_init_clock_gating(dev);
6759 }
6760
6761 static void haswell_init_clock_gating(struct drm_device *dev)
6762 {
6763         struct drm_i915_private *dev_priv = dev->dev_private;
6764
6765         ilk_init_lp_watermarks(dev);
6766
6767         /* L3 caching of data atomics doesn't work -- disable it. */
6768         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6769         I915_WRITE(HSW_ROW_CHICKEN3,
6770                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6771
6772         /* This is required by WaCatErrorRejectionIssue:hsw */
6773         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6774                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6775                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6776
6777         /* WaVSRefCountFullforceMissDisable:hsw */
6778         I915_WRITE(GEN7_FF_THREAD_MODE,
6779                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6780
6781         /* WaDisable_RenderCache_OperationalFlush:hsw */
6782         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6783
6784         /* enable HiZ Raw Stall Optimization */
6785         I915_WRITE(CACHE_MODE_0_GEN7,
6786                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6787
6788         /* WaDisable4x2SubspanOptimization:hsw */
6789         I915_WRITE(CACHE_MODE_1,
6790                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6791
6792         /*
6793          * BSpec recommends 8x4 when MSAA is used,
6794          * however in practice 16x4 seems fastest.
6795          *
6796          * Note that PS/WM thread counts depend on the WIZ hashing
6797          * disable bit, which we don't touch here, but it's good
6798          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6799          */
6800         I915_WRITE(GEN7_GT_MODE,
6801                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6802
6803         /* WaSampleCChickenBitEnable:hsw */
6804         I915_WRITE(HALF_SLICE_CHICKEN3,
6805                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6806
6807         /* WaSwitchSolVfFArbitrationPriority:hsw */
6808         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6809
6810         /* WaRsPkgCStateDisplayPMReq:hsw */
6811         I915_WRITE(CHICKEN_PAR1_1,
6812                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6813
6814         lpt_init_clock_gating(dev);
6815 }
6816
6817 static void ivybridge_init_clock_gating(struct drm_device *dev)
6818 {
6819         struct drm_i915_private *dev_priv = dev->dev_private;
6820         uint32_t snpcr;
6821
6822         ilk_init_lp_watermarks(dev);
6823
6824         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6825
6826         /* WaDisableEarlyCull:ivb */
6827         I915_WRITE(_3D_CHICKEN3,
6828                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6829
6830         /* WaDisableBackToBackFlipFix:ivb */
6831         I915_WRITE(IVB_CHICKEN3,
6832                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6833                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6834
6835         /* WaDisablePSDDualDispatchEnable:ivb */
6836         if (IS_IVB_GT1(dev))
6837                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6838                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6839
6840         /* WaDisable_RenderCache_OperationalFlush:ivb */
6841         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6842
6843         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6844         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6845                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6846
6847         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6848         I915_WRITE(GEN7_L3CNTLREG1,
6849                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6850         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6851                    GEN7_WA_L3_CHICKEN_MODE);
6852         if (IS_IVB_GT1(dev))
6853                 I915_WRITE(GEN7_ROW_CHICKEN2,
6854                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6855         else {
6856                 /* must write both registers */
6857                 I915_WRITE(GEN7_ROW_CHICKEN2,
6858                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6859                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6860                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6861         }
6862
6863         /* WaForceL3Serialization:ivb */
6864         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6865                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6866
6867         /*
6868          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6869          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6870          */
6871         I915_WRITE(GEN6_UCGCTL2,
6872                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6873
6874         /* This is required by WaCatErrorRejectionIssue:ivb */
6875         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6876                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6877                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6878
6879         g4x_disable_trickle_feed(dev);
6880
6881         gen7_setup_fixed_func_scheduler(dev_priv);
6882
6883         if (0) { /* causes HiZ corruption on ivb:gt1 */
6884                 /* enable HiZ Raw Stall Optimization */
6885                 I915_WRITE(CACHE_MODE_0_GEN7,
6886                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6887         }
6888
6889         /* WaDisable4x2SubspanOptimization:ivb */
6890         I915_WRITE(CACHE_MODE_1,
6891                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6892
6893         /*
6894          * BSpec recommends 8x4 when MSAA is used,
6895          * however in practice 16x4 seems fastest.
6896          *
6897          * Note that PS/WM thread counts depend on the WIZ hashing
6898          * disable bit, which we don't touch here, but it's good
6899          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6900          */
6901         I915_WRITE(GEN7_GT_MODE,
6902                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6903
6904         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6905         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6906         snpcr |= GEN6_MBC_SNPCR_MED;
6907         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6908
6909         if (!HAS_PCH_NOP(dev))
6910                 cpt_init_clock_gating(dev);
6911
6912         gen6_check_mch_setup(dev);
6913 }
6914
6915 static void valleyview_init_clock_gating(struct drm_device *dev)
6916 {
6917         struct drm_i915_private *dev_priv = dev->dev_private;
6918
6919         /* WaDisableEarlyCull:vlv */
6920         I915_WRITE(_3D_CHICKEN3,
6921                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6922
6923         /* WaDisableBackToBackFlipFix:vlv */
6924         I915_WRITE(IVB_CHICKEN3,
6925                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6926                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6927
6928         /* WaPsdDispatchEnable:vlv */
6929         /* WaDisablePSDDualDispatchEnable:vlv */
6930         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6931                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6932                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6933
6934         /* WaDisable_RenderCache_OperationalFlush:vlv */
6935         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6936
6937         /* WaForceL3Serialization:vlv */
6938         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6939                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6940
6941         /* WaDisableDopClockGating:vlv */
6942         I915_WRITE(GEN7_ROW_CHICKEN2,
6943                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6944
6945         /* This is required by WaCatErrorRejectionIssue:vlv */
6946         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6947                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6948                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6949
6950         gen7_setup_fixed_func_scheduler(dev_priv);
6951
6952         /*
6953          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6954          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6955          */
6956         I915_WRITE(GEN6_UCGCTL2,
6957                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6958
6959         /* WaDisableL3Bank2xClockGate:vlv
6960          * Disabling L3 clock gating- MMIO 940c[25] = 1
6961          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6962         I915_WRITE(GEN7_UCGCTL4,
6963                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6964
6965         /*
6966          * BSpec says this must be set, even though
6967          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6968          */
6969         I915_WRITE(CACHE_MODE_1,
6970                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6971
6972         /*
6973          * BSpec recommends 8x4 when MSAA is used,
6974          * however in practice 16x4 seems fastest.
6975          *
6976          * Note that PS/WM thread counts depend on the WIZ hashing
6977          * disable bit, which we don't touch here, but it's good
6978          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6979          */
6980         I915_WRITE(GEN7_GT_MODE,
6981                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6982
6983         /*
6984          * WaIncreaseL3CreditsForVLVB0:vlv
6985          * This is the hardware default actually.
6986          */
6987         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6988
6989         /*
6990          * WaDisableVLVClockGating_VBIIssue:vlv
6991          * Disable clock gating on th GCFG unit to prevent a delay
6992          * in the reporting of vblank events.
6993          */
6994         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6995 }
6996
6997 static void cherryview_init_clock_gating(struct drm_device *dev)
6998 {
6999         struct drm_i915_private *dev_priv = dev->dev_private;
7000
7001         /* WaVSRefCountFullforceMissDisable:chv */
7002         /* WaDSRefCountFullforceMissDisable:chv */
7003         I915_WRITE(GEN7_FF_THREAD_MODE,
7004                    I915_READ(GEN7_FF_THREAD_MODE) &
7005                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7006
7007         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7008         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7009                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7010
7011         /* WaDisableCSUnitClockGating:chv */
7012         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7013                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7014
7015         /* WaDisableSDEUnitClockGating:chv */
7016         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7017                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7018
7019         /*
7020          * GTT cache may not work with big pages, so if those
7021          * are ever enabled GTT cache may need to be disabled.
7022          */
7023         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7024 }
7025
7026 static void g4x_init_clock_gating(struct drm_device *dev)
7027 {
7028         struct drm_i915_private *dev_priv = dev->dev_private;
7029         uint32_t dspclk_gate;
7030
7031         I915_WRITE(RENCLK_GATE_D1, 0);
7032         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7033                    GS_UNIT_CLOCK_GATE_DISABLE |
7034                    CL_UNIT_CLOCK_GATE_DISABLE);
7035         I915_WRITE(RAMCLK_GATE_D, 0);
7036         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7037                 OVRUNIT_CLOCK_GATE_DISABLE |
7038                 OVCUNIT_CLOCK_GATE_DISABLE;
7039         if (IS_GM45(dev))
7040                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7041         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7042
7043         /* WaDisableRenderCachePipelinedFlush */
7044         I915_WRITE(CACHE_MODE_0,
7045                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7046
7047         /* WaDisable_RenderCache_OperationalFlush:g4x */
7048         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7049
7050         g4x_disable_trickle_feed(dev);
7051 }
7052
7053 static void crestline_init_clock_gating(struct drm_device *dev)
7054 {
7055         struct drm_i915_private *dev_priv = dev->dev_private;
7056
7057         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7058         I915_WRITE(RENCLK_GATE_D2, 0);
7059         I915_WRITE(DSPCLK_GATE_D, 0);
7060         I915_WRITE(RAMCLK_GATE_D, 0);
7061         I915_WRITE16(DEUC, 0);
7062         I915_WRITE(MI_ARB_STATE,
7063                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7064
7065         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7066         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7067 }
7068
7069 static void broadwater_init_clock_gating(struct drm_device *dev)
7070 {
7071         struct drm_i915_private *dev_priv = dev->dev_private;
7072
7073         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7074                    I965_RCC_CLOCK_GATE_DISABLE |
7075                    I965_RCPB_CLOCK_GATE_DISABLE |
7076                    I965_ISC_CLOCK_GATE_DISABLE |
7077                    I965_FBC_CLOCK_GATE_DISABLE);
7078         I915_WRITE(RENCLK_GATE_D2, 0);
7079         I915_WRITE(MI_ARB_STATE,
7080                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7081
7082         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7083         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7084 }
7085
7086 static void gen3_init_clock_gating(struct drm_device *dev)
7087 {
7088         struct drm_i915_private *dev_priv = dev->dev_private;
7089         u32 dstate = I915_READ(D_STATE);
7090
7091         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7092                 DSTATE_DOT_CLOCK_GATING;
7093         I915_WRITE(D_STATE, dstate);
7094
7095         if (IS_PINEVIEW(dev))
7096                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7097
7098         /* IIR "flip pending" means done if this bit is set */
7099         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7100
7101         /* interrupts should cause a wake up from C3 */
7102         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7103
7104         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7105         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7106
7107         I915_WRITE(MI_ARB_STATE,
7108                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7109 }
7110
7111 static void i85x_init_clock_gating(struct drm_device *dev)
7112 {
7113         struct drm_i915_private *dev_priv = dev->dev_private;
7114
7115         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7116
7117         /* interrupts should cause a wake up from C3 */
7118         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7119                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7120
7121         I915_WRITE(MEM_MODE,
7122                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7123 }
7124
7125 static void i830_init_clock_gating(struct drm_device *dev)
7126 {
7127         struct drm_i915_private *dev_priv = dev->dev_private;
7128
7129         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7130
7131         I915_WRITE(MEM_MODE,
7132                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7133                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7134 }
7135
7136 void intel_init_clock_gating(struct drm_device *dev)
7137 {
7138         struct drm_i915_private *dev_priv = dev->dev_private;
7139
7140         dev_priv->display.init_clock_gating(dev);
7141 }
7142
7143 void intel_suspend_hw(struct drm_device *dev)
7144 {
7145         if (HAS_PCH_LPT(dev))
7146                 lpt_suspend_hw(dev);
7147 }
7148
7149 static void nop_init_clock_gating(struct drm_device *dev)
7150 {
7151         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7152 }
7153
7154 /**
7155  * intel_init_clock_gating_hooks - setup the clock gating hooks
7156  * @dev_priv: device private
7157  *
7158  * Setup the hooks that configure which clocks of a given platform can be
7159  * gated and also apply various GT and display specific workarounds for these
7160  * platforms. Note that some GT specific workarounds are applied separately
7161  * when GPU contexts or batchbuffers start their execution.
7162  */
7163 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7164 {
7165         if (IS_SKYLAKE(dev_priv))
7166                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7167         else if (IS_KABYLAKE(dev_priv))
7168                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7169         else if (IS_BROXTON(dev_priv))
7170                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7171         else if (IS_BROADWELL(dev_priv))
7172                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7173         else if (IS_CHERRYVIEW(dev_priv))
7174                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7175         else if (IS_HASWELL(dev_priv))
7176                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7177         else if (IS_IVYBRIDGE(dev_priv))
7178                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7179         else if (IS_VALLEYVIEW(dev_priv))
7180                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7181         else if (IS_GEN6(dev_priv))
7182                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7183         else if (IS_GEN5(dev_priv))
7184                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7185         else if (IS_G4X(dev_priv))
7186                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7187         else if (IS_CRESTLINE(dev_priv))
7188                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7189         else if (IS_BROADWATER(dev_priv))
7190                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7191         else if (IS_GEN3(dev_priv))
7192                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7193         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7194                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7195         else if (IS_GEN2(dev_priv))
7196                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7197         else {
7198                 MISSING_CASE(INTEL_DEVID(dev_priv));
7199                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7200         }
7201 }
7202
7203 /* Set up chip specific power management-related functions */
7204 void intel_init_pm(struct drm_device *dev)
7205 {
7206         struct drm_i915_private *dev_priv = dev->dev_private;
7207
7208         intel_fbc_init(dev_priv);
7209
7210         /* For cxsr */
7211         if (IS_PINEVIEW(dev))
7212                 i915_pineview_get_mem_freq(dev);
7213         else if (IS_GEN5(dev))
7214                 i915_ironlake_get_mem_freq(dev);
7215
7216         /* For FIFO watermark updates */
7217         if (INTEL_INFO(dev)->gen >= 9) {
7218                 skl_setup_wm_latency(dev);
7219                 dev_priv->display.update_wm = skl_update_wm;
7220         } else if (HAS_PCH_SPLIT(dev)) {
7221                 ilk_setup_wm_latency(dev);
7222
7223                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7224                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7225                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7226                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7227                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7228                         dev_priv->display.compute_intermediate_wm =
7229                                 ilk_compute_intermediate_wm;
7230                         dev_priv->display.initial_watermarks =
7231                                 ilk_initial_watermarks;
7232                         dev_priv->display.optimize_watermarks =
7233                                 ilk_optimize_watermarks;
7234                 } else {
7235                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7236                                       "Disable CxSR\n");
7237                 }
7238         } else if (IS_CHERRYVIEW(dev)) {
7239                 vlv_setup_wm_latency(dev);
7240                 dev_priv->display.update_wm = vlv_update_wm;
7241         } else if (IS_VALLEYVIEW(dev)) {
7242                 vlv_setup_wm_latency(dev);
7243                 dev_priv->display.update_wm = vlv_update_wm;
7244         } else if (IS_PINEVIEW(dev)) {
7245                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7246                                             dev_priv->is_ddr3,
7247                                             dev_priv->fsb_freq,
7248                                             dev_priv->mem_freq)) {
7249                         DRM_INFO("failed to find known CxSR latency "
7250                                  "(found ddr%s fsb freq %d, mem freq %d), "
7251                                  "disabling CxSR\n",
7252                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7253                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7254                         /* Disable CxSR and never update its watermark again */
7255                         intel_set_memory_cxsr(dev_priv, false);
7256                         dev_priv->display.update_wm = NULL;
7257                 } else
7258                         dev_priv->display.update_wm = pineview_update_wm;
7259         } else if (IS_G4X(dev)) {
7260                 dev_priv->display.update_wm = g4x_update_wm;
7261         } else if (IS_GEN4(dev)) {
7262                 dev_priv->display.update_wm = i965_update_wm;
7263         } else if (IS_GEN3(dev)) {
7264                 dev_priv->display.update_wm = i9xx_update_wm;
7265                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7266         } else if (IS_GEN2(dev)) {
7267                 if (INTEL_INFO(dev)->num_pipes == 1) {
7268                         dev_priv->display.update_wm = i845_update_wm;
7269                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7270                 } else {
7271                         dev_priv->display.update_wm = i9xx_update_wm;
7272                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7273                 }
7274         } else {
7275                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7276         }
7277 }
7278
7279 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7280 {
7281         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7282
7283         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7284                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7285                 return -EAGAIN;
7286         }
7287
7288         I915_WRITE(GEN6_PCODE_DATA, *val);
7289         I915_WRITE(GEN6_PCODE_DATA1, 0);
7290         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7291
7292         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7293                      500)) {
7294                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7295                 return -ETIMEDOUT;
7296         }
7297
7298         *val = I915_READ(GEN6_PCODE_DATA);
7299         I915_WRITE(GEN6_PCODE_DATA, 0);
7300
7301         return 0;
7302 }
7303
7304 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7305 {
7306         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7307
7308         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7309                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7310                 return -EAGAIN;
7311         }
7312
7313         I915_WRITE(GEN6_PCODE_DATA, val);
7314         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7315
7316         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7317                      500)) {
7318                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7319                 return -ETIMEDOUT;
7320         }
7321
7322         I915_WRITE(GEN6_PCODE_DATA, 0);
7323
7324         return 0;
7325 }
7326
7327 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7328 {
7329         /*
7330          * N = val - 0xb7
7331          * Slow = Fast = GPLL ref * N
7332          */
7333         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7334 }
7335
7336 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7337 {
7338         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7339 }
7340
7341 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7342 {
7343         /*
7344          * N = val / 2
7345          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7346          */
7347         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7348 }
7349
7350 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7351 {
7352         /* CHV needs even values */
7353         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7354 }
7355
7356 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7357 {
7358         if (IS_GEN9(dev_priv))
7359                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7360                                          GEN9_FREQ_SCALER);
7361         else if (IS_CHERRYVIEW(dev_priv))
7362                 return chv_gpu_freq(dev_priv, val);
7363         else if (IS_VALLEYVIEW(dev_priv))
7364                 return byt_gpu_freq(dev_priv, val);
7365         else
7366                 return val * GT_FREQUENCY_MULTIPLIER;
7367 }
7368
7369 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7370 {
7371         if (IS_GEN9(dev_priv))
7372                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7373                                          GT_FREQUENCY_MULTIPLIER);
7374         else if (IS_CHERRYVIEW(dev_priv))
7375                 return chv_freq_opcode(dev_priv, val);
7376         else if (IS_VALLEYVIEW(dev_priv))
7377                 return byt_freq_opcode(dev_priv, val);
7378         else
7379                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7380 }
7381
7382 struct request_boost {
7383         struct work_struct work;
7384         struct drm_i915_gem_request *req;
7385 };
7386
7387 static void __intel_rps_boost_work(struct work_struct *work)
7388 {
7389         struct request_boost *boost = container_of(work, struct request_boost, work);
7390         struct drm_i915_gem_request *req = boost->req;
7391
7392         if (!i915_gem_request_completed(req, true))
7393                 gen6_rps_boost(to_i915(req->engine->dev), NULL,
7394                                req->emitted_jiffies);
7395
7396         i915_gem_request_unreference__unlocked(req);
7397         kfree(boost);
7398 }
7399
7400 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7401                                        struct drm_i915_gem_request *req)
7402 {
7403         struct request_boost *boost;
7404
7405         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7406                 return;
7407
7408         if (i915_gem_request_completed(req, true))
7409                 return;
7410
7411         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7412         if (boost == NULL)
7413                 return;
7414
7415         i915_gem_request_reference(req);
7416         boost->req = req;
7417
7418         INIT_WORK(&boost->work, __intel_rps_boost_work);
7419         queue_work(to_i915(dev)->wq, &boost->work);
7420 }
7421
7422 void intel_pm_setup(struct drm_device *dev)
7423 {
7424         struct drm_i915_private *dev_priv = dev->dev_private;
7425
7426         mutex_init(&dev_priv->rps.hw_lock);
7427         spin_lock_init(&dev_priv->rps.client_lock);
7428
7429         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7430                           intel_gen6_powersave_work);
7431         INIT_LIST_HEAD(&dev_priv->rps.clients);
7432         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7433         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7434
7435         dev_priv->pm.suspended = false;
7436         atomic_set(&dev_priv->pm.wakeref_count, 0);
7437         atomic_set(&dev_priv->pm.atomic_seq, 0);
7438 }