drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - (tail + I915_RING_FREE_SPACE);
  56         if (space < 0)
  57                 space += size;
  58         return space;
  59 }
  60
  61 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         return __intel_ring_space(ringbuf->head & HEAD_ADDR,
  64                                   ringbuf->tail, ringbuf->size);
  65 }
  66
  67 bool intel_ring_stopped(struct intel_engine_cs *ring)
  68 {
  69         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  70         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  71 }
  72
  73 void __intel_ring_advance(struct intel_engine_cs *ring)
  74 {
  75         struct intel_ringbuffer *ringbuf = ring->buffer;
  76         ringbuf->tail &= ringbuf->size - 1;
  77         if (intel_ring_stopped(ring))
  78                 return;
  79         ring->write_tail(ring, ringbuf->tail);
  80 }
  81
  82 static int
  83 gen2_render_ring_flush(struct intel_engine_cs *ring,
  84                        u32      invalidate_domains,
  85                        u32      flush_domains)
  86 {
  87         u32 cmd;
  88         int ret;
  89
  90         cmd = MI_FLUSH;
  91         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  92                 cmd |= MI_NO_WRITE_FLUSH;
  93
  94         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  95                 cmd |= MI_READ_FLUSH;
  96
  97         ret = intel_ring_begin(ring, 2);
  98         if (ret)
  99                 return ret;
 100
 101         intel_ring_emit(ring, cmd);
 102         intel_ring_emit(ring, MI_NOOP);
 103         intel_ring_advance(ring);
 104
 105         return 0;
 106 }
 107
 108 static int
 109 gen4_render_ring_flush(struct intel_engine_cs *ring,
 110                        u32      invalidate_domains,
 111                        u32      flush_domains)
 112 {
 113         struct drm_device *dev = ring->dev;
 114         u32 cmd;
 115         int ret;
 116
 117         /*
 118          * read/write caches:
 119          *
 120          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 121          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 122          * also flushed at 2d versus 3d pipeline switches.
 123          *
 124          * read-only caches:
 125          *
 126          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 127          * MI_READ_FLUSH is set, and is always flushed on 965.
 128          *
 129          * I915_GEM_DOMAIN_COMMAND may not exist?
 130          *
 131          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 132          * invalidated when MI_EXE_FLUSH is set.
 133          *
 134          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 135          * invalidated with every MI_FLUSH.
 136          *
 137          * TLBs:
 138          *
 139          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 140          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 141          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 142          * are flushed at any MI_FLUSH.
 143          */
 144
 145         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 146         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 147                 cmd &= ~MI_NO_WRITE_FLUSH;
 148         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 149                 cmd |= MI_EXE_FLUSH;
 150
 151         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 152             (IS_G4X(dev) || IS_GEN5(dev)))
 153                 cmd |= MI_INVALIDATE_ISP;
 154
 155         ret = intel_ring_begin(ring, 2);
 156         if (ret)
 157                 return ret;
 158
 159         intel_ring_emit(ring, cmd);
 160         intel_ring_emit(ring, MI_NOOP);
 161         intel_ring_advance(ring);
 162
 163         return 0;
 164 }
 165
 166 /**
 167  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 168  * implementing two workarounds on gen6.  From section 1.4.7.1
 169  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 170  *
 171  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 172  * produced by non-pipelined state commands), software needs to first
 173  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 174  * 0.
 175  *
 176  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 177  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 178  *
 179  * And the workaround for these two requires this workaround first:
 180  *
 181  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 182  * BEFORE the pipe-control with a post-sync op and no write-cache
 183  * flushes.
 184  *
 185  * And this last workaround is tricky because of the requirements on
 186  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 187  * volume 2 part 1:
 188  *
 189  *     "1 of the following must also be set:
 190  *      - Render Target Cache Flush Enable ([12] of DW1)
 191  *      - Depth Cache Flush Enable ([0] of DW1)
 192  *      - Stall at Pixel Scoreboard ([1] of DW1)
 193  *      - Depth Stall ([13] of DW1)
 194  *      - Post-Sync Operation ([13] of DW1)
 195  *      - Notify Enable ([8] of DW1)"
 196  *
 197  * The cache flushes require the workaround flush that triggered this
 198  * one, so we can't use it.  Depth stall would trigger the same.
 199  * Post-sync nonzero is what triggered this second workaround, so we
 200  * can't use that one either.  Notify enable is IRQs, which aren't
 201  * really our business.  That leaves only stall at scoreboard.
 202  */
 203 static int
 204 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 205 {
 206         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 207         int ret;
 208
 209
 210         ret = intel_ring_begin(ring, 6);
 211         if (ret)
 212                 return ret;
 213
 214         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 215         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 216                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 217         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 218         intel_ring_emit(ring, 0); /* low dword */
 219         intel_ring_emit(ring, 0); /* high dword */
 220         intel_ring_emit(ring, MI_NOOP);
 221         intel_ring_advance(ring);
 222
 223         ret = intel_ring_begin(ring, 6);
 224         if (ret)
 225                 return ret;
 226
 227         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 228         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 229         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 230         intel_ring_emit(ring, 0);
 231         intel_ring_emit(ring, 0);
 232         intel_ring_emit(ring, MI_NOOP);
 233         intel_ring_advance(ring);
 234
 235         return 0;
 236 }
 237
 238 static int
 239 gen6_render_ring_flush(struct intel_engine_cs *ring,
 240                          u32 invalidate_domains, u32 flush_domains)
 241 {
 242         u32 flags = 0;
 243         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 244         int ret;
 245
 246         /* Force SNB workarounds for PIPE_CONTROL flushes */
 247         ret = intel_emit_post_sync_nonzero_flush(ring);
 248         if (ret)
 249                 return ret;
 250
 251         /* Just flush everything.  Experiments have shown that reducing the
 252          * number of bits based on the write domains has little performance
 253          * impact.
 254          */
 255         if (flush_domains) {
 256                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 257                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 258                 /*
 259                  * Ensure that any following seqno writes only happen
 260                  * when the render cache is indeed flushed.
 261                  */
 262                 flags |= PIPE_CONTROL_CS_STALL;
 263         }
 264         if (invalidate_domains) {
 265                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 266                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 267                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 268                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 269                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 270                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 271                 /*
 272                  * TLB invalidate requires a post-sync write.
 273                  */
 274                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 275         }
 276
 277         ret = intel_ring_begin(ring, 4);
 278         if (ret)
 279                 return ret;
 280
 281         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 282         intel_ring_emit(ring, flags);
 283         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 284         intel_ring_emit(ring, 0);
 285         intel_ring_advance(ring);
 286
 287         return 0;
 288 }
 289
 290 static int
 291 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 292 {
 293         int ret;
 294
 295         ret = intel_ring_begin(ring, 4);
 296         if (ret)
 297                 return ret;
 298
 299         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 300         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 301                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 302         intel_ring_emit(ring, 0);
 303         intel_ring_emit(ring, 0);
 304         intel_ring_advance(ring);
 305
 306         return 0;
 307 }
 308
 309 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
 310 {
 311         int ret;
 312
 313         if (!ring->fbc_dirty)
 314                 return 0;
 315
 316         ret = intel_ring_begin(ring, 6);
 317         if (ret)
 318                 return ret;
 319         /* WaFbcNukeOn3DBlt:ivb/hsw */
 320         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 321         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 322         intel_ring_emit(ring, value);
 323         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 324         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 325         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 326         intel_ring_advance(ring);
 327
 328         ring->fbc_dirty = false;
 329         return 0;
 330 }
 331
 332 static int
 333 gen7_render_ring_flush(struct intel_engine_cs *ring,
 334                        u32 invalidate_domains, u32 flush_domains)
 335 {
 336         u32 flags = 0;
 337         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 338         int ret;
 339
 340         /*
 341          * Ensure that any following seqno writes only happen when the render
 342          * cache is indeed flushed.
 343          *
 344          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 345          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 346          * don't try to be clever and just set it unconditionally.
 347          */
 348         flags |= PIPE_CONTROL_CS_STALL;
 349
 350         /* Just flush everything.  Experiments have shown that reducing the
 351          * number of bits based on the write domains has little performance
 352          * impact.
 353          */
 354         if (flush_domains) {
 355                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 356                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 357         }
 358         if (invalidate_domains) {
 359                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 360                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 361                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 362                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 363                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 364                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 365                 /*
 366                  * TLB invalidate requires a post-sync write.
 367                  */
 368                 flags |= PIPE_CONTROL_QW_WRITE;
 369                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 370
 371                 /* Workaround: we must issue a pipe_control with CS-stall bit
 372                  * set before a pipe_control command that has the state cache
 373                  * invalidate bit set. */
 374                 gen7_render_ring_cs_stall_wa(ring);
 375         }
 376
 377         ret = intel_ring_begin(ring, 4);
 378         if (ret)
 379                 return ret;
 380
 381         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 382         intel_ring_emit(ring, flags);
 383         intel_ring_emit(ring, scratch_addr);
 384         intel_ring_emit(ring, 0);
 385         intel_ring_advance(ring);
 386
 387         if (!invalidate_domains && flush_domains)
 388                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 389
 390         return 0;
 391 }
 392
 393 static int
 394 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 395                        u32 flags, u32 scratch_addr)
 396 {
 397         int ret;
 398
 399         ret = intel_ring_begin(ring, 6);
 400         if (ret)
 401                 return ret;
 402
 403         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 404         intel_ring_emit(ring, flags);
 405         intel_ring_emit(ring, scratch_addr);
 406         intel_ring_emit(ring, 0);
 407         intel_ring_emit(ring, 0);
 408         intel_ring_emit(ring, 0);
 409         intel_ring_advance(ring);
 410
 411         return 0;
 412 }
 413
 414 static int
 415 gen8_render_ring_flush(struct intel_engine_cs *ring,
 416                        u32 invalidate_domains, u32 flush_domains)
 417 {
 418         u32 flags = 0;
 419         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 420         int ret;
 421
 422         flags |= PIPE_CONTROL_CS_STALL;
 423
 424         if (flush_domains) {
 425                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 426                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 427         }
 428         if (invalidate_domains) {
 429                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 430                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 431                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 432                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 433                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 434                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 435                 flags |= PIPE_CONTROL_QW_WRITE;
 436                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 437
 438                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 439                 ret = gen8_emit_pipe_control(ring,
 440                                              PIPE_CONTROL_CS_STALL |
 441                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 442                                              0);
 443                 if (ret)
 444                         return ret;
 445         }
 446
 447         ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
 448         if (ret)
 449                 return ret;
 450
 451         if (!invalidate_domains && flush_domains)
 452                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 453
 454         return 0;
 455 }
 456
 457 static void ring_write_tail(struct intel_engine_cs *ring,
 458                             u32 value)
 459 {
 460         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 461         I915_WRITE_TAIL(ring, value);
 462 }
 463
 464 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 465 {
 466         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 467         u64 acthd;
 468
 469         if (INTEL_INFO(ring->dev)->gen >= 8)
 470                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 471                                          RING_ACTHD_UDW(ring->mmio_base));
 472         else if (INTEL_INFO(ring->dev)->gen >= 4)
 473                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 474         else
 475                 acthd = I915_READ(ACTHD);
 476
 477         return acthd;
 478 }
 479
 480 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 481 {
 482         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 483         u32 addr;
 484
 485         addr = dev_priv->status_page_dmah->busaddr;
 486         if (INTEL_INFO(ring->dev)->gen >= 4)
 487                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 488         I915_WRITE(HWS_PGA, addr);
 489 }
 490
 491 static bool stop_ring(struct intel_engine_cs *ring)
 492 {
 493         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 494
 495         if (!IS_GEN2(ring->dev)) {
 496                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 497                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 498                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 499                         /* Sometimes we observe that the idle flag is not
 500                          * set even though the ring is empty. So double
 501                          * check before giving up.
 502                          */
 503                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 504                                 return false;
 505                 }
 506         }
 507
 508         I915_WRITE_CTL(ring, 0);
 509         I915_WRITE_HEAD(ring, 0);
 510         ring->write_tail(ring, 0);
 511
 512         if (!IS_GEN2(ring->dev)) {
 513                 (void)I915_READ_CTL(ring);
 514                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 515         }
 516
 517         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 518 }
 519
 520 static int init_ring_common(struct intel_engine_cs *ring)
 521 {
 522         struct drm_device *dev = ring->dev;
 523         struct drm_i915_private *dev_priv = dev->dev_private;
 524         struct intel_ringbuffer *ringbuf = ring->buffer;
 525         struct drm_i915_gem_object *obj = ringbuf->obj;
 526         int ret = 0;
 527
 528         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 529
 530         if (!stop_ring(ring)) {
 531                 /* G45 ring initialization often fails to reset head to zero */
 532                 DRM_DEBUG_KMS("%s head not reset to zero "
 533                               "ctl %08x head %08x tail %08x start %08x\n",
 534                               ring->name,
 535                               I915_READ_CTL(ring),
 536                               I915_READ_HEAD(ring),
 537                               I915_READ_TAIL(ring),
 538                               I915_READ_START(ring));
 539
 540                 if (!stop_ring(ring)) {
 541                         DRM_ERROR("failed to set %s head to zero "
 542                                   "ctl %08x head %08x tail %08x start %08x\n",
 543                                   ring->name,
 544                                   I915_READ_CTL(ring),
 545                                   I915_READ_HEAD(ring),
 546                                   I915_READ_TAIL(ring),
 547                                   I915_READ_START(ring));
 548                         ret = -EIO;
 549                         goto out;
 550                 }
 551         }
 552
 553         if (I915_NEED_GFX_HWS(dev))
 554                 intel_ring_setup_status_page(ring);
 555         else
 556                 ring_setup_phys_status_page(ring);
 557
 558         /* Enforce ordering by reading HEAD register back */
 559         I915_READ_HEAD(ring);
 560
 561         /* Initialize the ring. This must happen _after_ we've cleared the ring
 562          * registers with the above sequence (the readback of the HEAD registers
 563          * also enforces ordering), otherwise the hw might lose the new ring
 564          * register values. */
 565         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 566
 567         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 568         if (I915_READ_HEAD(ring))
 569                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 570                           ring->name, I915_READ_HEAD(ring));
 571         I915_WRITE_HEAD(ring, 0);
 572         (void)I915_READ_HEAD(ring);
 573
 574         I915_WRITE_CTL(ring,
 575                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 576                         | RING_VALID);
 577
 578         /* If the head is still not zero, the ring is dead */
 579         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 580                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 581                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 582                 DRM_ERROR("%s initialization failed "
 583                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 584                           ring->name,
 585                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 586                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 587                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 588                 ret = -EIO;
 589                 goto out;
 590         }
 591
 592         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 593                 i915_kernel_lost_context(ring->dev);
 594         else {
 595                 ringbuf->head = I915_READ_HEAD(ring);
 596                 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 597                 ringbuf->space = intel_ring_space(ringbuf);
 598                 ringbuf->last_retired_head = -1;
 599         }
 600
 601         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 602
 603 out:
 604         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 605
 606         return ret;
 607 }
 608
 609 void
 610 intel_fini_pipe_control(struct intel_engine_cs *ring)
 611 {
 612         struct drm_device *dev = ring->dev;
 613
 614         if (ring->scratch.obj == NULL)
 615                 return;
 616
 617         if (INTEL_INFO(dev)->gen >= 5) {
 618                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 619                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 620         }
 621
 622         drm_gem_object_unreference(&ring->scratch.obj->base);
 623         ring->scratch.obj = NULL;
 624 }
 625
 626 int
 627 intel_init_pipe_control(struct intel_engine_cs *ring)
 628 {
 629         int ret;
 630
 631         if (ring->scratch.obj)
 632                 return 0;
 633
 634         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 635         if (ring->scratch.obj == NULL) {
 636                 DRM_ERROR("Failed to allocate seqno page\n");
 637                 ret = -ENOMEM;
 638                 goto err;
 639         }
 640
 641         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 642         if (ret)
 643                 goto err_unref;
 644
 645         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 646         if (ret)
 647                 goto err_unref;
 648
 649         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 650         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 651         if (ring->scratch.cpu_page == NULL) {
 652                 ret = -ENOMEM;
 653                 goto err_unpin;
 654         }
 655
 656         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 657                          ring->name, ring->scratch.gtt_offset);
 658         return 0;
 659
 660 err_unpin:
 661         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 662 err_unref:
 663         drm_gem_object_unreference(&ring->scratch.obj->base);
 664 err:
 665         return ret;
 666 }
 667
 668 static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
 669                                        u32 addr, u32 value)
 670 {
 671         struct drm_device *dev = ring->dev;
 672         struct drm_i915_private *dev_priv = dev->dev_private;
 673
 674         if (WARN_ON(dev_priv->num_wa_regs >= I915_MAX_WA_REGS))
 675                 return;
 676
 677         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 678         intel_ring_emit(ring, addr);
 679         intel_ring_emit(ring, value);
 680
 681         dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr;
 682         dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = value & 0xFFFF;
 683         /* value is updated with the status of remaining bits of this
 684          * register when it is read from debugfs file
 685          */
 686         dev_priv->intel_wa_regs[dev_priv->num_wa_regs].value = value;
 687         dev_priv->num_wa_regs++;
 688
 689         return;
 690 }
 691
 692 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 693 {
 694         int ret;
 695         struct drm_device *dev = ring->dev;
 696         struct drm_i915_private *dev_priv = dev->dev_private;
 697
 698         /*
 699          * workarounds applied in this fn are part of register state context,
 700          * they need to be re-initialized followed by gpu reset, suspend/resume,
 701          * module reload.
 702          */
 703         dev_priv->num_wa_regs = 0;
 704         memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
 705
 706         /*
 707          * update the number of dwords required based on the
 708          * actual number of workarounds applied
 709          */
 710         ret = intel_ring_begin(ring, 18);
 711         if (ret)
 712                 return ret;
 713
 714         /* WaDisablePartialInstShootdown:bdw */
 715         /* WaDisableThreadStallDopClockGating:bdw */
 716         /* FIXME: Unclear whether we really need this on production bdw. */
 717         intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
 718                            _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
 719                                              | STALL_DOP_GATING_DISABLE));
 720
 721         /* WaDisableDopClockGating:bdw May not be needed for production */
 722         intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
 723                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
 724
 725         intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
 726                            _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
 727
 728         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 729          * workaround for for a possible hang in the unlikely event a TLB
 730          * invalidation occurs during a PSD flush.
 731          */
 732         /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
 733         intel_ring_emit_wa(ring, HDC_CHICKEN0,
 734                            _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT |
 735                                               (IS_BDW_GT3(dev) ?
 736                                                HDC_FENCE_DEST_SLM_DISABLE : 0)
 737                                    ));
 738
 739         /* Wa4x4STCOptimizationDisable:bdw */
 740         intel_ring_emit_wa(ring, CACHE_MODE_1,
 741                            _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
 742
 743         /*
 744          * BSpec recommends 8x4 when MSAA is used,
 745          * however in practice 16x4 seems fastest.
 746          *
 747          * Note that PS/WM thread counts depend on the WIZ hashing
 748          * disable bit, which we don't touch here, but it's good
 749          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 750          */
 751         intel_ring_emit_wa(ring, GEN7_GT_MODE,
 752                            GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
 753
 754         intel_ring_advance(ring);
 755
 756         DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
 757                          dev_priv->num_wa_regs);
 758
 759         return 0;
 760 }
 761
 762 static int chv_init_workarounds(struct intel_engine_cs *ring)
 763 {
 764         int ret;
 765         struct drm_device *dev = ring->dev;
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767
 768         /*
 769          * workarounds applied in this fn are part of register state context,
 770          * they need to be re-initialized followed by gpu reset, suspend/resume,
 771          * module reload.
 772          */
 773         dev_priv->num_wa_regs = 0;
 774         memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
 775
 776         ret = intel_ring_begin(ring, 12);
 777         if (ret)
 778                 return ret;
 779
 780         /* WaDisablePartialInstShootdown:chv */
 781         intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
 782                            _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
 783
 784         /* WaDisableThreadStallDopClockGating:chv */
 785         intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
 786                            _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
 787
 788         /* WaDisableDopClockGating:chv (pre-production hw) */
 789         intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
 790                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
 791
 792         /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
 793         intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
 794                            _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
 795
 796         intel_ring_advance(ring);
 797
 798         return 0;
 799 }
 800
 801 static int init_render_ring(struct intel_engine_cs *ring)
 802 {
 803         struct drm_device *dev = ring->dev;
 804         struct drm_i915_private *dev_priv = dev->dev_private;
 805         int ret = init_ring_common(ring);
 806         if (ret)
 807                 return ret;
 808
 809         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 810         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
 811                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 812
 813         /* We need to disable the AsyncFlip performance optimisations in order
 814          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 815          * programmed to '1' on all products.
 816          *
 817          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
 818          */
 819         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
 820                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 821
 822         /* Required for the hardware to program scanline values for waiting */
 823         /* WaEnableFlushTlbInvalidationMode:snb */
 824         if (INTEL_INFO(dev)->gen == 6)
 825                 I915_WRITE(GFX_MODE,
 826                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 827
 828         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 829         if (IS_GEN7(dev))
 830                 I915_WRITE(GFX_MODE_GEN7,
 831                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 832                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 833
 834         if (INTEL_INFO(dev)->gen >= 5) {
 835                 ret = intel_init_pipe_control(ring);
 836                 if (ret)
 837                         return ret;
 838         }
 839
 840         if (IS_GEN6(dev)) {
 841                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 842                  * "If this bit is set, STCunit will have LRA as replacement
 843                  *  policy. [...] This bit must be reset.  LRA replacement
 844                  *  policy is not supported."
 845                  */
 846                 I915_WRITE(CACHE_MODE_0,
 847                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 848         }
 849
 850         if (INTEL_INFO(dev)->gen >= 6)
 851                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 852
 853         if (HAS_L3_DPF(dev))
 854                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 855
 856         return ret;
 857 }
 858
 859 static void render_ring_cleanup(struct intel_engine_cs *ring)
 860 {
 861         struct drm_device *dev = ring->dev;
 862         struct drm_i915_private *dev_priv = dev->dev_private;
 863
 864         if (dev_priv->semaphore_obj) {
 865                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
 866                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
 867                 dev_priv->semaphore_obj = NULL;
 868         }
 869
 870         intel_fini_pipe_control(ring);
 871 }
 872
 873 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
 874                            unsigned int num_dwords)
 875 {
 876 #define MBOX_UPDATE_DWORDS 8
 877         struct drm_device *dev = signaller->dev;
 878         struct drm_i915_private *dev_priv = dev->dev_private;
 879         struct intel_engine_cs *waiter;
 880         int i, ret, num_rings;
 881
 882         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 883         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 884 #undef MBOX_UPDATE_DWORDS
 885
 886         ret = intel_ring_begin(signaller, num_dwords);
 887         if (ret)
 888                 return ret;
 889
 890         for_each_ring(waiter, dev_priv, i) {
 891                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 892                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 893                         continue;
 894
 895                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
 896                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
 897                                            PIPE_CONTROL_QW_WRITE |
 898                                            PIPE_CONTROL_FLUSH_ENABLE);
 899                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
 900                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 901                 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
 902                 intel_ring_emit(signaller, 0);
 903                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 904                                            MI_SEMAPHORE_TARGET(waiter->id));
 905                 intel_ring_emit(signaller, 0);
 906         }
 907
 908         return 0;
 909 }
 910
 911 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
 912                            unsigned int num_dwords)
 913 {
 914 #define MBOX_UPDATE_DWORDS 6
 915         struct drm_device *dev = signaller->dev;
 916         struct drm_i915_private *dev_priv = dev->dev_private;
 917         struct intel_engine_cs *waiter;
 918         int i, ret, num_rings;
 919
 920         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 921         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 922 #undef MBOX_UPDATE_DWORDS
 923
 924         ret = intel_ring_begin(signaller, num_dwords);
 925         if (ret)
 926                 return ret;
 927
 928         for_each_ring(waiter, dev_priv, i) {
 929                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 930                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 931                         continue;
 932
 933                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
 934                                            MI_FLUSH_DW_OP_STOREDW);
 935                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
 936                                            MI_FLUSH_DW_USE_GTT);
 937                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 938                 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
 939                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 940                                            MI_SEMAPHORE_TARGET(waiter->id));
 941                 intel_ring_emit(signaller, 0);
 942         }
 943
 944         return 0;
 945 }
 946
 947 static int gen6_signal(struct intel_engine_cs *signaller,
 948                        unsigned int num_dwords)
 949 {
 950         struct drm_device *dev = signaller->dev;
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         struct intel_engine_cs *useless;
 953         int i, ret, num_rings;
 954
 955 #define MBOX_UPDATE_DWORDS 3
 956         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 957         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
 958 #undef MBOX_UPDATE_DWORDS
 959
 960         ret = intel_ring_begin(signaller, num_dwords);
 961         if (ret)
 962                 return ret;
 963
 964         for_each_ring(useless, dev_priv, i) {
 965                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
 966                 if (mbox_reg != GEN6_NOSYNC) {
 967                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
 968                         intel_ring_emit(signaller, mbox_reg);
 969                         intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
 970                 }
 971         }
 972
 973         /* If num_dwords was rounded, make sure the tail pointer is correct */
 974         if (num_rings % 2 == 0)
 975                 intel_ring_emit(signaller, MI_NOOP);
 976
 977         return 0;
 978 }
 979
 980 /**
 981  * gen6_add_request - Update the semaphore mailbox registers
 982  *
 983  * @ring - ring that is adding a request
 984  * @seqno - return seqno stuck into the ring
 985  *
 986  * Update the mailbox registers in the *other* rings with the current seqno.
 987  * This acts like a signal in the canonical semaphore.
 988  */
 989 static int
 990 gen6_add_request(struct intel_engine_cs *ring)
 991 {
 992         int ret;
 993
 994         if (ring->semaphore.signal)
 995                 ret = ring->semaphore.signal(ring, 4);
 996         else
 997                 ret = intel_ring_begin(ring, 4);
 998
 999         if (ret)
1000                 return ret;
1001
1002         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1003         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1004         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1005         intel_ring_emit(ring, MI_USER_INTERRUPT);
1006         __intel_ring_advance(ring);
1007
1008         return 0;
1009 }
1010
1011 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1012                                               u32 seqno)
1013 {
1014         struct drm_i915_private *dev_priv = dev->dev_private;
1015         return dev_priv->last_seqno < seqno;
1016 }
1017
1018 /**
1019  * intel_ring_sync - sync the waiter to the signaller on seqno
1020  *
1021  * @waiter - ring that is waiting
1022  * @signaller - ring which has, or will signal
1023  * @seqno - seqno which the waiter will block on
1024  */
1025
1026 static int
1027 gen8_ring_sync(struct intel_engine_cs *waiter,
1028                struct intel_engine_cs *signaller,
1029                u32 seqno)
1030 {
1031         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1032         int ret;
1033
1034         ret = intel_ring_begin(waiter, 4);
1035         if (ret)
1036                 return ret;
1037
1038         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1039                                 MI_SEMAPHORE_GLOBAL_GTT |
1040                                 MI_SEMAPHORE_POLL |
1041                                 MI_SEMAPHORE_SAD_GTE_SDD);
1042         intel_ring_emit(waiter, seqno);
1043         intel_ring_emit(waiter,
1044                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1045         intel_ring_emit(waiter,
1046                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1047         intel_ring_advance(waiter);
1048         return 0;
1049 }
1050
1051 static int
1052 gen6_ring_sync(struct intel_engine_cs *waiter,
1053                struct intel_engine_cs *signaller,
1054                u32 seqno)
1055 {
1056         u32 dw1 = MI_SEMAPHORE_MBOX |
1057                   MI_SEMAPHORE_COMPARE |
1058                   MI_SEMAPHORE_REGISTER;
1059         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1060         int ret;
1061
1062         /* Throughout all of the GEM code, seqno passed implies our current
1063          * seqno is >= the last seqno executed. However for hardware the
1064          * comparison is strictly greater than.
1065          */
1066         seqno -= 1;
1067
1068         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1069
1070         ret = intel_ring_begin(waiter, 4);
1071         if (ret)
1072                 return ret;
1073
1074         /* If seqno wrap happened, omit the wait with no-ops */
1075         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1076                 intel_ring_emit(waiter, dw1 | wait_mbox);
1077                 intel_ring_emit(waiter, seqno);
1078                 intel_ring_emit(waiter, 0);
1079                 intel_ring_emit(waiter, MI_NOOP);
1080         } else {
1081                 intel_ring_emit(waiter, MI_NOOP);
1082                 intel_ring_emit(waiter, MI_NOOP);
1083                 intel_ring_emit(waiter, MI_NOOP);
1084                 intel_ring_emit(waiter, MI_NOOP);
1085         }
1086         intel_ring_advance(waiter);
1087
1088         return 0;
1089 }
1090
1091 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1092 do {                                                                    \
1093         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1094                  PIPE_CONTROL_DEPTH_STALL);                             \
1095         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1096         intel_ring_emit(ring__, 0);                                                     \
1097         intel_ring_emit(ring__, 0);                                                     \
1098 } while (0)
1099
1100 static int
1101 pc_render_add_request(struct intel_engine_cs *ring)
1102 {
1103         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1104         int ret;
1105
1106         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1107          * incoherent with writes to memory, i.e. completely fubar,
1108          * so we need to use PIPE_NOTIFY instead.
1109          *
1110          * However, we also need to workaround the qword write
1111          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1112          * memory before requesting an interrupt.
1113          */
1114         ret = intel_ring_begin(ring, 32);
1115         if (ret)
1116                 return ret;
1117
1118         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1119                         PIPE_CONTROL_WRITE_FLUSH |
1120                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1121         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1122         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1123         intel_ring_emit(ring, 0);
1124         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1125         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1126         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1127         scratch_addr += 2 * CACHELINE_BYTES;
1128         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1129         scratch_addr += 2 * CACHELINE_BYTES;
1130         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1131         scratch_addr += 2 * CACHELINE_BYTES;
1132         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1133         scratch_addr += 2 * CACHELINE_BYTES;
1134         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1135
1136         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1137                         PIPE_CONTROL_WRITE_FLUSH |
1138                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1139                         PIPE_CONTROL_NOTIFY);
1140         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1141         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1142         intel_ring_emit(ring, 0);
1143         __intel_ring_advance(ring);
1144
1145         return 0;
1146 }
1147
1148 static u32
1149 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1150 {
1151         /* Workaround to force correct ordering between irq and seqno writes on
1152          * ivb (and maybe also on snb) by reading from a CS register (like
1153          * ACTHD) before reading the status page. */
1154         if (!lazy_coherency) {
1155                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1156                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1157         }
1158
1159         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1160 }
1161
1162 static u32
1163 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1164 {
1165         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1166 }
1167
1168 static void
1169 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1170 {
1171         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1172 }
1173
1174 static u32
1175 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1176 {
1177         return ring->scratch.cpu_page[0];
1178 }
1179
1180 static void
1181 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1182 {
1183         ring->scratch.cpu_page[0] = seqno;
1184 }
1185
1186 static bool
1187 gen5_ring_get_irq(struct intel_engine_cs *ring)
1188 {
1189         struct drm_device *dev = ring->dev;
1190         struct drm_i915_private *dev_priv = dev->dev_private;
1191         unsigned long flags;
1192
1193         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1194                 return false;
1195
1196         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1197         if (ring->irq_refcount++ == 0)
1198                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1199         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1200
1201         return true;
1202 }
1203
1204 static void
1205 gen5_ring_put_irq(struct intel_engine_cs *ring)
1206 {
1207         struct drm_device *dev = ring->dev;
1208         struct drm_i915_private *dev_priv = dev->dev_private;
1209         unsigned long flags;
1210
1211         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1212         if (--ring->irq_refcount == 0)
1213                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1214         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1215 }
1216
1217 static bool
1218 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1219 {
1220         struct drm_device *dev = ring->dev;
1221         struct drm_i915_private *dev_priv = dev->dev_private;
1222         unsigned long flags;
1223
1224         if (!intel_irqs_enabled(dev_priv))
1225                 return false;
1226
1227         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1228         if (ring->irq_refcount++ == 0) {
1229                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1230                 I915_WRITE(IMR, dev_priv->irq_mask);
1231                 POSTING_READ(IMR);
1232         }
1233         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1234
1235         return true;
1236 }
1237
1238 static void
1239 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1240 {
1241         struct drm_device *dev = ring->dev;
1242         struct drm_i915_private *dev_priv = dev->dev_private;
1243         unsigned long flags;
1244
1245         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1246         if (--ring->irq_refcount == 0) {
1247                 dev_priv->irq_mask |= ring->irq_enable_mask;
1248                 I915_WRITE(IMR, dev_priv->irq_mask);
1249                 POSTING_READ(IMR);
1250         }
1251         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1252 }
1253
1254 static bool
1255 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1256 {
1257         struct drm_device *dev = ring->dev;
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259         unsigned long flags;
1260
1261         if (!intel_irqs_enabled(dev_priv))
1262                 return false;
1263
1264         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1265         if (ring->irq_refcount++ == 0) {
1266                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1267                 I915_WRITE16(IMR, dev_priv->irq_mask);
1268                 POSTING_READ16(IMR);
1269         }
1270         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1271
1272         return true;
1273 }
1274
1275 static void
1276 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1277 {
1278         struct drm_device *dev = ring->dev;
1279         struct drm_i915_private *dev_priv = dev->dev_private;
1280         unsigned long flags;
1281
1282         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1283         if (--ring->irq_refcount == 0) {
1284                 dev_priv->irq_mask |= ring->irq_enable_mask;
1285                 I915_WRITE16(IMR, dev_priv->irq_mask);
1286                 POSTING_READ16(IMR);
1287         }
1288         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1289 }
1290
1291 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1292 {
1293         struct drm_device *dev = ring->dev;
1294         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1295         u32 mmio = 0;
1296
1297         /* The ring status page addresses are no longer next to the rest of
1298          * the ring registers as of gen7.
1299          */
1300         if (IS_GEN7(dev)) {
1301                 switch (ring->id) {
1302                 case RCS:
1303                         mmio = RENDER_HWS_PGA_GEN7;
1304                         break;
1305                 case BCS:
1306                         mmio = BLT_HWS_PGA_GEN7;
1307                         break;
1308                 /*
1309                  * VCS2 actually doesn't exist on Gen7. Only shut up
1310                  * gcc switch check warning
1311                  */
1312                 case VCS2:
1313                 case VCS:
1314                         mmio = BSD_HWS_PGA_GEN7;
1315                         break;
1316                 case VECS:
1317                         mmio = VEBOX_HWS_PGA_GEN7;
1318                         break;
1319                 }
1320         } else if (IS_GEN6(ring->dev)) {
1321                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1322         } else {
1323                 /* XXX: gen8 returns to sanity */
1324                 mmio = RING_HWS_PGA(ring->mmio_base);
1325         }
1326
1327         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1328         POSTING_READ(mmio);
1329
1330         /*
1331          * Flush the TLB for this page
1332          *
1333          * FIXME: These two bits have disappeared on gen8, so a question
1334          * arises: do we still need this and if so how should we go about
1335          * invalidating the TLB?
1336          */
1337         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1338                 u32 reg = RING_INSTPM(ring->mmio_base);
1339
1340                 /* ring should be idle before issuing a sync flush*/
1341                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1342
1343                 I915_WRITE(reg,
1344                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1345                                               INSTPM_SYNC_FLUSH));
1346                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1347                              1000))
1348                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1349                                   ring->name);
1350         }
1351 }
1352
1353 static int
1354 bsd_ring_flush(struct intel_engine_cs *ring,
1355                u32     invalidate_domains,
1356                u32     flush_domains)
1357 {
1358         int ret;
1359
1360         ret = intel_ring_begin(ring, 2);
1361         if (ret)
1362                 return ret;
1363
1364         intel_ring_emit(ring, MI_FLUSH);
1365         intel_ring_emit(ring, MI_NOOP);
1366         intel_ring_advance(ring);
1367         return 0;
1368 }
1369
1370 static int
1371 i9xx_add_request(struct intel_engine_cs *ring)
1372 {
1373         int ret;
1374
1375         ret = intel_ring_begin(ring, 4);
1376         if (ret)
1377                 return ret;
1378
1379         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1380         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1381         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1382         intel_ring_emit(ring, MI_USER_INTERRUPT);
1383         __intel_ring_advance(ring);
1384
1385         return 0;
1386 }
1387
1388 static bool
1389 gen6_ring_get_irq(struct intel_engine_cs *ring)
1390 {
1391         struct drm_device *dev = ring->dev;
1392         struct drm_i915_private *dev_priv = dev->dev_private;
1393         unsigned long flags;
1394
1395         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1396                 return false;
1397
1398         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1399         if (ring->irq_refcount++ == 0) {
1400                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1401                         I915_WRITE_IMR(ring,
1402                                        ~(ring->irq_enable_mask |
1403                                          GT_PARITY_ERROR(dev)));
1404                 else
1405                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1406                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1407         }
1408         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1409
1410         return true;
1411 }
1412
1413 static void
1414 gen6_ring_put_irq(struct intel_engine_cs *ring)
1415 {
1416         struct drm_device *dev = ring->dev;
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418         unsigned long flags;
1419
1420         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1421         if (--ring->irq_refcount == 0) {
1422                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1423                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1424                 else
1425                         I915_WRITE_IMR(ring, ~0);
1426                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1427         }
1428         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1429 }
1430
1431 static bool
1432 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1433 {
1434         struct drm_device *dev = ring->dev;
1435         struct drm_i915_private *dev_priv = dev->dev_private;
1436         unsigned long flags;
1437
1438         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1439                 return false;
1440
1441         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1442         if (ring->irq_refcount++ == 0) {
1443                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1444                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1445         }
1446         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1447
1448         return true;
1449 }
1450
1451 static void
1452 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1453 {
1454         struct drm_device *dev = ring->dev;
1455         struct drm_i915_private *dev_priv = dev->dev_private;
1456         unsigned long flags;
1457
1458         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1459         if (--ring->irq_refcount == 0) {
1460                 I915_WRITE_IMR(ring, ~0);
1461                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1462         }
1463         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1464 }
1465
1466 static bool
1467 gen8_ring_get_irq(struct intel_engine_cs *ring)
1468 {
1469         struct drm_device *dev = ring->dev;
1470         struct drm_i915_private *dev_priv = dev->dev_private;
1471         unsigned long flags;
1472
1473         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1474                 return false;
1475
1476         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1477         if (ring->irq_refcount++ == 0) {
1478                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1479                         I915_WRITE_IMR(ring,
1480                                        ~(ring->irq_enable_mask |
1481                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1482                 } else {
1483                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1484                 }
1485                 POSTING_READ(RING_IMR(ring->mmio_base));
1486         }
1487         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1488
1489         return true;
1490 }
1491
1492 static void
1493 gen8_ring_put_irq(struct intel_engine_cs *ring)
1494 {
1495         struct drm_device *dev = ring->dev;
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497         unsigned long flags;
1498
1499         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1500         if (--ring->irq_refcount == 0) {
1501                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1502                         I915_WRITE_IMR(ring,
1503                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1504                 } else {
1505                         I915_WRITE_IMR(ring, ~0);
1506                 }
1507                 POSTING_READ(RING_IMR(ring->mmio_base));
1508         }
1509         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1510 }
1511
1512 static int
1513 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1514                          u64 offset, u32 length,
1515                          unsigned flags)
1516 {
1517         int ret;
1518
1519         ret = intel_ring_begin(ring, 2);
1520         if (ret)
1521                 return ret;
1522
1523         intel_ring_emit(ring,
1524                         MI_BATCH_BUFFER_START |
1525                         MI_BATCH_GTT |
1526                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1527         intel_ring_emit(ring, offset);
1528         intel_ring_advance(ring);
1529
1530         return 0;
1531 }
1532
1533 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1534 #define I830_BATCH_LIMIT (256*1024)
1535 #define I830_TLB_ENTRIES (2)
1536 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1537 static int
1538 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1539                                 u64 offset, u32 len,
1540                                 unsigned flags)
1541 {
1542         u32 cs_offset = ring->scratch.gtt_offset;
1543         int ret;
1544
1545         ret = intel_ring_begin(ring, 6);
1546         if (ret)
1547                 return ret;
1548
1549         /* Evict the invalid PTE TLBs */
1550         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1551         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1552         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1553         intel_ring_emit(ring, cs_offset);
1554         intel_ring_emit(ring, 0xdeadbeef);
1555         intel_ring_emit(ring, MI_NOOP);
1556         intel_ring_advance(ring);
1557
1558         if ((flags & I915_DISPATCH_PINNED) == 0) {
1559                 if (len > I830_BATCH_LIMIT)
1560                         return -ENOSPC;
1561
1562                 ret = intel_ring_begin(ring, 6 + 2);
1563                 if (ret)
1564                         return ret;
1565
1566                 /* Blit the batch (which has now all relocs applied) to the
1567                  * stable batch scratch bo area (so that the CS never
1568                  * stumbles over its tlb invalidation bug) ...
1569                  */
1570                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1571                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1572                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1573                 intel_ring_emit(ring, cs_offset);
1574                 intel_ring_emit(ring, 4096);
1575                 intel_ring_emit(ring, offset);
1576
1577                 intel_ring_emit(ring, MI_FLUSH);
1578                 intel_ring_emit(ring, MI_NOOP);
1579                 intel_ring_advance(ring);
1580
1581                 /* ... and execute it. */
1582                 offset = cs_offset;
1583         }
1584
1585         ret = intel_ring_begin(ring, 4);
1586         if (ret)
1587                 return ret;
1588
1589         intel_ring_emit(ring, MI_BATCH_BUFFER);
1590         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1591         intel_ring_emit(ring, offset + len - 8);
1592         intel_ring_emit(ring, MI_NOOP);
1593         intel_ring_advance(ring);
1594
1595         return 0;
1596 }
1597
1598 static int
1599 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1600                          u64 offset, u32 len,
1601                          unsigned flags)
1602 {
1603         int ret;
1604
1605         ret = intel_ring_begin(ring, 2);
1606         if (ret)
1607                 return ret;
1608
1609         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1610         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1611         intel_ring_advance(ring);
1612
1613         return 0;
1614 }
1615
1616 static void cleanup_status_page(struct intel_engine_cs *ring)
1617 {
1618         struct drm_i915_gem_object *obj;
1619
1620         obj = ring->status_page.obj;
1621         if (obj == NULL)
1622                 return;
1623
1624         kunmap(sg_page(obj->pages->sgl));
1625         i915_gem_object_ggtt_unpin(obj);
1626         drm_gem_object_unreference(&obj->base);
1627         ring->status_page.obj = NULL;
1628 }
1629
1630 static int init_status_page(struct intel_engine_cs *ring)
1631 {
1632         struct drm_i915_gem_object *obj;
1633
1634         if ((obj = ring->status_page.obj) == NULL) {
1635                 unsigned flags;
1636                 int ret;
1637
1638                 obj = i915_gem_alloc_object(ring->dev, 4096);
1639                 if (obj == NULL) {
1640                         DRM_ERROR("Failed to allocate status page\n");
1641                         return -ENOMEM;
1642                 }
1643
1644                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1645                 if (ret)
1646                         goto err_unref;
1647
1648                 flags = 0;
1649                 if (!HAS_LLC(ring->dev))
1650                         /* On g33, we cannot place HWS above 256MiB, so
1651                          * restrict its pinning to the low mappable arena.
1652                          * Though this restriction is not documented for
1653                          * gen4, gen5, or byt, they also behave similarly
1654                          * and hang if the HWS is placed at the top of the
1655                          * GTT. To generalise, it appears that all !llc
1656                          * platforms have issues with us placing the HWS
1657                          * above the mappable region (even though we never
1658                          * actualy map it).
1659                          */
1660                         flags |= PIN_MAPPABLE;
1661                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1662                 if (ret) {
1663 err_unref:
1664                         drm_gem_object_unreference(&obj->base);
1665                         return ret;
1666                 }
1667
1668                 ring->status_page.obj = obj;
1669         }
1670
1671         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1672         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1673         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1674
1675         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1676                         ring->name, ring->status_page.gfx_addr);
1677
1678         return 0;
1679 }
1680
1681 static int init_phys_status_page(struct intel_engine_cs *ring)
1682 {
1683         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1684
1685         if (!dev_priv->status_page_dmah) {
1686                 dev_priv->status_page_dmah =
1687                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1688                 if (!dev_priv->status_page_dmah)
1689                         return -ENOMEM;
1690         }
1691
1692         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1693         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1694
1695         return 0;
1696 }
1697
1698 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1699 {
1700         if (!ringbuf->obj)
1701                 return;
1702
1703         iounmap(ringbuf->virtual_start);
1704         i915_gem_object_ggtt_unpin(ringbuf->obj);
1705         drm_gem_object_unreference(&ringbuf->obj->base);
1706         ringbuf->obj = NULL;
1707 }
1708
1709 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1710                                struct intel_ringbuffer *ringbuf)
1711 {
1712         struct drm_i915_private *dev_priv = to_i915(dev);
1713         struct drm_i915_gem_object *obj;
1714         int ret;
1715
1716         if (ringbuf->obj)
1717                 return 0;
1718
1719         obj = NULL;
1720         if (!HAS_LLC(dev))
1721                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1722         if (obj == NULL)
1723                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1724         if (obj == NULL)
1725                 return -ENOMEM;
1726
1727         /* mark ring buffers as read-only from GPU side by default */
1728         obj->gt_ro = 1;
1729
1730         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1731         if (ret)
1732                 goto err_unref;
1733
1734         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1735         if (ret)
1736                 goto err_unpin;
1737
1738         ringbuf->virtual_start =
1739                 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1740                                 ringbuf->size);
1741         if (ringbuf->virtual_start == NULL) {
1742                 ret = -EINVAL;
1743                 goto err_unpin;
1744         }
1745
1746         ringbuf->obj = obj;
1747         return 0;
1748
1749 err_unpin:
1750         i915_gem_object_ggtt_unpin(obj);
1751 err_unref:
1752         drm_gem_object_unreference(&obj->base);
1753         return ret;
1754 }
1755
1756 static int intel_init_ring_buffer(struct drm_device *dev,
1757                                   struct intel_engine_cs *ring)
1758 {
1759         struct intel_ringbuffer *ringbuf = ring->buffer;
1760         int ret;
1761
1762         if (ringbuf == NULL) {
1763                 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1764                 if (!ringbuf)
1765                         return -ENOMEM;
1766                 ring->buffer = ringbuf;
1767         }
1768
1769         ring->dev = dev;
1770         INIT_LIST_HEAD(&ring->active_list);
1771         INIT_LIST_HEAD(&ring->request_list);
1772         INIT_LIST_HEAD(&ring->execlist_queue);
1773         ringbuf->size = 32 * PAGE_SIZE;
1774         ringbuf->ring = ring;
1775         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1776
1777         init_waitqueue_head(&ring->irq_queue);
1778
1779         if (I915_NEED_GFX_HWS(dev)) {
1780                 ret = init_status_page(ring);
1781                 if (ret)
1782                         goto error;
1783         } else {
1784                 BUG_ON(ring->id != RCS);
1785                 ret = init_phys_status_page(ring);
1786                 if (ret)
1787                         goto error;
1788         }
1789
1790         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1791         if (ret) {
1792                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1793                 goto error;
1794         }
1795
1796         /* Workaround an erratum on the i830 which causes a hang if
1797          * the TAIL pointer points to within the last 2 cachelines
1798          * of the buffer.
1799          */
1800         ringbuf->effective_size = ringbuf->size;
1801         if (IS_I830(dev) || IS_845G(dev))
1802                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1803
1804         ret = i915_cmd_parser_init_ring(ring);
1805         if (ret)
1806                 goto error;
1807
1808         ret = ring->init(ring);
1809         if (ret)
1810                 goto error;
1811
1812         return 0;
1813
1814 error:
1815         kfree(ringbuf);
1816         ring->buffer = NULL;
1817         return ret;
1818 }
1819
1820 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1821 {
1822         struct drm_i915_private *dev_priv = to_i915(ring->dev);
1823         struct intel_ringbuffer *ringbuf = ring->buffer;
1824
1825         if (!intel_ring_initialized(ring))
1826                 return;
1827
1828         intel_stop_ring_buffer(ring);
1829         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1830
1831         intel_destroy_ringbuffer_obj(ringbuf);
1832         ring->preallocated_lazy_request = NULL;
1833         ring->outstanding_lazy_seqno = 0;
1834
1835         if (ring->cleanup)
1836                 ring->cleanup(ring);
1837
1838         cleanup_status_page(ring);
1839
1840         i915_cmd_parser_fini_ring(ring);
1841
1842         kfree(ringbuf);
1843         ring->buffer = NULL;
1844 }
1845
1846 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1847 {
1848         struct intel_ringbuffer *ringbuf = ring->buffer;
1849         struct drm_i915_gem_request *request;
1850         u32 seqno = 0;
1851         int ret;
1852
1853         if (ringbuf->last_retired_head != -1) {
1854                 ringbuf->head = ringbuf->last_retired_head;
1855                 ringbuf->last_retired_head = -1;
1856
1857                 ringbuf->space = intel_ring_space(ringbuf);
1858                 if (ringbuf->space >= n)
1859                         return 0;
1860         }
1861
1862         list_for_each_entry(request, &ring->request_list, list) {
1863                 if (__intel_ring_space(request->tail, ringbuf->tail,
1864                                        ringbuf->size) >= n) {
1865                         seqno = request->seqno;
1866                         break;
1867                 }
1868         }
1869
1870         if (seqno == 0)
1871                 return -ENOSPC;
1872
1873         ret = i915_wait_seqno(ring, seqno);
1874         if (ret)
1875                 return ret;
1876
1877         i915_gem_retire_requests_ring(ring);
1878         ringbuf->head = ringbuf->last_retired_head;
1879         ringbuf->last_retired_head = -1;
1880
1881         ringbuf->space = intel_ring_space(ringbuf);
1882         return 0;
1883 }
1884
1885 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1886 {
1887         struct drm_device *dev = ring->dev;
1888         struct drm_i915_private *dev_priv = dev->dev_private;
1889         struct intel_ringbuffer *ringbuf = ring->buffer;
1890         unsigned long end;
1891         int ret;
1892
1893         ret = intel_ring_wait_request(ring, n);
1894         if (ret != -ENOSPC)
1895                 return ret;
1896
1897         /* force the tail write in case we have been skipping them */
1898         __intel_ring_advance(ring);
1899
1900         /* With GEM the hangcheck timer should kick us out of the loop,
1901          * leaving it early runs the risk of corrupting GEM state (due
1902          * to running on almost untested codepaths). But on resume
1903          * timers don't work yet, so prevent a complete hang in that
1904          * case by choosing an insanely large timeout. */
1905         end = jiffies + 60 * HZ;
1906
1907         trace_i915_ring_wait_begin(ring);
1908         do {
1909                 ringbuf->head = I915_READ_HEAD(ring);
1910                 ringbuf->space = intel_ring_space(ringbuf);
1911                 if (ringbuf->space >= n) {
1912                         ret = 0;
1913                         break;
1914                 }
1915
1916                 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1917                     dev->primary->master) {
1918                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1919                         if (master_priv->sarea_priv)
1920                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1921                 }
1922
1923                 msleep(1);
1924
1925                 if (dev_priv->mm.interruptible && signal_pending(current)) {
1926                         ret = -ERESTARTSYS;
1927                         break;
1928                 }
1929
1930                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1931                                            dev_priv->mm.interruptible);
1932                 if (ret)
1933                         break;
1934
1935                 if (time_after(jiffies, end)) {
1936                         ret = -EBUSY;
1937                         break;
1938                 }
1939         } while (1);
1940         trace_i915_ring_wait_end(ring);
1941         return ret;
1942 }
1943
1944 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
1945 {
1946         uint32_t __iomem *virt;
1947         struct intel_ringbuffer *ringbuf = ring->buffer;
1948         int rem = ringbuf->size - ringbuf->tail;
1949
1950         if (ringbuf->space < rem) {
1951                 int ret = ring_wait_for_space(ring, rem);
1952                 if (ret)
1953                         return ret;
1954         }
1955
1956         virt = ringbuf->virtual_start + ringbuf->tail;
1957         rem /= 4;
1958         while (rem--)
1959                 iowrite32(MI_NOOP, virt++);
1960
1961         ringbuf->tail = 0;
1962         ringbuf->space = intel_ring_space(ringbuf);
1963
1964         return 0;
1965 }
1966
1967 int intel_ring_idle(struct intel_engine_cs *ring)
1968 {
1969         u32 seqno;
1970         int ret;
1971
1972         /* We need to add any requests required to flush the objects and ring */
1973         if (ring->outstanding_lazy_seqno) {
1974                 ret = i915_add_request(ring, NULL);
1975                 if (ret)
1976                         return ret;
1977         }
1978
1979         /* Wait upon the last request to be completed */
1980         if (list_empty(&ring->request_list))
1981                 return 0;
1982
1983         seqno = list_entry(ring->request_list.prev,
1984                            struct drm_i915_gem_request,
1985                            list)->seqno;
1986
1987         return i915_wait_seqno(ring, seqno);
1988 }
1989
1990 static int
1991 intel_ring_alloc_seqno(struct intel_engine_cs *ring)
1992 {
1993         if (ring->outstanding_lazy_seqno)
1994                 return 0;
1995
1996         if (ring->preallocated_lazy_request == NULL) {
1997                 struct drm_i915_gem_request *request;
1998
1999                 request = kmalloc(sizeof(*request), GFP_KERNEL);
2000                 if (request == NULL)
2001                         return -ENOMEM;
2002
2003                 ring->preallocated_lazy_request = request;
2004         }
2005
2006         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
2007 }
2008
2009 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2010                                 int bytes)
2011 {
2012         struct intel_ringbuffer *ringbuf = ring->buffer;
2013         int ret;
2014
2015         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2016                 ret = intel_wrap_ring_buffer(ring);
2017                 if (unlikely(ret))
2018                         return ret;
2019         }
2020
2021         if (unlikely(ringbuf->space < bytes)) {
2022                 ret = ring_wait_for_space(ring, bytes);
2023                 if (unlikely(ret))
2024                         return ret;
2025         }
2026
2027         return 0;
2028 }
2029
2030 int intel_ring_begin(struct intel_engine_cs *ring,
2031                      int num_dwords)
2032 {
2033         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2034         int ret;
2035
2036         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2037                                    dev_priv->mm.interruptible);
2038         if (ret)
2039                 return ret;
2040
2041         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2042         if (ret)
2043                 return ret;
2044
2045         /* Preallocate the olr before touching the ring */
2046         ret = intel_ring_alloc_seqno(ring);
2047         if (ret)
2048                 return ret;
2049
2050         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2051         return 0;
2052 }
2053
2054 /* Align the ring tail to a cacheline boundary */
2055 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2056 {
2057         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2058         int ret;
2059
2060         if (num_dwords == 0)
2061                 return 0;
2062
2063         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2064         ret = intel_ring_begin(ring, num_dwords);
2065         if (ret)
2066                 return ret;
2067
2068         while (num_dwords--)
2069                 intel_ring_emit(ring, MI_NOOP);
2070
2071         intel_ring_advance(ring);
2072
2073         return 0;
2074 }
2075
2076 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2077 {
2078         struct drm_device *dev = ring->dev;
2079         struct drm_i915_private *dev_priv = dev->dev_private;
2080
2081         BUG_ON(ring->outstanding_lazy_seqno);
2082
2083         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2084                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2085                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2086                 if (HAS_VEBOX(dev))
2087                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2088         }
2089
2090         ring->set_seqno(ring, seqno);
2091         ring->hangcheck.seqno = seqno;
2092 }
2093
2094 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2095                                      u32 value)
2096 {
2097         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2098
2099        /* Every tail move must follow the sequence below */
2100
2101         /* Disable notification that the ring is IDLE. The GT
2102          * will then assume that it is busy and bring it out of rc6.
2103          */
2104         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2105                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2106
2107         /* Clear the context id. Here be magic! */
2108         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2109
2110         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2111         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2112                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2113                      50))
2114                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2115
2116         /* Now that the ring is fully powered up, update the tail */
2117         I915_WRITE_TAIL(ring, value);
2118         POSTING_READ(RING_TAIL(ring->mmio_base));
2119
2120         /* Let the ring send IDLE messages to the GT again,
2121          * and so let it sleep to conserve power when idle.
2122          */
2123         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2124                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2125 }
2126
2127 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2128                                u32 invalidate, u32 flush)
2129 {
2130         uint32_t cmd;
2131         int ret;
2132
2133         ret = intel_ring_begin(ring, 4);
2134         if (ret)
2135                 return ret;
2136
2137         cmd = MI_FLUSH_DW;
2138         if (INTEL_INFO(ring->dev)->gen >= 8)
2139                 cmd += 1;
2140         /*
2141          * Bspec vol 1c.5 - video engine command streamer:
2142          * "If ENABLED, all TLBs will be invalidated once the flush
2143          * operation is complete. This bit is only valid when the
2144          * Post-Sync Operation field is a value of 1h or 3h."
2145          */
2146         if (invalidate & I915_GEM_GPU_DOMAINS)
2147                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2148                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2149         intel_ring_emit(ring, cmd);
2150         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2151         if (INTEL_INFO(ring->dev)->gen >= 8) {
2152                 intel_ring_emit(ring, 0); /* upper addr */
2153                 intel_ring_emit(ring, 0); /* value */
2154         } else  {
2155                 intel_ring_emit(ring, 0);
2156                 intel_ring_emit(ring, MI_NOOP);
2157         }
2158         intel_ring_advance(ring);
2159         return 0;
2160 }
2161
2162 static int
2163 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2164                               u64 offset, u32 len,
2165                               unsigned flags)
2166 {
2167         bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2168         int ret;
2169
2170         ret = intel_ring_begin(ring, 4);
2171         if (ret)
2172                 return ret;
2173
2174         /* FIXME(BDW): Address space and security selectors. */
2175         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2176         intel_ring_emit(ring, lower_32_bits(offset));
2177         intel_ring_emit(ring, upper_32_bits(offset));
2178         intel_ring_emit(ring, MI_NOOP);
2179         intel_ring_advance(ring);
2180
2181         return 0;
2182 }
2183
2184 static int
2185 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2186                               u64 offset, u32 len,
2187                               unsigned flags)
2188 {
2189         int ret;
2190
2191         ret = intel_ring_begin(ring, 2);
2192         if (ret)
2193                 return ret;
2194
2195         intel_ring_emit(ring,
2196                         MI_BATCH_BUFFER_START |
2197                         (flags & I915_DISPATCH_SECURE ?
2198                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2199         /* bit0-7 is the length on GEN6+ */
2200         intel_ring_emit(ring, offset);
2201         intel_ring_advance(ring);
2202
2203         return 0;
2204 }
2205
2206 static int
2207 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2208                               u64 offset, u32 len,
2209                               unsigned flags)
2210 {
2211         int ret;
2212
2213         ret = intel_ring_begin(ring, 2);
2214         if (ret)
2215                 return ret;
2216
2217         intel_ring_emit(ring,
2218                         MI_BATCH_BUFFER_START |
2219                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2220         /* bit0-7 is the length on GEN6+ */
2221         intel_ring_emit(ring, offset);
2222         intel_ring_advance(ring);
2223
2224         return 0;
2225 }
2226
2227 /* Blitter support (SandyBridge+) */
2228
2229 static int gen6_ring_flush(struct intel_engine_cs *ring,
2230                            u32 invalidate, u32 flush)
2231 {
2232         struct drm_device *dev = ring->dev;
2233         struct drm_i915_private *dev_priv = dev->dev_private;
2234         uint32_t cmd;
2235         int ret;
2236
2237         ret = intel_ring_begin(ring, 4);
2238         if (ret)
2239                 return ret;
2240
2241         cmd = MI_FLUSH_DW;
2242         if (INTEL_INFO(ring->dev)->gen >= 8)
2243                 cmd += 1;
2244         /*
2245          * Bspec vol 1c.3 - blitter engine command streamer:
2246          * "If ENABLED, all TLBs will be invalidated once the flush
2247          * operation is complete. This bit is only valid when the
2248          * Post-Sync Operation field is a value of 1h or 3h."
2249          */
2250         if (invalidate & I915_GEM_DOMAIN_RENDER)
2251                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2252                         MI_FLUSH_DW_OP_STOREDW;
2253         intel_ring_emit(ring, cmd);
2254         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2255         if (INTEL_INFO(ring->dev)->gen >= 8) {
2256                 intel_ring_emit(ring, 0); /* upper addr */
2257                 intel_ring_emit(ring, 0); /* value */
2258         } else  {
2259                 intel_ring_emit(ring, 0);
2260                 intel_ring_emit(ring, MI_NOOP);
2261         }
2262         intel_ring_advance(ring);
2263
2264         if (!invalidate && flush) {
2265                 if (IS_GEN7(dev))
2266                         return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2267                 else if (IS_BROADWELL(dev))
2268                         dev_priv->fbc.need_sw_cache_clean = true;
2269         }
2270
2271         return 0;
2272 }
2273
2274 int intel_init_render_ring_buffer(struct drm_device *dev)
2275 {
2276         struct drm_i915_private *dev_priv = dev->dev_private;
2277         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2278         struct drm_i915_gem_object *obj;
2279         int ret;
2280
2281         ring->name = "render ring";
2282         ring->id = RCS;
2283         ring->mmio_base = RENDER_RING_BASE;
2284
2285         if (INTEL_INFO(dev)->gen >= 8) {
2286                 if (i915_semaphore_is_enabled(dev)) {
2287                         obj = i915_gem_alloc_object(dev, 4096);
2288                         if (obj == NULL) {
2289                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2290                                 i915.semaphores = 0;
2291                         } else {
2292                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2293                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2294                                 if (ret != 0) {
2295                                         drm_gem_object_unreference(&obj->base);
2296                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2297                                         i915.semaphores = 0;
2298                                 } else
2299                                         dev_priv->semaphore_obj = obj;
2300                         }
2301                 }
2302                 if (IS_CHERRYVIEW(dev))
2303                         ring->init_context = chv_init_workarounds;
2304                 else
2305                         ring->init_context = bdw_init_workarounds;
2306                 ring->add_request = gen6_add_request;
2307                 ring->flush = gen8_render_ring_flush;
2308                 ring->irq_get = gen8_ring_get_irq;
2309                 ring->irq_put = gen8_ring_put_irq;
2310                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2311                 ring->get_seqno = gen6_ring_get_seqno;
2312                 ring->set_seqno = ring_set_seqno;
2313                 if (i915_semaphore_is_enabled(dev)) {
2314                         WARN_ON(!dev_priv->semaphore_obj);
2315                         ring->semaphore.sync_to = gen8_ring_sync;
2316                         ring->semaphore.signal = gen8_rcs_signal;
2317                         GEN8_RING_SEMAPHORE_INIT;
2318                 }
2319         } else if (INTEL_INFO(dev)->gen >= 6) {
2320                 ring->add_request = gen6_add_request;
2321                 ring->flush = gen7_render_ring_flush;
2322                 if (INTEL_INFO(dev)->gen == 6)
2323                         ring->flush = gen6_render_ring_flush;
2324                 ring->irq_get = gen6_ring_get_irq;
2325                 ring->irq_put = gen6_ring_put_irq;
2326                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2327                 ring->get_seqno = gen6_ring_get_seqno;
2328                 ring->set_seqno = ring_set_seqno;
2329                 if (i915_semaphore_is_enabled(dev)) {
2330                         ring->semaphore.sync_to = gen6_ring_sync;
2331                         ring->semaphore.signal = gen6_signal;
2332                         /*
2333                          * The current semaphore is only applied on pre-gen8
2334                          * platform.  And there is no VCS2 ring on the pre-gen8
2335                          * platform. So the semaphore between RCS and VCS2 is
2336                          * initialized as INVALID.  Gen8 will initialize the
2337                          * sema between VCS2 and RCS later.
2338                          */
2339                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2340                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2341                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2342                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2343                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2344                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2345                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2346                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2347                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2348                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2349                 }
2350         } else if (IS_GEN5(dev)) {
2351                 ring->add_request = pc_render_add_request;
2352                 ring->flush = gen4_render_ring_flush;
2353                 ring->get_seqno = pc_render_get_seqno;
2354                 ring->set_seqno = pc_render_set_seqno;
2355                 ring->irq_get = gen5_ring_get_irq;
2356                 ring->irq_put = gen5_ring_put_irq;
2357                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2358                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2359         } else {
2360                 ring->add_request = i9xx_add_request;
2361                 if (INTEL_INFO(dev)->gen < 4)
2362                         ring->flush = gen2_render_ring_flush;
2363                 else
2364                         ring->flush = gen4_render_ring_flush;
2365                 ring->get_seqno = ring_get_seqno;
2366                 ring->set_seqno = ring_set_seqno;
2367                 if (IS_GEN2(dev)) {
2368                         ring->irq_get = i8xx_ring_get_irq;
2369                         ring->irq_put = i8xx_ring_put_irq;
2370                 } else {
2371                         ring->irq_get = i9xx_ring_get_irq;
2372                         ring->irq_put = i9xx_ring_put_irq;
2373                 }
2374                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2375         }
2376         ring->write_tail = ring_write_tail;
2377
2378         if (IS_HASWELL(dev))
2379                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2380         else if (IS_GEN8(dev))
2381                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2382         else if (INTEL_INFO(dev)->gen >= 6)
2383                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2384         else if (INTEL_INFO(dev)->gen >= 4)
2385                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2386         else if (IS_I830(dev) || IS_845G(dev))
2387                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2388         else
2389                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2390         ring->init = init_render_ring;
2391         ring->cleanup = render_ring_cleanup;
2392
2393         /* Workaround batchbuffer to combat CS tlb bug. */
2394         if (HAS_BROKEN_CS_TLB(dev)) {
2395                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2396                 if (obj == NULL) {
2397                         DRM_ERROR("Failed to allocate batch bo\n");
2398                         return -ENOMEM;
2399                 }
2400
2401                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2402                 if (ret != 0) {
2403                         drm_gem_object_unreference(&obj->base);
2404                         DRM_ERROR("Failed to ping batch bo\n");
2405                         return ret;
2406                 }
2407
2408                 ring->scratch.obj = obj;
2409                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2410         }
2411
2412         return intel_init_ring_buffer(dev, ring);
2413 }
2414
2415 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2416 {
2417         struct drm_i915_private *dev_priv = dev->dev_private;
2418         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2419         struct intel_ringbuffer *ringbuf = ring->buffer;
2420         int ret;
2421
2422         if (ringbuf == NULL) {
2423                 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2424                 if (!ringbuf)
2425                         return -ENOMEM;
2426                 ring->buffer = ringbuf;
2427         }
2428
2429         ring->name = "render ring";
2430         ring->id = RCS;
2431         ring->mmio_base = RENDER_RING_BASE;
2432
2433         if (INTEL_INFO(dev)->gen >= 6) {
2434                 /* non-kms not supported on gen6+ */
2435                 ret = -ENODEV;
2436                 goto err_ringbuf;
2437         }
2438
2439         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2440          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2441          * the special gen5 functions. */
2442         ring->add_request = i9xx_add_request;
2443         if (INTEL_INFO(dev)->gen < 4)
2444                 ring->flush = gen2_render_ring_flush;
2445         else
2446                 ring->flush = gen4_render_ring_flush;
2447         ring->get_seqno = ring_get_seqno;
2448         ring->set_seqno = ring_set_seqno;
2449         if (IS_GEN2(dev)) {
2450                 ring->irq_get = i8xx_ring_get_irq;
2451                 ring->irq_put = i8xx_ring_put_irq;
2452         } else {
2453                 ring->irq_get = i9xx_ring_get_irq;
2454                 ring->irq_put = i9xx_ring_put_irq;
2455         }
2456         ring->irq_enable_mask = I915_USER_INTERRUPT;
2457         ring->write_tail = ring_write_tail;
2458         if (INTEL_INFO(dev)->gen >= 4)
2459                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2460         else if (IS_I830(dev) || IS_845G(dev))
2461                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2462         else
2463                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2464         ring->init = init_render_ring;
2465         ring->cleanup = render_ring_cleanup;
2466
2467         ring->dev = dev;
2468         INIT_LIST_HEAD(&ring->active_list);
2469         INIT_LIST_HEAD(&ring->request_list);
2470
2471         ringbuf->size = size;
2472         ringbuf->effective_size = ringbuf->size;
2473         if (IS_I830(ring->dev) || IS_845G(ring->dev))
2474                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2475
2476         ringbuf->virtual_start = ioremap_wc(start, size);
2477         if (ringbuf->virtual_start == NULL) {
2478                 DRM_ERROR("can not ioremap virtual address for"
2479                           " ring buffer\n");
2480                 ret = -ENOMEM;
2481                 goto err_ringbuf;
2482         }
2483
2484         if (!I915_NEED_GFX_HWS(dev)) {
2485                 ret = init_phys_status_page(ring);
2486                 if (ret)
2487                         goto err_vstart;
2488         }
2489
2490         return 0;
2491
2492 err_vstart:
2493         iounmap(ringbuf->virtual_start);
2494 err_ringbuf:
2495         kfree(ringbuf);
2496         ring->buffer = NULL;
2497         return ret;
2498 }
2499
2500 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2501 {
2502         struct drm_i915_private *dev_priv = dev->dev_private;
2503         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2504
2505         ring->name = "bsd ring";
2506         ring->id = VCS;
2507
2508         ring->write_tail = ring_write_tail;
2509         if (INTEL_INFO(dev)->gen >= 6) {
2510                 ring->mmio_base = GEN6_BSD_RING_BASE;
2511                 /* gen6 bsd needs a special wa for tail updates */
2512                 if (IS_GEN6(dev))
2513                         ring->write_tail = gen6_bsd_ring_write_tail;
2514                 ring->flush = gen6_bsd_ring_flush;
2515                 ring->add_request = gen6_add_request;
2516                 ring->get_seqno = gen6_ring_get_seqno;
2517                 ring->set_seqno = ring_set_seqno;
2518                 if (INTEL_INFO(dev)->gen >= 8) {
2519                         ring->irq_enable_mask =
2520                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2521                         ring->irq_get = gen8_ring_get_irq;
2522                         ring->irq_put = gen8_ring_put_irq;
2523                         ring->dispatch_execbuffer =
2524                                 gen8_ring_dispatch_execbuffer;
2525                         if (i915_semaphore_is_enabled(dev)) {
2526                                 ring->semaphore.sync_to = gen8_ring_sync;
2527                                 ring->semaphore.signal = gen8_xcs_signal;
2528                                 GEN8_RING_SEMAPHORE_INIT;
2529                         }
2530                 } else {
2531                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2532                         ring->irq_get = gen6_ring_get_irq;
2533                         ring->irq_put = gen6_ring_put_irq;
2534                         ring->dispatch_execbuffer =
2535                                 gen6_ring_dispatch_execbuffer;
2536                         if (i915_semaphore_is_enabled(dev)) {
2537                                 ring->semaphore.sync_to = gen6_ring_sync;
2538                                 ring->semaphore.signal = gen6_signal;
2539                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2540                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2541                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2542                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2543                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2544                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2545                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2546                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2547                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2548                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2549                         }
2550                 }
2551         } else {
2552                 ring->mmio_base = BSD_RING_BASE;
2553                 ring->flush = bsd_ring_flush;
2554                 ring->add_request = i9xx_add_request;
2555                 ring->get_seqno = ring_get_seqno;
2556                 ring->set_seqno = ring_set_seqno;
2557                 if (IS_GEN5(dev)) {
2558                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2559                         ring->irq_get = gen5_ring_get_irq;
2560                         ring->irq_put = gen5_ring_put_irq;
2561                 } else {
2562                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2563                         ring->irq_get = i9xx_ring_get_irq;
2564                         ring->irq_put = i9xx_ring_put_irq;
2565                 }
2566                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2567         }
2568         ring->init = init_ring_common;
2569
2570         return intel_init_ring_buffer(dev, ring);
2571 }
2572
2573 /**
2574  * Initialize the second BSD ring for Broadwell GT3.
2575  * It is noted that this only exists on Broadwell GT3.
2576  */
2577 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2578 {
2579         struct drm_i915_private *dev_priv = dev->dev_private;
2580         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2581
2582         if ((INTEL_INFO(dev)->gen != 8)) {
2583                 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2584                 return -EINVAL;
2585         }
2586
2587         ring->name = "bsd2 ring";
2588         ring->id = VCS2;
2589
2590         ring->write_tail = ring_write_tail;
2591         ring->mmio_base = GEN8_BSD2_RING_BASE;
2592         ring->flush = gen6_bsd_ring_flush;
2593         ring->add_request = gen6_add_request;
2594         ring->get_seqno = gen6_ring_get_seqno;
2595         ring->set_seqno = ring_set_seqno;
2596         ring->irq_enable_mask =
2597                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2598         ring->irq_get = gen8_ring_get_irq;
2599         ring->irq_put = gen8_ring_put_irq;
2600         ring->dispatch_execbuffer =
2601                         gen8_ring_dispatch_execbuffer;
2602         if (i915_semaphore_is_enabled(dev)) {
2603                 ring->semaphore.sync_to = gen8_ring_sync;
2604                 ring->semaphore.signal = gen8_xcs_signal;
2605                 GEN8_RING_SEMAPHORE_INIT;
2606         }
2607         ring->init = init_ring_common;
2608
2609         return intel_init_ring_buffer(dev, ring);
2610 }
2611
2612 int intel_init_blt_ring_buffer(struct drm_device *dev)
2613 {
2614         struct drm_i915_private *dev_priv = dev->dev_private;
2615         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2616
2617         ring->name = "blitter ring";
2618         ring->id = BCS;
2619
2620         ring->mmio_base = BLT_RING_BASE;
2621         ring->write_tail = ring_write_tail;
2622         ring->flush = gen6_ring_flush;
2623         ring->add_request = gen6_add_request;
2624         ring->get_seqno = gen6_ring_get_seqno;
2625         ring->set_seqno = ring_set_seqno;
2626         if (INTEL_INFO(dev)->gen >= 8) {
2627                 ring->irq_enable_mask =
2628                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2629                 ring->irq_get = gen8_ring_get_irq;
2630                 ring->irq_put = gen8_ring_put_irq;
2631                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2632                 if (i915_semaphore_is_enabled(dev)) {
2633                         ring->semaphore.sync_to = gen8_ring_sync;
2634                         ring->semaphore.signal = gen8_xcs_signal;
2635                         GEN8_RING_SEMAPHORE_INIT;
2636                 }
2637         } else {
2638                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2639                 ring->irq_get = gen6_ring_get_irq;
2640                 ring->irq_put = gen6_ring_put_irq;
2641                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2642                 if (i915_semaphore_is_enabled(dev)) {
2643                         ring->semaphore.signal = gen6_signal;
2644                         ring->semaphore.sync_to = gen6_ring_sync;
2645                         /*
2646                          * The current semaphore is only applied on pre-gen8
2647                          * platform.  And there is no VCS2 ring on the pre-gen8
2648                          * platform. So the semaphore between BCS and VCS2 is
2649                          * initialized as INVALID.  Gen8 will initialize the
2650                          * sema between BCS and VCS2 later.
2651                          */
2652                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2653                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2654                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2655                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2656                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2657                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2658                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2659                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2660                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2661                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2662                 }
2663         }
2664         ring->init = init_ring_common;
2665
2666         return intel_init_ring_buffer(dev, ring);
2667 }
2668
2669 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2670 {
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2673
2674         ring->name = "video enhancement ring";
2675         ring->id = VECS;
2676
2677         ring->mmio_base = VEBOX_RING_BASE;
2678         ring->write_tail = ring_write_tail;
2679         ring->flush = gen6_ring_flush;
2680         ring->add_request = gen6_add_request;
2681         ring->get_seqno = gen6_ring_get_seqno;
2682         ring->set_seqno = ring_set_seqno;
2683
2684         if (INTEL_INFO(dev)->gen >= 8) {
2685                 ring->irq_enable_mask =
2686                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2687                 ring->irq_get = gen8_ring_get_irq;
2688                 ring->irq_put = gen8_ring_put_irq;
2689                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2690                 if (i915_semaphore_is_enabled(dev)) {
2691                         ring->semaphore.sync_to = gen8_ring_sync;
2692                         ring->semaphore.signal = gen8_xcs_signal;
2693                         GEN8_RING_SEMAPHORE_INIT;
2694                 }
2695         } else {
2696                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2697                 ring->irq_get = hsw_vebox_get_irq;
2698                 ring->irq_put = hsw_vebox_put_irq;
2699                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2700                 if (i915_semaphore_is_enabled(dev)) {
2701                         ring->semaphore.sync_to = gen6_ring_sync;
2702                         ring->semaphore.signal = gen6_signal;
2703                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2704                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2705                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2706                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2707                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2708                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2709                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2710                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2711                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2712                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2713                 }
2714         }
2715         ring->init = init_ring_common;
2716
2717         return intel_init_ring_buffer(dev, ring);
2718 }
2719
2720 int
2721 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2722 {
2723         int ret;
2724
2725         if (!ring->gpu_caches_dirty)
2726                 return 0;
2727
2728         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2729         if (ret)
2730                 return ret;
2731
2732         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2733
2734         ring->gpu_caches_dirty = false;
2735         return 0;
2736 }
2737
2738 int
2739 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2740 {
2741         uint32_t flush_domains;
2742         int ret;
2743
2744         flush_domains = 0;
2745         if (ring->gpu_caches_dirty)
2746                 flush_domains = I915_GEM_GPU_DOMAINS;
2747
2748         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2749         if (ret)
2750                 return ret;
2751
2752         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2753
2754         ring->gpu_caches_dirty = false;
2755         return 0;
2756 }
2757
2758 void
2759 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2760 {
2761         int ret;
2762
2763         if (!intel_ring_initialized(ring))
2764                 return;
2765
2766         ret = intel_ring_idle(ring);
2767         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2768                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2769                           ring->name, ret);
2770
2771         stop_ring(ring);
2772 }