drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct intel_engine_cs *ring,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         u32 cmd;
  99         int ret;
 100
 101         cmd = MI_FLUSH;
 102         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 103                 cmd |= MI_NO_WRITE_FLUSH;
 104
 105         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                 cmd |= MI_READ_FLUSH;
 107
 108         ret = intel_ring_begin(ring, 2);
 109         if (ret)
 110                 return ret;
 111
 112         intel_ring_emit(ring, cmd);
 113         intel_ring_emit(ring, MI_NOOP);
 114         intel_ring_advance(ring);
 115
 116         return 0;
 117 }
 118
 119 static int
 120 gen4_render_ring_flush(struct intel_engine_cs *ring,
 121                        u32      invalidate_domains,
 122                        u32      flush_domains)
 123 {
 124         struct drm_device *dev = ring->dev;
 125         u32 cmd;
 126         int ret;
 127
 128         /*
 129          * read/write caches:
 130          *
 131          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 132          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 133          * also flushed at 2d versus 3d pipeline switches.
 134          *
 135          * read-only caches:
 136          *
 137          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 138          * MI_READ_FLUSH is set, and is always flushed on 965.
 139          *
 140          * I915_GEM_DOMAIN_COMMAND may not exist?
 141          *
 142          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 143          * invalidated when MI_EXE_FLUSH is set.
 144          *
 145          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 146          * invalidated with every MI_FLUSH.
 147          *
 148          * TLBs:
 149          *
 150          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 151          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 152          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 153          * are flushed at any MI_FLUSH.
 154          */
 155
 156         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 157         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 158                 cmd &= ~MI_NO_WRITE_FLUSH;
 159         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 160                 cmd |= MI_EXE_FLUSH;
 161
 162         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 163             (IS_G4X(dev) || IS_GEN5(dev)))
 164                 cmd |= MI_INVALIDATE_ISP;
 165
 166         ret = intel_ring_begin(ring, 2);
 167         if (ret)
 168                 return ret;
 169
 170         intel_ring_emit(ring, cmd);
 171         intel_ring_emit(ring, MI_NOOP);
 172         intel_ring_advance(ring);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 179  * implementing two workarounds on gen6.  From section 1.4.7.1
 180  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 181  *
 182  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 183  * produced by non-pipelined state commands), software needs to first
 184  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 185  * 0.
 186  *
 187  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 188  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 189  *
 190  * And the workaround for these two requires this workaround first:
 191  *
 192  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 193  * BEFORE the pipe-control with a post-sync op and no write-cache
 194  * flushes.
 195  *
 196  * And this last workaround is tricky because of the requirements on
 197  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 198  * volume 2 part 1:
 199  *
 200  *     "1 of the following must also be set:
 201  *      - Render Target Cache Flush Enable ([12] of DW1)
 202  *      - Depth Cache Flush Enable ([0] of DW1)
 203  *      - Stall at Pixel Scoreboard ([1] of DW1)
 204  *      - Depth Stall ([13] of DW1)
 205  *      - Post-Sync Operation ([13] of DW1)
 206  *      - Notify Enable ([8] of DW1)"
 207  *
 208  * The cache flushes require the workaround flush that triggered this
 209  * one, so we can't use it.  Depth stall would trigger the same.
 210  * Post-sync nonzero is what triggered this second workaround, so we
 211  * can't use that one either.  Notify enable is IRQs, which aren't
 212  * really our business.  That leaves only stall at scoreboard.
 213  */
 214 static int
 215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 216 {
 217         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 218         int ret;
 219
 220
 221         ret = intel_ring_begin(ring, 6);
 222         if (ret)
 223                 return ret;
 224
 225         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 226         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 227                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 228         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 229         intel_ring_emit(ring, 0); /* low dword */
 230         intel_ring_emit(ring, 0); /* high dword */
 231         intel_ring_emit(ring, MI_NOOP);
 232         intel_ring_advance(ring);
 233
 234         ret = intel_ring_begin(ring, 6);
 235         if (ret)
 236                 return ret;
 237
 238         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 239         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 240         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 241         intel_ring_emit(ring, 0);
 242         intel_ring_emit(ring, 0);
 243         intel_ring_emit(ring, MI_NOOP);
 244         intel_ring_advance(ring);
 245
 246         return 0;
 247 }
 248
 249 static int
 250 gen6_render_ring_flush(struct intel_engine_cs *ring,
 251                          u32 invalidate_domains, u32 flush_domains)
 252 {
 253         u32 flags = 0;
 254         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 255         int ret;
 256
 257         /* Force SNB workarounds for PIPE_CONTROL flushes */
 258         ret = intel_emit_post_sync_nonzero_flush(ring);
 259         if (ret)
 260                 return ret;
 261
 262         /* Just flush everything.  Experiments have shown that reducing the
 263          * number of bits based on the write domains has little performance
 264          * impact.
 265          */
 266         if (flush_domains) {
 267                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 268                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 269                 /*
 270                  * Ensure that any following seqno writes only happen
 271                  * when the render cache is indeed flushed.
 272                  */
 273                 flags |= PIPE_CONTROL_CS_STALL;
 274         }
 275         if (invalidate_domains) {
 276                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 277                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 278                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 279                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 280                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 282                 /*
 283                  * TLB invalidate requires a post-sync write.
 284                  */
 285                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 286         }
 287
 288         ret = intel_ring_begin(ring, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(ring, flags);
 294         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 295         intel_ring_emit(ring, 0);
 296         intel_ring_advance(ring);
 297
 298         return 0;
 299 }
 300
 301 static int
 302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 303 {
 304         int ret;
 305
 306         ret = intel_ring_begin(ring, 4);
 307         if (ret)
 308                 return ret;
 309
 310         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 311         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 312                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 313         intel_ring_emit(ring, 0);
 314         intel_ring_emit(ring, 0);
 315         intel_ring_advance(ring);
 316
 317         return 0;
 318 }
 319
 320 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
 321 {
 322         int ret;
 323
 324         if (!ring->fbc_dirty)
 325                 return 0;
 326
 327         ret = intel_ring_begin(ring, 6);
 328         if (ret)
 329                 return ret;
 330         /* WaFbcNukeOn3DBlt:ivb/hsw */
 331         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 332         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 333         intel_ring_emit(ring, value);
 334         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 335         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 336         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 337         intel_ring_advance(ring);
 338
 339         ring->fbc_dirty = false;
 340         return 0;
 341 }
 342
 343 static int
 344 gen7_render_ring_flush(struct intel_engine_cs *ring,
 345                        u32 invalidate_domains, u32 flush_domains)
 346 {
 347         u32 flags = 0;
 348         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 349         int ret;
 350
 351         /*
 352          * Ensure that any following seqno writes only happen when the render
 353          * cache is indeed flushed.
 354          *
 355          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 356          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 357          * don't try to be clever and just set it unconditionally.
 358          */
 359         flags |= PIPE_CONTROL_CS_STALL;
 360
 361         /* Just flush everything.  Experiments have shown that reducing the
 362          * number of bits based on the write domains has little performance
 363          * impact.
 364          */
 365         if (flush_domains) {
 366                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 367                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 368         }
 369         if (invalidate_domains) {
 370                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 371                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 372                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 373                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 374                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 375                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 376                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 377                 /*
 378                  * TLB invalidate requires a post-sync write.
 379                  */
 380                 flags |= PIPE_CONTROL_QW_WRITE;
 381                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 382
 383                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 384
 385                 /* Workaround: we must issue a pipe_control with CS-stall bit
 386                  * set before a pipe_control command that has the state cache
 387                  * invalidate bit set. */
 388                 gen7_render_ring_cs_stall_wa(ring);
 389         }
 390
 391         ret = intel_ring_begin(ring, 4);
 392         if (ret)
 393                 return ret;
 394
 395         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 396         intel_ring_emit(ring, flags);
 397         intel_ring_emit(ring, scratch_addr);
 398         intel_ring_emit(ring, 0);
 399         intel_ring_advance(ring);
 400
 401         if (!invalidate_domains && flush_domains)
 402                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 403
 404         return 0;
 405 }
 406
 407 static int
 408 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 409                        u32 flags, u32 scratch_addr)
 410 {
 411         int ret;
 412
 413         ret = intel_ring_begin(ring, 6);
 414         if (ret)
 415                 return ret;
 416
 417         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 418         intel_ring_emit(ring, flags);
 419         intel_ring_emit(ring, scratch_addr);
 420         intel_ring_emit(ring, 0);
 421         intel_ring_emit(ring, 0);
 422         intel_ring_emit(ring, 0);
 423         intel_ring_advance(ring);
 424
 425         return 0;
 426 }
 427
 428 static int
 429 gen8_render_ring_flush(struct intel_engine_cs *ring,
 430                        u32 invalidate_domains, u32 flush_domains)
 431 {
 432         u32 flags = 0;
 433         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 434         int ret;
 435
 436         flags |= PIPE_CONTROL_CS_STALL;
 437
 438         if (flush_domains) {
 439                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 440                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 441         }
 442         if (invalidate_domains) {
 443                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 444                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 445                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 446                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 447                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 448                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 449                 flags |= PIPE_CONTROL_QW_WRITE;
 450                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 451
 452                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 453                 ret = gen8_emit_pipe_control(ring,
 454                                              PIPE_CONTROL_CS_STALL |
 455                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 456                                              0);
 457                 if (ret)
 458                         return ret;
 459         }
 460
 461         ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
 462         if (ret)
 463                 return ret;
 464
 465         if (!invalidate_domains && flush_domains)
 466                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 467
 468         return 0;
 469 }
 470
 471 static void ring_write_tail(struct intel_engine_cs *ring,
 472                             u32 value)
 473 {
 474         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 475         I915_WRITE_TAIL(ring, value);
 476 }
 477
 478 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 479 {
 480         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 481         u64 acthd;
 482
 483         if (INTEL_INFO(ring->dev)->gen >= 8)
 484                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 485                                          RING_ACTHD_UDW(ring->mmio_base));
 486         else if (INTEL_INFO(ring->dev)->gen >= 4)
 487                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 488         else
 489                 acthd = I915_READ(ACTHD);
 490
 491         return acthd;
 492 }
 493
 494 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 495 {
 496         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 497         u32 addr;
 498
 499         addr = dev_priv->status_page_dmah->busaddr;
 500         if (INTEL_INFO(ring->dev)->gen >= 4)
 501                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 502         I915_WRITE(HWS_PGA, addr);
 503 }
 504
 505 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 506 {
 507         struct drm_device *dev = ring->dev;
 508         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 509         u32 mmio = 0;
 510
 511         /* The ring status page addresses are no longer next to the rest of
 512          * the ring registers as of gen7.
 513          */
 514         if (IS_GEN7(dev)) {
 515                 switch (ring->id) {
 516                 case RCS:
 517                         mmio = RENDER_HWS_PGA_GEN7;
 518                         break;
 519                 case BCS:
 520                         mmio = BLT_HWS_PGA_GEN7;
 521                         break;
 522                 /*
 523                  * VCS2 actually doesn't exist on Gen7. Only shut up
 524                  * gcc switch check warning
 525                  */
 526                 case VCS2:
 527                 case VCS:
 528                         mmio = BSD_HWS_PGA_GEN7;
 529                         break;
 530                 case VECS:
 531                         mmio = VEBOX_HWS_PGA_GEN7;
 532                         break;
 533                 }
 534         } else if (IS_GEN6(ring->dev)) {
 535                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 536         } else {
 537                 /* XXX: gen8 returns to sanity */
 538                 mmio = RING_HWS_PGA(ring->mmio_base);
 539         }
 540
 541         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 542         POSTING_READ(mmio);
 543
 544         /*
 545          * Flush the TLB for this page
 546          *
 547          * FIXME: These two bits have disappeared on gen8, so a question
 548          * arises: do we still need this and if so how should we go about
 549          * invalidating the TLB?
 550          */
 551         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 552                 u32 reg = RING_INSTPM(ring->mmio_base);
 553
 554                 /* ring should be idle before issuing a sync flush*/
 555                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 556
 557                 I915_WRITE(reg,
 558                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 559                                               INSTPM_SYNC_FLUSH));
 560                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 561                              1000))
 562                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 563                                   ring->name);
 564         }
 565 }
 566
 567 static bool stop_ring(struct intel_engine_cs *ring)
 568 {
 569         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 570
 571         if (!IS_GEN2(ring->dev)) {
 572                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 573                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 574                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 575                         /* Sometimes we observe that the idle flag is not
 576                          * set even though the ring is empty. So double
 577                          * check before giving up.
 578                          */
 579                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 580                                 return false;
 581                 }
 582         }
 583
 584         I915_WRITE_CTL(ring, 0);
 585         I915_WRITE_HEAD(ring, 0);
 586         ring->write_tail(ring, 0);
 587
 588         if (!IS_GEN2(ring->dev)) {
 589                 (void)I915_READ_CTL(ring);
 590                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 591         }
 592
 593         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 594 }
 595
 596 static int init_ring_common(struct intel_engine_cs *ring)
 597 {
 598         struct drm_device *dev = ring->dev;
 599         struct drm_i915_private *dev_priv = dev->dev_private;
 600         struct intel_ringbuffer *ringbuf = ring->buffer;
 601         struct drm_i915_gem_object *obj = ringbuf->obj;
 602         int ret = 0;
 603
 604         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 605
 606         if (!stop_ring(ring)) {
 607                 /* G45 ring initialization often fails to reset head to zero */
 608                 DRM_DEBUG_KMS("%s head not reset to zero "
 609                               "ctl %08x head %08x tail %08x start %08x\n",
 610                               ring->name,
 611                               I915_READ_CTL(ring),
 612                               I915_READ_HEAD(ring),
 613                               I915_READ_TAIL(ring),
 614                               I915_READ_START(ring));
 615
 616                 if (!stop_ring(ring)) {
 617                         DRM_ERROR("failed to set %s head to zero "
 618                                   "ctl %08x head %08x tail %08x start %08x\n",
 619                                   ring->name,
 620                                   I915_READ_CTL(ring),
 621                                   I915_READ_HEAD(ring),
 622                                   I915_READ_TAIL(ring),
 623                                   I915_READ_START(ring));
 624                         ret = -EIO;
 625                         goto out;
 626                 }
 627         }
 628
 629         if (I915_NEED_GFX_HWS(dev))
 630                 intel_ring_setup_status_page(ring);
 631         else
 632                 ring_setup_phys_status_page(ring);
 633
 634         /* Enforce ordering by reading HEAD register back */
 635         I915_READ_HEAD(ring);
 636
 637         /* Initialize the ring. This must happen _after_ we've cleared the ring
 638          * registers with the above sequence (the readback of the HEAD registers
 639          * also enforces ordering), otherwise the hw might lose the new ring
 640          * register values. */
 641         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 642
 643         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 644         if (I915_READ_HEAD(ring))
 645                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 646                           ring->name, I915_READ_HEAD(ring));
 647         I915_WRITE_HEAD(ring, 0);
 648         (void)I915_READ_HEAD(ring);
 649
 650         I915_WRITE_CTL(ring,
 651                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 652                         | RING_VALID);
 653
 654         /* If the head is still not zero, the ring is dead */
 655         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 656                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 657                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 658                 DRM_ERROR("%s initialization failed "
 659                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 660                           ring->name,
 661                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 662                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 663                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 664                 ret = -EIO;
 665                 goto out;
 666         }
 667
 668         ringbuf->last_retired_head = -1;
 669         ringbuf->head = I915_READ_HEAD(ring);
 670         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 671         intel_ring_update_space(ringbuf);
 672
 673         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 674
 675 out:
 676         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 677
 678         return ret;
 679 }
 680
 681 void
 682 intel_fini_pipe_control(struct intel_engine_cs *ring)
 683 {
 684         struct drm_device *dev = ring->dev;
 685
 686         if (ring->scratch.obj == NULL)
 687                 return;
 688
 689         if (INTEL_INFO(dev)->gen >= 5) {
 690                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 691                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 692         }
 693
 694         drm_gem_object_unreference(&ring->scratch.obj->base);
 695         ring->scratch.obj = NULL;
 696 }
 697
 698 int
 699 intel_init_pipe_control(struct intel_engine_cs *ring)
 700 {
 701         int ret;
 702
 703         WARN_ON(ring->scratch.obj);
 704
 705         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 706         if (ring->scratch.obj == NULL) {
 707                 DRM_ERROR("Failed to allocate seqno page\n");
 708                 ret = -ENOMEM;
 709                 goto err;
 710         }
 711
 712         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 713         if (ret)
 714                 goto err_unref;
 715
 716         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 717         if (ret)
 718                 goto err_unref;
 719
 720         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 721         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 722         if (ring->scratch.cpu_page == NULL) {
 723                 ret = -ENOMEM;
 724                 goto err_unpin;
 725         }
 726
 727         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 728                          ring->name, ring->scratch.gtt_offset);
 729         return 0;
 730
 731 err_unpin:
 732         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 733 err_unref:
 734         drm_gem_object_unreference(&ring->scratch.obj->base);
 735 err:
 736         return ret;
 737 }
 738
 739 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
 740                                        struct intel_context *ctx)
 741 {
 742         int ret, i;
 743         struct drm_device *dev = ring->dev;
 744         struct drm_i915_private *dev_priv = dev->dev_private;
 745         struct i915_workarounds *w = &dev_priv->workarounds;
 746
 747         if (WARN_ON_ONCE(w->count == 0))
 748                 return 0;
 749
 750         ring->gpu_caches_dirty = true;
 751         ret = intel_ring_flush_all_caches(ring);
 752         if (ret)
 753                 return ret;
 754
 755         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 756         if (ret)
 757                 return ret;
 758
 759         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 760         for (i = 0; i < w->count; i++) {
 761                 intel_ring_emit(ring, w->reg[i].addr);
 762                 intel_ring_emit(ring, w->reg[i].value);
 763         }
 764         intel_ring_emit(ring, MI_NOOP);
 765
 766         intel_ring_advance(ring);
 767
 768         ring->gpu_caches_dirty = true;
 769         ret = intel_ring_flush_all_caches(ring);
 770         if (ret)
 771                 return ret;
 772
 773         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 774
 775         return 0;
 776 }
 777
 778 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
 779                               struct intel_context *ctx)
 780 {
 781         int ret;
 782
 783         ret = intel_ring_workarounds_emit(ring, ctx);
 784         if (ret != 0)
 785                 return ret;
 786
 787         ret = i915_gem_render_state_init(ring);
 788         if (ret)
 789                 DRM_ERROR("init render state: %d\n", ret);
 790
 791         return ret;
 792 }
 793
 794 static int wa_add(struct drm_i915_private *dev_priv,
 795                   const u32 addr, const u32 mask, const u32 val)
 796 {
 797         const u32 idx = dev_priv->workarounds.count;
 798
 799         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 800                 return -ENOSPC;
 801
 802         dev_priv->workarounds.reg[idx].addr = addr;
 803         dev_priv->workarounds.reg[idx].value = val;
 804         dev_priv->workarounds.reg[idx].mask = mask;
 805
 806         dev_priv->workarounds.count++;
 807
 808         return 0;
 809 }
 810
 811 #define WA_REG(addr, mask, val) { \
 812                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 813                 if (r) \
 814                         return r; \
 815         }
 816
 817 #define WA_SET_BIT_MASKED(addr, mask) \
 818         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 819
 820 #define WA_CLR_BIT_MASKED(addr, mask) \
 821         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 822
 823 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 824         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 825
 826 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 827 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 828
 829 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 830
 831 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 832 {
 833         struct drm_device *dev = ring->dev;
 834         struct drm_i915_private *dev_priv = dev->dev_private;
 835
 836         /* WaDisablePartialInstShootdown:bdw */
 837         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 838         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 839                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 840                           STALL_DOP_GATING_DISABLE);
 841
 842         /* WaDisableDopClockGating:bdw */
 843         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 844                           DOP_CLOCK_GATING_DISABLE);
 845
 846         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 847                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 848
 849         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 850          * workaround for for a possible hang in the unlikely event a TLB
 851          * invalidation occurs during a PSD flush.
 852          */
 853         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 854                           /* WaForceEnableNonCoherent:bdw */
 855                           HDC_FORCE_NON_COHERENT |
 856                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 857                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 858                           /* WaHdcDisableFetchWhenMasked:bdw */
 859                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 860                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 861                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 862
 863         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 864          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 865          *  polygons in the same 8x4 pixel/sample area to be processed without
 866          *  stalling waiting for the earlier ones to write to Hierarchical Z
 867          *  buffer."
 868          *
 869          * This optimization is off by default for Broadwell; turn it on.
 870          */
 871         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 872
 873         /* Wa4x4STCOptimizationDisable:bdw */
 874         WA_SET_BIT_MASKED(CACHE_MODE_1,
 875                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 876
 877         /*
 878          * BSpec recommends 8x4 when MSAA is used,
 879          * however in practice 16x4 seems fastest.
 880          *
 881          * Note that PS/WM thread counts depend on the WIZ hashing
 882          * disable bit, which we don't touch here, but it's good
 883          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 884          */
 885         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 886                             GEN6_WIZ_HASHING_MASK,
 887                             GEN6_WIZ_HASHING_16x4);
 888
 889         return 0;
 890 }
 891
 892 static int chv_init_workarounds(struct intel_engine_cs *ring)
 893 {
 894         struct drm_device *dev = ring->dev;
 895         struct drm_i915_private *dev_priv = dev->dev_private;
 896
 897         /* WaDisablePartialInstShootdown:chv */
 898         /* WaDisableThreadStallDopClockGating:chv */
 899         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 900                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 901                           STALL_DOP_GATING_DISABLE);
 902
 903         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 904          * workaround for a possible hang in the unlikely event a TLB
 905          * invalidation occurs during a PSD flush.
 906          */
 907         /* WaForceEnableNonCoherent:chv */
 908         /* WaHdcDisableFetchWhenMasked:chv */
 909         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 910                           HDC_FORCE_NON_COHERENT |
 911                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 912
 913         /* According to the CACHE_MODE_0 default value documentation, some
 914          * CHV platforms disable this optimization by default.  Turn it on.
 915          */
 916         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 917
 918         /* Wa4x4STCOptimizationDisable:chv */
 919         WA_SET_BIT_MASKED(CACHE_MODE_1,
 920                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 921
 922         /* Improve HiZ throughput on CHV. */
 923         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 924
 925         /*
 926          * BSpec recommends 8x4 when MSAA is used,
 927          * however in practice 16x4 seems fastest.
 928          *
 929          * Note that PS/WM thread counts depend on the WIZ hashing
 930          * disable bit, which we don't touch here, but it's good
 931          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 932          */
 933         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 934                             GEN6_WIZ_HASHING_MASK,
 935                             GEN6_WIZ_HASHING_16x4);
 936
 937         if (INTEL_REVID(dev) == SKL_REVID_C0 ||
 938             INTEL_REVID(dev) == SKL_REVID_D0)
 939                 /* WaBarrierPerformanceFixDisable:skl */
 940                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
 941                                   HDC_FENCE_DEST_SLM_DISABLE |
 942                                   HDC_BARRIER_PERFORMANCE_DISABLE);
 943
 944         return 0;
 945 }
 946
 947 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 948 {
 949         struct drm_device *dev = ring->dev;
 950         struct drm_i915_private *dev_priv = dev->dev_private;
 951
 952         /* WaDisablePartialInstShootdown:skl */
 953         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 954                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 955
 956         /* Syncing dependencies between camera and graphics */
 957         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 958                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 959
 960         if (INTEL_REVID(dev) == SKL_REVID_A0 ||
 961             INTEL_REVID(dev) == SKL_REVID_B0) {
 962                 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
 963                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 964                                   GEN9_DG_MIRROR_FIX_ENABLE);
 965         }
 966
 967         if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
 968                 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
 969                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 970                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 971                 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
 972                                   DISABLE_PIXEL_MASK_CAMMING);
 973         }
 974
 975         if (INTEL_REVID(dev) >= SKL_REVID_C0) {
 976                 /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
 977                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 978                                   GEN9_ENABLE_YV12_BUGFIX);
 979         }
 980
 981         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
 982                 /*
 983                  *Use Force Non-Coherent whenever executing a 3D context. This
 984                  * is a workaround for a possible hang in the unlikely event
 985                  * a TLB invalidation occurs during a PSD flush.
 986                  */
 987                 /* WaForceEnableNonCoherent:skl */
 988                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
 989                                   HDC_FORCE_NON_COHERENT);
 990         }
 991
 992         /* Wa4x4STCOptimizationDisable:skl */
 993         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 994
 995         /* WaDisablePartialResolveInVc:skl */
 996         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 997
 998         /* WaCcsTlbPrefetchDisable:skl */
 999         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
1000                           GEN9_CCS_TLB_PREFETCH_ENABLE);
1001
1002         return 0;
1003 }
1004
1005 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
1006 {
1007         struct drm_device *dev = ring->dev;
1008         struct drm_i915_private *dev_priv = dev->dev_private;
1009         u8 vals[3] = { 0, 0, 0 };
1010         unsigned int i;
1011
1012         for (i = 0; i < 3; i++) {
1013                 u8 ss;
1014
1015                 /*
1016                  * Only consider slices where one, and only one, subslice has 7
1017                  * EUs
1018                  */
1019                 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1020                         continue;
1021
1022                 /*
1023                  * subslice_7eu[i] != 0 (because of the check above) and
1024                  * ss_max == 4 (maximum number of subslices possible per slice)
1025                  *
1026                  * ->    0 <= ss <= 3;
1027                  */
1028                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1029                 vals[i] = 3 - ss;
1030         }
1031
1032         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1033                 return 0;
1034
1035         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1036         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1037                             GEN9_IZ_HASHING_MASK(2) |
1038                             GEN9_IZ_HASHING_MASK(1) |
1039                             GEN9_IZ_HASHING_MASK(0),
1040                             GEN9_IZ_HASHING(2, vals[2]) |
1041                             GEN9_IZ_HASHING(1, vals[1]) |
1042                             GEN9_IZ_HASHING(0, vals[0]));
1043
1044         return 0;
1045 }
1046
1047
1048 static int skl_init_workarounds(struct intel_engine_cs *ring)
1049 {
1050         struct drm_device *dev = ring->dev;
1051         struct drm_i915_private *dev_priv = dev->dev_private;
1052
1053         gen9_init_workarounds(ring);
1054
1055         /* WaDisablePowerCompilerClockGating:skl */
1056         if (INTEL_REVID(dev) == SKL_REVID_B0)
1057                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1058                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1059
1060         return skl_tune_iz_hashing(ring);
1061 }
1062
1063 int init_workarounds_ring(struct intel_engine_cs *ring)
1064 {
1065         struct drm_device *dev = ring->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067
1068         WARN_ON(ring->id != RCS);
1069
1070         dev_priv->workarounds.count = 0;
1071
1072         if (IS_BROADWELL(dev))
1073                 return bdw_init_workarounds(ring);
1074
1075         if (IS_CHERRYVIEW(dev))
1076                 return chv_init_workarounds(ring);
1077
1078         if (IS_SKYLAKE(dev))
1079                 return skl_init_workarounds(ring);
1080         else if (IS_GEN9(dev))
1081                 return gen9_init_workarounds(ring);
1082
1083         return 0;
1084 }
1085
1086 static int init_render_ring(struct intel_engine_cs *ring)
1087 {
1088         struct drm_device *dev = ring->dev;
1089         struct drm_i915_private *dev_priv = dev->dev_private;
1090         int ret = init_ring_common(ring);
1091         if (ret)
1092                 return ret;
1093
1094         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1095         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1096                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1097
1098         /* We need to disable the AsyncFlip performance optimisations in order
1099          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1100          * programmed to '1' on all products.
1101          *
1102          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1103          */
1104         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1105                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1106
1107         /* Required for the hardware to program scanline values for waiting */
1108         /* WaEnableFlushTlbInvalidationMode:snb */
1109         if (INTEL_INFO(dev)->gen == 6)
1110                 I915_WRITE(GFX_MODE,
1111                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1112
1113         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1114         if (IS_GEN7(dev))
1115                 I915_WRITE(GFX_MODE_GEN7,
1116                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1117                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1118
1119         if (IS_GEN6(dev)) {
1120                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1121                  * "If this bit is set, STCunit will have LRA as replacement
1122                  *  policy. [...] This bit must be reset.  LRA replacement
1123                  *  policy is not supported."
1124                  */
1125                 I915_WRITE(CACHE_MODE_0,
1126                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1127         }
1128
1129         if (INTEL_INFO(dev)->gen >= 6)
1130                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1131
1132         if (HAS_L3_DPF(dev))
1133                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1134
1135         return init_workarounds_ring(ring);
1136 }
1137
1138 static void render_ring_cleanup(struct intel_engine_cs *ring)
1139 {
1140         struct drm_device *dev = ring->dev;
1141         struct drm_i915_private *dev_priv = dev->dev_private;
1142
1143         if (dev_priv->semaphore_obj) {
1144                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1145                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1146                 dev_priv->semaphore_obj = NULL;
1147         }
1148
1149         intel_fini_pipe_control(ring);
1150 }
1151
1152 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1153                            unsigned int num_dwords)
1154 {
1155 #define MBOX_UPDATE_DWORDS 8
1156         struct drm_device *dev = signaller->dev;
1157         struct drm_i915_private *dev_priv = dev->dev_private;
1158         struct intel_engine_cs *waiter;
1159         int i, ret, num_rings;
1160
1161         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1162         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1163 #undef MBOX_UPDATE_DWORDS
1164
1165         ret = intel_ring_begin(signaller, num_dwords);
1166         if (ret)
1167                 return ret;
1168
1169         for_each_ring(waiter, dev_priv, i) {
1170                 u32 seqno;
1171                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1172                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1173                         continue;
1174
1175                 seqno = i915_gem_request_get_seqno(
1176                                            signaller->outstanding_lazy_request);
1177                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1178                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1179                                            PIPE_CONTROL_QW_WRITE |
1180                                            PIPE_CONTROL_FLUSH_ENABLE);
1181                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1182                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1183                 intel_ring_emit(signaller, seqno);
1184                 intel_ring_emit(signaller, 0);
1185                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1186                                            MI_SEMAPHORE_TARGET(waiter->id));
1187                 intel_ring_emit(signaller, 0);
1188         }
1189
1190         return 0;
1191 }
1192
1193 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1194                            unsigned int num_dwords)
1195 {
1196 #define MBOX_UPDATE_DWORDS 6
1197         struct drm_device *dev = signaller->dev;
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         struct intel_engine_cs *waiter;
1200         int i, ret, num_rings;
1201
1202         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1203         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1204 #undef MBOX_UPDATE_DWORDS
1205
1206         ret = intel_ring_begin(signaller, num_dwords);
1207         if (ret)
1208                 return ret;
1209
1210         for_each_ring(waiter, dev_priv, i) {
1211                 u32 seqno;
1212                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1213                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1214                         continue;
1215
1216                 seqno = i915_gem_request_get_seqno(
1217                                            signaller->outstanding_lazy_request);
1218                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1219                                            MI_FLUSH_DW_OP_STOREDW);
1220                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1221                                            MI_FLUSH_DW_USE_GTT);
1222                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1223                 intel_ring_emit(signaller, seqno);
1224                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1225                                            MI_SEMAPHORE_TARGET(waiter->id));
1226                 intel_ring_emit(signaller, 0);
1227         }
1228
1229         return 0;
1230 }
1231
1232 static int gen6_signal(struct intel_engine_cs *signaller,
1233                        unsigned int num_dwords)
1234 {
1235         struct drm_device *dev = signaller->dev;
1236         struct drm_i915_private *dev_priv = dev->dev_private;
1237         struct intel_engine_cs *useless;
1238         int i, ret, num_rings;
1239
1240 #define MBOX_UPDATE_DWORDS 3
1241         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1242         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1243 #undef MBOX_UPDATE_DWORDS
1244
1245         ret = intel_ring_begin(signaller, num_dwords);
1246         if (ret)
1247                 return ret;
1248
1249         for_each_ring(useless, dev_priv, i) {
1250                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1251                 if (mbox_reg != GEN6_NOSYNC) {
1252                         u32 seqno = i915_gem_request_get_seqno(
1253                                            signaller->outstanding_lazy_request);
1254                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1255                         intel_ring_emit(signaller, mbox_reg);
1256                         intel_ring_emit(signaller, seqno);
1257                 }
1258         }
1259
1260         /* If num_dwords was rounded, make sure the tail pointer is correct */
1261         if (num_rings % 2 == 0)
1262                 intel_ring_emit(signaller, MI_NOOP);
1263
1264         return 0;
1265 }
1266
1267 /**
1268  * gen6_add_request - Update the semaphore mailbox registers
1269  *
1270  * @ring - ring that is adding a request
1271  * @seqno - return seqno stuck into the ring
1272  *
1273  * Update the mailbox registers in the *other* rings with the current seqno.
1274  * This acts like a signal in the canonical semaphore.
1275  */
1276 static int
1277 gen6_add_request(struct intel_engine_cs *ring)
1278 {
1279         int ret;
1280
1281         if (ring->semaphore.signal)
1282                 ret = ring->semaphore.signal(ring, 4);
1283         else
1284                 ret = intel_ring_begin(ring, 4);
1285
1286         if (ret)
1287                 return ret;
1288
1289         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1290         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1291         intel_ring_emit(ring,
1292                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1293         intel_ring_emit(ring, MI_USER_INTERRUPT);
1294         __intel_ring_advance(ring);
1295
1296         return 0;
1297 }
1298
1299 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1300                                               u32 seqno)
1301 {
1302         struct drm_i915_private *dev_priv = dev->dev_private;
1303         return dev_priv->last_seqno < seqno;
1304 }
1305
1306 /**
1307  * intel_ring_sync - sync the waiter to the signaller on seqno
1308  *
1309  * @waiter - ring that is waiting
1310  * @signaller - ring which has, or will signal
1311  * @seqno - seqno which the waiter will block on
1312  */
1313
1314 static int
1315 gen8_ring_sync(struct intel_engine_cs *waiter,
1316                struct intel_engine_cs *signaller,
1317                u32 seqno)
1318 {
1319         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1320         int ret;
1321
1322         ret = intel_ring_begin(waiter, 4);
1323         if (ret)
1324                 return ret;
1325
1326         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1327                                 MI_SEMAPHORE_GLOBAL_GTT |
1328                                 MI_SEMAPHORE_POLL |
1329                                 MI_SEMAPHORE_SAD_GTE_SDD);
1330         intel_ring_emit(waiter, seqno);
1331         intel_ring_emit(waiter,
1332                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1333         intel_ring_emit(waiter,
1334                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1335         intel_ring_advance(waiter);
1336         return 0;
1337 }
1338
1339 static int
1340 gen6_ring_sync(struct intel_engine_cs *waiter,
1341                struct intel_engine_cs *signaller,
1342                u32 seqno)
1343 {
1344         u32 dw1 = MI_SEMAPHORE_MBOX |
1345                   MI_SEMAPHORE_COMPARE |
1346                   MI_SEMAPHORE_REGISTER;
1347         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1348         int ret;
1349
1350         /* Throughout all of the GEM code, seqno passed implies our current
1351          * seqno is >= the last seqno executed. However for hardware the
1352          * comparison is strictly greater than.
1353          */
1354         seqno -= 1;
1355
1356         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1357
1358         ret = intel_ring_begin(waiter, 4);
1359         if (ret)
1360                 return ret;
1361
1362         /* If seqno wrap happened, omit the wait with no-ops */
1363         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1364                 intel_ring_emit(waiter, dw1 | wait_mbox);
1365                 intel_ring_emit(waiter, seqno);
1366                 intel_ring_emit(waiter, 0);
1367                 intel_ring_emit(waiter, MI_NOOP);
1368         } else {
1369                 intel_ring_emit(waiter, MI_NOOP);
1370                 intel_ring_emit(waiter, MI_NOOP);
1371                 intel_ring_emit(waiter, MI_NOOP);
1372                 intel_ring_emit(waiter, MI_NOOP);
1373         }
1374         intel_ring_advance(waiter);
1375
1376         return 0;
1377 }
1378
1379 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1380 do {                                                                    \
1381         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1382                  PIPE_CONTROL_DEPTH_STALL);                             \
1383         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1384         intel_ring_emit(ring__, 0);                                                     \
1385         intel_ring_emit(ring__, 0);                                                     \
1386 } while (0)
1387
1388 static int
1389 pc_render_add_request(struct intel_engine_cs *ring)
1390 {
1391         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1392         int ret;
1393
1394         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1395          * incoherent with writes to memory, i.e. completely fubar,
1396          * so we need to use PIPE_NOTIFY instead.
1397          *
1398          * However, we also need to workaround the qword write
1399          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1400          * memory before requesting an interrupt.
1401          */
1402         ret = intel_ring_begin(ring, 32);
1403         if (ret)
1404                 return ret;
1405
1406         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1407                         PIPE_CONTROL_WRITE_FLUSH |
1408                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1409         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1410         intel_ring_emit(ring,
1411                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1412         intel_ring_emit(ring, 0);
1413         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1414         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1415         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1416         scratch_addr += 2 * CACHELINE_BYTES;
1417         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1418         scratch_addr += 2 * CACHELINE_BYTES;
1419         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1420         scratch_addr += 2 * CACHELINE_BYTES;
1421         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1422         scratch_addr += 2 * CACHELINE_BYTES;
1423         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1424
1425         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1426                         PIPE_CONTROL_WRITE_FLUSH |
1427                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1428                         PIPE_CONTROL_NOTIFY);
1429         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1430         intel_ring_emit(ring,
1431                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1432         intel_ring_emit(ring, 0);
1433         __intel_ring_advance(ring);
1434
1435         return 0;
1436 }
1437
1438 static u32
1439 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1440 {
1441         /* Workaround to force correct ordering between irq and seqno writes on
1442          * ivb (and maybe also on snb) by reading from a CS register (like
1443          * ACTHD) before reading the status page. */
1444         if (!lazy_coherency) {
1445                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1446                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1447         }
1448
1449         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1450 }
1451
1452 static u32
1453 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1454 {
1455         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1456 }
1457
1458 static void
1459 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1460 {
1461         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1462 }
1463
1464 static u32
1465 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1466 {
1467         return ring->scratch.cpu_page[0];
1468 }
1469
1470 static void
1471 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1472 {
1473         ring->scratch.cpu_page[0] = seqno;
1474 }
1475
1476 static bool
1477 gen5_ring_get_irq(struct intel_engine_cs *ring)
1478 {
1479         struct drm_device *dev = ring->dev;
1480         struct drm_i915_private *dev_priv = dev->dev_private;
1481         unsigned long flags;
1482
1483         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1484                 return false;
1485
1486         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1487         if (ring->irq_refcount++ == 0)
1488                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1489         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1490
1491         return true;
1492 }
1493
1494 static void
1495 gen5_ring_put_irq(struct intel_engine_cs *ring)
1496 {
1497         struct drm_device *dev = ring->dev;
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         unsigned long flags;
1500
1501         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1502         if (--ring->irq_refcount == 0)
1503                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1504         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1505 }
1506
1507 static bool
1508 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1509 {
1510         struct drm_device *dev = ring->dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         unsigned long flags;
1513
1514         if (!intel_irqs_enabled(dev_priv))
1515                 return false;
1516
1517         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1518         if (ring->irq_refcount++ == 0) {
1519                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1520                 I915_WRITE(IMR, dev_priv->irq_mask);
1521                 POSTING_READ(IMR);
1522         }
1523         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1524
1525         return true;
1526 }
1527
1528 static void
1529 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1530 {
1531         struct drm_device *dev = ring->dev;
1532         struct drm_i915_private *dev_priv = dev->dev_private;
1533         unsigned long flags;
1534
1535         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1536         if (--ring->irq_refcount == 0) {
1537                 dev_priv->irq_mask |= ring->irq_enable_mask;
1538                 I915_WRITE(IMR, dev_priv->irq_mask);
1539                 POSTING_READ(IMR);
1540         }
1541         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1542 }
1543
1544 static bool
1545 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1546 {
1547         struct drm_device *dev = ring->dev;
1548         struct drm_i915_private *dev_priv = dev->dev_private;
1549         unsigned long flags;
1550
1551         if (!intel_irqs_enabled(dev_priv))
1552                 return false;
1553
1554         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1555         if (ring->irq_refcount++ == 0) {
1556                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1557                 I915_WRITE16(IMR, dev_priv->irq_mask);
1558                 POSTING_READ16(IMR);
1559         }
1560         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1561
1562         return true;
1563 }
1564
1565 static void
1566 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1567 {
1568         struct drm_device *dev = ring->dev;
1569         struct drm_i915_private *dev_priv = dev->dev_private;
1570         unsigned long flags;
1571
1572         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1573         if (--ring->irq_refcount == 0) {
1574                 dev_priv->irq_mask |= ring->irq_enable_mask;
1575                 I915_WRITE16(IMR, dev_priv->irq_mask);
1576                 POSTING_READ16(IMR);
1577         }
1578         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1579 }
1580
1581 static int
1582 bsd_ring_flush(struct intel_engine_cs *ring,
1583                u32     invalidate_domains,
1584                u32     flush_domains)
1585 {
1586         int ret;
1587
1588         ret = intel_ring_begin(ring, 2);
1589         if (ret)
1590                 return ret;
1591
1592         intel_ring_emit(ring, MI_FLUSH);
1593         intel_ring_emit(ring, MI_NOOP);
1594         intel_ring_advance(ring);
1595         return 0;
1596 }
1597
1598 static int
1599 i9xx_add_request(struct intel_engine_cs *ring)
1600 {
1601         int ret;
1602
1603         ret = intel_ring_begin(ring, 4);
1604         if (ret)
1605                 return ret;
1606
1607         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1608         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1609         intel_ring_emit(ring,
1610                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1611         intel_ring_emit(ring, MI_USER_INTERRUPT);
1612         __intel_ring_advance(ring);
1613
1614         return 0;
1615 }
1616
1617 static bool
1618 gen6_ring_get_irq(struct intel_engine_cs *ring)
1619 {
1620         struct drm_device *dev = ring->dev;
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622         unsigned long flags;
1623
1624         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1625                 return false;
1626
1627         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1628         if (ring->irq_refcount++ == 0) {
1629                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1630                         I915_WRITE_IMR(ring,
1631                                        ~(ring->irq_enable_mask |
1632                                          GT_PARITY_ERROR(dev)));
1633                 else
1634                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1635                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1636         }
1637         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1638
1639         return true;
1640 }
1641
1642 static void
1643 gen6_ring_put_irq(struct intel_engine_cs *ring)
1644 {
1645         struct drm_device *dev = ring->dev;
1646         struct drm_i915_private *dev_priv = dev->dev_private;
1647         unsigned long flags;
1648
1649         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1650         if (--ring->irq_refcount == 0) {
1651                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1652                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1653                 else
1654                         I915_WRITE_IMR(ring, ~0);
1655                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1656         }
1657         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1658 }
1659
1660 static bool
1661 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1662 {
1663         struct drm_device *dev = ring->dev;
1664         struct drm_i915_private *dev_priv = dev->dev_private;
1665         unsigned long flags;
1666
1667         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1668                 return false;
1669
1670         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1671         if (ring->irq_refcount++ == 0) {
1672                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1673                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1674         }
1675         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1676
1677         return true;
1678 }
1679
1680 static void
1681 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1682 {
1683         struct drm_device *dev = ring->dev;
1684         struct drm_i915_private *dev_priv = dev->dev_private;
1685         unsigned long flags;
1686
1687         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1688         if (--ring->irq_refcount == 0) {
1689                 I915_WRITE_IMR(ring, ~0);
1690                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1691         }
1692         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1693 }
1694
1695 static bool
1696 gen8_ring_get_irq(struct intel_engine_cs *ring)
1697 {
1698         struct drm_device *dev = ring->dev;
1699         struct drm_i915_private *dev_priv = dev->dev_private;
1700         unsigned long flags;
1701
1702         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1703                 return false;
1704
1705         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1706         if (ring->irq_refcount++ == 0) {
1707                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1708                         I915_WRITE_IMR(ring,
1709                                        ~(ring->irq_enable_mask |
1710                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1711                 } else {
1712                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1713                 }
1714                 POSTING_READ(RING_IMR(ring->mmio_base));
1715         }
1716         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1717
1718         return true;
1719 }
1720
1721 static void
1722 gen8_ring_put_irq(struct intel_engine_cs *ring)
1723 {
1724         struct drm_device *dev = ring->dev;
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726         unsigned long flags;
1727
1728         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1729         if (--ring->irq_refcount == 0) {
1730                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1731                         I915_WRITE_IMR(ring,
1732                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1733                 } else {
1734                         I915_WRITE_IMR(ring, ~0);
1735                 }
1736                 POSTING_READ(RING_IMR(ring->mmio_base));
1737         }
1738         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1739 }
1740
1741 static int
1742 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1743                          u64 offset, u32 length,
1744                          unsigned dispatch_flags)
1745 {
1746         int ret;
1747
1748         ret = intel_ring_begin(ring, 2);
1749         if (ret)
1750                 return ret;
1751
1752         intel_ring_emit(ring,
1753                         MI_BATCH_BUFFER_START |
1754                         MI_BATCH_GTT |
1755                         (dispatch_flags & I915_DISPATCH_SECURE ?
1756                          0 : MI_BATCH_NON_SECURE_I965));
1757         intel_ring_emit(ring, offset);
1758         intel_ring_advance(ring);
1759
1760         return 0;
1761 }
1762
1763 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1764 #define I830_BATCH_LIMIT (256*1024)
1765 #define I830_TLB_ENTRIES (2)
1766 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1767 static int
1768 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1769                          u64 offset, u32 len,
1770                          unsigned dispatch_flags)
1771 {
1772         u32 cs_offset = ring->scratch.gtt_offset;
1773         int ret;
1774
1775         ret = intel_ring_begin(ring, 6);
1776         if (ret)
1777                 return ret;
1778
1779         /* Evict the invalid PTE TLBs */
1780         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1781         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1782         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1783         intel_ring_emit(ring, cs_offset);
1784         intel_ring_emit(ring, 0xdeadbeef);
1785         intel_ring_emit(ring, MI_NOOP);
1786         intel_ring_advance(ring);
1787
1788         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1789                 if (len > I830_BATCH_LIMIT)
1790                         return -ENOSPC;
1791
1792                 ret = intel_ring_begin(ring, 6 + 2);
1793                 if (ret)
1794                         return ret;
1795
1796                 /* Blit the batch (which has now all relocs applied) to the
1797                  * stable batch scratch bo area (so that the CS never
1798                  * stumbles over its tlb invalidation bug) ...
1799                  */
1800                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1801                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1802                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1803                 intel_ring_emit(ring, cs_offset);
1804                 intel_ring_emit(ring, 4096);
1805                 intel_ring_emit(ring, offset);
1806
1807                 intel_ring_emit(ring, MI_FLUSH);
1808                 intel_ring_emit(ring, MI_NOOP);
1809                 intel_ring_advance(ring);
1810
1811                 /* ... and execute it. */
1812                 offset = cs_offset;
1813         }
1814
1815         ret = intel_ring_begin(ring, 4);
1816         if (ret)
1817                 return ret;
1818
1819         intel_ring_emit(ring, MI_BATCH_BUFFER);
1820         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1821                                         0 : MI_BATCH_NON_SECURE));
1822         intel_ring_emit(ring, offset + len - 8);
1823         intel_ring_emit(ring, MI_NOOP);
1824         intel_ring_advance(ring);
1825
1826         return 0;
1827 }
1828
1829 static int
1830 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1831                          u64 offset, u32 len,
1832                          unsigned dispatch_flags)
1833 {
1834         int ret;
1835
1836         ret = intel_ring_begin(ring, 2);
1837         if (ret)
1838                 return ret;
1839
1840         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1841         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1842                                         0 : MI_BATCH_NON_SECURE));
1843         intel_ring_advance(ring);
1844
1845         return 0;
1846 }
1847
1848 static void cleanup_status_page(struct intel_engine_cs *ring)
1849 {
1850         struct drm_i915_gem_object *obj;
1851
1852         obj = ring->status_page.obj;
1853         if (obj == NULL)
1854                 return;
1855
1856         kunmap(sg_page(obj->pages->sgl));
1857         i915_gem_object_ggtt_unpin(obj);
1858         drm_gem_object_unreference(&obj->base);
1859         ring->status_page.obj = NULL;
1860 }
1861
1862 static int init_status_page(struct intel_engine_cs *ring)
1863 {
1864         struct drm_i915_gem_object *obj;
1865
1866         if ((obj = ring->status_page.obj) == NULL) {
1867                 unsigned flags;
1868                 int ret;
1869
1870                 obj = i915_gem_alloc_object(ring->dev, 4096);
1871                 if (obj == NULL) {
1872                         DRM_ERROR("Failed to allocate status page\n");
1873                         return -ENOMEM;
1874                 }
1875
1876                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1877                 if (ret)
1878                         goto err_unref;
1879
1880                 flags = 0;
1881                 if (!HAS_LLC(ring->dev))
1882                         /* On g33, we cannot place HWS above 256MiB, so
1883                          * restrict its pinning to the low mappable arena.
1884                          * Though this restriction is not documented for
1885                          * gen4, gen5, or byt, they also behave similarly
1886                          * and hang if the HWS is placed at the top of the
1887                          * GTT. To generalise, it appears that all !llc
1888                          * platforms have issues with us placing the HWS
1889                          * above the mappable region (even though we never
1890                          * actualy map it).
1891                          */
1892                         flags |= PIN_MAPPABLE;
1893                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1894                 if (ret) {
1895 err_unref:
1896                         drm_gem_object_unreference(&obj->base);
1897                         return ret;
1898                 }
1899
1900                 ring->status_page.obj = obj;
1901         }
1902
1903         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1904         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1905         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1906
1907         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1908                         ring->name, ring->status_page.gfx_addr);
1909
1910         return 0;
1911 }
1912
1913 static int init_phys_status_page(struct intel_engine_cs *ring)
1914 {
1915         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1916
1917         if (!dev_priv->status_page_dmah) {
1918                 dev_priv->status_page_dmah =
1919                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1920                 if (!dev_priv->status_page_dmah)
1921                         return -ENOMEM;
1922         }
1923
1924         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1925         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1926
1927         return 0;
1928 }
1929
1930 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1931 {
1932         iounmap(ringbuf->virtual_start);
1933         ringbuf->virtual_start = NULL;
1934         i915_gem_object_ggtt_unpin(ringbuf->obj);
1935 }
1936
1937 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1938                                      struct intel_ringbuffer *ringbuf)
1939 {
1940         struct drm_i915_private *dev_priv = to_i915(dev);
1941         struct drm_i915_gem_object *obj = ringbuf->obj;
1942         int ret;
1943
1944         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1945         if (ret)
1946                 return ret;
1947
1948         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1949         if (ret) {
1950                 i915_gem_object_ggtt_unpin(obj);
1951                 return ret;
1952         }
1953
1954         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1955                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1956         if (ringbuf->virtual_start == NULL) {
1957                 i915_gem_object_ggtt_unpin(obj);
1958                 return -EINVAL;
1959         }
1960
1961         return 0;
1962 }
1963
1964 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1965 {
1966         drm_gem_object_unreference(&ringbuf->obj->base);
1967         ringbuf->obj = NULL;
1968 }
1969
1970 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1971                                struct intel_ringbuffer *ringbuf)
1972 {
1973         struct drm_i915_gem_object *obj;
1974
1975         obj = NULL;
1976         if (!HAS_LLC(dev))
1977                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1978         if (obj == NULL)
1979                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1980         if (obj == NULL)
1981                 return -ENOMEM;
1982
1983         /* mark ring buffers as read-only from GPU side by default */
1984         obj->gt_ro = 1;
1985
1986         ringbuf->obj = obj;
1987
1988         return 0;
1989 }
1990
1991 static int intel_init_ring_buffer(struct drm_device *dev,
1992                                   struct intel_engine_cs *ring)
1993 {
1994         struct intel_ringbuffer *ringbuf;
1995         int ret;
1996
1997         WARN_ON(ring->buffer);
1998
1999         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2000         if (!ringbuf)
2001                 return -ENOMEM;
2002         ring->buffer = ringbuf;
2003
2004         ring->dev = dev;
2005         INIT_LIST_HEAD(&ring->active_list);
2006         INIT_LIST_HEAD(&ring->request_list);
2007         INIT_LIST_HEAD(&ring->execlist_queue);
2008         ringbuf->size = 32 * PAGE_SIZE;
2009         ringbuf->ring = ring;
2010         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2011
2012         init_waitqueue_head(&ring->irq_queue);
2013
2014         if (I915_NEED_GFX_HWS(dev)) {
2015                 ret = init_status_page(ring);
2016                 if (ret)
2017                         goto error;
2018         } else {
2019                 BUG_ON(ring->id != RCS);
2020                 ret = init_phys_status_page(ring);
2021                 if (ret)
2022                         goto error;
2023         }
2024
2025         WARN_ON(ringbuf->obj);
2026
2027         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2028         if (ret) {
2029                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2030                                 ring->name, ret);
2031                 goto error;
2032         }
2033
2034         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2035         if (ret) {
2036                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2037                                 ring->name, ret);
2038                 intel_destroy_ringbuffer_obj(ringbuf);
2039                 goto error;
2040         }
2041
2042         /* Workaround an erratum on the i830 which causes a hang if
2043          * the TAIL pointer points to within the last 2 cachelines
2044          * of the buffer.
2045          */
2046         ringbuf->effective_size = ringbuf->size;
2047         if (IS_I830(dev) || IS_845G(dev))
2048                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2049
2050         ret = i915_cmd_parser_init_ring(ring);
2051         if (ret)
2052                 goto error;
2053
2054         return 0;
2055
2056 error:
2057         kfree(ringbuf);
2058         ring->buffer = NULL;
2059         return ret;
2060 }
2061
2062 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2063 {
2064         struct drm_i915_private *dev_priv;
2065         struct intel_ringbuffer *ringbuf;
2066
2067         if (!intel_ring_initialized(ring))
2068                 return;
2069
2070         dev_priv = to_i915(ring->dev);
2071         ringbuf = ring->buffer;
2072
2073         intel_stop_ring_buffer(ring);
2074         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2075
2076         intel_unpin_ringbuffer_obj(ringbuf);
2077         intel_destroy_ringbuffer_obj(ringbuf);
2078         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2079
2080         if (ring->cleanup)
2081                 ring->cleanup(ring);
2082
2083         cleanup_status_page(ring);
2084
2085         i915_cmd_parser_fini_ring(ring);
2086
2087         kfree(ringbuf);
2088         ring->buffer = NULL;
2089 }
2090
2091 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
2092 {
2093         struct intel_ringbuffer *ringbuf = ring->buffer;
2094         struct drm_i915_gem_request *request;
2095         int ret;
2096
2097         if (intel_ring_space(ringbuf) >= n)
2098                 return 0;
2099
2100         list_for_each_entry(request, &ring->request_list, list) {
2101                 if (__intel_ring_space(request->postfix, ringbuf->tail,
2102                                        ringbuf->size) >= n) {
2103                         break;
2104                 }
2105         }
2106
2107         if (&request->list == &ring->request_list)
2108                 return -ENOSPC;
2109
2110         ret = i915_wait_request(request);
2111         if (ret)
2112                 return ret;
2113
2114         i915_gem_retire_requests_ring(ring);
2115
2116         return 0;
2117 }
2118
2119 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2120 {
2121         struct drm_device *dev = ring->dev;
2122         struct drm_i915_private *dev_priv = dev->dev_private;
2123         struct intel_ringbuffer *ringbuf = ring->buffer;
2124         unsigned long end;
2125         int ret;
2126
2127         ret = intel_ring_wait_request(ring, n);
2128         if (ret != -ENOSPC)
2129                 return ret;
2130
2131         /* force the tail write in case we have been skipping them */
2132         __intel_ring_advance(ring);
2133
2134         /* With GEM the hangcheck timer should kick us out of the loop,
2135          * leaving it early runs the risk of corrupting GEM state (due
2136          * to running on almost untested codepaths). But on resume
2137          * timers don't work yet, so prevent a complete hang in that
2138          * case by choosing an insanely large timeout. */
2139         end = jiffies + 60 * HZ;
2140
2141         ret = 0;
2142         trace_i915_ring_wait_begin(ring);
2143         do {
2144                 if (intel_ring_space(ringbuf) >= n)
2145                         break;
2146                 ringbuf->head = I915_READ_HEAD(ring);
2147                 if (intel_ring_space(ringbuf) >= n)
2148                         break;
2149
2150                 msleep(1);
2151
2152                 if (dev_priv->mm.interruptible && signal_pending(current)) {
2153                         ret = -ERESTARTSYS;
2154                         break;
2155                 }
2156
2157                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2158                                            dev_priv->mm.interruptible);
2159                 if (ret)
2160                         break;
2161
2162                 if (time_after(jiffies, end)) {
2163                         ret = -EBUSY;
2164                         break;
2165                 }
2166         } while (1);
2167         trace_i915_ring_wait_end(ring);
2168         return ret;
2169 }
2170
2171 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2172 {
2173         uint32_t __iomem *virt;
2174         struct intel_ringbuffer *ringbuf = ring->buffer;
2175         int rem = ringbuf->size - ringbuf->tail;
2176
2177         if (ringbuf->space < rem) {
2178                 int ret = ring_wait_for_space(ring, rem);
2179                 if (ret)
2180                         return ret;
2181         }
2182
2183         virt = ringbuf->virtual_start + ringbuf->tail;
2184         rem /= 4;
2185         while (rem--)
2186                 iowrite32(MI_NOOP, virt++);
2187
2188         ringbuf->tail = 0;
2189         intel_ring_update_space(ringbuf);
2190
2191         return 0;
2192 }
2193
2194 int intel_ring_idle(struct intel_engine_cs *ring)
2195 {
2196         struct drm_i915_gem_request *req;
2197         int ret;
2198
2199         /* We need to add any requests required to flush the objects and ring */
2200         if (ring->outstanding_lazy_request) {
2201                 ret = i915_add_request(ring);
2202                 if (ret)
2203                         return ret;
2204         }
2205
2206         /* Wait upon the last request to be completed */
2207         if (list_empty(&ring->request_list))
2208                 return 0;
2209
2210         req = list_entry(ring->request_list.prev,
2211                            struct drm_i915_gem_request,
2212                            list);
2213
2214         return i915_wait_request(req);
2215 }
2216
2217 static int
2218 intel_ring_alloc_request(struct intel_engine_cs *ring)
2219 {
2220         int ret;
2221         struct drm_i915_gem_request *request;
2222         struct drm_i915_private *dev_private = ring->dev->dev_private;
2223
2224         if (ring->outstanding_lazy_request)
2225                 return 0;
2226
2227         request = kzalloc(sizeof(*request), GFP_KERNEL);
2228         if (request == NULL)
2229                 return -ENOMEM;
2230
2231         kref_init(&request->ref);
2232         request->ring = ring;
2233         request->ringbuf = ring->buffer;
2234         request->uniq = dev_private->request_uniq++;
2235
2236         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
2237         if (ret) {
2238                 kfree(request);
2239                 return ret;
2240         }
2241
2242         ring->outstanding_lazy_request = request;
2243         return 0;
2244 }
2245
2246 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2247                                 int bytes)
2248 {
2249         struct intel_ringbuffer *ringbuf = ring->buffer;
2250         int ret;
2251
2252         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2253                 ret = intel_wrap_ring_buffer(ring);
2254                 if (unlikely(ret))
2255                         return ret;
2256         }
2257
2258         if (unlikely(ringbuf->space < bytes)) {
2259                 ret = ring_wait_for_space(ring, bytes);
2260                 if (unlikely(ret))
2261                         return ret;
2262         }
2263
2264         return 0;
2265 }
2266
2267 int intel_ring_begin(struct intel_engine_cs *ring,
2268                      int num_dwords)
2269 {
2270         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2271         int ret;
2272
2273         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2274                                    dev_priv->mm.interruptible);
2275         if (ret)
2276                 return ret;
2277
2278         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2279         if (ret)
2280                 return ret;
2281
2282         /* Preallocate the olr before touching the ring */
2283         ret = intel_ring_alloc_request(ring);
2284         if (ret)
2285                 return ret;
2286
2287         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2288         return 0;
2289 }
2290
2291 /* Align the ring tail to a cacheline boundary */
2292 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2293 {
2294         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2295         int ret;
2296
2297         if (num_dwords == 0)
2298                 return 0;
2299
2300         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2301         ret = intel_ring_begin(ring, num_dwords);
2302         if (ret)
2303                 return ret;
2304
2305         while (num_dwords--)
2306                 intel_ring_emit(ring, MI_NOOP);
2307
2308         intel_ring_advance(ring);
2309
2310         return 0;
2311 }
2312
2313 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2314 {
2315         struct drm_device *dev = ring->dev;
2316         struct drm_i915_private *dev_priv = dev->dev_private;
2317
2318         BUG_ON(ring->outstanding_lazy_request);
2319
2320         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2321                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2322                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2323                 if (HAS_VEBOX(dev))
2324                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2325         }
2326
2327         ring->set_seqno(ring, seqno);
2328         ring->hangcheck.seqno = seqno;
2329 }
2330
2331 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2332                                      u32 value)
2333 {
2334         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2335
2336        /* Every tail move must follow the sequence below */
2337
2338         /* Disable notification that the ring is IDLE. The GT
2339          * will then assume that it is busy and bring it out of rc6.
2340          */
2341         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2342                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2343
2344         /* Clear the context id. Here be magic! */
2345         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2346
2347         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2348         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2349                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2350                      50))
2351                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2352
2353         /* Now that the ring is fully powered up, update the tail */
2354         I915_WRITE_TAIL(ring, value);
2355         POSTING_READ(RING_TAIL(ring->mmio_base));
2356
2357         /* Let the ring send IDLE messages to the GT again,
2358          * and so let it sleep to conserve power when idle.
2359          */
2360         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2361                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2362 }
2363
2364 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2365                                u32 invalidate, u32 flush)
2366 {
2367         uint32_t cmd;
2368         int ret;
2369
2370         ret = intel_ring_begin(ring, 4);
2371         if (ret)
2372                 return ret;
2373
2374         cmd = MI_FLUSH_DW;
2375         if (INTEL_INFO(ring->dev)->gen >= 8)
2376                 cmd += 1;
2377
2378         /* We always require a command barrier so that subsequent
2379          * commands, such as breadcrumb interrupts, are strictly ordered
2380          * wrt the contents of the write cache being flushed to memory
2381          * (and thus being coherent from the CPU).
2382          */
2383         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2384
2385         /*
2386          * Bspec vol 1c.5 - video engine command streamer:
2387          * "If ENABLED, all TLBs will be invalidated once the flush
2388          * operation is complete. This bit is only valid when the
2389          * Post-Sync Operation field is a value of 1h or 3h."
2390          */
2391         if (invalidate & I915_GEM_GPU_DOMAINS)
2392                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2393
2394         intel_ring_emit(ring, cmd);
2395         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2396         if (INTEL_INFO(ring->dev)->gen >= 8) {
2397                 intel_ring_emit(ring, 0); /* upper addr */
2398                 intel_ring_emit(ring, 0); /* value */
2399         } else  {
2400                 intel_ring_emit(ring, 0);
2401                 intel_ring_emit(ring, MI_NOOP);
2402         }
2403         intel_ring_advance(ring);
2404         return 0;
2405 }
2406
2407 static int
2408 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2409                               u64 offset, u32 len,
2410                               unsigned dispatch_flags)
2411 {
2412         bool ppgtt = USES_PPGTT(ring->dev) &&
2413                         !(dispatch_flags & I915_DISPATCH_SECURE);
2414         int ret;
2415
2416         ret = intel_ring_begin(ring, 4);
2417         if (ret)
2418                 return ret;
2419
2420         /* FIXME(BDW): Address space and security selectors. */
2421         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2422         intel_ring_emit(ring, lower_32_bits(offset));
2423         intel_ring_emit(ring, upper_32_bits(offset));
2424         intel_ring_emit(ring, MI_NOOP);
2425         intel_ring_advance(ring);
2426
2427         return 0;
2428 }
2429
2430 static int
2431 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2432                              u64 offset, u32 len,
2433                              unsigned dispatch_flags)
2434 {
2435         int ret;
2436
2437         ret = intel_ring_begin(ring, 2);
2438         if (ret)
2439                 return ret;
2440
2441         intel_ring_emit(ring,
2442                         MI_BATCH_BUFFER_START |
2443                         (dispatch_flags & I915_DISPATCH_SECURE ?
2444                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2445         /* bit0-7 is the length on GEN6+ */
2446         intel_ring_emit(ring, offset);
2447         intel_ring_advance(ring);
2448
2449         return 0;
2450 }
2451
2452 static int
2453 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2454                               u64 offset, u32 len,
2455                               unsigned dispatch_flags)
2456 {
2457         int ret;
2458
2459         ret = intel_ring_begin(ring, 2);
2460         if (ret)
2461                 return ret;
2462
2463         intel_ring_emit(ring,
2464                         MI_BATCH_BUFFER_START |
2465                         (dispatch_flags & I915_DISPATCH_SECURE ?
2466                          0 : MI_BATCH_NON_SECURE_I965));
2467         /* bit0-7 is the length on GEN6+ */
2468         intel_ring_emit(ring, offset);
2469         intel_ring_advance(ring);
2470
2471         return 0;
2472 }
2473
2474 /* Blitter support (SandyBridge+) */
2475
2476 static int gen6_ring_flush(struct intel_engine_cs *ring,
2477                            u32 invalidate, u32 flush)
2478 {
2479         struct drm_device *dev = ring->dev;
2480         struct drm_i915_private *dev_priv = dev->dev_private;
2481         uint32_t cmd;
2482         int ret;
2483
2484         ret = intel_ring_begin(ring, 4);
2485         if (ret)
2486                 return ret;
2487
2488         cmd = MI_FLUSH_DW;
2489         if (INTEL_INFO(ring->dev)->gen >= 8)
2490                 cmd += 1;
2491
2492         /* We always require a command barrier so that subsequent
2493          * commands, such as breadcrumb interrupts, are strictly ordered
2494          * wrt the contents of the write cache being flushed to memory
2495          * (and thus being coherent from the CPU).
2496          */
2497         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2498
2499         /*
2500          * Bspec vol 1c.3 - blitter engine command streamer:
2501          * "If ENABLED, all TLBs will be invalidated once the flush
2502          * operation is complete. This bit is only valid when the
2503          * Post-Sync Operation field is a value of 1h or 3h."
2504          */
2505         if (invalidate & I915_GEM_DOMAIN_RENDER)
2506                 cmd |= MI_INVALIDATE_TLB;
2507         intel_ring_emit(ring, cmd);
2508         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2509         if (INTEL_INFO(ring->dev)->gen >= 8) {
2510                 intel_ring_emit(ring, 0); /* upper addr */
2511                 intel_ring_emit(ring, 0); /* value */
2512         } else  {
2513                 intel_ring_emit(ring, 0);
2514                 intel_ring_emit(ring, MI_NOOP);
2515         }
2516         intel_ring_advance(ring);
2517
2518         if (!invalidate && flush) {
2519                 if (IS_GEN7(dev))
2520                         return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2521                 else if (IS_BROADWELL(dev))
2522                         dev_priv->fbc.need_sw_cache_clean = true;
2523         }
2524
2525         return 0;
2526 }
2527
2528 int intel_init_render_ring_buffer(struct drm_device *dev)
2529 {
2530         struct drm_i915_private *dev_priv = dev->dev_private;
2531         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2532         struct drm_i915_gem_object *obj;
2533         int ret;
2534
2535         ring->name = "render ring";
2536         ring->id = RCS;
2537         ring->mmio_base = RENDER_RING_BASE;
2538
2539         if (INTEL_INFO(dev)->gen >= 8) {
2540                 if (i915_semaphore_is_enabled(dev)) {
2541                         obj = i915_gem_alloc_object(dev, 4096);
2542                         if (obj == NULL) {
2543                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2544                                 i915.semaphores = 0;
2545                         } else {
2546                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2547                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2548                                 if (ret != 0) {
2549                                         drm_gem_object_unreference(&obj->base);
2550                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2551                                         i915.semaphores = 0;
2552                                 } else
2553                                         dev_priv->semaphore_obj = obj;
2554                         }
2555                 }
2556
2557                 ring->init_context = intel_rcs_ctx_init;
2558                 ring->add_request = gen6_add_request;
2559                 ring->flush = gen8_render_ring_flush;
2560                 ring->irq_get = gen8_ring_get_irq;
2561                 ring->irq_put = gen8_ring_put_irq;
2562                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2563                 ring->get_seqno = gen6_ring_get_seqno;
2564                 ring->set_seqno = ring_set_seqno;
2565                 if (i915_semaphore_is_enabled(dev)) {
2566                         WARN_ON(!dev_priv->semaphore_obj);
2567                         ring->semaphore.sync_to = gen8_ring_sync;
2568                         ring->semaphore.signal = gen8_rcs_signal;
2569                         GEN8_RING_SEMAPHORE_INIT;
2570                 }
2571         } else if (INTEL_INFO(dev)->gen >= 6) {
2572                 ring->add_request = gen6_add_request;
2573                 ring->flush = gen7_render_ring_flush;
2574                 if (INTEL_INFO(dev)->gen == 6)
2575                         ring->flush = gen6_render_ring_flush;
2576                 ring->irq_get = gen6_ring_get_irq;
2577                 ring->irq_put = gen6_ring_put_irq;
2578                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2579                 ring->get_seqno = gen6_ring_get_seqno;
2580                 ring->set_seqno = ring_set_seqno;
2581                 if (i915_semaphore_is_enabled(dev)) {
2582                         ring->semaphore.sync_to = gen6_ring_sync;
2583                         ring->semaphore.signal = gen6_signal;
2584                         /*
2585                          * The current semaphore is only applied on pre-gen8
2586                          * platform.  And there is no VCS2 ring on the pre-gen8
2587                          * platform. So the semaphore between RCS and VCS2 is
2588                          * initialized as INVALID.  Gen8 will initialize the
2589                          * sema between VCS2 and RCS later.
2590                          */
2591                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2592                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2593                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2594                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2595                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2596                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2597                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2598                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2599                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2600                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2601                 }
2602         } else if (IS_GEN5(dev)) {
2603                 ring->add_request = pc_render_add_request;
2604                 ring->flush = gen4_render_ring_flush;
2605                 ring->get_seqno = pc_render_get_seqno;
2606                 ring->set_seqno = pc_render_set_seqno;
2607                 ring->irq_get = gen5_ring_get_irq;
2608                 ring->irq_put = gen5_ring_put_irq;
2609                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2610                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2611         } else {
2612                 ring->add_request = i9xx_add_request;
2613                 if (INTEL_INFO(dev)->gen < 4)
2614                         ring->flush = gen2_render_ring_flush;
2615                 else
2616                         ring->flush = gen4_render_ring_flush;
2617                 ring->get_seqno = ring_get_seqno;
2618                 ring->set_seqno = ring_set_seqno;
2619                 if (IS_GEN2(dev)) {
2620                         ring->irq_get = i8xx_ring_get_irq;
2621                         ring->irq_put = i8xx_ring_put_irq;
2622                 } else {
2623                         ring->irq_get = i9xx_ring_get_irq;
2624                         ring->irq_put = i9xx_ring_put_irq;
2625                 }
2626                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2627         }
2628         ring->write_tail = ring_write_tail;
2629
2630         if (IS_HASWELL(dev))
2631                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2632         else if (IS_GEN8(dev))
2633                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2634         else if (INTEL_INFO(dev)->gen >= 6)
2635                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2636         else if (INTEL_INFO(dev)->gen >= 4)
2637                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2638         else if (IS_I830(dev) || IS_845G(dev))
2639                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2640         else
2641                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2642         ring->init_hw = init_render_ring;
2643         ring->cleanup = render_ring_cleanup;
2644
2645         /* Workaround batchbuffer to combat CS tlb bug. */
2646         if (HAS_BROKEN_CS_TLB(dev)) {
2647                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2648                 if (obj == NULL) {
2649                         DRM_ERROR("Failed to allocate batch bo\n");
2650                         return -ENOMEM;
2651                 }
2652
2653                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2654                 if (ret != 0) {
2655                         drm_gem_object_unreference(&obj->base);
2656                         DRM_ERROR("Failed to ping batch bo\n");
2657                         return ret;
2658                 }
2659
2660                 ring->scratch.obj = obj;
2661                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2662         }
2663
2664         ret = intel_init_ring_buffer(dev, ring);
2665         if (ret)
2666                 return ret;
2667
2668         if (INTEL_INFO(dev)->gen >= 5) {
2669                 ret = intel_init_pipe_control(ring);
2670                 if (ret)
2671                         return ret;
2672         }
2673
2674         return 0;
2675 }
2676
2677 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2678 {
2679         struct drm_i915_private *dev_priv = dev->dev_private;
2680         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2681
2682         ring->name = "bsd ring";
2683         ring->id = VCS;
2684
2685         ring->write_tail = ring_write_tail;
2686         if (INTEL_INFO(dev)->gen >= 6) {
2687                 ring->mmio_base = GEN6_BSD_RING_BASE;
2688                 /* gen6 bsd needs a special wa for tail updates */
2689                 if (IS_GEN6(dev))
2690                         ring->write_tail = gen6_bsd_ring_write_tail;
2691                 ring->flush = gen6_bsd_ring_flush;
2692                 ring->add_request = gen6_add_request;
2693                 ring->get_seqno = gen6_ring_get_seqno;
2694                 ring->set_seqno = ring_set_seqno;
2695                 if (INTEL_INFO(dev)->gen >= 8) {
2696                         ring->irq_enable_mask =
2697                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2698                         ring->irq_get = gen8_ring_get_irq;
2699                         ring->irq_put = gen8_ring_put_irq;
2700                         ring->dispatch_execbuffer =
2701                                 gen8_ring_dispatch_execbuffer;
2702                         if (i915_semaphore_is_enabled(dev)) {
2703                                 ring->semaphore.sync_to = gen8_ring_sync;
2704                                 ring->semaphore.signal = gen8_xcs_signal;
2705                                 GEN8_RING_SEMAPHORE_INIT;
2706                         }
2707                 } else {
2708                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2709                         ring->irq_get = gen6_ring_get_irq;
2710                         ring->irq_put = gen6_ring_put_irq;
2711                         ring->dispatch_execbuffer =
2712                                 gen6_ring_dispatch_execbuffer;
2713                         if (i915_semaphore_is_enabled(dev)) {
2714                                 ring->semaphore.sync_to = gen6_ring_sync;
2715                                 ring->semaphore.signal = gen6_signal;
2716                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2717                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2718                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2719                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2720                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2721                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2722                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2723                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2724                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2725                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2726                         }
2727                 }
2728         } else {
2729                 ring->mmio_base = BSD_RING_BASE;
2730                 ring->flush = bsd_ring_flush;
2731                 ring->add_request = i9xx_add_request;
2732                 ring->get_seqno = ring_get_seqno;
2733                 ring->set_seqno = ring_set_seqno;
2734                 if (IS_GEN5(dev)) {
2735                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2736                         ring->irq_get = gen5_ring_get_irq;
2737                         ring->irq_put = gen5_ring_put_irq;
2738                 } else {
2739                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2740                         ring->irq_get = i9xx_ring_get_irq;
2741                         ring->irq_put = i9xx_ring_put_irq;
2742                 }
2743                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2744         }
2745         ring->init_hw = init_ring_common;
2746
2747         return intel_init_ring_buffer(dev, ring);
2748 }
2749
2750 /**
2751  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2752  */
2753 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2754 {
2755         struct drm_i915_private *dev_priv = dev->dev_private;
2756         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2757
2758         ring->name = "bsd2 ring";
2759         ring->id = VCS2;
2760
2761         ring->write_tail = ring_write_tail;
2762         ring->mmio_base = GEN8_BSD2_RING_BASE;
2763         ring->flush = gen6_bsd_ring_flush;
2764         ring->add_request = gen6_add_request;
2765         ring->get_seqno = gen6_ring_get_seqno;
2766         ring->set_seqno = ring_set_seqno;
2767         ring->irq_enable_mask =
2768                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2769         ring->irq_get = gen8_ring_get_irq;
2770         ring->irq_put = gen8_ring_put_irq;
2771         ring->dispatch_execbuffer =
2772                         gen8_ring_dispatch_execbuffer;
2773         if (i915_semaphore_is_enabled(dev)) {
2774                 ring->semaphore.sync_to = gen8_ring_sync;
2775                 ring->semaphore.signal = gen8_xcs_signal;
2776                 GEN8_RING_SEMAPHORE_INIT;
2777         }
2778         ring->init_hw = init_ring_common;
2779
2780         return intel_init_ring_buffer(dev, ring);
2781 }
2782
2783 int intel_init_blt_ring_buffer(struct drm_device *dev)
2784 {
2785         struct drm_i915_private *dev_priv = dev->dev_private;
2786         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2787
2788         ring->name = "blitter ring";
2789         ring->id = BCS;
2790
2791         ring->mmio_base = BLT_RING_BASE;
2792         ring->write_tail = ring_write_tail;
2793         ring->flush = gen6_ring_flush;
2794         ring->add_request = gen6_add_request;
2795         ring->get_seqno = gen6_ring_get_seqno;
2796         ring->set_seqno = ring_set_seqno;
2797         if (INTEL_INFO(dev)->gen >= 8) {
2798                 ring->irq_enable_mask =
2799                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2800                 ring->irq_get = gen8_ring_get_irq;
2801                 ring->irq_put = gen8_ring_put_irq;
2802                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2803                 if (i915_semaphore_is_enabled(dev)) {
2804                         ring->semaphore.sync_to = gen8_ring_sync;
2805                         ring->semaphore.signal = gen8_xcs_signal;
2806                         GEN8_RING_SEMAPHORE_INIT;
2807                 }
2808         } else {
2809                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2810                 ring->irq_get = gen6_ring_get_irq;
2811                 ring->irq_put = gen6_ring_put_irq;
2812                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2813                 if (i915_semaphore_is_enabled(dev)) {
2814                         ring->semaphore.signal = gen6_signal;
2815                         ring->semaphore.sync_to = gen6_ring_sync;
2816                         /*
2817                          * The current semaphore is only applied on pre-gen8
2818                          * platform.  And there is no VCS2 ring on the pre-gen8
2819                          * platform. So the semaphore between BCS and VCS2 is
2820                          * initialized as INVALID.  Gen8 will initialize the
2821                          * sema between BCS and VCS2 later.
2822                          */
2823                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2824                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2825                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2826                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2827                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2828                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2829                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2830                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2831                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2832                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2833                 }
2834         }
2835         ring->init_hw = init_ring_common;
2836
2837         return intel_init_ring_buffer(dev, ring);
2838 }
2839
2840 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2841 {
2842         struct drm_i915_private *dev_priv = dev->dev_private;
2843         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2844
2845         ring->name = "video enhancement ring";
2846         ring->id = VECS;
2847
2848         ring->mmio_base = VEBOX_RING_BASE;
2849         ring->write_tail = ring_write_tail;
2850         ring->flush = gen6_ring_flush;
2851         ring->add_request = gen6_add_request;
2852         ring->get_seqno = gen6_ring_get_seqno;
2853         ring->set_seqno = ring_set_seqno;
2854
2855         if (INTEL_INFO(dev)->gen >= 8) {
2856                 ring->irq_enable_mask =
2857                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2858                 ring->irq_get = gen8_ring_get_irq;
2859                 ring->irq_put = gen8_ring_put_irq;
2860                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2861                 if (i915_semaphore_is_enabled(dev)) {
2862                         ring->semaphore.sync_to = gen8_ring_sync;
2863                         ring->semaphore.signal = gen8_xcs_signal;
2864                         GEN8_RING_SEMAPHORE_INIT;
2865                 }
2866         } else {
2867                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2868                 ring->irq_get = hsw_vebox_get_irq;
2869                 ring->irq_put = hsw_vebox_put_irq;
2870                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2871                 if (i915_semaphore_is_enabled(dev)) {
2872                         ring->semaphore.sync_to = gen6_ring_sync;
2873                         ring->semaphore.signal = gen6_signal;
2874                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2875                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2876                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2877                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2878                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2879                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2880                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2881                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2882                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2883                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2884                 }
2885         }
2886         ring->init_hw = init_ring_common;
2887
2888         return intel_init_ring_buffer(dev, ring);
2889 }
2890
2891 int
2892 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2893 {
2894         int ret;
2895
2896         if (!ring->gpu_caches_dirty)
2897                 return 0;
2898
2899         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2900         if (ret)
2901                 return ret;
2902
2903         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2904
2905         ring->gpu_caches_dirty = false;
2906         return 0;
2907 }
2908
2909 int
2910 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2911 {
2912         uint32_t flush_domains;
2913         int ret;
2914
2915         flush_domains = 0;
2916         if (ring->gpu_caches_dirty)
2917                 flush_domains = I915_GEM_GPU_DOMAINS;
2918
2919         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2920         if (ret)
2921                 return ret;
2922
2923         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2924
2925         ring->gpu_caches_dirty = false;
2926         return 0;
2927 }
2928
2929 void
2930 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2931 {
2932         int ret;
2933
2934         if (!intel_ring_initialized(ring))
2935                 return;
2936
2937         ret = intel_ring_idle(ring);
2938         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2939                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2940                           ring->name, ret);
2941
2942         stop_ring(ring);
2943 }