drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct intel_engine_cs *ring,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         u32 cmd;
  99         int ret;
 100
 101         cmd = MI_FLUSH;
 102         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 103                 cmd |= MI_NO_WRITE_FLUSH;
 104
 105         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                 cmd |= MI_READ_FLUSH;
 107
 108         ret = intel_ring_begin(ring, 2);
 109         if (ret)
 110                 return ret;
 111
 112         intel_ring_emit(ring, cmd);
 113         intel_ring_emit(ring, MI_NOOP);
 114         intel_ring_advance(ring);
 115
 116         return 0;
 117 }
 118
 119 static int
 120 gen4_render_ring_flush(struct intel_engine_cs *ring,
 121                        u32      invalidate_domains,
 122                        u32      flush_domains)
 123 {
 124         struct drm_device *dev = ring->dev;
 125         u32 cmd;
 126         int ret;
 127
 128         /*
 129          * read/write caches:
 130          *
 131          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 132          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 133          * also flushed at 2d versus 3d pipeline switches.
 134          *
 135          * read-only caches:
 136          *
 137          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 138          * MI_READ_FLUSH is set, and is always flushed on 965.
 139          *
 140          * I915_GEM_DOMAIN_COMMAND may not exist?
 141          *
 142          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 143          * invalidated when MI_EXE_FLUSH is set.
 144          *
 145          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 146          * invalidated with every MI_FLUSH.
 147          *
 148          * TLBs:
 149          *
 150          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 151          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 152          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 153          * are flushed at any MI_FLUSH.
 154          */
 155
 156         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 157         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 158                 cmd &= ~MI_NO_WRITE_FLUSH;
 159         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 160                 cmd |= MI_EXE_FLUSH;
 161
 162         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 163             (IS_G4X(dev) || IS_GEN5(dev)))
 164                 cmd |= MI_INVALIDATE_ISP;
 165
 166         ret = intel_ring_begin(ring, 2);
 167         if (ret)
 168                 return ret;
 169
 170         intel_ring_emit(ring, cmd);
 171         intel_ring_emit(ring, MI_NOOP);
 172         intel_ring_advance(ring);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 179  * implementing two workarounds on gen6.  From section 1.4.7.1
 180  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 181  *
 182  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 183  * produced by non-pipelined state commands), software needs to first
 184  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 185  * 0.
 186  *
 187  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 188  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 189  *
 190  * And the workaround for these two requires this workaround first:
 191  *
 192  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 193  * BEFORE the pipe-control with a post-sync op and no write-cache
 194  * flushes.
 195  *
 196  * And this last workaround is tricky because of the requirements on
 197  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 198  * volume 2 part 1:
 199  *
 200  *     "1 of the following must also be set:
 201  *      - Render Target Cache Flush Enable ([12] of DW1)
 202  *      - Depth Cache Flush Enable ([0] of DW1)
 203  *      - Stall at Pixel Scoreboard ([1] of DW1)
 204  *      - Depth Stall ([13] of DW1)
 205  *      - Post-Sync Operation ([13] of DW1)
 206  *      - Notify Enable ([8] of DW1)"
 207  *
 208  * The cache flushes require the workaround flush that triggered this
 209  * one, so we can't use it.  Depth stall would trigger the same.
 210  * Post-sync nonzero is what triggered this second workaround, so we
 211  * can't use that one either.  Notify enable is IRQs, which aren't
 212  * really our business.  That leaves only stall at scoreboard.
 213  */
 214 static int
 215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 216 {
 217         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 218         int ret;
 219
 220
 221         ret = intel_ring_begin(ring, 6);
 222         if (ret)
 223                 return ret;
 224
 225         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 226         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 227                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 228         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 229         intel_ring_emit(ring, 0); /* low dword */
 230         intel_ring_emit(ring, 0); /* high dword */
 231         intel_ring_emit(ring, MI_NOOP);
 232         intel_ring_advance(ring);
 233
 234         ret = intel_ring_begin(ring, 6);
 235         if (ret)
 236                 return ret;
 237
 238         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 239         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 240         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 241         intel_ring_emit(ring, 0);
 242         intel_ring_emit(ring, 0);
 243         intel_ring_emit(ring, MI_NOOP);
 244         intel_ring_advance(ring);
 245
 246         return 0;
 247 }
 248
 249 static int
 250 gen6_render_ring_flush(struct intel_engine_cs *ring,
 251                          u32 invalidate_domains, u32 flush_domains)
 252 {
 253         u32 flags = 0;
 254         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 255         int ret;
 256
 257         /* Force SNB workarounds for PIPE_CONTROL flushes */
 258         ret = intel_emit_post_sync_nonzero_flush(ring);
 259         if (ret)
 260                 return ret;
 261
 262         /* Just flush everything.  Experiments have shown that reducing the
 263          * number of bits based on the write domains has little performance
 264          * impact.
 265          */
 266         if (flush_domains) {
 267                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 268                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 269                 /*
 270                  * Ensure that any following seqno writes only happen
 271                  * when the render cache is indeed flushed.
 272                  */
 273                 flags |= PIPE_CONTROL_CS_STALL;
 274         }
 275         if (invalidate_domains) {
 276                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 277                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 278                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 279                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 280                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 282                 /*
 283                  * TLB invalidate requires a post-sync write.
 284                  */
 285                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 286         }
 287
 288         ret = intel_ring_begin(ring, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(ring, flags);
 294         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 295         intel_ring_emit(ring, 0);
 296         intel_ring_advance(ring);
 297
 298         return 0;
 299 }
 300
 301 static int
 302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 303 {
 304         int ret;
 305
 306         ret = intel_ring_begin(ring, 4);
 307         if (ret)
 308                 return ret;
 309
 310         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 311         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 312                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 313         intel_ring_emit(ring, 0);
 314         intel_ring_emit(ring, 0);
 315         intel_ring_advance(ring);
 316
 317         return 0;
 318 }
 319
 320 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
 321 {
 322         int ret;
 323
 324         if (!ring->fbc_dirty)
 325                 return 0;
 326
 327         ret = intel_ring_begin(ring, 6);
 328         if (ret)
 329                 return ret;
 330         /* WaFbcNukeOn3DBlt:ivb/hsw */
 331         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 332         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 333         intel_ring_emit(ring, value);
 334         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 335         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 336         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 337         intel_ring_advance(ring);
 338
 339         ring->fbc_dirty = false;
 340         return 0;
 341 }
 342
 343 static int
 344 gen7_render_ring_flush(struct intel_engine_cs *ring,
 345                        u32 invalidate_domains, u32 flush_domains)
 346 {
 347         u32 flags = 0;
 348         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 349         int ret;
 350
 351         /*
 352          * Ensure that any following seqno writes only happen when the render
 353          * cache is indeed flushed.
 354          *
 355          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 356          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 357          * don't try to be clever and just set it unconditionally.
 358          */
 359         flags |= PIPE_CONTROL_CS_STALL;
 360
 361         /* Just flush everything.  Experiments have shown that reducing the
 362          * number of bits based on the write domains has little performance
 363          * impact.
 364          */
 365         if (flush_domains) {
 366                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 367                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 368         }
 369         if (invalidate_domains) {
 370                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 371                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 372                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 373                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 374                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 375                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 376                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 377                 /*
 378                  * TLB invalidate requires a post-sync write.
 379                  */
 380                 flags |= PIPE_CONTROL_QW_WRITE;
 381                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 382
 383                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 384
 385                 /* Workaround: we must issue a pipe_control with CS-stall bit
 386                  * set before a pipe_control command that has the state cache
 387                  * invalidate bit set. */
 388                 gen7_render_ring_cs_stall_wa(ring);
 389         }
 390
 391         ret = intel_ring_begin(ring, 4);
 392         if (ret)
 393                 return ret;
 394
 395         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 396         intel_ring_emit(ring, flags);
 397         intel_ring_emit(ring, scratch_addr);
 398         intel_ring_emit(ring, 0);
 399         intel_ring_advance(ring);
 400
 401         if (!invalidate_domains && flush_domains)
 402                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 403
 404         return 0;
 405 }
 406
 407 static int
 408 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 409                        u32 flags, u32 scratch_addr)
 410 {
 411         int ret;
 412
 413         ret = intel_ring_begin(ring, 6);
 414         if (ret)
 415                 return ret;
 416
 417         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 418         intel_ring_emit(ring, flags);
 419         intel_ring_emit(ring, scratch_addr);
 420         intel_ring_emit(ring, 0);
 421         intel_ring_emit(ring, 0);
 422         intel_ring_emit(ring, 0);
 423         intel_ring_advance(ring);
 424
 425         return 0;
 426 }
 427
 428 static int
 429 gen8_render_ring_flush(struct intel_engine_cs *ring,
 430                        u32 invalidate_domains, u32 flush_domains)
 431 {
 432         u32 flags = 0;
 433         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 434         int ret;
 435
 436         flags |= PIPE_CONTROL_CS_STALL;
 437
 438         if (flush_domains) {
 439                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 440                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 441         }
 442         if (invalidate_domains) {
 443                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 444                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 445                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 446                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 447                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 448                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 449                 flags |= PIPE_CONTROL_QW_WRITE;
 450                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 451
 452                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 453                 ret = gen8_emit_pipe_control(ring,
 454                                              PIPE_CONTROL_CS_STALL |
 455                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 456                                              0);
 457                 if (ret)
 458                         return ret;
 459         }
 460
 461         ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
 462         if (ret)
 463                 return ret;
 464
 465         if (!invalidate_domains && flush_domains)
 466                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 467
 468         return 0;
 469 }
 470
 471 static void ring_write_tail(struct intel_engine_cs *ring,
 472                             u32 value)
 473 {
 474         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 475         I915_WRITE_TAIL(ring, value);
 476 }
 477
 478 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 479 {
 480         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 481         u64 acthd;
 482
 483         if (INTEL_INFO(ring->dev)->gen >= 8)
 484                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 485                                          RING_ACTHD_UDW(ring->mmio_base));
 486         else if (INTEL_INFO(ring->dev)->gen >= 4)
 487                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 488         else
 489                 acthd = I915_READ(ACTHD);
 490
 491         return acthd;
 492 }
 493
 494 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 495 {
 496         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 497         u32 addr;
 498
 499         addr = dev_priv->status_page_dmah->busaddr;
 500         if (INTEL_INFO(ring->dev)->gen >= 4)
 501                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 502         I915_WRITE(HWS_PGA, addr);
 503 }
 504
 505 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 506 {
 507         struct drm_device *dev = ring->dev;
 508         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 509         u32 mmio = 0;
 510
 511         /* The ring status page addresses are no longer next to the rest of
 512          * the ring registers as of gen7.
 513          */
 514         if (IS_GEN7(dev)) {
 515                 switch (ring->id) {
 516                 case RCS:
 517                         mmio = RENDER_HWS_PGA_GEN7;
 518                         break;
 519                 case BCS:
 520                         mmio = BLT_HWS_PGA_GEN7;
 521                         break;
 522                 /*
 523                  * VCS2 actually doesn't exist on Gen7. Only shut up
 524                  * gcc switch check warning
 525                  */
 526                 case VCS2:
 527                 case VCS:
 528                         mmio = BSD_HWS_PGA_GEN7;
 529                         break;
 530                 case VECS:
 531                         mmio = VEBOX_HWS_PGA_GEN7;
 532                         break;
 533                 }
 534         } else if (IS_GEN6(ring->dev)) {
 535                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 536         } else {
 537                 /* XXX: gen8 returns to sanity */
 538                 mmio = RING_HWS_PGA(ring->mmio_base);
 539         }
 540
 541         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 542         POSTING_READ(mmio);
 543
 544         /*
 545          * Flush the TLB for this page
 546          *
 547          * FIXME: These two bits have disappeared on gen8, so a question
 548          * arises: do we still need this and if so how should we go about
 549          * invalidating the TLB?
 550          */
 551         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 552                 u32 reg = RING_INSTPM(ring->mmio_base);
 553
 554                 /* ring should be idle before issuing a sync flush*/
 555                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 556
 557                 I915_WRITE(reg,
 558                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 559                                               INSTPM_SYNC_FLUSH));
 560                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 561                              1000))
 562                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 563                                   ring->name);
 564         }
 565 }
 566
 567 static bool stop_ring(struct intel_engine_cs *ring)
 568 {
 569         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 570
 571         if (!IS_GEN2(ring->dev)) {
 572                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 573                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 574                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 575                         /* Sometimes we observe that the idle flag is not
 576                          * set even though the ring is empty. So double
 577                          * check before giving up.
 578                          */
 579                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 580                                 return false;
 581                 }
 582         }
 583
 584         I915_WRITE_CTL(ring, 0);
 585         I915_WRITE_HEAD(ring, 0);
 586         ring->write_tail(ring, 0);
 587
 588         if (!IS_GEN2(ring->dev)) {
 589                 (void)I915_READ_CTL(ring);
 590                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 591         }
 592
 593         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 594 }
 595
 596 static int init_ring_common(struct intel_engine_cs *ring)
 597 {
 598         struct drm_device *dev = ring->dev;
 599         struct drm_i915_private *dev_priv = dev->dev_private;
 600         struct intel_ringbuffer *ringbuf = ring->buffer;
 601         struct drm_i915_gem_object *obj = ringbuf->obj;
 602         int ret = 0;
 603
 604         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 605
 606         if (!stop_ring(ring)) {
 607                 /* G45 ring initialization often fails to reset head to zero */
 608                 DRM_DEBUG_KMS("%s head not reset to zero "
 609                               "ctl %08x head %08x tail %08x start %08x\n",
 610                               ring->name,
 611                               I915_READ_CTL(ring),
 612                               I915_READ_HEAD(ring),
 613                               I915_READ_TAIL(ring),
 614                               I915_READ_START(ring));
 615
 616                 if (!stop_ring(ring)) {
 617                         DRM_ERROR("failed to set %s head to zero "
 618                                   "ctl %08x head %08x tail %08x start %08x\n",
 619                                   ring->name,
 620                                   I915_READ_CTL(ring),
 621                                   I915_READ_HEAD(ring),
 622                                   I915_READ_TAIL(ring),
 623                                   I915_READ_START(ring));
 624                         ret = -EIO;
 625                         goto out;
 626                 }
 627         }
 628
 629         if (I915_NEED_GFX_HWS(dev))
 630                 intel_ring_setup_status_page(ring);
 631         else
 632                 ring_setup_phys_status_page(ring);
 633
 634         /* Enforce ordering by reading HEAD register back */
 635         I915_READ_HEAD(ring);
 636
 637         /* Initialize the ring. This must happen _after_ we've cleared the ring
 638          * registers with the above sequence (the readback of the HEAD registers
 639          * also enforces ordering), otherwise the hw might lose the new ring
 640          * register values. */
 641         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 642
 643         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 644         if (I915_READ_HEAD(ring))
 645                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 646                           ring->name, I915_READ_HEAD(ring));
 647         I915_WRITE_HEAD(ring, 0);
 648         (void)I915_READ_HEAD(ring);
 649
 650         I915_WRITE_CTL(ring,
 651                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 652                         | RING_VALID);
 653
 654         /* If the head is still not zero, the ring is dead */
 655         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 656                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 657                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 658                 DRM_ERROR("%s initialization failed "
 659                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 660                           ring->name,
 661                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 662                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 663                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 664                 ret = -EIO;
 665                 goto out;
 666         }
 667
 668         ringbuf->last_retired_head = -1;
 669         ringbuf->head = I915_READ_HEAD(ring);
 670         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 671         intel_ring_update_space(ringbuf);
 672
 673         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 674
 675 out:
 676         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 677
 678         return ret;
 679 }
 680
 681 void
 682 intel_fini_pipe_control(struct intel_engine_cs *ring)
 683 {
 684         struct drm_device *dev = ring->dev;
 685
 686         if (ring->scratch.obj == NULL)
 687                 return;
 688
 689         if (INTEL_INFO(dev)->gen >= 5) {
 690                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 691                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 692         }
 693
 694         drm_gem_object_unreference(&ring->scratch.obj->base);
 695         ring->scratch.obj = NULL;
 696 }
 697
 698 int
 699 intel_init_pipe_control(struct intel_engine_cs *ring)
 700 {
 701         int ret;
 702
 703         WARN_ON(ring->scratch.obj);
 704
 705         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 706         if (ring->scratch.obj == NULL) {
 707                 DRM_ERROR("Failed to allocate seqno page\n");
 708                 ret = -ENOMEM;
 709                 goto err;
 710         }
 711
 712         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 713         if (ret)
 714                 goto err_unref;
 715
 716         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 717         if (ret)
 718                 goto err_unref;
 719
 720         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 721         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 722         if (ring->scratch.cpu_page == NULL) {
 723                 ret = -ENOMEM;
 724                 goto err_unpin;
 725         }
 726
 727         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 728                          ring->name, ring->scratch.gtt_offset);
 729         return 0;
 730
 731 err_unpin:
 732         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 733 err_unref:
 734         drm_gem_object_unreference(&ring->scratch.obj->base);
 735 err:
 736         return ret;
 737 }
 738
 739 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
 740                                        struct intel_context *ctx)
 741 {
 742         int ret, i;
 743         struct drm_device *dev = ring->dev;
 744         struct drm_i915_private *dev_priv = dev->dev_private;
 745         struct i915_workarounds *w = &dev_priv->workarounds;
 746
 747         if (WARN_ON_ONCE(w->count == 0))
 748                 return 0;
 749
 750         ring->gpu_caches_dirty = true;
 751         ret = intel_ring_flush_all_caches(ring);
 752         if (ret)
 753                 return ret;
 754
 755         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 756         if (ret)
 757                 return ret;
 758
 759         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 760         for (i = 0; i < w->count; i++) {
 761                 intel_ring_emit(ring, w->reg[i].addr);
 762                 intel_ring_emit(ring, w->reg[i].value);
 763         }
 764         intel_ring_emit(ring, MI_NOOP);
 765
 766         intel_ring_advance(ring);
 767
 768         ring->gpu_caches_dirty = true;
 769         ret = intel_ring_flush_all_caches(ring);
 770         if (ret)
 771                 return ret;
 772
 773         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 774
 775         return 0;
 776 }
 777
 778 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
 779                               struct intel_context *ctx)
 780 {
 781         int ret;
 782
 783         ret = intel_ring_workarounds_emit(ring, ctx);
 784         if (ret != 0)
 785                 return ret;
 786
 787         ret = i915_gem_render_state_init(ring);
 788         if (ret)
 789                 DRM_ERROR("init render state: %d\n", ret);
 790
 791         return ret;
 792 }
 793
 794 static int wa_add(struct drm_i915_private *dev_priv,
 795                   const u32 addr, const u32 mask, const u32 val)
 796 {
 797         const u32 idx = dev_priv->workarounds.count;
 798
 799         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 800                 return -ENOSPC;
 801
 802         dev_priv->workarounds.reg[idx].addr = addr;
 803         dev_priv->workarounds.reg[idx].value = val;
 804         dev_priv->workarounds.reg[idx].mask = mask;
 805
 806         dev_priv->workarounds.count++;
 807
 808         return 0;
 809 }
 810
 811 #define WA_REG(addr, mask, val) { \
 812                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 813                 if (r) \
 814                         return r; \
 815         }
 816
 817 #define WA_SET_BIT_MASKED(addr, mask) \
 818         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 819
 820 #define WA_CLR_BIT_MASKED(addr, mask) \
 821         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 822
 823 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 824         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 825
 826 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 827 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 828
 829 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 830
 831 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 832 {
 833         struct drm_device *dev = ring->dev;
 834         struct drm_i915_private *dev_priv = dev->dev_private;
 835
 836         /* WaDisablePartialInstShootdown:bdw */
 837         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 838         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 839                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 840                           STALL_DOP_GATING_DISABLE);
 841
 842         /* WaDisableDopClockGating:bdw */
 843         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 844                           DOP_CLOCK_GATING_DISABLE);
 845
 846         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 847                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 848
 849         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 850          * workaround for for a possible hang in the unlikely event a TLB
 851          * invalidation occurs during a PSD flush.
 852          */
 853         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 854                           /* WaForceEnableNonCoherent:bdw */
 855                           HDC_FORCE_NON_COHERENT |
 856                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 857                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 858                           /* WaHdcDisableFetchWhenMasked:bdw */
 859                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 860                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 861                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 862
 863         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 864          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 865          *  polygons in the same 8x4 pixel/sample area to be processed without
 866          *  stalling waiting for the earlier ones to write to Hierarchical Z
 867          *  buffer."
 868          *
 869          * This optimization is off by default for Broadwell; turn it on.
 870          */
 871         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 872
 873         /* Wa4x4STCOptimizationDisable:bdw */
 874         WA_SET_BIT_MASKED(CACHE_MODE_1,
 875                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 876
 877         /*
 878          * BSpec recommends 8x4 when MSAA is used,
 879          * however in practice 16x4 seems fastest.
 880          *
 881          * Note that PS/WM thread counts depend on the WIZ hashing
 882          * disable bit, which we don't touch here, but it's good
 883          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 884          */
 885         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 886                             GEN6_WIZ_HASHING_MASK,
 887                             GEN6_WIZ_HASHING_16x4);
 888
 889         return 0;
 890 }
 891
 892 static int chv_init_workarounds(struct intel_engine_cs *ring)
 893 {
 894         struct drm_device *dev = ring->dev;
 895         struct drm_i915_private *dev_priv = dev->dev_private;
 896
 897         /* WaDisablePartialInstShootdown:chv */
 898         /* WaDisableThreadStallDopClockGating:chv */
 899         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 900                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 901                           STALL_DOP_GATING_DISABLE);
 902
 903         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 904          * workaround for a possible hang in the unlikely event a TLB
 905          * invalidation occurs during a PSD flush.
 906          */
 907         /* WaForceEnableNonCoherent:chv */
 908         /* WaHdcDisableFetchWhenMasked:chv */
 909         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 910                           HDC_FORCE_NON_COHERENT |
 911                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 912
 913         /* According to the CACHE_MODE_0 default value documentation, some
 914          * CHV platforms disable this optimization by default.  Turn it on.
 915          */
 916         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 917
 918         /* Wa4x4STCOptimizationDisable:chv */
 919         WA_SET_BIT_MASKED(CACHE_MODE_1,
 920                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 921
 922         /* Improve HiZ throughput on CHV. */
 923         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 924
 925         /*
 926          * BSpec recommends 8x4 when MSAA is used,
 927          * however in practice 16x4 seems fastest.
 928          *
 929          * Note that PS/WM thread counts depend on the WIZ hashing
 930          * disable bit, which we don't touch here, but it's good
 931          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 932          */
 933         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 934                             GEN6_WIZ_HASHING_MASK,
 935                             GEN6_WIZ_HASHING_16x4);
 936
 937         if (INTEL_REVID(dev) == SKL_REVID_C0 ||
 938             INTEL_REVID(dev) == SKL_REVID_D0)
 939                 /* WaBarrierPerformanceFixDisable:skl */
 940                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
 941                                   HDC_FENCE_DEST_SLM_DISABLE |
 942                                   HDC_BARRIER_PERFORMANCE_DISABLE);
 943
 944         return 0;
 945 }
 946
 947 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 948 {
 949         struct drm_device *dev = ring->dev;
 950         struct drm_i915_private *dev_priv = dev->dev_private;
 951
 952         /* WaDisablePartialInstShootdown:skl */
 953         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 954                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 955
 956         /* Syncing dependencies between camera and graphics */
 957         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 958                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 959
 960         if (INTEL_REVID(dev) == SKL_REVID_A0 ||
 961             INTEL_REVID(dev) == SKL_REVID_B0) {
 962                 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
 963                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 964                                   GEN9_DG_MIRROR_FIX_ENABLE);
 965         }
 966
 967         if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
 968                 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
 969                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 970                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 971                 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
 972                                   DISABLE_PIXEL_MASK_CAMMING);
 973         }
 974
 975         if (INTEL_REVID(dev) >= SKL_REVID_C0) {
 976                 /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
 977                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 978                                   GEN9_ENABLE_YV12_BUGFIX);
 979         }
 980
 981         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
 982                 /*
 983                  *Use Force Non-Coherent whenever executing a 3D context. This
 984                  * is a workaround for a possible hang in the unlikely event
 985                  * a TLB invalidation occurs during a PSD flush.
 986                  */
 987                 /* WaForceEnableNonCoherent:skl */
 988                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
 989                                   HDC_FORCE_NON_COHERENT);
 990         }
 991
 992         /* Wa4x4STCOptimizationDisable:skl */
 993         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 994
 995         /* WaDisablePartialResolveInVc:skl */
 996         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 997
 998         /* WaCcsTlbPrefetchDisable:skl */
 999         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
1000                           GEN9_CCS_TLB_PREFETCH_ENABLE);
1001
1002         return 0;
1003 }
1004
1005 static int skl_init_workarounds(struct intel_engine_cs *ring)
1006 {
1007         gen9_init_workarounds(ring);
1008
1009         return 0;
1010 }
1011
1012 int init_workarounds_ring(struct intel_engine_cs *ring)
1013 {
1014         struct drm_device *dev = ring->dev;
1015         struct drm_i915_private *dev_priv = dev->dev_private;
1016
1017         WARN_ON(ring->id != RCS);
1018
1019         dev_priv->workarounds.count = 0;
1020
1021         if (IS_BROADWELL(dev))
1022                 return bdw_init_workarounds(ring);
1023
1024         if (IS_CHERRYVIEW(dev))
1025                 return chv_init_workarounds(ring);
1026
1027         if (IS_SKYLAKE(dev))
1028                 return skl_init_workarounds(ring);
1029         else if (IS_GEN9(dev))
1030                 return gen9_init_workarounds(ring);
1031
1032         return 0;
1033 }
1034
1035 static int init_render_ring(struct intel_engine_cs *ring)
1036 {
1037         struct drm_device *dev = ring->dev;
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039         int ret = init_ring_common(ring);
1040         if (ret)
1041                 return ret;
1042
1043         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1044         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1045                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1046
1047         /* We need to disable the AsyncFlip performance optimisations in order
1048          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1049          * programmed to '1' on all products.
1050          *
1051          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1052          */
1053         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1054                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1055
1056         /* Required for the hardware to program scanline values for waiting */
1057         /* WaEnableFlushTlbInvalidationMode:snb */
1058         if (INTEL_INFO(dev)->gen == 6)
1059                 I915_WRITE(GFX_MODE,
1060                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1061
1062         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1063         if (IS_GEN7(dev))
1064                 I915_WRITE(GFX_MODE_GEN7,
1065                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1066                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1067
1068         if (IS_GEN6(dev)) {
1069                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1070                  * "If this bit is set, STCunit will have LRA as replacement
1071                  *  policy. [...] This bit must be reset.  LRA replacement
1072                  *  policy is not supported."
1073                  */
1074                 I915_WRITE(CACHE_MODE_0,
1075                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1076         }
1077
1078         if (INTEL_INFO(dev)->gen >= 6)
1079                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1080
1081         if (HAS_L3_DPF(dev))
1082                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1083
1084         return init_workarounds_ring(ring);
1085 }
1086
1087 static void render_ring_cleanup(struct intel_engine_cs *ring)
1088 {
1089         struct drm_device *dev = ring->dev;
1090         struct drm_i915_private *dev_priv = dev->dev_private;
1091
1092         if (dev_priv->semaphore_obj) {
1093                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1094                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1095                 dev_priv->semaphore_obj = NULL;
1096         }
1097
1098         intel_fini_pipe_control(ring);
1099 }
1100
1101 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1102                            unsigned int num_dwords)
1103 {
1104 #define MBOX_UPDATE_DWORDS 8
1105         struct drm_device *dev = signaller->dev;
1106         struct drm_i915_private *dev_priv = dev->dev_private;
1107         struct intel_engine_cs *waiter;
1108         int i, ret, num_rings;
1109
1110         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1111         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1112 #undef MBOX_UPDATE_DWORDS
1113
1114         ret = intel_ring_begin(signaller, num_dwords);
1115         if (ret)
1116                 return ret;
1117
1118         for_each_ring(waiter, dev_priv, i) {
1119                 u32 seqno;
1120                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1121                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1122                         continue;
1123
1124                 seqno = i915_gem_request_get_seqno(
1125                                            signaller->outstanding_lazy_request);
1126                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1127                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1128                                            PIPE_CONTROL_QW_WRITE |
1129                                            PIPE_CONTROL_FLUSH_ENABLE);
1130                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1131                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1132                 intel_ring_emit(signaller, seqno);
1133                 intel_ring_emit(signaller, 0);
1134                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1135                                            MI_SEMAPHORE_TARGET(waiter->id));
1136                 intel_ring_emit(signaller, 0);
1137         }
1138
1139         return 0;
1140 }
1141
1142 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1143                            unsigned int num_dwords)
1144 {
1145 #define MBOX_UPDATE_DWORDS 6
1146         struct drm_device *dev = signaller->dev;
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148         struct intel_engine_cs *waiter;
1149         int i, ret, num_rings;
1150
1151         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1152         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1153 #undef MBOX_UPDATE_DWORDS
1154
1155         ret = intel_ring_begin(signaller, num_dwords);
1156         if (ret)
1157                 return ret;
1158
1159         for_each_ring(waiter, dev_priv, i) {
1160                 u32 seqno;
1161                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1162                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1163                         continue;
1164
1165                 seqno = i915_gem_request_get_seqno(
1166                                            signaller->outstanding_lazy_request);
1167                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1168                                            MI_FLUSH_DW_OP_STOREDW);
1169                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1170                                            MI_FLUSH_DW_USE_GTT);
1171                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1172                 intel_ring_emit(signaller, seqno);
1173                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1174                                            MI_SEMAPHORE_TARGET(waiter->id));
1175                 intel_ring_emit(signaller, 0);
1176         }
1177
1178         return 0;
1179 }
1180
1181 static int gen6_signal(struct intel_engine_cs *signaller,
1182                        unsigned int num_dwords)
1183 {
1184         struct drm_device *dev = signaller->dev;
1185         struct drm_i915_private *dev_priv = dev->dev_private;
1186         struct intel_engine_cs *useless;
1187         int i, ret, num_rings;
1188
1189 #define MBOX_UPDATE_DWORDS 3
1190         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1191         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1192 #undef MBOX_UPDATE_DWORDS
1193
1194         ret = intel_ring_begin(signaller, num_dwords);
1195         if (ret)
1196                 return ret;
1197
1198         for_each_ring(useless, dev_priv, i) {
1199                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1200                 if (mbox_reg != GEN6_NOSYNC) {
1201                         u32 seqno = i915_gem_request_get_seqno(
1202                                            signaller->outstanding_lazy_request);
1203                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1204                         intel_ring_emit(signaller, mbox_reg);
1205                         intel_ring_emit(signaller, seqno);
1206                 }
1207         }
1208
1209         /* If num_dwords was rounded, make sure the tail pointer is correct */
1210         if (num_rings % 2 == 0)
1211                 intel_ring_emit(signaller, MI_NOOP);
1212
1213         return 0;
1214 }
1215
1216 /**
1217  * gen6_add_request - Update the semaphore mailbox registers
1218  *
1219  * @ring - ring that is adding a request
1220  * @seqno - return seqno stuck into the ring
1221  *
1222  * Update the mailbox registers in the *other* rings with the current seqno.
1223  * This acts like a signal in the canonical semaphore.
1224  */
1225 static int
1226 gen6_add_request(struct intel_engine_cs *ring)
1227 {
1228         int ret;
1229
1230         if (ring->semaphore.signal)
1231                 ret = ring->semaphore.signal(ring, 4);
1232         else
1233                 ret = intel_ring_begin(ring, 4);
1234
1235         if (ret)
1236                 return ret;
1237
1238         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1239         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1240         intel_ring_emit(ring,
1241                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1242         intel_ring_emit(ring, MI_USER_INTERRUPT);
1243         __intel_ring_advance(ring);
1244
1245         return 0;
1246 }
1247
1248 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1249                                               u32 seqno)
1250 {
1251         struct drm_i915_private *dev_priv = dev->dev_private;
1252         return dev_priv->last_seqno < seqno;
1253 }
1254
1255 /**
1256  * intel_ring_sync - sync the waiter to the signaller on seqno
1257  *
1258  * @waiter - ring that is waiting
1259  * @signaller - ring which has, or will signal
1260  * @seqno - seqno which the waiter will block on
1261  */
1262
1263 static int
1264 gen8_ring_sync(struct intel_engine_cs *waiter,
1265                struct intel_engine_cs *signaller,
1266                u32 seqno)
1267 {
1268         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1269         int ret;
1270
1271         ret = intel_ring_begin(waiter, 4);
1272         if (ret)
1273                 return ret;
1274
1275         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1276                                 MI_SEMAPHORE_GLOBAL_GTT |
1277                                 MI_SEMAPHORE_POLL |
1278                                 MI_SEMAPHORE_SAD_GTE_SDD);
1279         intel_ring_emit(waiter, seqno);
1280         intel_ring_emit(waiter,
1281                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1282         intel_ring_emit(waiter,
1283                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1284         intel_ring_advance(waiter);
1285         return 0;
1286 }
1287
1288 static int
1289 gen6_ring_sync(struct intel_engine_cs *waiter,
1290                struct intel_engine_cs *signaller,
1291                u32 seqno)
1292 {
1293         u32 dw1 = MI_SEMAPHORE_MBOX |
1294                   MI_SEMAPHORE_COMPARE |
1295                   MI_SEMAPHORE_REGISTER;
1296         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1297         int ret;
1298
1299         /* Throughout all of the GEM code, seqno passed implies our current
1300          * seqno is >= the last seqno executed. However for hardware the
1301          * comparison is strictly greater than.
1302          */
1303         seqno -= 1;
1304
1305         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1306
1307         ret = intel_ring_begin(waiter, 4);
1308         if (ret)
1309                 return ret;
1310
1311         /* If seqno wrap happened, omit the wait with no-ops */
1312         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1313                 intel_ring_emit(waiter, dw1 | wait_mbox);
1314                 intel_ring_emit(waiter, seqno);
1315                 intel_ring_emit(waiter, 0);
1316                 intel_ring_emit(waiter, MI_NOOP);
1317         } else {
1318                 intel_ring_emit(waiter, MI_NOOP);
1319                 intel_ring_emit(waiter, MI_NOOP);
1320                 intel_ring_emit(waiter, MI_NOOP);
1321                 intel_ring_emit(waiter, MI_NOOP);
1322         }
1323         intel_ring_advance(waiter);
1324
1325         return 0;
1326 }
1327
1328 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1329 do {                                                                    \
1330         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1331                  PIPE_CONTROL_DEPTH_STALL);                             \
1332         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1333         intel_ring_emit(ring__, 0);                                                     \
1334         intel_ring_emit(ring__, 0);                                                     \
1335 } while (0)
1336
1337 static int
1338 pc_render_add_request(struct intel_engine_cs *ring)
1339 {
1340         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1341         int ret;
1342
1343         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1344          * incoherent with writes to memory, i.e. completely fubar,
1345          * so we need to use PIPE_NOTIFY instead.
1346          *
1347          * However, we also need to workaround the qword write
1348          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1349          * memory before requesting an interrupt.
1350          */
1351         ret = intel_ring_begin(ring, 32);
1352         if (ret)
1353                 return ret;
1354
1355         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1356                         PIPE_CONTROL_WRITE_FLUSH |
1357                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1358         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1359         intel_ring_emit(ring,
1360                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1361         intel_ring_emit(ring, 0);
1362         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1363         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1364         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1365         scratch_addr += 2 * CACHELINE_BYTES;
1366         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1367         scratch_addr += 2 * CACHELINE_BYTES;
1368         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1369         scratch_addr += 2 * CACHELINE_BYTES;
1370         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1371         scratch_addr += 2 * CACHELINE_BYTES;
1372         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1373
1374         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1375                         PIPE_CONTROL_WRITE_FLUSH |
1376                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1377                         PIPE_CONTROL_NOTIFY);
1378         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1379         intel_ring_emit(ring,
1380                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1381         intel_ring_emit(ring, 0);
1382         __intel_ring_advance(ring);
1383
1384         return 0;
1385 }
1386
1387 static u32
1388 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1389 {
1390         /* Workaround to force correct ordering between irq and seqno writes on
1391          * ivb (and maybe also on snb) by reading from a CS register (like
1392          * ACTHD) before reading the status page. */
1393         if (!lazy_coherency) {
1394                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1395                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1396         }
1397
1398         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1399 }
1400
1401 static u32
1402 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1403 {
1404         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1405 }
1406
1407 static void
1408 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1409 {
1410         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1411 }
1412
1413 static u32
1414 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1415 {
1416         return ring->scratch.cpu_page[0];
1417 }
1418
1419 static void
1420 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1421 {
1422         ring->scratch.cpu_page[0] = seqno;
1423 }
1424
1425 static bool
1426 gen5_ring_get_irq(struct intel_engine_cs *ring)
1427 {
1428         struct drm_device *dev = ring->dev;
1429         struct drm_i915_private *dev_priv = dev->dev_private;
1430         unsigned long flags;
1431
1432         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1433                 return false;
1434
1435         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1436         if (ring->irq_refcount++ == 0)
1437                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1438         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1439
1440         return true;
1441 }
1442
1443 static void
1444 gen5_ring_put_irq(struct intel_engine_cs *ring)
1445 {
1446         struct drm_device *dev = ring->dev;
1447         struct drm_i915_private *dev_priv = dev->dev_private;
1448         unsigned long flags;
1449
1450         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1451         if (--ring->irq_refcount == 0)
1452                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1453         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1454 }
1455
1456 static bool
1457 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1458 {
1459         struct drm_device *dev = ring->dev;
1460         struct drm_i915_private *dev_priv = dev->dev_private;
1461         unsigned long flags;
1462
1463         if (!intel_irqs_enabled(dev_priv))
1464                 return false;
1465
1466         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1467         if (ring->irq_refcount++ == 0) {
1468                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1469                 I915_WRITE(IMR, dev_priv->irq_mask);
1470                 POSTING_READ(IMR);
1471         }
1472         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1473
1474         return true;
1475 }
1476
1477 static void
1478 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1479 {
1480         struct drm_device *dev = ring->dev;
1481         struct drm_i915_private *dev_priv = dev->dev_private;
1482         unsigned long flags;
1483
1484         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1485         if (--ring->irq_refcount == 0) {
1486                 dev_priv->irq_mask |= ring->irq_enable_mask;
1487                 I915_WRITE(IMR, dev_priv->irq_mask);
1488                 POSTING_READ(IMR);
1489         }
1490         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1491 }
1492
1493 static bool
1494 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1495 {
1496         struct drm_device *dev = ring->dev;
1497         struct drm_i915_private *dev_priv = dev->dev_private;
1498         unsigned long flags;
1499
1500         if (!intel_irqs_enabled(dev_priv))
1501                 return false;
1502
1503         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1504         if (ring->irq_refcount++ == 0) {
1505                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1506                 I915_WRITE16(IMR, dev_priv->irq_mask);
1507                 POSTING_READ16(IMR);
1508         }
1509         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1510
1511         return true;
1512 }
1513
1514 static void
1515 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1516 {
1517         struct drm_device *dev = ring->dev;
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519         unsigned long flags;
1520
1521         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1522         if (--ring->irq_refcount == 0) {
1523                 dev_priv->irq_mask |= ring->irq_enable_mask;
1524                 I915_WRITE16(IMR, dev_priv->irq_mask);
1525                 POSTING_READ16(IMR);
1526         }
1527         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1528 }
1529
1530 static int
1531 bsd_ring_flush(struct intel_engine_cs *ring,
1532                u32     invalidate_domains,
1533                u32     flush_domains)
1534 {
1535         int ret;
1536
1537         ret = intel_ring_begin(ring, 2);
1538         if (ret)
1539                 return ret;
1540
1541         intel_ring_emit(ring, MI_FLUSH);
1542         intel_ring_emit(ring, MI_NOOP);
1543         intel_ring_advance(ring);
1544         return 0;
1545 }
1546
1547 static int
1548 i9xx_add_request(struct intel_engine_cs *ring)
1549 {
1550         int ret;
1551
1552         ret = intel_ring_begin(ring, 4);
1553         if (ret)
1554                 return ret;
1555
1556         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1557         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1558         intel_ring_emit(ring,
1559                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1560         intel_ring_emit(ring, MI_USER_INTERRUPT);
1561         __intel_ring_advance(ring);
1562
1563         return 0;
1564 }
1565
1566 static bool
1567 gen6_ring_get_irq(struct intel_engine_cs *ring)
1568 {
1569         struct drm_device *dev = ring->dev;
1570         struct drm_i915_private *dev_priv = dev->dev_private;
1571         unsigned long flags;
1572
1573         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1574                 return false;
1575
1576         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1577         if (ring->irq_refcount++ == 0) {
1578                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1579                         I915_WRITE_IMR(ring,
1580                                        ~(ring->irq_enable_mask |
1581                                          GT_PARITY_ERROR(dev)));
1582                 else
1583                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1584                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1585         }
1586         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1587
1588         return true;
1589 }
1590
1591 static void
1592 gen6_ring_put_irq(struct intel_engine_cs *ring)
1593 {
1594         struct drm_device *dev = ring->dev;
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596         unsigned long flags;
1597
1598         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1599         if (--ring->irq_refcount == 0) {
1600                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1601                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1602                 else
1603                         I915_WRITE_IMR(ring, ~0);
1604                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1605         }
1606         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1607 }
1608
1609 static bool
1610 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1611 {
1612         struct drm_device *dev = ring->dev;
1613         struct drm_i915_private *dev_priv = dev->dev_private;
1614         unsigned long flags;
1615
1616         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1617                 return false;
1618
1619         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1620         if (ring->irq_refcount++ == 0) {
1621                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1622                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1623         }
1624         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1625
1626         return true;
1627 }
1628
1629 static void
1630 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1631 {
1632         struct drm_device *dev = ring->dev;
1633         struct drm_i915_private *dev_priv = dev->dev_private;
1634         unsigned long flags;
1635
1636         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1637         if (--ring->irq_refcount == 0) {
1638                 I915_WRITE_IMR(ring, ~0);
1639                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1640         }
1641         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1642 }
1643
1644 static bool
1645 gen8_ring_get_irq(struct intel_engine_cs *ring)
1646 {
1647         struct drm_device *dev = ring->dev;
1648         struct drm_i915_private *dev_priv = dev->dev_private;
1649         unsigned long flags;
1650
1651         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1652                 return false;
1653
1654         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1655         if (ring->irq_refcount++ == 0) {
1656                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1657                         I915_WRITE_IMR(ring,
1658                                        ~(ring->irq_enable_mask |
1659                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1660                 } else {
1661                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1662                 }
1663                 POSTING_READ(RING_IMR(ring->mmio_base));
1664         }
1665         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1666
1667         return true;
1668 }
1669
1670 static void
1671 gen8_ring_put_irq(struct intel_engine_cs *ring)
1672 {
1673         struct drm_device *dev = ring->dev;
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675         unsigned long flags;
1676
1677         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1678         if (--ring->irq_refcount == 0) {
1679                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1680                         I915_WRITE_IMR(ring,
1681                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1682                 } else {
1683                         I915_WRITE_IMR(ring, ~0);
1684                 }
1685                 POSTING_READ(RING_IMR(ring->mmio_base));
1686         }
1687         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1688 }
1689
1690 static int
1691 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1692                          u64 offset, u32 length,
1693                          unsigned flags)
1694 {
1695         int ret;
1696
1697         ret = intel_ring_begin(ring, 2);
1698         if (ret)
1699                 return ret;
1700
1701         intel_ring_emit(ring,
1702                         MI_BATCH_BUFFER_START |
1703                         MI_BATCH_GTT |
1704                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1705         intel_ring_emit(ring, offset);
1706         intel_ring_advance(ring);
1707
1708         return 0;
1709 }
1710
1711 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1712 #define I830_BATCH_LIMIT (256*1024)
1713 #define I830_TLB_ENTRIES (2)
1714 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1715 static int
1716 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1717                                 u64 offset, u32 len,
1718                                 unsigned flags)
1719 {
1720         u32 cs_offset = ring->scratch.gtt_offset;
1721         int ret;
1722
1723         ret = intel_ring_begin(ring, 6);
1724         if (ret)
1725                 return ret;
1726
1727         /* Evict the invalid PTE TLBs */
1728         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1729         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1730         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1731         intel_ring_emit(ring, cs_offset);
1732         intel_ring_emit(ring, 0xdeadbeef);
1733         intel_ring_emit(ring, MI_NOOP);
1734         intel_ring_advance(ring);
1735
1736         if ((flags & I915_DISPATCH_PINNED) == 0) {
1737                 if (len > I830_BATCH_LIMIT)
1738                         return -ENOSPC;
1739
1740                 ret = intel_ring_begin(ring, 6 + 2);
1741                 if (ret)
1742                         return ret;
1743
1744                 /* Blit the batch (which has now all relocs applied) to the
1745                  * stable batch scratch bo area (so that the CS never
1746                  * stumbles over its tlb invalidation bug) ...
1747                  */
1748                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1749                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1750                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1751                 intel_ring_emit(ring, cs_offset);
1752                 intel_ring_emit(ring, 4096);
1753                 intel_ring_emit(ring, offset);
1754
1755                 intel_ring_emit(ring, MI_FLUSH);
1756                 intel_ring_emit(ring, MI_NOOP);
1757                 intel_ring_advance(ring);
1758
1759                 /* ... and execute it. */
1760                 offset = cs_offset;
1761         }
1762
1763         ret = intel_ring_begin(ring, 4);
1764         if (ret)
1765                 return ret;
1766
1767         intel_ring_emit(ring, MI_BATCH_BUFFER);
1768         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1769         intel_ring_emit(ring, offset + len - 8);
1770         intel_ring_emit(ring, MI_NOOP);
1771         intel_ring_advance(ring);
1772
1773         return 0;
1774 }
1775
1776 static int
1777 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1778                          u64 offset, u32 len,
1779                          unsigned flags)
1780 {
1781         int ret;
1782
1783         ret = intel_ring_begin(ring, 2);
1784         if (ret)
1785                 return ret;
1786
1787         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1788         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1789         intel_ring_advance(ring);
1790
1791         return 0;
1792 }
1793
1794 static void cleanup_status_page(struct intel_engine_cs *ring)
1795 {
1796         struct drm_i915_gem_object *obj;
1797
1798         obj = ring->status_page.obj;
1799         if (obj == NULL)
1800                 return;
1801
1802         kunmap(sg_page(obj->pages->sgl));
1803         i915_gem_object_ggtt_unpin(obj);
1804         drm_gem_object_unreference(&obj->base);
1805         ring->status_page.obj = NULL;
1806 }
1807
1808 static int init_status_page(struct intel_engine_cs *ring)
1809 {
1810         struct drm_i915_gem_object *obj;
1811
1812         if ((obj = ring->status_page.obj) == NULL) {
1813                 unsigned flags;
1814                 int ret;
1815
1816                 obj = i915_gem_alloc_object(ring->dev, 4096);
1817                 if (obj == NULL) {
1818                         DRM_ERROR("Failed to allocate status page\n");
1819                         return -ENOMEM;
1820                 }
1821
1822                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1823                 if (ret)
1824                         goto err_unref;
1825
1826                 flags = 0;
1827                 if (!HAS_LLC(ring->dev))
1828                         /* On g33, we cannot place HWS above 256MiB, so
1829                          * restrict its pinning to the low mappable arena.
1830                          * Though this restriction is not documented for
1831                          * gen4, gen5, or byt, they also behave similarly
1832                          * and hang if the HWS is placed at the top of the
1833                          * GTT. To generalise, it appears that all !llc
1834                          * platforms have issues with us placing the HWS
1835                          * above the mappable region (even though we never
1836                          * actualy map it).
1837                          */
1838                         flags |= PIN_MAPPABLE;
1839                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1840                 if (ret) {
1841 err_unref:
1842                         drm_gem_object_unreference(&obj->base);
1843                         return ret;
1844                 }
1845
1846                 ring->status_page.obj = obj;
1847         }
1848
1849         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1850         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1851         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1852
1853         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1854                         ring->name, ring->status_page.gfx_addr);
1855
1856         return 0;
1857 }
1858
1859 static int init_phys_status_page(struct intel_engine_cs *ring)
1860 {
1861         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1862
1863         if (!dev_priv->status_page_dmah) {
1864                 dev_priv->status_page_dmah =
1865                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1866                 if (!dev_priv->status_page_dmah)
1867                         return -ENOMEM;
1868         }
1869
1870         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1871         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1872
1873         return 0;
1874 }
1875
1876 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1877 {
1878         iounmap(ringbuf->virtual_start);
1879         ringbuf->virtual_start = NULL;
1880         i915_gem_object_ggtt_unpin(ringbuf->obj);
1881 }
1882
1883 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1884                                      struct intel_ringbuffer *ringbuf)
1885 {
1886         struct drm_i915_private *dev_priv = to_i915(dev);
1887         struct drm_i915_gem_object *obj = ringbuf->obj;
1888         int ret;
1889
1890         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1891         if (ret)
1892                 return ret;
1893
1894         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1895         if (ret) {
1896                 i915_gem_object_ggtt_unpin(obj);
1897                 return ret;
1898         }
1899
1900         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1901                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1902         if (ringbuf->virtual_start == NULL) {
1903                 i915_gem_object_ggtt_unpin(obj);
1904                 return -EINVAL;
1905         }
1906
1907         return 0;
1908 }
1909
1910 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1911 {
1912         drm_gem_object_unreference(&ringbuf->obj->base);
1913         ringbuf->obj = NULL;
1914 }
1915
1916 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1917                                struct intel_ringbuffer *ringbuf)
1918 {
1919         struct drm_i915_gem_object *obj;
1920
1921         obj = NULL;
1922         if (!HAS_LLC(dev))
1923                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1924         if (obj == NULL)
1925                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1926         if (obj == NULL)
1927                 return -ENOMEM;
1928
1929         /* mark ring buffers as read-only from GPU side by default */
1930         obj->gt_ro = 1;
1931
1932         ringbuf->obj = obj;
1933
1934         return 0;
1935 }
1936
1937 static int intel_init_ring_buffer(struct drm_device *dev,
1938                                   struct intel_engine_cs *ring)
1939 {
1940         struct intel_ringbuffer *ringbuf;
1941         int ret;
1942
1943         WARN_ON(ring->buffer);
1944
1945         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1946         if (!ringbuf)
1947                 return -ENOMEM;
1948         ring->buffer = ringbuf;
1949
1950         ring->dev = dev;
1951         INIT_LIST_HEAD(&ring->active_list);
1952         INIT_LIST_HEAD(&ring->request_list);
1953         INIT_LIST_HEAD(&ring->execlist_queue);
1954         ringbuf->size = 32 * PAGE_SIZE;
1955         ringbuf->ring = ring;
1956         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1957
1958         init_waitqueue_head(&ring->irq_queue);
1959
1960         if (I915_NEED_GFX_HWS(dev)) {
1961                 ret = init_status_page(ring);
1962                 if (ret)
1963                         goto error;
1964         } else {
1965                 BUG_ON(ring->id != RCS);
1966                 ret = init_phys_status_page(ring);
1967                 if (ret)
1968                         goto error;
1969         }
1970
1971         WARN_ON(ringbuf->obj);
1972
1973         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1974         if (ret) {
1975                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1976                                 ring->name, ret);
1977                 goto error;
1978         }
1979
1980         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1981         if (ret) {
1982                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1983                                 ring->name, ret);
1984                 intel_destroy_ringbuffer_obj(ringbuf);
1985                 goto error;
1986         }
1987
1988         /* Workaround an erratum on the i830 which causes a hang if
1989          * the TAIL pointer points to within the last 2 cachelines
1990          * of the buffer.
1991          */
1992         ringbuf->effective_size = ringbuf->size;
1993         if (IS_I830(dev) || IS_845G(dev))
1994                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1995
1996         ret = i915_cmd_parser_init_ring(ring);
1997         if (ret)
1998                 goto error;
1999
2000         return 0;
2001
2002 error:
2003         kfree(ringbuf);
2004         ring->buffer = NULL;
2005         return ret;
2006 }
2007
2008 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2009 {
2010         struct drm_i915_private *dev_priv;
2011         struct intel_ringbuffer *ringbuf;
2012
2013         if (!intel_ring_initialized(ring))
2014                 return;
2015
2016         dev_priv = to_i915(ring->dev);
2017         ringbuf = ring->buffer;
2018
2019         intel_stop_ring_buffer(ring);
2020         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2021
2022         intel_unpin_ringbuffer_obj(ringbuf);
2023         intel_destroy_ringbuffer_obj(ringbuf);
2024         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2025
2026         if (ring->cleanup)
2027                 ring->cleanup(ring);
2028
2029         cleanup_status_page(ring);
2030
2031         i915_cmd_parser_fini_ring(ring);
2032
2033         kfree(ringbuf);
2034         ring->buffer = NULL;
2035 }
2036
2037 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
2038 {
2039         struct intel_ringbuffer *ringbuf = ring->buffer;
2040         struct drm_i915_gem_request *request;
2041         int ret;
2042
2043         if (intel_ring_space(ringbuf) >= n)
2044                 return 0;
2045
2046         list_for_each_entry(request, &ring->request_list, list) {
2047                 if (__intel_ring_space(request->postfix, ringbuf->tail,
2048                                        ringbuf->size) >= n) {
2049                         break;
2050                 }
2051         }
2052
2053         if (&request->list == &ring->request_list)
2054                 return -ENOSPC;
2055
2056         ret = i915_wait_request(request);
2057         if (ret)
2058                 return ret;
2059
2060         i915_gem_retire_requests_ring(ring);
2061
2062         return 0;
2063 }
2064
2065 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2066 {
2067         struct drm_device *dev = ring->dev;
2068         struct drm_i915_private *dev_priv = dev->dev_private;
2069         struct intel_ringbuffer *ringbuf = ring->buffer;
2070         unsigned long end;
2071         int ret;
2072
2073         ret = intel_ring_wait_request(ring, n);
2074         if (ret != -ENOSPC)
2075                 return ret;
2076
2077         /* force the tail write in case we have been skipping them */
2078         __intel_ring_advance(ring);
2079
2080         /* With GEM the hangcheck timer should kick us out of the loop,
2081          * leaving it early runs the risk of corrupting GEM state (due
2082          * to running on almost untested codepaths). But on resume
2083          * timers don't work yet, so prevent a complete hang in that
2084          * case by choosing an insanely large timeout. */
2085         end = jiffies + 60 * HZ;
2086
2087         ret = 0;
2088         trace_i915_ring_wait_begin(ring);
2089         do {
2090                 if (intel_ring_space(ringbuf) >= n)
2091                         break;
2092                 ringbuf->head = I915_READ_HEAD(ring);
2093                 if (intel_ring_space(ringbuf) >= n)
2094                         break;
2095
2096                 msleep(1);
2097
2098                 if (dev_priv->mm.interruptible && signal_pending(current)) {
2099                         ret = -ERESTARTSYS;
2100                         break;
2101                 }
2102
2103                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2104                                            dev_priv->mm.interruptible);
2105                 if (ret)
2106                         break;
2107
2108                 if (time_after(jiffies, end)) {
2109                         ret = -EBUSY;
2110                         break;
2111                 }
2112         } while (1);
2113         trace_i915_ring_wait_end(ring);
2114         return ret;
2115 }
2116
2117 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2118 {
2119         uint32_t __iomem *virt;
2120         struct intel_ringbuffer *ringbuf = ring->buffer;
2121         int rem = ringbuf->size - ringbuf->tail;
2122
2123         if (ringbuf->space < rem) {
2124                 int ret = ring_wait_for_space(ring, rem);
2125                 if (ret)
2126                         return ret;
2127         }
2128
2129         virt = ringbuf->virtual_start + ringbuf->tail;
2130         rem /= 4;
2131         while (rem--)
2132                 iowrite32(MI_NOOP, virt++);
2133
2134         ringbuf->tail = 0;
2135         intel_ring_update_space(ringbuf);
2136
2137         return 0;
2138 }
2139
2140 int intel_ring_idle(struct intel_engine_cs *ring)
2141 {
2142         struct drm_i915_gem_request *req;
2143         int ret;
2144
2145         /* We need to add any requests required to flush the objects and ring */
2146         if (ring->outstanding_lazy_request) {
2147                 ret = i915_add_request(ring);
2148                 if (ret)
2149                         return ret;
2150         }
2151
2152         /* Wait upon the last request to be completed */
2153         if (list_empty(&ring->request_list))
2154                 return 0;
2155
2156         req = list_entry(ring->request_list.prev,
2157                            struct drm_i915_gem_request,
2158                            list);
2159
2160         return i915_wait_request(req);
2161 }
2162
2163 static int
2164 intel_ring_alloc_request(struct intel_engine_cs *ring)
2165 {
2166         int ret;
2167         struct drm_i915_gem_request *request;
2168         struct drm_i915_private *dev_private = ring->dev->dev_private;
2169
2170         if (ring->outstanding_lazy_request)
2171                 return 0;
2172
2173         request = kzalloc(sizeof(*request), GFP_KERNEL);
2174         if (request == NULL)
2175                 return -ENOMEM;
2176
2177         kref_init(&request->ref);
2178         request->ring = ring;
2179         request->uniq = dev_private->request_uniq++;
2180
2181         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
2182         if (ret) {
2183                 kfree(request);
2184                 return ret;
2185         }
2186
2187         ring->outstanding_lazy_request = request;
2188         return 0;
2189 }
2190
2191 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2192                                 int bytes)
2193 {
2194         struct intel_ringbuffer *ringbuf = ring->buffer;
2195         int ret;
2196
2197         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2198                 ret = intel_wrap_ring_buffer(ring);
2199                 if (unlikely(ret))
2200                         return ret;
2201         }
2202
2203         if (unlikely(ringbuf->space < bytes)) {
2204                 ret = ring_wait_for_space(ring, bytes);
2205                 if (unlikely(ret))
2206                         return ret;
2207         }
2208
2209         return 0;
2210 }
2211
2212 int intel_ring_begin(struct intel_engine_cs *ring,
2213                      int num_dwords)
2214 {
2215         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2216         int ret;
2217
2218         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2219                                    dev_priv->mm.interruptible);
2220         if (ret)
2221                 return ret;
2222
2223         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2224         if (ret)
2225                 return ret;
2226
2227         /* Preallocate the olr before touching the ring */
2228         ret = intel_ring_alloc_request(ring);
2229         if (ret)
2230                 return ret;
2231
2232         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2233         return 0;
2234 }
2235
2236 /* Align the ring tail to a cacheline boundary */
2237 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2238 {
2239         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2240         int ret;
2241
2242         if (num_dwords == 0)
2243                 return 0;
2244
2245         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2246         ret = intel_ring_begin(ring, num_dwords);
2247         if (ret)
2248                 return ret;
2249
2250         while (num_dwords--)
2251                 intel_ring_emit(ring, MI_NOOP);
2252
2253         intel_ring_advance(ring);
2254
2255         return 0;
2256 }
2257
2258 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2259 {
2260         struct drm_device *dev = ring->dev;
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262
2263         BUG_ON(ring->outstanding_lazy_request);
2264
2265         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2266                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2267                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2268                 if (HAS_VEBOX(dev))
2269                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2270         }
2271
2272         ring->set_seqno(ring, seqno);
2273         ring->hangcheck.seqno = seqno;
2274 }
2275
2276 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2277                                      u32 value)
2278 {
2279         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2280
2281        /* Every tail move must follow the sequence below */
2282
2283         /* Disable notification that the ring is IDLE. The GT
2284          * will then assume that it is busy and bring it out of rc6.
2285          */
2286         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2287                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2288
2289         /* Clear the context id. Here be magic! */
2290         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2291
2292         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2293         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2294                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2295                      50))
2296                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2297
2298         /* Now that the ring is fully powered up, update the tail */
2299         I915_WRITE_TAIL(ring, value);
2300         POSTING_READ(RING_TAIL(ring->mmio_base));
2301
2302         /* Let the ring send IDLE messages to the GT again,
2303          * and so let it sleep to conserve power when idle.
2304          */
2305         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2306                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2307 }
2308
2309 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2310                                u32 invalidate, u32 flush)
2311 {
2312         uint32_t cmd;
2313         int ret;
2314
2315         ret = intel_ring_begin(ring, 4);
2316         if (ret)
2317                 return ret;
2318
2319         cmd = MI_FLUSH_DW;
2320         if (INTEL_INFO(ring->dev)->gen >= 8)
2321                 cmd += 1;
2322
2323         /* We always require a command barrier so that subsequent
2324          * commands, such as breadcrumb interrupts, are strictly ordered
2325          * wrt the contents of the write cache being flushed to memory
2326          * (and thus being coherent from the CPU).
2327          */
2328         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2329
2330         /*
2331          * Bspec vol 1c.5 - video engine command streamer:
2332          * "If ENABLED, all TLBs will be invalidated once the flush
2333          * operation is complete. This bit is only valid when the
2334          * Post-Sync Operation field is a value of 1h or 3h."
2335          */
2336         if (invalidate & I915_GEM_GPU_DOMAINS)
2337                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2338
2339         intel_ring_emit(ring, cmd);
2340         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2341         if (INTEL_INFO(ring->dev)->gen >= 8) {
2342                 intel_ring_emit(ring, 0); /* upper addr */
2343                 intel_ring_emit(ring, 0); /* value */
2344         } else  {
2345                 intel_ring_emit(ring, 0);
2346                 intel_ring_emit(ring, MI_NOOP);
2347         }
2348         intel_ring_advance(ring);
2349         return 0;
2350 }
2351
2352 static int
2353 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2354                               u64 offset, u32 len,
2355                               unsigned flags)
2356 {
2357         bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2358         int ret;
2359
2360         ret = intel_ring_begin(ring, 4);
2361         if (ret)
2362                 return ret;
2363
2364         /* FIXME(BDW): Address space and security selectors. */
2365         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2366         intel_ring_emit(ring, lower_32_bits(offset));
2367         intel_ring_emit(ring, upper_32_bits(offset));
2368         intel_ring_emit(ring, MI_NOOP);
2369         intel_ring_advance(ring);
2370
2371         return 0;
2372 }
2373
2374 static int
2375 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2376                               u64 offset, u32 len,
2377                               unsigned flags)
2378 {
2379         int ret;
2380
2381         ret = intel_ring_begin(ring, 2);
2382         if (ret)
2383                 return ret;
2384
2385         intel_ring_emit(ring,
2386                         MI_BATCH_BUFFER_START |
2387                         (flags & I915_DISPATCH_SECURE ?
2388                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2389         /* bit0-7 is the length on GEN6+ */
2390         intel_ring_emit(ring, offset);
2391         intel_ring_advance(ring);
2392
2393         return 0;
2394 }
2395
2396 static int
2397 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2398                               u64 offset, u32 len,
2399                               unsigned flags)
2400 {
2401         int ret;
2402
2403         ret = intel_ring_begin(ring, 2);
2404         if (ret)
2405                 return ret;
2406
2407         intel_ring_emit(ring,
2408                         MI_BATCH_BUFFER_START |
2409                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2410         /* bit0-7 is the length on GEN6+ */
2411         intel_ring_emit(ring, offset);
2412         intel_ring_advance(ring);
2413
2414         return 0;
2415 }
2416
2417 /* Blitter support (SandyBridge+) */
2418
2419 static int gen6_ring_flush(struct intel_engine_cs *ring,
2420                            u32 invalidate, u32 flush)
2421 {
2422         struct drm_device *dev = ring->dev;
2423         struct drm_i915_private *dev_priv = dev->dev_private;
2424         uint32_t cmd;
2425         int ret;
2426
2427         ret = intel_ring_begin(ring, 4);
2428         if (ret)
2429                 return ret;
2430
2431         cmd = MI_FLUSH_DW;
2432         if (INTEL_INFO(ring->dev)->gen >= 8)
2433                 cmd += 1;
2434
2435         /* We always require a command barrier so that subsequent
2436          * commands, such as breadcrumb interrupts, are strictly ordered
2437          * wrt the contents of the write cache being flushed to memory
2438          * (and thus being coherent from the CPU).
2439          */
2440         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2441
2442         /*
2443          * Bspec vol 1c.3 - blitter engine command streamer:
2444          * "If ENABLED, all TLBs will be invalidated once the flush
2445          * operation is complete. This bit is only valid when the
2446          * Post-Sync Operation field is a value of 1h or 3h."
2447          */
2448         if (invalidate & I915_GEM_DOMAIN_RENDER)
2449                 cmd |= MI_INVALIDATE_TLB;
2450         intel_ring_emit(ring, cmd);
2451         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2452         if (INTEL_INFO(ring->dev)->gen >= 8) {
2453                 intel_ring_emit(ring, 0); /* upper addr */
2454                 intel_ring_emit(ring, 0); /* value */
2455         } else  {
2456                 intel_ring_emit(ring, 0);
2457                 intel_ring_emit(ring, MI_NOOP);
2458         }
2459         intel_ring_advance(ring);
2460
2461         if (!invalidate && flush) {
2462                 if (IS_GEN7(dev))
2463                         return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2464                 else if (IS_BROADWELL(dev))
2465                         dev_priv->fbc.need_sw_cache_clean = true;
2466         }
2467
2468         return 0;
2469 }
2470
2471 int intel_init_render_ring_buffer(struct drm_device *dev)
2472 {
2473         struct drm_i915_private *dev_priv = dev->dev_private;
2474         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2475         struct drm_i915_gem_object *obj;
2476         int ret;
2477
2478         ring->name = "render ring";
2479         ring->id = RCS;
2480         ring->mmio_base = RENDER_RING_BASE;
2481
2482         if (INTEL_INFO(dev)->gen >= 8) {
2483                 if (i915_semaphore_is_enabled(dev)) {
2484                         obj = i915_gem_alloc_object(dev, 4096);
2485                         if (obj == NULL) {
2486                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2487                                 i915.semaphores = 0;
2488                         } else {
2489                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2490                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2491                                 if (ret != 0) {
2492                                         drm_gem_object_unreference(&obj->base);
2493                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2494                                         i915.semaphores = 0;
2495                                 } else
2496                                         dev_priv->semaphore_obj = obj;
2497                         }
2498                 }
2499
2500                 ring->init_context = intel_rcs_ctx_init;
2501                 ring->add_request = gen6_add_request;
2502                 ring->flush = gen8_render_ring_flush;
2503                 ring->irq_get = gen8_ring_get_irq;
2504                 ring->irq_put = gen8_ring_put_irq;
2505                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2506                 ring->get_seqno = gen6_ring_get_seqno;
2507                 ring->set_seqno = ring_set_seqno;
2508                 if (i915_semaphore_is_enabled(dev)) {
2509                         WARN_ON(!dev_priv->semaphore_obj);
2510                         ring->semaphore.sync_to = gen8_ring_sync;
2511                         ring->semaphore.signal = gen8_rcs_signal;
2512                         GEN8_RING_SEMAPHORE_INIT;
2513                 }
2514         } else if (INTEL_INFO(dev)->gen >= 6) {
2515                 ring->add_request = gen6_add_request;
2516                 ring->flush = gen7_render_ring_flush;
2517                 if (INTEL_INFO(dev)->gen == 6)
2518                         ring->flush = gen6_render_ring_flush;
2519                 ring->irq_get = gen6_ring_get_irq;
2520                 ring->irq_put = gen6_ring_put_irq;
2521                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2522                 ring->get_seqno = gen6_ring_get_seqno;
2523                 ring->set_seqno = ring_set_seqno;
2524                 if (i915_semaphore_is_enabled(dev)) {
2525                         ring->semaphore.sync_to = gen6_ring_sync;
2526                         ring->semaphore.signal = gen6_signal;
2527                         /*
2528                          * The current semaphore is only applied on pre-gen8
2529                          * platform.  And there is no VCS2 ring on the pre-gen8
2530                          * platform. So the semaphore between RCS and VCS2 is
2531                          * initialized as INVALID.  Gen8 will initialize the
2532                          * sema between VCS2 and RCS later.
2533                          */
2534                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2535                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2536                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2537                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2538                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2539                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2540                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2541                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2542                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2543                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2544                 }
2545         } else if (IS_GEN5(dev)) {
2546                 ring->add_request = pc_render_add_request;
2547                 ring->flush = gen4_render_ring_flush;
2548                 ring->get_seqno = pc_render_get_seqno;
2549                 ring->set_seqno = pc_render_set_seqno;
2550                 ring->irq_get = gen5_ring_get_irq;
2551                 ring->irq_put = gen5_ring_put_irq;
2552                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2553                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2554         } else {
2555                 ring->add_request = i9xx_add_request;
2556                 if (INTEL_INFO(dev)->gen < 4)
2557                         ring->flush = gen2_render_ring_flush;
2558                 else
2559                         ring->flush = gen4_render_ring_flush;
2560                 ring->get_seqno = ring_get_seqno;
2561                 ring->set_seqno = ring_set_seqno;
2562                 if (IS_GEN2(dev)) {
2563                         ring->irq_get = i8xx_ring_get_irq;
2564                         ring->irq_put = i8xx_ring_put_irq;
2565                 } else {
2566                         ring->irq_get = i9xx_ring_get_irq;
2567                         ring->irq_put = i9xx_ring_put_irq;
2568                 }
2569                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2570         }
2571         ring->write_tail = ring_write_tail;
2572
2573         if (IS_HASWELL(dev))
2574                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2575         else if (IS_GEN8(dev))
2576                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2577         else if (INTEL_INFO(dev)->gen >= 6)
2578                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2579         else if (INTEL_INFO(dev)->gen >= 4)
2580                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2581         else if (IS_I830(dev) || IS_845G(dev))
2582                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2583         else
2584                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2585         ring->init_hw = init_render_ring;
2586         ring->cleanup = render_ring_cleanup;
2587
2588         /* Workaround batchbuffer to combat CS tlb bug. */
2589         if (HAS_BROKEN_CS_TLB(dev)) {
2590                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2591                 if (obj == NULL) {
2592                         DRM_ERROR("Failed to allocate batch bo\n");
2593                         return -ENOMEM;
2594                 }
2595
2596                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2597                 if (ret != 0) {
2598                         drm_gem_object_unreference(&obj->base);
2599                         DRM_ERROR("Failed to ping batch bo\n");
2600                         return ret;
2601                 }
2602
2603                 ring->scratch.obj = obj;
2604                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2605         }
2606
2607         ret = intel_init_ring_buffer(dev, ring);
2608         if (ret)
2609                 return ret;
2610
2611         if (INTEL_INFO(dev)->gen >= 5) {
2612                 ret = intel_init_pipe_control(ring);
2613                 if (ret)
2614                         return ret;
2615         }
2616
2617         return 0;
2618 }
2619
2620 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2621 {
2622         struct drm_i915_private *dev_priv = dev->dev_private;
2623         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2624
2625         ring->name = "bsd ring";
2626         ring->id = VCS;
2627
2628         ring->write_tail = ring_write_tail;
2629         if (INTEL_INFO(dev)->gen >= 6) {
2630                 ring->mmio_base = GEN6_BSD_RING_BASE;
2631                 /* gen6 bsd needs a special wa for tail updates */
2632                 if (IS_GEN6(dev))
2633                         ring->write_tail = gen6_bsd_ring_write_tail;
2634                 ring->flush = gen6_bsd_ring_flush;
2635                 ring->add_request = gen6_add_request;
2636                 ring->get_seqno = gen6_ring_get_seqno;
2637                 ring->set_seqno = ring_set_seqno;
2638                 if (INTEL_INFO(dev)->gen >= 8) {
2639                         ring->irq_enable_mask =
2640                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2641                         ring->irq_get = gen8_ring_get_irq;
2642                         ring->irq_put = gen8_ring_put_irq;
2643                         ring->dispatch_execbuffer =
2644                                 gen8_ring_dispatch_execbuffer;
2645                         if (i915_semaphore_is_enabled(dev)) {
2646                                 ring->semaphore.sync_to = gen8_ring_sync;
2647                                 ring->semaphore.signal = gen8_xcs_signal;
2648                                 GEN8_RING_SEMAPHORE_INIT;
2649                         }
2650                 } else {
2651                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2652                         ring->irq_get = gen6_ring_get_irq;
2653                         ring->irq_put = gen6_ring_put_irq;
2654                         ring->dispatch_execbuffer =
2655                                 gen6_ring_dispatch_execbuffer;
2656                         if (i915_semaphore_is_enabled(dev)) {
2657                                 ring->semaphore.sync_to = gen6_ring_sync;
2658                                 ring->semaphore.signal = gen6_signal;
2659                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2660                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2661                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2662                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2663                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2664                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2665                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2666                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2667                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2668                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2669                         }
2670                 }
2671         } else {
2672                 ring->mmio_base = BSD_RING_BASE;
2673                 ring->flush = bsd_ring_flush;
2674                 ring->add_request = i9xx_add_request;
2675                 ring->get_seqno = ring_get_seqno;
2676                 ring->set_seqno = ring_set_seqno;
2677                 if (IS_GEN5(dev)) {
2678                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2679                         ring->irq_get = gen5_ring_get_irq;
2680                         ring->irq_put = gen5_ring_put_irq;
2681                 } else {
2682                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2683                         ring->irq_get = i9xx_ring_get_irq;
2684                         ring->irq_put = i9xx_ring_put_irq;
2685                 }
2686                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2687         }
2688         ring->init_hw = init_ring_common;
2689
2690         return intel_init_ring_buffer(dev, ring);
2691 }
2692
2693 /**
2694  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2695  */
2696 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2697 {
2698         struct drm_i915_private *dev_priv = dev->dev_private;
2699         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2700
2701         ring->name = "bsd2 ring";
2702         ring->id = VCS2;
2703
2704         ring->write_tail = ring_write_tail;
2705         ring->mmio_base = GEN8_BSD2_RING_BASE;
2706         ring->flush = gen6_bsd_ring_flush;
2707         ring->add_request = gen6_add_request;
2708         ring->get_seqno = gen6_ring_get_seqno;
2709         ring->set_seqno = ring_set_seqno;
2710         ring->irq_enable_mask =
2711                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2712         ring->irq_get = gen8_ring_get_irq;
2713         ring->irq_put = gen8_ring_put_irq;
2714         ring->dispatch_execbuffer =
2715                         gen8_ring_dispatch_execbuffer;
2716         if (i915_semaphore_is_enabled(dev)) {
2717                 ring->semaphore.sync_to = gen8_ring_sync;
2718                 ring->semaphore.signal = gen8_xcs_signal;
2719                 GEN8_RING_SEMAPHORE_INIT;
2720         }
2721         ring->init_hw = init_ring_common;
2722
2723         return intel_init_ring_buffer(dev, ring);
2724 }
2725
2726 int intel_init_blt_ring_buffer(struct drm_device *dev)
2727 {
2728         struct drm_i915_private *dev_priv = dev->dev_private;
2729         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2730
2731         ring->name = "blitter ring";
2732         ring->id = BCS;
2733
2734         ring->mmio_base = BLT_RING_BASE;
2735         ring->write_tail = ring_write_tail;
2736         ring->flush = gen6_ring_flush;
2737         ring->add_request = gen6_add_request;
2738         ring->get_seqno = gen6_ring_get_seqno;
2739         ring->set_seqno = ring_set_seqno;
2740         if (INTEL_INFO(dev)->gen >= 8) {
2741                 ring->irq_enable_mask =
2742                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2743                 ring->irq_get = gen8_ring_get_irq;
2744                 ring->irq_put = gen8_ring_put_irq;
2745                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2746                 if (i915_semaphore_is_enabled(dev)) {
2747                         ring->semaphore.sync_to = gen8_ring_sync;
2748                         ring->semaphore.signal = gen8_xcs_signal;
2749                         GEN8_RING_SEMAPHORE_INIT;
2750                 }
2751         } else {
2752                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2753                 ring->irq_get = gen6_ring_get_irq;
2754                 ring->irq_put = gen6_ring_put_irq;
2755                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2756                 if (i915_semaphore_is_enabled(dev)) {
2757                         ring->semaphore.signal = gen6_signal;
2758                         ring->semaphore.sync_to = gen6_ring_sync;
2759                         /*
2760                          * The current semaphore is only applied on pre-gen8
2761                          * platform.  And there is no VCS2 ring on the pre-gen8
2762                          * platform. So the semaphore between BCS and VCS2 is
2763                          * initialized as INVALID.  Gen8 will initialize the
2764                          * sema between BCS and VCS2 later.
2765                          */
2766                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2767                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2768                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2769                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2770                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2771                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2772                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2773                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2774                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2775                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2776                 }
2777         }
2778         ring->init_hw = init_ring_common;
2779
2780         return intel_init_ring_buffer(dev, ring);
2781 }
2782
2783 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2784 {
2785         struct drm_i915_private *dev_priv = dev->dev_private;
2786         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2787
2788         ring->name = "video enhancement ring";
2789         ring->id = VECS;
2790
2791         ring->mmio_base = VEBOX_RING_BASE;
2792         ring->write_tail = ring_write_tail;
2793         ring->flush = gen6_ring_flush;
2794         ring->add_request = gen6_add_request;
2795         ring->get_seqno = gen6_ring_get_seqno;
2796         ring->set_seqno = ring_set_seqno;
2797
2798         if (INTEL_INFO(dev)->gen >= 8) {
2799                 ring->irq_enable_mask =
2800                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2801                 ring->irq_get = gen8_ring_get_irq;
2802                 ring->irq_put = gen8_ring_put_irq;
2803                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2804                 if (i915_semaphore_is_enabled(dev)) {
2805                         ring->semaphore.sync_to = gen8_ring_sync;
2806                         ring->semaphore.signal = gen8_xcs_signal;
2807                         GEN8_RING_SEMAPHORE_INIT;
2808                 }
2809         } else {
2810                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2811                 ring->irq_get = hsw_vebox_get_irq;
2812                 ring->irq_put = hsw_vebox_put_irq;
2813                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2814                 if (i915_semaphore_is_enabled(dev)) {
2815                         ring->semaphore.sync_to = gen6_ring_sync;
2816                         ring->semaphore.signal = gen6_signal;
2817                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2818                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2819                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2820                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2821                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2822                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2823                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2824                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2825                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2826                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2827                 }
2828         }
2829         ring->init_hw = init_ring_common;
2830
2831         return intel_init_ring_buffer(dev, ring);
2832 }
2833
2834 int
2835 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2836 {
2837         int ret;
2838
2839         if (!ring->gpu_caches_dirty)
2840                 return 0;
2841
2842         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2843         if (ret)
2844                 return ret;
2845
2846         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2847
2848         ring->gpu_caches_dirty = false;
2849         return 0;
2850 }
2851
2852 int
2853 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2854 {
2855         uint32_t flush_domains;
2856         int ret;
2857
2858         flush_domains = 0;
2859         if (ring->gpu_caches_dirty)
2860                 flush_domains = I915_GEM_GPU_DOMAINS;
2861
2862         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2863         if (ret)
2864                 return ret;
2865
2866         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2867
2868         ring->gpu_caches_dirty = false;
2869         return 0;
2870 }
2871
2872 void
2873 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2874 {
2875         int ret;
2876
2877         if (!intel_ring_initialized(ring))
2878                 return;
2879
2880         ret = intel_ring_idle(ring);
2881         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2882                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2883                           ring->name, ret);
2884
2885         stop_ring(ring);
2886 }