drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct intel_engine_cs *ring,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         u32 cmd;
  99         int ret;
 100
 101         cmd = MI_FLUSH;
 102         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 103                 cmd |= MI_NO_WRITE_FLUSH;
 104
 105         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                 cmd |= MI_READ_FLUSH;
 107
 108         ret = intel_ring_begin(ring, 2);
 109         if (ret)
 110                 return ret;
 111
 112         intel_ring_emit(ring, cmd);
 113         intel_ring_emit(ring, MI_NOOP);
 114         intel_ring_advance(ring);
 115
 116         return 0;
 117 }
 118
 119 static int
 120 gen4_render_ring_flush(struct intel_engine_cs *ring,
 121                        u32      invalidate_domains,
 122                        u32      flush_domains)
 123 {
 124         struct drm_device *dev = ring->dev;
 125         u32 cmd;
 126         int ret;
 127
 128         /*
 129          * read/write caches:
 130          *
 131          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 132          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 133          * also flushed at 2d versus 3d pipeline switches.
 134          *
 135          * read-only caches:
 136          *
 137          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 138          * MI_READ_FLUSH is set, and is always flushed on 965.
 139          *
 140          * I915_GEM_DOMAIN_COMMAND may not exist?
 141          *
 142          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 143          * invalidated when MI_EXE_FLUSH is set.
 144          *
 145          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 146          * invalidated with every MI_FLUSH.
 147          *
 148          * TLBs:
 149          *
 150          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 151          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 152          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 153          * are flushed at any MI_FLUSH.
 154          */
 155
 156         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 157         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 158                 cmd &= ~MI_NO_WRITE_FLUSH;
 159         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 160                 cmd |= MI_EXE_FLUSH;
 161
 162         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 163             (IS_G4X(dev) || IS_GEN5(dev)))
 164                 cmd |= MI_INVALIDATE_ISP;
 165
 166         ret = intel_ring_begin(ring, 2);
 167         if (ret)
 168                 return ret;
 169
 170         intel_ring_emit(ring, cmd);
 171         intel_ring_emit(ring, MI_NOOP);
 172         intel_ring_advance(ring);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 179  * implementing two workarounds on gen6.  From section 1.4.7.1
 180  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 181  *
 182  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 183  * produced by non-pipelined state commands), software needs to first
 184  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 185  * 0.
 186  *
 187  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 188  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 189  *
 190  * And the workaround for these two requires this workaround first:
 191  *
 192  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 193  * BEFORE the pipe-control with a post-sync op and no write-cache
 194  * flushes.
 195  *
 196  * And this last workaround is tricky because of the requirements on
 197  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 198  * volume 2 part 1:
 199  *
 200  *     "1 of the following must also be set:
 201  *      - Render Target Cache Flush Enable ([12] of DW1)
 202  *      - Depth Cache Flush Enable ([0] of DW1)
 203  *      - Stall at Pixel Scoreboard ([1] of DW1)
 204  *      - Depth Stall ([13] of DW1)
 205  *      - Post-Sync Operation ([13] of DW1)
 206  *      - Notify Enable ([8] of DW1)"
 207  *
 208  * The cache flushes require the workaround flush that triggered this
 209  * one, so we can't use it.  Depth stall would trigger the same.
 210  * Post-sync nonzero is what triggered this second workaround, so we
 211  * can't use that one either.  Notify enable is IRQs, which aren't
 212  * really our business.  That leaves only stall at scoreboard.
 213  */
 214 static int
 215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 216 {
 217         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 218         int ret;
 219
 220
 221         ret = intel_ring_begin(ring, 6);
 222         if (ret)
 223                 return ret;
 224
 225         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 226         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 227                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 228         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 229         intel_ring_emit(ring, 0); /* low dword */
 230         intel_ring_emit(ring, 0); /* high dword */
 231         intel_ring_emit(ring, MI_NOOP);
 232         intel_ring_advance(ring);
 233
 234         ret = intel_ring_begin(ring, 6);
 235         if (ret)
 236                 return ret;
 237
 238         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 239         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 240         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 241         intel_ring_emit(ring, 0);
 242         intel_ring_emit(ring, 0);
 243         intel_ring_emit(ring, MI_NOOP);
 244         intel_ring_advance(ring);
 245
 246         return 0;
 247 }
 248
 249 static int
 250 gen6_render_ring_flush(struct intel_engine_cs *ring,
 251                          u32 invalidate_domains, u32 flush_domains)
 252 {
 253         u32 flags = 0;
 254         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 255         int ret;
 256
 257         /* Force SNB workarounds for PIPE_CONTROL flushes */
 258         ret = intel_emit_post_sync_nonzero_flush(ring);
 259         if (ret)
 260                 return ret;
 261
 262         /* Just flush everything.  Experiments have shown that reducing the
 263          * number of bits based on the write domains has little performance
 264          * impact.
 265          */
 266         if (flush_domains) {
 267                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 268                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 269                 /*
 270                  * Ensure that any following seqno writes only happen
 271                  * when the render cache is indeed flushed.
 272                  */
 273                 flags |= PIPE_CONTROL_CS_STALL;
 274         }
 275         if (invalidate_domains) {
 276                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 277                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 278                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 279                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 280                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 282                 /*
 283                  * TLB invalidate requires a post-sync write.
 284                  */
 285                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 286         }
 287
 288         ret = intel_ring_begin(ring, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(ring, flags);
 294         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 295         intel_ring_emit(ring, 0);
 296         intel_ring_advance(ring);
 297
 298         return 0;
 299 }
 300
 301 static int
 302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 303 {
 304         int ret;
 305
 306         ret = intel_ring_begin(ring, 4);
 307         if (ret)
 308                 return ret;
 309
 310         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 311         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 312                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 313         intel_ring_emit(ring, 0);
 314         intel_ring_emit(ring, 0);
 315         intel_ring_advance(ring);
 316
 317         return 0;
 318 }
 319
 320 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
 321 {
 322         int ret;
 323
 324         if (!ring->fbc_dirty)
 325                 return 0;
 326
 327         ret = intel_ring_begin(ring, 6);
 328         if (ret)
 329                 return ret;
 330         /* WaFbcNukeOn3DBlt:ivb/hsw */
 331         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 332         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 333         intel_ring_emit(ring, value);
 334         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 335         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 336         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 337         intel_ring_advance(ring);
 338
 339         ring->fbc_dirty = false;
 340         return 0;
 341 }
 342
 343 static int
 344 gen7_render_ring_flush(struct intel_engine_cs *ring,
 345                        u32 invalidate_domains, u32 flush_domains)
 346 {
 347         u32 flags = 0;
 348         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 349         int ret;
 350
 351         /*
 352          * Ensure that any following seqno writes only happen when the render
 353          * cache is indeed flushed.
 354          *
 355          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 356          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 357          * don't try to be clever and just set it unconditionally.
 358          */
 359         flags |= PIPE_CONTROL_CS_STALL;
 360
 361         /* Just flush everything.  Experiments have shown that reducing the
 362          * number of bits based on the write domains has little performance
 363          * impact.
 364          */
 365         if (flush_domains) {
 366                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 367                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 368         }
 369         if (invalidate_domains) {
 370                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 371                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 372                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 373                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 374                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 375                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 376                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 377                 /*
 378                  * TLB invalidate requires a post-sync write.
 379                  */
 380                 flags |= PIPE_CONTROL_QW_WRITE;
 381                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 382
 383                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 384
 385                 /* Workaround: we must issue a pipe_control with CS-stall bit
 386                  * set before a pipe_control command that has the state cache
 387                  * invalidate bit set. */
 388                 gen7_render_ring_cs_stall_wa(ring);
 389         }
 390
 391         ret = intel_ring_begin(ring, 4);
 392         if (ret)
 393                 return ret;
 394
 395         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 396         intel_ring_emit(ring, flags);
 397         intel_ring_emit(ring, scratch_addr);
 398         intel_ring_emit(ring, 0);
 399         intel_ring_advance(ring);
 400
 401         if (!invalidate_domains && flush_domains)
 402                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 403
 404         return 0;
 405 }
 406
 407 static int
 408 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 409                        u32 flags, u32 scratch_addr)
 410 {
 411         int ret;
 412
 413         ret = intel_ring_begin(ring, 6);
 414         if (ret)
 415                 return ret;
 416
 417         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 418         intel_ring_emit(ring, flags);
 419         intel_ring_emit(ring, scratch_addr);
 420         intel_ring_emit(ring, 0);
 421         intel_ring_emit(ring, 0);
 422         intel_ring_emit(ring, 0);
 423         intel_ring_advance(ring);
 424
 425         return 0;
 426 }
 427
 428 static int
 429 gen8_render_ring_flush(struct intel_engine_cs *ring,
 430                        u32 invalidate_domains, u32 flush_domains)
 431 {
 432         u32 flags = 0;
 433         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 434         int ret;
 435
 436         flags |= PIPE_CONTROL_CS_STALL;
 437
 438         if (flush_domains) {
 439                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 440                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 441         }
 442         if (invalidate_domains) {
 443                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 444                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 445                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 446                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 447                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 448                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 449                 flags |= PIPE_CONTROL_QW_WRITE;
 450                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 451
 452                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 453                 ret = gen8_emit_pipe_control(ring,
 454                                              PIPE_CONTROL_CS_STALL |
 455                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 456                                              0);
 457                 if (ret)
 458                         return ret;
 459         }
 460
 461         ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
 462         if (ret)
 463                 return ret;
 464
 465         if (!invalidate_domains && flush_domains)
 466                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 467
 468         return 0;
 469 }
 470
 471 static void ring_write_tail(struct intel_engine_cs *ring,
 472                             u32 value)
 473 {
 474         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 475         I915_WRITE_TAIL(ring, value);
 476 }
 477
 478 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 479 {
 480         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 481         u64 acthd;
 482
 483         if (INTEL_INFO(ring->dev)->gen >= 8)
 484                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 485                                          RING_ACTHD_UDW(ring->mmio_base));
 486         else if (INTEL_INFO(ring->dev)->gen >= 4)
 487                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 488         else
 489                 acthd = I915_READ(ACTHD);
 490
 491         return acthd;
 492 }
 493
 494 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 495 {
 496         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 497         u32 addr;
 498
 499         addr = dev_priv->status_page_dmah->busaddr;
 500         if (INTEL_INFO(ring->dev)->gen >= 4)
 501                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 502         I915_WRITE(HWS_PGA, addr);
 503 }
 504
 505 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 506 {
 507         struct drm_device *dev = ring->dev;
 508         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 509         u32 mmio = 0;
 510
 511         /* The ring status page addresses are no longer next to the rest of
 512          * the ring registers as of gen7.
 513          */
 514         if (IS_GEN7(dev)) {
 515                 switch (ring->id) {
 516                 case RCS:
 517                         mmio = RENDER_HWS_PGA_GEN7;
 518                         break;
 519                 case BCS:
 520                         mmio = BLT_HWS_PGA_GEN7;
 521                         break;
 522                 /*
 523                  * VCS2 actually doesn't exist on Gen7. Only shut up
 524                  * gcc switch check warning
 525                  */
 526                 case VCS2:
 527                 case VCS:
 528                         mmio = BSD_HWS_PGA_GEN7;
 529                         break;
 530                 case VECS:
 531                         mmio = VEBOX_HWS_PGA_GEN7;
 532                         break;
 533                 }
 534         } else if (IS_GEN6(ring->dev)) {
 535                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 536         } else {
 537                 /* XXX: gen8 returns to sanity */
 538                 mmio = RING_HWS_PGA(ring->mmio_base);
 539         }
 540
 541         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 542         POSTING_READ(mmio);
 543
 544         /*
 545          * Flush the TLB for this page
 546          *
 547          * FIXME: These two bits have disappeared on gen8, so a question
 548          * arises: do we still need this and if so how should we go about
 549          * invalidating the TLB?
 550          */
 551         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 552                 u32 reg = RING_INSTPM(ring->mmio_base);
 553
 554                 /* ring should be idle before issuing a sync flush*/
 555                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 556
 557                 I915_WRITE(reg,
 558                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 559                                               INSTPM_SYNC_FLUSH));
 560                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 561                              1000))
 562                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 563                                   ring->name);
 564         }
 565 }
 566
 567 static bool stop_ring(struct intel_engine_cs *ring)
 568 {
 569         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 570
 571         if (!IS_GEN2(ring->dev)) {
 572                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 573                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 574                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 575                         /* Sometimes we observe that the idle flag is not
 576                          * set even though the ring is empty. So double
 577                          * check before giving up.
 578                          */
 579                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 580                                 return false;
 581                 }
 582         }
 583
 584         I915_WRITE_CTL(ring, 0);
 585         I915_WRITE_HEAD(ring, 0);
 586         ring->write_tail(ring, 0);
 587
 588         if (!IS_GEN2(ring->dev)) {
 589                 (void)I915_READ_CTL(ring);
 590                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 591         }
 592
 593         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 594 }
 595
 596 static int init_ring_common(struct intel_engine_cs *ring)
 597 {
 598         struct drm_device *dev = ring->dev;
 599         struct drm_i915_private *dev_priv = dev->dev_private;
 600         struct intel_ringbuffer *ringbuf = ring->buffer;
 601         struct drm_i915_gem_object *obj = ringbuf->obj;
 602         int ret = 0;
 603
 604         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 605
 606         if (!stop_ring(ring)) {
 607                 /* G45 ring initialization often fails to reset head to zero */
 608                 DRM_DEBUG_KMS("%s head not reset to zero "
 609                               "ctl %08x head %08x tail %08x start %08x\n",
 610                               ring->name,
 611                               I915_READ_CTL(ring),
 612                               I915_READ_HEAD(ring),
 613                               I915_READ_TAIL(ring),
 614                               I915_READ_START(ring));
 615
 616                 if (!stop_ring(ring)) {
 617                         DRM_ERROR("failed to set %s head to zero "
 618                                   "ctl %08x head %08x tail %08x start %08x\n",
 619                                   ring->name,
 620                                   I915_READ_CTL(ring),
 621                                   I915_READ_HEAD(ring),
 622                                   I915_READ_TAIL(ring),
 623                                   I915_READ_START(ring));
 624                         ret = -EIO;
 625                         goto out;
 626                 }
 627         }
 628
 629         if (I915_NEED_GFX_HWS(dev))
 630                 intel_ring_setup_status_page(ring);
 631         else
 632                 ring_setup_phys_status_page(ring);
 633
 634         /* Enforce ordering by reading HEAD register back */
 635         I915_READ_HEAD(ring);
 636
 637         /* Initialize the ring. This must happen _after_ we've cleared the ring
 638          * registers with the above sequence (the readback of the HEAD registers
 639          * also enforces ordering), otherwise the hw might lose the new ring
 640          * register values. */
 641         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 642
 643         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 644         if (I915_READ_HEAD(ring))
 645                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 646                           ring->name, I915_READ_HEAD(ring));
 647         I915_WRITE_HEAD(ring, 0);
 648         (void)I915_READ_HEAD(ring);
 649
 650         I915_WRITE_CTL(ring,
 651                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 652                         | RING_VALID);
 653
 654         /* If the head is still not zero, the ring is dead */
 655         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 656                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 657                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 658                 DRM_ERROR("%s initialization failed "
 659                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 660                           ring->name,
 661                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 662                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 663                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 664                 ret = -EIO;
 665                 goto out;
 666         }
 667
 668         ringbuf->last_retired_head = -1;
 669         ringbuf->head = I915_READ_HEAD(ring);
 670         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 671         intel_ring_update_space(ringbuf);
 672
 673         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 674
 675 out:
 676         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 677
 678         return ret;
 679 }
 680
 681 void
 682 intel_fini_pipe_control(struct intel_engine_cs *ring)
 683 {
 684         struct drm_device *dev = ring->dev;
 685
 686         if (ring->scratch.obj == NULL)
 687                 return;
 688
 689         if (INTEL_INFO(dev)->gen >= 5) {
 690                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 691                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 692         }
 693
 694         drm_gem_object_unreference(&ring->scratch.obj->base);
 695         ring->scratch.obj = NULL;
 696 }
 697
 698 int
 699 intel_init_pipe_control(struct intel_engine_cs *ring)
 700 {
 701         int ret;
 702
 703         WARN_ON(ring->scratch.obj);
 704
 705         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 706         if (ring->scratch.obj == NULL) {
 707                 DRM_ERROR("Failed to allocate seqno page\n");
 708                 ret = -ENOMEM;
 709                 goto err;
 710         }
 711
 712         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 713         if (ret)
 714                 goto err_unref;
 715
 716         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 717         if (ret)
 718                 goto err_unref;
 719
 720         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 721         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 722         if (ring->scratch.cpu_page == NULL) {
 723                 ret = -ENOMEM;
 724                 goto err_unpin;
 725         }
 726
 727         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 728                          ring->name, ring->scratch.gtt_offset);
 729         return 0;
 730
 731 err_unpin:
 732         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 733 err_unref:
 734         drm_gem_object_unreference(&ring->scratch.obj->base);
 735 err:
 736         return ret;
 737 }
 738
 739 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
 740                                        struct intel_context *ctx)
 741 {
 742         int ret, i;
 743         struct drm_device *dev = ring->dev;
 744         struct drm_i915_private *dev_priv = dev->dev_private;
 745         struct i915_workarounds *w = &dev_priv->workarounds;
 746
 747         if (WARN_ON_ONCE(w->count == 0))
 748                 return 0;
 749
 750         ring->gpu_caches_dirty = true;
 751         ret = intel_ring_flush_all_caches(ring);
 752         if (ret)
 753                 return ret;
 754
 755         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 756         if (ret)
 757                 return ret;
 758
 759         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 760         for (i = 0; i < w->count; i++) {
 761                 intel_ring_emit(ring, w->reg[i].addr);
 762                 intel_ring_emit(ring, w->reg[i].value);
 763         }
 764         intel_ring_emit(ring, MI_NOOP);
 765
 766         intel_ring_advance(ring);
 767
 768         ring->gpu_caches_dirty = true;
 769         ret = intel_ring_flush_all_caches(ring);
 770         if (ret)
 771                 return ret;
 772
 773         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 774
 775         return 0;
 776 }
 777
 778 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
 779                               struct intel_context *ctx)
 780 {
 781         int ret;
 782
 783         ret = intel_ring_workarounds_emit(ring, ctx);
 784         if (ret != 0)
 785                 return ret;
 786
 787         ret = i915_gem_render_state_init(ring);
 788         if (ret)
 789                 DRM_ERROR("init render state: %d\n", ret);
 790
 791         return ret;
 792 }
 793
 794 static int wa_add(struct drm_i915_private *dev_priv,
 795                   const u32 addr, const u32 mask, const u32 val)
 796 {
 797         const u32 idx = dev_priv->workarounds.count;
 798
 799         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 800                 return -ENOSPC;
 801
 802         dev_priv->workarounds.reg[idx].addr = addr;
 803         dev_priv->workarounds.reg[idx].value = val;
 804         dev_priv->workarounds.reg[idx].mask = mask;
 805
 806         dev_priv->workarounds.count++;
 807
 808         return 0;
 809 }
 810
 811 #define WA_REG(addr, mask, val) { \
 812                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 813                 if (r) \
 814                         return r; \
 815         }
 816
 817 #define WA_SET_BIT_MASKED(addr, mask) \
 818         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 819
 820 #define WA_CLR_BIT_MASKED(addr, mask) \
 821         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 822
 823 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 824         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 825
 826 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 827 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 828
 829 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 830
 831 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 832 {
 833         struct drm_device *dev = ring->dev;
 834         struct drm_i915_private *dev_priv = dev->dev_private;
 835
 836         /* WaDisablePartialInstShootdown:bdw */
 837         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 838         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 839                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 840                           STALL_DOP_GATING_DISABLE);
 841
 842         /* WaDisableDopClockGating:bdw */
 843         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 844                           DOP_CLOCK_GATING_DISABLE);
 845
 846         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 847                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 848
 849         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 850          * workaround for for a possible hang in the unlikely event a TLB
 851          * invalidation occurs during a PSD flush.
 852          */
 853         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 854                           /* WaForceEnableNonCoherent:bdw */
 855                           HDC_FORCE_NON_COHERENT |
 856                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 857                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 858                           /* WaHdcDisableFetchWhenMasked:bdw */
 859                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 860                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 861                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 862
 863         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 864          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 865          *  polygons in the same 8x4 pixel/sample area to be processed without
 866          *  stalling waiting for the earlier ones to write to Hierarchical Z
 867          *  buffer."
 868          *
 869          * This optimization is off by default for Broadwell; turn it on.
 870          */
 871         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 872
 873         /* Wa4x4STCOptimizationDisable:bdw */
 874         WA_SET_BIT_MASKED(CACHE_MODE_1,
 875                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 876
 877         /*
 878          * BSpec recommends 8x4 when MSAA is used,
 879          * however in practice 16x4 seems fastest.
 880          *
 881          * Note that PS/WM thread counts depend on the WIZ hashing
 882          * disable bit, which we don't touch here, but it's good
 883          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 884          */
 885         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 886                             GEN6_WIZ_HASHING_MASK,
 887                             GEN6_WIZ_HASHING_16x4);
 888
 889         return 0;
 890 }
 891
 892 static int chv_init_workarounds(struct intel_engine_cs *ring)
 893 {
 894         struct drm_device *dev = ring->dev;
 895         struct drm_i915_private *dev_priv = dev->dev_private;
 896
 897         /* WaDisablePartialInstShootdown:chv */
 898         /* WaDisableThreadStallDopClockGating:chv */
 899         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 900                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 901                           STALL_DOP_GATING_DISABLE);
 902
 903         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 904          * workaround for a possible hang in the unlikely event a TLB
 905          * invalidation occurs during a PSD flush.
 906          */
 907         /* WaForceEnableNonCoherent:chv */
 908         /* WaHdcDisableFetchWhenMasked:chv */
 909         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 910                           HDC_FORCE_NON_COHERENT |
 911                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 912
 913         /* According to the CACHE_MODE_0 default value documentation, some
 914          * CHV platforms disable this optimization by default.  Turn it on.
 915          */
 916         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 917
 918         /* Wa4x4STCOptimizationDisable:chv */
 919         WA_SET_BIT_MASKED(CACHE_MODE_1,
 920                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 921
 922         /* Improve HiZ throughput on CHV. */
 923         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 924
 925         /*
 926          * BSpec recommends 8x4 when MSAA is used,
 927          * however in practice 16x4 seems fastest.
 928          *
 929          * Note that PS/WM thread counts depend on the WIZ hashing
 930          * disable bit, which we don't touch here, but it's good
 931          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 932          */
 933         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 934                             GEN6_WIZ_HASHING_MASK,
 935                             GEN6_WIZ_HASHING_16x4);
 936
 937         return 0;
 938 }
 939
 940 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 941 {
 942         struct drm_device *dev = ring->dev;
 943         struct drm_i915_private *dev_priv = dev->dev_private;
 944
 945         /* WaDisablePartialInstShootdown:skl */
 946         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 947                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 948
 949         /* Syncing dependencies between camera and graphics */
 950         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 951                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 952
 953         if (INTEL_REVID(dev) >= SKL_REVID_A0 &&
 954             INTEL_REVID(dev) <= SKL_REVID_B0) {
 955                 /*
 956                 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
 957                 * This is a pre-production w/a.
 958                 */
 959                 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
 960                         I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
 961                         ~GEN9_DG_MIRROR_FIX_ENABLE);
 962         }
 963
 964         if (INTEL_REVID(dev) >= SKL_REVID_C0) {
 965                 /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
 966                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 967                                   GEN9_ENABLE_YV12_BUGFIX);
 968         }
 969
 970         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
 971                 /*
 972                  *Use Force Non-Coherent whenever executing a 3D context. This
 973                  * is a workaround for a possible hang in the unlikely event
 974                  * a TLB invalidation occurs during a PSD flush.
 975                  */
 976                 /* WaForceEnableNonCoherent:skl */
 977                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
 978                                   HDC_FORCE_NON_COHERENT);
 979         }
 980
 981         /* Wa4x4STCOptimizationDisable:skl */
 982         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 983
 984         return 0;
 985 }
 986
 987 int init_workarounds_ring(struct intel_engine_cs *ring)
 988 {
 989         struct drm_device *dev = ring->dev;
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991
 992         WARN_ON(ring->id != RCS);
 993
 994         dev_priv->workarounds.count = 0;
 995
 996         if (IS_BROADWELL(dev))
 997                 return bdw_init_workarounds(ring);
 998
 999         if (IS_CHERRYVIEW(dev))
1000                 return chv_init_workarounds(ring);
1001
1002         if (IS_GEN9(dev))
1003                 return gen9_init_workarounds(ring);
1004
1005         return 0;
1006 }
1007
1008 static int init_render_ring(struct intel_engine_cs *ring)
1009 {
1010         struct drm_device *dev = ring->dev;
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012         int ret = init_ring_common(ring);
1013         if (ret)
1014                 return ret;
1015
1016         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1017         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1018                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1019
1020         /* We need to disable the AsyncFlip performance optimisations in order
1021          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1022          * programmed to '1' on all products.
1023          *
1024          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1025          */
1026         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1027                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1028
1029         /* Required for the hardware to program scanline values for waiting */
1030         /* WaEnableFlushTlbInvalidationMode:snb */
1031         if (INTEL_INFO(dev)->gen == 6)
1032                 I915_WRITE(GFX_MODE,
1033                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1034
1035         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1036         if (IS_GEN7(dev))
1037                 I915_WRITE(GFX_MODE_GEN7,
1038                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1039                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1040
1041         if (IS_GEN6(dev)) {
1042                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1043                  * "If this bit is set, STCunit will have LRA as replacement
1044                  *  policy. [...] This bit must be reset.  LRA replacement
1045                  *  policy is not supported."
1046                  */
1047                 I915_WRITE(CACHE_MODE_0,
1048                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1049         }
1050
1051         if (INTEL_INFO(dev)->gen >= 6)
1052                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1053
1054         if (HAS_L3_DPF(dev))
1055                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1056
1057         return init_workarounds_ring(ring);
1058 }
1059
1060 static void render_ring_cleanup(struct intel_engine_cs *ring)
1061 {
1062         struct drm_device *dev = ring->dev;
1063         struct drm_i915_private *dev_priv = dev->dev_private;
1064
1065         if (dev_priv->semaphore_obj) {
1066                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1067                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1068                 dev_priv->semaphore_obj = NULL;
1069         }
1070
1071         intel_fini_pipe_control(ring);
1072 }
1073
1074 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1075                            unsigned int num_dwords)
1076 {
1077 #define MBOX_UPDATE_DWORDS 8
1078         struct drm_device *dev = signaller->dev;
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080         struct intel_engine_cs *waiter;
1081         int i, ret, num_rings;
1082
1083         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1084         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1085 #undef MBOX_UPDATE_DWORDS
1086
1087         ret = intel_ring_begin(signaller, num_dwords);
1088         if (ret)
1089                 return ret;
1090
1091         for_each_ring(waiter, dev_priv, i) {
1092                 u32 seqno;
1093                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1094                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1095                         continue;
1096
1097                 seqno = i915_gem_request_get_seqno(
1098                                            signaller->outstanding_lazy_request);
1099                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1100                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1101                                            PIPE_CONTROL_QW_WRITE |
1102                                            PIPE_CONTROL_FLUSH_ENABLE);
1103                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1104                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1105                 intel_ring_emit(signaller, seqno);
1106                 intel_ring_emit(signaller, 0);
1107                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1108                                            MI_SEMAPHORE_TARGET(waiter->id));
1109                 intel_ring_emit(signaller, 0);
1110         }
1111
1112         return 0;
1113 }
1114
1115 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1116                            unsigned int num_dwords)
1117 {
1118 #define MBOX_UPDATE_DWORDS 6
1119         struct drm_device *dev = signaller->dev;
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         struct intel_engine_cs *waiter;
1122         int i, ret, num_rings;
1123
1124         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1125         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1126 #undef MBOX_UPDATE_DWORDS
1127
1128         ret = intel_ring_begin(signaller, num_dwords);
1129         if (ret)
1130                 return ret;
1131
1132         for_each_ring(waiter, dev_priv, i) {
1133                 u32 seqno;
1134                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1135                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1136                         continue;
1137
1138                 seqno = i915_gem_request_get_seqno(
1139                                            signaller->outstanding_lazy_request);
1140                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1141                                            MI_FLUSH_DW_OP_STOREDW);
1142                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1143                                            MI_FLUSH_DW_USE_GTT);
1144                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1145                 intel_ring_emit(signaller, seqno);
1146                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1147                                            MI_SEMAPHORE_TARGET(waiter->id));
1148                 intel_ring_emit(signaller, 0);
1149         }
1150
1151         return 0;
1152 }
1153
1154 static int gen6_signal(struct intel_engine_cs *signaller,
1155                        unsigned int num_dwords)
1156 {
1157         struct drm_device *dev = signaller->dev;
1158         struct drm_i915_private *dev_priv = dev->dev_private;
1159         struct intel_engine_cs *useless;
1160         int i, ret, num_rings;
1161
1162 #define MBOX_UPDATE_DWORDS 3
1163         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1164         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1165 #undef MBOX_UPDATE_DWORDS
1166
1167         ret = intel_ring_begin(signaller, num_dwords);
1168         if (ret)
1169                 return ret;
1170
1171         for_each_ring(useless, dev_priv, i) {
1172                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1173                 if (mbox_reg != GEN6_NOSYNC) {
1174                         u32 seqno = i915_gem_request_get_seqno(
1175                                            signaller->outstanding_lazy_request);
1176                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1177                         intel_ring_emit(signaller, mbox_reg);
1178                         intel_ring_emit(signaller, seqno);
1179                 }
1180         }
1181
1182         /* If num_dwords was rounded, make sure the tail pointer is correct */
1183         if (num_rings % 2 == 0)
1184                 intel_ring_emit(signaller, MI_NOOP);
1185
1186         return 0;
1187 }
1188
1189 /**
1190  * gen6_add_request - Update the semaphore mailbox registers
1191  *
1192  * @ring - ring that is adding a request
1193  * @seqno - return seqno stuck into the ring
1194  *
1195  * Update the mailbox registers in the *other* rings with the current seqno.
1196  * This acts like a signal in the canonical semaphore.
1197  */
1198 static int
1199 gen6_add_request(struct intel_engine_cs *ring)
1200 {
1201         int ret;
1202
1203         if (ring->semaphore.signal)
1204                 ret = ring->semaphore.signal(ring, 4);
1205         else
1206                 ret = intel_ring_begin(ring, 4);
1207
1208         if (ret)
1209                 return ret;
1210
1211         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1212         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1213         intel_ring_emit(ring,
1214                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1215         intel_ring_emit(ring, MI_USER_INTERRUPT);
1216         __intel_ring_advance(ring);
1217
1218         return 0;
1219 }
1220
1221 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1222                                               u32 seqno)
1223 {
1224         struct drm_i915_private *dev_priv = dev->dev_private;
1225         return dev_priv->last_seqno < seqno;
1226 }
1227
1228 /**
1229  * intel_ring_sync - sync the waiter to the signaller on seqno
1230  *
1231  * @waiter - ring that is waiting
1232  * @signaller - ring which has, or will signal
1233  * @seqno - seqno which the waiter will block on
1234  */
1235
1236 static int
1237 gen8_ring_sync(struct intel_engine_cs *waiter,
1238                struct intel_engine_cs *signaller,
1239                u32 seqno)
1240 {
1241         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1242         int ret;
1243
1244         ret = intel_ring_begin(waiter, 4);
1245         if (ret)
1246                 return ret;
1247
1248         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1249                                 MI_SEMAPHORE_GLOBAL_GTT |
1250                                 MI_SEMAPHORE_POLL |
1251                                 MI_SEMAPHORE_SAD_GTE_SDD);
1252         intel_ring_emit(waiter, seqno);
1253         intel_ring_emit(waiter,
1254                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1255         intel_ring_emit(waiter,
1256                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1257         intel_ring_advance(waiter);
1258         return 0;
1259 }
1260
1261 static int
1262 gen6_ring_sync(struct intel_engine_cs *waiter,
1263                struct intel_engine_cs *signaller,
1264                u32 seqno)
1265 {
1266         u32 dw1 = MI_SEMAPHORE_MBOX |
1267                   MI_SEMAPHORE_COMPARE |
1268                   MI_SEMAPHORE_REGISTER;
1269         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1270         int ret;
1271
1272         /* Throughout all of the GEM code, seqno passed implies our current
1273          * seqno is >= the last seqno executed. However for hardware the
1274          * comparison is strictly greater than.
1275          */
1276         seqno -= 1;
1277
1278         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1279
1280         ret = intel_ring_begin(waiter, 4);
1281         if (ret)
1282                 return ret;
1283
1284         /* If seqno wrap happened, omit the wait with no-ops */
1285         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1286                 intel_ring_emit(waiter, dw1 | wait_mbox);
1287                 intel_ring_emit(waiter, seqno);
1288                 intel_ring_emit(waiter, 0);
1289                 intel_ring_emit(waiter, MI_NOOP);
1290         } else {
1291                 intel_ring_emit(waiter, MI_NOOP);
1292                 intel_ring_emit(waiter, MI_NOOP);
1293                 intel_ring_emit(waiter, MI_NOOP);
1294                 intel_ring_emit(waiter, MI_NOOP);
1295         }
1296         intel_ring_advance(waiter);
1297
1298         return 0;
1299 }
1300
1301 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1302 do {                                                                    \
1303         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1304                  PIPE_CONTROL_DEPTH_STALL);                             \
1305         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1306         intel_ring_emit(ring__, 0);                                                     \
1307         intel_ring_emit(ring__, 0);                                                     \
1308 } while (0)
1309
1310 static int
1311 pc_render_add_request(struct intel_engine_cs *ring)
1312 {
1313         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1314         int ret;
1315
1316         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1317          * incoherent with writes to memory, i.e. completely fubar,
1318          * so we need to use PIPE_NOTIFY instead.
1319          *
1320          * However, we also need to workaround the qword write
1321          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1322          * memory before requesting an interrupt.
1323          */
1324         ret = intel_ring_begin(ring, 32);
1325         if (ret)
1326                 return ret;
1327
1328         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1329                         PIPE_CONTROL_WRITE_FLUSH |
1330                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1331         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1332         intel_ring_emit(ring,
1333                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1334         intel_ring_emit(ring, 0);
1335         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1336         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1337         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1338         scratch_addr += 2 * CACHELINE_BYTES;
1339         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1340         scratch_addr += 2 * CACHELINE_BYTES;
1341         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1342         scratch_addr += 2 * CACHELINE_BYTES;
1343         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1344         scratch_addr += 2 * CACHELINE_BYTES;
1345         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1346
1347         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1348                         PIPE_CONTROL_WRITE_FLUSH |
1349                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1350                         PIPE_CONTROL_NOTIFY);
1351         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1352         intel_ring_emit(ring,
1353                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1354         intel_ring_emit(ring, 0);
1355         __intel_ring_advance(ring);
1356
1357         return 0;
1358 }
1359
1360 static u32
1361 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1362 {
1363         /* Workaround to force correct ordering between irq and seqno writes on
1364          * ivb (and maybe also on snb) by reading from a CS register (like
1365          * ACTHD) before reading the status page. */
1366         if (!lazy_coherency) {
1367                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1368                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1369         }
1370
1371         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1372 }
1373
1374 static u32
1375 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1376 {
1377         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1378 }
1379
1380 static void
1381 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1382 {
1383         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1384 }
1385
1386 static u32
1387 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1388 {
1389         return ring->scratch.cpu_page[0];
1390 }
1391
1392 static void
1393 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1394 {
1395         ring->scratch.cpu_page[0] = seqno;
1396 }
1397
1398 static bool
1399 gen5_ring_get_irq(struct intel_engine_cs *ring)
1400 {
1401         struct drm_device *dev = ring->dev;
1402         struct drm_i915_private *dev_priv = dev->dev_private;
1403         unsigned long flags;
1404
1405         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1406                 return false;
1407
1408         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1409         if (ring->irq_refcount++ == 0)
1410                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1411         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1412
1413         return true;
1414 }
1415
1416 static void
1417 gen5_ring_put_irq(struct intel_engine_cs *ring)
1418 {
1419         struct drm_device *dev = ring->dev;
1420         struct drm_i915_private *dev_priv = dev->dev_private;
1421         unsigned long flags;
1422
1423         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1424         if (--ring->irq_refcount == 0)
1425                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1426         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1427 }
1428
1429 static bool
1430 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1431 {
1432         struct drm_device *dev = ring->dev;
1433         struct drm_i915_private *dev_priv = dev->dev_private;
1434         unsigned long flags;
1435
1436         if (!intel_irqs_enabled(dev_priv))
1437                 return false;
1438
1439         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1440         if (ring->irq_refcount++ == 0) {
1441                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1442                 I915_WRITE(IMR, dev_priv->irq_mask);
1443                 POSTING_READ(IMR);
1444         }
1445         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1446
1447         return true;
1448 }
1449
1450 static void
1451 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1452 {
1453         struct drm_device *dev = ring->dev;
1454         struct drm_i915_private *dev_priv = dev->dev_private;
1455         unsigned long flags;
1456
1457         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1458         if (--ring->irq_refcount == 0) {
1459                 dev_priv->irq_mask |= ring->irq_enable_mask;
1460                 I915_WRITE(IMR, dev_priv->irq_mask);
1461                 POSTING_READ(IMR);
1462         }
1463         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1464 }
1465
1466 static bool
1467 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1468 {
1469         struct drm_device *dev = ring->dev;
1470         struct drm_i915_private *dev_priv = dev->dev_private;
1471         unsigned long flags;
1472
1473         if (!intel_irqs_enabled(dev_priv))
1474                 return false;
1475
1476         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1477         if (ring->irq_refcount++ == 0) {
1478                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1479                 I915_WRITE16(IMR, dev_priv->irq_mask);
1480                 POSTING_READ16(IMR);
1481         }
1482         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1483
1484         return true;
1485 }
1486
1487 static void
1488 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1489 {
1490         struct drm_device *dev = ring->dev;
1491         struct drm_i915_private *dev_priv = dev->dev_private;
1492         unsigned long flags;
1493
1494         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1495         if (--ring->irq_refcount == 0) {
1496                 dev_priv->irq_mask |= ring->irq_enable_mask;
1497                 I915_WRITE16(IMR, dev_priv->irq_mask);
1498                 POSTING_READ16(IMR);
1499         }
1500         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1501 }
1502
1503 static int
1504 bsd_ring_flush(struct intel_engine_cs *ring,
1505                u32     invalidate_domains,
1506                u32     flush_domains)
1507 {
1508         int ret;
1509
1510         ret = intel_ring_begin(ring, 2);
1511         if (ret)
1512                 return ret;
1513
1514         intel_ring_emit(ring, MI_FLUSH);
1515         intel_ring_emit(ring, MI_NOOP);
1516         intel_ring_advance(ring);
1517         return 0;
1518 }
1519
1520 static int
1521 i9xx_add_request(struct intel_engine_cs *ring)
1522 {
1523         int ret;
1524
1525         ret = intel_ring_begin(ring, 4);
1526         if (ret)
1527                 return ret;
1528
1529         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1530         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1531         intel_ring_emit(ring,
1532                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1533         intel_ring_emit(ring, MI_USER_INTERRUPT);
1534         __intel_ring_advance(ring);
1535
1536         return 0;
1537 }
1538
1539 static bool
1540 gen6_ring_get_irq(struct intel_engine_cs *ring)
1541 {
1542         struct drm_device *dev = ring->dev;
1543         struct drm_i915_private *dev_priv = dev->dev_private;
1544         unsigned long flags;
1545
1546         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1547                 return false;
1548
1549         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1550         if (ring->irq_refcount++ == 0) {
1551                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1552                         I915_WRITE_IMR(ring,
1553                                        ~(ring->irq_enable_mask |
1554                                          GT_PARITY_ERROR(dev)));
1555                 else
1556                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1557                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1558         }
1559         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1560
1561         return true;
1562 }
1563
1564 static void
1565 gen6_ring_put_irq(struct intel_engine_cs *ring)
1566 {
1567         struct drm_device *dev = ring->dev;
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569         unsigned long flags;
1570
1571         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1572         if (--ring->irq_refcount == 0) {
1573                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1574                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1575                 else
1576                         I915_WRITE_IMR(ring, ~0);
1577                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1578         }
1579         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1580 }
1581
1582 static bool
1583 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1584 {
1585         struct drm_device *dev = ring->dev;
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         unsigned long flags;
1588
1589         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1590                 return false;
1591
1592         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1593         if (ring->irq_refcount++ == 0) {
1594                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1595                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1596         }
1597         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1598
1599         return true;
1600 }
1601
1602 static void
1603 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1604 {
1605         struct drm_device *dev = ring->dev;
1606         struct drm_i915_private *dev_priv = dev->dev_private;
1607         unsigned long flags;
1608
1609         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1610         if (--ring->irq_refcount == 0) {
1611                 I915_WRITE_IMR(ring, ~0);
1612                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1613         }
1614         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1615 }
1616
1617 static bool
1618 gen8_ring_get_irq(struct intel_engine_cs *ring)
1619 {
1620         struct drm_device *dev = ring->dev;
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622         unsigned long flags;
1623
1624         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1625                 return false;
1626
1627         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1628         if (ring->irq_refcount++ == 0) {
1629                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1630                         I915_WRITE_IMR(ring,
1631                                        ~(ring->irq_enable_mask |
1632                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1633                 } else {
1634                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1635                 }
1636                 POSTING_READ(RING_IMR(ring->mmio_base));
1637         }
1638         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1639
1640         return true;
1641 }
1642
1643 static void
1644 gen8_ring_put_irq(struct intel_engine_cs *ring)
1645 {
1646         struct drm_device *dev = ring->dev;
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         unsigned long flags;
1649
1650         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1651         if (--ring->irq_refcount == 0) {
1652                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1653                         I915_WRITE_IMR(ring,
1654                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1655                 } else {
1656                         I915_WRITE_IMR(ring, ~0);
1657                 }
1658                 POSTING_READ(RING_IMR(ring->mmio_base));
1659         }
1660         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1661 }
1662
1663 static int
1664 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1665                          u64 offset, u32 length,
1666                          unsigned flags)
1667 {
1668         int ret;
1669
1670         ret = intel_ring_begin(ring, 2);
1671         if (ret)
1672                 return ret;
1673
1674         intel_ring_emit(ring,
1675                         MI_BATCH_BUFFER_START |
1676                         MI_BATCH_GTT |
1677                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1678         intel_ring_emit(ring, offset);
1679         intel_ring_advance(ring);
1680
1681         return 0;
1682 }
1683
1684 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1685 #define I830_BATCH_LIMIT (256*1024)
1686 #define I830_TLB_ENTRIES (2)
1687 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1688 static int
1689 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1690                                 u64 offset, u32 len,
1691                                 unsigned flags)
1692 {
1693         u32 cs_offset = ring->scratch.gtt_offset;
1694         int ret;
1695
1696         ret = intel_ring_begin(ring, 6);
1697         if (ret)
1698                 return ret;
1699
1700         /* Evict the invalid PTE TLBs */
1701         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1702         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1703         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1704         intel_ring_emit(ring, cs_offset);
1705         intel_ring_emit(ring, 0xdeadbeef);
1706         intel_ring_emit(ring, MI_NOOP);
1707         intel_ring_advance(ring);
1708
1709         if ((flags & I915_DISPATCH_PINNED) == 0) {
1710                 if (len > I830_BATCH_LIMIT)
1711                         return -ENOSPC;
1712
1713                 ret = intel_ring_begin(ring, 6 + 2);
1714                 if (ret)
1715                         return ret;
1716
1717                 /* Blit the batch (which has now all relocs applied) to the
1718                  * stable batch scratch bo area (so that the CS never
1719                  * stumbles over its tlb invalidation bug) ...
1720                  */
1721                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1722                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1723                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1724                 intel_ring_emit(ring, cs_offset);
1725                 intel_ring_emit(ring, 4096);
1726                 intel_ring_emit(ring, offset);
1727
1728                 intel_ring_emit(ring, MI_FLUSH);
1729                 intel_ring_emit(ring, MI_NOOP);
1730                 intel_ring_advance(ring);
1731
1732                 /* ... and execute it. */
1733                 offset = cs_offset;
1734         }
1735
1736         ret = intel_ring_begin(ring, 4);
1737         if (ret)
1738                 return ret;
1739
1740         intel_ring_emit(ring, MI_BATCH_BUFFER);
1741         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1742         intel_ring_emit(ring, offset + len - 8);
1743         intel_ring_emit(ring, MI_NOOP);
1744         intel_ring_advance(ring);
1745
1746         return 0;
1747 }
1748
1749 static int
1750 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1751                          u64 offset, u32 len,
1752                          unsigned flags)
1753 {
1754         int ret;
1755
1756         ret = intel_ring_begin(ring, 2);
1757         if (ret)
1758                 return ret;
1759
1760         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1761         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1762         intel_ring_advance(ring);
1763
1764         return 0;
1765 }
1766
1767 static void cleanup_status_page(struct intel_engine_cs *ring)
1768 {
1769         struct drm_i915_gem_object *obj;
1770
1771         obj = ring->status_page.obj;
1772         if (obj == NULL)
1773                 return;
1774
1775         kunmap(sg_page(obj->pages->sgl));
1776         i915_gem_object_ggtt_unpin(obj);
1777         drm_gem_object_unreference(&obj->base);
1778         ring->status_page.obj = NULL;
1779 }
1780
1781 static int init_status_page(struct intel_engine_cs *ring)
1782 {
1783         struct drm_i915_gem_object *obj;
1784
1785         if ((obj = ring->status_page.obj) == NULL) {
1786                 unsigned flags;
1787                 int ret;
1788
1789                 obj = i915_gem_alloc_object(ring->dev, 4096);
1790                 if (obj == NULL) {
1791                         DRM_ERROR("Failed to allocate status page\n");
1792                         return -ENOMEM;
1793                 }
1794
1795                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1796                 if (ret)
1797                         goto err_unref;
1798
1799                 flags = 0;
1800                 if (!HAS_LLC(ring->dev))
1801                         /* On g33, we cannot place HWS above 256MiB, so
1802                          * restrict its pinning to the low mappable arena.
1803                          * Though this restriction is not documented for
1804                          * gen4, gen5, or byt, they also behave similarly
1805                          * and hang if the HWS is placed at the top of the
1806                          * GTT. To generalise, it appears that all !llc
1807                          * platforms have issues with us placing the HWS
1808                          * above the mappable region (even though we never
1809                          * actualy map it).
1810                          */
1811                         flags |= PIN_MAPPABLE;
1812                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1813                 if (ret) {
1814 err_unref:
1815                         drm_gem_object_unreference(&obj->base);
1816                         return ret;
1817                 }
1818
1819                 ring->status_page.obj = obj;
1820         }
1821
1822         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1823         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1824         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1825
1826         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1827                         ring->name, ring->status_page.gfx_addr);
1828
1829         return 0;
1830 }
1831
1832 static int init_phys_status_page(struct intel_engine_cs *ring)
1833 {
1834         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1835
1836         if (!dev_priv->status_page_dmah) {
1837                 dev_priv->status_page_dmah =
1838                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1839                 if (!dev_priv->status_page_dmah)
1840                         return -ENOMEM;
1841         }
1842
1843         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1844         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1845
1846         return 0;
1847 }
1848
1849 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1850 {
1851         iounmap(ringbuf->virtual_start);
1852         ringbuf->virtual_start = NULL;
1853         i915_gem_object_ggtt_unpin(ringbuf->obj);
1854 }
1855
1856 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1857                                      struct intel_ringbuffer *ringbuf)
1858 {
1859         struct drm_i915_private *dev_priv = to_i915(dev);
1860         struct drm_i915_gem_object *obj = ringbuf->obj;
1861         int ret;
1862
1863         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1864         if (ret)
1865                 return ret;
1866
1867         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1868         if (ret) {
1869                 i915_gem_object_ggtt_unpin(obj);
1870                 return ret;
1871         }
1872
1873         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1874                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1875         if (ringbuf->virtual_start == NULL) {
1876                 i915_gem_object_ggtt_unpin(obj);
1877                 return -EINVAL;
1878         }
1879
1880         return 0;
1881 }
1882
1883 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1884 {
1885         drm_gem_object_unreference(&ringbuf->obj->base);
1886         ringbuf->obj = NULL;
1887 }
1888
1889 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1890                                struct intel_ringbuffer *ringbuf)
1891 {
1892         struct drm_i915_gem_object *obj;
1893
1894         obj = NULL;
1895         if (!HAS_LLC(dev))
1896                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1897         if (obj == NULL)
1898                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1899         if (obj == NULL)
1900                 return -ENOMEM;
1901
1902         /* mark ring buffers as read-only from GPU side by default */
1903         obj->gt_ro = 1;
1904
1905         ringbuf->obj = obj;
1906
1907         return 0;
1908 }
1909
1910 static int intel_init_ring_buffer(struct drm_device *dev,
1911                                   struct intel_engine_cs *ring)
1912 {
1913         struct intel_ringbuffer *ringbuf;
1914         int ret;
1915
1916         WARN_ON(ring->buffer);
1917
1918         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1919         if (!ringbuf)
1920                 return -ENOMEM;
1921         ring->buffer = ringbuf;
1922
1923         ring->dev = dev;
1924         INIT_LIST_HEAD(&ring->active_list);
1925         INIT_LIST_HEAD(&ring->request_list);
1926         INIT_LIST_HEAD(&ring->execlist_queue);
1927         ringbuf->size = 32 * PAGE_SIZE;
1928         ringbuf->ring = ring;
1929         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1930
1931         init_waitqueue_head(&ring->irq_queue);
1932
1933         if (I915_NEED_GFX_HWS(dev)) {
1934                 ret = init_status_page(ring);
1935                 if (ret)
1936                         goto error;
1937         } else {
1938                 BUG_ON(ring->id != RCS);
1939                 ret = init_phys_status_page(ring);
1940                 if (ret)
1941                         goto error;
1942         }
1943
1944         WARN_ON(ringbuf->obj);
1945
1946         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1947         if (ret) {
1948                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1949                                 ring->name, ret);
1950                 goto error;
1951         }
1952
1953         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1954         if (ret) {
1955                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1956                                 ring->name, ret);
1957                 intel_destroy_ringbuffer_obj(ringbuf);
1958                 goto error;
1959         }
1960
1961         /* Workaround an erratum on the i830 which causes a hang if
1962          * the TAIL pointer points to within the last 2 cachelines
1963          * of the buffer.
1964          */
1965         ringbuf->effective_size = ringbuf->size;
1966         if (IS_I830(dev) || IS_845G(dev))
1967                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1968
1969         ret = i915_cmd_parser_init_ring(ring);
1970         if (ret)
1971                 goto error;
1972
1973         return 0;
1974
1975 error:
1976         kfree(ringbuf);
1977         ring->buffer = NULL;
1978         return ret;
1979 }
1980
1981 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1982 {
1983         struct drm_i915_private *dev_priv;
1984         struct intel_ringbuffer *ringbuf;
1985
1986         if (!intel_ring_initialized(ring))
1987                 return;
1988
1989         dev_priv = to_i915(ring->dev);
1990         ringbuf = ring->buffer;
1991
1992         intel_stop_ring_buffer(ring);
1993         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1994
1995         intel_unpin_ringbuffer_obj(ringbuf);
1996         intel_destroy_ringbuffer_obj(ringbuf);
1997         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1998
1999         if (ring->cleanup)
2000                 ring->cleanup(ring);
2001
2002         cleanup_status_page(ring);
2003
2004         i915_cmd_parser_fini_ring(ring);
2005
2006         kfree(ringbuf);
2007         ring->buffer = NULL;
2008 }
2009
2010 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
2011 {
2012         struct intel_ringbuffer *ringbuf = ring->buffer;
2013         struct drm_i915_gem_request *request;
2014         int ret;
2015
2016         if (intel_ring_space(ringbuf) >= n)
2017                 return 0;
2018
2019         list_for_each_entry(request, &ring->request_list, list) {
2020                 if (__intel_ring_space(request->postfix, ringbuf->tail,
2021                                        ringbuf->size) >= n) {
2022                         break;
2023                 }
2024         }
2025
2026         if (&request->list == &ring->request_list)
2027                 return -ENOSPC;
2028
2029         ret = i915_wait_request(request);
2030         if (ret)
2031                 return ret;
2032
2033         i915_gem_retire_requests_ring(ring);
2034
2035         return 0;
2036 }
2037
2038 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2039 {
2040         struct drm_device *dev = ring->dev;
2041         struct drm_i915_private *dev_priv = dev->dev_private;
2042         struct intel_ringbuffer *ringbuf = ring->buffer;
2043         unsigned long end;
2044         int ret;
2045
2046         ret = intel_ring_wait_request(ring, n);
2047         if (ret != -ENOSPC)
2048                 return ret;
2049
2050         /* force the tail write in case we have been skipping them */
2051         __intel_ring_advance(ring);
2052
2053         /* With GEM the hangcheck timer should kick us out of the loop,
2054          * leaving it early runs the risk of corrupting GEM state (due
2055          * to running on almost untested codepaths). But on resume
2056          * timers don't work yet, so prevent a complete hang in that
2057          * case by choosing an insanely large timeout. */
2058         end = jiffies + 60 * HZ;
2059
2060         ret = 0;
2061         trace_i915_ring_wait_begin(ring);
2062         do {
2063                 if (intel_ring_space(ringbuf) >= n)
2064                         break;
2065                 ringbuf->head = I915_READ_HEAD(ring);
2066                 if (intel_ring_space(ringbuf) >= n)
2067                         break;
2068
2069                 msleep(1);
2070
2071                 if (dev_priv->mm.interruptible && signal_pending(current)) {
2072                         ret = -ERESTARTSYS;
2073                         break;
2074                 }
2075
2076                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2077                                            dev_priv->mm.interruptible);
2078                 if (ret)
2079                         break;
2080
2081                 if (time_after(jiffies, end)) {
2082                         ret = -EBUSY;
2083                         break;
2084                 }
2085         } while (1);
2086         trace_i915_ring_wait_end(ring);
2087         return ret;
2088 }
2089
2090 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2091 {
2092         uint32_t __iomem *virt;
2093         struct intel_ringbuffer *ringbuf = ring->buffer;
2094         int rem = ringbuf->size - ringbuf->tail;
2095
2096         if (ringbuf->space < rem) {
2097                 int ret = ring_wait_for_space(ring, rem);
2098                 if (ret)
2099                         return ret;
2100         }
2101
2102         virt = ringbuf->virtual_start + ringbuf->tail;
2103         rem /= 4;
2104         while (rem--)
2105                 iowrite32(MI_NOOP, virt++);
2106
2107         ringbuf->tail = 0;
2108         intel_ring_update_space(ringbuf);
2109
2110         return 0;
2111 }
2112
2113 int intel_ring_idle(struct intel_engine_cs *ring)
2114 {
2115         struct drm_i915_gem_request *req;
2116         int ret;
2117
2118         /* We need to add any requests required to flush the objects and ring */
2119         if (ring->outstanding_lazy_request) {
2120                 ret = i915_add_request(ring);
2121                 if (ret)
2122                         return ret;
2123         }
2124
2125         /* Wait upon the last request to be completed */
2126         if (list_empty(&ring->request_list))
2127                 return 0;
2128
2129         req = list_entry(ring->request_list.prev,
2130                            struct drm_i915_gem_request,
2131                            list);
2132
2133         return i915_wait_request(req);
2134 }
2135
2136 static int
2137 intel_ring_alloc_request(struct intel_engine_cs *ring)
2138 {
2139         int ret;
2140         struct drm_i915_gem_request *request;
2141         struct drm_i915_private *dev_private = ring->dev->dev_private;
2142
2143         if (ring->outstanding_lazy_request)
2144                 return 0;
2145
2146         request = kzalloc(sizeof(*request), GFP_KERNEL);
2147         if (request == NULL)
2148                 return -ENOMEM;
2149
2150         kref_init(&request->ref);
2151         request->ring = ring;
2152         request->uniq = dev_private->request_uniq++;
2153
2154         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
2155         if (ret) {
2156                 kfree(request);
2157                 return ret;
2158         }
2159
2160         ring->outstanding_lazy_request = request;
2161         return 0;
2162 }
2163
2164 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2165                                 int bytes)
2166 {
2167         struct intel_ringbuffer *ringbuf = ring->buffer;
2168         int ret;
2169
2170         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2171                 ret = intel_wrap_ring_buffer(ring);
2172                 if (unlikely(ret))
2173                         return ret;
2174         }
2175
2176         if (unlikely(ringbuf->space < bytes)) {
2177                 ret = ring_wait_for_space(ring, bytes);
2178                 if (unlikely(ret))
2179                         return ret;
2180         }
2181
2182         return 0;
2183 }
2184
2185 int intel_ring_begin(struct intel_engine_cs *ring,
2186                      int num_dwords)
2187 {
2188         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2189         int ret;
2190
2191         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2192                                    dev_priv->mm.interruptible);
2193         if (ret)
2194                 return ret;
2195
2196         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2197         if (ret)
2198                 return ret;
2199
2200         /* Preallocate the olr before touching the ring */
2201         ret = intel_ring_alloc_request(ring);
2202         if (ret)
2203                 return ret;
2204
2205         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2206         return 0;
2207 }
2208
2209 /* Align the ring tail to a cacheline boundary */
2210 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2211 {
2212         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2213         int ret;
2214
2215         if (num_dwords == 0)
2216                 return 0;
2217
2218         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2219         ret = intel_ring_begin(ring, num_dwords);
2220         if (ret)
2221                 return ret;
2222
2223         while (num_dwords--)
2224                 intel_ring_emit(ring, MI_NOOP);
2225
2226         intel_ring_advance(ring);
2227
2228         return 0;
2229 }
2230
2231 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2232 {
2233         struct drm_device *dev = ring->dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235
2236         BUG_ON(ring->outstanding_lazy_request);
2237
2238         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2239                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2240                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2241                 if (HAS_VEBOX(dev))
2242                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2243         }
2244
2245         ring->set_seqno(ring, seqno);
2246         ring->hangcheck.seqno = seqno;
2247 }
2248
2249 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2250                                      u32 value)
2251 {
2252         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2253
2254        /* Every tail move must follow the sequence below */
2255
2256         /* Disable notification that the ring is IDLE. The GT
2257          * will then assume that it is busy and bring it out of rc6.
2258          */
2259         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2260                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2261
2262         /* Clear the context id. Here be magic! */
2263         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2264
2265         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2266         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2267                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2268                      50))
2269                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2270
2271         /* Now that the ring is fully powered up, update the tail */
2272         I915_WRITE_TAIL(ring, value);
2273         POSTING_READ(RING_TAIL(ring->mmio_base));
2274
2275         /* Let the ring send IDLE messages to the GT again,
2276          * and so let it sleep to conserve power when idle.
2277          */
2278         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2279                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2280 }
2281
2282 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2283                                u32 invalidate, u32 flush)
2284 {
2285         uint32_t cmd;
2286         int ret;
2287
2288         ret = intel_ring_begin(ring, 4);
2289         if (ret)
2290                 return ret;
2291
2292         cmd = MI_FLUSH_DW;
2293         if (INTEL_INFO(ring->dev)->gen >= 8)
2294                 cmd += 1;
2295         /*
2296          * Bspec vol 1c.5 - video engine command streamer:
2297          * "If ENABLED, all TLBs will be invalidated once the flush
2298          * operation is complete. This bit is only valid when the
2299          * Post-Sync Operation field is a value of 1h or 3h."
2300          */
2301         if (invalidate & I915_GEM_GPU_DOMAINS)
2302                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2303                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2304         intel_ring_emit(ring, cmd);
2305         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2306         if (INTEL_INFO(ring->dev)->gen >= 8) {
2307                 intel_ring_emit(ring, 0); /* upper addr */
2308                 intel_ring_emit(ring, 0); /* value */
2309         } else  {
2310                 intel_ring_emit(ring, 0);
2311                 intel_ring_emit(ring, MI_NOOP);
2312         }
2313         intel_ring_advance(ring);
2314         return 0;
2315 }
2316
2317 static int
2318 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2319                               u64 offset, u32 len,
2320                               unsigned flags)
2321 {
2322         bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2323         int ret;
2324
2325         ret = intel_ring_begin(ring, 4);
2326         if (ret)
2327                 return ret;
2328
2329         /* FIXME(BDW): Address space and security selectors. */
2330         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2331         intel_ring_emit(ring, lower_32_bits(offset));
2332         intel_ring_emit(ring, upper_32_bits(offset));
2333         intel_ring_emit(ring, MI_NOOP);
2334         intel_ring_advance(ring);
2335
2336         return 0;
2337 }
2338
2339 static int
2340 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2341                               u64 offset, u32 len,
2342                               unsigned flags)
2343 {
2344         int ret;
2345
2346         ret = intel_ring_begin(ring, 2);
2347         if (ret)
2348                 return ret;
2349
2350         intel_ring_emit(ring,
2351                         MI_BATCH_BUFFER_START |
2352                         (flags & I915_DISPATCH_SECURE ?
2353                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2354         /* bit0-7 is the length on GEN6+ */
2355         intel_ring_emit(ring, offset);
2356         intel_ring_advance(ring);
2357
2358         return 0;
2359 }
2360
2361 static int
2362 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2363                               u64 offset, u32 len,
2364                               unsigned flags)
2365 {
2366         int ret;
2367
2368         ret = intel_ring_begin(ring, 2);
2369         if (ret)
2370                 return ret;
2371
2372         intel_ring_emit(ring,
2373                         MI_BATCH_BUFFER_START |
2374                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2375         /* bit0-7 is the length on GEN6+ */
2376         intel_ring_emit(ring, offset);
2377         intel_ring_advance(ring);
2378
2379         return 0;
2380 }
2381
2382 /* Blitter support (SandyBridge+) */
2383
2384 static int gen6_ring_flush(struct intel_engine_cs *ring,
2385                            u32 invalidate, u32 flush)
2386 {
2387         struct drm_device *dev = ring->dev;
2388         struct drm_i915_private *dev_priv = dev->dev_private;
2389         uint32_t cmd;
2390         int ret;
2391
2392         ret = intel_ring_begin(ring, 4);
2393         if (ret)
2394                 return ret;
2395
2396         cmd = MI_FLUSH_DW;
2397         if (INTEL_INFO(ring->dev)->gen >= 8)
2398                 cmd += 1;
2399         /*
2400          * Bspec vol 1c.3 - blitter engine command streamer:
2401          * "If ENABLED, all TLBs will be invalidated once the flush
2402          * operation is complete. This bit is only valid when the
2403          * Post-Sync Operation field is a value of 1h or 3h."
2404          */
2405         if (invalidate & I915_GEM_DOMAIN_RENDER)
2406                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2407                         MI_FLUSH_DW_OP_STOREDW;
2408         intel_ring_emit(ring, cmd);
2409         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2410         if (INTEL_INFO(ring->dev)->gen >= 8) {
2411                 intel_ring_emit(ring, 0); /* upper addr */
2412                 intel_ring_emit(ring, 0); /* value */
2413         } else  {
2414                 intel_ring_emit(ring, 0);
2415                 intel_ring_emit(ring, MI_NOOP);
2416         }
2417         intel_ring_advance(ring);
2418
2419         if (!invalidate && flush) {
2420                 if (IS_GEN7(dev))
2421                         return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2422                 else if (IS_BROADWELL(dev))
2423                         dev_priv->fbc.need_sw_cache_clean = true;
2424         }
2425
2426         return 0;
2427 }
2428
2429 int intel_init_render_ring_buffer(struct drm_device *dev)
2430 {
2431         struct drm_i915_private *dev_priv = dev->dev_private;
2432         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2433         struct drm_i915_gem_object *obj;
2434         int ret;
2435
2436         ring->name = "render ring";
2437         ring->id = RCS;
2438         ring->mmio_base = RENDER_RING_BASE;
2439
2440         if (INTEL_INFO(dev)->gen >= 8) {
2441                 if (i915_semaphore_is_enabled(dev)) {
2442                         obj = i915_gem_alloc_object(dev, 4096);
2443                         if (obj == NULL) {
2444                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2445                                 i915.semaphores = 0;
2446                         } else {
2447                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2448                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2449                                 if (ret != 0) {
2450                                         drm_gem_object_unreference(&obj->base);
2451                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2452                                         i915.semaphores = 0;
2453                                 } else
2454                                         dev_priv->semaphore_obj = obj;
2455                         }
2456                 }
2457
2458                 ring->init_context = intel_rcs_ctx_init;
2459                 ring->add_request = gen6_add_request;
2460                 ring->flush = gen8_render_ring_flush;
2461                 ring->irq_get = gen8_ring_get_irq;
2462                 ring->irq_put = gen8_ring_put_irq;
2463                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2464                 ring->get_seqno = gen6_ring_get_seqno;
2465                 ring->set_seqno = ring_set_seqno;
2466                 if (i915_semaphore_is_enabled(dev)) {
2467                         WARN_ON(!dev_priv->semaphore_obj);
2468                         ring->semaphore.sync_to = gen8_ring_sync;
2469                         ring->semaphore.signal = gen8_rcs_signal;
2470                         GEN8_RING_SEMAPHORE_INIT;
2471                 }
2472         } else if (INTEL_INFO(dev)->gen >= 6) {
2473                 ring->add_request = gen6_add_request;
2474                 ring->flush = gen7_render_ring_flush;
2475                 if (INTEL_INFO(dev)->gen == 6)
2476                         ring->flush = gen6_render_ring_flush;
2477                 ring->irq_get = gen6_ring_get_irq;
2478                 ring->irq_put = gen6_ring_put_irq;
2479                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2480                 ring->get_seqno = gen6_ring_get_seqno;
2481                 ring->set_seqno = ring_set_seqno;
2482                 if (i915_semaphore_is_enabled(dev)) {
2483                         ring->semaphore.sync_to = gen6_ring_sync;
2484                         ring->semaphore.signal = gen6_signal;
2485                         /*
2486                          * The current semaphore is only applied on pre-gen8
2487                          * platform.  And there is no VCS2 ring on the pre-gen8
2488                          * platform. So the semaphore between RCS and VCS2 is
2489                          * initialized as INVALID.  Gen8 will initialize the
2490                          * sema between VCS2 and RCS later.
2491                          */
2492                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2493                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2494                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2495                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2496                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2497                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2498                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2499                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2500                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2501                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2502                 }
2503         } else if (IS_GEN5(dev)) {
2504                 ring->add_request = pc_render_add_request;
2505                 ring->flush = gen4_render_ring_flush;
2506                 ring->get_seqno = pc_render_get_seqno;
2507                 ring->set_seqno = pc_render_set_seqno;
2508                 ring->irq_get = gen5_ring_get_irq;
2509                 ring->irq_put = gen5_ring_put_irq;
2510                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2511                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2512         } else {
2513                 ring->add_request = i9xx_add_request;
2514                 if (INTEL_INFO(dev)->gen < 4)
2515                         ring->flush = gen2_render_ring_flush;
2516                 else
2517                         ring->flush = gen4_render_ring_flush;
2518                 ring->get_seqno = ring_get_seqno;
2519                 ring->set_seqno = ring_set_seqno;
2520                 if (IS_GEN2(dev)) {
2521                         ring->irq_get = i8xx_ring_get_irq;
2522                         ring->irq_put = i8xx_ring_put_irq;
2523                 } else {
2524                         ring->irq_get = i9xx_ring_get_irq;
2525                         ring->irq_put = i9xx_ring_put_irq;
2526                 }
2527                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2528         }
2529         ring->write_tail = ring_write_tail;
2530
2531         if (IS_HASWELL(dev))
2532                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2533         else if (IS_GEN8(dev))
2534                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2535         else if (INTEL_INFO(dev)->gen >= 6)
2536                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2537         else if (INTEL_INFO(dev)->gen >= 4)
2538                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2539         else if (IS_I830(dev) || IS_845G(dev))
2540                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2541         else
2542                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2543         ring->init_hw = init_render_ring;
2544         ring->cleanup = render_ring_cleanup;
2545
2546         /* Workaround batchbuffer to combat CS tlb bug. */
2547         if (HAS_BROKEN_CS_TLB(dev)) {
2548                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2549                 if (obj == NULL) {
2550                         DRM_ERROR("Failed to allocate batch bo\n");
2551                         return -ENOMEM;
2552                 }
2553
2554                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2555                 if (ret != 0) {
2556                         drm_gem_object_unreference(&obj->base);
2557                         DRM_ERROR("Failed to ping batch bo\n");
2558                         return ret;
2559                 }
2560
2561                 ring->scratch.obj = obj;
2562                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2563         }
2564
2565         ret = intel_init_ring_buffer(dev, ring);
2566         if (ret)
2567                 return ret;
2568
2569         if (INTEL_INFO(dev)->gen >= 5) {
2570                 ret = intel_init_pipe_control(ring);
2571                 if (ret)
2572                         return ret;
2573         }
2574
2575         return 0;
2576 }
2577
2578 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2579 {
2580         struct drm_i915_private *dev_priv = dev->dev_private;
2581         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2582
2583         ring->name = "bsd ring";
2584         ring->id = VCS;
2585
2586         ring->write_tail = ring_write_tail;
2587         if (INTEL_INFO(dev)->gen >= 6) {
2588                 ring->mmio_base = GEN6_BSD_RING_BASE;
2589                 /* gen6 bsd needs a special wa for tail updates */
2590                 if (IS_GEN6(dev))
2591                         ring->write_tail = gen6_bsd_ring_write_tail;
2592                 ring->flush = gen6_bsd_ring_flush;
2593                 ring->add_request = gen6_add_request;
2594                 ring->get_seqno = gen6_ring_get_seqno;
2595                 ring->set_seqno = ring_set_seqno;
2596                 if (INTEL_INFO(dev)->gen >= 8) {
2597                         ring->irq_enable_mask =
2598                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2599                         ring->irq_get = gen8_ring_get_irq;
2600                         ring->irq_put = gen8_ring_put_irq;
2601                         ring->dispatch_execbuffer =
2602                                 gen8_ring_dispatch_execbuffer;
2603                         if (i915_semaphore_is_enabled(dev)) {
2604                                 ring->semaphore.sync_to = gen8_ring_sync;
2605                                 ring->semaphore.signal = gen8_xcs_signal;
2606                                 GEN8_RING_SEMAPHORE_INIT;
2607                         }
2608                 } else {
2609                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2610                         ring->irq_get = gen6_ring_get_irq;
2611                         ring->irq_put = gen6_ring_put_irq;
2612                         ring->dispatch_execbuffer =
2613                                 gen6_ring_dispatch_execbuffer;
2614                         if (i915_semaphore_is_enabled(dev)) {
2615                                 ring->semaphore.sync_to = gen6_ring_sync;
2616                                 ring->semaphore.signal = gen6_signal;
2617                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2618                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2619                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2620                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2621                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2622                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2623                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2624                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2625                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2626                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2627                         }
2628                 }
2629         } else {
2630                 ring->mmio_base = BSD_RING_BASE;
2631                 ring->flush = bsd_ring_flush;
2632                 ring->add_request = i9xx_add_request;
2633                 ring->get_seqno = ring_get_seqno;
2634                 ring->set_seqno = ring_set_seqno;
2635                 if (IS_GEN5(dev)) {
2636                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2637                         ring->irq_get = gen5_ring_get_irq;
2638                         ring->irq_put = gen5_ring_put_irq;
2639                 } else {
2640                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2641                         ring->irq_get = i9xx_ring_get_irq;
2642                         ring->irq_put = i9xx_ring_put_irq;
2643                 }
2644                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2645         }
2646         ring->init_hw = init_ring_common;
2647
2648         return intel_init_ring_buffer(dev, ring);
2649 }
2650
2651 /**
2652  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2653  */
2654 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2655 {
2656         struct drm_i915_private *dev_priv = dev->dev_private;
2657         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2658
2659         ring->name = "bsd2 ring";
2660         ring->id = VCS2;
2661
2662         ring->write_tail = ring_write_tail;
2663         ring->mmio_base = GEN8_BSD2_RING_BASE;
2664         ring->flush = gen6_bsd_ring_flush;
2665         ring->add_request = gen6_add_request;
2666         ring->get_seqno = gen6_ring_get_seqno;
2667         ring->set_seqno = ring_set_seqno;
2668         ring->irq_enable_mask =
2669                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2670         ring->irq_get = gen8_ring_get_irq;
2671         ring->irq_put = gen8_ring_put_irq;
2672         ring->dispatch_execbuffer =
2673                         gen8_ring_dispatch_execbuffer;
2674         if (i915_semaphore_is_enabled(dev)) {
2675                 ring->semaphore.sync_to = gen8_ring_sync;
2676                 ring->semaphore.signal = gen8_xcs_signal;
2677                 GEN8_RING_SEMAPHORE_INIT;
2678         }
2679         ring->init_hw = init_ring_common;
2680
2681         return intel_init_ring_buffer(dev, ring);
2682 }
2683
2684 int intel_init_blt_ring_buffer(struct drm_device *dev)
2685 {
2686         struct drm_i915_private *dev_priv = dev->dev_private;
2687         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2688
2689         ring->name = "blitter ring";
2690         ring->id = BCS;
2691
2692         ring->mmio_base = BLT_RING_BASE;
2693         ring->write_tail = ring_write_tail;
2694         ring->flush = gen6_ring_flush;
2695         ring->add_request = gen6_add_request;
2696         ring->get_seqno = gen6_ring_get_seqno;
2697         ring->set_seqno = ring_set_seqno;
2698         if (INTEL_INFO(dev)->gen >= 8) {
2699                 ring->irq_enable_mask =
2700                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2701                 ring->irq_get = gen8_ring_get_irq;
2702                 ring->irq_put = gen8_ring_put_irq;
2703                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2704                 if (i915_semaphore_is_enabled(dev)) {
2705                         ring->semaphore.sync_to = gen8_ring_sync;
2706                         ring->semaphore.signal = gen8_xcs_signal;
2707                         GEN8_RING_SEMAPHORE_INIT;
2708                 }
2709         } else {
2710                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2711                 ring->irq_get = gen6_ring_get_irq;
2712                 ring->irq_put = gen6_ring_put_irq;
2713                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2714                 if (i915_semaphore_is_enabled(dev)) {
2715                         ring->semaphore.signal = gen6_signal;
2716                         ring->semaphore.sync_to = gen6_ring_sync;
2717                         /*
2718                          * The current semaphore is only applied on pre-gen8
2719                          * platform.  And there is no VCS2 ring on the pre-gen8
2720                          * platform. So the semaphore between BCS and VCS2 is
2721                          * initialized as INVALID.  Gen8 will initialize the
2722                          * sema between BCS and VCS2 later.
2723                          */
2724                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2725                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2726                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2727                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2728                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2729                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2730                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2731                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2732                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2733                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2734                 }
2735         }
2736         ring->init_hw = init_ring_common;
2737
2738         return intel_init_ring_buffer(dev, ring);
2739 }
2740
2741 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2742 {
2743         struct drm_i915_private *dev_priv = dev->dev_private;
2744         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2745
2746         ring->name = "video enhancement ring";
2747         ring->id = VECS;
2748
2749         ring->mmio_base = VEBOX_RING_BASE;
2750         ring->write_tail = ring_write_tail;
2751         ring->flush = gen6_ring_flush;
2752         ring->add_request = gen6_add_request;
2753         ring->get_seqno = gen6_ring_get_seqno;
2754         ring->set_seqno = ring_set_seqno;
2755
2756         if (INTEL_INFO(dev)->gen >= 8) {
2757                 ring->irq_enable_mask =
2758                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2759                 ring->irq_get = gen8_ring_get_irq;
2760                 ring->irq_put = gen8_ring_put_irq;
2761                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2762                 if (i915_semaphore_is_enabled(dev)) {
2763                         ring->semaphore.sync_to = gen8_ring_sync;
2764                         ring->semaphore.signal = gen8_xcs_signal;
2765                         GEN8_RING_SEMAPHORE_INIT;
2766                 }
2767         } else {
2768                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2769                 ring->irq_get = hsw_vebox_get_irq;
2770                 ring->irq_put = hsw_vebox_put_irq;
2771                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2772                 if (i915_semaphore_is_enabled(dev)) {
2773                         ring->semaphore.sync_to = gen6_ring_sync;
2774                         ring->semaphore.signal = gen6_signal;
2775                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2776                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2777                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2778                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2779                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2780                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2781                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2782                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2783                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2784                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2785                 }
2786         }
2787         ring->init_hw = init_ring_common;
2788
2789         return intel_init_ring_buffer(dev, ring);
2790 }
2791
2792 int
2793 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2794 {
2795         int ret;
2796
2797         if (!ring->gpu_caches_dirty)
2798                 return 0;
2799
2800         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2801         if (ret)
2802                 return ret;
2803
2804         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2805
2806         ring->gpu_caches_dirty = false;
2807         return 0;
2808 }
2809
2810 int
2811 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2812 {
2813         uint32_t flush_domains;
2814         int ret;
2815
2816         flush_domains = 0;
2817         if (ring->gpu_caches_dirty)
2818                 flush_domains = I915_GEM_GPU_DOMAINS;
2819
2820         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2821         if (ret)
2822                 return ret;
2823
2824         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2825
2826         ring->gpu_caches_dirty = false;
2827         return 0;
2828 }
2829
2830 void
2831 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2832 {
2833         int ret;
2834
2835         if (!intel_ring_initialized(ring))
2836                 return;
2837
2838         ret = intel_ring_idle(ring);
2839         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2840                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2841                           ring->name, ret);
2842
2843         stop_ring(ring);
2844 }