drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct intel_engine_cs *ring,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         u32 cmd;
  99         int ret;
 100
 101         cmd = MI_FLUSH;
 102         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 103                 cmd |= MI_NO_WRITE_FLUSH;
 104
 105         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                 cmd |= MI_READ_FLUSH;
 107
 108         ret = intel_ring_begin(ring, 2);
 109         if (ret)
 110                 return ret;
 111
 112         intel_ring_emit(ring, cmd);
 113         intel_ring_emit(ring, MI_NOOP);
 114         intel_ring_advance(ring);
 115
 116         return 0;
 117 }
 118
 119 static int
 120 gen4_render_ring_flush(struct intel_engine_cs *ring,
 121                        u32      invalidate_domains,
 122                        u32      flush_domains)
 123 {
 124         struct drm_device *dev = ring->dev;
 125         u32 cmd;
 126         int ret;
 127
 128         /*
 129          * read/write caches:
 130          *
 131          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 132          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 133          * also flushed at 2d versus 3d pipeline switches.
 134          *
 135          * read-only caches:
 136          *
 137          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 138          * MI_READ_FLUSH is set, and is always flushed on 965.
 139          *
 140          * I915_GEM_DOMAIN_COMMAND may not exist?
 141          *
 142          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 143          * invalidated when MI_EXE_FLUSH is set.
 144          *
 145          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 146          * invalidated with every MI_FLUSH.
 147          *
 148          * TLBs:
 149          *
 150          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 151          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 152          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 153          * are flushed at any MI_FLUSH.
 154          */
 155
 156         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 157         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 158                 cmd &= ~MI_NO_WRITE_FLUSH;
 159         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 160                 cmd |= MI_EXE_FLUSH;
 161
 162         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 163             (IS_G4X(dev) || IS_GEN5(dev)))
 164                 cmd |= MI_INVALIDATE_ISP;
 165
 166         ret = intel_ring_begin(ring, 2);
 167         if (ret)
 168                 return ret;
 169
 170         intel_ring_emit(ring, cmd);
 171         intel_ring_emit(ring, MI_NOOP);
 172         intel_ring_advance(ring);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 179  * implementing two workarounds on gen6.  From section 1.4.7.1
 180  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 181  *
 182  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 183  * produced by non-pipelined state commands), software needs to first
 184  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 185  * 0.
 186  *
 187  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 188  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 189  *
 190  * And the workaround for these two requires this workaround first:
 191  *
 192  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 193  * BEFORE the pipe-control with a post-sync op and no write-cache
 194  * flushes.
 195  *
 196  * And this last workaround is tricky because of the requirements on
 197  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 198  * volume 2 part 1:
 199  *
 200  *     "1 of the following must also be set:
 201  *      - Render Target Cache Flush Enable ([12] of DW1)
 202  *      - Depth Cache Flush Enable ([0] of DW1)
 203  *      - Stall at Pixel Scoreboard ([1] of DW1)
 204  *      - Depth Stall ([13] of DW1)
 205  *      - Post-Sync Operation ([13] of DW1)
 206  *      - Notify Enable ([8] of DW1)"
 207  *
 208  * The cache flushes require the workaround flush that triggered this
 209  * one, so we can't use it.  Depth stall would trigger the same.
 210  * Post-sync nonzero is what triggered this second workaround, so we
 211  * can't use that one either.  Notify enable is IRQs, which aren't
 212  * really our business.  That leaves only stall at scoreboard.
 213  */
 214 static int
 215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 216 {
 217         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 218         int ret;
 219
 220
 221         ret = intel_ring_begin(ring, 6);
 222         if (ret)
 223                 return ret;
 224
 225         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 226         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 227                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 228         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 229         intel_ring_emit(ring, 0); /* low dword */
 230         intel_ring_emit(ring, 0); /* high dword */
 231         intel_ring_emit(ring, MI_NOOP);
 232         intel_ring_advance(ring);
 233
 234         ret = intel_ring_begin(ring, 6);
 235         if (ret)
 236                 return ret;
 237
 238         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 239         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 240         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 241         intel_ring_emit(ring, 0);
 242         intel_ring_emit(ring, 0);
 243         intel_ring_emit(ring, MI_NOOP);
 244         intel_ring_advance(ring);
 245
 246         return 0;
 247 }
 248
 249 static int
 250 gen6_render_ring_flush(struct intel_engine_cs *ring,
 251                          u32 invalidate_domains, u32 flush_domains)
 252 {
 253         u32 flags = 0;
 254         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 255         int ret;
 256
 257         /* Force SNB workarounds for PIPE_CONTROL flushes */
 258         ret = intel_emit_post_sync_nonzero_flush(ring);
 259         if (ret)
 260                 return ret;
 261
 262         /* Just flush everything.  Experiments have shown that reducing the
 263          * number of bits based on the write domains has little performance
 264          * impact.
 265          */
 266         if (flush_domains) {
 267                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 268                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 269                 /*
 270                  * Ensure that any following seqno writes only happen
 271                  * when the render cache is indeed flushed.
 272                  */
 273                 flags |= PIPE_CONTROL_CS_STALL;
 274         }
 275         if (invalidate_domains) {
 276                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 277                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 278                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 279                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 280                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 282                 /*
 283                  * TLB invalidate requires a post-sync write.
 284                  */
 285                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 286         }
 287
 288         ret = intel_ring_begin(ring, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(ring, flags);
 294         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 295         intel_ring_emit(ring, 0);
 296         intel_ring_advance(ring);
 297
 298         return 0;
 299 }
 300
 301 static int
 302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 303 {
 304         int ret;
 305
 306         ret = intel_ring_begin(ring, 4);
 307         if (ret)
 308                 return ret;
 309
 310         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 311         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 312                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 313         intel_ring_emit(ring, 0);
 314         intel_ring_emit(ring, 0);
 315         intel_ring_advance(ring);
 316
 317         return 0;
 318 }
 319
 320 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
 321 {
 322         int ret;
 323
 324         if (!ring->fbc_dirty)
 325                 return 0;
 326
 327         ret = intel_ring_begin(ring, 6);
 328         if (ret)
 329                 return ret;
 330         /* WaFbcNukeOn3DBlt:ivb/hsw */
 331         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 332         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 333         intel_ring_emit(ring, value);
 334         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 335         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 336         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 337         intel_ring_advance(ring);
 338
 339         ring->fbc_dirty = false;
 340         return 0;
 341 }
 342
 343 static int
 344 gen7_render_ring_flush(struct intel_engine_cs *ring,
 345                        u32 invalidate_domains, u32 flush_domains)
 346 {
 347         u32 flags = 0;
 348         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 349         int ret;
 350
 351         /*
 352          * Ensure that any following seqno writes only happen when the render
 353          * cache is indeed flushed.
 354          *
 355          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 356          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 357          * don't try to be clever and just set it unconditionally.
 358          */
 359         flags |= PIPE_CONTROL_CS_STALL;
 360
 361         /* Just flush everything.  Experiments have shown that reducing the
 362          * number of bits based on the write domains has little performance
 363          * impact.
 364          */
 365         if (flush_domains) {
 366                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 367                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 368         }
 369         if (invalidate_domains) {
 370                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 371                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 372                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 373                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 374                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 375                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 376                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 377                 /*
 378                  * TLB invalidate requires a post-sync write.
 379                  */
 380                 flags |= PIPE_CONTROL_QW_WRITE;
 381                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 382
 383                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 384
 385                 /* Workaround: we must issue a pipe_control with CS-stall bit
 386                  * set before a pipe_control command that has the state cache
 387                  * invalidate bit set. */
 388                 gen7_render_ring_cs_stall_wa(ring);
 389         }
 390
 391         ret = intel_ring_begin(ring, 4);
 392         if (ret)
 393                 return ret;
 394
 395         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 396         intel_ring_emit(ring, flags);
 397         intel_ring_emit(ring, scratch_addr);
 398         intel_ring_emit(ring, 0);
 399         intel_ring_advance(ring);
 400
 401         if (!invalidate_domains && flush_domains)
 402                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 403
 404         return 0;
 405 }
 406
 407 static int
 408 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 409                        u32 flags, u32 scratch_addr)
 410 {
 411         int ret;
 412
 413         ret = intel_ring_begin(ring, 6);
 414         if (ret)
 415                 return ret;
 416
 417         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 418         intel_ring_emit(ring, flags);
 419         intel_ring_emit(ring, scratch_addr);
 420         intel_ring_emit(ring, 0);
 421         intel_ring_emit(ring, 0);
 422         intel_ring_emit(ring, 0);
 423         intel_ring_advance(ring);
 424
 425         return 0;
 426 }
 427
 428 static int
 429 gen8_render_ring_flush(struct intel_engine_cs *ring,
 430                        u32 invalidate_domains, u32 flush_domains)
 431 {
 432         u32 flags = 0;
 433         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 434         int ret;
 435
 436         flags |= PIPE_CONTROL_CS_STALL;
 437
 438         if (flush_domains) {
 439                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 440                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 441         }
 442         if (invalidate_domains) {
 443                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 444                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 445                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 446                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 447                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 448                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 449                 flags |= PIPE_CONTROL_QW_WRITE;
 450                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 451
 452                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 453                 ret = gen8_emit_pipe_control(ring,
 454                                              PIPE_CONTROL_CS_STALL |
 455                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 456                                              0);
 457                 if (ret)
 458                         return ret;
 459         }
 460
 461         ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
 462         if (ret)
 463                 return ret;
 464
 465         if (!invalidate_domains && flush_domains)
 466                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 467
 468         return 0;
 469 }
 470
 471 static void ring_write_tail(struct intel_engine_cs *ring,
 472                             u32 value)
 473 {
 474         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 475         I915_WRITE_TAIL(ring, value);
 476 }
 477
 478 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 479 {
 480         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 481         u64 acthd;
 482
 483         if (INTEL_INFO(ring->dev)->gen >= 8)
 484                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 485                                          RING_ACTHD_UDW(ring->mmio_base));
 486         else if (INTEL_INFO(ring->dev)->gen >= 4)
 487                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 488         else
 489                 acthd = I915_READ(ACTHD);
 490
 491         return acthd;
 492 }
 493
 494 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 495 {
 496         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 497         u32 addr;
 498
 499         addr = dev_priv->status_page_dmah->busaddr;
 500         if (INTEL_INFO(ring->dev)->gen >= 4)
 501                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 502         I915_WRITE(HWS_PGA, addr);
 503 }
 504
 505 static bool stop_ring(struct intel_engine_cs *ring)
 506 {
 507         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 508
 509         if (!IS_GEN2(ring->dev)) {
 510                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 511                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 512                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 513                         /* Sometimes we observe that the idle flag is not
 514                          * set even though the ring is empty. So double
 515                          * check before giving up.
 516                          */
 517                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 518                                 return false;
 519                 }
 520         }
 521
 522         I915_WRITE_CTL(ring, 0);
 523         I915_WRITE_HEAD(ring, 0);
 524         ring->write_tail(ring, 0);
 525
 526         if (!IS_GEN2(ring->dev)) {
 527                 (void)I915_READ_CTL(ring);
 528                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 529         }
 530
 531         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 532 }
 533
 534 static int init_ring_common(struct intel_engine_cs *ring)
 535 {
 536         struct drm_device *dev = ring->dev;
 537         struct drm_i915_private *dev_priv = dev->dev_private;
 538         struct intel_ringbuffer *ringbuf = ring->buffer;
 539         struct drm_i915_gem_object *obj = ringbuf->obj;
 540         int ret = 0;
 541
 542         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 543
 544         if (!stop_ring(ring)) {
 545                 /* G45 ring initialization often fails to reset head to zero */
 546                 DRM_DEBUG_KMS("%s head not reset to zero "
 547                               "ctl %08x head %08x tail %08x start %08x\n",
 548                               ring->name,
 549                               I915_READ_CTL(ring),
 550                               I915_READ_HEAD(ring),
 551                               I915_READ_TAIL(ring),
 552                               I915_READ_START(ring));
 553
 554                 if (!stop_ring(ring)) {
 555                         DRM_ERROR("failed to set %s head to zero "
 556                                   "ctl %08x head %08x tail %08x start %08x\n",
 557                                   ring->name,
 558                                   I915_READ_CTL(ring),
 559                                   I915_READ_HEAD(ring),
 560                                   I915_READ_TAIL(ring),
 561                                   I915_READ_START(ring));
 562                         ret = -EIO;
 563                         goto out;
 564                 }
 565         }
 566
 567         if (I915_NEED_GFX_HWS(dev))
 568                 intel_ring_setup_status_page(ring);
 569         else
 570                 ring_setup_phys_status_page(ring);
 571
 572         /* Enforce ordering by reading HEAD register back */
 573         I915_READ_HEAD(ring);
 574
 575         /* Initialize the ring. This must happen _after_ we've cleared the ring
 576          * registers with the above sequence (the readback of the HEAD registers
 577          * also enforces ordering), otherwise the hw might lose the new ring
 578          * register values. */
 579         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 580
 581         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 582         if (I915_READ_HEAD(ring))
 583                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 584                           ring->name, I915_READ_HEAD(ring));
 585         I915_WRITE_HEAD(ring, 0);
 586         (void)I915_READ_HEAD(ring);
 587
 588         I915_WRITE_CTL(ring,
 589                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 590                         | RING_VALID);
 591
 592         /* If the head is still not zero, the ring is dead */
 593         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 594                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 595                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 596                 DRM_ERROR("%s initialization failed "
 597                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 598                           ring->name,
 599                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 600                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 601                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 602                 ret = -EIO;
 603                 goto out;
 604         }
 605
 606         ringbuf->last_retired_head = -1;
 607         ringbuf->head = I915_READ_HEAD(ring);
 608         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 609         intel_ring_update_space(ringbuf);
 610
 611         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 612
 613 out:
 614         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 615
 616         return ret;
 617 }
 618
 619 void
 620 intel_fini_pipe_control(struct intel_engine_cs *ring)
 621 {
 622         struct drm_device *dev = ring->dev;
 623
 624         if (ring->scratch.obj == NULL)
 625                 return;
 626
 627         if (INTEL_INFO(dev)->gen >= 5) {
 628                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 629                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 630         }
 631
 632         drm_gem_object_unreference(&ring->scratch.obj->base);
 633         ring->scratch.obj = NULL;
 634 }
 635
 636 int
 637 intel_init_pipe_control(struct intel_engine_cs *ring)
 638 {
 639         int ret;
 640
 641         WARN_ON(ring->scratch.obj);
 642
 643         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 644         if (ring->scratch.obj == NULL) {
 645                 DRM_ERROR("Failed to allocate seqno page\n");
 646                 ret = -ENOMEM;
 647                 goto err;
 648         }
 649
 650         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 651         if (ret)
 652                 goto err_unref;
 653
 654         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 655         if (ret)
 656                 goto err_unref;
 657
 658         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 659         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 660         if (ring->scratch.cpu_page == NULL) {
 661                 ret = -ENOMEM;
 662                 goto err_unpin;
 663         }
 664
 665         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 666                          ring->name, ring->scratch.gtt_offset);
 667         return 0;
 668
 669 err_unpin:
 670         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 671 err_unref:
 672         drm_gem_object_unreference(&ring->scratch.obj->base);
 673 err:
 674         return ret;
 675 }
 676
 677 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
 678                                        struct intel_context *ctx)
 679 {
 680         int ret, i;
 681         struct drm_device *dev = ring->dev;
 682         struct drm_i915_private *dev_priv = dev->dev_private;
 683         struct i915_workarounds *w = &dev_priv->workarounds;
 684
 685         if (WARN_ON_ONCE(w->count == 0))
 686                 return 0;
 687
 688         ring->gpu_caches_dirty = true;
 689         ret = intel_ring_flush_all_caches(ring);
 690         if (ret)
 691                 return ret;
 692
 693         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 694         if (ret)
 695                 return ret;
 696
 697         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 698         for (i = 0; i < w->count; i++) {
 699                 intel_ring_emit(ring, w->reg[i].addr);
 700                 intel_ring_emit(ring, w->reg[i].value);
 701         }
 702         intel_ring_emit(ring, MI_NOOP);
 703
 704         intel_ring_advance(ring);
 705
 706         ring->gpu_caches_dirty = true;
 707         ret = intel_ring_flush_all_caches(ring);
 708         if (ret)
 709                 return ret;
 710
 711         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 712
 713         return 0;
 714 }
 715
 716 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
 717                               struct intel_context *ctx)
 718 {
 719         int ret;
 720
 721         ret = intel_ring_workarounds_emit(ring, ctx);
 722         if (ret != 0)
 723                 return ret;
 724
 725         ret = i915_gem_render_state_init(ring);
 726         if (ret)
 727                 DRM_ERROR("init render state: %d\n", ret);
 728
 729         return ret;
 730 }
 731
 732 static int wa_add(struct drm_i915_private *dev_priv,
 733                   const u32 addr, const u32 mask, const u32 val)
 734 {
 735         const u32 idx = dev_priv->workarounds.count;
 736
 737         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 738                 return -ENOSPC;
 739
 740         dev_priv->workarounds.reg[idx].addr = addr;
 741         dev_priv->workarounds.reg[idx].value = val;
 742         dev_priv->workarounds.reg[idx].mask = mask;
 743
 744         dev_priv->workarounds.count++;
 745
 746         return 0;
 747 }
 748
 749 #define WA_REG(addr, mask, val) { \
 750                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 751                 if (r) \
 752                         return r; \
 753         }
 754
 755 #define WA_SET_BIT_MASKED(addr, mask) \
 756         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 757
 758 #define WA_CLR_BIT_MASKED(addr, mask) \
 759         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 760
 761 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 762         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 763
 764 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 765 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 766
 767 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 768
 769 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 770 {
 771         struct drm_device *dev = ring->dev;
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773
 774         /* WaDisablePartialInstShootdown:bdw */
 775         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 776         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 777                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 778                           STALL_DOP_GATING_DISABLE);
 779
 780         /* WaDisableDopClockGating:bdw */
 781         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 782                           DOP_CLOCK_GATING_DISABLE);
 783
 784         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 785                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 786
 787         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 788          * workaround for for a possible hang in the unlikely event a TLB
 789          * invalidation occurs during a PSD flush.
 790          */
 791         /* WaForceEnableNonCoherent:bdw */
 792         /* WaHdcDisableFetchWhenMasked:bdw */
 793         /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
 794         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 795                           HDC_FORCE_NON_COHERENT |
 796                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 797                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 798
 799         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 800          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 801          *  polygons in the same 8x4 pixel/sample area to be processed without
 802          *  stalling waiting for the earlier ones to write to Hierarchical Z
 803          *  buffer."
 804          *
 805          * This optimization is off by default for Broadwell; turn it on.
 806          */
 807         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 808
 809         /* Wa4x4STCOptimizationDisable:bdw */
 810         WA_SET_BIT_MASKED(CACHE_MODE_1,
 811                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 812
 813         /*
 814          * BSpec recommends 8x4 when MSAA is used,
 815          * however in practice 16x4 seems fastest.
 816          *
 817          * Note that PS/WM thread counts depend on the WIZ hashing
 818          * disable bit, which we don't touch here, but it's good
 819          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 820          */
 821         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 822                             GEN6_WIZ_HASHING_MASK,
 823                             GEN6_WIZ_HASHING_16x4);
 824
 825         return 0;
 826 }
 827
 828 static int chv_init_workarounds(struct intel_engine_cs *ring)
 829 {
 830         struct drm_device *dev = ring->dev;
 831         struct drm_i915_private *dev_priv = dev->dev_private;
 832
 833         /* WaDisablePartialInstShootdown:chv */
 834         /* WaDisableThreadStallDopClockGating:chv */
 835         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 836                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 837                           STALL_DOP_GATING_DISABLE);
 838
 839         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 840          * workaround for a possible hang in the unlikely event a TLB
 841          * invalidation occurs during a PSD flush.
 842          */
 843         /* WaForceEnableNonCoherent:chv */
 844         /* WaHdcDisableFetchWhenMasked:chv */
 845         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 846                           HDC_FORCE_NON_COHERENT |
 847                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 848
 849         /* According to the CACHE_MODE_0 default value documentation, some
 850          * CHV platforms disable this optimization by default.  Turn it on.
 851          */
 852         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 853
 854         /* Wa4x4STCOptimizationDisable:chv */
 855         WA_SET_BIT_MASKED(CACHE_MODE_1,
 856                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 857
 858         /* Improve HiZ throughput on CHV. */
 859         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 860
 861         /*
 862          * BSpec recommends 8x4 when MSAA is used,
 863          * however in practice 16x4 seems fastest.
 864          *
 865          * Note that PS/WM thread counts depend on the WIZ hashing
 866          * disable bit, which we don't touch here, but it's good
 867          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 868          */
 869         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 870                             GEN6_WIZ_HASHING_MASK,
 871                             GEN6_WIZ_HASHING_16x4);
 872
 873         return 0;
 874 }
 875
 876 int init_workarounds_ring(struct intel_engine_cs *ring)
 877 {
 878         struct drm_device *dev = ring->dev;
 879         struct drm_i915_private *dev_priv = dev->dev_private;
 880
 881         WARN_ON(ring->id != RCS);
 882
 883         dev_priv->workarounds.count = 0;
 884
 885         if (IS_BROADWELL(dev))
 886                 return bdw_init_workarounds(ring);
 887
 888         if (IS_CHERRYVIEW(dev))
 889                 return chv_init_workarounds(ring);
 890
 891         return 0;
 892 }
 893
 894 static int init_render_ring(struct intel_engine_cs *ring)
 895 {
 896         struct drm_device *dev = ring->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898         int ret = init_ring_common(ring);
 899         if (ret)
 900                 return ret;
 901
 902         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 903         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
 904                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 905
 906         /* We need to disable the AsyncFlip performance optimisations in order
 907          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 908          * programmed to '1' on all products.
 909          *
 910          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
 911          */
 912         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
 913                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 914
 915         /* Required for the hardware to program scanline values for waiting */
 916         /* WaEnableFlushTlbInvalidationMode:snb */
 917         if (INTEL_INFO(dev)->gen == 6)
 918                 I915_WRITE(GFX_MODE,
 919                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 920
 921         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 922         if (IS_GEN7(dev))
 923                 I915_WRITE(GFX_MODE_GEN7,
 924                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 925                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 926
 927         if (IS_GEN6(dev)) {
 928                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 929                  * "If this bit is set, STCunit will have LRA as replacement
 930                  *  policy. [...] This bit must be reset.  LRA replacement
 931                  *  policy is not supported."
 932                  */
 933                 I915_WRITE(CACHE_MODE_0,
 934                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 935         }
 936
 937         if (INTEL_INFO(dev)->gen >= 6)
 938                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 939
 940         if (HAS_L3_DPF(dev))
 941                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 942
 943         return init_workarounds_ring(ring);
 944 }
 945
 946 static void render_ring_cleanup(struct intel_engine_cs *ring)
 947 {
 948         struct drm_device *dev = ring->dev;
 949         struct drm_i915_private *dev_priv = dev->dev_private;
 950
 951         if (dev_priv->semaphore_obj) {
 952                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
 953                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
 954                 dev_priv->semaphore_obj = NULL;
 955         }
 956
 957         intel_fini_pipe_control(ring);
 958 }
 959
 960 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
 961                            unsigned int num_dwords)
 962 {
 963 #define MBOX_UPDATE_DWORDS 8
 964         struct drm_device *dev = signaller->dev;
 965         struct drm_i915_private *dev_priv = dev->dev_private;
 966         struct intel_engine_cs *waiter;
 967         int i, ret, num_rings;
 968
 969         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 970         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 971 #undef MBOX_UPDATE_DWORDS
 972
 973         ret = intel_ring_begin(signaller, num_dwords);
 974         if (ret)
 975                 return ret;
 976
 977         for_each_ring(waiter, dev_priv, i) {
 978                 u32 seqno;
 979                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 980                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 981                         continue;
 982
 983                 seqno = i915_gem_request_get_seqno(
 984                                            signaller->outstanding_lazy_request);
 985                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
 986                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
 987                                            PIPE_CONTROL_QW_WRITE |
 988                                            PIPE_CONTROL_FLUSH_ENABLE);
 989                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
 990                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 991                 intel_ring_emit(signaller, seqno);
 992                 intel_ring_emit(signaller, 0);
 993                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 994                                            MI_SEMAPHORE_TARGET(waiter->id));
 995                 intel_ring_emit(signaller, 0);
 996         }
 997
 998         return 0;
 999 }
1000
1001 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1002                            unsigned int num_dwords)
1003 {
1004 #define MBOX_UPDATE_DWORDS 6
1005         struct drm_device *dev = signaller->dev;
1006         struct drm_i915_private *dev_priv = dev->dev_private;
1007         struct intel_engine_cs *waiter;
1008         int i, ret, num_rings;
1009
1010         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1011         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1012 #undef MBOX_UPDATE_DWORDS
1013
1014         ret = intel_ring_begin(signaller, num_dwords);
1015         if (ret)
1016                 return ret;
1017
1018         for_each_ring(waiter, dev_priv, i) {
1019                 u32 seqno;
1020                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1021                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1022                         continue;
1023
1024                 seqno = i915_gem_request_get_seqno(
1025                                            signaller->outstanding_lazy_request);
1026                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1027                                            MI_FLUSH_DW_OP_STOREDW);
1028                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1029                                            MI_FLUSH_DW_USE_GTT);
1030                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1031                 intel_ring_emit(signaller, seqno);
1032                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1033                                            MI_SEMAPHORE_TARGET(waiter->id));
1034                 intel_ring_emit(signaller, 0);
1035         }
1036
1037         return 0;
1038 }
1039
1040 static int gen6_signal(struct intel_engine_cs *signaller,
1041                        unsigned int num_dwords)
1042 {
1043         struct drm_device *dev = signaller->dev;
1044         struct drm_i915_private *dev_priv = dev->dev_private;
1045         struct intel_engine_cs *useless;
1046         int i, ret, num_rings;
1047
1048 #define MBOX_UPDATE_DWORDS 3
1049         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1050         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1051 #undef MBOX_UPDATE_DWORDS
1052
1053         ret = intel_ring_begin(signaller, num_dwords);
1054         if (ret)
1055                 return ret;
1056
1057         for_each_ring(useless, dev_priv, i) {
1058                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1059                 if (mbox_reg != GEN6_NOSYNC) {
1060                         u32 seqno = i915_gem_request_get_seqno(
1061                                            signaller->outstanding_lazy_request);
1062                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1063                         intel_ring_emit(signaller, mbox_reg);
1064                         intel_ring_emit(signaller, seqno);
1065                 }
1066         }
1067
1068         /* If num_dwords was rounded, make sure the tail pointer is correct */
1069         if (num_rings % 2 == 0)
1070                 intel_ring_emit(signaller, MI_NOOP);
1071
1072         return 0;
1073 }
1074
1075 /**
1076  * gen6_add_request - Update the semaphore mailbox registers
1077  *
1078  * @ring - ring that is adding a request
1079  * @seqno - return seqno stuck into the ring
1080  *
1081  * Update the mailbox registers in the *other* rings with the current seqno.
1082  * This acts like a signal in the canonical semaphore.
1083  */
1084 static int
1085 gen6_add_request(struct intel_engine_cs *ring)
1086 {
1087         int ret;
1088
1089         if (ring->semaphore.signal)
1090                 ret = ring->semaphore.signal(ring, 4);
1091         else
1092                 ret = intel_ring_begin(ring, 4);
1093
1094         if (ret)
1095                 return ret;
1096
1097         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1098         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1099         intel_ring_emit(ring,
1100                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1101         intel_ring_emit(ring, MI_USER_INTERRUPT);
1102         __intel_ring_advance(ring);
1103
1104         return 0;
1105 }
1106
1107 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1108                                               u32 seqno)
1109 {
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         return dev_priv->last_seqno < seqno;
1112 }
1113
1114 /**
1115  * intel_ring_sync - sync the waiter to the signaller on seqno
1116  *
1117  * @waiter - ring that is waiting
1118  * @signaller - ring which has, or will signal
1119  * @seqno - seqno which the waiter will block on
1120  */
1121
1122 static int
1123 gen8_ring_sync(struct intel_engine_cs *waiter,
1124                struct intel_engine_cs *signaller,
1125                u32 seqno)
1126 {
1127         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1128         int ret;
1129
1130         ret = intel_ring_begin(waiter, 4);
1131         if (ret)
1132                 return ret;
1133
1134         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1135                                 MI_SEMAPHORE_GLOBAL_GTT |
1136                                 MI_SEMAPHORE_POLL |
1137                                 MI_SEMAPHORE_SAD_GTE_SDD);
1138         intel_ring_emit(waiter, seqno);
1139         intel_ring_emit(waiter,
1140                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1141         intel_ring_emit(waiter,
1142                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1143         intel_ring_advance(waiter);
1144         return 0;
1145 }
1146
1147 static int
1148 gen6_ring_sync(struct intel_engine_cs *waiter,
1149                struct intel_engine_cs *signaller,
1150                u32 seqno)
1151 {
1152         u32 dw1 = MI_SEMAPHORE_MBOX |
1153                   MI_SEMAPHORE_COMPARE |
1154                   MI_SEMAPHORE_REGISTER;
1155         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1156         int ret;
1157
1158         /* Throughout all of the GEM code, seqno passed implies our current
1159          * seqno is >= the last seqno executed. However for hardware the
1160          * comparison is strictly greater than.
1161          */
1162         seqno -= 1;
1163
1164         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1165
1166         ret = intel_ring_begin(waiter, 4);
1167         if (ret)
1168                 return ret;
1169
1170         /* If seqno wrap happened, omit the wait with no-ops */
1171         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1172                 intel_ring_emit(waiter, dw1 | wait_mbox);
1173                 intel_ring_emit(waiter, seqno);
1174                 intel_ring_emit(waiter, 0);
1175                 intel_ring_emit(waiter, MI_NOOP);
1176         } else {
1177                 intel_ring_emit(waiter, MI_NOOP);
1178                 intel_ring_emit(waiter, MI_NOOP);
1179                 intel_ring_emit(waiter, MI_NOOP);
1180                 intel_ring_emit(waiter, MI_NOOP);
1181         }
1182         intel_ring_advance(waiter);
1183
1184         return 0;
1185 }
1186
1187 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1188 do {                                                                    \
1189         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1190                  PIPE_CONTROL_DEPTH_STALL);                             \
1191         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1192         intel_ring_emit(ring__, 0);                                                     \
1193         intel_ring_emit(ring__, 0);                                                     \
1194 } while (0)
1195
1196 static int
1197 pc_render_add_request(struct intel_engine_cs *ring)
1198 {
1199         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1200         int ret;
1201
1202         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1203          * incoherent with writes to memory, i.e. completely fubar,
1204          * so we need to use PIPE_NOTIFY instead.
1205          *
1206          * However, we also need to workaround the qword write
1207          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1208          * memory before requesting an interrupt.
1209          */
1210         ret = intel_ring_begin(ring, 32);
1211         if (ret)
1212                 return ret;
1213
1214         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1215                         PIPE_CONTROL_WRITE_FLUSH |
1216                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1217         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1218         intel_ring_emit(ring,
1219                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1220         intel_ring_emit(ring, 0);
1221         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1222         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1223         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1224         scratch_addr += 2 * CACHELINE_BYTES;
1225         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1226         scratch_addr += 2 * CACHELINE_BYTES;
1227         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1228         scratch_addr += 2 * CACHELINE_BYTES;
1229         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1230         scratch_addr += 2 * CACHELINE_BYTES;
1231         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1232
1233         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1234                         PIPE_CONTROL_WRITE_FLUSH |
1235                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1236                         PIPE_CONTROL_NOTIFY);
1237         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1238         intel_ring_emit(ring,
1239                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1240         intel_ring_emit(ring, 0);
1241         __intel_ring_advance(ring);
1242
1243         return 0;
1244 }
1245
1246 static u32
1247 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1248 {
1249         /* Workaround to force correct ordering between irq and seqno writes on
1250          * ivb (and maybe also on snb) by reading from a CS register (like
1251          * ACTHD) before reading the status page. */
1252         if (!lazy_coherency) {
1253                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1254                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1255         }
1256
1257         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1258 }
1259
1260 static u32
1261 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1262 {
1263         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1264 }
1265
1266 static void
1267 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1268 {
1269         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1270 }
1271
1272 static u32
1273 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1274 {
1275         return ring->scratch.cpu_page[0];
1276 }
1277
1278 static void
1279 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1280 {
1281         ring->scratch.cpu_page[0] = seqno;
1282 }
1283
1284 static bool
1285 gen5_ring_get_irq(struct intel_engine_cs *ring)
1286 {
1287         struct drm_device *dev = ring->dev;
1288         struct drm_i915_private *dev_priv = dev->dev_private;
1289         unsigned long flags;
1290
1291         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1292                 return false;
1293
1294         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1295         if (ring->irq_refcount++ == 0)
1296                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1297         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1298
1299         return true;
1300 }
1301
1302 static void
1303 gen5_ring_put_irq(struct intel_engine_cs *ring)
1304 {
1305         struct drm_device *dev = ring->dev;
1306         struct drm_i915_private *dev_priv = dev->dev_private;
1307         unsigned long flags;
1308
1309         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1310         if (--ring->irq_refcount == 0)
1311                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1312         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1313 }
1314
1315 static bool
1316 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1317 {
1318         struct drm_device *dev = ring->dev;
1319         struct drm_i915_private *dev_priv = dev->dev_private;
1320         unsigned long flags;
1321
1322         if (!intel_irqs_enabled(dev_priv))
1323                 return false;
1324
1325         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1326         if (ring->irq_refcount++ == 0) {
1327                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1328                 I915_WRITE(IMR, dev_priv->irq_mask);
1329                 POSTING_READ(IMR);
1330         }
1331         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1332
1333         return true;
1334 }
1335
1336 static void
1337 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1338 {
1339         struct drm_device *dev = ring->dev;
1340         struct drm_i915_private *dev_priv = dev->dev_private;
1341         unsigned long flags;
1342
1343         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1344         if (--ring->irq_refcount == 0) {
1345                 dev_priv->irq_mask |= ring->irq_enable_mask;
1346                 I915_WRITE(IMR, dev_priv->irq_mask);
1347                 POSTING_READ(IMR);
1348         }
1349         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1350 }
1351
1352 static bool
1353 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1354 {
1355         struct drm_device *dev = ring->dev;
1356         struct drm_i915_private *dev_priv = dev->dev_private;
1357         unsigned long flags;
1358
1359         if (!intel_irqs_enabled(dev_priv))
1360                 return false;
1361
1362         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1363         if (ring->irq_refcount++ == 0) {
1364                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1365                 I915_WRITE16(IMR, dev_priv->irq_mask);
1366                 POSTING_READ16(IMR);
1367         }
1368         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1369
1370         return true;
1371 }
1372
1373 static void
1374 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1375 {
1376         struct drm_device *dev = ring->dev;
1377         struct drm_i915_private *dev_priv = dev->dev_private;
1378         unsigned long flags;
1379
1380         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1381         if (--ring->irq_refcount == 0) {
1382                 dev_priv->irq_mask |= ring->irq_enable_mask;
1383                 I915_WRITE16(IMR, dev_priv->irq_mask);
1384                 POSTING_READ16(IMR);
1385         }
1386         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1387 }
1388
1389 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1390 {
1391         struct drm_device *dev = ring->dev;
1392         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1393         u32 mmio = 0;
1394
1395         /* The ring status page addresses are no longer next to the rest of
1396          * the ring registers as of gen7.
1397          */
1398         if (IS_GEN7(dev)) {
1399                 switch (ring->id) {
1400                 case RCS:
1401                         mmio = RENDER_HWS_PGA_GEN7;
1402                         break;
1403                 case BCS:
1404                         mmio = BLT_HWS_PGA_GEN7;
1405                         break;
1406                 /*
1407                  * VCS2 actually doesn't exist on Gen7. Only shut up
1408                  * gcc switch check warning
1409                  */
1410                 case VCS2:
1411                 case VCS:
1412                         mmio = BSD_HWS_PGA_GEN7;
1413                         break;
1414                 case VECS:
1415                         mmio = VEBOX_HWS_PGA_GEN7;
1416                         break;
1417                 }
1418         } else if (IS_GEN6(ring->dev)) {
1419                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1420         } else {
1421                 /* XXX: gen8 returns to sanity */
1422                 mmio = RING_HWS_PGA(ring->mmio_base);
1423         }
1424
1425         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1426         POSTING_READ(mmio);
1427
1428         /*
1429          * Flush the TLB for this page
1430          *
1431          * FIXME: These two bits have disappeared on gen8, so a question
1432          * arises: do we still need this and if so how should we go about
1433          * invalidating the TLB?
1434          */
1435         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1436                 u32 reg = RING_INSTPM(ring->mmio_base);
1437
1438                 /* ring should be idle before issuing a sync flush*/
1439                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1440
1441                 I915_WRITE(reg,
1442                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1443                                               INSTPM_SYNC_FLUSH));
1444                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1445                              1000))
1446                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1447                                   ring->name);
1448         }
1449 }
1450
1451 static int
1452 bsd_ring_flush(struct intel_engine_cs *ring,
1453                u32     invalidate_domains,
1454                u32     flush_domains)
1455 {
1456         int ret;
1457
1458         ret = intel_ring_begin(ring, 2);
1459         if (ret)
1460                 return ret;
1461
1462         intel_ring_emit(ring, MI_FLUSH);
1463         intel_ring_emit(ring, MI_NOOP);
1464         intel_ring_advance(ring);
1465         return 0;
1466 }
1467
1468 static int
1469 i9xx_add_request(struct intel_engine_cs *ring)
1470 {
1471         int ret;
1472
1473         ret = intel_ring_begin(ring, 4);
1474         if (ret)
1475                 return ret;
1476
1477         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1478         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1479         intel_ring_emit(ring,
1480                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1481         intel_ring_emit(ring, MI_USER_INTERRUPT);
1482         __intel_ring_advance(ring);
1483
1484         return 0;
1485 }
1486
1487 static bool
1488 gen6_ring_get_irq(struct intel_engine_cs *ring)
1489 {
1490         struct drm_device *dev = ring->dev;
1491         struct drm_i915_private *dev_priv = dev->dev_private;
1492         unsigned long flags;
1493
1494         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1495                 return false;
1496
1497         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1498         if (ring->irq_refcount++ == 0) {
1499                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1500                         I915_WRITE_IMR(ring,
1501                                        ~(ring->irq_enable_mask |
1502                                          GT_PARITY_ERROR(dev)));
1503                 else
1504                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1505                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1506         }
1507         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1508
1509         return true;
1510 }
1511
1512 static void
1513 gen6_ring_put_irq(struct intel_engine_cs *ring)
1514 {
1515         struct drm_device *dev = ring->dev;
1516         struct drm_i915_private *dev_priv = dev->dev_private;
1517         unsigned long flags;
1518
1519         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1520         if (--ring->irq_refcount == 0) {
1521                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1522                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1523                 else
1524                         I915_WRITE_IMR(ring, ~0);
1525                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1526         }
1527         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1528 }
1529
1530 static bool
1531 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1532 {
1533         struct drm_device *dev = ring->dev;
1534         struct drm_i915_private *dev_priv = dev->dev_private;
1535         unsigned long flags;
1536
1537         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1538                 return false;
1539
1540         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1541         if (ring->irq_refcount++ == 0) {
1542                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1543                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1544         }
1545         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1546
1547         return true;
1548 }
1549
1550 static void
1551 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1552 {
1553         struct drm_device *dev = ring->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         unsigned long flags;
1556
1557         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1558         if (--ring->irq_refcount == 0) {
1559                 I915_WRITE_IMR(ring, ~0);
1560                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1561         }
1562         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1563 }
1564
1565 static bool
1566 gen8_ring_get_irq(struct intel_engine_cs *ring)
1567 {
1568         struct drm_device *dev = ring->dev;
1569         struct drm_i915_private *dev_priv = dev->dev_private;
1570         unsigned long flags;
1571
1572         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1573                 return false;
1574
1575         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1576         if (ring->irq_refcount++ == 0) {
1577                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1578                         I915_WRITE_IMR(ring,
1579                                        ~(ring->irq_enable_mask |
1580                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1581                 } else {
1582                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1583                 }
1584                 POSTING_READ(RING_IMR(ring->mmio_base));
1585         }
1586         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1587
1588         return true;
1589 }
1590
1591 static void
1592 gen8_ring_put_irq(struct intel_engine_cs *ring)
1593 {
1594         struct drm_device *dev = ring->dev;
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596         unsigned long flags;
1597
1598         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1599         if (--ring->irq_refcount == 0) {
1600                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1601                         I915_WRITE_IMR(ring,
1602                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1603                 } else {
1604                         I915_WRITE_IMR(ring, ~0);
1605                 }
1606                 POSTING_READ(RING_IMR(ring->mmio_base));
1607         }
1608         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1609 }
1610
1611 static int
1612 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1613                          u64 offset, u32 length,
1614                          unsigned flags)
1615 {
1616         int ret;
1617
1618         ret = intel_ring_begin(ring, 2);
1619         if (ret)
1620                 return ret;
1621
1622         intel_ring_emit(ring,
1623                         MI_BATCH_BUFFER_START |
1624                         MI_BATCH_GTT |
1625                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1626         intel_ring_emit(ring, offset);
1627         intel_ring_advance(ring);
1628
1629         return 0;
1630 }
1631
1632 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1633 #define I830_BATCH_LIMIT (256*1024)
1634 #define I830_TLB_ENTRIES (2)
1635 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1636 static int
1637 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1638                                 u64 offset, u32 len,
1639                                 unsigned flags)
1640 {
1641         u32 cs_offset = ring->scratch.gtt_offset;
1642         int ret;
1643
1644         ret = intel_ring_begin(ring, 6);
1645         if (ret)
1646                 return ret;
1647
1648         /* Evict the invalid PTE TLBs */
1649         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1650         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1651         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1652         intel_ring_emit(ring, cs_offset);
1653         intel_ring_emit(ring, 0xdeadbeef);
1654         intel_ring_emit(ring, MI_NOOP);
1655         intel_ring_advance(ring);
1656
1657         if ((flags & I915_DISPATCH_PINNED) == 0) {
1658                 if (len > I830_BATCH_LIMIT)
1659                         return -ENOSPC;
1660
1661                 ret = intel_ring_begin(ring, 6 + 2);
1662                 if (ret)
1663                         return ret;
1664
1665                 /* Blit the batch (which has now all relocs applied) to the
1666                  * stable batch scratch bo area (so that the CS never
1667                  * stumbles over its tlb invalidation bug) ...
1668                  */
1669                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1670                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1671                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1672                 intel_ring_emit(ring, cs_offset);
1673                 intel_ring_emit(ring, 4096);
1674                 intel_ring_emit(ring, offset);
1675
1676                 intel_ring_emit(ring, MI_FLUSH);
1677                 intel_ring_emit(ring, MI_NOOP);
1678                 intel_ring_advance(ring);
1679
1680                 /* ... and execute it. */
1681                 offset = cs_offset;
1682         }
1683
1684         ret = intel_ring_begin(ring, 4);
1685         if (ret)
1686                 return ret;
1687
1688         intel_ring_emit(ring, MI_BATCH_BUFFER);
1689         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1690         intel_ring_emit(ring, offset + len - 8);
1691         intel_ring_emit(ring, MI_NOOP);
1692         intel_ring_advance(ring);
1693
1694         return 0;
1695 }
1696
1697 static int
1698 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1699                          u64 offset, u32 len,
1700                          unsigned flags)
1701 {
1702         int ret;
1703
1704         ret = intel_ring_begin(ring, 2);
1705         if (ret)
1706                 return ret;
1707
1708         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1709         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1710         intel_ring_advance(ring);
1711
1712         return 0;
1713 }
1714
1715 static void cleanup_status_page(struct intel_engine_cs *ring)
1716 {
1717         struct drm_i915_gem_object *obj;
1718
1719         obj = ring->status_page.obj;
1720         if (obj == NULL)
1721                 return;
1722
1723         kunmap(sg_page(obj->pages->sgl));
1724         i915_gem_object_ggtt_unpin(obj);
1725         drm_gem_object_unreference(&obj->base);
1726         ring->status_page.obj = NULL;
1727 }
1728
1729 static int init_status_page(struct intel_engine_cs *ring)
1730 {
1731         struct drm_i915_gem_object *obj;
1732
1733         if ((obj = ring->status_page.obj) == NULL) {
1734                 unsigned flags;
1735                 int ret;
1736
1737                 obj = i915_gem_alloc_object(ring->dev, 4096);
1738                 if (obj == NULL) {
1739                         DRM_ERROR("Failed to allocate status page\n");
1740                         return -ENOMEM;
1741                 }
1742
1743                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1744                 if (ret)
1745                         goto err_unref;
1746
1747                 flags = 0;
1748                 if (!HAS_LLC(ring->dev))
1749                         /* On g33, we cannot place HWS above 256MiB, so
1750                          * restrict its pinning to the low mappable arena.
1751                          * Though this restriction is not documented for
1752                          * gen4, gen5, or byt, they also behave similarly
1753                          * and hang if the HWS is placed at the top of the
1754                          * GTT. To generalise, it appears that all !llc
1755                          * platforms have issues with us placing the HWS
1756                          * above the mappable region (even though we never
1757                          * actualy map it).
1758                          */
1759                         flags |= PIN_MAPPABLE;
1760                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1761                 if (ret) {
1762 err_unref:
1763                         drm_gem_object_unreference(&obj->base);
1764                         return ret;
1765                 }
1766
1767                 ring->status_page.obj = obj;
1768         }
1769
1770         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1771         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1772         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1773
1774         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1775                         ring->name, ring->status_page.gfx_addr);
1776
1777         return 0;
1778 }
1779
1780 static int init_phys_status_page(struct intel_engine_cs *ring)
1781 {
1782         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1783
1784         if (!dev_priv->status_page_dmah) {
1785                 dev_priv->status_page_dmah =
1786                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1787                 if (!dev_priv->status_page_dmah)
1788                         return -ENOMEM;
1789         }
1790
1791         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1792         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1793
1794         return 0;
1795 }
1796
1797 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1798 {
1799         iounmap(ringbuf->virtual_start);
1800         ringbuf->virtual_start = NULL;
1801         i915_gem_object_ggtt_unpin(ringbuf->obj);
1802 }
1803
1804 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1805                                      struct intel_ringbuffer *ringbuf)
1806 {
1807         struct drm_i915_private *dev_priv = to_i915(dev);
1808         struct drm_i915_gem_object *obj = ringbuf->obj;
1809         int ret;
1810
1811         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1812         if (ret)
1813                 return ret;
1814
1815         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1816         if (ret) {
1817                 i915_gem_object_ggtt_unpin(obj);
1818                 return ret;
1819         }
1820
1821         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1822                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1823         if (ringbuf->virtual_start == NULL) {
1824                 i915_gem_object_ggtt_unpin(obj);
1825                 return -EINVAL;
1826         }
1827
1828         return 0;
1829 }
1830
1831 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1832 {
1833         drm_gem_object_unreference(&ringbuf->obj->base);
1834         ringbuf->obj = NULL;
1835 }
1836
1837 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1838                                struct intel_ringbuffer *ringbuf)
1839 {
1840         struct drm_i915_gem_object *obj;
1841
1842         obj = NULL;
1843         if (!HAS_LLC(dev))
1844                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1845         if (obj == NULL)
1846                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1847         if (obj == NULL)
1848                 return -ENOMEM;
1849
1850         /* mark ring buffers as read-only from GPU side by default */
1851         obj->gt_ro = 1;
1852
1853         ringbuf->obj = obj;
1854
1855         return 0;
1856 }
1857
1858 static int intel_init_ring_buffer(struct drm_device *dev,
1859                                   struct intel_engine_cs *ring)
1860 {
1861         struct intel_ringbuffer *ringbuf;
1862         int ret;
1863
1864         WARN_ON(ring->buffer);
1865
1866         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1867         if (!ringbuf)
1868                 return -ENOMEM;
1869         ring->buffer = ringbuf;
1870
1871         ring->dev = dev;
1872         INIT_LIST_HEAD(&ring->active_list);
1873         INIT_LIST_HEAD(&ring->request_list);
1874         INIT_LIST_HEAD(&ring->execlist_queue);
1875         ringbuf->size = 32 * PAGE_SIZE;
1876         ringbuf->ring = ring;
1877         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1878
1879         init_waitqueue_head(&ring->irq_queue);
1880
1881         if (I915_NEED_GFX_HWS(dev)) {
1882                 ret = init_status_page(ring);
1883                 if (ret)
1884                         goto error;
1885         } else {
1886                 BUG_ON(ring->id != RCS);
1887                 ret = init_phys_status_page(ring);
1888                 if (ret)
1889                         goto error;
1890         }
1891
1892         WARN_ON(ringbuf->obj);
1893
1894         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1895         if (ret) {
1896                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1897                                 ring->name, ret);
1898                 goto error;
1899         }
1900
1901         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1902         if (ret) {
1903                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1904                                 ring->name, ret);
1905                 intel_destroy_ringbuffer_obj(ringbuf);
1906                 goto error;
1907         }
1908
1909         /* Workaround an erratum on the i830 which causes a hang if
1910          * the TAIL pointer points to within the last 2 cachelines
1911          * of the buffer.
1912          */
1913         ringbuf->effective_size = ringbuf->size;
1914         if (IS_I830(dev) || IS_845G(dev))
1915                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1916
1917         ret = i915_cmd_parser_init_ring(ring);
1918         if (ret)
1919                 goto error;
1920
1921         return 0;
1922
1923 error:
1924         kfree(ringbuf);
1925         ring->buffer = NULL;
1926         return ret;
1927 }
1928
1929 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1930 {
1931         struct drm_i915_private *dev_priv;
1932         struct intel_ringbuffer *ringbuf;
1933
1934         if (!intel_ring_initialized(ring))
1935                 return;
1936
1937         dev_priv = to_i915(ring->dev);
1938         ringbuf = ring->buffer;
1939
1940         intel_stop_ring_buffer(ring);
1941         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1942
1943         intel_unpin_ringbuffer_obj(ringbuf);
1944         intel_destroy_ringbuffer_obj(ringbuf);
1945         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1946
1947         if (ring->cleanup)
1948                 ring->cleanup(ring);
1949
1950         cleanup_status_page(ring);
1951
1952         i915_cmd_parser_fini_ring(ring);
1953
1954         kfree(ringbuf);
1955         ring->buffer = NULL;
1956 }
1957
1958 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1959 {
1960         struct intel_ringbuffer *ringbuf = ring->buffer;
1961         struct drm_i915_gem_request *request;
1962         int ret;
1963
1964         if (intel_ring_space(ringbuf) >= n)
1965                 return 0;
1966
1967         list_for_each_entry(request, &ring->request_list, list) {
1968                 if (__intel_ring_space(request->postfix, ringbuf->tail,
1969                                        ringbuf->size) >= n) {
1970                         break;
1971                 }
1972         }
1973
1974         if (&request->list == &ring->request_list)
1975                 return -ENOSPC;
1976
1977         ret = i915_wait_request(request);
1978         if (ret)
1979                 return ret;
1980
1981         i915_gem_retire_requests_ring(ring);
1982
1983         return 0;
1984 }
1985
1986 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1987 {
1988         struct drm_device *dev = ring->dev;
1989         struct drm_i915_private *dev_priv = dev->dev_private;
1990         struct intel_ringbuffer *ringbuf = ring->buffer;
1991         unsigned long end;
1992         int ret;
1993
1994         ret = intel_ring_wait_request(ring, n);
1995         if (ret != -ENOSPC)
1996                 return ret;
1997
1998         /* force the tail write in case we have been skipping them */
1999         __intel_ring_advance(ring);
2000
2001         /* With GEM the hangcheck timer should kick us out of the loop,
2002          * leaving it early runs the risk of corrupting GEM state (due
2003          * to running on almost untested codepaths). But on resume
2004          * timers don't work yet, so prevent a complete hang in that
2005          * case by choosing an insanely large timeout. */
2006         end = jiffies + 60 * HZ;
2007
2008         ret = 0;
2009         trace_i915_ring_wait_begin(ring);
2010         do {
2011                 if (intel_ring_space(ringbuf) >= n)
2012                         break;
2013                 ringbuf->head = I915_READ_HEAD(ring);
2014                 if (intel_ring_space(ringbuf) >= n)
2015                         break;
2016
2017                 msleep(1);
2018
2019                 if (dev_priv->mm.interruptible && signal_pending(current)) {
2020                         ret = -ERESTARTSYS;
2021                         break;
2022                 }
2023
2024                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2025                                            dev_priv->mm.interruptible);
2026                 if (ret)
2027                         break;
2028
2029                 if (time_after(jiffies, end)) {
2030                         ret = -EBUSY;
2031                         break;
2032                 }
2033         } while (1);
2034         trace_i915_ring_wait_end(ring);
2035         return ret;
2036 }
2037
2038 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2039 {
2040         uint32_t __iomem *virt;
2041         struct intel_ringbuffer *ringbuf = ring->buffer;
2042         int rem = ringbuf->size - ringbuf->tail;
2043
2044         if (ringbuf->space < rem) {
2045                 int ret = ring_wait_for_space(ring, rem);
2046                 if (ret)
2047                         return ret;
2048         }
2049
2050         virt = ringbuf->virtual_start + ringbuf->tail;
2051         rem /= 4;
2052         while (rem--)
2053                 iowrite32(MI_NOOP, virt++);
2054
2055         ringbuf->tail = 0;
2056         intel_ring_update_space(ringbuf);
2057
2058         return 0;
2059 }
2060
2061 int intel_ring_idle(struct intel_engine_cs *ring)
2062 {
2063         struct drm_i915_gem_request *req;
2064         int ret;
2065
2066         /* We need to add any requests required to flush the objects and ring */
2067         if (ring->outstanding_lazy_request) {
2068                 ret = i915_add_request(ring);
2069                 if (ret)
2070                         return ret;
2071         }
2072
2073         /* Wait upon the last request to be completed */
2074         if (list_empty(&ring->request_list))
2075                 return 0;
2076
2077         req = list_entry(ring->request_list.prev,
2078                            struct drm_i915_gem_request,
2079                            list);
2080
2081         return i915_wait_request(req);
2082 }
2083
2084 static int
2085 intel_ring_alloc_request(struct intel_engine_cs *ring)
2086 {
2087         int ret;
2088         struct drm_i915_gem_request *request;
2089         struct drm_i915_private *dev_private = ring->dev->dev_private;
2090
2091         if (ring->outstanding_lazy_request)
2092                 return 0;
2093
2094         request = kzalloc(sizeof(*request), GFP_KERNEL);
2095         if (request == NULL)
2096                 return -ENOMEM;
2097
2098         kref_init(&request->ref);
2099         request->ring = ring;
2100         request->uniq = dev_private->request_uniq++;
2101
2102         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
2103         if (ret) {
2104                 kfree(request);
2105                 return ret;
2106         }
2107
2108         ring->outstanding_lazy_request = request;
2109         return 0;
2110 }
2111
2112 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2113                                 int bytes)
2114 {
2115         struct intel_ringbuffer *ringbuf = ring->buffer;
2116         int ret;
2117
2118         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2119                 ret = intel_wrap_ring_buffer(ring);
2120                 if (unlikely(ret))
2121                         return ret;
2122         }
2123
2124         if (unlikely(ringbuf->space < bytes)) {
2125                 ret = ring_wait_for_space(ring, bytes);
2126                 if (unlikely(ret))
2127                         return ret;
2128         }
2129
2130         return 0;
2131 }
2132
2133 int intel_ring_begin(struct intel_engine_cs *ring,
2134                      int num_dwords)
2135 {
2136         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2137         int ret;
2138
2139         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2140                                    dev_priv->mm.interruptible);
2141         if (ret)
2142                 return ret;
2143
2144         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2145         if (ret)
2146                 return ret;
2147
2148         /* Preallocate the olr before touching the ring */
2149         ret = intel_ring_alloc_request(ring);
2150         if (ret)
2151                 return ret;
2152
2153         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2154         return 0;
2155 }
2156
2157 /* Align the ring tail to a cacheline boundary */
2158 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2159 {
2160         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2161         int ret;
2162
2163         if (num_dwords == 0)
2164                 return 0;
2165
2166         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2167         ret = intel_ring_begin(ring, num_dwords);
2168         if (ret)
2169                 return ret;
2170
2171         while (num_dwords--)
2172                 intel_ring_emit(ring, MI_NOOP);
2173
2174         intel_ring_advance(ring);
2175
2176         return 0;
2177 }
2178
2179 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2180 {
2181         struct drm_device *dev = ring->dev;
2182         struct drm_i915_private *dev_priv = dev->dev_private;
2183
2184         BUG_ON(ring->outstanding_lazy_request);
2185
2186         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2187                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2188                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2189                 if (HAS_VEBOX(dev))
2190                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2191         }
2192
2193         ring->set_seqno(ring, seqno);
2194         ring->hangcheck.seqno = seqno;
2195 }
2196
2197 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2198                                      u32 value)
2199 {
2200         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2201
2202        /* Every tail move must follow the sequence below */
2203
2204         /* Disable notification that the ring is IDLE. The GT
2205          * will then assume that it is busy and bring it out of rc6.
2206          */
2207         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2208                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2209
2210         /* Clear the context id. Here be magic! */
2211         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2212
2213         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2214         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2215                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2216                      50))
2217                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2218
2219         /* Now that the ring is fully powered up, update the tail */
2220         I915_WRITE_TAIL(ring, value);
2221         POSTING_READ(RING_TAIL(ring->mmio_base));
2222
2223         /* Let the ring send IDLE messages to the GT again,
2224          * and so let it sleep to conserve power when idle.
2225          */
2226         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2227                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2228 }
2229
2230 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2231                                u32 invalidate, u32 flush)
2232 {
2233         uint32_t cmd;
2234         int ret;
2235
2236         ret = intel_ring_begin(ring, 4);
2237         if (ret)
2238                 return ret;
2239
2240         cmd = MI_FLUSH_DW;
2241         if (INTEL_INFO(ring->dev)->gen >= 8)
2242                 cmd += 1;
2243
2244         /* We always require a command barrier so that subsequent
2245          * commands, such as breadcrumb interrupts, are strictly ordered
2246          * wrt the contents of the write cache being flushed to memory
2247          * (and thus being coherent from the CPU).
2248          */
2249         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2250
2251         /*
2252          * Bspec vol 1c.5 - video engine command streamer:
2253          * "If ENABLED, all TLBs will be invalidated once the flush
2254          * operation is complete. This bit is only valid when the
2255          * Post-Sync Operation field is a value of 1h or 3h."
2256          */
2257         if (invalidate & I915_GEM_GPU_DOMAINS)
2258                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2259
2260         intel_ring_emit(ring, cmd);
2261         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2262         if (INTEL_INFO(ring->dev)->gen >= 8) {
2263                 intel_ring_emit(ring, 0); /* upper addr */
2264                 intel_ring_emit(ring, 0); /* value */
2265         } else  {
2266                 intel_ring_emit(ring, 0);
2267                 intel_ring_emit(ring, MI_NOOP);
2268         }
2269         intel_ring_advance(ring);
2270         return 0;
2271 }
2272
2273 static int
2274 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2275                               u64 offset, u32 len,
2276                               unsigned flags)
2277 {
2278         bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2279         int ret;
2280
2281         ret = intel_ring_begin(ring, 4);
2282         if (ret)
2283                 return ret;
2284
2285         /* FIXME(BDW): Address space and security selectors. */
2286         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2287         intel_ring_emit(ring, lower_32_bits(offset));
2288         intel_ring_emit(ring, upper_32_bits(offset));
2289         intel_ring_emit(ring, MI_NOOP);
2290         intel_ring_advance(ring);
2291
2292         return 0;
2293 }
2294
2295 static int
2296 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2297                               u64 offset, u32 len,
2298                               unsigned flags)
2299 {
2300         int ret;
2301
2302         ret = intel_ring_begin(ring, 2);
2303         if (ret)
2304                 return ret;
2305
2306         intel_ring_emit(ring,
2307                         MI_BATCH_BUFFER_START |
2308                         (flags & I915_DISPATCH_SECURE ?
2309                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2310         /* bit0-7 is the length on GEN6+ */
2311         intel_ring_emit(ring, offset);
2312         intel_ring_advance(ring);
2313
2314         return 0;
2315 }
2316
2317 static int
2318 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2319                               u64 offset, u32 len,
2320                               unsigned flags)
2321 {
2322         int ret;
2323
2324         ret = intel_ring_begin(ring, 2);
2325         if (ret)
2326                 return ret;
2327
2328         intel_ring_emit(ring,
2329                         MI_BATCH_BUFFER_START |
2330                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2331         /* bit0-7 is the length on GEN6+ */
2332         intel_ring_emit(ring, offset);
2333         intel_ring_advance(ring);
2334
2335         return 0;
2336 }
2337
2338 /* Blitter support (SandyBridge+) */
2339
2340 static int gen6_ring_flush(struct intel_engine_cs *ring,
2341                            u32 invalidate, u32 flush)
2342 {
2343         struct drm_device *dev = ring->dev;
2344         struct drm_i915_private *dev_priv = dev->dev_private;
2345         uint32_t cmd;
2346         int ret;
2347
2348         ret = intel_ring_begin(ring, 4);
2349         if (ret)
2350                 return ret;
2351
2352         cmd = MI_FLUSH_DW;
2353         if (INTEL_INFO(ring->dev)->gen >= 8)
2354                 cmd += 1;
2355
2356         /* We always require a command barrier so that subsequent
2357          * commands, such as breadcrumb interrupts, are strictly ordered
2358          * wrt the contents of the write cache being flushed to memory
2359          * (and thus being coherent from the CPU).
2360          */
2361         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2362
2363         /*
2364          * Bspec vol 1c.3 - blitter engine command streamer:
2365          * "If ENABLED, all TLBs will be invalidated once the flush
2366          * operation is complete. This bit is only valid when the
2367          * Post-Sync Operation field is a value of 1h or 3h."
2368          */
2369         if (invalidate & I915_GEM_DOMAIN_RENDER)
2370                 cmd |= MI_INVALIDATE_TLB;
2371         intel_ring_emit(ring, cmd);
2372         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2373         if (INTEL_INFO(ring->dev)->gen >= 8) {
2374                 intel_ring_emit(ring, 0); /* upper addr */
2375                 intel_ring_emit(ring, 0); /* value */
2376         } else  {
2377                 intel_ring_emit(ring, 0);
2378                 intel_ring_emit(ring, MI_NOOP);
2379         }
2380         intel_ring_advance(ring);
2381
2382         if (!invalidate && flush) {
2383                 if (IS_GEN7(dev))
2384                         return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2385                 else if (IS_BROADWELL(dev))
2386                         dev_priv->fbc.need_sw_cache_clean = true;
2387         }
2388
2389         return 0;
2390 }
2391
2392 int intel_init_render_ring_buffer(struct drm_device *dev)
2393 {
2394         struct drm_i915_private *dev_priv = dev->dev_private;
2395         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2396         struct drm_i915_gem_object *obj;
2397         int ret;
2398
2399         ring->name = "render ring";
2400         ring->id = RCS;
2401         ring->mmio_base = RENDER_RING_BASE;
2402
2403         if (INTEL_INFO(dev)->gen >= 8) {
2404                 if (i915_semaphore_is_enabled(dev)) {
2405                         obj = i915_gem_alloc_object(dev, 4096);
2406                         if (obj == NULL) {
2407                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2408                                 i915.semaphores = 0;
2409                         } else {
2410                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2411                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2412                                 if (ret != 0) {
2413                                         drm_gem_object_unreference(&obj->base);
2414                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2415                                         i915.semaphores = 0;
2416                                 } else
2417                                         dev_priv->semaphore_obj = obj;
2418                         }
2419                 }
2420
2421                 ring->init_context = intel_rcs_ctx_init;
2422                 ring->add_request = gen6_add_request;
2423                 ring->flush = gen8_render_ring_flush;
2424                 ring->irq_get = gen8_ring_get_irq;
2425                 ring->irq_put = gen8_ring_put_irq;
2426                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2427                 ring->get_seqno = gen6_ring_get_seqno;
2428                 ring->set_seqno = ring_set_seqno;
2429                 if (i915_semaphore_is_enabled(dev)) {
2430                         WARN_ON(!dev_priv->semaphore_obj);
2431                         ring->semaphore.sync_to = gen8_ring_sync;
2432                         ring->semaphore.signal = gen8_rcs_signal;
2433                         GEN8_RING_SEMAPHORE_INIT;
2434                 }
2435         } else if (INTEL_INFO(dev)->gen >= 6) {
2436                 ring->add_request = gen6_add_request;
2437                 ring->flush = gen7_render_ring_flush;
2438                 if (INTEL_INFO(dev)->gen == 6)
2439                         ring->flush = gen6_render_ring_flush;
2440                 ring->irq_get = gen6_ring_get_irq;
2441                 ring->irq_put = gen6_ring_put_irq;
2442                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2443                 ring->get_seqno = gen6_ring_get_seqno;
2444                 ring->set_seqno = ring_set_seqno;
2445                 if (i915_semaphore_is_enabled(dev)) {
2446                         ring->semaphore.sync_to = gen6_ring_sync;
2447                         ring->semaphore.signal = gen6_signal;
2448                         /*
2449                          * The current semaphore is only applied on pre-gen8
2450                          * platform.  And there is no VCS2 ring on the pre-gen8
2451                          * platform. So the semaphore between RCS and VCS2 is
2452                          * initialized as INVALID.  Gen8 will initialize the
2453                          * sema between VCS2 and RCS later.
2454                          */
2455                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2456                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2457                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2458                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2459                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2460                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2461                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2462                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2463                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2464                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2465                 }
2466         } else if (IS_GEN5(dev)) {
2467                 ring->add_request = pc_render_add_request;
2468                 ring->flush = gen4_render_ring_flush;
2469                 ring->get_seqno = pc_render_get_seqno;
2470                 ring->set_seqno = pc_render_set_seqno;
2471                 ring->irq_get = gen5_ring_get_irq;
2472                 ring->irq_put = gen5_ring_put_irq;
2473                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2474                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2475         } else {
2476                 ring->add_request = i9xx_add_request;
2477                 if (INTEL_INFO(dev)->gen < 4)
2478                         ring->flush = gen2_render_ring_flush;
2479                 else
2480                         ring->flush = gen4_render_ring_flush;
2481                 ring->get_seqno = ring_get_seqno;
2482                 ring->set_seqno = ring_set_seqno;
2483                 if (IS_GEN2(dev)) {
2484                         ring->irq_get = i8xx_ring_get_irq;
2485                         ring->irq_put = i8xx_ring_put_irq;
2486                 } else {
2487                         ring->irq_get = i9xx_ring_get_irq;
2488                         ring->irq_put = i9xx_ring_put_irq;
2489                 }
2490                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2491         }
2492         ring->write_tail = ring_write_tail;
2493
2494         if (IS_HASWELL(dev))
2495                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2496         else if (IS_GEN8(dev))
2497                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2498         else if (INTEL_INFO(dev)->gen >= 6)
2499                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2500         else if (INTEL_INFO(dev)->gen >= 4)
2501                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2502         else if (IS_I830(dev) || IS_845G(dev))
2503                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2504         else
2505                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2506         ring->init_hw = init_render_ring;
2507         ring->cleanup = render_ring_cleanup;
2508
2509         /* Workaround batchbuffer to combat CS tlb bug. */
2510         if (HAS_BROKEN_CS_TLB(dev)) {
2511                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2512                 if (obj == NULL) {
2513                         DRM_ERROR("Failed to allocate batch bo\n");
2514                         return -ENOMEM;
2515                 }
2516
2517                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2518                 if (ret != 0) {
2519                         drm_gem_object_unreference(&obj->base);
2520                         DRM_ERROR("Failed to ping batch bo\n");
2521                         return ret;
2522                 }
2523
2524                 ring->scratch.obj = obj;
2525                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2526         }
2527
2528         ret = intel_init_ring_buffer(dev, ring);
2529         if (ret)
2530                 return ret;
2531
2532         if (INTEL_INFO(dev)->gen >= 5) {
2533                 ret = intel_init_pipe_control(ring);
2534                 if (ret)
2535                         return ret;
2536         }
2537
2538         return 0;
2539 }
2540
2541 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2542 {
2543         struct drm_i915_private *dev_priv = dev->dev_private;
2544         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2545
2546         ring->name = "bsd ring";
2547         ring->id = VCS;
2548
2549         ring->write_tail = ring_write_tail;
2550         if (INTEL_INFO(dev)->gen >= 6) {
2551                 ring->mmio_base = GEN6_BSD_RING_BASE;
2552                 /* gen6 bsd needs a special wa for tail updates */
2553                 if (IS_GEN6(dev))
2554                         ring->write_tail = gen6_bsd_ring_write_tail;
2555                 ring->flush = gen6_bsd_ring_flush;
2556                 ring->add_request = gen6_add_request;
2557                 ring->get_seqno = gen6_ring_get_seqno;
2558                 ring->set_seqno = ring_set_seqno;
2559                 if (INTEL_INFO(dev)->gen >= 8) {
2560                         ring->irq_enable_mask =
2561                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2562                         ring->irq_get = gen8_ring_get_irq;
2563                         ring->irq_put = gen8_ring_put_irq;
2564                         ring->dispatch_execbuffer =
2565                                 gen8_ring_dispatch_execbuffer;
2566                         if (i915_semaphore_is_enabled(dev)) {
2567                                 ring->semaphore.sync_to = gen8_ring_sync;
2568                                 ring->semaphore.signal = gen8_xcs_signal;
2569                                 GEN8_RING_SEMAPHORE_INIT;
2570                         }
2571                 } else {
2572                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2573                         ring->irq_get = gen6_ring_get_irq;
2574                         ring->irq_put = gen6_ring_put_irq;
2575                         ring->dispatch_execbuffer =
2576                                 gen6_ring_dispatch_execbuffer;
2577                         if (i915_semaphore_is_enabled(dev)) {
2578                                 ring->semaphore.sync_to = gen6_ring_sync;
2579                                 ring->semaphore.signal = gen6_signal;
2580                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2581                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2582                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2583                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2584                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2585                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2586                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2587                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2588                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2589                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2590                         }
2591                 }
2592         } else {
2593                 ring->mmio_base = BSD_RING_BASE;
2594                 ring->flush = bsd_ring_flush;
2595                 ring->add_request = i9xx_add_request;
2596                 ring->get_seqno = ring_get_seqno;
2597                 ring->set_seqno = ring_set_seqno;
2598                 if (IS_GEN5(dev)) {
2599                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2600                         ring->irq_get = gen5_ring_get_irq;
2601                         ring->irq_put = gen5_ring_put_irq;
2602                 } else {
2603                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2604                         ring->irq_get = i9xx_ring_get_irq;
2605                         ring->irq_put = i9xx_ring_put_irq;
2606                 }
2607                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2608         }
2609         ring->init_hw = init_ring_common;
2610
2611         return intel_init_ring_buffer(dev, ring);
2612 }
2613
2614 /**
2615  * Initialize the second BSD ring for Broadwell GT3.
2616  * It is noted that this only exists on Broadwell GT3.
2617  */
2618 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2619 {
2620         struct drm_i915_private *dev_priv = dev->dev_private;
2621         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2622
2623         if ((INTEL_INFO(dev)->gen != 8)) {
2624                 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2625                 return -EINVAL;
2626         }
2627
2628         ring->name = "bsd2 ring";
2629         ring->id = VCS2;
2630
2631         ring->write_tail = ring_write_tail;
2632         ring->mmio_base = GEN8_BSD2_RING_BASE;
2633         ring->flush = gen6_bsd_ring_flush;
2634         ring->add_request = gen6_add_request;
2635         ring->get_seqno = gen6_ring_get_seqno;
2636         ring->set_seqno = ring_set_seqno;
2637         ring->irq_enable_mask =
2638                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2639         ring->irq_get = gen8_ring_get_irq;
2640         ring->irq_put = gen8_ring_put_irq;
2641         ring->dispatch_execbuffer =
2642                         gen8_ring_dispatch_execbuffer;
2643         if (i915_semaphore_is_enabled(dev)) {
2644                 ring->semaphore.sync_to = gen8_ring_sync;
2645                 ring->semaphore.signal = gen8_xcs_signal;
2646                 GEN8_RING_SEMAPHORE_INIT;
2647         }
2648         ring->init_hw = init_ring_common;
2649
2650         return intel_init_ring_buffer(dev, ring);
2651 }
2652
2653 int intel_init_blt_ring_buffer(struct drm_device *dev)
2654 {
2655         struct drm_i915_private *dev_priv = dev->dev_private;
2656         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2657
2658         ring->name = "blitter ring";
2659         ring->id = BCS;
2660
2661         ring->mmio_base = BLT_RING_BASE;
2662         ring->write_tail = ring_write_tail;
2663         ring->flush = gen6_ring_flush;
2664         ring->add_request = gen6_add_request;
2665         ring->get_seqno = gen6_ring_get_seqno;
2666         ring->set_seqno = ring_set_seqno;
2667         if (INTEL_INFO(dev)->gen >= 8) {
2668                 ring->irq_enable_mask =
2669                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2670                 ring->irq_get = gen8_ring_get_irq;
2671                 ring->irq_put = gen8_ring_put_irq;
2672                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2673                 if (i915_semaphore_is_enabled(dev)) {
2674                         ring->semaphore.sync_to = gen8_ring_sync;
2675                         ring->semaphore.signal = gen8_xcs_signal;
2676                         GEN8_RING_SEMAPHORE_INIT;
2677                 }
2678         } else {
2679                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2680                 ring->irq_get = gen6_ring_get_irq;
2681                 ring->irq_put = gen6_ring_put_irq;
2682                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2683                 if (i915_semaphore_is_enabled(dev)) {
2684                         ring->semaphore.signal = gen6_signal;
2685                         ring->semaphore.sync_to = gen6_ring_sync;
2686                         /*
2687                          * The current semaphore is only applied on pre-gen8
2688                          * platform.  And there is no VCS2 ring on the pre-gen8
2689                          * platform. So the semaphore between BCS and VCS2 is
2690                          * initialized as INVALID.  Gen8 will initialize the
2691                          * sema between BCS and VCS2 later.
2692                          */
2693                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2694                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2695                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2696                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2697                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2698                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2699                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2700                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2701                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2702                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2703                 }
2704         }
2705         ring->init_hw = init_ring_common;
2706
2707         return intel_init_ring_buffer(dev, ring);
2708 }
2709
2710 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2711 {
2712         struct drm_i915_private *dev_priv = dev->dev_private;
2713         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2714
2715         ring->name = "video enhancement ring";
2716         ring->id = VECS;
2717
2718         ring->mmio_base = VEBOX_RING_BASE;
2719         ring->write_tail = ring_write_tail;
2720         ring->flush = gen6_ring_flush;
2721         ring->add_request = gen6_add_request;
2722         ring->get_seqno = gen6_ring_get_seqno;
2723         ring->set_seqno = ring_set_seqno;
2724
2725         if (INTEL_INFO(dev)->gen >= 8) {
2726                 ring->irq_enable_mask =
2727                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2728                 ring->irq_get = gen8_ring_get_irq;
2729                 ring->irq_put = gen8_ring_put_irq;
2730                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2731                 if (i915_semaphore_is_enabled(dev)) {
2732                         ring->semaphore.sync_to = gen8_ring_sync;
2733                         ring->semaphore.signal = gen8_xcs_signal;
2734                         GEN8_RING_SEMAPHORE_INIT;
2735                 }
2736         } else {
2737                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2738                 ring->irq_get = hsw_vebox_get_irq;
2739                 ring->irq_put = hsw_vebox_put_irq;
2740                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2741                 if (i915_semaphore_is_enabled(dev)) {
2742                         ring->semaphore.sync_to = gen6_ring_sync;
2743                         ring->semaphore.signal = gen6_signal;
2744                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2745                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2746                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2747                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2748                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2749                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2750                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2751                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2752                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2753                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2754                 }
2755         }
2756         ring->init_hw = init_ring_common;
2757
2758         return intel_init_ring_buffer(dev, ring);
2759 }
2760
2761 int
2762 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2763 {
2764         int ret;
2765
2766         if (!ring->gpu_caches_dirty)
2767                 return 0;
2768
2769         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2770         if (ret)
2771                 return ret;
2772
2773         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2774
2775         ring->gpu_caches_dirty = false;
2776         return 0;
2777 }
2778
2779 int
2780 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2781 {
2782         uint32_t flush_domains;
2783         int ret;
2784
2785         flush_domains = 0;
2786         if (ring->gpu_caches_dirty)
2787                 flush_domains = I915_GEM_GPU_DOMAINS;
2788
2789         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2790         if (ret)
2791                 return ret;
2792
2793         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2794
2795         ring->gpu_caches_dirty = false;
2796         return 0;
2797 }
2798
2799 void
2800 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2801 {
2802         int ret;
2803
2804         if (!intel_ring_initialized(ring))
2805                 return;
2806
2807         ret = intel_ring_idle(ring);
2808         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2809                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2810                           ring->name, ret);
2811
2812         stop_ring(ring);
2813 }