drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 const char *
  69 intel_display_power_domain_str(enum intel_display_power_domain domain)
  70 {
  71         switch (domain) {
  72         case POWER_DOMAIN_PIPE_A:
  73                 return "PIPE_A";
  74         case POWER_DOMAIN_PIPE_B:
  75                 return "PIPE_B";
  76         case POWER_DOMAIN_PIPE_C:
  77                 return "PIPE_C";
  78         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  79                 return "PIPE_A_PANEL_FITTER";
  80         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  81                 return "PIPE_B_PANEL_FITTER";
  82         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  83                 return "PIPE_C_PANEL_FITTER";
  84         case POWER_DOMAIN_TRANSCODER_A:
  85                 return "TRANSCODER_A";
  86         case POWER_DOMAIN_TRANSCODER_B:
  87                 return "TRANSCODER_B";
  88         case POWER_DOMAIN_TRANSCODER_C:
  89                 return "TRANSCODER_C";
  90         case POWER_DOMAIN_TRANSCODER_EDP:
  91                 return "TRANSCODER_EDP";
  92         case POWER_DOMAIN_TRANSCODER_DSI_A:
  93                 return "TRANSCODER_DSI_A";
  94         case POWER_DOMAIN_TRANSCODER_DSI_C:
  95                 return "TRANSCODER_DSI_C";
  96         case POWER_DOMAIN_PORT_DDI_A_LANES:
  97                 return "PORT_DDI_A_LANES";
  98         case POWER_DOMAIN_PORT_DDI_B_LANES:
  99                 return "PORT_DDI_B_LANES";
 100         case POWER_DOMAIN_PORT_DDI_C_LANES:
 101                 return "PORT_DDI_C_LANES";
 102         case POWER_DOMAIN_PORT_DDI_D_LANES:
 103                 return "PORT_DDI_D_LANES";
 104         case POWER_DOMAIN_PORT_DDI_E_LANES:
 105                 return "PORT_DDI_E_LANES";
 106         case POWER_DOMAIN_PORT_DSI:
 107                 return "PORT_DSI";
 108         case POWER_DOMAIN_PORT_CRT:
 109                 return "PORT_CRT";
 110         case POWER_DOMAIN_PORT_OTHER:
 111                 return "PORT_OTHER";
 112         case POWER_DOMAIN_VGA:
 113                 return "VGA";
 114         case POWER_DOMAIN_AUDIO:
 115                 return "AUDIO";
 116         case POWER_DOMAIN_PLLS:
 117                 return "PLLS";
 118         case POWER_DOMAIN_AUX_A:
 119                 return "AUX_A";
 120         case POWER_DOMAIN_AUX_B:
 121                 return "AUX_B";
 122         case POWER_DOMAIN_AUX_C:
 123                 return "AUX_C";
 124         case POWER_DOMAIN_AUX_D:
 125                 return "AUX_D";
 126         case POWER_DOMAIN_GMBUS:
 127                 return "GMBUS";
 128         case POWER_DOMAIN_INIT:
 129                 return "INIT";
 130         case POWER_DOMAIN_MODESET:
 131                 return "MODESET";
 132         default:
 133                 MISSING_CASE(domain);
 134                 return "?";
 135         }
 136 }
 137
 138 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 139                                     struct i915_power_well *power_well)
 140 {
 141         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 142         power_well->ops->enable(dev_priv, power_well);
 143         power_well->hw_enabled = true;
 144 }
 145
 146 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 147                                      struct i915_power_well *power_well)
 148 {
 149         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 150         power_well->hw_enabled = false;
 151         power_well->ops->disable(dev_priv, power_well);
 152 }
 153
 154 /*
 155  * We should only use the power well if we explicitly asked the hardware to
 156  * enable it, so check if it's enabled and also check if we've requested it to
 157  * be enabled.
 158  */
 159 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 160                                    struct i915_power_well *power_well)
 161 {
 162         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 163                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 164 }
 165
 166 /**
 167  * __intel_display_power_is_enabled - unlocked check for a power domain
 168  * @dev_priv: i915 device instance
 169  * @domain: power domain to check
 170  *
 171  * This is the unlocked version of intel_display_power_is_enabled() and should
 172  * only be used from error capture and recovery code where deadlocks are
 173  * possible.
 174  *
 175  * Returns:
 176  * True when the power domain is enabled, false otherwise.
 177  */
 178 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 179                                       enum intel_display_power_domain domain)
 180 {
 181         struct i915_power_domains *power_domains;
 182         struct i915_power_well *power_well;
 183         bool is_enabled;
 184         int i;
 185
 186         if (dev_priv->pm.suspended)
 187                 return false;
 188
 189         power_domains = &dev_priv->power_domains;
 190
 191         is_enabled = true;
 192
 193         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 194                 if (power_well->always_on)
 195                         continue;
 196
 197                 if (!power_well->hw_enabled) {
 198                         is_enabled = false;
 199                         break;
 200                 }
 201         }
 202
 203         return is_enabled;
 204 }
 205
 206 /**
 207  * intel_display_power_is_enabled - check for a power domain
 208  * @dev_priv: i915 device instance
 209  * @domain: power domain to check
 210  *
 211  * This function can be used to check the hw power domain state. It is mostly
 212  * used in hardware state readout functions. Everywhere else code should rely
 213  * upon explicit power domain reference counting to ensure that the hardware
 214  * block is powered up before accessing it.
 215  *
 216  * Callers must hold the relevant modesetting locks to ensure that concurrent
 217  * threads can't disable the power well while the caller tries to read a few
 218  * registers.
 219  *
 220  * Returns:
 221  * True when the power domain is enabled, false otherwise.
 222  */
 223 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 224                                     enum intel_display_power_domain domain)
 225 {
 226         struct i915_power_domains *power_domains;
 227         bool ret;
 228
 229         power_domains = &dev_priv->power_domains;
 230
 231         mutex_lock(&power_domains->lock);
 232         ret = __intel_display_power_is_enabled(dev_priv, domain);
 233         mutex_unlock(&power_domains->lock);
 234
 235         return ret;
 236 }
 237
 238 /**
 239  * intel_display_set_init_power - set the initial power domain state
 240  * @dev_priv: i915 device instance
 241  * @enable: whether to enable or disable the initial power domain state
 242  *
 243  * For simplicity our driver load/unload and system suspend/resume code assumes
 244  * that all power domains are always enabled. This functions controls the state
 245  * of this little hack. While the initial power domain state is enabled runtime
 246  * pm is effectively disabled.
 247  */
 248 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 249                                   bool enable)
 250 {
 251         if (dev_priv->power_domains.init_power_on == enable)
 252                 return;
 253
 254         if (enable)
 255                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 256         else
 257                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 258
 259         dev_priv->power_domains.init_power_on = enable;
 260 }
 261
 262 /*
 263  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 264  * when not needed anymore. We have 4 registers that can request the power well
 265  * to be enabled, and it will only be disabled if none of the registers is
 266  * requesting it to be enabled.
 267  */
 268 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 269 {
 270         struct drm_device *dev = dev_priv->dev;
 271
 272         /*
 273          * After we re-enable the power well, if we touch VGA register 0x3d5
 274          * we'll get unclaimed register interrupts. This stops after we write
 275          * anything to the VGA MSR register. The vgacon module uses this
 276          * register all the time, so if we unbind our driver and, as a
 277          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 278          * console_unlock(). So make here we touch the VGA MSR register, making
 279          * sure vgacon can keep working normally without triggering interrupts
 280          * and error messages.
 281          */
 282         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 283         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 284         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 285
 286         if (IS_BROADWELL(dev))
 287                 gen8_irq_power_well_post_enable(dev_priv,
 288                                                 1 << PIPE_C | 1 << PIPE_B);
 289 }
 290
 291 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 292 {
 293         if (IS_BROADWELL(dev_priv))
 294                 gen8_irq_power_well_pre_disable(dev_priv,
 295                                                 1 << PIPE_C | 1 << PIPE_B);
 296 }
 297
 298 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 299                                        struct i915_power_well *power_well)
 300 {
 301         struct drm_device *dev = dev_priv->dev;
 302
 303         /*
 304          * After we re-enable the power well, if we touch VGA register 0x3d5
 305          * we'll get unclaimed register interrupts. This stops after we write
 306          * anything to the VGA MSR register. The vgacon module uses this
 307          * register all the time, so if we unbind our driver and, as a
 308          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 309          * console_unlock(). So make here we touch the VGA MSR register, making
 310          * sure vgacon can keep working normally without triggering interrupts
 311          * and error messages.
 312          */
 313         if (power_well->data == SKL_DISP_PW_2) {
 314                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 315                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 316                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 317
 318                 gen8_irq_power_well_post_enable(dev_priv,
 319                                                 1 << PIPE_C | 1 << PIPE_B);
 320         }
 321 }
 322
 323 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 324                                        struct i915_power_well *power_well)
 325 {
 326         if (power_well->data == SKL_DISP_PW_2)
 327                 gen8_irq_power_well_pre_disable(dev_priv,
 328                                                 1 << PIPE_C | 1 << PIPE_B);
 329 }
 330
 331 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 332                                struct i915_power_well *power_well, bool enable)
 333 {
 334         bool is_enabled, enable_requested;
 335         uint32_t tmp;
 336
 337         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 338         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 339         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 340
 341         if (enable) {
 342                 if (!enable_requested)
 343                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 344                                    HSW_PWR_WELL_ENABLE_REQUEST);
 345
 346                 if (!is_enabled) {
 347                         DRM_DEBUG_KMS("Enabling power well\n");
 348                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 349                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 350                                 DRM_ERROR("Timeout enabling power well\n");
 351                         hsw_power_well_post_enable(dev_priv);
 352                 }
 353
 354         } else {
 355                 if (enable_requested) {
 356                         hsw_power_well_pre_disable(dev_priv);
 357                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 358                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 359                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 360                 }
 361         }
 362 }
 363
 364 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 365         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 366         BIT(POWER_DOMAIN_PIPE_B) |                      \
 367         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 368         BIT(POWER_DOMAIN_PIPE_C) |                      \
 369         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 370         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 371         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 372         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 373         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 374         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 375         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 376         BIT(POWER_DOMAIN_AUX_B) |                       \
 377         BIT(POWER_DOMAIN_AUX_C) |                       \
 378         BIT(POWER_DOMAIN_AUX_D) |                       \
 379         BIT(POWER_DOMAIN_AUDIO) |                       \
 380         BIT(POWER_DOMAIN_VGA) |                         \
 381         BIT(POWER_DOMAIN_INIT))
 382 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 383         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 384         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 385         BIT(POWER_DOMAIN_INIT))
 386 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 387         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 388         BIT(POWER_DOMAIN_INIT))
 389 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 390         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 391         BIT(POWER_DOMAIN_INIT))
 392 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 393         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 394         BIT(POWER_DOMAIN_INIT))
 395 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 396         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 397         BIT(POWER_DOMAIN_MODESET) |                     \
 398         BIT(POWER_DOMAIN_AUX_A) |                       \
 399         BIT(POWER_DOMAIN_INIT))
 400
 401 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 402         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 403         BIT(POWER_DOMAIN_PIPE_B) |                      \
 404         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 405         BIT(POWER_DOMAIN_PIPE_C) |                      \
 406         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 407         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 408         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 409         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 410         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 411         BIT(POWER_DOMAIN_AUX_B) |                       \
 412         BIT(POWER_DOMAIN_AUX_C) |                       \
 413         BIT(POWER_DOMAIN_AUDIO) |                       \
 414         BIT(POWER_DOMAIN_VGA) |                         \
 415         BIT(POWER_DOMAIN_GMBUS) |                       \
 416         BIT(POWER_DOMAIN_INIT))
 417 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 418         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 419         BIT(POWER_DOMAIN_MODESET) |                     \
 420         BIT(POWER_DOMAIN_AUX_A) |                       \
 421         BIT(POWER_DOMAIN_INIT))
 422
 423 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 424 {
 425         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 426                   "DC9 already programmed to be enabled.\n");
 427         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 428                   "DC5 still not disabled to enable DC9.\n");
 429         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 430         WARN_ONCE(intel_irqs_enabled(dev_priv),
 431                   "Interrupts not disabled yet.\n");
 432
 433          /*
 434           * TODO: check for the following to verify the conditions to enter DC9
 435           * state are satisfied:
 436           * 1] Check relevant display engine registers to verify if mode set
 437           * disable sequence was followed.
 438           * 2] Check if display uninitialize sequence is initialized.
 439           */
 440 }
 441
 442 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 443 {
 444         WARN_ONCE(intel_irqs_enabled(dev_priv),
 445                   "Interrupts not disabled yet.\n");
 446         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 447                   "DC5 still not disabled.\n");
 448
 449          /*
 450           * TODO: check for the following to verify DC9 state was indeed
 451           * entered before programming to disable it:
 452           * 1] Check relevant display engine registers to verify if mode
 453           *  set disable sequence was followed.
 454           * 2] Check if display uninitialize sequence is initialized.
 455           */
 456 }
 457
 458 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 459                                 u32 state)
 460 {
 461         int rewrites = 0;
 462         int rereads = 0;
 463         u32 v;
 464
 465         I915_WRITE(DC_STATE_EN, state);
 466
 467         /* It has been observed that disabling the dc6 state sometimes
 468          * doesn't stick and dmc keeps returning old value. Make sure
 469          * the write really sticks enough times and also force rewrite until
 470          * we are confident that state is exactly what we want.
 471          */
 472         do  {
 473                 v = I915_READ(DC_STATE_EN);
 474
 475                 if (v != state) {
 476                         I915_WRITE(DC_STATE_EN, state);
 477                         rewrites++;
 478                         rereads = 0;
 479                 } else if (rereads++ > 5) {
 480                         break;
 481                 }
 482
 483         } while (rewrites < 100);
 484
 485         if (v != state)
 486                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 487                           state, v);
 488
 489         /* Most of the times we need one retry, avoid spam */
 490         if (rewrites > 1)
 491                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 492                               state, rewrites);
 493 }
 494
 495 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 496 {
 497         u32 mask;
 498
 499         mask = DC_STATE_EN_UPTO_DC5;
 500         if (IS_BROXTON(dev_priv))
 501                 mask |= DC_STATE_EN_DC9;
 502         else
 503                 mask |= DC_STATE_EN_UPTO_DC6;
 504
 505         return mask;
 506 }
 507
 508 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 509 {
 510         u32 val;
 511
 512         val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
 513
 514         DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
 515                       dev_priv->csr.dc_state, val);
 516         dev_priv->csr.dc_state = val;
 517 }
 518
 519 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 520 {
 521         uint32_t val;
 522         uint32_t mask;
 523
 524         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 525                 state &= dev_priv->csr.allowed_dc_mask;
 526
 527         val = I915_READ(DC_STATE_EN);
 528         mask = gen9_dc_mask(dev_priv);
 529         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 530                       val & mask, state);
 531
 532         /* Check if DMC is ignoring our DC state requests */
 533         if ((val & mask) != dev_priv->csr.dc_state)
 534                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 535                           dev_priv->csr.dc_state, val & mask);
 536
 537         val &= ~mask;
 538         val |= state;
 539
 540         gen9_write_dc_state(dev_priv, val);
 541
 542         dev_priv->csr.dc_state = val & mask;
 543 }
 544
 545 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 546 {
 547         assert_can_enable_dc9(dev_priv);
 548
 549         DRM_DEBUG_KMS("Enabling DC9\n");
 550
 551         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 552 }
 553
 554 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 555 {
 556         assert_can_disable_dc9(dev_priv);
 557
 558         DRM_DEBUG_KMS("Disabling DC9\n");
 559
 560         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 561 }
 562
 563 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 564 {
 565         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 566                   "CSR program storage start is NULL\n");
 567         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 568         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 569 }
 570
 571 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 572 {
 573         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 574                                         SKL_DISP_PW_2);
 575
 576         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 577
 578         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 579                   "DC5 already programmed to be enabled.\n");
 580         assert_rpm_wakelock_held(dev_priv);
 581
 582         assert_csr_loaded(dev_priv);
 583 }
 584
 585 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 586 {
 587         assert_can_enable_dc5(dev_priv);
 588
 589         DRM_DEBUG_KMS("Enabling DC5\n");
 590
 591         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 592 }
 593
 594 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 595 {
 596         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 597                   "Backlight is not disabled.\n");
 598         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 599                   "DC6 already programmed to be enabled.\n");
 600
 601         assert_csr_loaded(dev_priv);
 602 }
 603
 604 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 605 {
 606         assert_can_enable_dc6(dev_priv);
 607
 608         DRM_DEBUG_KMS("Enabling DC6\n");
 609
 610         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 611
 612 }
 613
 614 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 615 {
 616         DRM_DEBUG_KMS("Disabling DC6\n");
 617
 618         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 619 }
 620
 621 static void
 622 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 623                                   struct i915_power_well *power_well)
 624 {
 625         enum skl_disp_power_wells power_well_id = power_well->data;
 626         u32 val;
 627         u32 mask;
 628
 629         mask = SKL_POWER_WELL_REQ(power_well_id);
 630
 631         val = I915_READ(HSW_PWR_WELL_KVMR);
 632         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 633                       power_well->name))
 634                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 635
 636         val = I915_READ(HSW_PWR_WELL_BIOS);
 637         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 638
 639         if (!(val & mask))
 640                 return;
 641
 642         /*
 643          * DMC is known to force on the request bits for power well 1 on SKL
 644          * and BXT and the misc IO power well on SKL but we don't expect any
 645          * other request bits to be set, so WARN for those.
 646          */
 647         if (power_well_id == SKL_DISP_PW_1 ||
 648             ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 649              power_well_id == SKL_DISP_PW_MISC_IO))
 650                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 651                                  "by DMC\n", power_well->name);
 652         else
 653                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 654                           power_well->name);
 655
 656         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 657         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 658 }
 659
 660 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 661                         struct i915_power_well *power_well, bool enable)
 662 {
 663         uint32_t tmp, fuse_status;
 664         uint32_t req_mask, state_mask;
 665         bool is_enabled, enable_requested, check_fuse_status = false;
 666
 667         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 668         fuse_status = I915_READ(SKL_FUSE_STATUS);
 669
 670         switch (power_well->data) {
 671         case SKL_DISP_PW_1:
 672                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 673                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 674                         DRM_ERROR("PG0 not enabled\n");
 675                         return;
 676                 }
 677                 break;
 678         case SKL_DISP_PW_2:
 679                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 680                         DRM_ERROR("PG1 in disabled state\n");
 681                         return;
 682                 }
 683                 break;
 684         case SKL_DISP_PW_DDI_A_E:
 685         case SKL_DISP_PW_DDI_B:
 686         case SKL_DISP_PW_DDI_C:
 687         case SKL_DISP_PW_DDI_D:
 688         case SKL_DISP_PW_MISC_IO:
 689                 break;
 690         default:
 691                 WARN(1, "Unknown power well %lu\n", power_well->data);
 692                 return;
 693         }
 694
 695         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 696         enable_requested = tmp & req_mask;
 697         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 698         is_enabled = tmp & state_mask;
 699
 700         if (!enable && enable_requested)
 701                 skl_power_well_pre_disable(dev_priv, power_well);
 702
 703         if (enable) {
 704                 if (!enable_requested) {
 705                         WARN((tmp & state_mask) &&
 706                                 !I915_READ(HSW_PWR_WELL_BIOS),
 707                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 708                                 when request is to disable!\n");
 709                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 710                 }
 711
 712                 if (!is_enabled) {
 713                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 714                         check_fuse_status = true;
 715                 }
 716         } else {
 717                 if (enable_requested) {
 718                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 719                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 720                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 721                 }
 722
 723                 if (IS_GEN9(dev_priv))
 724                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 725         }
 726
 727         if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
 728                      1))
 729                 DRM_ERROR("%s %s timeout\n",
 730                           power_well->name, enable ? "enable" : "disable");
 731
 732         if (check_fuse_status) {
 733                 if (power_well->data == SKL_DISP_PW_1) {
 734                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 735                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 736                                 DRM_ERROR("PG1 distributing status timeout\n");
 737                 } else if (power_well->data == SKL_DISP_PW_2) {
 738                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 739                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 740                                 DRM_ERROR("PG2 distributing status timeout\n");
 741                 }
 742         }
 743
 744         if (enable && !is_enabled)
 745                 skl_power_well_post_enable(dev_priv, power_well);
 746 }
 747
 748 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 749                                    struct i915_power_well *power_well)
 750 {
 751         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 752
 753         /*
 754          * We're taking over the BIOS, so clear any requests made by it since
 755          * the driver is in charge now.
 756          */
 757         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 758                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 759 }
 760
 761 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 762                                   struct i915_power_well *power_well)
 763 {
 764         hsw_set_power_well(dev_priv, power_well, true);
 765 }
 766
 767 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 768                                    struct i915_power_well *power_well)
 769 {
 770         hsw_set_power_well(dev_priv, power_well, false);
 771 }
 772
 773 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 774                                         struct i915_power_well *power_well)
 775 {
 776         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 777                 SKL_POWER_WELL_STATE(power_well->data);
 778
 779         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 780 }
 781
 782 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 783                                 struct i915_power_well *power_well)
 784 {
 785         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 786
 787         /* Clear any request made by BIOS as driver is taking over */
 788         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 789 }
 790
 791 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 792                                 struct i915_power_well *power_well)
 793 {
 794         skl_set_power_well(dev_priv, power_well, true);
 795 }
 796
 797 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 798                                 struct i915_power_well *power_well)
 799 {
 800         skl_set_power_well(dev_priv, power_well, false);
 801 }
 802
 803 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 804                                            struct i915_power_well *power_well)
 805 {
 806         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 807 }
 808
 809 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 810 {
 811         u32 tmp = I915_READ(DBUF_CTL);
 812
 813         WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
 814              (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
 815              "Unexpected DBuf power power state (0x%08x)\n", tmp);
 816 }
 817
 818 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 819                                           struct i915_power_well *power_well)
 820 {
 821         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 822
 823         WARN_ON(dev_priv->cdclk_freq !=
 824                 dev_priv->display.get_display_clock_speed(dev_priv->dev));
 825
 826         gen9_assert_dbuf_enabled(dev_priv);
 827
 828         if (IS_BROXTON(dev_priv))
 829                 broxton_ddi_phy_verify_state(dev_priv);
 830 }
 831
 832 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 833                                            struct i915_power_well *power_well)
 834 {
 835         if (!dev_priv->csr.dmc_payload)
 836                 return;
 837
 838         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 839                 skl_enable_dc6(dev_priv);
 840         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 841                 gen9_enable_dc5(dev_priv);
 842 }
 843
 844 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 845                                            struct i915_power_well *power_well)
 846 {
 847         if (power_well->count > 0)
 848                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 849         else
 850                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 851 }
 852
 853 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 854                                            struct i915_power_well *power_well)
 855 {
 856 }
 857
 858 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 859                                              struct i915_power_well *power_well)
 860 {
 861         return true;
 862 }
 863
 864 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 865                                struct i915_power_well *power_well, bool enable)
 866 {
 867         enum punit_power_well power_well_id = power_well->data;
 868         u32 mask;
 869         u32 state;
 870         u32 ctrl;
 871
 872         mask = PUNIT_PWRGT_MASK(power_well_id);
 873         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 874                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 875
 876         mutex_lock(&dev_priv->rps.hw_lock);
 877
 878 #define COND \
 879         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 880
 881         if (COND)
 882                 goto out;
 883
 884         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 885         ctrl &= ~mask;
 886         ctrl |= state;
 887         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 888
 889         if (wait_for(COND, 100))
 890                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 891                           state,
 892                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 893
 894 #undef COND
 895
 896 out:
 897         mutex_unlock(&dev_priv->rps.hw_lock);
 898 }
 899
 900 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 901                                    struct i915_power_well *power_well)
 902 {
 903         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 904 }
 905
 906 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 907                                   struct i915_power_well *power_well)
 908 {
 909         vlv_set_power_well(dev_priv, power_well, true);
 910 }
 911
 912 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 913                                    struct i915_power_well *power_well)
 914 {
 915         vlv_set_power_well(dev_priv, power_well, false);
 916 }
 917
 918 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 919                                    struct i915_power_well *power_well)
 920 {
 921         int power_well_id = power_well->data;
 922         bool enabled = false;
 923         u32 mask;
 924         u32 state;
 925         u32 ctrl;
 926
 927         mask = PUNIT_PWRGT_MASK(power_well_id);
 928         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 929
 930         mutex_lock(&dev_priv->rps.hw_lock);
 931
 932         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 933         /*
 934          * We only ever set the power-on and power-gate states, anything
 935          * else is unexpected.
 936          */
 937         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 938                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 939         if (state == ctrl)
 940                 enabled = true;
 941
 942         /*
 943          * A transient state at this point would mean some unexpected party
 944          * is poking at the power controls too.
 945          */
 946         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 947         WARN_ON(ctrl != state);
 948
 949         mutex_unlock(&dev_priv->rps.hw_lock);
 950
 951         return enabled;
 952 }
 953
 954 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 955 {
 956         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 957
 958         /*
 959          * Disable trickle feed and enable pnd deadline calculation
 960          */
 961         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 962         I915_WRITE(CBR1_VLV, 0);
 963
 964         WARN_ON(dev_priv->rawclk_freq == 0);
 965
 966         I915_WRITE(RAWCLK_FREQ_VLV,
 967                    DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
 968 }
 969
 970 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 971 {
 972         enum pipe pipe;
 973
 974         /*
 975          * Enable the CRI clock source so we can get at the
 976          * display and the reference clock for VGA
 977          * hotplug / manual detection. Supposedly DSI also
 978          * needs the ref clock up and running.
 979          *
 980          * CHV DPLL B/C have some issues if VGA mode is enabled.
 981          */
 982         for_each_pipe(dev_priv->dev, pipe) {
 983                 u32 val = I915_READ(DPLL(pipe));
 984
 985                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 986                 if (pipe != PIPE_A)
 987                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 988
 989                 I915_WRITE(DPLL(pipe), val);
 990         }
 991
 992         vlv_init_display_clock_gating(dev_priv);
 993
 994         spin_lock_irq(&dev_priv->irq_lock);
 995         valleyview_enable_display_irqs(dev_priv);
 996         spin_unlock_irq(&dev_priv->irq_lock);
 997
 998         /*
 999          * During driver initialization/resume we can avoid restoring the
1000          * part of the HW/SW state that will be inited anyway explicitly.
1001          */
1002         if (dev_priv->power_domains.initializing)
1003                 return;
1004
1005         intel_hpd_init(dev_priv);
1006
1007         i915_redisable_vga_power_on(dev_priv->dev);
1008 }
1009
1010 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1011 {
1012         spin_lock_irq(&dev_priv->irq_lock);
1013         valleyview_disable_display_irqs(dev_priv);
1014         spin_unlock_irq(&dev_priv->irq_lock);
1015
1016         /* make sure we're done processing display irqs */
1017         synchronize_irq(dev_priv->dev->irq);
1018
1019         vlv_power_sequencer_reset(dev_priv);
1020 }
1021
1022 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1023                                           struct i915_power_well *power_well)
1024 {
1025         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1026
1027         vlv_set_power_well(dev_priv, power_well, true);
1028
1029         vlv_display_power_well_init(dev_priv);
1030 }
1031
1032 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1033                                            struct i915_power_well *power_well)
1034 {
1035         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1036
1037         vlv_display_power_well_deinit(dev_priv);
1038
1039         vlv_set_power_well(dev_priv, power_well, false);
1040 }
1041
1042 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1043                                            struct i915_power_well *power_well)
1044 {
1045         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1046
1047         /* since ref/cri clock was enabled */
1048         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1049
1050         vlv_set_power_well(dev_priv, power_well, true);
1051
1052         /*
1053          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1054          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1055          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1056          *   b. The other bits such as sfr settings / modesel may all
1057          *      be set to 0.
1058          *
1059          * This should only be done on init and resume from S3 with
1060          * both PLLs disabled, or we risk losing DPIO and PLL
1061          * synchronization.
1062          */
1063         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1064 }
1065
1066 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1067                                             struct i915_power_well *power_well)
1068 {
1069         enum pipe pipe;
1070
1071         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1072
1073         for_each_pipe(dev_priv, pipe)
1074                 assert_pll_disabled(dev_priv, pipe);
1075
1076         /* Assert common reset */
1077         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1078
1079         vlv_set_power_well(dev_priv, power_well, false);
1080 }
1081
1082 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1083
1084 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1085                                                  int power_well_id)
1086 {
1087         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1088         int i;
1089
1090         for (i = 0; i < power_domains->power_well_count; i++) {
1091                 struct i915_power_well *power_well;
1092
1093                 power_well = &power_domains->power_wells[i];
1094                 if (power_well->data == power_well_id)
1095                         return power_well;
1096         }
1097
1098         return NULL;
1099 }
1100
1101 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1102
1103 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1104 {
1105         struct i915_power_well *cmn_bc =
1106                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1107         struct i915_power_well *cmn_d =
1108                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1109         u32 phy_control = dev_priv->chv_phy_control;
1110         u32 phy_status = 0;
1111         u32 phy_status_mask = 0xffffffff;
1112         u32 tmp;
1113
1114         /*
1115          * The BIOS can leave the PHY is some weird state
1116          * where it doesn't fully power down some parts.
1117          * Disable the asserts until the PHY has been fully
1118          * reset (ie. the power well has been disabled at
1119          * least once).
1120          */
1121         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1122                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1123                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1124                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1125                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1126                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1127                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1128
1129         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1130                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1131                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1132                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1133
1134         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1135                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1136
1137                 /* this assumes override is only used to enable lanes */
1138                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1139                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1140
1141                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1142                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1143
1144                 /* CL1 is on whenever anything is on in either channel */
1145                 if (BITS_SET(phy_control,
1146                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1147                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1148                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1149
1150                 /*
1151                  * The DPLLB check accounts for the pipe B + port A usage
1152                  * with CL2 powered up but all the lanes in the second channel
1153                  * powered down.
1154                  */
1155                 if (BITS_SET(phy_control,
1156                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1157                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1158                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1159
1160                 if (BITS_SET(phy_control,
1161                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1162                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1163                 if (BITS_SET(phy_control,
1164                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1165                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1166
1167                 if (BITS_SET(phy_control,
1168                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1169                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1170                 if (BITS_SET(phy_control,
1171                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1172                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1173         }
1174
1175         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1176                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1177
1178                 /* this assumes override is only used to enable lanes */
1179                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1180                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1181
1182                 if (BITS_SET(phy_control,
1183                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1184                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1185
1186                 if (BITS_SET(phy_control,
1187                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1188                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1189                 if (BITS_SET(phy_control,
1190                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1191                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1192         }
1193
1194         phy_status &= phy_status_mask;
1195
1196         /*
1197          * The PHY may be busy with some initial calibration and whatnot,
1198          * so the power state can take a while to actually change.
1199          */
1200         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1201                 WARN(phy_status != tmp,
1202                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1203                      tmp, phy_status, dev_priv->chv_phy_control);
1204 }
1205
1206 #undef BITS_SET
1207
1208 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1209                                            struct i915_power_well *power_well)
1210 {
1211         enum dpio_phy phy;
1212         enum pipe pipe;
1213         uint32_t tmp;
1214
1215         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1216                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1217
1218         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1219                 pipe = PIPE_A;
1220                 phy = DPIO_PHY0;
1221         } else {
1222                 pipe = PIPE_C;
1223                 phy = DPIO_PHY1;
1224         }
1225
1226         /* since ref/cri clock was enabled */
1227         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1228         vlv_set_power_well(dev_priv, power_well, true);
1229
1230         /* Poll for phypwrgood signal */
1231         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1232                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1233
1234         mutex_lock(&dev_priv->sb_lock);
1235
1236         /* Enable dynamic power down */
1237         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1238         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1239                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1240         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1241
1242         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1243                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1244                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1245                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1246         } else {
1247                 /*
1248                  * Force the non-existing CL2 off. BXT does this
1249                  * too, so maybe it saves some power even though
1250                  * CL2 doesn't exist?
1251                  */
1252                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1253                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1254                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1255         }
1256
1257         mutex_unlock(&dev_priv->sb_lock);
1258
1259         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1260         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1261
1262         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1263                       phy, dev_priv->chv_phy_control);
1264
1265         assert_chv_phy_status(dev_priv);
1266 }
1267
1268 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1269                                             struct i915_power_well *power_well)
1270 {
1271         enum dpio_phy phy;
1272
1273         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1274                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1275
1276         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1277                 phy = DPIO_PHY0;
1278                 assert_pll_disabled(dev_priv, PIPE_A);
1279                 assert_pll_disabled(dev_priv, PIPE_B);
1280         } else {
1281                 phy = DPIO_PHY1;
1282                 assert_pll_disabled(dev_priv, PIPE_C);
1283         }
1284
1285         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1286         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1287
1288         vlv_set_power_well(dev_priv, power_well, false);
1289
1290         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1291                       phy, dev_priv->chv_phy_control);
1292
1293         /* PHY is fully reset now, so we can enable the PHY state asserts */
1294         dev_priv->chv_phy_assert[phy] = true;
1295
1296         assert_chv_phy_status(dev_priv);
1297 }
1298
1299 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1300                                      enum dpio_channel ch, bool override, unsigned int mask)
1301 {
1302         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1303         u32 reg, val, expected, actual;
1304
1305         /*
1306          * The BIOS can leave the PHY is some weird state
1307          * where it doesn't fully power down some parts.
1308          * Disable the asserts until the PHY has been fully
1309          * reset (ie. the power well has been disabled at
1310          * least once).
1311          */
1312         if (!dev_priv->chv_phy_assert[phy])
1313                 return;
1314
1315         if (ch == DPIO_CH0)
1316                 reg = _CHV_CMN_DW0_CH0;
1317         else
1318                 reg = _CHV_CMN_DW6_CH1;
1319
1320         mutex_lock(&dev_priv->sb_lock);
1321         val = vlv_dpio_read(dev_priv, pipe, reg);
1322         mutex_unlock(&dev_priv->sb_lock);
1323
1324         /*
1325          * This assumes !override is only used when the port is disabled.
1326          * All lanes should power down even without the override when
1327          * the port is disabled.
1328          */
1329         if (!override || mask == 0xf) {
1330                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1331                 /*
1332                  * If CH1 common lane is not active anymore
1333                  * (eg. for pipe B DPLL) the entire channel will
1334                  * shut down, which causes the common lane registers
1335                  * to read as 0. That means we can't actually check
1336                  * the lane power down status bits, but as the entire
1337                  * register reads as 0 it's a good indication that the
1338                  * channel is indeed entirely powered down.
1339                  */
1340                 if (ch == DPIO_CH1 && val == 0)
1341                         expected = 0;
1342         } else if (mask != 0x0) {
1343                 expected = DPIO_ANYDL_POWERDOWN;
1344         } else {
1345                 expected = 0;
1346         }
1347
1348         if (ch == DPIO_CH0)
1349                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1350         else
1351                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1352         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1353
1354         WARN(actual != expected,
1355              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1356              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1357              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1358              reg, val);
1359 }
1360
1361 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1362                           enum dpio_channel ch, bool override)
1363 {
1364         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1365         bool was_override;
1366
1367         mutex_lock(&power_domains->lock);
1368
1369         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1370
1371         if (override == was_override)
1372                 goto out;
1373
1374         if (override)
1375                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1376         else
1377                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1378
1379         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1380
1381         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1382                       phy, ch, dev_priv->chv_phy_control);
1383
1384         assert_chv_phy_status(dev_priv);
1385
1386 out:
1387         mutex_unlock(&power_domains->lock);
1388
1389         return was_override;
1390 }
1391
1392 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1393                              bool override, unsigned int mask)
1394 {
1395         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1396         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1397         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1398         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1399
1400         mutex_lock(&power_domains->lock);
1401
1402         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1403         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1404
1405         if (override)
1406                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1407         else
1408                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1409
1410         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1411
1412         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1413                       phy, ch, mask, dev_priv->chv_phy_control);
1414
1415         assert_chv_phy_status(dev_priv);
1416
1417         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1418
1419         mutex_unlock(&power_domains->lock);
1420 }
1421
1422 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1423                                         struct i915_power_well *power_well)
1424 {
1425         enum pipe pipe = power_well->data;
1426         bool enabled;
1427         u32 state, ctrl;
1428
1429         mutex_lock(&dev_priv->rps.hw_lock);
1430
1431         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1432         /*
1433          * We only ever set the power-on and power-gate states, anything
1434          * else is unexpected.
1435          */
1436         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1437         enabled = state == DP_SSS_PWR_ON(pipe);
1438
1439         /*
1440          * A transient state at this point would mean some unexpected party
1441          * is poking at the power controls too.
1442          */
1443         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1444         WARN_ON(ctrl << 16 != state);
1445
1446         mutex_unlock(&dev_priv->rps.hw_lock);
1447
1448         return enabled;
1449 }
1450
1451 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1452                                     struct i915_power_well *power_well,
1453                                     bool enable)
1454 {
1455         enum pipe pipe = power_well->data;
1456         u32 state;
1457         u32 ctrl;
1458
1459         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1460
1461         mutex_lock(&dev_priv->rps.hw_lock);
1462
1463 #define COND \
1464         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1465
1466         if (COND)
1467                 goto out;
1468
1469         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1470         ctrl &= ~DP_SSC_MASK(pipe);
1471         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1472         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1473
1474         if (wait_for(COND, 100))
1475                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1476                           state,
1477                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1478
1479 #undef COND
1480
1481 out:
1482         mutex_unlock(&dev_priv->rps.hw_lock);
1483 }
1484
1485 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1486                                         struct i915_power_well *power_well)
1487 {
1488         WARN_ON_ONCE(power_well->data != PIPE_A);
1489
1490         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1491 }
1492
1493 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1494                                        struct i915_power_well *power_well)
1495 {
1496         WARN_ON_ONCE(power_well->data != PIPE_A);
1497
1498         chv_set_pipe_power_well(dev_priv, power_well, true);
1499
1500         vlv_display_power_well_init(dev_priv);
1501 }
1502
1503 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1504                                         struct i915_power_well *power_well)
1505 {
1506         WARN_ON_ONCE(power_well->data != PIPE_A);
1507
1508         vlv_display_power_well_deinit(dev_priv);
1509
1510         chv_set_pipe_power_well(dev_priv, power_well, false);
1511 }
1512
1513 static void
1514 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1515                                  enum intel_display_power_domain domain)
1516 {
1517         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1518         struct i915_power_well *power_well;
1519         int i;
1520
1521         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1522                 if (!power_well->count++)
1523                         intel_power_well_enable(dev_priv, power_well);
1524         }
1525
1526         power_domains->domain_use_count[domain]++;
1527 }
1528
1529 /**
1530  * intel_display_power_get - grab a power domain reference
1531  * @dev_priv: i915 device instance
1532  * @domain: power domain to reference
1533  *
1534  * This function grabs a power domain reference for @domain and ensures that the
1535  * power domain and all its parents are powered up. Therefore users should only
1536  * grab a reference to the innermost power domain they need.
1537  *
1538  * Any power domain reference obtained by this function must have a symmetric
1539  * call to intel_display_power_put() to release the reference again.
1540  */
1541 void intel_display_power_get(struct drm_i915_private *dev_priv,
1542                              enum intel_display_power_domain domain)
1543 {
1544         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1545
1546         intel_runtime_pm_get(dev_priv);
1547
1548         mutex_lock(&power_domains->lock);
1549
1550         __intel_display_power_get_domain(dev_priv, domain);
1551
1552         mutex_unlock(&power_domains->lock);
1553 }
1554
1555 /**
1556  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1557  * @dev_priv: i915 device instance
1558  * @domain: power domain to reference
1559  *
1560  * This function grabs a power domain reference for @domain and ensures that the
1561  * power domain and all its parents are powered up. Therefore users should only
1562  * grab a reference to the innermost power domain they need.
1563  *
1564  * Any power domain reference obtained by this function must have a symmetric
1565  * call to intel_display_power_put() to release the reference again.
1566  */
1567 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1568                                         enum intel_display_power_domain domain)
1569 {
1570         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1571         bool is_enabled;
1572
1573         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1574                 return false;
1575
1576         mutex_lock(&power_domains->lock);
1577
1578         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1579                 __intel_display_power_get_domain(dev_priv, domain);
1580                 is_enabled = true;
1581         } else {
1582                 is_enabled = false;
1583         }
1584
1585         mutex_unlock(&power_domains->lock);
1586
1587         if (!is_enabled)
1588                 intel_runtime_pm_put(dev_priv);
1589
1590         return is_enabled;
1591 }
1592
1593 /**
1594  * intel_display_power_put - release a power domain reference
1595  * @dev_priv: i915 device instance
1596  * @domain: power domain to reference
1597  *
1598  * This function drops the power domain reference obtained by
1599  * intel_display_power_get() and might power down the corresponding hardware
1600  * block right away if this is the last reference.
1601  */
1602 void intel_display_power_put(struct drm_i915_private *dev_priv,
1603                              enum intel_display_power_domain domain)
1604 {
1605         struct i915_power_domains *power_domains;
1606         struct i915_power_well *power_well;
1607         int i;
1608
1609         power_domains = &dev_priv->power_domains;
1610
1611         mutex_lock(&power_domains->lock);
1612
1613         WARN(!power_domains->domain_use_count[domain],
1614              "Use count on domain %s is already zero\n",
1615              intel_display_power_domain_str(domain));
1616         power_domains->domain_use_count[domain]--;
1617
1618         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1619                 WARN(!power_well->count,
1620                      "Use count on power well %s is already zero",
1621                      power_well->name);
1622
1623                 if (!--power_well->count)
1624                         intel_power_well_disable(dev_priv, power_well);
1625         }
1626
1627         mutex_unlock(&power_domains->lock);
1628
1629         intel_runtime_pm_put(dev_priv);
1630 }
1631
1632 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1633         BIT(POWER_DOMAIN_PIPE_B) |                      \
1634         BIT(POWER_DOMAIN_PIPE_C) |                      \
1635         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
1636         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1637         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1638         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1639         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1640         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1641         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1642         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1643         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1644         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1645         BIT(POWER_DOMAIN_VGA) |                         \
1646         BIT(POWER_DOMAIN_AUDIO) |                       \
1647         BIT(POWER_DOMAIN_INIT))
1648
1649 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1650         BIT(POWER_DOMAIN_PIPE_B) |                      \
1651         BIT(POWER_DOMAIN_PIPE_C) |                      \
1652         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1653         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1654         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1655         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1656         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1657         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1658         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1659         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1660         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1661         BIT(POWER_DOMAIN_VGA) |                         \
1662         BIT(POWER_DOMAIN_AUDIO) |                       \
1663         BIT(POWER_DOMAIN_INIT))
1664
1665 #define VLV_DISPLAY_POWER_DOMAINS (             \
1666         BIT(POWER_DOMAIN_PIPE_A) |              \
1667         BIT(POWER_DOMAIN_PIPE_B) |              \
1668         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1669         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1670         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1671         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1672         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1673         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1674         BIT(POWER_DOMAIN_PORT_DSI) |            \
1675         BIT(POWER_DOMAIN_PORT_CRT) |            \
1676         BIT(POWER_DOMAIN_VGA) |                 \
1677         BIT(POWER_DOMAIN_AUDIO) |               \
1678         BIT(POWER_DOMAIN_AUX_B) |               \
1679         BIT(POWER_DOMAIN_AUX_C) |               \
1680         BIT(POWER_DOMAIN_GMBUS) |               \
1681         BIT(POWER_DOMAIN_INIT))
1682
1683 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1684         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1685         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1686         BIT(POWER_DOMAIN_PORT_CRT) |            \
1687         BIT(POWER_DOMAIN_AUX_B) |               \
1688         BIT(POWER_DOMAIN_AUX_C) |               \
1689         BIT(POWER_DOMAIN_INIT))
1690
1691 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1692         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1693         BIT(POWER_DOMAIN_AUX_B) |               \
1694         BIT(POWER_DOMAIN_INIT))
1695
1696 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1697         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1698         BIT(POWER_DOMAIN_AUX_B) |               \
1699         BIT(POWER_DOMAIN_INIT))
1700
1701 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1702         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1703         BIT(POWER_DOMAIN_AUX_C) |               \
1704         BIT(POWER_DOMAIN_INIT))
1705
1706 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1707         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1708         BIT(POWER_DOMAIN_AUX_C) |               \
1709         BIT(POWER_DOMAIN_INIT))
1710
1711 #define CHV_DISPLAY_POWER_DOMAINS (             \
1712         BIT(POWER_DOMAIN_PIPE_A) |              \
1713         BIT(POWER_DOMAIN_PIPE_B) |              \
1714         BIT(POWER_DOMAIN_PIPE_C) |              \
1715         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1716         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1717         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1718         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1719         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1720         BIT(POWER_DOMAIN_TRANSCODER_C) |        \
1721         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1722         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1723         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1724         BIT(POWER_DOMAIN_PORT_DSI) |            \
1725         BIT(POWER_DOMAIN_VGA) |                 \
1726         BIT(POWER_DOMAIN_AUDIO) |               \
1727         BIT(POWER_DOMAIN_AUX_B) |               \
1728         BIT(POWER_DOMAIN_AUX_C) |               \
1729         BIT(POWER_DOMAIN_AUX_D) |               \
1730         BIT(POWER_DOMAIN_GMBUS) |               \
1731         BIT(POWER_DOMAIN_INIT))
1732
1733 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1734         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1735         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1736         BIT(POWER_DOMAIN_AUX_B) |               \
1737         BIT(POWER_DOMAIN_AUX_C) |               \
1738         BIT(POWER_DOMAIN_INIT))
1739
1740 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1741         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1742         BIT(POWER_DOMAIN_AUX_D) |               \
1743         BIT(POWER_DOMAIN_INIT))
1744
1745 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1746         .sync_hw = i9xx_always_on_power_well_noop,
1747         .enable = i9xx_always_on_power_well_noop,
1748         .disable = i9xx_always_on_power_well_noop,
1749         .is_enabled = i9xx_always_on_power_well_enabled,
1750 };
1751
1752 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1753         .sync_hw = chv_pipe_power_well_sync_hw,
1754         .enable = chv_pipe_power_well_enable,
1755         .disable = chv_pipe_power_well_disable,
1756         .is_enabled = chv_pipe_power_well_enabled,
1757 };
1758
1759 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1760         .sync_hw = vlv_power_well_sync_hw,
1761         .enable = chv_dpio_cmn_power_well_enable,
1762         .disable = chv_dpio_cmn_power_well_disable,
1763         .is_enabled = vlv_power_well_enabled,
1764 };
1765
1766 static struct i915_power_well i9xx_always_on_power_well[] = {
1767         {
1768                 .name = "always-on",
1769                 .always_on = 1,
1770                 .domains = POWER_DOMAIN_MASK,
1771                 .ops = &i9xx_always_on_power_well_ops,
1772         },
1773 };
1774
1775 static const struct i915_power_well_ops hsw_power_well_ops = {
1776         .sync_hw = hsw_power_well_sync_hw,
1777         .enable = hsw_power_well_enable,
1778         .disable = hsw_power_well_disable,
1779         .is_enabled = hsw_power_well_enabled,
1780 };
1781
1782 static const struct i915_power_well_ops skl_power_well_ops = {
1783         .sync_hw = skl_power_well_sync_hw,
1784         .enable = skl_power_well_enable,
1785         .disable = skl_power_well_disable,
1786         .is_enabled = skl_power_well_enabled,
1787 };
1788
1789 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1790         .sync_hw = gen9_dc_off_power_well_sync_hw,
1791         .enable = gen9_dc_off_power_well_enable,
1792         .disable = gen9_dc_off_power_well_disable,
1793         .is_enabled = gen9_dc_off_power_well_enabled,
1794 };
1795
1796 static struct i915_power_well hsw_power_wells[] = {
1797         {
1798                 .name = "always-on",
1799                 .always_on = 1,
1800                 .domains = POWER_DOMAIN_MASK,
1801                 .ops = &i9xx_always_on_power_well_ops,
1802         },
1803         {
1804                 .name = "display",
1805                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1806                 .ops = &hsw_power_well_ops,
1807         },
1808 };
1809
1810 static struct i915_power_well bdw_power_wells[] = {
1811         {
1812                 .name = "always-on",
1813                 .always_on = 1,
1814                 .domains = POWER_DOMAIN_MASK,
1815                 .ops = &i9xx_always_on_power_well_ops,
1816         },
1817         {
1818                 .name = "display",
1819                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1820                 .ops = &hsw_power_well_ops,
1821         },
1822 };
1823
1824 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1825         .sync_hw = vlv_power_well_sync_hw,
1826         .enable = vlv_display_power_well_enable,
1827         .disable = vlv_display_power_well_disable,
1828         .is_enabled = vlv_power_well_enabled,
1829 };
1830
1831 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1832         .sync_hw = vlv_power_well_sync_hw,
1833         .enable = vlv_dpio_cmn_power_well_enable,
1834         .disable = vlv_dpio_cmn_power_well_disable,
1835         .is_enabled = vlv_power_well_enabled,
1836 };
1837
1838 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1839         .sync_hw = vlv_power_well_sync_hw,
1840         .enable = vlv_power_well_enable,
1841         .disable = vlv_power_well_disable,
1842         .is_enabled = vlv_power_well_enabled,
1843 };
1844
1845 static struct i915_power_well vlv_power_wells[] = {
1846         {
1847                 .name = "always-on",
1848                 .always_on = 1,
1849                 .domains = POWER_DOMAIN_MASK,
1850                 .ops = &i9xx_always_on_power_well_ops,
1851                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1852         },
1853         {
1854                 .name = "display",
1855                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1856                 .data = PUNIT_POWER_WELL_DISP2D,
1857                 .ops = &vlv_display_power_well_ops,
1858         },
1859         {
1860                 .name = "dpio-tx-b-01",
1861                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1862                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1863                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1864                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1865                 .ops = &vlv_dpio_power_well_ops,
1866                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1867         },
1868         {
1869                 .name = "dpio-tx-b-23",
1870                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1871                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1872                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1873                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1874                 .ops = &vlv_dpio_power_well_ops,
1875                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1876         },
1877         {
1878                 .name = "dpio-tx-c-01",
1879                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1880                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1881                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1882                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1883                 .ops = &vlv_dpio_power_well_ops,
1884                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1885         },
1886         {
1887                 .name = "dpio-tx-c-23",
1888                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1889                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1890                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1891                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1892                 .ops = &vlv_dpio_power_well_ops,
1893                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1894         },
1895         {
1896                 .name = "dpio-common",
1897                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1898                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1899                 .ops = &vlv_dpio_cmn_power_well_ops,
1900         },
1901 };
1902
1903 static struct i915_power_well chv_power_wells[] = {
1904         {
1905                 .name = "always-on",
1906                 .always_on = 1,
1907                 .domains = POWER_DOMAIN_MASK,
1908                 .ops = &i9xx_always_on_power_well_ops,
1909         },
1910         {
1911                 .name = "display",
1912                 /*
1913                  * Pipe A power well is the new disp2d well. Pipe B and C
1914                  * power wells don't actually exist. Pipe A power well is
1915                  * required for any pipe to work.
1916                  */
1917                 .domains = CHV_DISPLAY_POWER_DOMAINS,
1918                 .data = PIPE_A,
1919                 .ops = &chv_pipe_power_well_ops,
1920         },
1921         {
1922                 .name = "dpio-common-bc",
1923                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1924                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1925                 .ops = &chv_dpio_cmn_power_well_ops,
1926         },
1927         {
1928                 .name = "dpio-common-d",
1929                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1930                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1931                 .ops = &chv_dpio_cmn_power_well_ops,
1932         },
1933 };
1934
1935 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1936                                     int power_well_id)
1937 {
1938         struct i915_power_well *power_well;
1939         bool ret;
1940
1941         power_well = lookup_power_well(dev_priv, power_well_id);
1942         ret = power_well->ops->is_enabled(dev_priv, power_well);
1943
1944         return ret;
1945 }
1946
1947 static struct i915_power_well skl_power_wells[] = {
1948         {
1949                 .name = "always-on",
1950                 .always_on = 1,
1951                 .domains = POWER_DOMAIN_MASK,
1952                 .ops = &i9xx_always_on_power_well_ops,
1953                 .data = SKL_DISP_PW_ALWAYS_ON,
1954         },
1955         {
1956                 .name = "power well 1",
1957                 /* Handled by the DMC firmware */
1958                 .domains = 0,
1959                 .ops = &skl_power_well_ops,
1960                 .data = SKL_DISP_PW_1,
1961         },
1962         {
1963                 .name = "MISC IO power well",
1964                 /* Handled by the DMC firmware */
1965                 .domains = 0,
1966                 .ops = &skl_power_well_ops,
1967                 .data = SKL_DISP_PW_MISC_IO,
1968         },
1969         {
1970                 .name = "DC off",
1971                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1972                 .ops = &gen9_dc_off_power_well_ops,
1973                 .data = SKL_DISP_PW_DC_OFF,
1974         },
1975         {
1976                 .name = "power well 2",
1977                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1978                 .ops = &skl_power_well_ops,
1979                 .data = SKL_DISP_PW_2,
1980         },
1981         {
1982                 .name = "DDI A/E power well",
1983                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1984                 .ops = &skl_power_well_ops,
1985                 .data = SKL_DISP_PW_DDI_A_E,
1986         },
1987         {
1988                 .name = "DDI B power well",
1989                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1990                 .ops = &skl_power_well_ops,
1991                 .data = SKL_DISP_PW_DDI_B,
1992         },
1993         {
1994                 .name = "DDI C power well",
1995                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1996                 .ops = &skl_power_well_ops,
1997                 .data = SKL_DISP_PW_DDI_C,
1998         },
1999         {
2000                 .name = "DDI D power well",
2001                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
2002                 .ops = &skl_power_well_ops,
2003                 .data = SKL_DISP_PW_DDI_D,
2004         },
2005 };
2006
2007 static struct i915_power_well bxt_power_wells[] = {
2008         {
2009                 .name = "always-on",
2010                 .always_on = 1,
2011                 .domains = POWER_DOMAIN_MASK,
2012                 .ops = &i9xx_always_on_power_well_ops,
2013         },
2014         {
2015                 .name = "power well 1",
2016                 .domains = 0,
2017                 .ops = &skl_power_well_ops,
2018                 .data = SKL_DISP_PW_1,
2019         },
2020         {
2021                 .name = "DC off",
2022                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2023                 .ops = &gen9_dc_off_power_well_ops,
2024                 .data = SKL_DISP_PW_DC_OFF,
2025         },
2026         {
2027                 .name = "power well 2",
2028                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2029                 .ops = &skl_power_well_ops,
2030                 .data = SKL_DISP_PW_2,
2031         },
2032 };
2033
2034 static int
2035 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2036                                    int disable_power_well)
2037 {
2038         if (disable_power_well >= 0)
2039                 return !!disable_power_well;
2040
2041         return 1;
2042 }
2043
2044 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2045                                     int enable_dc)
2046 {
2047         uint32_t mask;
2048         int requested_dc;
2049         int max_dc;
2050
2051         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2052                 max_dc = 2;
2053                 mask = 0;
2054         } else if (IS_BROXTON(dev_priv)) {
2055                 max_dc = 1;
2056                 /*
2057                  * DC9 has a separate HW flow from the rest of the DC states,
2058                  * not depending on the DMC firmware. It's needed by system
2059                  * suspend/resume, so allow it unconditionally.
2060                  */
2061                 mask = DC_STATE_EN_DC9;
2062         } else {
2063                 max_dc = 0;
2064                 mask = 0;
2065         }
2066
2067         if (!i915.disable_power_well)
2068                 max_dc = 0;
2069
2070         if (enable_dc >= 0 && enable_dc <= max_dc) {
2071                 requested_dc = enable_dc;
2072         } else if (enable_dc == -1) {
2073                 requested_dc = max_dc;
2074         } else if (enable_dc > max_dc && enable_dc <= 2) {
2075                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2076                               enable_dc, max_dc);
2077                 requested_dc = max_dc;
2078         } else {
2079                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2080                 requested_dc = max_dc;
2081         }
2082
2083         if (requested_dc > 1)
2084                 mask |= DC_STATE_EN_UPTO_DC6;
2085         if (requested_dc > 0)
2086                 mask |= DC_STATE_EN_UPTO_DC5;
2087
2088         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2089
2090         return mask;
2091 }
2092
2093 #define set_power_wells(power_domains, __power_wells) ({                \
2094         (power_domains)->power_wells = (__power_wells);                 \
2095         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2096 })
2097
2098 /**
2099  * intel_power_domains_init - initializes the power domain structures
2100  * @dev_priv: i915 device instance
2101  *
2102  * Initializes the power domain structures for @dev_priv depending upon the
2103  * supported platform.
2104  */
2105 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2106 {
2107         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2108
2109         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2110                                                      i915.disable_power_well);
2111         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2112                                                             i915.enable_dc);
2113
2114         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2115
2116         mutex_init(&power_domains->lock);
2117
2118         /*
2119          * The enabling order will be from lower to higher indexed wells,
2120          * the disabling order is reversed.
2121          */
2122         if (IS_HASWELL(dev_priv)) {
2123                 set_power_wells(power_domains, hsw_power_wells);
2124         } else if (IS_BROADWELL(dev_priv)) {
2125                 set_power_wells(power_domains, bdw_power_wells);
2126         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2127                 set_power_wells(power_domains, skl_power_wells);
2128         } else if (IS_BROXTON(dev_priv)) {
2129                 set_power_wells(power_domains, bxt_power_wells);
2130         } else if (IS_CHERRYVIEW(dev_priv)) {
2131                 set_power_wells(power_domains, chv_power_wells);
2132         } else if (IS_VALLEYVIEW(dev_priv)) {
2133                 set_power_wells(power_domains, vlv_power_wells);
2134         } else {
2135                 set_power_wells(power_domains, i9xx_always_on_power_well);
2136         }
2137
2138         return 0;
2139 }
2140
2141 /**
2142  * intel_power_domains_fini - finalizes the power domain structures
2143  * @dev_priv: i915 device instance
2144  *
2145  * Finalizes the power domain structures for @dev_priv depending upon the
2146  * supported platform. This function also disables runtime pm and ensures that
2147  * the device stays powered up so that the driver can be reloaded.
2148  */
2149 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2150 {
2151         struct device *device = &dev_priv->dev->pdev->dev;
2152
2153         /*
2154          * The i915.ko module is still not prepared to be loaded when
2155          * the power well is not enabled, so just enable it in case
2156          * we're going to unload/reload.
2157          * The following also reacquires the RPM reference the core passed
2158          * to the driver during loading, which is dropped in
2159          * intel_runtime_pm_enable(). We have to hand back the control of the
2160          * device to the core with this reference held.
2161          */
2162         intel_display_set_init_power(dev_priv, true);
2163
2164         /* Remove the refcount we took to keep power well support disabled. */
2165         if (!i915.disable_power_well)
2166                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2167
2168         /*
2169          * Remove the refcount we took in intel_runtime_pm_enable() in case
2170          * the platform doesn't support runtime PM.
2171          */
2172         if (!HAS_RUNTIME_PM(dev_priv))
2173                 pm_runtime_put(device);
2174 }
2175
2176 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2177 {
2178         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2179         struct i915_power_well *power_well;
2180         int i;
2181
2182         mutex_lock(&power_domains->lock);
2183         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2184                 power_well->ops->sync_hw(dev_priv, power_well);
2185                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2186                                                                      power_well);
2187         }
2188         mutex_unlock(&power_domains->lock);
2189 }
2190
2191 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
2192 {
2193         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
2194         POSTING_READ(DBUF_CTL);
2195
2196         udelay(10);
2197
2198         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
2199                 DRM_ERROR("DBuf power enable timeout\n");
2200 }
2201
2202 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
2203 {
2204         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
2205         POSTING_READ(DBUF_CTL);
2206
2207         udelay(10);
2208
2209         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
2210                 DRM_ERROR("DBuf power disable timeout!\n");
2211 }
2212
2213 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2214                                    bool resume)
2215 {
2216         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2217         struct i915_power_well *well;
2218         uint32_t val;
2219
2220         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2221
2222         /* enable PCH reset handshake */
2223         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2224         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2225
2226         /* enable PG1 and Misc I/O */
2227         mutex_lock(&power_domains->lock);
2228
2229         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2230         intel_power_well_enable(dev_priv, well);
2231
2232         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2233         intel_power_well_enable(dev_priv, well);
2234
2235         mutex_unlock(&power_domains->lock);
2236
2237         skl_init_cdclk(dev_priv);
2238
2239         gen9_dbuf_enable(dev_priv);
2240
2241         if (resume && dev_priv->csr.dmc_payload)
2242                 intel_csr_load_program(dev_priv);
2243 }
2244
2245 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2246 {
2247         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2248         struct i915_power_well *well;
2249
2250         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2251
2252         gen9_dbuf_disable(dev_priv);
2253
2254         skl_uninit_cdclk(dev_priv);
2255
2256         /* The spec doesn't call for removing the reset handshake flag */
2257         /* disable PG1 and Misc I/O */
2258
2259         mutex_lock(&power_domains->lock);
2260
2261         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2262         intel_power_well_disable(dev_priv, well);
2263
2264         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2265         intel_power_well_disable(dev_priv, well);
2266
2267         mutex_unlock(&power_domains->lock);
2268 }
2269
2270 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2271                            bool resume)
2272 {
2273         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2274         struct i915_power_well *well;
2275         uint32_t val;
2276
2277         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2278
2279         /*
2280          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2281          * or else the reset will hang because there is no PCH to respond.
2282          * Move the handshake programming to initialization sequence.
2283          * Previously was left up to BIOS.
2284          */
2285         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2286         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2287         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2288
2289         /* Enable PG1 */
2290         mutex_lock(&power_domains->lock);
2291
2292         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2293         intel_power_well_enable(dev_priv, well);
2294
2295         mutex_unlock(&power_domains->lock);
2296
2297         broxton_init_cdclk(dev_priv);
2298
2299         gen9_dbuf_enable(dev_priv);
2300
2301         broxton_ddi_phy_init(dev_priv);
2302
2303         broxton_ddi_phy_verify_state(dev_priv);
2304
2305         if (resume && dev_priv->csr.dmc_payload)
2306                 intel_csr_load_program(dev_priv);
2307 }
2308
2309 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2310 {
2311         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2312         struct i915_power_well *well;
2313
2314         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2315
2316         broxton_ddi_phy_uninit(dev_priv);
2317
2318         gen9_dbuf_disable(dev_priv);
2319
2320         broxton_uninit_cdclk(dev_priv);
2321
2322         /* The spec doesn't call for removing the reset handshake flag */
2323
2324         /* Disable PG1 */
2325         mutex_lock(&power_domains->lock);
2326
2327         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2328         intel_power_well_disable(dev_priv, well);
2329
2330         mutex_unlock(&power_domains->lock);
2331 }
2332
2333 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2334 {
2335         struct i915_power_well *cmn_bc =
2336                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2337         struct i915_power_well *cmn_d =
2338                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2339
2340         /*
2341          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2342          * workaround never ever read DISPLAY_PHY_CONTROL, and
2343          * instead maintain a shadow copy ourselves. Use the actual
2344          * power well state and lane status to reconstruct the
2345          * expected initial value.
2346          */
2347         dev_priv->chv_phy_control =
2348                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2349                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2350                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2351                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2352                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2353
2354         /*
2355          * If all lanes are disabled we leave the override disabled
2356          * with all power down bits cleared to match the state we
2357          * would use after disabling the port. Otherwise enable the
2358          * override and set the lane powerdown bits accding to the
2359          * current lane status.
2360          */
2361         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2362                 uint32_t status = I915_READ(DPLL(PIPE_A));
2363                 unsigned int mask;
2364
2365                 mask = status & DPLL_PORTB_READY_MASK;
2366                 if (mask == 0xf)
2367                         mask = 0x0;
2368                 else
2369                         dev_priv->chv_phy_control |=
2370                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2371
2372                 dev_priv->chv_phy_control |=
2373                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2374
2375                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2376                 if (mask == 0xf)
2377                         mask = 0x0;
2378                 else
2379                         dev_priv->chv_phy_control |=
2380                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2381
2382                 dev_priv->chv_phy_control |=
2383                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2384
2385                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2386
2387                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2388         } else {
2389                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2390         }
2391
2392         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2393                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2394                 unsigned int mask;
2395
2396                 mask = status & DPLL_PORTD_READY_MASK;
2397
2398                 if (mask == 0xf)
2399                         mask = 0x0;
2400                 else
2401                         dev_priv->chv_phy_control |=
2402                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2403
2404                 dev_priv->chv_phy_control |=
2405                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2406
2407                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2408
2409                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2410         } else {
2411                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2412         }
2413
2414         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2415
2416         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2417                       dev_priv->chv_phy_control);
2418 }
2419
2420 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2421 {
2422         struct i915_power_well *cmn =
2423                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2424         struct i915_power_well *disp2d =
2425                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2426
2427         /* If the display might be already active skip this */
2428         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2429             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2430             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2431                 return;
2432
2433         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2434
2435         /* cmnlane needs DPLL registers */
2436         disp2d->ops->enable(dev_priv, disp2d);
2437
2438         /*
2439          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2440          * Need to assert and de-assert PHY SB reset by gating the
2441          * common lane power, then un-gating it.
2442          * Simply ungating isn't enough to reset the PHY enough to get
2443          * ports and lanes running.
2444          */
2445         cmn->ops->disable(dev_priv, cmn);
2446 }
2447
2448 /**
2449  * intel_power_domains_init_hw - initialize hardware power domain state
2450  * @dev_priv: i915 device instance
2451  *
2452  * This function initializes the hardware power domain state and enables all
2453  * power domains using intel_display_set_init_power().
2454  */
2455 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2456 {
2457         struct drm_device *dev = dev_priv->dev;
2458         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2459
2460         power_domains->initializing = true;
2461
2462         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2463                 skl_display_core_init(dev_priv, resume);
2464         } else if (IS_BROXTON(dev)) {
2465                 bxt_display_core_init(dev_priv, resume);
2466         } else if (IS_CHERRYVIEW(dev)) {
2467                 mutex_lock(&power_domains->lock);
2468                 chv_phy_control_init(dev_priv);
2469                 mutex_unlock(&power_domains->lock);
2470         } else if (IS_VALLEYVIEW(dev)) {
2471                 mutex_lock(&power_domains->lock);
2472                 vlv_cmnlane_wa(dev_priv);
2473                 mutex_unlock(&power_domains->lock);
2474         }
2475
2476         /* For now, we need the power well to be always enabled. */
2477         intel_display_set_init_power(dev_priv, true);
2478         /* Disable power support if the user asked so. */
2479         if (!i915.disable_power_well)
2480                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2481         intel_power_domains_sync_hw(dev_priv);
2482         power_domains->initializing = false;
2483 }
2484
2485 /**
2486  * intel_power_domains_suspend - suspend power domain state
2487  * @dev_priv: i915 device instance
2488  *
2489  * This function prepares the hardware power domain state before entering
2490  * system suspend. It must be paired with intel_power_domains_init_hw().
2491  */
2492 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2493 {
2494         /*
2495          * Even if power well support was disabled we still want to disable
2496          * power wells while we are system suspended.
2497          */
2498         if (!i915.disable_power_well)
2499                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2500
2501         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2502                 skl_display_core_uninit(dev_priv);
2503         else if (IS_BROXTON(dev_priv))
2504                 bxt_display_core_uninit(dev_priv);
2505 }
2506
2507 /**
2508  * intel_runtime_pm_get - grab a runtime pm reference
2509  * @dev_priv: i915 device instance
2510  *
2511  * This function grabs a device-level runtime pm reference (mostly used for GEM
2512  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2513  *
2514  * Any runtime pm reference obtained by this function must have a symmetric
2515  * call to intel_runtime_pm_put() to release the reference again.
2516  */
2517 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2518 {
2519         struct drm_device *dev = dev_priv->dev;
2520         struct device *device = &dev->pdev->dev;
2521
2522         pm_runtime_get_sync(device);
2523
2524         atomic_inc(&dev_priv->pm.wakeref_count);
2525         assert_rpm_wakelock_held(dev_priv);
2526 }
2527
2528 /**
2529  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2530  * @dev_priv: i915 device instance
2531  *
2532  * This function grabs a device-level runtime pm reference if the device is
2533  * already in use and ensures that it is powered up.
2534  *
2535  * Any runtime pm reference obtained by this function must have a symmetric
2536  * call to intel_runtime_pm_put() to release the reference again.
2537  */
2538 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2539 {
2540         struct drm_device *dev = dev_priv->dev;
2541         struct device *device = &dev->pdev->dev;
2542
2543         if (IS_ENABLED(CONFIG_PM)) {
2544                 int ret = pm_runtime_get_if_in_use(device);
2545
2546                 /*
2547                  * In cases runtime PM is disabled by the RPM core and we get
2548                  * an -EINVAL return value we are not supposed to call this
2549                  * function, since the power state is undefined. This applies
2550                  * atm to the late/early system suspend/resume handlers.
2551                  */
2552                 WARN_ON_ONCE(ret < 0);
2553                 if (ret <= 0)
2554                         return false;
2555         }
2556
2557         atomic_inc(&dev_priv->pm.wakeref_count);
2558         assert_rpm_wakelock_held(dev_priv);
2559
2560         return true;
2561 }
2562
2563 /**
2564  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2565  * @dev_priv: i915 device instance
2566  *
2567  * This function grabs a device-level runtime pm reference (mostly used for GEM
2568  * code to ensure the GTT or GT is on).
2569  *
2570  * It will _not_ power up the device but instead only check that it's powered
2571  * on.  Therefore it is only valid to call this functions from contexts where
2572  * the device is known to be powered up and where trying to power it up would
2573  * result in hilarity and deadlocks. That pretty much means only the system
2574  * suspend/resume code where this is used to grab runtime pm references for
2575  * delayed setup down in work items.
2576  *
2577  * Any runtime pm reference obtained by this function must have a symmetric
2578  * call to intel_runtime_pm_put() to release the reference again.
2579  */
2580 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2581 {
2582         struct drm_device *dev = dev_priv->dev;
2583         struct device *device = &dev->pdev->dev;
2584
2585         assert_rpm_wakelock_held(dev_priv);
2586         pm_runtime_get_noresume(device);
2587
2588         atomic_inc(&dev_priv->pm.wakeref_count);
2589 }
2590
2591 /**
2592  * intel_runtime_pm_put - release a runtime pm reference
2593  * @dev_priv: i915 device instance
2594  *
2595  * This function drops the device-level runtime pm reference obtained by
2596  * intel_runtime_pm_get() and might power down the corresponding
2597  * hardware block right away if this is the last reference.
2598  */
2599 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2600 {
2601         struct drm_device *dev = dev_priv->dev;
2602         struct device *device = &dev->pdev->dev;
2603
2604         assert_rpm_wakelock_held(dev_priv);
2605         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2606                 atomic_inc(&dev_priv->pm.atomic_seq);
2607
2608         pm_runtime_mark_last_busy(device);
2609         pm_runtime_put_autosuspend(device);
2610 }
2611
2612 /**
2613  * intel_runtime_pm_enable - enable runtime pm
2614  * @dev_priv: i915 device instance
2615  *
2616  * This function enables runtime pm at the end of the driver load sequence.
2617  *
2618  * Note that this function does currently not enable runtime pm for the
2619  * subordinate display power domains. That is only done on the first modeset
2620  * using intel_display_set_init_power().
2621  */
2622 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2623 {
2624         struct drm_device *dev = dev_priv->dev;
2625         struct device *device = &dev->pdev->dev;
2626
2627         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2628         pm_runtime_mark_last_busy(device);
2629
2630         /*
2631          * Take a permanent reference to disable the RPM functionality and drop
2632          * it only when unloading the driver. Use the low level get/put helpers,
2633          * so the driver's own RPM reference tracking asserts also work on
2634          * platforms without RPM support.
2635          */
2636         if (!HAS_RUNTIME_PM(dev)) {
2637                 pm_runtime_dont_use_autosuspend(device);
2638                 pm_runtime_get_sync(device);
2639         } else {
2640                 pm_runtime_use_autosuspend(device);
2641         }
2642
2643         /*
2644          * The core calls the driver load handler with an RPM reference held.
2645          * We drop that here and will reacquire it during unloading in
2646          * intel_power_domains_fini().
2647          */
2648         pm_runtime_put_autosuspend(device);
2649 }
2650