drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29
  30 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  31
  32 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  33 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
  34
  35 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  36 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
  37
  38 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  39 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
  40
  41 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  42 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
  43
  44 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  45
  46 static const char * const forcewake_domain_names[] = {
  47         "render",
  48         "blitter",
  49         "media",
  50 };
  51
  52 const char *
  53 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  54 {
  55         BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
  56                      FW_DOMAIN_ID_COUNT);
  57
  58         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  59                 return forcewake_domain_names[id];
  60
  61         WARN_ON(id);
  62
  63         return "unknown";
  64 }
  65
  66 static void
  67 assert_device_not_suspended(struct drm_i915_private *dev_priv)
  68 {
  69         WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
  70                   "Device suspended\n");
  71 }
  72
  73 static inline void
  74 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  75 {
  76         WARN_ON(d->reg_set == 0);
  77         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  78 }
  79
  80 static inline void
  81 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  82 {
  83         mod_timer_pinned(&d->timer, jiffies + 1);
  84 }
  85
  86 static inline void
  87 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  88 {
  89         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  90                              FORCEWAKE_KERNEL) == 0,
  91                             FORCEWAKE_ACK_TIMEOUT_MS))
  92                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  93                           intel_uncore_forcewake_domain_to_str(d->id));
  94 }
  95
  96 static inline void
  97 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  98 {
  99         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
 100 }
 101
 102 static inline void
 103 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
 104 {
 105         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
 106                              FORCEWAKE_KERNEL),
 107                             FORCEWAKE_ACK_TIMEOUT_MS))
 108                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 109                           intel_uncore_forcewake_domain_to_str(d->id));
 110 }
 111
 112 static inline void
 113 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 114 {
 115         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 116 }
 117
 118 static inline void
 119 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 120 {
 121         /* something from same cacheline, but not from the set register */
 122         if (d->reg_post)
 123                 __raw_posting_read(d->i915, d->reg_post);
 124 }
 125
 126 static void
 127 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 128 {
 129         struct intel_uncore_forcewake_domain *d;
 130         enum forcewake_domain_id id;
 131
 132         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 133                 fw_domain_wait_ack_clear(d);
 134                 fw_domain_get(d);
 135                 fw_domain_wait_ack(d);
 136         }
 137 }
 138
 139 static void
 140 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 141 {
 142         struct intel_uncore_forcewake_domain *d;
 143         enum forcewake_domain_id id;
 144
 145         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 146                 fw_domain_put(d);
 147                 fw_domain_posting_read(d);
 148         }
 149 }
 150
 151 static void
 152 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 153 {
 154         struct intel_uncore_forcewake_domain *d;
 155         enum forcewake_domain_id id;
 156
 157         /* No need to do for all, just do for first found */
 158         for_each_fw_domain(d, dev_priv, id) {
 159                 fw_domain_posting_read(d);
 160                 break;
 161         }
 162 }
 163
 164 static void
 165 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 166 {
 167         struct intel_uncore_forcewake_domain *d;
 168         enum forcewake_domain_id id;
 169
 170         if (dev_priv->uncore.fw_domains == 0)
 171                 return;
 172
 173         for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
 174                 fw_domain_reset(d);
 175
 176         fw_domains_posting_read(dev_priv);
 177 }
 178
 179 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 180 {
 181         /* w/a for a sporadic read returning 0 by waiting for the GT
 182          * thread to wake up.
 183          */
 184         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 185                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 186                 DRM_ERROR("GT thread status wait timed out\n");
 187 }
 188
 189 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 190                                               enum forcewake_domains fw_domains)
 191 {
 192         fw_domains_get(dev_priv, fw_domains);
 193
 194         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 195         __gen6_gt_wait_for_thread_c0(dev_priv);
 196 }
 197
 198 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 199 {
 200         u32 gtfifodbg;
 201
 202         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 203         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 204                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 205 }
 206
 207 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 208                                      enum forcewake_domains fw_domains)
 209 {
 210         fw_domains_put(dev_priv, fw_domains);
 211         gen6_gt_check_fifodbg(dev_priv);
 212 }
 213
 214 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 215 {
 216         int ret = 0;
 217
 218         /* On VLV, FIFO will be shared by both SW and HW.
 219          * So, we need to read the FREE_ENTRIES everytime */
 220         if (IS_VALLEYVIEW(dev_priv->dev))
 221                 dev_priv->uncore.fifo_count =
 222                         __raw_i915_read32(dev_priv, GTFIFOCTL) &
 223                                                 GT_FIFO_FREE_ENTRIES_MASK;
 224
 225         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 226                 int loop = 500;
 227                 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 228                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 229                         udelay(10);
 230                         fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 231                 }
 232                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 233                         ++ret;
 234                 dev_priv->uncore.fifo_count = fifo;
 235         }
 236         dev_priv->uncore.fifo_count--;
 237
 238         return ret;
 239 }
 240
 241 static void intel_uncore_fw_release_timer(unsigned long arg)
 242 {
 243         struct intel_uncore_forcewake_domain *domain = (void *)arg;
 244         unsigned long irqflags;
 245
 246         assert_device_not_suspended(domain->i915);
 247
 248         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 249         if (WARN_ON(domain->wake_count == 0))
 250                 domain->wake_count++;
 251
 252         if (--domain->wake_count == 0)
 253                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 254                                                           1 << domain->id);
 255
 256         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 257 }
 258
 259 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 260 {
 261         struct drm_i915_private *dev_priv = dev->dev_private;
 262         unsigned long irqflags;
 263         struct intel_uncore_forcewake_domain *domain;
 264         int retry_count = 100;
 265         enum forcewake_domain_id id;
 266         enum forcewake_domains fw = 0, active_domains;
 267
 268         /* Hold uncore.lock across reset to prevent any register access
 269          * with forcewake not set correctly. Wait until all pending
 270          * timers are run before holding.
 271          */
 272         while (1) {
 273                 active_domains = 0;
 274
 275                 for_each_fw_domain(domain, dev_priv, id) {
 276                         if (del_timer_sync(&domain->timer) == 0)
 277                                 continue;
 278
 279                         intel_uncore_fw_release_timer((unsigned long)domain);
 280                 }
 281
 282                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 283
 284                 for_each_fw_domain(domain, dev_priv, id) {
 285                         if (timer_pending(&domain->timer))
 286                                 active_domains |= (1 << id);
 287                 }
 288
 289                 if (active_domains == 0)
 290                         break;
 291
 292                 if (--retry_count == 0) {
 293                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 294                         break;
 295                 }
 296
 297                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 298                 cond_resched();
 299         }
 300
 301         WARN_ON(active_domains);
 302
 303         for_each_fw_domain(domain, dev_priv, id)
 304                 if (domain->wake_count)
 305                         fw |= 1 << id;
 306
 307         if (fw)
 308                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 309
 310         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 311
 312         if (restore) { /* If reset with a user forcewake, try to restore */
 313                 if (fw)
 314                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 315
 316                 if (IS_GEN6(dev) || IS_GEN7(dev))
 317                         dev_priv->uncore.fifo_count =
 318                                 __raw_i915_read32(dev_priv, GTFIFOCTL) &
 319                                 GT_FIFO_FREE_ENTRIES_MASK;
 320         }
 321
 322         if (!restore)
 323                 assert_forcewakes_inactive(dev_priv);
 324
 325         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 326 }
 327
 328 static void intel_uncore_ellc_detect(struct drm_device *dev)
 329 {
 330         struct drm_i915_private *dev_priv = dev->dev_private;
 331
 332         if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
 333              INTEL_INFO(dev)->gen >= 9) &&
 334             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
 335                 /* The docs do not explain exactly how the calculation can be
 336                  * made. It is somewhat guessable, but for now, it's always
 337                  * 128MB.
 338                  * NB: We can't write IDICR yet because we do not have gt funcs
 339                  * set up */
 340                 dev_priv->ellc_size = 128;
 341                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 342         }
 343 }
 344
 345 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 346                                           bool restore_forcewake)
 347 {
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349
 350         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 351                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 352
 353         /* clear out old GT FIFO errors */
 354         if (IS_GEN6(dev) || IS_GEN7(dev))
 355                 __raw_i915_write32(dev_priv, GTFIFODBG,
 356                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 357
 358         intel_uncore_forcewake_reset(dev, restore_forcewake);
 359 }
 360
 361 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 362 {
 363         __intel_uncore_early_sanitize(dev, restore_forcewake);
 364         i915_check_and_clear_faults(dev);
 365 }
 366
 367 void intel_uncore_sanitize(struct drm_device *dev)
 368 {
 369         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 370         intel_disable_gt_powersave(dev);
 371 }
 372
 373 /**
 374  * intel_uncore_forcewake_get - grab forcewake domain references
 375  * @dev_priv: i915 device instance
 376  * @fw_domains: forcewake domains to get reference on
 377  *
 378  * This function can be used get GT's forcewake domain references.
 379  * Normal register access will handle the forcewake domains automatically.
 380  * However if some sequence requires the GT to not power down a particular
 381  * forcewake domains this function should be called at the beginning of the
 382  * sequence. And subsequently the reference should be dropped by symmetric
 383  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 384  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 385  */
 386 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 387                                 enum forcewake_domains fw_domains)
 388 {
 389         unsigned long irqflags;
 390         struct intel_uncore_forcewake_domain *domain;
 391         enum forcewake_domain_id id;
 392
 393         if (!dev_priv->uncore.funcs.force_wake_get)
 394                 return;
 395
 396         WARN_ON(dev_priv->pm.suspended);
 397
 398         fw_domains &= dev_priv->uncore.fw_domains;
 399
 400         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 401
 402         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 403                 if (domain->wake_count++)
 404                         fw_domains &= ~(1 << id);
 405         }
 406
 407         if (fw_domains)
 408                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 409
 410         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 411 }
 412
 413 /**
 414  * intel_uncore_forcewake_put - release a forcewake domain reference
 415  * @dev_priv: i915 device instance
 416  * @fw_domains: forcewake domains to put references
 417  *
 418  * This function drops the device-level forcewakes for specified
 419  * domains obtained by intel_uncore_forcewake_get().
 420  */
 421 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 422                                 enum forcewake_domains fw_domains)
 423 {
 424         unsigned long irqflags;
 425         struct intel_uncore_forcewake_domain *domain;
 426         enum forcewake_domain_id id;
 427
 428         if (!dev_priv->uncore.funcs.force_wake_put)
 429                 return;
 430
 431         fw_domains &= dev_priv->uncore.fw_domains;
 432
 433         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 434
 435         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 436                 if (WARN_ON(domain->wake_count == 0))
 437                         continue;
 438
 439                 if (--domain->wake_count)
 440                         continue;
 441
 442                 domain->wake_count++;
 443                 fw_domain_arm_timer(domain);
 444         }
 445
 446         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 447 }
 448
 449 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 450 {
 451         struct intel_uncore_forcewake_domain *domain;
 452         enum forcewake_domain_id id;
 453
 454         if (!dev_priv->uncore.funcs.force_wake_get)
 455                 return;
 456
 457         for_each_fw_domain(domain, dev_priv, id)
 458                 WARN_ON(domain->wake_count);
 459 }
 460
 461 /* We give fast paths for the really cool registers */
 462 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 463          ((reg) < 0x40000 && (reg) != FORCEWAKE)
 464
 465 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 466
 467 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 468         (REG_RANGE((reg), 0x2000, 0x4000) || \
 469          REG_RANGE((reg), 0x5000, 0x8000) || \
 470          REG_RANGE((reg), 0xB000, 0x12000) || \
 471          REG_RANGE((reg), 0x2E000, 0x30000))
 472
 473 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 474         (REG_RANGE((reg), 0x12000, 0x14000) || \
 475          REG_RANGE((reg), 0x22000, 0x24000) || \
 476          REG_RANGE((reg), 0x30000, 0x40000))
 477
 478 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 479         (REG_RANGE((reg), 0x2000, 0x4000) || \
 480          REG_RANGE((reg), 0x5200, 0x8000) || \
 481          REG_RANGE((reg), 0x8300, 0x8500) || \
 482          REG_RANGE((reg), 0xB000, 0xB480) || \
 483          REG_RANGE((reg), 0xE000, 0xE800))
 484
 485 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 486         (REG_RANGE((reg), 0x8800, 0x8900) || \
 487          REG_RANGE((reg), 0xD000, 0xD800) || \
 488          REG_RANGE((reg), 0x12000, 0x14000) || \
 489          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 490          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 491          REG_RANGE((reg), 0x30000, 0x38000))
 492
 493 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 494         (REG_RANGE((reg), 0x4000, 0x5000) || \
 495          REG_RANGE((reg), 0x8000, 0x8300) || \
 496          REG_RANGE((reg), 0x8500, 0x8600) || \
 497          REG_RANGE((reg), 0x9000, 0xB000) || \
 498          REG_RANGE((reg), 0xF000, 0x10000))
 499
 500 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 501         REG_RANGE((reg), 0xB00,  0x2000)
 502
 503 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 504         (REG_RANGE((reg), 0x2000, 0x2700) || \
 505          REG_RANGE((reg), 0x3000, 0x4000) || \
 506          REG_RANGE((reg), 0x5200, 0x8000) || \
 507          REG_RANGE((reg), 0x8140, 0x8160) || \
 508          REG_RANGE((reg), 0x8300, 0x8500) || \
 509          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 510          REG_RANGE((reg), 0xB000, 0xB480) || \
 511          REG_RANGE((reg), 0xE000, 0xE900) || \
 512          REG_RANGE((reg), 0x24400, 0x24800))
 513
 514 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 515         (REG_RANGE((reg), 0x8130, 0x8140) || \
 516          REG_RANGE((reg), 0x8800, 0x8A00) || \
 517          REG_RANGE((reg), 0xD000, 0xD800) || \
 518          REG_RANGE((reg), 0x12000, 0x14000) || \
 519          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 520          REG_RANGE((reg), 0x30000, 0x40000))
 521
 522 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 523         REG_RANGE((reg), 0x9400, 0x9800)
 524
 525 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 526         ((reg) < 0x40000 &&\
 527          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 528          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 529          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 530          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 531
 532 static void
 533 ilk_dummy_write(struct drm_i915_private *dev_priv)
 534 {
 535         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 536          * the chip from rc6 before touching it for real. MI_MODE is masked,
 537          * hence harmless to write 0 into. */
 538         __raw_i915_write32(dev_priv, MI_MODE, 0);
 539 }
 540
 541 static void
 542 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
 543                         bool before)
 544 {
 545         const char *op = read ? "reading" : "writing to";
 546         const char *when = before ? "before" : "after";
 547
 548         if (!i915.mmio_debug)
 549                 return;
 550
 551         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 552                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 553                      when, op, reg);
 554                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 555         }
 556 }
 557
 558 static void
 559 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 560 {
 561         if (i915.mmio_debug)
 562                 return;
 563
 564         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 565                 DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
 566                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 567         }
 568 }
 569
 570 #define GEN2_READ_HEADER(x) \
 571         u##x val = 0; \
 572         assert_device_not_suspended(dev_priv);
 573
 574 #define GEN2_READ_FOOTER \
 575         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 576         return val
 577
 578 #define __gen2_read(x) \
 579 static u##x \
 580 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 581         GEN2_READ_HEADER(x); \
 582         val = __raw_i915_read##x(dev_priv, reg); \
 583         GEN2_READ_FOOTER; \
 584 }
 585
 586 #define __gen5_read(x) \
 587 static u##x \
 588 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 589         GEN2_READ_HEADER(x); \
 590         ilk_dummy_write(dev_priv); \
 591         val = __raw_i915_read##x(dev_priv, reg); \
 592         GEN2_READ_FOOTER; \
 593 }
 594
 595 __gen5_read(8)
 596 __gen5_read(16)
 597 __gen5_read(32)
 598 __gen5_read(64)
 599 __gen2_read(8)
 600 __gen2_read(16)
 601 __gen2_read(32)
 602 __gen2_read(64)
 603
 604 #undef __gen5_read
 605 #undef __gen2_read
 606
 607 #undef GEN2_READ_FOOTER
 608 #undef GEN2_READ_HEADER
 609
 610 #define GEN6_READ_HEADER(x) \
 611         unsigned long irqflags; \
 612         u##x val = 0; \
 613         assert_device_not_suspended(dev_priv); \
 614         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 615
 616 #define GEN6_READ_FOOTER \
 617         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 618         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 619         return val
 620
 621 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 622                                     enum forcewake_domains fw_domains)
 623 {
 624         struct intel_uncore_forcewake_domain *domain;
 625         enum forcewake_domain_id id;
 626
 627         if (WARN_ON(!fw_domains))
 628                 return;
 629
 630         /* Ideally GCC would be constant-fold and eliminate this loop */
 631         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 632                 if (domain->wake_count) {
 633                         fw_domains &= ~(1 << id);
 634                         continue;
 635                 }
 636
 637                 domain->wake_count++;
 638                 fw_domain_arm_timer(domain);
 639         }
 640
 641         if (fw_domains)
 642                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 643 }
 644
 645 #define __vgpu_read(x) \
 646 static u##x \
 647 vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 648         GEN6_READ_HEADER(x); \
 649         val = __raw_i915_read##x(dev_priv, reg); \
 650         GEN6_READ_FOOTER; \
 651 }
 652
 653 #define __gen6_read(x) \
 654 static u##x \
 655 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 656         GEN6_READ_HEADER(x); \
 657         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 658         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
 659                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 660         val = __raw_i915_read##x(dev_priv, reg); \
 661         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 662         GEN6_READ_FOOTER; \
 663 }
 664
 665 #define __vlv_read(x) \
 666 static u##x \
 667 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 668         GEN6_READ_HEADER(x); \
 669         if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
 670                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 671         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
 672                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 673         val = __raw_i915_read##x(dev_priv, reg); \
 674         GEN6_READ_FOOTER; \
 675 }
 676
 677 #define __chv_read(x) \
 678 static u##x \
 679 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 680         GEN6_READ_HEADER(x); \
 681         if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 682                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 683         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 684                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 685         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 686                 __force_wake_get(dev_priv, \
 687                                  FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 688         val = __raw_i915_read##x(dev_priv, reg); \
 689         GEN6_READ_FOOTER; \
 690 }
 691
 692 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)     \
 693          ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 694
 695 #define __gen9_read(x) \
 696 static u##x \
 697 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 698         enum forcewake_domains fw_engine; \
 699         GEN6_READ_HEADER(x); \
 700         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)))   \
 701                 fw_engine = 0; \
 702         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg))       \
 703                 fw_engine = FORCEWAKE_RENDER; \
 704         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 705                 fw_engine = FORCEWAKE_MEDIA; \
 706         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 707                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 708         else \
 709                 fw_engine = FORCEWAKE_BLITTER; \
 710         if (fw_engine) \
 711                 __force_wake_get(dev_priv, fw_engine); \
 712         val = __raw_i915_read##x(dev_priv, reg); \
 713         GEN6_READ_FOOTER; \
 714 }
 715
 716 __vgpu_read(8)
 717 __vgpu_read(16)
 718 __vgpu_read(32)
 719 __vgpu_read(64)
 720 __gen9_read(8)
 721 __gen9_read(16)
 722 __gen9_read(32)
 723 __gen9_read(64)
 724 __chv_read(8)
 725 __chv_read(16)
 726 __chv_read(32)
 727 __chv_read(64)
 728 __vlv_read(8)
 729 __vlv_read(16)
 730 __vlv_read(32)
 731 __vlv_read(64)
 732 __gen6_read(8)
 733 __gen6_read(16)
 734 __gen6_read(32)
 735 __gen6_read(64)
 736
 737 #undef __gen9_read
 738 #undef __chv_read
 739 #undef __vlv_read
 740 #undef __gen6_read
 741 #undef __vgpu_read
 742 #undef GEN6_READ_FOOTER
 743 #undef GEN6_READ_HEADER
 744
 745 #define GEN2_WRITE_HEADER \
 746         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 747         assert_device_not_suspended(dev_priv); \
 748
 749 #define GEN2_WRITE_FOOTER
 750
 751 #define __gen2_write(x) \
 752 static void \
 753 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 754         GEN2_WRITE_HEADER; \
 755         __raw_i915_write##x(dev_priv, reg, val); \
 756         GEN2_WRITE_FOOTER; \
 757 }
 758
 759 #define __gen5_write(x) \
 760 static void \
 761 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 762         GEN2_WRITE_HEADER; \
 763         ilk_dummy_write(dev_priv); \
 764         __raw_i915_write##x(dev_priv, reg, val); \
 765         GEN2_WRITE_FOOTER; \
 766 }
 767
 768 __gen5_write(8)
 769 __gen5_write(16)
 770 __gen5_write(32)
 771 __gen5_write(64)
 772 __gen2_write(8)
 773 __gen2_write(16)
 774 __gen2_write(32)
 775 __gen2_write(64)
 776
 777 #undef __gen5_write
 778 #undef __gen2_write
 779
 780 #undef GEN2_WRITE_FOOTER
 781 #undef GEN2_WRITE_HEADER
 782
 783 #define GEN6_WRITE_HEADER \
 784         unsigned long irqflags; \
 785         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 786         assert_device_not_suspended(dev_priv); \
 787         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 788
 789 #define GEN6_WRITE_FOOTER \
 790         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 791
 792 #define __gen6_write(x) \
 793 static void \
 794 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 795         u32 __fifo_ret = 0; \
 796         GEN6_WRITE_HEADER; \
 797         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 798                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 799         } \
 800         __raw_i915_write##x(dev_priv, reg, val); \
 801         if (unlikely(__fifo_ret)) { \
 802                 gen6_gt_check_fifodbg(dev_priv); \
 803         } \
 804         GEN6_WRITE_FOOTER; \
 805 }
 806
 807 #define __hsw_write(x) \
 808 static void \
 809 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 810         u32 __fifo_ret = 0; \
 811         GEN6_WRITE_HEADER; \
 812         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 813                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 814         } \
 815         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 816         __raw_i915_write##x(dev_priv, reg, val); \
 817         if (unlikely(__fifo_ret)) { \
 818                 gen6_gt_check_fifodbg(dev_priv); \
 819         } \
 820         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 821         hsw_unclaimed_reg_detect(dev_priv); \
 822         GEN6_WRITE_FOOTER; \
 823 }
 824
 825 #define __vgpu_write(x) \
 826 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
 827                           off_t reg, u##x val, bool trace) { \
 828         GEN6_WRITE_HEADER; \
 829         __raw_i915_write##x(dev_priv, reg, val); \
 830         GEN6_WRITE_FOOTER; \
 831 }
 832
 833 static const u32 gen8_shadowed_regs[] = {
 834         FORCEWAKE_MT,
 835         GEN6_RPNSWREQ,
 836         GEN6_RC_VIDEO_FREQ,
 837         RING_TAIL(RENDER_RING_BASE),
 838         RING_TAIL(GEN6_BSD_RING_BASE),
 839         RING_TAIL(VEBOX_RING_BASE),
 840         RING_TAIL(BLT_RING_BASE),
 841         /* TODO: Other registers are not yet used */
 842 };
 843
 844 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 845 {
 846         int i;
 847         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 848                 if (reg == gen8_shadowed_regs[i])
 849                         return true;
 850
 851         return false;
 852 }
 853
 854 #define __gen8_write(x) \
 855 static void \
 856 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 857         GEN6_WRITE_HEADER; \
 858         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 859         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
 860                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 861         __raw_i915_write##x(dev_priv, reg, val); \
 862         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 863         hsw_unclaimed_reg_detect(dev_priv); \
 864         GEN6_WRITE_FOOTER; \
 865 }
 866
 867 #define __chv_write(x) \
 868 static void \
 869 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 870         bool shadowed = is_gen8_shadowed(dev_priv, reg); \
 871         GEN6_WRITE_HEADER; \
 872         if (!shadowed) { \
 873                 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 874                         __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 875                 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 876                         __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 877                 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 878                         __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 879         } \
 880         __raw_i915_write##x(dev_priv, reg, val); \
 881         GEN6_WRITE_FOOTER; \
 882 }
 883
 884 static const u32 gen9_shadowed_regs[] = {
 885         RING_TAIL(RENDER_RING_BASE),
 886         RING_TAIL(GEN6_BSD_RING_BASE),
 887         RING_TAIL(VEBOX_RING_BASE),
 888         RING_TAIL(BLT_RING_BASE),
 889         FORCEWAKE_BLITTER_GEN9,
 890         FORCEWAKE_RENDER_GEN9,
 891         FORCEWAKE_MEDIA_GEN9,
 892         GEN6_RPNSWREQ,
 893         GEN6_RC_VIDEO_FREQ,
 894         /* TODO: Other registers are not yet used */
 895 };
 896
 897 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 898 {
 899         int i;
 900         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 901                 if (reg == gen9_shadowed_regs[i])
 902                         return true;
 903
 904         return false;
 905 }
 906
 907 #define __gen9_write(x) \
 908 static void \
 909 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
 910                 bool trace) { \
 911         enum forcewake_domains fw_engine; \
 912         GEN6_WRITE_HEADER; \
 913         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
 914             is_gen9_shadowed(dev_priv, reg)) \
 915                 fw_engine = 0; \
 916         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
 917                 fw_engine = FORCEWAKE_RENDER; \
 918         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 919                 fw_engine = FORCEWAKE_MEDIA; \
 920         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 921                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 922         else \
 923                 fw_engine = FORCEWAKE_BLITTER; \
 924         if (fw_engine) \
 925                 __force_wake_get(dev_priv, fw_engine); \
 926         __raw_i915_write##x(dev_priv, reg, val); \
 927         GEN6_WRITE_FOOTER; \
 928 }
 929
 930 __gen9_write(8)
 931 __gen9_write(16)
 932 __gen9_write(32)
 933 __gen9_write(64)
 934 __chv_write(8)
 935 __chv_write(16)
 936 __chv_write(32)
 937 __chv_write(64)
 938 __gen8_write(8)
 939 __gen8_write(16)
 940 __gen8_write(32)
 941 __gen8_write(64)
 942 __hsw_write(8)
 943 __hsw_write(16)
 944 __hsw_write(32)
 945 __hsw_write(64)
 946 __gen6_write(8)
 947 __gen6_write(16)
 948 __gen6_write(32)
 949 __gen6_write(64)
 950 __vgpu_write(8)
 951 __vgpu_write(16)
 952 __vgpu_write(32)
 953 __vgpu_write(64)
 954
 955 #undef __gen9_write
 956 #undef __chv_write
 957 #undef __gen8_write
 958 #undef __hsw_write
 959 #undef __gen6_write
 960 #undef __vgpu_write
 961 #undef GEN6_WRITE_FOOTER
 962 #undef GEN6_WRITE_HEADER
 963
 964 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
 965 do { \
 966         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
 967         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
 968         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
 969         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
 970 } while (0)
 971
 972 #define ASSIGN_READ_MMIO_VFUNCS(x) \
 973 do { \
 974         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
 975         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
 976         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
 977         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
 978 } while (0)
 979
 980
 981 static void fw_domain_init(struct drm_i915_private *dev_priv,
 982                            enum forcewake_domain_id domain_id,
 983                            u32 reg_set, u32 reg_ack)
 984 {
 985         struct intel_uncore_forcewake_domain *d;
 986
 987         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
 988                 return;
 989
 990         d = &dev_priv->uncore.fw_domain[domain_id];
 991
 992         WARN_ON(d->wake_count);
 993
 994         d->wake_count = 0;
 995         d->reg_set = reg_set;
 996         d->reg_ack = reg_ack;
 997
 998         if (IS_GEN6(dev_priv)) {
 999                 d->val_reset = 0;
1000                 d->val_set = FORCEWAKE_KERNEL;
1001                 d->val_clear = 0;
1002         } else {
1003                 /* WaRsClearFWBitsAtReset:bdw,skl */
1004                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1005                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1006                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1007         }
1008
1009         if (IS_VALLEYVIEW(dev_priv))
1010                 d->reg_post = FORCEWAKE_ACK_VLV;
1011         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1012                 d->reg_post = ECOBUS;
1013         else
1014                 d->reg_post = 0;
1015
1016         d->i915 = dev_priv;
1017         d->id = domain_id;
1018
1019         setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
1020
1021         dev_priv->uncore.fw_domains |= (1 << domain_id);
1022
1023         fw_domain_reset(d);
1024 }
1025
1026 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1027 {
1028         struct drm_i915_private *dev_priv = dev->dev_private;
1029
1030         if (INTEL_INFO(dev_priv->dev)->gen <= 5)
1031                 return;
1032
1033         if (IS_GEN9(dev)) {
1034                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1035                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1036                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1037                                FORCEWAKE_RENDER_GEN9,
1038                                FORCEWAKE_ACK_RENDER_GEN9);
1039                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1040                                FORCEWAKE_BLITTER_GEN9,
1041                                FORCEWAKE_ACK_BLITTER_GEN9);
1042                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1043                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1044         } else if (IS_VALLEYVIEW(dev)) {
1045                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1046                 if (!IS_CHERRYVIEW(dev))
1047                         dev_priv->uncore.funcs.force_wake_put =
1048                                 fw_domains_put_with_fifo;
1049                 else
1050                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1051                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1052                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1053                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1054                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1055         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1056                 dev_priv->uncore.funcs.force_wake_get =
1057                         fw_domains_get_with_thread_status;
1058                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1059                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1060                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1061         } else if (IS_IVYBRIDGE(dev)) {
1062                 u32 ecobus;
1063
1064                 /* IVB configs may use multi-threaded forcewake */
1065
1066                 /* A small trick here - if the bios hasn't configured
1067                  * MT forcewake, and if the device is in RC6, then
1068                  * force_wake_mt_get will not wake the device and the
1069                  * ECOBUS read will return zero. Which will be
1070                  * (correctly) interpreted by the test below as MT
1071                  * forcewake being disabled.
1072                  */
1073                 dev_priv->uncore.funcs.force_wake_get =
1074                         fw_domains_get_with_thread_status;
1075                 dev_priv->uncore.funcs.force_wake_put =
1076                         fw_domains_put_with_fifo;
1077
1078                 /* We need to init first for ECOBUS access and then
1079                  * determine later if we want to reinit, in case of MT access is
1080                  * not working
1081                  */
1082                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1083                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1084
1085                 mutex_lock(&dev->struct_mutex);
1086                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1087                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1088                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1089                 mutex_unlock(&dev->struct_mutex);
1090
1091                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1092                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1093                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1094                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1095                                        FORCEWAKE, FORCEWAKE_ACK);
1096                 }
1097         } else if (IS_GEN6(dev)) {
1098                 dev_priv->uncore.funcs.force_wake_get =
1099                         fw_domains_get_with_thread_status;
1100                 dev_priv->uncore.funcs.force_wake_put =
1101                         fw_domains_put_with_fifo;
1102                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1103                                FORCEWAKE, FORCEWAKE_ACK);
1104         }
1105
1106         /* All future platforms are expected to require complex power gating */
1107         WARN_ON(dev_priv->uncore.fw_domains == 0);
1108 }
1109
1110 void intel_uncore_init(struct drm_device *dev)
1111 {
1112         struct drm_i915_private *dev_priv = dev->dev_private;
1113
1114         i915_check_vgpu(dev);
1115
1116         intel_uncore_ellc_detect(dev);
1117         intel_uncore_fw_domains_init(dev);
1118         __intel_uncore_early_sanitize(dev, false);
1119
1120         switch (INTEL_INFO(dev)->gen) {
1121         default:
1122                 MISSING_CASE(INTEL_INFO(dev)->gen);
1123                 return;
1124         case 9:
1125                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1126                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1127                 break;
1128         case 8:
1129                 if (IS_CHERRYVIEW(dev)) {
1130                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1131                         ASSIGN_READ_MMIO_VFUNCS(chv);
1132
1133                 } else {
1134                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1135                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1136                 }
1137                 break;
1138         case 7:
1139         case 6:
1140                 if (IS_HASWELL(dev)) {
1141                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1142                 } else {
1143                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1144                 }
1145
1146                 if (IS_VALLEYVIEW(dev)) {
1147                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1148                 } else {
1149                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1150                 }
1151                 break;
1152         case 5:
1153                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1154                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1155                 break;
1156         case 4:
1157         case 3:
1158         case 2:
1159                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1160                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1161                 break;
1162         }
1163
1164         if (intel_vgpu_active(dev)) {
1165                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1166                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1167         }
1168
1169         i915_check_and_clear_faults(dev);
1170 }
1171 #undef ASSIGN_WRITE_MMIO_VFUNCS
1172 #undef ASSIGN_READ_MMIO_VFUNCS
1173
1174 void intel_uncore_fini(struct drm_device *dev)
1175 {
1176         /* Paranoia: make sure we have disabled everything before we exit. */
1177         intel_uncore_sanitize(dev);
1178         intel_uncore_forcewake_reset(dev, false);
1179 }
1180
1181 #define GEN_RANGE(l, h) GENMASK(h, l)
1182
1183 static const struct register_whitelist {
1184         uint64_t offset;
1185         uint32_t size;
1186         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1187         uint32_t gen_bitmask;
1188 } whitelist[] = {
1189         { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1190 };
1191
1192 int i915_reg_read_ioctl(struct drm_device *dev,
1193                         void *data, struct drm_file *file)
1194 {
1195         struct drm_i915_private *dev_priv = dev->dev_private;
1196         struct drm_i915_reg_read *reg = data;
1197         struct register_whitelist const *entry = whitelist;
1198         int i, ret = 0;
1199
1200         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1201                 if (entry->offset == reg->offset &&
1202                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1203                         break;
1204         }
1205
1206         if (i == ARRAY_SIZE(whitelist))
1207                 return -EINVAL;
1208
1209         intel_runtime_pm_get(dev_priv);
1210
1211         switch (entry->size) {
1212         case 8:
1213                 reg->val = I915_READ64(reg->offset);
1214                 break;
1215         case 4:
1216                 reg->val = I915_READ(reg->offset);
1217                 break;
1218         case 2:
1219                 reg->val = I915_READ16(reg->offset);
1220                 break;
1221         case 1:
1222                 reg->val = I915_READ8(reg->offset);
1223                 break;
1224         default:
1225                 MISSING_CASE(entry->size);
1226                 ret = -EINVAL;
1227                 goto out;
1228         }
1229
1230 out:
1231         intel_runtime_pm_put(dev_priv);
1232         return ret;
1233 }
1234
1235 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1236                                void *data, struct drm_file *file)
1237 {
1238         struct drm_i915_private *dev_priv = dev->dev_private;
1239         struct drm_i915_reset_stats *args = data;
1240         struct i915_ctx_hang_stats *hs;
1241         struct intel_context *ctx;
1242         int ret;
1243
1244         if (args->flags || args->pad)
1245                 return -EINVAL;
1246
1247         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1248                 return -EPERM;
1249
1250         ret = mutex_lock_interruptible(&dev->struct_mutex);
1251         if (ret)
1252                 return ret;
1253
1254         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1255         if (IS_ERR(ctx)) {
1256                 mutex_unlock(&dev->struct_mutex);
1257                 return PTR_ERR(ctx);
1258         }
1259         hs = &ctx->hang_stats;
1260
1261         if (capable(CAP_SYS_ADMIN))
1262                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1263         else
1264                 args->reset_count = 0;
1265
1266         args->batch_active = hs->batch_active;
1267         args->batch_pending = hs->batch_pending;
1268
1269         mutex_unlock(&dev->struct_mutex);
1270
1271         return 0;
1272 }
1273
1274 static int i915_reset_complete(struct drm_device *dev)
1275 {
1276         u8 gdrst;
1277         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1278         return (gdrst & GRDOM_RESET_STATUS) == 0;
1279 }
1280
1281 static int i915_do_reset(struct drm_device *dev)
1282 {
1283         /* assert reset for at least 20 usec */
1284         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1285         udelay(20);
1286         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1287
1288         return wait_for(i915_reset_complete(dev), 500);
1289 }
1290
1291 static int g4x_reset_complete(struct drm_device *dev)
1292 {
1293         u8 gdrst;
1294         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1295         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1296 }
1297
1298 static int g33_do_reset(struct drm_device *dev)
1299 {
1300         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1301         return wait_for(g4x_reset_complete(dev), 500);
1302 }
1303
1304 static int g4x_do_reset(struct drm_device *dev)
1305 {
1306         struct drm_i915_private *dev_priv = dev->dev_private;
1307         int ret;
1308
1309         pci_write_config_byte(dev->pdev, I915_GDRST,
1310                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1311         ret =  wait_for(g4x_reset_complete(dev), 500);
1312         if (ret)
1313                 return ret;
1314
1315         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1316         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1317         POSTING_READ(VDECCLK_GATE_D);
1318
1319         pci_write_config_byte(dev->pdev, I915_GDRST,
1320                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1321         ret =  wait_for(g4x_reset_complete(dev), 500);
1322         if (ret)
1323                 return ret;
1324
1325         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1326         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1327         POSTING_READ(VDECCLK_GATE_D);
1328
1329         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1330
1331         return 0;
1332 }
1333
1334 static int ironlake_do_reset(struct drm_device *dev)
1335 {
1336         struct drm_i915_private *dev_priv = dev->dev_private;
1337         int ret;
1338
1339         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1340                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1341         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1342                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1343         if (ret)
1344                 return ret;
1345
1346         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1347                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1348         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1349                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1350         if (ret)
1351                 return ret;
1352
1353         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1354
1355         return 0;
1356 }
1357
1358 static int gen6_do_reset(struct drm_device *dev)
1359 {
1360         struct drm_i915_private *dev_priv = dev->dev_private;
1361         int     ret;
1362
1363         /* Reset the chip */
1364
1365         /* GEN6_GDRST is not in the gt power well, no need to check
1366          * for fifo space for the write or forcewake the chip for
1367          * the read
1368          */
1369         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1370
1371         /* Spin waiting for the device to ack the reset request */
1372         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1373
1374         intel_uncore_forcewake_reset(dev, true);
1375
1376         return ret;
1377 }
1378
1379 int intel_gpu_reset(struct drm_device *dev)
1380 {
1381         if (INTEL_INFO(dev)->gen >= 6)
1382                 return gen6_do_reset(dev);
1383         else if (IS_GEN5(dev))
1384                 return ironlake_do_reset(dev);
1385         else if (IS_G4X(dev))
1386                 return g4x_do_reset(dev);
1387         else if (IS_G33(dev))
1388                 return g33_do_reset(dev);
1389         else if (INTEL_INFO(dev)->gen >= 3)
1390                 return i915_do_reset(dev);
1391         else
1392                 return -ENODEV;
1393 }
1394
1395 void intel_uncore_check_errors(struct drm_device *dev)
1396 {
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398
1399         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1400             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1401                 DRM_ERROR("Unclaimed register before interrupt\n");
1402                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1403         }
1404 }